2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
39 #include <asm/perf_event.h>
40 #include <asm/tlbflush.h>
42 #include <asm/debugreg.h>
43 #include <asm/kvm_para.h>
45 #include <asm/virtext.h>
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 MODULE_AUTHOR("Qumranet");
51 MODULE_LICENSE("GPL");
53 static const struct x86_cpu_id svm_cpu_id[] = {
54 X86_FEATURE_MATCH(X86_FEATURE_SVM),
57 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
59 #define IOPM_ALLOC_ORDER 2
60 #define MSRPM_ALLOC_ORDER 1
62 #define SEG_TYPE_LDT 2
63 #define SEG_TYPE_BUSY_TSS16 3
65 #define SVM_FEATURE_NPT (1 << 0)
66 #define SVM_FEATURE_LBRV (1 << 1)
67 #define SVM_FEATURE_SVML (1 << 2)
68 #define SVM_FEATURE_NRIP (1 << 3)
69 #define SVM_FEATURE_TSC_RATE (1 << 4)
70 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
71 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
72 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
73 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
75 #define SVM_AVIC_DOORBELL 0xc001011b
77 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
78 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
79 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
81 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
83 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
84 #define TSC_RATIO_MIN 0x0000000000000001ULL
85 #define TSC_RATIO_MAX 0x000000ffffffffffULL
87 #define AVIC_HPA_MASK ~((0xFFFULL << 52) || 0xFFF)
90 * 0xff is broadcast, so the max index allowed for physical APIC ID
91 * table is 0xfe. APIC IDs above 0xff are reserved.
93 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
95 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
96 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
97 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
99 static bool erratum_383_found __read_mostly;
101 static const u32 host_save_user_msrs[] = {
103 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
106 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
110 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
114 struct nested_state {
120 /* These are the merged vectors */
123 /* gpa pointers to the real vectors */
127 /* A VMEXIT is required but not yet emulated */
130 /* cache for intercepts of the guest */
133 u32 intercept_exceptions;
136 /* Nested Paging related state */
140 #define MSRPM_OFFSETS 16
141 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
144 * Set osvw_len to higher value when updated Revision Guides
145 * are published and we know what the new status bits are
147 static uint64_t osvw_len = 4, osvw_status;
150 struct kvm_vcpu vcpu;
152 unsigned long vmcb_pa;
153 struct svm_cpu_data *svm_data;
154 uint64_t asid_generation;
155 uint64_t sysenter_esp;
156 uint64_t sysenter_eip;
161 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
173 struct nested_state nested;
177 unsigned int3_injected;
178 unsigned long int3_rip;
181 /* cached guest cpuid flags for faster access */
182 bool nrips_enabled : 1;
185 struct page *avic_backing_page;
186 u64 *avic_physical_id_cache;
187 bool avic_is_running;
190 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
191 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
193 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
194 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
195 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
196 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
198 static DEFINE_PER_CPU(u64, current_tsc_ratio);
199 #define TSC_RATIO_DEFAULT 0x0100000000ULL
201 #define MSR_INVALID 0xffffffffU
203 static const struct svm_direct_access_msrs {
204 u32 index; /* Index of the MSR */
205 bool always; /* True if intercept is always on */
206 } direct_access_msrs[] = {
207 { .index = MSR_STAR, .always = true },
208 { .index = MSR_IA32_SYSENTER_CS, .always = true },
210 { .index = MSR_GS_BASE, .always = true },
211 { .index = MSR_FS_BASE, .always = true },
212 { .index = MSR_KERNEL_GS_BASE, .always = true },
213 { .index = MSR_LSTAR, .always = true },
214 { .index = MSR_CSTAR, .always = true },
215 { .index = MSR_SYSCALL_MASK, .always = true },
217 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
218 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
219 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
220 { .index = MSR_IA32_LASTINTTOIP, .always = false },
221 { .index = MSR_INVALID, .always = false },
224 /* enable NPT for AMD64 and X86 with PAE */
225 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
226 static bool npt_enabled = true;
228 static bool npt_enabled;
231 /* allow nested paging (virtualized MMU) for all guests */
232 static int npt = true;
233 module_param(npt, int, S_IRUGO);
235 /* allow nested virtualization in KVM/SVM */
236 static int nested = true;
237 module_param(nested, int, S_IRUGO);
239 /* enable / disable AVIC */
241 module_param(avic, int, S_IRUGO);
243 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
244 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
245 static void svm_complete_interrupts(struct vcpu_svm *svm);
247 static int nested_svm_exit_handled(struct vcpu_svm *svm);
248 static int nested_svm_intercept(struct vcpu_svm *svm);
249 static int nested_svm_vmexit(struct vcpu_svm *svm);
250 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
251 bool has_error_code, u32 error_code);
254 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
255 pause filter count */
256 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
257 VMCB_ASID, /* ASID */
258 VMCB_INTR, /* int_ctl, int_vector */
259 VMCB_NPT, /* npt_en, nCR3, gPAT */
260 VMCB_CR, /* CR0, CR3, CR4, EFER */
261 VMCB_DR, /* DR6, DR7 */
262 VMCB_DT, /* GDT, IDT */
263 VMCB_SEG, /* CS, DS, SS, ES, CPL */
264 VMCB_CR2, /* CR2 only */
265 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
266 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
267 * AVIC PHYSICAL_TABLE pointer,
268 * AVIC LOGICAL_TABLE pointer
273 /* TPR and CR2 are always written before VMRUN */
274 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
276 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
278 static inline void mark_all_dirty(struct vmcb *vmcb)
280 vmcb->control.clean = 0;
283 static inline void mark_all_clean(struct vmcb *vmcb)
285 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
286 & ~VMCB_ALWAYS_DIRTY_MASK;
289 static inline void mark_dirty(struct vmcb *vmcb, int bit)
291 vmcb->control.clean &= ~(1 << bit);
294 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
296 return container_of(vcpu, struct vcpu_svm, vcpu);
299 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
301 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
302 mark_dirty(svm->vmcb, VMCB_AVIC);
305 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
307 struct vcpu_svm *svm = to_svm(vcpu);
308 u64 *entry = svm->avic_physical_id_cache;
313 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
316 static void recalc_intercepts(struct vcpu_svm *svm)
318 struct vmcb_control_area *c, *h;
319 struct nested_state *g;
321 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
323 if (!is_guest_mode(&svm->vcpu))
326 c = &svm->vmcb->control;
327 h = &svm->nested.hsave->control;
330 c->intercept_cr = h->intercept_cr | g->intercept_cr;
331 c->intercept_dr = h->intercept_dr | g->intercept_dr;
332 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
333 c->intercept = h->intercept | g->intercept;
336 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
338 if (is_guest_mode(&svm->vcpu))
339 return svm->nested.hsave;
344 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
346 struct vmcb *vmcb = get_host_vmcb(svm);
348 vmcb->control.intercept_cr |= (1U << bit);
350 recalc_intercepts(svm);
353 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
355 struct vmcb *vmcb = get_host_vmcb(svm);
357 vmcb->control.intercept_cr &= ~(1U << bit);
359 recalc_intercepts(svm);
362 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
364 struct vmcb *vmcb = get_host_vmcb(svm);
366 return vmcb->control.intercept_cr & (1U << bit);
369 static inline void set_dr_intercepts(struct vcpu_svm *svm)
371 struct vmcb *vmcb = get_host_vmcb(svm);
373 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
374 | (1 << INTERCEPT_DR1_READ)
375 | (1 << INTERCEPT_DR2_READ)
376 | (1 << INTERCEPT_DR3_READ)
377 | (1 << INTERCEPT_DR4_READ)
378 | (1 << INTERCEPT_DR5_READ)
379 | (1 << INTERCEPT_DR6_READ)
380 | (1 << INTERCEPT_DR7_READ)
381 | (1 << INTERCEPT_DR0_WRITE)
382 | (1 << INTERCEPT_DR1_WRITE)
383 | (1 << INTERCEPT_DR2_WRITE)
384 | (1 << INTERCEPT_DR3_WRITE)
385 | (1 << INTERCEPT_DR4_WRITE)
386 | (1 << INTERCEPT_DR5_WRITE)
387 | (1 << INTERCEPT_DR6_WRITE)
388 | (1 << INTERCEPT_DR7_WRITE);
390 recalc_intercepts(svm);
393 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
395 struct vmcb *vmcb = get_host_vmcb(svm);
397 vmcb->control.intercept_dr = 0;
399 recalc_intercepts(svm);
402 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
404 struct vmcb *vmcb = get_host_vmcb(svm);
406 vmcb->control.intercept_exceptions |= (1U << bit);
408 recalc_intercepts(svm);
411 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
413 struct vmcb *vmcb = get_host_vmcb(svm);
415 vmcb->control.intercept_exceptions &= ~(1U << bit);
417 recalc_intercepts(svm);
420 static inline void set_intercept(struct vcpu_svm *svm, int bit)
422 struct vmcb *vmcb = get_host_vmcb(svm);
424 vmcb->control.intercept |= (1ULL << bit);
426 recalc_intercepts(svm);
429 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
431 struct vmcb *vmcb = get_host_vmcb(svm);
433 vmcb->control.intercept &= ~(1ULL << bit);
435 recalc_intercepts(svm);
438 static inline void enable_gif(struct vcpu_svm *svm)
440 svm->vcpu.arch.hflags |= HF_GIF_MASK;
443 static inline void disable_gif(struct vcpu_svm *svm)
445 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
448 static inline bool gif_set(struct vcpu_svm *svm)
450 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
453 static unsigned long iopm_base;
455 struct kvm_ldttss_desc {
458 unsigned base1:8, type:5, dpl:2, p:1;
459 unsigned limit1:4, zero0:3, g:1, base2:8;
462 } __attribute__((packed));
464 struct svm_cpu_data {
470 struct kvm_ldttss_desc *tss_desc;
472 struct page *save_area;
475 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
477 struct svm_init_data {
482 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
484 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
485 #define MSRS_RANGE_SIZE 2048
486 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
488 static u32 svm_msrpm_offset(u32 msr)
493 for (i = 0; i < NUM_MSR_MAPS; i++) {
494 if (msr < msrpm_ranges[i] ||
495 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
498 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
499 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
501 /* Now we have the u8 offset - but need the u32 offset */
505 /* MSR not in any range */
509 #define MAX_INST_SIZE 15
511 static inline void clgi(void)
513 asm volatile (__ex(SVM_CLGI));
516 static inline void stgi(void)
518 asm volatile (__ex(SVM_STGI));
521 static inline void invlpga(unsigned long addr, u32 asid)
523 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
526 static int get_npt_level(void)
529 return PT64_ROOT_LEVEL;
531 return PT32E_ROOT_LEVEL;
535 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
537 vcpu->arch.efer = efer;
538 if (!npt_enabled && !(efer & EFER_LMA))
541 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
542 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
545 static int is_external_interrupt(u32 info)
547 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
548 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
551 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
553 struct vcpu_svm *svm = to_svm(vcpu);
556 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
557 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
561 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
563 struct vcpu_svm *svm = to_svm(vcpu);
566 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
568 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
572 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
574 struct vcpu_svm *svm = to_svm(vcpu);
576 if (svm->vmcb->control.next_rip != 0) {
577 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
578 svm->next_rip = svm->vmcb->control.next_rip;
581 if (!svm->next_rip) {
582 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
584 printk(KERN_DEBUG "%s: NOP\n", __func__);
587 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
588 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
589 __func__, kvm_rip_read(vcpu), svm->next_rip);
591 kvm_rip_write(vcpu, svm->next_rip);
592 svm_set_interrupt_shadow(vcpu, 0);
595 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
596 bool has_error_code, u32 error_code,
599 struct vcpu_svm *svm = to_svm(vcpu);
602 * If we are within a nested VM we'd better #VMEXIT and let the guest
603 * handle the exception
606 nested_svm_check_exception(svm, nr, has_error_code, error_code))
609 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
610 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
613 * For guest debugging where we have to reinject #BP if some
614 * INT3 is guest-owned:
615 * Emulate nRIP by moving RIP forward. Will fail if injection
616 * raises a fault that is not intercepted. Still better than
617 * failing in all cases.
619 skip_emulated_instruction(&svm->vcpu);
620 rip = kvm_rip_read(&svm->vcpu);
621 svm->int3_rip = rip + svm->vmcb->save.cs.base;
622 svm->int3_injected = rip - old_rip;
625 svm->vmcb->control.event_inj = nr
627 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
628 | SVM_EVTINJ_TYPE_EXEPT;
629 svm->vmcb->control.event_inj_err = error_code;
632 static void svm_init_erratum_383(void)
638 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
641 /* Use _safe variants to not break nested virtualization */
642 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
648 low = lower_32_bits(val);
649 high = upper_32_bits(val);
651 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
653 erratum_383_found = true;
656 static void svm_init_osvw(struct kvm_vcpu *vcpu)
659 * Guests should see errata 400 and 415 as fixed (assuming that
660 * HLT and IO instructions are intercepted).
662 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
663 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
666 * By increasing VCPU's osvw.length to 3 we are telling the guest that
667 * all osvw.status bits inside that length, including bit 0 (which is
668 * reserved for erratum 298), are valid. However, if host processor's
669 * osvw_len is 0 then osvw_status[0] carries no information. We need to
670 * be conservative here and therefore we tell the guest that erratum 298
671 * is present (because we really don't know).
673 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
674 vcpu->arch.osvw.status |= 1;
677 static int has_svm(void)
681 if (!cpu_has_svm(&msg)) {
682 printk(KERN_INFO "has_svm: %s\n", msg);
689 static void svm_hardware_disable(void)
691 /* Make sure we clean up behind us */
692 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
693 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
697 amd_pmu_disable_virt();
700 static int svm_hardware_enable(void)
703 struct svm_cpu_data *sd;
705 struct desc_ptr gdt_descr;
706 struct desc_struct *gdt;
707 int me = raw_smp_processor_id();
709 rdmsrl(MSR_EFER, efer);
710 if (efer & EFER_SVME)
714 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
717 sd = per_cpu(svm_data, me);
719 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
723 sd->asid_generation = 1;
724 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
725 sd->next_asid = sd->max_asid + 1;
727 native_store_gdt(&gdt_descr);
728 gdt = (struct desc_struct *)gdt_descr.address;
729 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
731 wrmsrl(MSR_EFER, efer | EFER_SVME);
733 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
735 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
736 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
737 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
744 * Note that it is possible to have a system with mixed processor
745 * revisions and therefore different OSVW bits. If bits are not the same
746 * on different processors then choose the worst case (i.e. if erratum
747 * is present on one processor and not on another then assume that the
748 * erratum is present everywhere).
750 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
751 uint64_t len, status = 0;
754 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
756 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
760 osvw_status = osvw_len = 0;
764 osvw_status |= status;
765 osvw_status &= (1ULL << osvw_len) - 1;
768 osvw_status = osvw_len = 0;
770 svm_init_erratum_383();
772 amd_pmu_enable_virt();
777 static void svm_cpu_uninit(int cpu)
779 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
784 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
785 __free_page(sd->save_area);
789 static int svm_cpu_init(int cpu)
791 struct svm_cpu_data *sd;
794 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
798 sd->save_area = alloc_page(GFP_KERNEL);
803 per_cpu(svm_data, cpu) = sd;
813 static bool valid_msr_intercept(u32 index)
817 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
818 if (direct_access_msrs[i].index == index)
824 static void set_msr_interception(u32 *msrpm, unsigned msr,
827 u8 bit_read, bit_write;
832 * If this warning triggers extend the direct_access_msrs list at the
833 * beginning of the file
835 WARN_ON(!valid_msr_intercept(msr));
837 offset = svm_msrpm_offset(msr);
838 bit_read = 2 * (msr & 0x0f);
839 bit_write = 2 * (msr & 0x0f) + 1;
842 BUG_ON(offset == MSR_INVALID);
844 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
845 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
850 static void svm_vcpu_init_msrpm(u32 *msrpm)
854 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
856 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
857 if (!direct_access_msrs[i].always)
860 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
864 static void add_msr_offset(u32 offset)
868 for (i = 0; i < MSRPM_OFFSETS; ++i) {
870 /* Offset already in list? */
871 if (msrpm_offsets[i] == offset)
874 /* Slot used by another offset? */
875 if (msrpm_offsets[i] != MSR_INVALID)
878 /* Add offset to list */
879 msrpm_offsets[i] = offset;
885 * If this BUG triggers the msrpm_offsets table has an overflow. Just
886 * increase MSRPM_OFFSETS in this case.
891 static void init_msrpm_offsets(void)
895 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
897 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
900 offset = svm_msrpm_offset(direct_access_msrs[i].index);
901 BUG_ON(offset == MSR_INVALID);
903 add_msr_offset(offset);
907 static void svm_enable_lbrv(struct vcpu_svm *svm)
909 u32 *msrpm = svm->msrpm;
911 svm->vmcb->control.lbr_ctl = 1;
912 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
913 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
914 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
915 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
918 static void svm_disable_lbrv(struct vcpu_svm *svm)
920 u32 *msrpm = svm->msrpm;
922 svm->vmcb->control.lbr_ctl = 0;
923 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
924 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
925 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
926 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
929 static __init int svm_hardware_setup(void)
932 struct page *iopm_pages;
936 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
941 iopm_va = page_address(iopm_pages);
942 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
943 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
945 init_msrpm_offsets();
947 if (boot_cpu_has(X86_FEATURE_NX))
948 kvm_enable_efer_bits(EFER_NX);
950 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
951 kvm_enable_efer_bits(EFER_FFXSR);
953 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
954 kvm_has_tsc_control = true;
955 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
956 kvm_tsc_scaling_ratio_frac_bits = 32;
960 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
961 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
964 for_each_possible_cpu(cpu) {
965 r = svm_cpu_init(cpu);
970 if (!boot_cpu_has(X86_FEATURE_NPT))
973 if (npt_enabled && !npt) {
974 printk(KERN_INFO "kvm: Nested Paging disabled\n");
979 printk(KERN_INFO "kvm: Nested Paging enabled\n");
984 if (avic && (!npt_enabled || !boot_cpu_has(X86_FEATURE_AVIC)))
988 pr_info("AVIC enabled\n");
993 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
998 static __exit void svm_hardware_unsetup(void)
1002 for_each_possible_cpu(cpu)
1003 svm_cpu_uninit(cpu);
1005 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1009 static void init_seg(struct vmcb_seg *seg)
1012 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1013 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1014 seg->limit = 0xffff;
1018 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1021 seg->attrib = SVM_SELECTOR_P_MASK | type;
1022 seg->limit = 0xffff;
1026 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1028 struct vcpu_svm *svm = to_svm(vcpu);
1030 return svm->vmcb->control.tsc_offset;
1033 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1035 struct vcpu_svm *svm = to_svm(vcpu);
1036 u64 g_tsc_offset = 0;
1038 if (is_guest_mode(vcpu)) {
1039 g_tsc_offset = svm->vmcb->control.tsc_offset -
1040 svm->nested.hsave->control.tsc_offset;
1041 svm->nested.hsave->control.tsc_offset = offset;
1043 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1044 svm->vmcb->control.tsc_offset,
1047 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1049 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1052 static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
1054 struct vcpu_svm *svm = to_svm(vcpu);
1056 svm->vmcb->control.tsc_offset += adjustment;
1057 if (is_guest_mode(vcpu))
1058 svm->nested.hsave->control.tsc_offset += adjustment;
1060 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1061 svm->vmcb->control.tsc_offset - adjustment,
1062 svm->vmcb->control.tsc_offset);
1064 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1067 static void avic_init_vmcb(struct vcpu_svm *svm)
1069 struct vmcb *vmcb = svm->vmcb;
1070 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1071 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1072 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1073 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1075 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1076 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1077 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1078 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1079 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1080 svm->vcpu.arch.apicv_active = true;
1083 static void init_vmcb(struct vcpu_svm *svm)
1085 struct vmcb_control_area *control = &svm->vmcb->control;
1086 struct vmcb_save_area *save = &svm->vmcb->save;
1088 svm->vcpu.fpu_active = 1;
1089 svm->vcpu.arch.hflags = 0;
1091 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1092 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1093 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1094 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1095 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1096 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1097 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1098 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1100 set_dr_intercepts(svm);
1102 set_exception_intercept(svm, PF_VECTOR);
1103 set_exception_intercept(svm, UD_VECTOR);
1104 set_exception_intercept(svm, MC_VECTOR);
1105 set_exception_intercept(svm, AC_VECTOR);
1106 set_exception_intercept(svm, DB_VECTOR);
1108 set_intercept(svm, INTERCEPT_INTR);
1109 set_intercept(svm, INTERCEPT_NMI);
1110 set_intercept(svm, INTERCEPT_SMI);
1111 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1112 set_intercept(svm, INTERCEPT_RDPMC);
1113 set_intercept(svm, INTERCEPT_CPUID);
1114 set_intercept(svm, INTERCEPT_INVD);
1115 set_intercept(svm, INTERCEPT_HLT);
1116 set_intercept(svm, INTERCEPT_INVLPG);
1117 set_intercept(svm, INTERCEPT_INVLPGA);
1118 set_intercept(svm, INTERCEPT_IOIO_PROT);
1119 set_intercept(svm, INTERCEPT_MSR_PROT);
1120 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1121 set_intercept(svm, INTERCEPT_SHUTDOWN);
1122 set_intercept(svm, INTERCEPT_VMRUN);
1123 set_intercept(svm, INTERCEPT_VMMCALL);
1124 set_intercept(svm, INTERCEPT_VMLOAD);
1125 set_intercept(svm, INTERCEPT_VMSAVE);
1126 set_intercept(svm, INTERCEPT_STGI);
1127 set_intercept(svm, INTERCEPT_CLGI);
1128 set_intercept(svm, INTERCEPT_SKINIT);
1129 set_intercept(svm, INTERCEPT_WBINVD);
1130 set_intercept(svm, INTERCEPT_MONITOR);
1131 set_intercept(svm, INTERCEPT_MWAIT);
1132 set_intercept(svm, INTERCEPT_XSETBV);
1134 control->iopm_base_pa = iopm_base;
1135 control->msrpm_base_pa = __pa(svm->msrpm);
1136 control->int_ctl = V_INTR_MASKING_MASK;
1138 init_seg(&save->es);
1139 init_seg(&save->ss);
1140 init_seg(&save->ds);
1141 init_seg(&save->fs);
1142 init_seg(&save->gs);
1144 save->cs.selector = 0xf000;
1145 save->cs.base = 0xffff0000;
1146 /* Executable/Readable Code Segment */
1147 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1148 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1149 save->cs.limit = 0xffff;
1151 save->gdtr.limit = 0xffff;
1152 save->idtr.limit = 0xffff;
1154 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1155 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1157 svm_set_efer(&svm->vcpu, 0);
1158 save->dr6 = 0xffff0ff0;
1159 kvm_set_rflags(&svm->vcpu, 2);
1160 save->rip = 0x0000fff0;
1161 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1164 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1165 * It also updates the guest-visible cr0 value.
1167 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1168 kvm_mmu_reset_context(&svm->vcpu);
1170 save->cr4 = X86_CR4_PAE;
1174 /* Setup VMCB for Nested Paging */
1175 control->nested_ctl = 1;
1176 clr_intercept(svm, INTERCEPT_INVLPG);
1177 clr_exception_intercept(svm, PF_VECTOR);
1178 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1179 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1180 save->g_pat = svm->vcpu.arch.pat;
1184 svm->asid_generation = 0;
1186 svm->nested.vmcb = 0;
1187 svm->vcpu.arch.hflags = 0;
1189 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1190 control->pause_filter_count = 3000;
1191 set_intercept(svm, INTERCEPT_PAUSE);
1195 avic_init_vmcb(svm);
1197 mark_all_dirty(svm->vmcb);
1203 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1205 u64 *avic_physical_id_table;
1206 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1208 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1211 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1213 return &avic_physical_id_table[index];
1218 * AVIC hardware walks the nested page table to check permissions,
1219 * but does not use the SPA address specified in the leaf page
1220 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1221 * field of the VMCB. Therefore, we set up the
1222 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1224 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1226 struct kvm *kvm = vcpu->kvm;
1229 if (kvm->arch.apic_access_page_done)
1232 ret = x86_set_memory_region(kvm,
1233 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1234 APIC_DEFAULT_PHYS_BASE,
1239 kvm->arch.apic_access_page_done = true;
1243 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1246 u64 *entry, new_entry;
1247 int id = vcpu->vcpu_id;
1248 struct vcpu_svm *svm = to_svm(vcpu);
1250 ret = avic_init_access_page(vcpu);
1254 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1257 if (!svm->vcpu.arch.apic->regs)
1260 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1262 /* Setting AVIC backing page address in the phy APIC ID table */
1263 entry = avic_get_physical_id_entry(vcpu, id);
1267 new_entry = READ_ONCE(*entry);
1268 new_entry = (page_to_phys(svm->avic_backing_page) &
1269 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1270 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1271 WRITE_ONCE(*entry, new_entry);
1273 svm->avic_physical_id_cache = entry;
1278 static void avic_vm_destroy(struct kvm *kvm)
1280 struct kvm_arch *vm_data = &kvm->arch;
1282 if (vm_data->avic_logical_id_table_page)
1283 __free_page(vm_data->avic_logical_id_table_page);
1284 if (vm_data->avic_physical_id_table_page)
1285 __free_page(vm_data->avic_physical_id_table_page);
1288 static int avic_vm_init(struct kvm *kvm)
1291 struct kvm_arch *vm_data = &kvm->arch;
1292 struct page *p_page;
1293 struct page *l_page;
1298 /* Allocating physical APIC ID table (4KB) */
1299 p_page = alloc_page(GFP_KERNEL);
1303 vm_data->avic_physical_id_table_page = p_page;
1304 clear_page(page_address(p_page));
1306 /* Allocating logical APIC ID table (4KB) */
1307 l_page = alloc_page(GFP_KERNEL);
1311 vm_data->avic_logical_id_table_page = l_page;
1312 clear_page(page_address(l_page));
1317 avic_vm_destroy(kvm);
1322 * This function is called during VCPU halt/unhalt.
1324 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1327 int h_physical_id = __default_cpu_present_to_apicid(vcpu->cpu);
1328 struct vcpu_svm *svm = to_svm(vcpu);
1330 if (!kvm_vcpu_apicv_active(vcpu))
1333 svm->avic_is_running = is_run;
1335 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1336 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1339 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1340 WARN_ON(is_run == !!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK));
1342 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1344 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1345 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1348 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1351 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1352 int h_physical_id = __default_cpu_present_to_apicid(cpu);
1353 struct vcpu_svm *svm = to_svm(vcpu);
1355 if (!kvm_vcpu_apicv_active(vcpu))
1358 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1361 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1362 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1364 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1365 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1367 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1368 if (svm->avic_is_running)
1369 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1371 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1374 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1377 struct vcpu_svm *svm = to_svm(vcpu);
1379 if (!kvm_vcpu_apicv_active(vcpu))
1382 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1383 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1384 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1387 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1389 struct vcpu_svm *svm = to_svm(vcpu);
1394 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1395 MSR_IA32_APICBASE_ENABLE;
1396 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1397 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1401 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1402 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1404 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1405 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1408 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1410 struct vcpu_svm *svm;
1412 struct page *msrpm_pages;
1413 struct page *hsave_page;
1414 struct page *nested_msrpm_pages;
1417 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1423 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1428 page = alloc_page(GFP_KERNEL);
1432 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1436 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1437 if (!nested_msrpm_pages)
1440 hsave_page = alloc_page(GFP_KERNEL);
1445 err = avic_init_backing_page(&svm->vcpu);
1450 /* We initialize this flag to true to make sure that the is_running
1451 * bit would be set the first time the vcpu is loaded.
1453 svm->avic_is_running = true;
1455 svm->nested.hsave = page_address(hsave_page);
1457 svm->msrpm = page_address(msrpm_pages);
1458 svm_vcpu_init_msrpm(svm->msrpm);
1460 svm->nested.msrpm = page_address(nested_msrpm_pages);
1461 svm_vcpu_init_msrpm(svm->nested.msrpm);
1463 svm->vmcb = page_address(page);
1464 clear_page(svm->vmcb);
1465 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1466 svm->asid_generation = 0;
1469 svm_init_osvw(&svm->vcpu);
1474 __free_page(hsave_page);
1476 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1478 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1482 kvm_vcpu_uninit(&svm->vcpu);
1484 kmem_cache_free(kvm_vcpu_cache, svm);
1486 return ERR_PTR(err);
1489 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1491 struct vcpu_svm *svm = to_svm(vcpu);
1493 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1494 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1495 __free_page(virt_to_page(svm->nested.hsave));
1496 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1497 kvm_vcpu_uninit(vcpu);
1498 kmem_cache_free(kvm_vcpu_cache, svm);
1501 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1503 struct vcpu_svm *svm = to_svm(vcpu);
1506 if (unlikely(cpu != vcpu->cpu)) {
1507 svm->asid_generation = 0;
1508 mark_all_dirty(svm->vmcb);
1511 #ifdef CONFIG_X86_64
1512 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1514 savesegment(fs, svm->host.fs);
1515 savesegment(gs, svm->host.gs);
1516 svm->host.ldt = kvm_read_ldt();
1518 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1519 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1521 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1522 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1523 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1524 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1525 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1528 /* This assumes that the kernel never uses MSR_TSC_AUX */
1529 if (static_cpu_has(X86_FEATURE_RDTSCP))
1530 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1532 avic_vcpu_load(vcpu, cpu);
1535 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1537 struct vcpu_svm *svm = to_svm(vcpu);
1540 avic_vcpu_put(vcpu);
1542 ++vcpu->stat.host_state_reload;
1543 kvm_load_ldt(svm->host.ldt);
1544 #ifdef CONFIG_X86_64
1545 loadsegment(fs, svm->host.fs);
1546 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1547 load_gs_index(svm->host.gs);
1549 #ifdef CONFIG_X86_32_LAZY_GS
1550 loadsegment(gs, svm->host.gs);
1553 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1554 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1557 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1559 avic_set_running(vcpu, false);
1562 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1564 avic_set_running(vcpu, true);
1567 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1569 return to_svm(vcpu)->vmcb->save.rflags;
1572 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1575 * Any change of EFLAGS.VM is accompained by a reload of SS
1576 * (caused by either a task switch or an inter-privilege IRET),
1577 * so we do not need to update the CPL here.
1579 to_svm(vcpu)->vmcb->save.rflags = rflags;
1582 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1587 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1590 case VCPU_EXREG_PDPTR:
1591 BUG_ON(!npt_enabled);
1592 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1599 static void svm_set_vintr(struct vcpu_svm *svm)
1601 set_intercept(svm, INTERCEPT_VINTR);
1604 static void svm_clear_vintr(struct vcpu_svm *svm)
1606 clr_intercept(svm, INTERCEPT_VINTR);
1609 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1611 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1614 case VCPU_SREG_CS: return &save->cs;
1615 case VCPU_SREG_DS: return &save->ds;
1616 case VCPU_SREG_ES: return &save->es;
1617 case VCPU_SREG_FS: return &save->fs;
1618 case VCPU_SREG_GS: return &save->gs;
1619 case VCPU_SREG_SS: return &save->ss;
1620 case VCPU_SREG_TR: return &save->tr;
1621 case VCPU_SREG_LDTR: return &save->ldtr;
1627 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1629 struct vmcb_seg *s = svm_seg(vcpu, seg);
1634 static void svm_get_segment(struct kvm_vcpu *vcpu,
1635 struct kvm_segment *var, int seg)
1637 struct vmcb_seg *s = svm_seg(vcpu, seg);
1639 var->base = s->base;
1640 var->limit = s->limit;
1641 var->selector = s->selector;
1642 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1643 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1644 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1645 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1646 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1647 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1648 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1651 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1652 * However, the SVM spec states that the G bit is not observed by the
1653 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1654 * So let's synthesize a legal G bit for all segments, this helps
1655 * running KVM nested. It also helps cross-vendor migration, because
1656 * Intel's vmentry has a check on the 'G' bit.
1658 var->g = s->limit > 0xfffff;
1661 * AMD's VMCB does not have an explicit unusable field, so emulate it
1662 * for cross vendor migration purposes by "not present"
1664 var->unusable = !var->present || (var->type == 0);
1669 * Work around a bug where the busy flag in the tr selector
1679 * The accessed bit must always be set in the segment
1680 * descriptor cache, although it can be cleared in the
1681 * descriptor, the cached bit always remains at 1. Since
1682 * Intel has a check on this, set it here to support
1683 * cross-vendor migration.
1690 * On AMD CPUs sometimes the DB bit in the segment
1691 * descriptor is left as 1, although the whole segment has
1692 * been made unusable. Clear it here to pass an Intel VMX
1693 * entry check when cross vendor migrating.
1697 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1702 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1704 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1709 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1711 struct vcpu_svm *svm = to_svm(vcpu);
1713 dt->size = svm->vmcb->save.idtr.limit;
1714 dt->address = svm->vmcb->save.idtr.base;
1717 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1719 struct vcpu_svm *svm = to_svm(vcpu);
1721 svm->vmcb->save.idtr.limit = dt->size;
1722 svm->vmcb->save.idtr.base = dt->address ;
1723 mark_dirty(svm->vmcb, VMCB_DT);
1726 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1728 struct vcpu_svm *svm = to_svm(vcpu);
1730 dt->size = svm->vmcb->save.gdtr.limit;
1731 dt->address = svm->vmcb->save.gdtr.base;
1734 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1736 struct vcpu_svm *svm = to_svm(vcpu);
1738 svm->vmcb->save.gdtr.limit = dt->size;
1739 svm->vmcb->save.gdtr.base = dt->address ;
1740 mark_dirty(svm->vmcb, VMCB_DT);
1743 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1747 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1751 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1755 static void update_cr0_intercept(struct vcpu_svm *svm)
1757 ulong gcr0 = svm->vcpu.arch.cr0;
1758 u64 *hcr0 = &svm->vmcb->save.cr0;
1760 if (!svm->vcpu.fpu_active)
1761 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1763 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1764 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1766 mark_dirty(svm->vmcb, VMCB_CR);
1768 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1769 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1770 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1772 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1773 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1777 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1779 struct vcpu_svm *svm = to_svm(vcpu);
1781 #ifdef CONFIG_X86_64
1782 if (vcpu->arch.efer & EFER_LME) {
1783 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1784 vcpu->arch.efer |= EFER_LMA;
1785 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1788 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1789 vcpu->arch.efer &= ~EFER_LMA;
1790 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1794 vcpu->arch.cr0 = cr0;
1797 cr0 |= X86_CR0_PG | X86_CR0_WP;
1799 if (!vcpu->fpu_active)
1802 * re-enable caching here because the QEMU bios
1803 * does not do it - this results in some delay at
1806 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1807 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1808 svm->vmcb->save.cr0 = cr0;
1809 mark_dirty(svm->vmcb, VMCB_CR);
1810 update_cr0_intercept(svm);
1813 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1815 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1816 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1818 if (cr4 & X86_CR4_VMXE)
1821 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1822 svm_flush_tlb(vcpu);
1824 vcpu->arch.cr4 = cr4;
1827 cr4 |= host_cr4_mce;
1828 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1829 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1833 static void svm_set_segment(struct kvm_vcpu *vcpu,
1834 struct kvm_segment *var, int seg)
1836 struct vcpu_svm *svm = to_svm(vcpu);
1837 struct vmcb_seg *s = svm_seg(vcpu, seg);
1839 s->base = var->base;
1840 s->limit = var->limit;
1841 s->selector = var->selector;
1845 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1846 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1847 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1848 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1849 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1850 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1851 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1852 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1856 * This is always accurate, except if SYSRET returned to a segment
1857 * with SS.DPL != 3. Intel does not have this quirk, and always
1858 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1859 * would entail passing the CPL to userspace and back.
1861 if (seg == VCPU_SREG_SS)
1862 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1864 mark_dirty(svm->vmcb, VMCB_SEG);
1867 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1869 struct vcpu_svm *svm = to_svm(vcpu);
1871 clr_exception_intercept(svm, BP_VECTOR);
1873 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1874 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1875 set_exception_intercept(svm, BP_VECTOR);
1877 vcpu->guest_debug = 0;
1880 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1882 if (sd->next_asid > sd->max_asid) {
1883 ++sd->asid_generation;
1885 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1888 svm->asid_generation = sd->asid_generation;
1889 svm->vmcb->control.asid = sd->next_asid++;
1891 mark_dirty(svm->vmcb, VMCB_ASID);
1894 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1896 return to_svm(vcpu)->vmcb->save.dr6;
1899 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1901 struct vcpu_svm *svm = to_svm(vcpu);
1903 svm->vmcb->save.dr6 = value;
1904 mark_dirty(svm->vmcb, VMCB_DR);
1907 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1909 struct vcpu_svm *svm = to_svm(vcpu);
1911 get_debugreg(vcpu->arch.db[0], 0);
1912 get_debugreg(vcpu->arch.db[1], 1);
1913 get_debugreg(vcpu->arch.db[2], 2);
1914 get_debugreg(vcpu->arch.db[3], 3);
1915 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1916 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1918 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1919 set_dr_intercepts(svm);
1922 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1924 struct vcpu_svm *svm = to_svm(vcpu);
1926 svm->vmcb->save.dr7 = value;
1927 mark_dirty(svm->vmcb, VMCB_DR);
1930 static int pf_interception(struct vcpu_svm *svm)
1932 u64 fault_address = svm->vmcb->control.exit_info_2;
1936 switch (svm->apf_reason) {
1938 error_code = svm->vmcb->control.exit_info_1;
1940 trace_kvm_page_fault(fault_address, error_code);
1941 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1942 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1943 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1944 svm->vmcb->control.insn_bytes,
1945 svm->vmcb->control.insn_len);
1947 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1948 svm->apf_reason = 0;
1949 local_irq_disable();
1950 kvm_async_pf_task_wait(fault_address);
1953 case KVM_PV_REASON_PAGE_READY:
1954 svm->apf_reason = 0;
1955 local_irq_disable();
1956 kvm_async_pf_task_wake(fault_address);
1963 static int db_interception(struct vcpu_svm *svm)
1965 struct kvm_run *kvm_run = svm->vcpu.run;
1967 if (!(svm->vcpu.guest_debug &
1968 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1969 !svm->nmi_singlestep) {
1970 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1974 if (svm->nmi_singlestep) {
1975 svm->nmi_singlestep = false;
1976 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1977 svm->vmcb->save.rflags &=
1978 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1981 if (svm->vcpu.guest_debug &
1982 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1983 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1984 kvm_run->debug.arch.pc =
1985 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1986 kvm_run->debug.arch.exception = DB_VECTOR;
1993 static int bp_interception(struct vcpu_svm *svm)
1995 struct kvm_run *kvm_run = svm->vcpu.run;
1997 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1998 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1999 kvm_run->debug.arch.exception = BP_VECTOR;
2003 static int ud_interception(struct vcpu_svm *svm)
2007 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2008 if (er != EMULATE_DONE)
2009 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2013 static int ac_interception(struct vcpu_svm *svm)
2015 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2019 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
2021 struct vcpu_svm *svm = to_svm(vcpu);
2023 clr_exception_intercept(svm, NM_VECTOR);
2025 svm->vcpu.fpu_active = 1;
2026 update_cr0_intercept(svm);
2029 static int nm_interception(struct vcpu_svm *svm)
2031 svm_fpu_activate(&svm->vcpu);
2035 static bool is_erratum_383(void)
2040 if (!erratum_383_found)
2043 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2047 /* Bit 62 may or may not be set for this mce */
2048 value &= ~(1ULL << 62);
2050 if (value != 0xb600000000010015ULL)
2053 /* Clear MCi_STATUS registers */
2054 for (i = 0; i < 6; ++i)
2055 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2057 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2061 value &= ~(1ULL << 2);
2062 low = lower_32_bits(value);
2063 high = upper_32_bits(value);
2065 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2068 /* Flush tlb to evict multi-match entries */
2074 static void svm_handle_mce(struct vcpu_svm *svm)
2076 if (is_erratum_383()) {
2078 * Erratum 383 triggered. Guest state is corrupt so kill the
2081 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2083 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2089 * On an #MC intercept the MCE handler is not called automatically in
2090 * the host. So do it by hand here.
2094 /* not sure if we ever come back to this point */
2099 static int mc_interception(struct vcpu_svm *svm)
2104 static int shutdown_interception(struct vcpu_svm *svm)
2106 struct kvm_run *kvm_run = svm->vcpu.run;
2109 * VMCB is undefined after a SHUTDOWN intercept
2110 * so reinitialize it.
2112 clear_page(svm->vmcb);
2115 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2119 static int io_interception(struct vcpu_svm *svm)
2121 struct kvm_vcpu *vcpu = &svm->vcpu;
2122 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2123 int size, in, string;
2126 ++svm->vcpu.stat.io_exits;
2127 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2128 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2130 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2132 port = io_info >> 16;
2133 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2134 svm->next_rip = svm->vmcb->control.exit_info_2;
2135 skip_emulated_instruction(&svm->vcpu);
2137 return kvm_fast_pio_out(vcpu, size, port);
2140 static int nmi_interception(struct vcpu_svm *svm)
2145 static int intr_interception(struct vcpu_svm *svm)
2147 ++svm->vcpu.stat.irq_exits;
2151 static int nop_on_interception(struct vcpu_svm *svm)
2156 static int halt_interception(struct vcpu_svm *svm)
2158 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2159 return kvm_emulate_halt(&svm->vcpu);
2162 static int vmmcall_interception(struct vcpu_svm *svm)
2164 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2165 return kvm_emulate_hypercall(&svm->vcpu);
2168 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2170 struct vcpu_svm *svm = to_svm(vcpu);
2172 return svm->nested.nested_cr3;
2175 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2177 struct vcpu_svm *svm = to_svm(vcpu);
2178 u64 cr3 = svm->nested.nested_cr3;
2182 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2183 offset_in_page(cr3) + index * 8, 8);
2189 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2192 struct vcpu_svm *svm = to_svm(vcpu);
2194 svm->vmcb->control.nested_cr3 = root;
2195 mark_dirty(svm->vmcb, VMCB_NPT);
2196 svm_flush_tlb(vcpu);
2199 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2200 struct x86_exception *fault)
2202 struct vcpu_svm *svm = to_svm(vcpu);
2204 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2206 * TODO: track the cause of the nested page fault, and
2207 * correctly fill in the high bits of exit_info_1.
2209 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2210 svm->vmcb->control.exit_code_hi = 0;
2211 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2212 svm->vmcb->control.exit_info_2 = fault->address;
2215 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2216 svm->vmcb->control.exit_info_1 |= fault->error_code;
2219 * The present bit is always zero for page structure faults on real
2222 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2223 svm->vmcb->control.exit_info_1 &= ~1;
2225 nested_svm_vmexit(svm);
2228 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2230 WARN_ON(mmu_is_nested(vcpu));
2231 kvm_init_shadow_mmu(vcpu);
2232 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2233 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2234 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2235 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2236 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2237 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2238 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2241 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2243 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2246 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2248 if (!(svm->vcpu.arch.efer & EFER_SVME)
2249 || !is_paging(&svm->vcpu)) {
2250 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2254 if (svm->vmcb->save.cpl) {
2255 kvm_inject_gp(&svm->vcpu, 0);
2262 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2263 bool has_error_code, u32 error_code)
2267 if (!is_guest_mode(&svm->vcpu))
2270 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2271 svm->vmcb->control.exit_code_hi = 0;
2272 svm->vmcb->control.exit_info_1 = error_code;
2273 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2275 vmexit = nested_svm_intercept(svm);
2276 if (vmexit == NESTED_EXIT_DONE)
2277 svm->nested.exit_required = true;
2282 /* This function returns true if it is save to enable the irq window */
2283 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2285 if (!is_guest_mode(&svm->vcpu))
2288 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2291 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2295 * if vmexit was already requested (by intercepted exception
2296 * for instance) do not overwrite it with "external interrupt"
2299 if (svm->nested.exit_required)
2302 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2303 svm->vmcb->control.exit_info_1 = 0;
2304 svm->vmcb->control.exit_info_2 = 0;
2306 if (svm->nested.intercept & 1ULL) {
2308 * The #vmexit can't be emulated here directly because this
2309 * code path runs with irqs and preemption disabled. A
2310 * #vmexit emulation might sleep. Only signal request for
2313 svm->nested.exit_required = true;
2314 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2321 /* This function returns true if it is save to enable the nmi window */
2322 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2324 if (!is_guest_mode(&svm->vcpu))
2327 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2330 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2331 svm->nested.exit_required = true;
2336 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2342 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2343 if (is_error_page(page))
2351 kvm_inject_gp(&svm->vcpu, 0);
2356 static void nested_svm_unmap(struct page *page)
2359 kvm_release_page_dirty(page);
2362 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2364 unsigned port, size, iopm_len;
2369 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2370 return NESTED_EXIT_HOST;
2372 port = svm->vmcb->control.exit_info_1 >> 16;
2373 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2374 SVM_IOIO_SIZE_SHIFT;
2375 gpa = svm->nested.vmcb_iopm + (port / 8);
2376 start_bit = port % 8;
2377 iopm_len = (start_bit + size > 8) ? 2 : 1;
2378 mask = (0xf >> (4 - size)) << start_bit;
2381 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2382 return NESTED_EXIT_DONE;
2384 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2387 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2389 u32 offset, msr, value;
2392 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2393 return NESTED_EXIT_HOST;
2395 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2396 offset = svm_msrpm_offset(msr);
2397 write = svm->vmcb->control.exit_info_1 & 1;
2398 mask = 1 << ((2 * (msr & 0xf)) + write);
2400 if (offset == MSR_INVALID)
2401 return NESTED_EXIT_DONE;
2403 /* Offset is in 32 bit units but need in 8 bit units */
2406 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2407 return NESTED_EXIT_DONE;
2409 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2412 static int nested_svm_exit_special(struct vcpu_svm *svm)
2414 u32 exit_code = svm->vmcb->control.exit_code;
2416 switch (exit_code) {
2419 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2420 return NESTED_EXIT_HOST;
2422 /* For now we are always handling NPFs when using them */
2424 return NESTED_EXIT_HOST;
2426 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2427 /* When we're shadowing, trap PFs, but not async PF */
2428 if (!npt_enabled && svm->apf_reason == 0)
2429 return NESTED_EXIT_HOST;
2431 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2432 nm_interception(svm);
2438 return NESTED_EXIT_CONTINUE;
2442 * If this function returns true, this #vmexit was already handled
2444 static int nested_svm_intercept(struct vcpu_svm *svm)
2446 u32 exit_code = svm->vmcb->control.exit_code;
2447 int vmexit = NESTED_EXIT_HOST;
2449 switch (exit_code) {
2451 vmexit = nested_svm_exit_handled_msr(svm);
2454 vmexit = nested_svm_intercept_ioio(svm);
2456 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2457 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2458 if (svm->nested.intercept_cr & bit)
2459 vmexit = NESTED_EXIT_DONE;
2462 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2463 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2464 if (svm->nested.intercept_dr & bit)
2465 vmexit = NESTED_EXIT_DONE;
2468 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2469 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2470 if (svm->nested.intercept_exceptions & excp_bits)
2471 vmexit = NESTED_EXIT_DONE;
2472 /* async page fault always cause vmexit */
2473 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2474 svm->apf_reason != 0)
2475 vmexit = NESTED_EXIT_DONE;
2478 case SVM_EXIT_ERR: {
2479 vmexit = NESTED_EXIT_DONE;
2483 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2484 if (svm->nested.intercept & exit_bits)
2485 vmexit = NESTED_EXIT_DONE;
2492 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2496 vmexit = nested_svm_intercept(svm);
2498 if (vmexit == NESTED_EXIT_DONE)
2499 nested_svm_vmexit(svm);
2504 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2506 struct vmcb_control_area *dst = &dst_vmcb->control;
2507 struct vmcb_control_area *from = &from_vmcb->control;
2509 dst->intercept_cr = from->intercept_cr;
2510 dst->intercept_dr = from->intercept_dr;
2511 dst->intercept_exceptions = from->intercept_exceptions;
2512 dst->intercept = from->intercept;
2513 dst->iopm_base_pa = from->iopm_base_pa;
2514 dst->msrpm_base_pa = from->msrpm_base_pa;
2515 dst->tsc_offset = from->tsc_offset;
2516 dst->asid = from->asid;
2517 dst->tlb_ctl = from->tlb_ctl;
2518 dst->int_ctl = from->int_ctl;
2519 dst->int_vector = from->int_vector;
2520 dst->int_state = from->int_state;
2521 dst->exit_code = from->exit_code;
2522 dst->exit_code_hi = from->exit_code_hi;
2523 dst->exit_info_1 = from->exit_info_1;
2524 dst->exit_info_2 = from->exit_info_2;
2525 dst->exit_int_info = from->exit_int_info;
2526 dst->exit_int_info_err = from->exit_int_info_err;
2527 dst->nested_ctl = from->nested_ctl;
2528 dst->event_inj = from->event_inj;
2529 dst->event_inj_err = from->event_inj_err;
2530 dst->nested_cr3 = from->nested_cr3;
2531 dst->lbr_ctl = from->lbr_ctl;
2534 static int nested_svm_vmexit(struct vcpu_svm *svm)
2536 struct vmcb *nested_vmcb;
2537 struct vmcb *hsave = svm->nested.hsave;
2538 struct vmcb *vmcb = svm->vmcb;
2541 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2542 vmcb->control.exit_info_1,
2543 vmcb->control.exit_info_2,
2544 vmcb->control.exit_int_info,
2545 vmcb->control.exit_int_info_err,
2548 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2552 /* Exit Guest-Mode */
2553 leave_guest_mode(&svm->vcpu);
2554 svm->nested.vmcb = 0;
2556 /* Give the current vmcb to the guest */
2559 nested_vmcb->save.es = vmcb->save.es;
2560 nested_vmcb->save.cs = vmcb->save.cs;
2561 nested_vmcb->save.ss = vmcb->save.ss;
2562 nested_vmcb->save.ds = vmcb->save.ds;
2563 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2564 nested_vmcb->save.idtr = vmcb->save.idtr;
2565 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2566 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2567 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2568 nested_vmcb->save.cr2 = vmcb->save.cr2;
2569 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2570 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2571 nested_vmcb->save.rip = vmcb->save.rip;
2572 nested_vmcb->save.rsp = vmcb->save.rsp;
2573 nested_vmcb->save.rax = vmcb->save.rax;
2574 nested_vmcb->save.dr7 = vmcb->save.dr7;
2575 nested_vmcb->save.dr6 = vmcb->save.dr6;
2576 nested_vmcb->save.cpl = vmcb->save.cpl;
2578 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2579 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2580 nested_vmcb->control.int_state = vmcb->control.int_state;
2581 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2582 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2583 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2584 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2585 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2586 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2588 if (svm->nrips_enabled)
2589 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2592 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2593 * to make sure that we do not lose injected events. So check event_inj
2594 * here and copy it to exit_int_info if it is valid.
2595 * Exit_int_info and event_inj can't be both valid because the case
2596 * below only happens on a VMRUN instruction intercept which has
2597 * no valid exit_int_info set.
2599 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2600 struct vmcb_control_area *nc = &nested_vmcb->control;
2602 nc->exit_int_info = vmcb->control.event_inj;
2603 nc->exit_int_info_err = vmcb->control.event_inj_err;
2606 nested_vmcb->control.tlb_ctl = 0;
2607 nested_vmcb->control.event_inj = 0;
2608 nested_vmcb->control.event_inj_err = 0;
2610 /* We always set V_INTR_MASKING and remember the old value in hflags */
2611 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2612 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2614 /* Restore the original control entries */
2615 copy_vmcb_control_area(vmcb, hsave);
2617 kvm_clear_exception_queue(&svm->vcpu);
2618 kvm_clear_interrupt_queue(&svm->vcpu);
2620 svm->nested.nested_cr3 = 0;
2622 /* Restore selected save entries */
2623 svm->vmcb->save.es = hsave->save.es;
2624 svm->vmcb->save.cs = hsave->save.cs;
2625 svm->vmcb->save.ss = hsave->save.ss;
2626 svm->vmcb->save.ds = hsave->save.ds;
2627 svm->vmcb->save.gdtr = hsave->save.gdtr;
2628 svm->vmcb->save.idtr = hsave->save.idtr;
2629 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2630 svm_set_efer(&svm->vcpu, hsave->save.efer);
2631 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2632 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2634 svm->vmcb->save.cr3 = hsave->save.cr3;
2635 svm->vcpu.arch.cr3 = hsave->save.cr3;
2637 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2639 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2640 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2641 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2642 svm->vmcb->save.dr7 = 0;
2643 svm->vmcb->save.cpl = 0;
2644 svm->vmcb->control.exit_int_info = 0;
2646 mark_all_dirty(svm->vmcb);
2648 nested_svm_unmap(page);
2650 nested_svm_uninit_mmu_context(&svm->vcpu);
2651 kvm_mmu_reset_context(&svm->vcpu);
2652 kvm_mmu_load(&svm->vcpu);
2657 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2660 * This function merges the msr permission bitmaps of kvm and the
2661 * nested vmcb. It is optimized in that it only merges the parts where
2662 * the kvm msr permission bitmap may contain zero bits
2666 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2669 for (i = 0; i < MSRPM_OFFSETS; i++) {
2673 if (msrpm_offsets[i] == 0xffffffff)
2676 p = msrpm_offsets[i];
2677 offset = svm->nested.vmcb_msrpm + (p * 4);
2679 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2682 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2685 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2690 static bool nested_vmcb_checks(struct vmcb *vmcb)
2692 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2695 if (vmcb->control.asid == 0)
2698 if (vmcb->control.nested_ctl && !npt_enabled)
2704 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2706 struct vmcb *nested_vmcb;
2707 struct vmcb *hsave = svm->nested.hsave;
2708 struct vmcb *vmcb = svm->vmcb;
2712 vmcb_gpa = svm->vmcb->save.rax;
2714 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2718 if (!nested_vmcb_checks(nested_vmcb)) {
2719 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2720 nested_vmcb->control.exit_code_hi = 0;
2721 nested_vmcb->control.exit_info_1 = 0;
2722 nested_vmcb->control.exit_info_2 = 0;
2724 nested_svm_unmap(page);
2729 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2730 nested_vmcb->save.rip,
2731 nested_vmcb->control.int_ctl,
2732 nested_vmcb->control.event_inj,
2733 nested_vmcb->control.nested_ctl);
2735 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2736 nested_vmcb->control.intercept_cr >> 16,
2737 nested_vmcb->control.intercept_exceptions,
2738 nested_vmcb->control.intercept);
2740 /* Clear internal status */
2741 kvm_clear_exception_queue(&svm->vcpu);
2742 kvm_clear_interrupt_queue(&svm->vcpu);
2745 * Save the old vmcb, so we don't need to pick what we save, but can
2746 * restore everything when a VMEXIT occurs
2748 hsave->save.es = vmcb->save.es;
2749 hsave->save.cs = vmcb->save.cs;
2750 hsave->save.ss = vmcb->save.ss;
2751 hsave->save.ds = vmcb->save.ds;
2752 hsave->save.gdtr = vmcb->save.gdtr;
2753 hsave->save.idtr = vmcb->save.idtr;
2754 hsave->save.efer = svm->vcpu.arch.efer;
2755 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2756 hsave->save.cr4 = svm->vcpu.arch.cr4;
2757 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2758 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2759 hsave->save.rsp = vmcb->save.rsp;
2760 hsave->save.rax = vmcb->save.rax;
2762 hsave->save.cr3 = vmcb->save.cr3;
2764 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2766 copy_vmcb_control_area(hsave, vmcb);
2768 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2769 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2771 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2773 if (nested_vmcb->control.nested_ctl) {
2774 kvm_mmu_unload(&svm->vcpu);
2775 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2776 nested_svm_init_mmu_context(&svm->vcpu);
2779 /* Load the nested guest state */
2780 svm->vmcb->save.es = nested_vmcb->save.es;
2781 svm->vmcb->save.cs = nested_vmcb->save.cs;
2782 svm->vmcb->save.ss = nested_vmcb->save.ss;
2783 svm->vmcb->save.ds = nested_vmcb->save.ds;
2784 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2785 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2786 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2787 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2788 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2789 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2791 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2792 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2794 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2796 /* Guest paging mode is active - reset mmu */
2797 kvm_mmu_reset_context(&svm->vcpu);
2799 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2800 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2801 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2802 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2804 /* In case we don't even reach vcpu_run, the fields are not updated */
2805 svm->vmcb->save.rax = nested_vmcb->save.rax;
2806 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2807 svm->vmcb->save.rip = nested_vmcb->save.rip;
2808 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2809 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2810 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2812 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2813 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2815 /* cache intercepts */
2816 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2817 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2818 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2819 svm->nested.intercept = nested_vmcb->control.intercept;
2821 svm_flush_tlb(&svm->vcpu);
2822 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2823 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2824 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2826 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2828 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2829 /* We only want the cr8 intercept bits of the guest */
2830 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2831 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2834 /* We don't want to see VMMCALLs from a nested guest */
2835 clr_intercept(svm, INTERCEPT_VMMCALL);
2837 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2838 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2839 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2840 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2841 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2842 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2844 nested_svm_unmap(page);
2846 /* Enter Guest-Mode */
2847 enter_guest_mode(&svm->vcpu);
2850 * Merge guest and host intercepts - must be called with vcpu in
2851 * guest-mode to take affect here
2853 recalc_intercepts(svm);
2855 svm->nested.vmcb = vmcb_gpa;
2859 mark_all_dirty(svm->vmcb);
2864 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2866 to_vmcb->save.fs = from_vmcb->save.fs;
2867 to_vmcb->save.gs = from_vmcb->save.gs;
2868 to_vmcb->save.tr = from_vmcb->save.tr;
2869 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2870 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2871 to_vmcb->save.star = from_vmcb->save.star;
2872 to_vmcb->save.lstar = from_vmcb->save.lstar;
2873 to_vmcb->save.cstar = from_vmcb->save.cstar;
2874 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2875 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2876 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2877 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2880 static int vmload_interception(struct vcpu_svm *svm)
2882 struct vmcb *nested_vmcb;
2885 if (nested_svm_check_permissions(svm))
2888 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2892 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2893 skip_emulated_instruction(&svm->vcpu);
2895 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2896 nested_svm_unmap(page);
2901 static int vmsave_interception(struct vcpu_svm *svm)
2903 struct vmcb *nested_vmcb;
2906 if (nested_svm_check_permissions(svm))
2909 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2913 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2914 skip_emulated_instruction(&svm->vcpu);
2916 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2917 nested_svm_unmap(page);
2922 static int vmrun_interception(struct vcpu_svm *svm)
2924 if (nested_svm_check_permissions(svm))
2927 /* Save rip after vmrun instruction */
2928 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2930 if (!nested_svm_vmrun(svm))
2933 if (!nested_svm_vmrun_msrpm(svm))
2940 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2941 svm->vmcb->control.exit_code_hi = 0;
2942 svm->vmcb->control.exit_info_1 = 0;
2943 svm->vmcb->control.exit_info_2 = 0;
2945 nested_svm_vmexit(svm);
2950 static int stgi_interception(struct vcpu_svm *svm)
2952 if (nested_svm_check_permissions(svm))
2955 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2956 skip_emulated_instruction(&svm->vcpu);
2957 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2964 static int clgi_interception(struct vcpu_svm *svm)
2966 if (nested_svm_check_permissions(svm))
2969 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2970 skip_emulated_instruction(&svm->vcpu);
2974 /* After a CLGI no interrupts should come */
2975 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
2976 svm_clear_vintr(svm);
2977 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2978 mark_dirty(svm->vmcb, VMCB_INTR);
2984 static int invlpga_interception(struct vcpu_svm *svm)
2986 struct kvm_vcpu *vcpu = &svm->vcpu;
2988 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2989 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2991 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2992 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2994 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2995 skip_emulated_instruction(&svm->vcpu);
2999 static int skinit_interception(struct vcpu_svm *svm)
3001 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3003 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3007 static int wbinvd_interception(struct vcpu_svm *svm)
3009 kvm_emulate_wbinvd(&svm->vcpu);
3013 static int xsetbv_interception(struct vcpu_svm *svm)
3015 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3016 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3018 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3019 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3020 skip_emulated_instruction(&svm->vcpu);
3026 static int task_switch_interception(struct vcpu_svm *svm)
3030 int int_type = svm->vmcb->control.exit_int_info &
3031 SVM_EXITINTINFO_TYPE_MASK;
3032 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3034 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3036 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3037 bool has_error_code = false;
3040 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3042 if (svm->vmcb->control.exit_info_2 &
3043 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3044 reason = TASK_SWITCH_IRET;
3045 else if (svm->vmcb->control.exit_info_2 &
3046 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3047 reason = TASK_SWITCH_JMP;
3049 reason = TASK_SWITCH_GATE;
3051 reason = TASK_SWITCH_CALL;
3053 if (reason == TASK_SWITCH_GATE) {
3055 case SVM_EXITINTINFO_TYPE_NMI:
3056 svm->vcpu.arch.nmi_injected = false;
3058 case SVM_EXITINTINFO_TYPE_EXEPT:
3059 if (svm->vmcb->control.exit_info_2 &
3060 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3061 has_error_code = true;
3063 (u32)svm->vmcb->control.exit_info_2;
3065 kvm_clear_exception_queue(&svm->vcpu);
3067 case SVM_EXITINTINFO_TYPE_INTR:
3068 kvm_clear_interrupt_queue(&svm->vcpu);
3075 if (reason != TASK_SWITCH_GATE ||
3076 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3077 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3078 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3079 skip_emulated_instruction(&svm->vcpu);
3081 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3084 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3085 has_error_code, error_code) == EMULATE_FAIL) {
3086 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3087 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3088 svm->vcpu.run->internal.ndata = 0;
3094 static int cpuid_interception(struct vcpu_svm *svm)
3096 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3097 kvm_emulate_cpuid(&svm->vcpu);
3101 static int iret_interception(struct vcpu_svm *svm)
3103 ++svm->vcpu.stat.nmi_window_exits;
3104 clr_intercept(svm, INTERCEPT_IRET);
3105 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3106 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3107 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3111 static int invlpg_interception(struct vcpu_svm *svm)
3113 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3114 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3116 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3117 skip_emulated_instruction(&svm->vcpu);
3121 static int emulate_on_interception(struct vcpu_svm *svm)
3123 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3126 static int rdpmc_interception(struct vcpu_svm *svm)
3130 if (!static_cpu_has(X86_FEATURE_NRIPS))
3131 return emulate_on_interception(svm);
3133 err = kvm_rdpmc(&svm->vcpu);
3134 kvm_complete_insn_gp(&svm->vcpu, err);
3139 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3142 unsigned long cr0 = svm->vcpu.arch.cr0;
3146 intercept = svm->nested.intercept;
3148 if (!is_guest_mode(&svm->vcpu) ||
3149 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3152 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3153 val &= ~SVM_CR0_SELECTIVE_MASK;
3156 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3157 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3163 #define CR_VALID (1ULL << 63)
3165 static int cr_interception(struct vcpu_svm *svm)
3171 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3172 return emulate_on_interception(svm);
3174 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3175 return emulate_on_interception(svm);
3177 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3178 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3179 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3181 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3184 if (cr >= 16) { /* mov to cr */
3186 val = kvm_register_read(&svm->vcpu, reg);
3189 if (!check_selective_cr0_intercepted(svm, val))
3190 err = kvm_set_cr0(&svm->vcpu, val);
3196 err = kvm_set_cr3(&svm->vcpu, val);
3199 err = kvm_set_cr4(&svm->vcpu, val);
3202 err = kvm_set_cr8(&svm->vcpu, val);
3205 WARN(1, "unhandled write to CR%d", cr);
3206 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3209 } else { /* mov from cr */
3212 val = kvm_read_cr0(&svm->vcpu);
3215 val = svm->vcpu.arch.cr2;
3218 val = kvm_read_cr3(&svm->vcpu);
3221 val = kvm_read_cr4(&svm->vcpu);
3224 val = kvm_get_cr8(&svm->vcpu);
3227 WARN(1, "unhandled read from CR%d", cr);
3228 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3231 kvm_register_write(&svm->vcpu, reg, val);
3233 kvm_complete_insn_gp(&svm->vcpu, err);
3238 static int dr_interception(struct vcpu_svm *svm)
3243 if (svm->vcpu.guest_debug == 0) {
3245 * No more DR vmexits; force a reload of the debug registers
3246 * and reenter on this instruction. The next vmexit will
3247 * retrieve the full state of the debug registers.
3249 clr_dr_intercepts(svm);
3250 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3254 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3255 return emulate_on_interception(svm);
3257 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3258 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3260 if (dr >= 16) { /* mov to DRn */
3261 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3263 val = kvm_register_read(&svm->vcpu, reg);
3264 kvm_set_dr(&svm->vcpu, dr - 16, val);
3266 if (!kvm_require_dr(&svm->vcpu, dr))
3268 kvm_get_dr(&svm->vcpu, dr, &val);
3269 kvm_register_write(&svm->vcpu, reg, val);
3272 skip_emulated_instruction(&svm->vcpu);
3277 static int cr8_write_interception(struct vcpu_svm *svm)
3279 struct kvm_run *kvm_run = svm->vcpu.run;
3282 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3283 /* instruction emulation calls kvm_set_cr8() */
3284 r = cr_interception(svm);
3285 if (lapic_in_kernel(&svm->vcpu))
3287 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3289 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3293 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3295 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3296 return vmcb->control.tsc_offset + host_tsc;
3299 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3301 struct vcpu_svm *svm = to_svm(vcpu);
3303 switch (msr_info->index) {
3304 case MSR_IA32_TSC: {
3305 msr_info->data = svm->vmcb->control.tsc_offset +
3306 kvm_scale_tsc(vcpu, rdtsc());
3311 msr_info->data = svm->vmcb->save.star;
3313 #ifdef CONFIG_X86_64
3315 msr_info->data = svm->vmcb->save.lstar;
3318 msr_info->data = svm->vmcb->save.cstar;
3320 case MSR_KERNEL_GS_BASE:
3321 msr_info->data = svm->vmcb->save.kernel_gs_base;
3323 case MSR_SYSCALL_MASK:
3324 msr_info->data = svm->vmcb->save.sfmask;
3327 case MSR_IA32_SYSENTER_CS:
3328 msr_info->data = svm->vmcb->save.sysenter_cs;
3330 case MSR_IA32_SYSENTER_EIP:
3331 msr_info->data = svm->sysenter_eip;
3333 case MSR_IA32_SYSENTER_ESP:
3334 msr_info->data = svm->sysenter_esp;
3337 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3339 msr_info->data = svm->tsc_aux;
3342 * Nobody will change the following 5 values in the VMCB so we can
3343 * safely return them on rdmsr. They will always be 0 until LBRV is
3346 case MSR_IA32_DEBUGCTLMSR:
3347 msr_info->data = svm->vmcb->save.dbgctl;
3349 case MSR_IA32_LASTBRANCHFROMIP:
3350 msr_info->data = svm->vmcb->save.br_from;
3352 case MSR_IA32_LASTBRANCHTOIP:
3353 msr_info->data = svm->vmcb->save.br_to;
3355 case MSR_IA32_LASTINTFROMIP:
3356 msr_info->data = svm->vmcb->save.last_excp_from;
3358 case MSR_IA32_LASTINTTOIP:
3359 msr_info->data = svm->vmcb->save.last_excp_to;
3361 case MSR_VM_HSAVE_PA:
3362 msr_info->data = svm->nested.hsave_msr;
3365 msr_info->data = svm->nested.vm_cr_msr;
3367 case MSR_IA32_UCODE_REV:
3368 msr_info->data = 0x01000065;
3370 case MSR_F15H_IC_CFG: {
3374 family = guest_cpuid_family(vcpu);
3375 model = guest_cpuid_model(vcpu);
3377 if (family < 0 || model < 0)
3378 return kvm_get_msr_common(vcpu, msr_info);
3382 if (family == 0x15 &&
3383 (model >= 0x2 && model < 0x20))
3384 msr_info->data = 0x1E;
3388 return kvm_get_msr_common(vcpu, msr_info);
3393 static int rdmsr_interception(struct vcpu_svm *svm)
3395 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3396 struct msr_data msr_info;
3398 msr_info.index = ecx;
3399 msr_info.host_initiated = false;
3400 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3401 trace_kvm_msr_read_ex(ecx);
3402 kvm_inject_gp(&svm->vcpu, 0);
3404 trace_kvm_msr_read(ecx, msr_info.data);
3406 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3407 msr_info.data & 0xffffffff);
3408 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3409 msr_info.data >> 32);
3410 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3411 skip_emulated_instruction(&svm->vcpu);
3416 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3418 struct vcpu_svm *svm = to_svm(vcpu);
3419 int svm_dis, chg_mask;
3421 if (data & ~SVM_VM_CR_VALID_MASK)
3424 chg_mask = SVM_VM_CR_VALID_MASK;
3426 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3427 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3429 svm->nested.vm_cr_msr &= ~chg_mask;
3430 svm->nested.vm_cr_msr |= (data & chg_mask);
3432 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3434 /* check for svm_disable while efer.svme is set */
3435 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3441 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3443 struct vcpu_svm *svm = to_svm(vcpu);
3445 u32 ecx = msr->index;
3446 u64 data = msr->data;
3449 kvm_write_tsc(vcpu, msr);
3452 svm->vmcb->save.star = data;
3454 #ifdef CONFIG_X86_64
3456 svm->vmcb->save.lstar = data;
3459 svm->vmcb->save.cstar = data;
3461 case MSR_KERNEL_GS_BASE:
3462 svm->vmcb->save.kernel_gs_base = data;
3464 case MSR_SYSCALL_MASK:
3465 svm->vmcb->save.sfmask = data;
3468 case MSR_IA32_SYSENTER_CS:
3469 svm->vmcb->save.sysenter_cs = data;
3471 case MSR_IA32_SYSENTER_EIP:
3472 svm->sysenter_eip = data;
3473 svm->vmcb->save.sysenter_eip = data;
3475 case MSR_IA32_SYSENTER_ESP:
3476 svm->sysenter_esp = data;
3477 svm->vmcb->save.sysenter_esp = data;
3480 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3484 * This is rare, so we update the MSR here instead of using
3485 * direct_access_msrs. Doing that would require a rdmsr in
3488 svm->tsc_aux = data;
3489 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3491 case MSR_IA32_DEBUGCTLMSR:
3492 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3493 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3497 if (data & DEBUGCTL_RESERVED_BITS)
3500 svm->vmcb->save.dbgctl = data;
3501 mark_dirty(svm->vmcb, VMCB_LBR);
3502 if (data & (1ULL<<0))
3503 svm_enable_lbrv(svm);
3505 svm_disable_lbrv(svm);
3507 case MSR_VM_HSAVE_PA:
3508 svm->nested.hsave_msr = data;
3511 return svm_set_vm_cr(vcpu, data);
3513 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3515 case MSR_IA32_APICBASE:
3516 if (kvm_vcpu_apicv_active(vcpu))
3517 avic_update_vapic_bar(to_svm(vcpu), data);
3518 /* Follow through */
3520 return kvm_set_msr_common(vcpu, msr);
3525 static int wrmsr_interception(struct vcpu_svm *svm)
3527 struct msr_data msr;
3528 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3529 u64 data = kvm_read_edx_eax(&svm->vcpu);
3533 msr.host_initiated = false;
3535 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3536 if (kvm_set_msr(&svm->vcpu, &msr)) {
3537 trace_kvm_msr_write_ex(ecx, data);
3538 kvm_inject_gp(&svm->vcpu, 0);
3540 trace_kvm_msr_write(ecx, data);
3541 skip_emulated_instruction(&svm->vcpu);
3546 static int msr_interception(struct vcpu_svm *svm)
3548 if (svm->vmcb->control.exit_info_1)
3549 return wrmsr_interception(svm);
3551 return rdmsr_interception(svm);
3554 static int interrupt_window_interception(struct vcpu_svm *svm)
3556 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3557 svm_clear_vintr(svm);
3558 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3559 mark_dirty(svm->vmcb, VMCB_INTR);
3560 ++svm->vcpu.stat.irq_window_exits;
3564 static int pause_interception(struct vcpu_svm *svm)
3566 kvm_vcpu_on_spin(&(svm->vcpu));
3570 static int nop_interception(struct vcpu_svm *svm)
3572 skip_emulated_instruction(&(svm->vcpu));
3576 static int monitor_interception(struct vcpu_svm *svm)
3578 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3579 return nop_interception(svm);
3582 static int mwait_interception(struct vcpu_svm *svm)
3584 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3585 return nop_interception(svm);
3588 enum avic_ipi_failure_cause {
3589 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3590 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3591 AVIC_IPI_FAILURE_INVALID_TARGET,
3592 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3595 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3597 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3598 u32 icrl = svm->vmcb->control.exit_info_1;
3599 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3600 u32 index = svm->vmcb->control.exit_info_2 && 0xFF;
3601 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3603 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3606 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3608 * AVIC hardware handles the generation of
3609 * IPIs when the specified Message Type is Fixed
3610 * (also known as fixed delivery mode) and
3611 * the Trigger Mode is edge-triggered. The hardware
3612 * also supports self and broadcast delivery modes
3613 * specified via the Destination Shorthand(DSH)
3614 * field of the ICRL. Logical and physical APIC ID
3615 * formats are supported. All other IPI types cause
3616 * a #VMEXIT, which needs to emulated.
3618 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3619 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3621 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3623 struct kvm_vcpu *vcpu;
3624 struct kvm *kvm = svm->vcpu.kvm;
3625 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3628 * At this point, we expect that the AVIC HW has already
3629 * set the appropriate IRR bits on the valid target
3630 * vcpus. So, we just need to kick the appropriate vcpu.
3632 kvm_for_each_vcpu(i, vcpu, kvm) {
3633 bool m = kvm_apic_match_dest(vcpu, apic,
3634 icrl & KVM_APIC_SHORT_MASK,
3635 GET_APIC_DEST_FIELD(icrh),
3636 icrl & KVM_APIC_DEST_MASK);
3638 if (m && !avic_vcpu_is_running(vcpu))
3639 kvm_vcpu_wake_up(vcpu);
3643 case AVIC_IPI_FAILURE_INVALID_TARGET:
3645 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3646 WARN_ONCE(1, "Invalid backing page\n");
3649 pr_err("Unknown IPI interception\n");
3655 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3657 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3659 u32 *logical_apic_id_table;
3660 int dlid = GET_APIC_LOGICAL_ID(ldr);
3665 if (flat) { /* flat */
3666 index = ffs(dlid) - 1;
3669 } else { /* cluster */
3670 int cluster = (dlid & 0xf0) >> 4;
3671 int apic = ffs(dlid & 0x0f) - 1;
3673 if ((apic < 0) || (apic > 7) ||
3676 index = (cluster << 2) + apic;
3679 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3681 return &logical_apic_id_table[index];
3684 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3688 u32 *entry, new_entry;
3690 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3691 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3695 new_entry = READ_ONCE(*entry);
3696 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3697 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3699 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3701 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3702 WRITE_ONCE(*entry, new_entry);
3707 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3710 struct vcpu_svm *svm = to_svm(vcpu);
3711 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3716 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3717 if (ret && svm->ldr_reg) {
3718 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3726 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3729 struct vcpu_svm *svm = to_svm(vcpu);
3730 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3731 u32 id = (apic_id_reg >> 24) & 0xff;
3733 if (vcpu->vcpu_id == id)
3736 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3737 new = avic_get_physical_id_entry(vcpu, id);
3741 /* We need to move physical_id_entry to new offset */
3744 to_svm(vcpu)->avic_physical_id_cache = new;
3747 * Also update the guest physical APIC ID in the logical
3748 * APIC ID table entry if already setup the LDR.
3751 avic_handle_ldr_update(vcpu);
3756 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3758 struct vcpu_svm *svm = to_svm(vcpu);
3759 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3760 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3761 u32 mod = (dfr >> 28) & 0xf;
3764 * We assume that all local APICs are using the same type.
3765 * If this changes, we need to flush the AVIC logical
3768 if (vm_data->ldr_mode == mod)
3771 clear_page(page_address(vm_data->avic_logical_id_table_page));
3772 vm_data->ldr_mode = mod;
3775 avic_handle_ldr_update(vcpu);
3779 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3781 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3782 u32 offset = svm->vmcb->control.exit_info_1 &
3783 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3787 if (avic_handle_apic_id_update(&svm->vcpu))
3791 if (avic_handle_ldr_update(&svm->vcpu))
3795 avic_handle_dfr_update(&svm->vcpu);
3801 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3806 static bool is_avic_unaccelerated_access_trap(u32 offset)
3835 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3838 u32 offset = svm->vmcb->control.exit_info_1 &
3839 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3840 u32 vector = svm->vmcb->control.exit_info_2 &
3841 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3842 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3843 AVIC_UNACCEL_ACCESS_WRITE_MASK;
3844 bool trap = is_avic_unaccelerated_access_trap(offset);
3846 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3847 trap, write, vector);
3850 WARN_ONCE(!write, "svm: Handling trap read.\n");
3851 ret = avic_unaccel_trap_write(svm);
3853 /* Handling Fault */
3854 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3860 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3861 [SVM_EXIT_READ_CR0] = cr_interception,
3862 [SVM_EXIT_READ_CR3] = cr_interception,
3863 [SVM_EXIT_READ_CR4] = cr_interception,
3864 [SVM_EXIT_READ_CR8] = cr_interception,
3865 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3866 [SVM_EXIT_WRITE_CR0] = cr_interception,
3867 [SVM_EXIT_WRITE_CR3] = cr_interception,
3868 [SVM_EXIT_WRITE_CR4] = cr_interception,
3869 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3870 [SVM_EXIT_READ_DR0] = dr_interception,
3871 [SVM_EXIT_READ_DR1] = dr_interception,
3872 [SVM_EXIT_READ_DR2] = dr_interception,
3873 [SVM_EXIT_READ_DR3] = dr_interception,
3874 [SVM_EXIT_READ_DR4] = dr_interception,
3875 [SVM_EXIT_READ_DR5] = dr_interception,
3876 [SVM_EXIT_READ_DR6] = dr_interception,
3877 [SVM_EXIT_READ_DR7] = dr_interception,
3878 [SVM_EXIT_WRITE_DR0] = dr_interception,
3879 [SVM_EXIT_WRITE_DR1] = dr_interception,
3880 [SVM_EXIT_WRITE_DR2] = dr_interception,
3881 [SVM_EXIT_WRITE_DR3] = dr_interception,
3882 [SVM_EXIT_WRITE_DR4] = dr_interception,
3883 [SVM_EXIT_WRITE_DR5] = dr_interception,
3884 [SVM_EXIT_WRITE_DR6] = dr_interception,
3885 [SVM_EXIT_WRITE_DR7] = dr_interception,
3886 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3887 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3888 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3889 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3890 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3891 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3892 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3893 [SVM_EXIT_INTR] = intr_interception,
3894 [SVM_EXIT_NMI] = nmi_interception,
3895 [SVM_EXIT_SMI] = nop_on_interception,
3896 [SVM_EXIT_INIT] = nop_on_interception,
3897 [SVM_EXIT_VINTR] = interrupt_window_interception,
3898 [SVM_EXIT_RDPMC] = rdpmc_interception,
3899 [SVM_EXIT_CPUID] = cpuid_interception,
3900 [SVM_EXIT_IRET] = iret_interception,
3901 [SVM_EXIT_INVD] = emulate_on_interception,
3902 [SVM_EXIT_PAUSE] = pause_interception,
3903 [SVM_EXIT_HLT] = halt_interception,
3904 [SVM_EXIT_INVLPG] = invlpg_interception,
3905 [SVM_EXIT_INVLPGA] = invlpga_interception,
3906 [SVM_EXIT_IOIO] = io_interception,
3907 [SVM_EXIT_MSR] = msr_interception,
3908 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3909 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3910 [SVM_EXIT_VMRUN] = vmrun_interception,
3911 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3912 [SVM_EXIT_VMLOAD] = vmload_interception,
3913 [SVM_EXIT_VMSAVE] = vmsave_interception,
3914 [SVM_EXIT_STGI] = stgi_interception,
3915 [SVM_EXIT_CLGI] = clgi_interception,
3916 [SVM_EXIT_SKINIT] = skinit_interception,
3917 [SVM_EXIT_WBINVD] = wbinvd_interception,
3918 [SVM_EXIT_MONITOR] = monitor_interception,
3919 [SVM_EXIT_MWAIT] = mwait_interception,
3920 [SVM_EXIT_XSETBV] = xsetbv_interception,
3921 [SVM_EXIT_NPF] = pf_interception,
3922 [SVM_EXIT_RSM] = emulate_on_interception,
3923 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3924 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3927 static void dump_vmcb(struct kvm_vcpu *vcpu)
3929 struct vcpu_svm *svm = to_svm(vcpu);
3930 struct vmcb_control_area *control = &svm->vmcb->control;
3931 struct vmcb_save_area *save = &svm->vmcb->save;
3933 pr_err("VMCB Control Area:\n");
3934 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3935 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3936 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3937 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3938 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3939 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3940 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3941 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3942 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3943 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3944 pr_err("%-20s%d\n", "asid:", control->asid);
3945 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3946 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3947 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3948 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3949 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3950 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3951 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3952 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3953 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3954 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3955 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3956 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3957 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3958 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3959 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3960 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3961 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3962 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3963 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3964 pr_err("VMCB State Save Area:\n");
3965 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3967 save->es.selector, save->es.attrib,
3968 save->es.limit, save->es.base);
3969 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3971 save->cs.selector, save->cs.attrib,
3972 save->cs.limit, save->cs.base);
3973 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3975 save->ss.selector, save->ss.attrib,
3976 save->ss.limit, save->ss.base);
3977 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3979 save->ds.selector, save->ds.attrib,
3980 save->ds.limit, save->ds.base);
3981 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3983 save->fs.selector, save->fs.attrib,
3984 save->fs.limit, save->fs.base);
3985 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3987 save->gs.selector, save->gs.attrib,
3988 save->gs.limit, save->gs.base);
3989 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3991 save->gdtr.selector, save->gdtr.attrib,
3992 save->gdtr.limit, save->gdtr.base);
3993 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3995 save->ldtr.selector, save->ldtr.attrib,
3996 save->ldtr.limit, save->ldtr.base);
3997 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3999 save->idtr.selector, save->idtr.attrib,
4000 save->idtr.limit, save->idtr.base);
4001 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4003 save->tr.selector, save->tr.attrib,
4004 save->tr.limit, save->tr.base);
4005 pr_err("cpl: %d efer: %016llx\n",
4006 save->cpl, save->efer);
4007 pr_err("%-15s %016llx %-13s %016llx\n",
4008 "cr0:", save->cr0, "cr2:", save->cr2);
4009 pr_err("%-15s %016llx %-13s %016llx\n",
4010 "cr3:", save->cr3, "cr4:", save->cr4);
4011 pr_err("%-15s %016llx %-13s %016llx\n",
4012 "dr6:", save->dr6, "dr7:", save->dr7);
4013 pr_err("%-15s %016llx %-13s %016llx\n",
4014 "rip:", save->rip, "rflags:", save->rflags);
4015 pr_err("%-15s %016llx %-13s %016llx\n",
4016 "rsp:", save->rsp, "rax:", save->rax);
4017 pr_err("%-15s %016llx %-13s %016llx\n",
4018 "star:", save->star, "lstar:", save->lstar);
4019 pr_err("%-15s %016llx %-13s %016llx\n",
4020 "cstar:", save->cstar, "sfmask:", save->sfmask);
4021 pr_err("%-15s %016llx %-13s %016llx\n",
4022 "kernel_gs_base:", save->kernel_gs_base,
4023 "sysenter_cs:", save->sysenter_cs);
4024 pr_err("%-15s %016llx %-13s %016llx\n",
4025 "sysenter_esp:", save->sysenter_esp,
4026 "sysenter_eip:", save->sysenter_eip);
4027 pr_err("%-15s %016llx %-13s %016llx\n",
4028 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4029 pr_err("%-15s %016llx %-13s %016llx\n",
4030 "br_from:", save->br_from, "br_to:", save->br_to);
4031 pr_err("%-15s %016llx %-13s %016llx\n",
4032 "excp_from:", save->last_excp_from,
4033 "excp_to:", save->last_excp_to);
4036 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4038 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4040 *info1 = control->exit_info_1;
4041 *info2 = control->exit_info_2;
4044 static int handle_exit(struct kvm_vcpu *vcpu)
4046 struct vcpu_svm *svm = to_svm(vcpu);
4047 struct kvm_run *kvm_run = vcpu->run;
4048 u32 exit_code = svm->vmcb->control.exit_code;
4050 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4052 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4053 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4055 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4057 if (unlikely(svm->nested.exit_required)) {
4058 nested_svm_vmexit(svm);
4059 svm->nested.exit_required = false;
4064 if (is_guest_mode(vcpu)) {
4067 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4068 svm->vmcb->control.exit_info_1,
4069 svm->vmcb->control.exit_info_2,
4070 svm->vmcb->control.exit_int_info,
4071 svm->vmcb->control.exit_int_info_err,
4074 vmexit = nested_svm_exit_special(svm);
4076 if (vmexit == NESTED_EXIT_CONTINUE)
4077 vmexit = nested_svm_exit_handled(svm);
4079 if (vmexit == NESTED_EXIT_DONE)
4083 svm_complete_interrupts(svm);
4085 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4086 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4087 kvm_run->fail_entry.hardware_entry_failure_reason
4088 = svm->vmcb->control.exit_code;
4089 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4094 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4095 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4096 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4097 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4098 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4100 __func__, svm->vmcb->control.exit_int_info,
4103 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4104 || !svm_exit_handlers[exit_code]) {
4105 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4106 kvm_queue_exception(vcpu, UD_VECTOR);
4110 return svm_exit_handlers[exit_code](svm);
4113 static void reload_tss(struct kvm_vcpu *vcpu)
4115 int cpu = raw_smp_processor_id();
4117 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4118 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4122 static void pre_svm_run(struct vcpu_svm *svm)
4124 int cpu = raw_smp_processor_id();
4126 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4128 /* FIXME: handle wraparound of asid_generation */
4129 if (svm->asid_generation != sd->asid_generation)
4133 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4135 struct vcpu_svm *svm = to_svm(vcpu);
4137 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4138 vcpu->arch.hflags |= HF_NMI_MASK;
4139 set_intercept(svm, INTERCEPT_IRET);
4140 ++vcpu->stat.nmi_injections;
4143 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4145 struct vmcb_control_area *control;
4147 /* The following fields are ignored when AVIC is enabled */
4148 control = &svm->vmcb->control;
4149 control->int_vector = irq;
4150 control->int_ctl &= ~V_INTR_PRIO_MASK;
4151 control->int_ctl |= V_IRQ_MASK |
4152 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4153 mark_dirty(svm->vmcb, VMCB_INTR);
4156 static void svm_set_irq(struct kvm_vcpu *vcpu)
4158 struct vcpu_svm *svm = to_svm(vcpu);
4160 BUG_ON(!(gif_set(svm)));
4162 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4163 ++vcpu->stat.irq_injections;
4165 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4166 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4169 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4171 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4174 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4176 struct vcpu_svm *svm = to_svm(vcpu);
4178 if (svm_nested_virtualize_tpr(vcpu) ||
4179 kvm_vcpu_apicv_active(vcpu))
4182 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4188 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4191 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4196 static bool svm_get_enable_apicv(void)
4201 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4205 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
4209 /* Note: Currently only used by Hyper-V. */
4210 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4212 struct vcpu_svm *svm = to_svm(vcpu);
4213 struct vmcb *vmcb = svm->vmcb;
4218 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4219 mark_dirty(vmcb, VMCB_INTR);
4222 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4227 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4232 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4234 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4235 smp_mb__after_atomic();
4237 if (avic_vcpu_is_running(vcpu))
4238 wrmsrl(SVM_AVIC_DOORBELL,
4239 __default_cpu_present_to_apicid(vcpu->cpu));
4241 kvm_vcpu_wake_up(vcpu);
4244 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4246 struct vcpu_svm *svm = to_svm(vcpu);
4247 struct vmcb *vmcb = svm->vmcb;
4249 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4250 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4251 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4256 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4258 struct vcpu_svm *svm = to_svm(vcpu);
4260 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4263 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4265 struct vcpu_svm *svm = to_svm(vcpu);
4268 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4269 set_intercept(svm, INTERCEPT_IRET);
4271 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4272 clr_intercept(svm, INTERCEPT_IRET);
4276 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4278 struct vcpu_svm *svm = to_svm(vcpu);
4279 struct vmcb *vmcb = svm->vmcb;
4282 if (!gif_set(svm) ||
4283 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4286 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4288 if (is_guest_mode(vcpu))
4289 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4294 static void enable_irq_window(struct kvm_vcpu *vcpu)
4296 struct vcpu_svm *svm = to_svm(vcpu);
4298 if (kvm_vcpu_apicv_active(vcpu))
4302 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4303 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4304 * get that intercept, this function will be called again though and
4305 * we'll get the vintr intercept.
4307 if (gif_set(svm) && nested_svm_intr(svm)) {
4309 svm_inject_irq(svm, 0x0);
4313 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4315 struct vcpu_svm *svm = to_svm(vcpu);
4317 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4319 return; /* IRET will cause a vm exit */
4322 * Something prevents NMI from been injected. Single step over possible
4323 * problem (IRET or exception injection or interrupt shadow)
4325 svm->nmi_singlestep = true;
4326 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4329 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4334 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4336 struct vcpu_svm *svm = to_svm(vcpu);
4338 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4339 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4341 svm->asid_generation--;
4344 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4348 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4350 struct vcpu_svm *svm = to_svm(vcpu);
4352 if (svm_nested_virtualize_tpr(vcpu))
4355 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4356 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4357 kvm_set_cr8(vcpu, cr8);
4361 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4363 struct vcpu_svm *svm = to_svm(vcpu);
4366 if (svm_nested_virtualize_tpr(vcpu) ||
4367 kvm_vcpu_apicv_active(vcpu))
4370 cr8 = kvm_get_cr8(vcpu);
4371 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4372 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4375 static void svm_complete_interrupts(struct vcpu_svm *svm)
4379 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4380 unsigned int3_injected = svm->int3_injected;
4382 svm->int3_injected = 0;
4385 * If we've made progress since setting HF_IRET_MASK, we've
4386 * executed an IRET and can allow NMI injection.
4388 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4389 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4390 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4391 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4394 svm->vcpu.arch.nmi_injected = false;
4395 kvm_clear_exception_queue(&svm->vcpu);
4396 kvm_clear_interrupt_queue(&svm->vcpu);
4398 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4401 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4403 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4404 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4407 case SVM_EXITINTINFO_TYPE_NMI:
4408 svm->vcpu.arch.nmi_injected = true;
4410 case SVM_EXITINTINFO_TYPE_EXEPT:
4412 * In case of software exceptions, do not reinject the vector,
4413 * but re-execute the instruction instead. Rewind RIP first
4414 * if we emulated INT3 before.
4416 if (kvm_exception_is_soft(vector)) {
4417 if (vector == BP_VECTOR && int3_injected &&
4418 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4419 kvm_rip_write(&svm->vcpu,
4420 kvm_rip_read(&svm->vcpu) -
4424 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4425 u32 err = svm->vmcb->control.exit_int_info_err;
4426 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4429 kvm_requeue_exception(&svm->vcpu, vector);
4431 case SVM_EXITINTINFO_TYPE_INTR:
4432 kvm_queue_interrupt(&svm->vcpu, vector, false);
4439 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4441 struct vcpu_svm *svm = to_svm(vcpu);
4442 struct vmcb_control_area *control = &svm->vmcb->control;
4444 control->exit_int_info = control->event_inj;
4445 control->exit_int_info_err = control->event_inj_err;
4446 control->event_inj = 0;
4447 svm_complete_interrupts(svm);
4450 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4452 struct vcpu_svm *svm = to_svm(vcpu);
4454 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4455 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4456 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4459 * A vmexit emulation is required before the vcpu can be executed
4462 if (unlikely(svm->nested.exit_required))
4467 sync_lapic_to_cr8(vcpu);
4469 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4476 "push %%" _ASM_BP "; \n\t"
4477 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4478 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4479 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4480 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4481 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4482 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4483 #ifdef CONFIG_X86_64
4484 "mov %c[r8](%[svm]), %%r8 \n\t"
4485 "mov %c[r9](%[svm]), %%r9 \n\t"
4486 "mov %c[r10](%[svm]), %%r10 \n\t"
4487 "mov %c[r11](%[svm]), %%r11 \n\t"
4488 "mov %c[r12](%[svm]), %%r12 \n\t"
4489 "mov %c[r13](%[svm]), %%r13 \n\t"
4490 "mov %c[r14](%[svm]), %%r14 \n\t"
4491 "mov %c[r15](%[svm]), %%r15 \n\t"
4494 /* Enter guest mode */
4495 "push %%" _ASM_AX " \n\t"
4496 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4497 __ex(SVM_VMLOAD) "\n\t"
4498 __ex(SVM_VMRUN) "\n\t"
4499 __ex(SVM_VMSAVE) "\n\t"
4500 "pop %%" _ASM_AX " \n\t"
4502 /* Save guest registers, load host registers */
4503 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4504 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4505 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4506 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4507 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4508 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4509 #ifdef CONFIG_X86_64
4510 "mov %%r8, %c[r8](%[svm]) \n\t"
4511 "mov %%r9, %c[r9](%[svm]) \n\t"
4512 "mov %%r10, %c[r10](%[svm]) \n\t"
4513 "mov %%r11, %c[r11](%[svm]) \n\t"
4514 "mov %%r12, %c[r12](%[svm]) \n\t"
4515 "mov %%r13, %c[r13](%[svm]) \n\t"
4516 "mov %%r14, %c[r14](%[svm]) \n\t"
4517 "mov %%r15, %c[r15](%[svm]) \n\t"
4522 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4523 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4524 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4525 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4526 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4527 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4528 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4529 #ifdef CONFIG_X86_64
4530 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4531 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4532 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4533 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4534 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4535 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4536 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4537 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4540 #ifdef CONFIG_X86_64
4541 , "rbx", "rcx", "rdx", "rsi", "rdi"
4542 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4544 , "ebx", "ecx", "edx", "esi", "edi"
4548 #ifdef CONFIG_X86_64
4549 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4551 loadsegment(fs, svm->host.fs);
4552 #ifndef CONFIG_X86_32_LAZY_GS
4553 loadsegment(gs, svm->host.gs);
4559 local_irq_disable();
4561 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4562 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4563 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4564 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4566 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4567 kvm_before_handle_nmi(&svm->vcpu);
4571 /* Any pending NMI will happen here */
4573 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4574 kvm_after_handle_nmi(&svm->vcpu);
4576 sync_cr8_to_lapic(vcpu);
4580 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4582 /* if exit due to PF check for async PF */
4583 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4584 svm->apf_reason = kvm_read_and_reset_pf_reason();
4587 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4588 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4592 * We need to handle MC intercepts here before the vcpu has a chance to
4593 * change the physical cpu
4595 if (unlikely(svm->vmcb->control.exit_code ==
4596 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4597 svm_handle_mce(svm);
4599 mark_all_clean(svm->vmcb);
4602 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4604 struct vcpu_svm *svm = to_svm(vcpu);
4606 svm->vmcb->save.cr3 = root;
4607 mark_dirty(svm->vmcb, VMCB_CR);
4608 svm_flush_tlb(vcpu);
4611 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4613 struct vcpu_svm *svm = to_svm(vcpu);
4615 svm->vmcb->control.nested_cr3 = root;
4616 mark_dirty(svm->vmcb, VMCB_NPT);
4618 /* Also sync guest cr3 here in case we live migrate */
4619 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4620 mark_dirty(svm->vmcb, VMCB_CR);
4622 svm_flush_tlb(vcpu);
4625 static int is_disabled(void)
4629 rdmsrl(MSR_VM_CR, vm_cr);
4630 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4637 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4640 * Patch in the VMMCALL instruction:
4642 hypercall[0] = 0x0f;
4643 hypercall[1] = 0x01;
4644 hypercall[2] = 0xd9;
4647 static void svm_check_processor_compat(void *rtn)
4652 static bool svm_cpu_has_accelerated_tpr(void)
4657 static bool svm_has_high_real_mode_segbase(void)
4662 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4667 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4669 struct vcpu_svm *svm = to_svm(vcpu);
4670 struct kvm_cpuid_entry2 *entry;
4672 /* Update nrips enabled cache */
4673 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4675 if (!kvm_vcpu_apicv_active(vcpu))
4678 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
4680 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4683 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4688 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
4692 entry->ecx |= (1 << 2); /* Set SVM bit */
4695 entry->eax = 1; /* SVM revision 1 */
4696 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4697 ASID emulation to nested SVM */
4698 entry->ecx = 0; /* Reserved */
4699 entry->edx = 0; /* Per default do not support any
4700 additional features */
4702 /* Support next_rip if host supports it */
4703 if (boot_cpu_has(X86_FEATURE_NRIPS))
4704 entry->edx |= SVM_FEATURE_NRIP;
4706 /* Support NPT for the guest if enabled */
4708 entry->edx |= SVM_FEATURE_NPT;
4714 static int svm_get_lpage_level(void)
4716 return PT_PDPE_LEVEL;
4719 static bool svm_rdtscp_supported(void)
4721 return boot_cpu_has(X86_FEATURE_RDTSCP);
4724 static bool svm_invpcid_supported(void)
4729 static bool svm_mpx_supported(void)
4734 static bool svm_xsaves_supported(void)
4739 static bool svm_has_wbinvd_exit(void)
4744 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4746 struct vcpu_svm *svm = to_svm(vcpu);
4748 set_exception_intercept(svm, NM_VECTOR);
4749 update_cr0_intercept(svm);
4752 #define PRE_EX(exit) { .exit_code = (exit), \
4753 .stage = X86_ICPT_PRE_EXCEPT, }
4754 #define POST_EX(exit) { .exit_code = (exit), \
4755 .stage = X86_ICPT_POST_EXCEPT, }
4756 #define POST_MEM(exit) { .exit_code = (exit), \
4757 .stage = X86_ICPT_POST_MEMACCESS, }
4759 static const struct __x86_intercept {
4761 enum x86_intercept_stage stage;
4762 } x86_intercept_map[] = {
4763 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4764 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4765 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4766 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4767 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4768 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4769 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4770 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4771 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4772 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4773 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4774 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4775 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4776 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4777 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4778 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4779 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4780 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4781 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4782 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4783 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4784 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4785 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4786 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4787 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4788 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4789 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4790 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4791 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4792 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4793 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4794 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4795 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4796 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4797 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4798 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4799 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4800 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4801 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4802 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4803 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4804 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4805 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4806 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4807 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4808 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4815 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4816 struct x86_instruction_info *info,
4817 enum x86_intercept_stage stage)
4819 struct vcpu_svm *svm = to_svm(vcpu);
4820 int vmexit, ret = X86EMUL_CONTINUE;
4821 struct __x86_intercept icpt_info;
4822 struct vmcb *vmcb = svm->vmcb;
4824 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4827 icpt_info = x86_intercept_map[info->intercept];
4829 if (stage != icpt_info.stage)
4832 switch (icpt_info.exit_code) {
4833 case SVM_EXIT_READ_CR0:
4834 if (info->intercept == x86_intercept_cr_read)
4835 icpt_info.exit_code += info->modrm_reg;
4837 case SVM_EXIT_WRITE_CR0: {
4838 unsigned long cr0, val;
4841 if (info->intercept == x86_intercept_cr_write)
4842 icpt_info.exit_code += info->modrm_reg;
4844 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4845 info->intercept == x86_intercept_clts)
4848 intercept = svm->nested.intercept;
4850 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4853 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4854 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4856 if (info->intercept == x86_intercept_lmsw) {
4859 /* lmsw can't clear PE - catch this here */
4860 if (cr0 & X86_CR0_PE)
4865 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4869 case SVM_EXIT_READ_DR0:
4870 case SVM_EXIT_WRITE_DR0:
4871 icpt_info.exit_code += info->modrm_reg;
4874 if (info->intercept == x86_intercept_wrmsr)
4875 vmcb->control.exit_info_1 = 1;
4877 vmcb->control.exit_info_1 = 0;
4879 case SVM_EXIT_PAUSE:
4881 * We get this for NOP only, but pause
4882 * is rep not, check this here
4884 if (info->rep_prefix != REPE_PREFIX)
4886 case SVM_EXIT_IOIO: {
4890 if (info->intercept == x86_intercept_in ||
4891 info->intercept == x86_intercept_ins) {
4892 exit_info = ((info->src_val & 0xffff) << 16) |
4894 bytes = info->dst_bytes;
4896 exit_info = (info->dst_val & 0xffff) << 16;
4897 bytes = info->src_bytes;
4900 if (info->intercept == x86_intercept_outs ||
4901 info->intercept == x86_intercept_ins)
4902 exit_info |= SVM_IOIO_STR_MASK;
4904 if (info->rep_prefix)
4905 exit_info |= SVM_IOIO_REP_MASK;
4907 bytes = min(bytes, 4u);
4909 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4911 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4913 vmcb->control.exit_info_1 = exit_info;
4914 vmcb->control.exit_info_2 = info->next_rip;
4922 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4923 if (static_cpu_has(X86_FEATURE_NRIPS))
4924 vmcb->control.next_rip = info->next_rip;
4925 vmcb->control.exit_code = icpt_info.exit_code;
4926 vmexit = nested_svm_exit_handled(svm);
4928 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4935 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4940 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4944 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
4946 if (avic_handle_apic_id_update(vcpu) != 0)
4948 if (avic_handle_dfr_update(vcpu) != 0)
4950 avic_handle_ldr_update(vcpu);
4953 static struct kvm_x86_ops svm_x86_ops = {
4954 .cpu_has_kvm_support = has_svm,
4955 .disabled_by_bios = is_disabled,
4956 .hardware_setup = svm_hardware_setup,
4957 .hardware_unsetup = svm_hardware_unsetup,
4958 .check_processor_compatibility = svm_check_processor_compat,
4959 .hardware_enable = svm_hardware_enable,
4960 .hardware_disable = svm_hardware_disable,
4961 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4962 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4964 .vcpu_create = svm_create_vcpu,
4965 .vcpu_free = svm_free_vcpu,
4966 .vcpu_reset = svm_vcpu_reset,
4968 .vm_init = avic_vm_init,
4969 .vm_destroy = avic_vm_destroy,
4971 .prepare_guest_switch = svm_prepare_guest_switch,
4972 .vcpu_load = svm_vcpu_load,
4973 .vcpu_put = svm_vcpu_put,
4974 .vcpu_blocking = svm_vcpu_blocking,
4975 .vcpu_unblocking = svm_vcpu_unblocking,
4977 .update_bp_intercept = update_bp_intercept,
4978 .get_msr = svm_get_msr,
4979 .set_msr = svm_set_msr,
4980 .get_segment_base = svm_get_segment_base,
4981 .get_segment = svm_get_segment,
4982 .set_segment = svm_set_segment,
4983 .get_cpl = svm_get_cpl,
4984 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4985 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4986 .decache_cr3 = svm_decache_cr3,
4987 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4988 .set_cr0 = svm_set_cr0,
4989 .set_cr3 = svm_set_cr3,
4990 .set_cr4 = svm_set_cr4,
4991 .set_efer = svm_set_efer,
4992 .get_idt = svm_get_idt,
4993 .set_idt = svm_set_idt,
4994 .get_gdt = svm_get_gdt,
4995 .set_gdt = svm_set_gdt,
4996 .get_dr6 = svm_get_dr6,
4997 .set_dr6 = svm_set_dr6,
4998 .set_dr7 = svm_set_dr7,
4999 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5000 .cache_reg = svm_cache_reg,
5001 .get_rflags = svm_get_rflags,
5002 .set_rflags = svm_set_rflags,
5004 .get_pkru = svm_get_pkru,
5006 .fpu_activate = svm_fpu_activate,
5007 .fpu_deactivate = svm_fpu_deactivate,
5009 .tlb_flush = svm_flush_tlb,
5011 .run = svm_vcpu_run,
5012 .handle_exit = handle_exit,
5013 .skip_emulated_instruction = skip_emulated_instruction,
5014 .set_interrupt_shadow = svm_set_interrupt_shadow,
5015 .get_interrupt_shadow = svm_get_interrupt_shadow,
5016 .patch_hypercall = svm_patch_hypercall,
5017 .set_irq = svm_set_irq,
5018 .set_nmi = svm_inject_nmi,
5019 .queue_exception = svm_queue_exception,
5020 .cancel_injection = svm_cancel_injection,
5021 .interrupt_allowed = svm_interrupt_allowed,
5022 .nmi_allowed = svm_nmi_allowed,
5023 .get_nmi_mask = svm_get_nmi_mask,
5024 .set_nmi_mask = svm_set_nmi_mask,
5025 .enable_nmi_window = enable_nmi_window,
5026 .enable_irq_window = enable_irq_window,
5027 .update_cr8_intercept = update_cr8_intercept,
5028 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5029 .get_enable_apicv = svm_get_enable_apicv,
5030 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5031 .load_eoi_exitmap = svm_load_eoi_exitmap,
5032 .sync_pir_to_irr = svm_sync_pir_to_irr,
5033 .hwapic_irr_update = svm_hwapic_irr_update,
5034 .hwapic_isr_update = svm_hwapic_isr_update,
5035 .apicv_post_state_restore = avic_post_state_restore,
5037 .set_tss_addr = svm_set_tss_addr,
5038 .get_tdp_level = get_npt_level,
5039 .get_mt_mask = svm_get_mt_mask,
5041 .get_exit_info = svm_get_exit_info,
5043 .get_lpage_level = svm_get_lpage_level,
5045 .cpuid_update = svm_cpuid_update,
5047 .rdtscp_supported = svm_rdtscp_supported,
5048 .invpcid_supported = svm_invpcid_supported,
5049 .mpx_supported = svm_mpx_supported,
5050 .xsaves_supported = svm_xsaves_supported,
5052 .set_supported_cpuid = svm_set_supported_cpuid,
5054 .has_wbinvd_exit = svm_has_wbinvd_exit,
5056 .read_tsc_offset = svm_read_tsc_offset,
5057 .write_tsc_offset = svm_write_tsc_offset,
5058 .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest,
5059 .read_l1_tsc = svm_read_l1_tsc,
5061 .set_tdp_cr3 = set_tdp_cr3,
5063 .check_intercept = svm_check_intercept,
5064 .handle_external_intr = svm_handle_external_intr,
5066 .sched_in = svm_sched_in,
5068 .pmu_ops = &amd_pmu_ops,
5069 .deliver_posted_interrupt = svm_deliver_avic_intr,
5072 static int __init svm_init(void)
5074 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5075 __alignof__(struct vcpu_svm), THIS_MODULE);
5078 static void __exit svm_exit(void)
5083 module_init(svm_init)
5084 module_exit(svm_exit)