arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         struct page *avic_logical_id_table_page;
 149         struct page *avic_physical_id_table_page;
 150         struct hlist_node hnode;
 151
 152         struct kvm_sev_info sev_info;
 153 };
 154
 155 struct kvm_vcpu;
 156
 157 struct nested_state {
 158         struct vmcb *hsave;
 159         u64 hsave_msr;
 160         u64 vm_cr_msr;
 161         u64 vmcb;
 162
 163         /* These are the merged vectors */
 164         u32 *msrpm;
 165
 166         /* gpa pointers to the real vectors */
 167         u64 vmcb_msrpm;
 168         u64 vmcb_iopm;
 169
 170         /* A VMEXIT is required but not yet emulated */
 171         bool exit_required;
 172
 173         /* cache for intercepts of the guest */
 174         u32 intercept_cr;
 175         u32 intercept_dr;
 176         u32 intercept_exceptions;
 177         u64 intercept;
 178
 179         /* Nested Paging related state */
 180         u64 nested_cr3;
 181 };
 182
 183 #define MSRPM_OFFSETS   16
 184 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 185
 186 /*
 187  * Set osvw_len to higher value when updated Revision Guides
 188  * are published and we know what the new status bits are
 189  */
 190 static uint64_t osvw_len = 4, osvw_status;
 191
 192 struct vcpu_svm {
 193         struct kvm_vcpu vcpu;
 194         struct vmcb *vmcb;
 195         unsigned long vmcb_pa;
 196         struct svm_cpu_data *svm_data;
 197         uint64_t asid_generation;
 198         uint64_t sysenter_esp;
 199         uint64_t sysenter_eip;
 200         uint64_t tsc_aux;
 201
 202         u64 msr_decfg;
 203
 204         u64 next_rip;
 205
 206         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 207         struct {
 208                 u16 fs;
 209                 u16 gs;
 210                 u16 ldt;
 211                 u64 gs_base;
 212         } host;
 213
 214         u64 spec_ctrl;
 215         /*
 216          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 217          * translated into the appropriate L2_CFG bits on the host to
 218          * perform speculative control.
 219          */
 220         u64 virt_spec_ctrl;
 221
 222         u32 *msrpm;
 223
 224         ulong nmi_iret_rip;
 225
 226         struct nested_state nested;
 227
 228         bool nmi_singlestep;
 229         u64 nmi_singlestep_guest_rflags;
 230
 231         unsigned int3_injected;
 232         unsigned long int3_rip;
 233
 234         /* cached guest cpuid flags for faster access */
 235         bool nrips_enabled      : 1;
 236
 237         u32 ldr_reg;
 238         u32 dfr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT                 31
 266 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 267
 268 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 269 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 270 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 271 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 272
 273 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 274 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 275
 276 #define MSR_INVALID                     0xffffffffU
 277
 278 static const struct svm_direct_access_msrs {
 279         u32 index;   /* Index of the MSR */
 280         bool always; /* True if intercept is always on */
 281 } direct_access_msrs[] = {
 282         { .index = MSR_STAR,                            .always = true  },
 283         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 284 #ifdef CONFIG_X86_64
 285         { .index = MSR_GS_BASE,                         .always = true  },
 286         { .index = MSR_FS_BASE,                         .always = true  },
 287         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 288         { .index = MSR_LSTAR,                           .always = true  },
 289         { .index = MSR_CSTAR,                           .always = true  },
 290         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 291 #endif
 292         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 293         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 294         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 295         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 296         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 297         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 298         { .index = MSR_INVALID,                         .always = false },
 299 };
 300
 301 /* enable NPT for AMD64 and X86 with PAE */
 302 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 303 static bool npt_enabled = true;
 304 #else
 305 static bool npt_enabled;
 306 #endif
 307
 308 /*
 309  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 310  * pause_filter_count: On processors that support Pause filtering(indicated
 311  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 312  *      count value. On VMRUN this value is loaded into an internal counter.
 313  *      Each time a pause instruction is executed, this counter is decremented
 314  *      until it reaches zero at which time a #VMEXIT is generated if pause
 315  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 316  *      Intercept Filtering for more details.
 317  *      This also indicate if ple logic enabled.
 318  *
 319  * pause_filter_thresh: In addition, some processor families support advanced
 320  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 321  *      the amount of time a guest is allowed to execute in a pause loop.
 322  *      In this mode, a 16-bit pause filter threshold field is added in the
 323  *      VMCB. The threshold value is a cycle count that is used to reset the
 324  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 325  *      count value from VMCB into an internal counter. Then, on each pause
 326  *      instruction the hardware checks the elapsed number of cycles since
 327  *      the most recent pause instruction against the pause filter threshold.
 328  *      If the elapsed cycle count is greater than the pause filter threshold,
 329  *      then the internal pause count is reloaded from the VMCB and execution
 330  *      continues. If the elapsed cycle count is less than the pause filter
 331  *      threshold, then the internal pause count is decremented. If the count
 332  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 333  *      triggered. If advanced pause filtering is supported and pause filter
 334  *      threshold field is set to zero, the filter will operate in the simpler,
 335  *      count only mode.
 336  */
 337
 338 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 339 module_param(pause_filter_thresh, ushort, 0444);
 340
 341 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 342 module_param(pause_filter_count, ushort, 0444);
 343
 344 /* Default doubles per-vcpu window every exit. */
 345 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 346 module_param(pause_filter_count_grow, ushort, 0444);
 347
 348 /* Default resets per-vcpu window every exit to pause_filter_count. */
 349 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 350 module_param(pause_filter_count_shrink, ushort, 0444);
 351
 352 /* Default is to compute the maximum so we can never overflow. */
 353 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 354 module_param(pause_filter_count_max, ushort, 0444);
 355
 356 /* allow nested paging (virtualized MMU) for all guests */
 357 static int npt = true;
 358 module_param(npt, int, S_IRUGO);
 359
 360 /* allow nested virtualization in KVM/SVM */
 361 static int nested = true;
 362 module_param(nested, int, S_IRUGO);
 363
 364 /* enable / disable AVIC */
 365 static int avic;
 366 #ifdef CONFIG_X86_LOCAL_APIC
 367 module_param(avic, int, S_IRUGO);
 368 #endif
 369
 370 /* enable/disable Virtual VMLOAD VMSAVE */
 371 static int vls = true;
 372 module_param(vls, int, 0444);
 373
 374 /* enable/disable Virtual GIF */
 375 static int vgif = true;
 376 module_param(vgif, int, 0444);
 377
 378 /* enable/disable SEV support */
 379 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 380 module_param(sev, int, 0444);
 381
 382 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 383
 384 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 385 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 386 static void svm_complete_interrupts(struct vcpu_svm *svm);
 387
 388 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 389 static int nested_svm_intercept(struct vcpu_svm *svm);
 390 static int nested_svm_vmexit(struct vcpu_svm *svm);
 391 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 392                                       bool has_error_code, u32 error_code);
 393
 394 enum {
 395         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 396                             pause filter count */
 397         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 398         VMCB_ASID,       /* ASID */
 399         VMCB_INTR,       /* int_ctl, int_vector */
 400         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 401         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 402         VMCB_DR,         /* DR6, DR7 */
 403         VMCB_DT,         /* GDT, IDT */
 404         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 405         VMCB_CR2,        /* CR2 only */
 406         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 407         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 408                           * AVIC PHYSICAL_TABLE pointer,
 409                           * AVIC LOGICAL_TABLE pointer
 410                           */
 411         VMCB_DIRTY_MAX,
 412 };
 413
 414 /* TPR and CR2 are always written before VMRUN */
 415 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 416
 417 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 418
 419 static unsigned int max_sev_asid;
 420 static unsigned int min_sev_asid;
 421 static unsigned long *sev_asid_bitmap;
 422 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 423
 424 struct enc_region {
 425         struct list_head list;
 426         unsigned long npages;
 427         struct page **pages;
 428         unsigned long uaddr;
 429         unsigned long size;
 430 };
 431
 432
 433 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 434 {
 435         return container_of(kvm, struct kvm_svm, kvm);
 436 }
 437
 438 static inline bool svm_sev_enabled(void)
 439 {
 440         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 441 }
 442
 443 static inline bool sev_guest(struct kvm *kvm)
 444 {
 445 #ifdef CONFIG_KVM_AMD_SEV
 446         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 447
 448         return sev->active;
 449 #else
 450         return false;
 451 #endif
 452 }
 453
 454 static inline int sev_get_asid(struct kvm *kvm)
 455 {
 456         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 457
 458         return sev->asid;
 459 }
 460
 461 static inline void mark_all_dirty(struct vmcb *vmcb)
 462 {
 463         vmcb->control.clean = 0;
 464 }
 465
 466 static inline void mark_all_clean(struct vmcb *vmcb)
 467 {
 468         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 469                                & ~VMCB_ALWAYS_DIRTY_MASK;
 470 }
 471
 472 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 473 {
 474         vmcb->control.clean &= ~(1 << bit);
 475 }
 476
 477 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 478 {
 479         return container_of(vcpu, struct vcpu_svm, vcpu);
 480 }
 481
 482 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 483 {
 484         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 485         mark_dirty(svm->vmcb, VMCB_AVIC);
 486 }
 487
 488 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 489 {
 490         struct vcpu_svm *svm = to_svm(vcpu);
 491         u64 *entry = svm->avic_physical_id_cache;
 492
 493         if (!entry)
 494                 return false;
 495
 496         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 497 }
 498
 499 static void recalc_intercepts(struct vcpu_svm *svm)
 500 {
 501         struct vmcb_control_area *c, *h;
 502         struct nested_state *g;
 503
 504         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 505
 506         if (!is_guest_mode(&svm->vcpu))
 507                 return;
 508
 509         c = &svm->vmcb->control;
 510         h = &svm->nested.hsave->control;
 511         g = &svm->nested;
 512
 513         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 514         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 515         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 516         c->intercept = h->intercept | g->intercept;
 517 }
 518
 519 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 520 {
 521         if (is_guest_mode(&svm->vcpu))
 522                 return svm->nested.hsave;
 523         else
 524                 return svm->vmcb;
 525 }
 526
 527 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 528 {
 529         struct vmcb *vmcb = get_host_vmcb(svm);
 530
 531         vmcb->control.intercept_cr |= (1U << bit);
 532
 533         recalc_intercepts(svm);
 534 }
 535
 536 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 537 {
 538         struct vmcb *vmcb = get_host_vmcb(svm);
 539
 540         vmcb->control.intercept_cr &= ~(1U << bit);
 541
 542         recalc_intercepts(svm);
 543 }
 544
 545 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 546 {
 547         struct vmcb *vmcb = get_host_vmcb(svm);
 548
 549         return vmcb->control.intercept_cr & (1U << bit);
 550 }
 551
 552 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 553 {
 554         struct vmcb *vmcb = get_host_vmcb(svm);
 555
 556         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 557                 | (1 << INTERCEPT_DR1_READ)
 558                 | (1 << INTERCEPT_DR2_READ)
 559                 | (1 << INTERCEPT_DR3_READ)
 560                 | (1 << INTERCEPT_DR4_READ)
 561                 | (1 << INTERCEPT_DR5_READ)
 562                 | (1 << INTERCEPT_DR6_READ)
 563                 | (1 << INTERCEPT_DR7_READ)
 564                 | (1 << INTERCEPT_DR0_WRITE)
 565                 | (1 << INTERCEPT_DR1_WRITE)
 566                 | (1 << INTERCEPT_DR2_WRITE)
 567                 | (1 << INTERCEPT_DR3_WRITE)
 568                 | (1 << INTERCEPT_DR4_WRITE)
 569                 | (1 << INTERCEPT_DR5_WRITE)
 570                 | (1 << INTERCEPT_DR6_WRITE)
 571                 | (1 << INTERCEPT_DR7_WRITE);
 572
 573         recalc_intercepts(svm);
 574 }
 575
 576 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 577 {
 578         struct vmcb *vmcb = get_host_vmcb(svm);
 579
 580         vmcb->control.intercept_dr = 0;
 581
 582         recalc_intercepts(svm);
 583 }
 584
 585 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 586 {
 587         struct vmcb *vmcb = get_host_vmcb(svm);
 588
 589         vmcb->control.intercept_exceptions |= (1U << bit);
 590
 591         recalc_intercepts(svm);
 592 }
 593
 594 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 595 {
 596         struct vmcb *vmcb = get_host_vmcb(svm);
 597
 598         vmcb->control.intercept_exceptions &= ~(1U << bit);
 599
 600         recalc_intercepts(svm);
 601 }
 602
 603 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 604 {
 605         struct vmcb *vmcb = get_host_vmcb(svm);
 606
 607         vmcb->control.intercept |= (1ULL << bit);
 608
 609         recalc_intercepts(svm);
 610 }
 611
 612 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 613 {
 614         struct vmcb *vmcb = get_host_vmcb(svm);
 615
 616         vmcb->control.intercept &= ~(1ULL << bit);
 617
 618         recalc_intercepts(svm);
 619 }
 620
 621 static inline bool vgif_enabled(struct vcpu_svm *svm)
 622 {
 623         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 624 }
 625
 626 static inline void enable_gif(struct vcpu_svm *svm)
 627 {
 628         if (vgif_enabled(svm))
 629                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 630         else
 631                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 632 }
 633
 634 static inline void disable_gif(struct vcpu_svm *svm)
 635 {
 636         if (vgif_enabled(svm))
 637                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 638         else
 639                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 640 }
 641
 642 static inline bool gif_set(struct vcpu_svm *svm)
 643 {
 644         if (vgif_enabled(svm))
 645                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 646         else
 647                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 648 }
 649
 650 static unsigned long iopm_base;
 651
 652 struct kvm_ldttss_desc {
 653         u16 limit0;
 654         u16 base0;
 655         unsigned base1:8, type:5, dpl:2, p:1;
 656         unsigned limit1:4, zero0:3, g:1, base2:8;
 657         u32 base3;
 658         u32 zero1;
 659 } __attribute__((packed));
 660
 661 struct svm_cpu_data {
 662         int cpu;
 663
 664         u64 asid_generation;
 665         u32 max_asid;
 666         u32 next_asid;
 667         u32 min_asid;
 668         struct kvm_ldttss_desc *tss_desc;
 669
 670         struct page *save_area;
 671         struct vmcb *current_vmcb;
 672
 673         /* index = sev_asid, value = vmcb pointer */
 674         struct vmcb **sev_vmcbs;
 675 };
 676
 677 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 678
 679 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 680
 681 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 682 #define MSRS_RANGE_SIZE 2048
 683 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 684
 685 static u32 svm_msrpm_offset(u32 msr)
 686 {
 687         u32 offset;
 688         int i;
 689
 690         for (i = 0; i < NUM_MSR_MAPS; i++) {
 691                 if (msr < msrpm_ranges[i] ||
 692                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 693                         continue;
 694
 695                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 696                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 697
 698                 /* Now we have the u8 offset - but need the u32 offset */
 699                 return offset / 4;
 700         }
 701
 702         /* MSR not in any range */
 703         return MSR_INVALID;
 704 }
 705
 706 #define MAX_INST_SIZE 15
 707
 708 static inline void clgi(void)
 709 {
 710         asm volatile (__ex("clgi"));
 711 }
 712
 713 static inline void stgi(void)
 714 {
 715         asm volatile (__ex("stgi"));
 716 }
 717
 718 static inline void invlpga(unsigned long addr, u32 asid)
 719 {
 720         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 721 }
 722
 723 static int get_npt_level(struct kvm_vcpu *vcpu)
 724 {
 725 #ifdef CONFIG_X86_64
 726         return PT64_ROOT_4LEVEL;
 727 #else
 728         return PT32E_ROOT_LEVEL;
 729 #endif
 730 }
 731
 732 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 733 {
 734         vcpu->arch.efer = efer;
 735         if (!npt_enabled && !(efer & EFER_LMA))
 736                 efer &= ~EFER_LME;
 737
 738         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 739         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 740 }
 741
 742 static int is_external_interrupt(u32 info)
 743 {
 744         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 745         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 746 }
 747
 748 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 749 {
 750         struct vcpu_svm *svm = to_svm(vcpu);
 751         u32 ret = 0;
 752
 753         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 754                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 755         return ret;
 756 }
 757
 758 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 759 {
 760         struct vcpu_svm *svm = to_svm(vcpu);
 761
 762         if (mask == 0)
 763                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 764         else
 765                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 766
 767 }
 768
 769 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 770 {
 771         struct vcpu_svm *svm = to_svm(vcpu);
 772
 773         if (svm->vmcb->control.next_rip != 0) {
 774                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 775                 svm->next_rip = svm->vmcb->control.next_rip;
 776         }
 777
 778         if (!svm->next_rip) {
 779                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 780                                 EMULATE_DONE)
 781                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 782                 return;
 783         }
 784         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 785                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 786                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 787
 788         kvm_rip_write(vcpu, svm->next_rip);
 789         svm_set_interrupt_shadow(vcpu, 0);
 790 }
 791
 792 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 793 {
 794         struct vcpu_svm *svm = to_svm(vcpu);
 795         unsigned nr = vcpu->arch.exception.nr;
 796         bool has_error_code = vcpu->arch.exception.has_error_code;
 797         bool reinject = vcpu->arch.exception.injected;
 798         u32 error_code = vcpu->arch.exception.error_code;
 799
 800         /*
 801          * If we are within a nested VM we'd better #VMEXIT and let the guest
 802          * handle the exception
 803          */
 804         if (!reinject &&
 805             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 806                 return;
 807
 808         kvm_deliver_exception_payload(&svm->vcpu);
 809
 810         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 811                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 812
 813                 /*
 814                  * For guest debugging where we have to reinject #BP if some
 815                  * INT3 is guest-owned:
 816                  * Emulate nRIP by moving RIP forward. Will fail if injection
 817                  * raises a fault that is not intercepted. Still better than
 818                  * failing in all cases.
 819                  */
 820                 skip_emulated_instruction(&svm->vcpu);
 821                 rip = kvm_rip_read(&svm->vcpu);
 822                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 823                 svm->int3_injected = rip - old_rip;
 824         }
 825
 826         svm->vmcb->control.event_inj = nr
 827                 | SVM_EVTINJ_VALID
 828                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 829                 | SVM_EVTINJ_TYPE_EXEPT;
 830         svm->vmcb->control.event_inj_err = error_code;
 831 }
 832
 833 static void svm_init_erratum_383(void)
 834 {
 835         u32 low, high;
 836         int err;
 837         u64 val;
 838
 839         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 840                 return;
 841
 842         /* Use _safe variants to not break nested virtualization */
 843         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 844         if (err)
 845                 return;
 846
 847         val |= (1ULL << 47);
 848
 849         low  = lower_32_bits(val);
 850         high = upper_32_bits(val);
 851
 852         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 853
 854         erratum_383_found = true;
 855 }
 856
 857 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 858 {
 859         /*
 860          * Guests should see errata 400 and 415 as fixed (assuming that
 861          * HLT and IO instructions are intercepted).
 862          */
 863         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 864         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 865
 866         /*
 867          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 868          * all osvw.status bits inside that length, including bit 0 (which is
 869          * reserved for erratum 298), are valid. However, if host processor's
 870          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 871          * be conservative here and therefore we tell the guest that erratum 298
 872          * is present (because we really don't know).
 873          */
 874         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 875                 vcpu->arch.osvw.status |= 1;
 876 }
 877
 878 static int has_svm(void)
 879 {
 880         const char *msg;
 881
 882         if (!cpu_has_svm(&msg)) {
 883                 printk(KERN_INFO "has_svm: %s\n", msg);
 884                 return 0;
 885         }
 886
 887         return 1;
 888 }
 889
 890 static void svm_hardware_disable(void)
 891 {
 892         /* Make sure we clean up behind us */
 893         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 894                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 895
 896         cpu_svm_disable();
 897
 898         amd_pmu_disable_virt();
 899 }
 900
 901 static int svm_hardware_enable(void)
 902 {
 903
 904         struct svm_cpu_data *sd;
 905         uint64_t efer;
 906         struct desc_struct *gdt;
 907         int me = raw_smp_processor_id();
 908
 909         rdmsrl(MSR_EFER, efer);
 910         if (efer & EFER_SVME)
 911                 return -EBUSY;
 912
 913         if (!has_svm()) {
 914                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 915                 return -EINVAL;
 916         }
 917         sd = per_cpu(svm_data, me);
 918         if (!sd) {
 919                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 920                 return -EINVAL;
 921         }
 922
 923         sd->asid_generation = 1;
 924         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 925         sd->next_asid = sd->max_asid + 1;
 926         sd->min_asid = max_sev_asid + 1;
 927
 928         gdt = get_current_gdt_rw();
 929         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 930
 931         wrmsrl(MSR_EFER, efer | EFER_SVME);
 932
 933         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 934
 935         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 936                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 937                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 938         }
 939
 940
 941         /*
 942          * Get OSVW bits.
 943          *
 944          * Note that it is possible to have a system with mixed processor
 945          * revisions and therefore different OSVW bits. If bits are not the same
 946          * on different processors then choose the worst case (i.e. if erratum
 947          * is present on one processor and not on another then assume that the
 948          * erratum is present everywhere).
 949          */
 950         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 951                 uint64_t len, status = 0;
 952                 int err;
 953
 954                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 955                 if (!err)
 956                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 957                                                       &err);
 958
 959                 if (err)
 960                         osvw_status = osvw_len = 0;
 961                 else {
 962                         if (len < osvw_len)
 963                                 osvw_len = len;
 964                         osvw_status |= status;
 965                         osvw_status &= (1ULL << osvw_len) - 1;
 966                 }
 967         } else
 968                 osvw_status = osvw_len = 0;
 969
 970         svm_init_erratum_383();
 971
 972         amd_pmu_enable_virt();
 973
 974         return 0;
 975 }
 976
 977 static void svm_cpu_uninit(int cpu)
 978 {
 979         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 980
 981         if (!sd)
 982                 return;
 983
 984         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 985         kfree(sd->sev_vmcbs);
 986         __free_page(sd->save_area);
 987         kfree(sd);
 988 }
 989
 990 static int svm_cpu_init(int cpu)
 991 {
 992         struct svm_cpu_data *sd;
 993         int r;
 994
 995         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 996         if (!sd)
 997                 return -ENOMEM;
 998         sd->cpu = cpu;
 999         r = -ENOMEM;
1000         sd->save_area = alloc_page(GFP_KERNEL);
1001         if (!sd->save_area)
1002                 goto err_1;
1003
1004         if (svm_sev_enabled()) {
1005                 r = -ENOMEM;
1006                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1007                                               sizeof(void *),
1008                                               GFP_KERNEL);
1009                 if (!sd->sev_vmcbs)
1010                         goto err_1;
1011         }
1012
1013         per_cpu(svm_data, cpu) = sd;
1014
1015         return 0;
1016
1017 err_1:
1018         kfree(sd);
1019         return r;
1020
1021 }
1022
1023 static bool valid_msr_intercept(u32 index)
1024 {
1025         int i;
1026
1027         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1028                 if (direct_access_msrs[i].index == index)
1029                         return true;
1030
1031         return false;
1032 }
1033
1034 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1035 {
1036         u8 bit_write;
1037         unsigned long tmp;
1038         u32 offset;
1039         u32 *msrpm;
1040
1041         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1042                                       to_svm(vcpu)->msrpm;
1043
1044         offset    = svm_msrpm_offset(msr);
1045         bit_write = 2 * (msr & 0x0f) + 1;
1046         tmp       = msrpm[offset];
1047
1048         BUG_ON(offset == MSR_INVALID);
1049
1050         return !!test_bit(bit_write,  &tmp);
1051 }
1052
1053 static void set_msr_interception(u32 *msrpm, unsigned msr,
1054                                  int read, int write)
1055 {
1056         u8 bit_read, bit_write;
1057         unsigned long tmp;
1058         u32 offset;
1059
1060         /*
1061          * If this warning triggers extend the direct_access_msrs list at the
1062          * beginning of the file
1063          */
1064         WARN_ON(!valid_msr_intercept(msr));
1065
1066         offset    = svm_msrpm_offset(msr);
1067         bit_read  = 2 * (msr & 0x0f);
1068         bit_write = 2 * (msr & 0x0f) + 1;
1069         tmp       = msrpm[offset];
1070
1071         BUG_ON(offset == MSR_INVALID);
1072
1073         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1074         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1075
1076         msrpm[offset] = tmp;
1077 }
1078
1079 static void svm_vcpu_init_msrpm(u32 *msrpm)
1080 {
1081         int i;
1082
1083         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1084
1085         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1086                 if (!direct_access_msrs[i].always)
1087                         continue;
1088
1089                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1090         }
1091 }
1092
1093 static void add_msr_offset(u32 offset)
1094 {
1095         int i;
1096
1097         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1098
1099                 /* Offset already in list? */
1100                 if (msrpm_offsets[i] == offset)
1101                         return;
1102
1103                 /* Slot used by another offset? */
1104                 if (msrpm_offsets[i] != MSR_INVALID)
1105                         continue;
1106
1107                 /* Add offset to list */
1108                 msrpm_offsets[i] = offset;
1109
1110                 return;
1111         }
1112
1113         /*
1114          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1115          * increase MSRPM_OFFSETS in this case.
1116          */
1117         BUG();
1118 }
1119
1120 static void init_msrpm_offsets(void)
1121 {
1122         int i;
1123
1124         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1125
1126         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1127                 u32 offset;
1128
1129                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1130                 BUG_ON(offset == MSR_INVALID);
1131
1132                 add_msr_offset(offset);
1133         }
1134 }
1135
1136 static void svm_enable_lbrv(struct vcpu_svm *svm)
1137 {
1138         u32 *msrpm = svm->msrpm;
1139
1140         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1141         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1142         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1143         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1144         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1145 }
1146
1147 static void svm_disable_lbrv(struct vcpu_svm *svm)
1148 {
1149         u32 *msrpm = svm->msrpm;
1150
1151         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1152         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1153         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1154         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1155         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1156 }
1157
1158 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1159 {
1160         svm->nmi_singlestep = false;
1161
1162         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1163                 /* Clear our flags if they were not set by the guest */
1164                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1165                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1166                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1167                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1168         }
1169 }
1170
1171 /* Note:
1172  * This hash table is used to map VM_ID to a struct kvm_svm,
1173  * when handling AMD IOMMU GALOG notification to schedule in
1174  * a particular vCPU.
1175  */
1176 #define SVM_VM_DATA_HASH_BITS   8
1177 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1178 static u32 next_vm_id = 0;
1179 static bool next_vm_id_wrapped = 0;
1180 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1181
1182 /* Note:
1183  * This function is called from IOMMU driver to notify
1184  * SVM to schedule in a particular vCPU of a particular VM.
1185  */
1186 static int avic_ga_log_notifier(u32 ga_tag)
1187 {
1188         unsigned long flags;
1189         struct kvm_svm *kvm_svm;
1190         struct kvm_vcpu *vcpu = NULL;
1191         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1192         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1193
1194         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1195
1196         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1197         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1198                 if (kvm_svm->avic_vm_id != vm_id)
1199                         continue;
1200                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1201                 break;
1202         }
1203         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1204
1205         /* Note:
1206          * At this point, the IOMMU should have already set the pending
1207          * bit in the vAPIC backing page. So, we just need to schedule
1208          * in the vcpu.
1209          */
1210         if (vcpu)
1211                 kvm_vcpu_wake_up(vcpu);
1212
1213         return 0;
1214 }
1215
1216 static __init int sev_hardware_setup(void)
1217 {
1218         struct sev_user_data_status *status;
1219         int rc;
1220
1221         /* Maximum number of encrypted guests supported simultaneously */
1222         max_sev_asid = cpuid_ecx(0x8000001F);
1223
1224         if (!max_sev_asid)
1225                 return 1;
1226
1227         /* Minimum ASID value that should be used for SEV guest */
1228         min_sev_asid = cpuid_edx(0x8000001F);
1229
1230         /* Initialize SEV ASID bitmap */
1231         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1232         if (!sev_asid_bitmap)
1233                 return 1;
1234
1235         status = kmalloc(sizeof(*status), GFP_KERNEL);
1236         if (!status)
1237                 return 1;
1238
1239         /*
1240          * Check SEV platform status.
1241          *
1242          * PLATFORM_STATUS can be called in any state, if we failed to query
1243          * the PLATFORM status then either PSP firmware does not support SEV
1244          * feature or SEV firmware is dead.
1245          */
1246         rc = sev_platform_status(status, NULL);
1247         if (rc)
1248                 goto err;
1249
1250         pr_info("SEV supported\n");
1251
1252 err:
1253         kfree(status);
1254         return rc;
1255 }
1256
1257 static void grow_ple_window(struct kvm_vcpu *vcpu)
1258 {
1259         struct vcpu_svm *svm = to_svm(vcpu);
1260         struct vmcb_control_area *control = &svm->vmcb->control;
1261         int old = control->pause_filter_count;
1262
1263         control->pause_filter_count = __grow_ple_window(old,
1264                                                         pause_filter_count,
1265                                                         pause_filter_count_grow,
1266                                                         pause_filter_count_max);
1267
1268         if (control->pause_filter_count != old)
1269                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1270
1271         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1272                                   control->pause_filter_count, old);
1273 }
1274
1275 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1276 {
1277         struct vcpu_svm *svm = to_svm(vcpu);
1278         struct vmcb_control_area *control = &svm->vmcb->control;
1279         int old = control->pause_filter_count;
1280
1281         control->pause_filter_count =
1282                                 __shrink_ple_window(old,
1283                                                     pause_filter_count,
1284                                                     pause_filter_count_shrink,
1285                                                     pause_filter_count);
1286         if (control->pause_filter_count != old)
1287                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1288
1289         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1290                                     control->pause_filter_count, old);
1291 }
1292
1293 static __init int svm_hardware_setup(void)
1294 {
1295         int cpu;
1296         struct page *iopm_pages;
1297         void *iopm_va;
1298         int r;
1299
1300         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1301
1302         if (!iopm_pages)
1303                 return -ENOMEM;
1304
1305         iopm_va = page_address(iopm_pages);
1306         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1307         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1308
1309         init_msrpm_offsets();
1310
1311         if (boot_cpu_has(X86_FEATURE_NX))
1312                 kvm_enable_efer_bits(EFER_NX);
1313
1314         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1315                 kvm_enable_efer_bits(EFER_FFXSR);
1316
1317         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1318                 kvm_has_tsc_control = true;
1319                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1320                 kvm_tsc_scaling_ratio_frac_bits = 32;
1321         }
1322
1323         /* Check for pause filtering support */
1324         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1325                 pause_filter_count = 0;
1326                 pause_filter_thresh = 0;
1327         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1328                 pause_filter_thresh = 0;
1329         }
1330
1331         if (nested) {
1332                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1333                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1334         }
1335
1336         if (sev) {
1337                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1338                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1339                         r = sev_hardware_setup();
1340                         if (r)
1341                                 sev = false;
1342                 } else {
1343                         sev = false;
1344                 }
1345         }
1346
1347         for_each_possible_cpu(cpu) {
1348                 r = svm_cpu_init(cpu);
1349                 if (r)
1350                         goto err;
1351         }
1352
1353         if (!boot_cpu_has(X86_FEATURE_NPT))
1354                 npt_enabled = false;
1355
1356         if (npt_enabled && !npt) {
1357                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1358                 npt_enabled = false;
1359         }
1360
1361         if (npt_enabled) {
1362                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1363                 kvm_enable_tdp();
1364         } else
1365                 kvm_disable_tdp();
1366
1367         if (avic) {
1368                 if (!npt_enabled ||
1369                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1370                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1371                         avic = false;
1372                 } else {
1373                         pr_info("AVIC enabled\n");
1374
1375                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1376                 }
1377         }
1378
1379         if (vls) {
1380                 if (!npt_enabled ||
1381                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1382                     !IS_ENABLED(CONFIG_X86_64)) {
1383                         vls = false;
1384                 } else {
1385                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1386                 }
1387         }
1388
1389         if (vgif) {
1390                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1391                         vgif = false;
1392                 else
1393                         pr_info("Virtual GIF supported\n");
1394         }
1395
1396         return 0;
1397
1398 err:
1399         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1400         iopm_base = 0;
1401         return r;
1402 }
1403
1404 static __exit void svm_hardware_unsetup(void)
1405 {
1406         int cpu;
1407
1408         if (svm_sev_enabled())
1409                 bitmap_free(sev_asid_bitmap);
1410
1411         for_each_possible_cpu(cpu)
1412                 svm_cpu_uninit(cpu);
1413
1414         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1415         iopm_base = 0;
1416 }
1417
1418 static void init_seg(struct vmcb_seg *seg)
1419 {
1420         seg->selector = 0;
1421         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1422                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1423         seg->limit = 0xffff;
1424         seg->base = 0;
1425 }
1426
1427 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1428 {
1429         seg->selector = 0;
1430         seg->attrib = SVM_SELECTOR_P_MASK | type;
1431         seg->limit = 0xffff;
1432         seg->base = 0;
1433 }
1434
1435 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1436 {
1437         struct vcpu_svm *svm = to_svm(vcpu);
1438
1439         if (is_guest_mode(vcpu))
1440                 return svm->nested.hsave->control.tsc_offset;
1441
1442         return vcpu->arch.tsc_offset;
1443 }
1444
1445 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1446 {
1447         struct vcpu_svm *svm = to_svm(vcpu);
1448         u64 g_tsc_offset = 0;
1449
1450         if (is_guest_mode(vcpu)) {
1451                 /* Write L1's TSC offset.  */
1452                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1453                                svm->nested.hsave->control.tsc_offset;
1454                 svm->nested.hsave->control.tsc_offset = offset;
1455         }
1456
1457         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1458                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1459                                    offset);
1460
1461         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1462
1463         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1464         return svm->vmcb->control.tsc_offset;
1465 }
1466
1467 static void avic_init_vmcb(struct vcpu_svm *svm)
1468 {
1469         struct vmcb *vmcb = svm->vmcb;
1470         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1471         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1472         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1473         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1474
1475         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1476         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1477         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1478         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1479         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1480 }
1481
1482 static void init_vmcb(struct vcpu_svm *svm)
1483 {
1484         struct vmcb_control_area *control = &svm->vmcb->control;
1485         struct vmcb_save_area *save = &svm->vmcb->save;
1486
1487         svm->vcpu.arch.hflags = 0;
1488
1489         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1490         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1491         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1492         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1493         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1494         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1495         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1496                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1497
1498         set_dr_intercepts(svm);
1499
1500         set_exception_intercept(svm, PF_VECTOR);
1501         set_exception_intercept(svm, UD_VECTOR);
1502         set_exception_intercept(svm, MC_VECTOR);
1503         set_exception_intercept(svm, AC_VECTOR);
1504         set_exception_intercept(svm, DB_VECTOR);
1505         /*
1506          * Guest access to VMware backdoor ports could legitimately
1507          * trigger #GP because of TSS I/O permission bitmap.
1508          * We intercept those #GP and allow access to them anyway
1509          * as VMware does.
1510          */
1511         if (enable_vmware_backdoor)
1512                 set_exception_intercept(svm, GP_VECTOR);
1513
1514         set_intercept(svm, INTERCEPT_INTR);
1515         set_intercept(svm, INTERCEPT_NMI);
1516         set_intercept(svm, INTERCEPT_SMI);
1517         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1518         set_intercept(svm, INTERCEPT_RDPMC);
1519         set_intercept(svm, INTERCEPT_CPUID);
1520         set_intercept(svm, INTERCEPT_INVD);
1521         set_intercept(svm, INTERCEPT_INVLPG);
1522         set_intercept(svm, INTERCEPT_INVLPGA);
1523         set_intercept(svm, INTERCEPT_IOIO_PROT);
1524         set_intercept(svm, INTERCEPT_MSR_PROT);
1525         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1526         set_intercept(svm, INTERCEPT_SHUTDOWN);
1527         set_intercept(svm, INTERCEPT_VMRUN);
1528         set_intercept(svm, INTERCEPT_VMMCALL);
1529         set_intercept(svm, INTERCEPT_VMLOAD);
1530         set_intercept(svm, INTERCEPT_VMSAVE);
1531         set_intercept(svm, INTERCEPT_STGI);
1532         set_intercept(svm, INTERCEPT_CLGI);
1533         set_intercept(svm, INTERCEPT_SKINIT);
1534         set_intercept(svm, INTERCEPT_WBINVD);
1535         set_intercept(svm, INTERCEPT_XSETBV);
1536         set_intercept(svm, INTERCEPT_RSM);
1537
1538         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1539                 set_intercept(svm, INTERCEPT_MONITOR);
1540                 set_intercept(svm, INTERCEPT_MWAIT);
1541         }
1542
1543         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1544                 set_intercept(svm, INTERCEPT_HLT);
1545
1546         control->iopm_base_pa = __sme_set(iopm_base);
1547         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1548         control->int_ctl = V_INTR_MASKING_MASK;
1549
1550         init_seg(&save->es);
1551         init_seg(&save->ss);
1552         init_seg(&save->ds);
1553         init_seg(&save->fs);
1554         init_seg(&save->gs);
1555
1556         save->cs.selector = 0xf000;
1557         save->cs.base = 0xffff0000;
1558         /* Executable/Readable Code Segment */
1559         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1560                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1561         save->cs.limit = 0xffff;
1562
1563         save->gdtr.limit = 0xffff;
1564         save->idtr.limit = 0xffff;
1565
1566         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1567         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1568
1569         svm_set_efer(&svm->vcpu, 0);
1570         save->dr6 = 0xffff0ff0;
1571         kvm_set_rflags(&svm->vcpu, 2);
1572         save->rip = 0x0000fff0;
1573         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1574
1575         /*
1576          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1577          * It also updates the guest-visible cr0 value.
1578          */
1579         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1580         kvm_mmu_reset_context(&svm->vcpu);
1581
1582         save->cr4 = X86_CR4_PAE;
1583         /* rdx = ?? */
1584
1585         if (npt_enabled) {
1586                 /* Setup VMCB for Nested Paging */
1587                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1588                 clr_intercept(svm, INTERCEPT_INVLPG);
1589                 clr_exception_intercept(svm, PF_VECTOR);
1590                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1591                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1592                 save->g_pat = svm->vcpu.arch.pat;
1593                 save->cr3 = 0;
1594                 save->cr4 = 0;
1595         }
1596         svm->asid_generation = 0;
1597
1598         svm->nested.vmcb = 0;
1599         svm->vcpu.arch.hflags = 0;
1600
1601         if (pause_filter_count) {
1602                 control->pause_filter_count = pause_filter_count;
1603                 if (pause_filter_thresh)
1604                         control->pause_filter_thresh = pause_filter_thresh;
1605                 set_intercept(svm, INTERCEPT_PAUSE);
1606         } else {
1607                 clr_intercept(svm, INTERCEPT_PAUSE);
1608         }
1609
1610         if (kvm_vcpu_apicv_active(&svm->vcpu))
1611                 avic_init_vmcb(svm);
1612
1613         /*
1614          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1615          * in VMCB and clear intercepts to avoid #VMEXIT.
1616          */
1617         if (vls) {
1618                 clr_intercept(svm, INTERCEPT_VMLOAD);
1619                 clr_intercept(svm, INTERCEPT_VMSAVE);
1620                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1621         }
1622
1623         if (vgif) {
1624                 clr_intercept(svm, INTERCEPT_STGI);
1625                 clr_intercept(svm, INTERCEPT_CLGI);
1626                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1627         }
1628
1629         if (sev_guest(svm->vcpu.kvm)) {
1630                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1631                 clr_exception_intercept(svm, UD_VECTOR);
1632         }
1633
1634         mark_all_dirty(svm->vmcb);
1635
1636         enable_gif(svm);
1637
1638 }
1639
1640 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1641                                        unsigned int index)
1642 {
1643         u64 *avic_physical_id_table;
1644         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1645
1646         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1647                 return NULL;
1648
1649         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1650
1651         return &avic_physical_id_table[index];
1652 }
1653
1654 /**
1655  * Note:
1656  * AVIC hardware walks the nested page table to check permissions,
1657  * but does not use the SPA address specified in the leaf page
1658  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1659  * field of the VMCB. Therefore, we set up the
1660  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1661  */
1662 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1663 {
1664         struct kvm *kvm = vcpu->kvm;
1665         int ret = 0;
1666
1667         mutex_lock(&kvm->slots_lock);
1668         if (kvm->arch.apic_access_page_done)
1669                 goto out;
1670
1671         ret = __x86_set_memory_region(kvm,
1672                                       APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1673                                       APIC_DEFAULT_PHYS_BASE,
1674                                       PAGE_SIZE);
1675         if (ret)
1676                 goto out;
1677
1678         kvm->arch.apic_access_page_done = true;
1679 out:
1680         mutex_unlock(&kvm->slots_lock);
1681         return ret;
1682 }
1683
1684 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1685 {
1686         int ret;
1687         u64 *entry, new_entry;
1688         int id = vcpu->vcpu_id;
1689         struct vcpu_svm *svm = to_svm(vcpu);
1690
1691         ret = avic_init_access_page(vcpu);
1692         if (ret)
1693                 return ret;
1694
1695         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1696                 return -EINVAL;
1697
1698         if (!svm->vcpu.arch.apic->regs)
1699                 return -EINVAL;
1700
1701         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1702
1703         /* Setting AVIC backing page address in the phy APIC ID table */
1704         entry = avic_get_physical_id_entry(vcpu, id);
1705         if (!entry)
1706                 return -EINVAL;
1707
1708         new_entry = READ_ONCE(*entry);
1709         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1710                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1711                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1712         WRITE_ONCE(*entry, new_entry);
1713
1714         svm->avic_physical_id_cache = entry;
1715
1716         return 0;
1717 }
1718
1719 static void __sev_asid_free(int asid)
1720 {
1721         struct svm_cpu_data *sd;
1722         int cpu, pos;
1723
1724         pos = asid - 1;
1725         clear_bit(pos, sev_asid_bitmap);
1726
1727         for_each_possible_cpu(cpu) {
1728                 sd = per_cpu(svm_data, cpu);
1729                 sd->sev_vmcbs[pos] = NULL;
1730         }
1731 }
1732
1733 static void sev_asid_free(struct kvm *kvm)
1734 {
1735         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1736
1737         __sev_asid_free(sev->asid);
1738 }
1739
1740 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1741 {
1742         struct sev_data_decommission *decommission;
1743         struct sev_data_deactivate *data;
1744
1745         if (!handle)
1746                 return;
1747
1748         data = kzalloc(sizeof(*data), GFP_KERNEL);
1749         if (!data)
1750                 return;
1751
1752         /* deactivate handle */
1753         data->handle = handle;
1754         sev_guest_deactivate(data, NULL);
1755
1756         wbinvd_on_all_cpus();
1757         sev_guest_df_flush(NULL);
1758         kfree(data);
1759
1760         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1761         if (!decommission)
1762                 return;
1763
1764         /* decommission handle */
1765         decommission->handle = handle;
1766         sev_guest_decommission(decommission, NULL);
1767
1768         kfree(decommission);
1769 }
1770
1771 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1772                                     unsigned long ulen, unsigned long *n,
1773                                     int write)
1774 {
1775         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1776         unsigned long npages, npinned, size;
1777         unsigned long locked, lock_limit;
1778         struct page **pages;
1779         unsigned long first, last;
1780
1781         if (ulen == 0 || uaddr + ulen < uaddr)
1782                 return NULL;
1783
1784         /* Calculate number of pages. */
1785         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1786         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1787         npages = (last - first + 1);
1788
1789         locked = sev->pages_locked + npages;
1790         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1791         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1792                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1793                 return NULL;
1794         }
1795
1796         /* Avoid using vmalloc for smaller buffers. */
1797         size = npages * sizeof(struct page *);
1798         if (size > PAGE_SIZE)
1799                 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1800                                   PAGE_KERNEL);
1801         else
1802                 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1803
1804         if (!pages)
1805                 return NULL;
1806
1807         /* Pin the user virtual address. */
1808         npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1809         if (npinned != npages) {
1810                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1811                 goto err;
1812         }
1813
1814         *n = npages;
1815         sev->pages_locked = locked;
1816
1817         return pages;
1818
1819 err:
1820         if (npinned > 0)
1821                 release_pages(pages, npinned);
1822
1823         kvfree(pages);
1824         return NULL;
1825 }
1826
1827 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1828                              unsigned long npages)
1829 {
1830         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1831
1832         release_pages(pages, npages);
1833         kvfree(pages);
1834         sev->pages_locked -= npages;
1835 }
1836
1837 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1838 {
1839         uint8_t *page_virtual;
1840         unsigned long i;
1841
1842         if (npages == 0 || pages == NULL)
1843                 return;
1844
1845         for (i = 0; i < npages; i++) {
1846                 page_virtual = kmap_atomic(pages[i]);
1847                 clflush_cache_range(page_virtual, PAGE_SIZE);
1848                 kunmap_atomic(page_virtual);
1849         }
1850 }
1851
1852 static void __unregister_enc_region_locked(struct kvm *kvm,
1853                                            struct enc_region *region)
1854 {
1855         /*
1856          * The guest may change the memory encryption attribute from C=0 -> C=1
1857          * or vice versa for this memory range. Lets make sure caches are
1858          * flushed to ensure that guest data gets written into memory with
1859          * correct C-bit.
1860          */
1861         sev_clflush_pages(region->pages, region->npages);
1862
1863         sev_unpin_memory(kvm, region->pages, region->npages);
1864         list_del(&region->list);
1865         kfree(region);
1866 }
1867
1868 static struct kvm *svm_vm_alloc(void)
1869 {
1870         struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1871                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1872                                             PAGE_KERNEL);
1873         return &kvm_svm->kvm;
1874 }
1875
1876 static void svm_vm_free(struct kvm *kvm)
1877 {
1878         vfree(to_kvm_svm(kvm));
1879 }
1880
1881 static void sev_vm_destroy(struct kvm *kvm)
1882 {
1883         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1884         struct list_head *head = &sev->regions_list;
1885         struct list_head *pos, *q;
1886
1887         if (!sev_guest(kvm))
1888                 return;
1889
1890         mutex_lock(&kvm->lock);
1891
1892         /*
1893          * if userspace was terminated before unregistering the memory regions
1894          * then lets unpin all the registered memory.
1895          */
1896         if (!list_empty(head)) {
1897                 list_for_each_safe(pos, q, head) {
1898                         __unregister_enc_region_locked(kvm,
1899                                 list_entry(pos, struct enc_region, list));
1900                 }
1901         }
1902
1903         mutex_unlock(&kvm->lock);
1904
1905         sev_unbind_asid(kvm, sev->handle);
1906         sev_asid_free(kvm);
1907 }
1908
1909 static void avic_vm_destroy(struct kvm *kvm)
1910 {
1911         unsigned long flags;
1912         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1913
1914         if (!avic)
1915                 return;
1916
1917         if (kvm_svm->avic_logical_id_table_page)
1918                 __free_page(kvm_svm->avic_logical_id_table_page);
1919         if (kvm_svm->avic_physical_id_table_page)
1920                 __free_page(kvm_svm->avic_physical_id_table_page);
1921
1922         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1923         hash_del(&kvm_svm->hnode);
1924         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1925 }
1926
1927 static void svm_vm_destroy(struct kvm *kvm)
1928 {
1929         avic_vm_destroy(kvm);
1930         sev_vm_destroy(kvm);
1931 }
1932
1933 static int avic_vm_init(struct kvm *kvm)
1934 {
1935         unsigned long flags;
1936         int err = -ENOMEM;
1937         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1938         struct kvm_svm *k2;
1939         struct page *p_page;
1940         struct page *l_page;
1941         u32 vm_id;
1942
1943         if (!avic)
1944                 return 0;
1945
1946         /* Allocating physical APIC ID table (4KB) */
1947         p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1948         if (!p_page)
1949                 goto free_avic;
1950
1951         kvm_svm->avic_physical_id_table_page = p_page;
1952         clear_page(page_address(p_page));
1953
1954         /* Allocating logical APIC ID table (4KB) */
1955         l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1956         if (!l_page)
1957                 goto free_avic;
1958
1959         kvm_svm->avic_logical_id_table_page = l_page;
1960         clear_page(page_address(l_page));
1961
1962         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1963  again:
1964         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1965         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1966                 next_vm_id_wrapped = 1;
1967                 goto again;
1968         }
1969         /* Is it still in use? Only possible if wrapped at least once */
1970         if (next_vm_id_wrapped) {
1971                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1972                         if (k2->avic_vm_id == vm_id)
1973                                 goto again;
1974                 }
1975         }
1976         kvm_svm->avic_vm_id = vm_id;
1977         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1978         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1979
1980         return 0;
1981
1982 free_avic:
1983         avic_vm_destroy(kvm);
1984         return err;
1985 }
1986
1987 static inline int
1988 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1989 {
1990         int ret = 0;
1991         unsigned long flags;
1992         struct amd_svm_iommu_ir *ir;
1993         struct vcpu_svm *svm = to_svm(vcpu);
1994
1995         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1996                 return 0;
1997
1998         /*
1999          * Here, we go through the per-vcpu ir_list to update all existing
2000          * interrupt remapping table entry targeting this vcpu.
2001          */
2002         spin_lock_irqsave(&svm->ir_list_lock, flags);
2003
2004         if (list_empty(&svm->ir_list))
2005                 goto out;
2006
2007         list_for_each_entry(ir, &svm->ir_list, node) {
2008                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2009                 if (ret)
2010                         break;
2011         }
2012 out:
2013         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2014         return ret;
2015 }
2016
2017 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2018 {
2019         u64 entry;
2020         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2021         int h_physical_id = kvm_cpu_get_apicid(cpu);
2022         struct vcpu_svm *svm = to_svm(vcpu);
2023
2024         if (!kvm_vcpu_apicv_active(vcpu))
2025                 return;
2026
2027         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2028                 return;
2029
2030         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2031         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2032
2033         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2034         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2035
2036         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2037         if (svm->avic_is_running)
2038                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2039
2040         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2041         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2042                                         svm->avic_is_running);
2043 }
2044
2045 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2046 {
2047         u64 entry;
2048         struct vcpu_svm *svm = to_svm(vcpu);
2049
2050         if (!kvm_vcpu_apicv_active(vcpu))
2051                 return;
2052
2053         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2054         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2055                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2056
2057         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2058         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2059 }
2060
2061 /**
2062  * This function is called during VCPU halt/unhalt.
2063  */
2064 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2065 {
2066         struct vcpu_svm *svm = to_svm(vcpu);
2067
2068         svm->avic_is_running = is_run;
2069         if (is_run)
2070                 avic_vcpu_load(vcpu, vcpu->cpu);
2071         else
2072                 avic_vcpu_put(vcpu);
2073 }
2074
2075 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2076 {
2077         struct vcpu_svm *svm = to_svm(vcpu);
2078         u32 dummy;
2079         u32 eax = 1;
2080
2081         vcpu->arch.microcode_version = 0x01000065;
2082         svm->spec_ctrl = 0;
2083         svm->virt_spec_ctrl = 0;
2084
2085         if (!init_event) {
2086                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2087                                            MSR_IA32_APICBASE_ENABLE;
2088                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2089                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2090         }
2091         init_vmcb(svm);
2092
2093         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2094         kvm_rdx_write(vcpu, eax);
2095
2096         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2097                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2098 }
2099
2100 static int avic_init_vcpu(struct vcpu_svm *svm)
2101 {
2102         int ret;
2103
2104         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2105                 return 0;
2106
2107         ret = avic_init_backing_page(&svm->vcpu);
2108         if (ret)
2109                 return ret;
2110
2111         INIT_LIST_HEAD(&svm->ir_list);
2112         spin_lock_init(&svm->ir_list_lock);
2113         svm->dfr_reg = APIC_DFR_FLAT;
2114
2115         return ret;
2116 }
2117
2118 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2119 {
2120         struct vcpu_svm *svm;
2121         struct page *page;
2122         struct page *msrpm_pages;
2123         struct page *hsave_page;
2124         struct page *nested_msrpm_pages;
2125         int err;
2126
2127         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2128         if (!svm) {
2129                 err = -ENOMEM;
2130                 goto out;
2131         }
2132
2133         svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2134                                                      GFP_KERNEL_ACCOUNT);
2135         if (!svm->vcpu.arch.guest_fpu) {
2136                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2137                 err = -ENOMEM;
2138                 goto free_partial_svm;
2139         }
2140
2141         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2142         if (err)
2143                 goto free_svm;
2144
2145         err = -ENOMEM;
2146         page = alloc_page(GFP_KERNEL_ACCOUNT);
2147         if (!page)
2148                 goto uninit;
2149
2150         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2151         if (!msrpm_pages)
2152                 goto free_page1;
2153
2154         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2155         if (!nested_msrpm_pages)
2156                 goto free_page2;
2157
2158         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2159         if (!hsave_page)
2160                 goto free_page3;
2161
2162         err = avic_init_vcpu(svm);
2163         if (err)
2164                 goto free_page4;
2165
2166         /* We initialize this flag to true to make sure that the is_running
2167          * bit would be set the first time the vcpu is loaded.
2168          */
2169         svm->avic_is_running = true;
2170
2171         svm->nested.hsave = page_address(hsave_page);
2172
2173         svm->msrpm = page_address(msrpm_pages);
2174         svm_vcpu_init_msrpm(svm->msrpm);
2175
2176         svm->nested.msrpm = page_address(nested_msrpm_pages);
2177         svm_vcpu_init_msrpm(svm->nested.msrpm);
2178
2179         svm->vmcb = page_address(page);
2180         clear_page(svm->vmcb);
2181         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2182         svm->asid_generation = 0;
2183         init_vmcb(svm);
2184
2185         svm_init_osvw(&svm->vcpu);
2186
2187         return &svm->vcpu;
2188
2189 free_page4:
2190         __free_page(hsave_page);
2191 free_page3:
2192         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2193 free_page2:
2194         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2195 free_page1:
2196         __free_page(page);
2197 uninit:
2198         kvm_vcpu_uninit(&svm->vcpu);
2199 free_svm:
2200         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2201 free_partial_svm:
2202         kmem_cache_free(kvm_vcpu_cache, svm);
2203 out:
2204         return ERR_PTR(err);
2205 }
2206
2207 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2208 {
2209         int i;
2210
2211         for_each_online_cpu(i)
2212                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2213 }
2214
2215 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2216 {
2217         struct vcpu_svm *svm = to_svm(vcpu);
2218
2219         /*
2220          * The vmcb page can be recycled, causing a false negative in
2221          * svm_vcpu_load(). So, ensure that no logical CPU has this
2222          * vmcb page recorded as its current vmcb.
2223          */
2224         svm_clear_current_vmcb(svm->vmcb);
2225
2226         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2227         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2228         __free_page(virt_to_page(svm->nested.hsave));
2229         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2230         kvm_vcpu_uninit(vcpu);
2231         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2232         kmem_cache_free(kvm_vcpu_cache, svm);
2233 }
2234
2235 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2236 {
2237         struct vcpu_svm *svm = to_svm(vcpu);
2238         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2239         int i;
2240
2241         if (unlikely(cpu != vcpu->cpu)) {
2242                 svm->asid_generation = 0;
2243                 mark_all_dirty(svm->vmcb);
2244         }
2245
2246 #ifdef CONFIG_X86_64
2247         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2248 #endif
2249         savesegment(fs, svm->host.fs);
2250         savesegment(gs, svm->host.gs);
2251         svm->host.ldt = kvm_read_ldt();
2252
2253         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2254                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2255
2256         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2257                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2258                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2259                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2260                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2261                 }
2262         }
2263         /* This assumes that the kernel never uses MSR_TSC_AUX */
2264         if (static_cpu_has(X86_FEATURE_RDTSCP))
2265                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2266
2267         if (sd->current_vmcb != svm->vmcb) {
2268                 sd->current_vmcb = svm->vmcb;
2269                 indirect_branch_prediction_barrier();
2270         }
2271         avic_vcpu_load(vcpu, cpu);
2272 }
2273
2274 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2275 {
2276         struct vcpu_svm *svm = to_svm(vcpu);
2277         int i;
2278
2279         avic_vcpu_put(vcpu);
2280
2281         ++vcpu->stat.host_state_reload;
2282         kvm_load_ldt(svm->host.ldt);
2283 #ifdef CONFIG_X86_64
2284         loadsegment(fs, svm->host.fs);
2285         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2286         load_gs_index(svm->host.gs);
2287 #else
2288 #ifdef CONFIG_X86_32_LAZY_GS
2289         loadsegment(gs, svm->host.gs);
2290 #endif
2291 #endif
2292         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2293                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2294 }
2295
2296 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2297 {
2298         avic_set_running(vcpu, false);
2299 }
2300
2301 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2302 {
2303         avic_set_running(vcpu, true);
2304 }
2305
2306 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2307 {
2308         struct vcpu_svm *svm = to_svm(vcpu);
2309         unsigned long rflags = svm->vmcb->save.rflags;
2310
2311         if (svm->nmi_singlestep) {
2312                 /* Hide our flags if they were not set by the guest */
2313                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2314                         rflags &= ~X86_EFLAGS_TF;
2315                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2316                         rflags &= ~X86_EFLAGS_RF;
2317         }
2318         return rflags;
2319 }
2320
2321 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2322 {
2323         if (to_svm(vcpu)->nmi_singlestep)
2324                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2325
2326        /*
2327         * Any change of EFLAGS.VM is accompanied by a reload of SS
2328         * (caused by either a task switch or an inter-privilege IRET),
2329         * so we do not need to update the CPL here.
2330         */
2331         to_svm(vcpu)->vmcb->save.rflags = rflags;
2332 }
2333
2334 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2335 {
2336         switch (reg) {
2337         case VCPU_EXREG_PDPTR:
2338                 BUG_ON(!npt_enabled);
2339                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2340                 break;
2341         default:
2342                 BUG();
2343         }
2344 }
2345
2346 static void svm_set_vintr(struct vcpu_svm *svm)
2347 {
2348         set_intercept(svm, INTERCEPT_VINTR);
2349 }
2350
2351 static void svm_clear_vintr(struct vcpu_svm *svm)
2352 {
2353         clr_intercept(svm, INTERCEPT_VINTR);
2354 }
2355
2356 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2357 {
2358         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2359
2360         switch (seg) {
2361         case VCPU_SREG_CS: return &save->cs;
2362         case VCPU_SREG_DS: return &save->ds;
2363         case VCPU_SREG_ES: return &save->es;
2364         case VCPU_SREG_FS: return &save->fs;
2365         case VCPU_SREG_GS: return &save->gs;
2366         case VCPU_SREG_SS: return &save->ss;
2367         case VCPU_SREG_TR: return &save->tr;
2368         case VCPU_SREG_LDTR: return &save->ldtr;
2369         }
2370         BUG();
2371         return NULL;
2372 }
2373
2374 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2375 {
2376         struct vmcb_seg *s = svm_seg(vcpu, seg);
2377
2378         return s->base;
2379 }
2380
2381 static void svm_get_segment(struct kvm_vcpu *vcpu,
2382                             struct kvm_segment *var, int seg)
2383 {
2384         struct vmcb_seg *s = svm_seg(vcpu, seg);
2385
2386         var->base = s->base;
2387         var->limit = s->limit;
2388         var->selector = s->selector;
2389         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2390         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2391         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2392         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2393         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2394         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2395         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2396
2397         /*
2398          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2399          * However, the SVM spec states that the G bit is not observed by the
2400          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2401          * So let's synthesize a legal G bit for all segments, this helps
2402          * running KVM nested. It also helps cross-vendor migration, because
2403          * Intel's vmentry has a check on the 'G' bit.
2404          */
2405         var->g = s->limit > 0xfffff;
2406
2407         /*
2408          * AMD's VMCB does not have an explicit unusable field, so emulate it
2409          * for cross vendor migration purposes by "not present"
2410          */
2411         var->unusable = !var->present;
2412
2413         switch (seg) {
2414         case VCPU_SREG_TR:
2415                 /*
2416                  * Work around a bug where the busy flag in the tr selector
2417                  * isn't exposed
2418                  */
2419                 var->type |= 0x2;
2420                 break;
2421         case VCPU_SREG_DS:
2422         case VCPU_SREG_ES:
2423         case VCPU_SREG_FS:
2424         case VCPU_SREG_GS:
2425                 /*
2426                  * The accessed bit must always be set in the segment
2427                  * descriptor cache, although it can be cleared in the
2428                  * descriptor, the cached bit always remains at 1. Since
2429                  * Intel has a check on this, set it here to support
2430                  * cross-vendor migration.
2431                  */
2432                 if (!var->unusable)
2433                         var->type |= 0x1;
2434                 break;
2435         case VCPU_SREG_SS:
2436                 /*
2437                  * On AMD CPUs sometimes the DB bit in the segment
2438                  * descriptor is left as 1, although the whole segment has
2439                  * been made unusable. Clear it here to pass an Intel VMX
2440                  * entry check when cross vendor migrating.
2441                  */
2442                 if (var->unusable)
2443                         var->db = 0;
2444                 /* This is symmetric with svm_set_segment() */
2445                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2446                 break;
2447         }
2448 }
2449
2450 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2451 {
2452         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2453
2454         return save->cpl;
2455 }
2456
2457 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2458 {
2459         struct vcpu_svm *svm = to_svm(vcpu);
2460
2461         dt->size = svm->vmcb->save.idtr.limit;
2462         dt->address = svm->vmcb->save.idtr.base;
2463 }
2464
2465 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2466 {
2467         struct vcpu_svm *svm = to_svm(vcpu);
2468
2469         svm->vmcb->save.idtr.limit = dt->size;
2470         svm->vmcb->save.idtr.base = dt->address ;
2471         mark_dirty(svm->vmcb, VMCB_DT);
2472 }
2473
2474 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2475 {
2476         struct vcpu_svm *svm = to_svm(vcpu);
2477
2478         dt->size = svm->vmcb->save.gdtr.limit;
2479         dt->address = svm->vmcb->save.gdtr.base;
2480 }
2481
2482 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2483 {
2484         struct vcpu_svm *svm = to_svm(vcpu);
2485
2486         svm->vmcb->save.gdtr.limit = dt->size;
2487         svm->vmcb->save.gdtr.base = dt->address ;
2488         mark_dirty(svm->vmcb, VMCB_DT);
2489 }
2490
2491 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2492 {
2493 }
2494
2495 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2496 {
2497 }
2498
2499 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2500 {
2501 }
2502
2503 static void update_cr0_intercept(struct vcpu_svm *svm)
2504 {
2505         ulong gcr0 = svm->vcpu.arch.cr0;
2506         u64 *hcr0 = &svm->vmcb->save.cr0;
2507
2508         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2509                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2510
2511         mark_dirty(svm->vmcb, VMCB_CR);
2512
2513         if (gcr0 == *hcr0) {
2514                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2515                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2516         } else {
2517                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2518                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2519         }
2520 }
2521
2522 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2523 {
2524         struct vcpu_svm *svm = to_svm(vcpu);
2525
2526 #ifdef CONFIG_X86_64
2527         if (vcpu->arch.efer & EFER_LME) {
2528                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2529                         vcpu->arch.efer |= EFER_LMA;
2530                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2531                 }
2532
2533                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2534                         vcpu->arch.efer &= ~EFER_LMA;
2535                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2536                 }
2537         }
2538 #endif
2539         vcpu->arch.cr0 = cr0;
2540
2541         if (!npt_enabled)
2542                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2543
2544         /*
2545          * re-enable caching here because the QEMU bios
2546          * does not do it - this results in some delay at
2547          * reboot
2548          */
2549         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2550                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2551         svm->vmcb->save.cr0 = cr0;
2552         mark_dirty(svm->vmcb, VMCB_CR);
2553         update_cr0_intercept(svm);
2554 }
2555
2556 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2557 {
2558         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2559         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2560
2561         if (cr4 & X86_CR4_VMXE)
2562                 return 1;
2563
2564         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2565                 svm_flush_tlb(vcpu, true);
2566
2567         vcpu->arch.cr4 = cr4;
2568         if (!npt_enabled)
2569                 cr4 |= X86_CR4_PAE;
2570         cr4 |= host_cr4_mce;
2571         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2572         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2573         return 0;
2574 }
2575
2576 static void svm_set_segment(struct kvm_vcpu *vcpu,
2577                             struct kvm_segment *var, int seg)
2578 {
2579         struct vcpu_svm *svm = to_svm(vcpu);
2580         struct vmcb_seg *s = svm_seg(vcpu, seg);
2581
2582         s->base = var->base;
2583         s->limit = var->limit;
2584         s->selector = var->selector;
2585         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2586         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2587         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2588         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2589         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2590         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2591         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2592         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2593
2594         /*
2595          * This is always accurate, except if SYSRET returned to a segment
2596          * with SS.DPL != 3.  Intel does not have this quirk, and always
2597          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2598          * would entail passing the CPL to userspace and back.
2599          */
2600         if (seg == VCPU_SREG_SS)
2601                 /* This is symmetric with svm_get_segment() */
2602                 svm->vmcb->save.cpl = (var->dpl & 3);
2603
2604         mark_dirty(svm->vmcb, VMCB_SEG);
2605 }
2606
2607 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2608 {
2609         struct vcpu_svm *svm = to_svm(vcpu);
2610
2611         clr_exception_intercept(svm, BP_VECTOR);
2612
2613         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2614                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2615                         set_exception_intercept(svm, BP_VECTOR);
2616         } else
2617                 vcpu->guest_debug = 0;
2618 }
2619
2620 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2621 {
2622         if (sd->next_asid > sd->max_asid) {
2623                 ++sd->asid_generation;
2624                 sd->next_asid = sd->min_asid;
2625                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2626         }
2627
2628         svm->asid_generation = sd->asid_generation;
2629         svm->vmcb->control.asid = sd->next_asid++;
2630
2631         mark_dirty(svm->vmcb, VMCB_ASID);
2632 }
2633
2634 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2635 {
2636         return to_svm(vcpu)->vmcb->save.dr6;
2637 }
2638
2639 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2640 {
2641         struct vcpu_svm *svm = to_svm(vcpu);
2642
2643         svm->vmcb->save.dr6 = value;
2644         mark_dirty(svm->vmcb, VMCB_DR);
2645 }
2646
2647 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2648 {
2649         struct vcpu_svm *svm = to_svm(vcpu);
2650
2651         get_debugreg(vcpu->arch.db[0], 0);
2652         get_debugreg(vcpu->arch.db[1], 1);
2653         get_debugreg(vcpu->arch.db[2], 2);
2654         get_debugreg(vcpu->arch.db[3], 3);
2655         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2656         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2657
2658         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2659         set_dr_intercepts(svm);
2660 }
2661
2662 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2663 {
2664         struct vcpu_svm *svm = to_svm(vcpu);
2665
2666         svm->vmcb->save.dr7 = value;
2667         mark_dirty(svm->vmcb, VMCB_DR);
2668 }
2669
2670 static int pf_interception(struct vcpu_svm *svm)
2671 {
2672         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2673         u64 error_code = svm->vmcb->control.exit_info_1;
2674
2675         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2676                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2677                         svm->vmcb->control.insn_bytes : NULL,
2678                         svm->vmcb->control.insn_len);
2679 }
2680
2681 static int npf_interception(struct vcpu_svm *svm)
2682 {
2683         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2684         u64 error_code = svm->vmcb->control.exit_info_1;
2685
2686         trace_kvm_page_fault(fault_address, error_code);
2687         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2688                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2689                         svm->vmcb->control.insn_bytes : NULL,
2690                         svm->vmcb->control.insn_len);
2691 }
2692
2693 static int db_interception(struct vcpu_svm *svm)
2694 {
2695         struct kvm_run *kvm_run = svm->vcpu.run;
2696         struct kvm_vcpu *vcpu = &svm->vcpu;
2697
2698         if (!(svm->vcpu.guest_debug &
2699               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2700                 !svm->nmi_singlestep) {
2701                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2702                 return 1;
2703         }
2704
2705         if (svm->nmi_singlestep) {
2706                 disable_nmi_singlestep(svm);
2707                 /* Make sure we check for pending NMIs upon entry */
2708                 kvm_make_request(KVM_REQ_EVENT, vcpu);
2709         }
2710
2711         if (svm->vcpu.guest_debug &
2712             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2713                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2714                 kvm_run->debug.arch.pc =
2715                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2716                 kvm_run->debug.arch.exception = DB_VECTOR;
2717                 return 0;
2718         }
2719
2720         return 1;
2721 }
2722
2723 static int bp_interception(struct vcpu_svm *svm)
2724 {
2725         struct kvm_run *kvm_run = svm->vcpu.run;
2726
2727         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2728         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2729         kvm_run->debug.arch.exception = BP_VECTOR;
2730         return 0;
2731 }
2732
2733 static int ud_interception(struct vcpu_svm *svm)
2734 {
2735         return handle_ud(&svm->vcpu);
2736 }
2737
2738 static int ac_interception(struct vcpu_svm *svm)
2739 {
2740         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2741         return 1;
2742 }
2743
2744 static int gp_interception(struct vcpu_svm *svm)
2745 {
2746         struct kvm_vcpu *vcpu = &svm->vcpu;
2747         u32 error_code = svm->vmcb->control.exit_info_1;
2748         int er;
2749
2750         WARN_ON_ONCE(!enable_vmware_backdoor);
2751
2752         er = kvm_emulate_instruction(vcpu,
2753                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2754         if (er == EMULATE_USER_EXIT)
2755                 return 0;
2756         else if (er != EMULATE_DONE)
2757                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2758         return 1;
2759 }
2760
2761 static bool is_erratum_383(void)
2762 {
2763         int err, i;
2764         u64 value;
2765
2766         if (!erratum_383_found)
2767                 return false;
2768
2769         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2770         if (err)
2771                 return false;
2772
2773         /* Bit 62 may or may not be set for this mce */
2774         value &= ~(1ULL << 62);
2775
2776         if (value != 0xb600000000010015ULL)
2777                 return false;
2778
2779         /* Clear MCi_STATUS registers */
2780         for (i = 0; i < 6; ++i)
2781                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2782
2783         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2784         if (!err) {
2785                 u32 low, high;
2786
2787                 value &= ~(1ULL << 2);
2788                 low    = lower_32_bits(value);
2789                 high   = upper_32_bits(value);
2790
2791                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2792         }
2793
2794         /* Flush tlb to evict multi-match entries */
2795         __flush_tlb_all();
2796
2797         return true;
2798 }
2799
2800 static void svm_handle_mce(struct vcpu_svm *svm)
2801 {
2802         if (is_erratum_383()) {
2803                 /*
2804                  * Erratum 383 triggered. Guest state is corrupt so kill the
2805                  * guest.
2806                  */
2807                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2808
2809                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2810
2811                 return;
2812         }
2813
2814         /*
2815          * On an #MC intercept the MCE handler is not called automatically in
2816          * the host. So do it by hand here.
2817          */
2818         asm volatile (
2819                 "int $0x12\n");
2820         /* not sure if we ever come back to this point */
2821
2822         return;
2823 }
2824
2825 static int mc_interception(struct vcpu_svm *svm)
2826 {
2827         return 1;
2828 }
2829
2830 static int shutdown_interception(struct vcpu_svm *svm)
2831 {
2832         struct kvm_run *kvm_run = svm->vcpu.run;
2833
2834         /*
2835          * VMCB is undefined after a SHUTDOWN intercept
2836          * so reinitialize it.
2837          */
2838         clear_page(svm->vmcb);
2839         init_vmcb(svm);
2840
2841         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2842         return 0;
2843 }
2844
2845 static int io_interception(struct vcpu_svm *svm)
2846 {
2847         struct kvm_vcpu *vcpu = &svm->vcpu;
2848         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2849         int size, in, string;
2850         unsigned port;
2851
2852         ++svm->vcpu.stat.io_exits;
2853         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2854         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2855         if (string)
2856                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2857
2858         port = io_info >> 16;
2859         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2860         svm->next_rip = svm->vmcb->control.exit_info_2;
2861
2862         return kvm_fast_pio(&svm->vcpu, size, port, in);
2863 }
2864
2865 static int nmi_interception(struct vcpu_svm *svm)
2866 {
2867         return 1;
2868 }
2869
2870 static int intr_interception(struct vcpu_svm *svm)
2871 {
2872         ++svm->vcpu.stat.irq_exits;
2873         return 1;
2874 }
2875
2876 static int nop_on_interception(struct vcpu_svm *svm)
2877 {
2878         return 1;
2879 }
2880
2881 static int halt_interception(struct vcpu_svm *svm)
2882 {
2883         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2884         return kvm_emulate_halt(&svm->vcpu);
2885 }
2886
2887 static int vmmcall_interception(struct vcpu_svm *svm)
2888 {
2889         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2890         return kvm_emulate_hypercall(&svm->vcpu);
2891 }
2892
2893 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2894 {
2895         struct vcpu_svm *svm = to_svm(vcpu);
2896
2897         return svm->nested.nested_cr3;
2898 }
2899
2900 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2901 {
2902         struct vcpu_svm *svm = to_svm(vcpu);
2903         u64 cr3 = svm->nested.nested_cr3;
2904         u64 pdpte;
2905         int ret;
2906
2907         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2908                                        offset_in_page(cr3) + index * 8, 8);
2909         if (ret)
2910                 return 0;
2911         return pdpte;
2912 }
2913
2914 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2915                                    unsigned long root)
2916 {
2917         struct vcpu_svm *svm = to_svm(vcpu);
2918
2919         svm->vmcb->control.nested_cr3 = __sme_set(root);
2920         mark_dirty(svm->vmcb, VMCB_NPT);
2921 }
2922
2923 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2924                                        struct x86_exception *fault)
2925 {
2926         struct vcpu_svm *svm = to_svm(vcpu);
2927
2928         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2929                 /*
2930                  * TODO: track the cause of the nested page fault, and
2931                  * correctly fill in the high bits of exit_info_1.
2932                  */
2933                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2934                 svm->vmcb->control.exit_code_hi = 0;
2935                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2936                 svm->vmcb->control.exit_info_2 = fault->address;
2937         }
2938
2939         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2940         svm->vmcb->control.exit_info_1 |= fault->error_code;
2941
2942         /*
2943          * The present bit is always zero for page structure faults on real
2944          * hardware.
2945          */
2946         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2947                 svm->vmcb->control.exit_info_1 &= ~1;
2948
2949         nested_svm_vmexit(svm);
2950 }
2951
2952 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2953 {
2954         WARN_ON(mmu_is_nested(vcpu));
2955
2956         vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2957         kvm_init_shadow_mmu(vcpu);
2958         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2959         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2960         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2961         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2962         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2963         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2964         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2965 }
2966
2967 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2968 {
2969         vcpu->arch.mmu = &vcpu->arch.root_mmu;
2970         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2971 }
2972
2973 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2974 {
2975         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2976             !is_paging(&svm->vcpu)) {
2977                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2978                 return 1;
2979         }
2980
2981         if (svm->vmcb->save.cpl) {
2982                 kvm_inject_gp(&svm->vcpu, 0);
2983                 return 1;
2984         }
2985
2986         return 0;
2987 }
2988
2989 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2990                                       bool has_error_code, u32 error_code)
2991 {
2992         int vmexit;
2993
2994         if (!is_guest_mode(&svm->vcpu))
2995                 return 0;
2996
2997         vmexit = nested_svm_intercept(svm);
2998         if (vmexit != NESTED_EXIT_DONE)
2999                 return 0;
3000
3001         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3002         svm->vmcb->control.exit_code_hi = 0;
3003         svm->vmcb->control.exit_info_1 = error_code;
3004
3005         /*
3006          * EXITINFO2 is undefined for all exception intercepts other
3007          * than #PF.
3008          */
3009         if (svm->vcpu.arch.exception.nested_apf)
3010                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3011         else if (svm->vcpu.arch.exception.has_payload)
3012                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3013         else
3014                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3015
3016         svm->nested.exit_required = true;
3017         return vmexit;
3018 }
3019
3020 /* This function returns true if it is save to enable the irq window */
3021 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3022 {
3023         if (!is_guest_mode(&svm->vcpu))
3024                 return true;
3025
3026         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3027                 return true;
3028
3029         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3030                 return false;
3031
3032         /*
3033          * if vmexit was already requested (by intercepted exception
3034          * for instance) do not overwrite it with "external interrupt"
3035          * vmexit.
3036          */
3037         if (svm->nested.exit_required)
3038                 return false;
3039
3040         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3041         svm->vmcb->control.exit_info_1 = 0;
3042         svm->vmcb->control.exit_info_2 = 0;
3043
3044         if (svm->nested.intercept & 1ULL) {
3045                 /*
3046                  * The #vmexit can't be emulated here directly because this
3047                  * code path runs with irqs and preemption disabled. A
3048                  * #vmexit emulation might sleep. Only signal request for
3049                  * the #vmexit here.
3050                  */
3051                 svm->nested.exit_required = true;
3052                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3053                 return false;
3054         }
3055
3056         return true;
3057 }
3058
3059 /* This function returns true if it is save to enable the nmi window */
3060 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3061 {
3062         if (!is_guest_mode(&svm->vcpu))
3063                 return true;
3064
3065         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3066                 return true;
3067
3068         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3069         svm->nested.exit_required = true;
3070
3071         return false;
3072 }
3073
3074 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3075 {
3076         unsigned port, size, iopm_len;
3077         u16 val, mask;
3078         u8 start_bit;
3079         u64 gpa;
3080
3081         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3082                 return NESTED_EXIT_HOST;
3083
3084         port = svm->vmcb->control.exit_info_1 >> 16;
3085         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3086                 SVM_IOIO_SIZE_SHIFT;
3087         gpa  = svm->nested.vmcb_iopm + (port / 8);
3088         start_bit = port % 8;
3089         iopm_len = (start_bit + size > 8) ? 2 : 1;
3090         mask = (0xf >> (4 - size)) << start_bit;
3091         val = 0;
3092
3093         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3094                 return NESTED_EXIT_DONE;
3095
3096         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3097 }
3098
3099 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3100 {
3101         u32 offset, msr, value;
3102         int write, mask;
3103
3104         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3105                 return NESTED_EXIT_HOST;
3106
3107         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3108         offset = svm_msrpm_offset(msr);
3109         write  = svm->vmcb->control.exit_info_1 & 1;
3110         mask   = 1 << ((2 * (msr & 0xf)) + write);
3111
3112         if (offset == MSR_INVALID)
3113                 return NESTED_EXIT_DONE;
3114
3115         /* Offset is in 32 bit units but need in 8 bit units */
3116         offset *= 4;
3117
3118         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3119                 return NESTED_EXIT_DONE;
3120
3121         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3122 }
3123
3124 /* DB exceptions for our internal use must not cause vmexit */
3125 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3126 {
3127         unsigned long dr6;
3128
3129         /* if we're not singlestepping, it's not ours */
3130         if (!svm->nmi_singlestep)
3131                 return NESTED_EXIT_DONE;
3132
3133         /* if it's not a singlestep exception, it's not ours */
3134         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3135                 return NESTED_EXIT_DONE;
3136         if (!(dr6 & DR6_BS))
3137                 return NESTED_EXIT_DONE;
3138
3139         /* if the guest is singlestepping, it should get the vmexit */
3140         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3141                 disable_nmi_singlestep(svm);
3142                 return NESTED_EXIT_DONE;
3143         }
3144
3145         /* it's ours, the nested hypervisor must not see this one */
3146         return NESTED_EXIT_HOST;
3147 }
3148
3149 static int nested_svm_exit_special(struct vcpu_svm *svm)
3150 {
3151         u32 exit_code = svm->vmcb->control.exit_code;
3152
3153         switch (exit_code) {
3154         case SVM_EXIT_INTR:
3155         case SVM_EXIT_NMI:
3156         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3157                 return NESTED_EXIT_HOST;
3158         case SVM_EXIT_NPF:
3159                 /* For now we are always handling NPFs when using them */
3160                 if (npt_enabled)
3161                         return NESTED_EXIT_HOST;
3162                 break;
3163         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3164                 /* When we're shadowing, trap PFs, but not async PF */
3165                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3166                         return NESTED_EXIT_HOST;
3167                 break;
3168         default:
3169                 break;
3170         }
3171
3172         return NESTED_EXIT_CONTINUE;
3173 }
3174
3175 /*
3176  * If this function returns true, this #vmexit was already handled
3177  */
3178 static int nested_svm_intercept(struct vcpu_svm *svm)
3179 {
3180         u32 exit_code = svm->vmcb->control.exit_code;
3181         int vmexit = NESTED_EXIT_HOST;
3182
3183         switch (exit_code) {
3184         case SVM_EXIT_MSR:
3185                 vmexit = nested_svm_exit_handled_msr(svm);
3186                 break;
3187         case SVM_EXIT_IOIO:
3188                 vmexit = nested_svm_intercept_ioio(svm);
3189                 break;
3190         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3191                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3192                 if (svm->nested.intercept_cr & bit)
3193                         vmexit = NESTED_EXIT_DONE;
3194                 break;
3195         }
3196         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3197                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3198                 if (svm->nested.intercept_dr & bit)
3199                         vmexit = NESTED_EXIT_DONE;
3200                 break;
3201         }
3202         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3203                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3204                 if (svm->nested.intercept_exceptions & excp_bits) {
3205                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3206                                 vmexit = nested_svm_intercept_db(svm);
3207                         else
3208                                 vmexit = NESTED_EXIT_DONE;
3209                 }
3210                 /* async page fault always cause vmexit */
3211                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3212                          svm->vcpu.arch.exception.nested_apf != 0)
3213                         vmexit = NESTED_EXIT_DONE;
3214                 break;
3215         }
3216         case SVM_EXIT_ERR: {
3217                 vmexit = NESTED_EXIT_DONE;
3218                 break;
3219         }
3220         default: {
3221                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3222                 if (svm->nested.intercept & exit_bits)
3223                         vmexit = NESTED_EXIT_DONE;
3224         }
3225         }
3226
3227         return vmexit;
3228 }
3229
3230 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3231 {
3232         int vmexit;
3233
3234         vmexit = nested_svm_intercept(svm);
3235
3236         if (vmexit == NESTED_EXIT_DONE)
3237                 nested_svm_vmexit(svm);
3238
3239         return vmexit;
3240 }
3241
3242 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3243 {
3244         struct vmcb_control_area *dst  = &dst_vmcb->control;
3245         struct vmcb_control_area *from = &from_vmcb->control;
3246
3247         dst->intercept_cr         = from->intercept_cr;
3248         dst->intercept_dr         = from->intercept_dr;
3249         dst->intercept_exceptions = from->intercept_exceptions;
3250         dst->intercept            = from->intercept;
3251         dst->iopm_base_pa         = from->iopm_base_pa;
3252         dst->msrpm_base_pa        = from->msrpm_base_pa;
3253         dst->tsc_offset           = from->tsc_offset;
3254         dst->asid                 = from->asid;
3255         dst->tlb_ctl              = from->tlb_ctl;
3256         dst->int_ctl              = from->int_ctl;
3257         dst->int_vector           = from->int_vector;
3258         dst->int_state            = from->int_state;
3259         dst->exit_code            = from->exit_code;
3260         dst->exit_code_hi         = from->exit_code_hi;
3261         dst->exit_info_1          = from->exit_info_1;
3262         dst->exit_info_2          = from->exit_info_2;
3263         dst->exit_int_info        = from->exit_int_info;
3264         dst->exit_int_info_err    = from->exit_int_info_err;
3265         dst->nested_ctl           = from->nested_ctl;
3266         dst->event_inj            = from->event_inj;
3267         dst->event_inj_err        = from->event_inj_err;
3268         dst->nested_cr3           = from->nested_cr3;
3269         dst->virt_ext              = from->virt_ext;
3270         dst->pause_filter_count   = from->pause_filter_count;
3271         dst->pause_filter_thresh  = from->pause_filter_thresh;
3272 }
3273
3274 static int nested_svm_vmexit(struct vcpu_svm *svm)
3275 {
3276         int rc;
3277         struct vmcb *nested_vmcb;
3278         struct vmcb *hsave = svm->nested.hsave;
3279         struct vmcb *vmcb = svm->vmcb;
3280         struct kvm_host_map map;
3281
3282         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3283                                        vmcb->control.exit_info_1,
3284                                        vmcb->control.exit_info_2,
3285                                        vmcb->control.exit_int_info,
3286                                        vmcb->control.exit_int_info_err,
3287                                        KVM_ISA_SVM);
3288
3289         rc = kvm_vcpu_map(&svm->vcpu, gfn_to_gpa(svm->nested.vmcb), &map);
3290         if (rc) {
3291                 if (rc == -EINVAL)
3292                         kvm_inject_gp(&svm->vcpu, 0);
3293                 return 1;
3294         }
3295
3296         nested_vmcb = map.hva;
3297
3298         /* Exit Guest-Mode */
3299         leave_guest_mode(&svm->vcpu);
3300         svm->nested.vmcb = 0;
3301
3302         /* Give the current vmcb to the guest */
3303         disable_gif(svm);
3304
3305         nested_vmcb->save.es     = vmcb->save.es;
3306         nested_vmcb->save.cs     = vmcb->save.cs;
3307         nested_vmcb->save.ss     = vmcb->save.ss;
3308         nested_vmcb->save.ds     = vmcb->save.ds;
3309         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3310         nested_vmcb->save.idtr   = vmcb->save.idtr;
3311         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3312         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3313         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3314         nested_vmcb->save.cr2    = vmcb->save.cr2;
3315         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3316         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3317         nested_vmcb->save.rip    = vmcb->save.rip;
3318         nested_vmcb->save.rsp    = vmcb->save.rsp;
3319         nested_vmcb->save.rax    = vmcb->save.rax;
3320         nested_vmcb->save.dr7    = vmcb->save.dr7;
3321         nested_vmcb->save.dr6    = vmcb->save.dr6;
3322         nested_vmcb->save.cpl    = vmcb->save.cpl;
3323
3324         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3325         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3326         nested_vmcb->control.int_state         = vmcb->control.int_state;
3327         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3328         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3329         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3330         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3331         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3332         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3333
3334         if (svm->nrips_enabled)
3335                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3336
3337         /*
3338          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3339          * to make sure that we do not lose injected events. So check event_inj
3340          * here and copy it to exit_int_info if it is valid.
3341          * Exit_int_info and event_inj can't be both valid because the case
3342          * below only happens on a VMRUN instruction intercept which has
3343          * no valid exit_int_info set.
3344          */
3345         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3346                 struct vmcb_control_area *nc = &nested_vmcb->control;
3347
3348                 nc->exit_int_info     = vmcb->control.event_inj;
3349                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3350         }
3351
3352         nested_vmcb->control.tlb_ctl           = 0;
3353         nested_vmcb->control.event_inj         = 0;
3354         nested_vmcb->control.event_inj_err     = 0;
3355
3356         nested_vmcb->control.pause_filter_count =
3357                 svm->vmcb->control.pause_filter_count;
3358         nested_vmcb->control.pause_filter_thresh =
3359                 svm->vmcb->control.pause_filter_thresh;
3360
3361         /* We always set V_INTR_MASKING and remember the old value in hflags */
3362         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3363                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3364
3365         /* Restore the original control entries */
3366         copy_vmcb_control_area(vmcb, hsave);
3367
3368         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3369         kvm_clear_exception_queue(&svm->vcpu);
3370         kvm_clear_interrupt_queue(&svm->vcpu);
3371
3372         svm->nested.nested_cr3 = 0;
3373
3374         /* Restore selected save entries */
3375         svm->vmcb->save.es = hsave->save.es;
3376         svm->vmcb->save.cs = hsave->save.cs;
3377         svm->vmcb->save.ss = hsave->save.ss;
3378         svm->vmcb->save.ds = hsave->save.ds;
3379         svm->vmcb->save.gdtr = hsave->save.gdtr;
3380         svm->vmcb->save.idtr = hsave->save.idtr;
3381         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3382         svm_set_efer(&svm->vcpu, hsave->save.efer);
3383         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3384         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3385         if (npt_enabled) {
3386                 svm->vmcb->save.cr3 = hsave->save.cr3;
3387                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3388         } else {
3389                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3390         }
3391         kvm_rax_write(&svm->vcpu, hsave->save.rax);
3392         kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3393         kvm_rip_write(&svm->vcpu, hsave->save.rip);
3394         svm->vmcb->save.dr7 = 0;
3395         svm->vmcb->save.cpl = 0;
3396         svm->vmcb->control.exit_int_info = 0;
3397
3398         mark_all_dirty(svm->vmcb);
3399
3400         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3401
3402         nested_svm_uninit_mmu_context(&svm->vcpu);
3403         kvm_mmu_reset_context(&svm->vcpu);
3404         kvm_mmu_load(&svm->vcpu);
3405
3406         /*
3407          * Drop what we picked up for L2 via svm_complete_interrupts() so it
3408          * doesn't end up in L1.
3409          */
3410         svm->vcpu.arch.nmi_injected = false;
3411         kvm_clear_exception_queue(&svm->vcpu);
3412         kvm_clear_interrupt_queue(&svm->vcpu);
3413
3414         return 0;
3415 }
3416
3417 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3418 {
3419         /*
3420          * This function merges the msr permission bitmaps of kvm and the
3421          * nested vmcb. It is optimized in that it only merges the parts where
3422          * the kvm msr permission bitmap may contain zero bits
3423          */
3424         int i;
3425
3426         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3427                 return true;
3428
3429         for (i = 0; i < MSRPM_OFFSETS; i++) {
3430                 u32 value, p;
3431                 u64 offset;
3432
3433                 if (msrpm_offsets[i] == 0xffffffff)
3434                         break;
3435
3436                 p      = msrpm_offsets[i];
3437                 offset = svm->nested.vmcb_msrpm + (p * 4);
3438
3439                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3440                         return false;
3441
3442                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3443         }
3444
3445         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3446
3447         return true;
3448 }
3449
3450 static bool nested_vmcb_checks(struct vmcb *vmcb)
3451 {
3452         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3453                 return false;
3454
3455         if (vmcb->control.asid == 0)
3456                 return false;
3457
3458         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3459             !npt_enabled)
3460                 return false;
3461
3462         return true;
3463 }
3464
3465 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3466                                  struct vmcb *nested_vmcb, struct kvm_host_map *map)
3467 {
3468         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3469                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3470         else
3471                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3472
3473         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3474                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3475                 nested_svm_init_mmu_context(&svm->vcpu);
3476         }
3477
3478         /* Load the nested guest state */
3479         svm->vmcb->save.es = nested_vmcb->save.es;
3480         svm->vmcb->save.cs = nested_vmcb->save.cs;
3481         svm->vmcb->save.ss = nested_vmcb->save.ss;
3482         svm->vmcb->save.ds = nested_vmcb->save.ds;
3483         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3484         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3485         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3486         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3487         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3488         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3489         if (npt_enabled) {
3490                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3491                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3492         } else
3493                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3494
3495         /* Guest paging mode is active - reset mmu */
3496         kvm_mmu_reset_context(&svm->vcpu);
3497
3498         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3499         kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3500         kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3501         kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3502
3503         /* In case we don't even reach vcpu_run, the fields are not updated */
3504         svm->vmcb->save.rax = nested_vmcb->save.rax;
3505         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3506         svm->vmcb->save.rip = nested_vmcb->save.rip;
3507         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3508         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3509         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3510
3511         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3512         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3513
3514         /* cache intercepts */
3515         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3516         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3517         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3518         svm->nested.intercept            = nested_vmcb->control.intercept;
3519
3520         svm_flush_tlb(&svm->vcpu, true);
3521         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3522         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3523                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3524         else
3525                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3526
3527         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3528                 /* We only want the cr8 intercept bits of the guest */
3529                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3530                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3531         }
3532
3533         /* We don't want to see VMMCALLs from a nested guest */
3534         clr_intercept(svm, INTERCEPT_VMMCALL);
3535
3536         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3537         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3538
3539         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3540         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3541         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3542         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3543         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3544
3545         svm->vmcb->control.pause_filter_count =
3546                 nested_vmcb->control.pause_filter_count;
3547         svm->vmcb->control.pause_filter_thresh =
3548                 nested_vmcb->control.pause_filter_thresh;
3549
3550         kvm_vcpu_unmap(&svm->vcpu, map, true);
3551
3552         /* Enter Guest-Mode */
3553         enter_guest_mode(&svm->vcpu);
3554
3555         /*
3556          * Merge guest and host intercepts - must be called  with vcpu in
3557          * guest-mode to take affect here
3558          */
3559         recalc_intercepts(svm);
3560
3561         svm->nested.vmcb = vmcb_gpa;
3562
3563         enable_gif(svm);
3564
3565         mark_all_dirty(svm->vmcb);
3566 }
3567
3568 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3569 {
3570         int rc;
3571         struct vmcb *nested_vmcb;
3572         struct vmcb *hsave = svm->nested.hsave;
3573         struct vmcb *vmcb = svm->vmcb;
3574         struct kvm_host_map map;
3575         u64 vmcb_gpa;
3576
3577         vmcb_gpa = svm->vmcb->save.rax;
3578
3579         rc = kvm_vcpu_map(&svm->vcpu, gfn_to_gpa(vmcb_gpa), &map);
3580         if (rc) {
3581                 if (rc == -EINVAL)
3582                         kvm_inject_gp(&svm->vcpu, 0);
3583                 return false;
3584         }
3585
3586         nested_vmcb = map.hva;
3587
3588         if (!nested_vmcb_checks(nested_vmcb)) {
3589                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3590                 nested_vmcb->control.exit_code_hi = 0;
3591                 nested_vmcb->control.exit_info_1  = 0;
3592                 nested_vmcb->control.exit_info_2  = 0;
3593
3594                 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3595
3596                 return false;
3597         }
3598
3599         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3600                                nested_vmcb->save.rip,
3601                                nested_vmcb->control.int_ctl,
3602                                nested_vmcb->control.event_inj,
3603                                nested_vmcb->control.nested_ctl);
3604
3605         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3606                                     nested_vmcb->control.intercept_cr >> 16,
3607                                     nested_vmcb->control.intercept_exceptions,
3608                                     nested_vmcb->control.intercept);
3609
3610         /* Clear internal status */
3611         kvm_clear_exception_queue(&svm->vcpu);
3612         kvm_clear_interrupt_queue(&svm->vcpu);
3613
3614         /*
3615          * Save the old vmcb, so we don't need to pick what we save, but can
3616          * restore everything when a VMEXIT occurs
3617          */
3618         hsave->save.es     = vmcb->save.es;
3619         hsave->save.cs     = vmcb->save.cs;
3620         hsave->save.ss     = vmcb->save.ss;
3621         hsave->save.ds     = vmcb->save.ds;
3622         hsave->save.gdtr   = vmcb->save.gdtr;
3623         hsave->save.idtr   = vmcb->save.idtr;
3624         hsave->save.efer   = svm->vcpu.arch.efer;
3625         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3626         hsave->save.cr4    = svm->vcpu.arch.cr4;
3627         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3628         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3629         hsave->save.rsp    = vmcb->save.rsp;
3630         hsave->save.rax    = vmcb->save.rax;
3631         if (npt_enabled)
3632                 hsave->save.cr3    = vmcb->save.cr3;
3633         else
3634                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3635
3636         copy_vmcb_control_area(hsave, vmcb);
3637
3638         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3639
3640         return true;
3641 }
3642
3643 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3644 {
3645         to_vmcb->save.fs = from_vmcb->save.fs;
3646         to_vmcb->save.gs = from_vmcb->save.gs;
3647         to_vmcb->save.tr = from_vmcb->save.tr;
3648         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3649         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3650         to_vmcb->save.star = from_vmcb->save.star;
3651         to_vmcb->save.lstar = from_vmcb->save.lstar;
3652         to_vmcb->save.cstar = from_vmcb->save.cstar;
3653         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3654         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3655         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3656         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3657 }
3658
3659 static int vmload_interception(struct vcpu_svm *svm)
3660 {
3661         struct vmcb *nested_vmcb;
3662         struct kvm_host_map map;
3663         int ret;
3664
3665         if (nested_svm_check_permissions(svm))
3666                 return 1;
3667
3668         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3669         if (ret) {
3670                 if (ret == -EINVAL)
3671                         kvm_inject_gp(&svm->vcpu, 0);
3672                 return 1;
3673         }
3674
3675         nested_vmcb = map.hva;
3676
3677         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3678         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3679
3680         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3681         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3682
3683         return ret;
3684 }
3685
3686 static int vmsave_interception(struct vcpu_svm *svm)
3687 {
3688         struct vmcb *nested_vmcb;
3689         struct kvm_host_map map;
3690         int ret;
3691
3692         if (nested_svm_check_permissions(svm))
3693                 return 1;
3694
3695         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3696         if (ret) {
3697                 if (ret == -EINVAL)
3698                         kvm_inject_gp(&svm->vcpu, 0);
3699                 return 1;
3700         }
3701
3702         nested_vmcb = map.hva;
3703
3704         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3705         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3706
3707         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3708         kvm_vcpu_unmap(&svm->vcpu, &map, true);
3709
3710         return ret;
3711 }
3712
3713 static int vmrun_interception(struct vcpu_svm *svm)
3714 {
3715         if (nested_svm_check_permissions(svm))
3716                 return 1;
3717
3718         /* Save rip after vmrun instruction */
3719         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3720
3721         if (!nested_svm_vmrun(svm))
3722                 return 1;
3723
3724         if (!nested_svm_vmrun_msrpm(svm))
3725                 goto failed;
3726
3727         return 1;
3728
3729 failed:
3730
3731         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3732         svm->vmcb->control.exit_code_hi = 0;
3733         svm->vmcb->control.exit_info_1  = 0;
3734         svm->vmcb->control.exit_info_2  = 0;
3735
3736         nested_svm_vmexit(svm);
3737
3738         return 1;
3739 }
3740
3741 static int stgi_interception(struct vcpu_svm *svm)
3742 {
3743         int ret;
3744
3745         if (nested_svm_check_permissions(svm))
3746                 return 1;
3747
3748         /*
3749          * If VGIF is enabled, the STGI intercept is only added to
3750          * detect the opening of the SMI/NMI window; remove it now.
3751          */
3752         if (vgif_enabled(svm))
3753                 clr_intercept(svm, INTERCEPT_STGI);
3754
3755         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3756         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3757         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3758
3759         enable_gif(svm);
3760
3761         return ret;
3762 }
3763
3764 static int clgi_interception(struct vcpu_svm *svm)
3765 {
3766         int ret;
3767
3768         if (nested_svm_check_permissions(svm))
3769                 return 1;
3770
3771         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3772         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3773
3774         disable_gif(svm);
3775
3776         /* After a CLGI no interrupts should come */
3777         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3778                 svm_clear_vintr(svm);
3779                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3780                 mark_dirty(svm->vmcb, VMCB_INTR);
3781         }
3782
3783         return ret;
3784 }
3785
3786 static int invlpga_interception(struct vcpu_svm *svm)
3787 {
3788         struct kvm_vcpu *vcpu = &svm->vcpu;
3789
3790         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3791                           kvm_rax_read(&svm->vcpu));
3792
3793         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3794         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3795
3796         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3797         return kvm_skip_emulated_instruction(&svm->vcpu);
3798 }
3799
3800 static int skinit_interception(struct vcpu_svm *svm)
3801 {
3802         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3803
3804         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3805         return 1;
3806 }
3807
3808 static int wbinvd_interception(struct vcpu_svm *svm)
3809 {
3810         return kvm_emulate_wbinvd(&svm->vcpu);
3811 }
3812
3813 static int xsetbv_interception(struct vcpu_svm *svm)
3814 {
3815         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3816         u32 index = kvm_rcx_read(&svm->vcpu);
3817
3818         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3819                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3820                 return kvm_skip_emulated_instruction(&svm->vcpu);
3821         }
3822
3823         return 1;
3824 }
3825
3826 static int task_switch_interception(struct vcpu_svm *svm)
3827 {
3828         u16 tss_selector;
3829         int reason;
3830         int int_type = svm->vmcb->control.exit_int_info &
3831                 SVM_EXITINTINFO_TYPE_MASK;
3832         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3833         uint32_t type =
3834                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3835         uint32_t idt_v =
3836                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3837         bool has_error_code = false;
3838         u32 error_code = 0;
3839
3840         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3841
3842         if (svm->vmcb->control.exit_info_2 &
3843             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3844                 reason = TASK_SWITCH_IRET;
3845         else if (svm->vmcb->control.exit_info_2 &
3846                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3847                 reason = TASK_SWITCH_JMP;
3848         else if (idt_v)
3849                 reason = TASK_SWITCH_GATE;
3850         else
3851                 reason = TASK_SWITCH_CALL;
3852
3853         if (reason == TASK_SWITCH_GATE) {
3854                 switch (type) {
3855                 case SVM_EXITINTINFO_TYPE_NMI:
3856                         svm->vcpu.arch.nmi_injected = false;
3857                         break;
3858                 case SVM_EXITINTINFO_TYPE_EXEPT:
3859                         if (svm->vmcb->control.exit_info_2 &
3860                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3861                                 has_error_code = true;
3862                                 error_code =
3863                                         (u32)svm->vmcb->control.exit_info_2;
3864                         }
3865                         kvm_clear_exception_queue(&svm->vcpu);
3866                         break;
3867                 case SVM_EXITINTINFO_TYPE_INTR:
3868                         kvm_clear_interrupt_queue(&svm->vcpu);
3869                         break;
3870                 default:
3871                         break;
3872                 }
3873         }
3874
3875         if (reason != TASK_SWITCH_GATE ||
3876             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3877             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3878              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3879                 skip_emulated_instruction(&svm->vcpu);
3880
3881         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3882                 int_vec = -1;
3883
3884         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3885                                 has_error_code, error_code) == EMULATE_FAIL) {
3886                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3887                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3888                 svm->vcpu.run->internal.ndata = 0;
3889                 return 0;
3890         }
3891         return 1;
3892 }
3893
3894 static int cpuid_interception(struct vcpu_svm *svm)
3895 {
3896         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3897         return kvm_emulate_cpuid(&svm->vcpu);
3898 }
3899
3900 static int iret_interception(struct vcpu_svm *svm)
3901 {
3902         ++svm->vcpu.stat.nmi_window_exits;
3903         clr_intercept(svm, INTERCEPT_IRET);
3904         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3905         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3906         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3907         return 1;
3908 }
3909
3910 static int invlpg_interception(struct vcpu_svm *svm)
3911 {
3912         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3913                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3914
3915         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3916         return kvm_skip_emulated_instruction(&svm->vcpu);
3917 }
3918
3919 static int emulate_on_interception(struct vcpu_svm *svm)
3920 {
3921         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3922 }
3923
3924 static int rsm_interception(struct vcpu_svm *svm)
3925 {
3926         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3927                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3928 }
3929
3930 static int rdpmc_interception(struct vcpu_svm *svm)
3931 {
3932         int err;
3933
3934         if (!static_cpu_has(X86_FEATURE_NRIPS))
3935                 return emulate_on_interception(svm);
3936
3937         err = kvm_rdpmc(&svm->vcpu);
3938         return kvm_complete_insn_gp(&svm->vcpu, err);
3939 }
3940
3941 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3942                                             unsigned long val)
3943 {
3944         unsigned long cr0 = svm->vcpu.arch.cr0;
3945         bool ret = false;
3946         u64 intercept;
3947
3948         intercept = svm->nested.intercept;
3949
3950         if (!is_guest_mode(&svm->vcpu) ||
3951             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3952                 return false;
3953
3954         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3955         val &= ~SVM_CR0_SELECTIVE_MASK;
3956
3957         if (cr0 ^ val) {
3958                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3959                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3960         }
3961
3962         return ret;
3963 }
3964
3965 #define CR_VALID (1ULL << 63)
3966
3967 static int cr_interception(struct vcpu_svm *svm)
3968 {
3969         int reg, cr;
3970         unsigned long val;
3971         int err;
3972
3973         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3974                 return emulate_on_interception(svm);
3975
3976         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3977                 return emulate_on_interception(svm);
3978
3979         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3980         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3981                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3982         else
3983                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3984
3985         err = 0;
3986         if (cr >= 16) { /* mov to cr */
3987                 cr -= 16;
3988                 val = kvm_register_read(&svm->vcpu, reg);
3989                 switch (cr) {
3990                 case 0:
3991                         if (!check_selective_cr0_intercepted(svm, val))
3992                                 err = kvm_set_cr0(&svm->vcpu, val);
3993                         else
3994                                 return 1;
3995
3996                         break;
3997                 case 3:
3998                         err = kvm_set_cr3(&svm->vcpu, val);
3999                         break;
4000                 case 4:
4001                         err = kvm_set_cr4(&svm->vcpu, val);
4002                         break;
4003                 case 8:
4004                         err = kvm_set_cr8(&svm->vcpu, val);
4005                         break;
4006                 default:
4007                         WARN(1, "unhandled write to CR%d", cr);
4008                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4009                         return 1;
4010                 }
4011         } else { /* mov from cr */
4012                 switch (cr) {
4013                 case 0:
4014                         val = kvm_read_cr0(&svm->vcpu);
4015                         break;
4016                 case 2:
4017                         val = svm->vcpu.arch.cr2;
4018                         break;
4019                 case 3:
4020                         val = kvm_read_cr3(&svm->vcpu);
4021                         break;
4022                 case 4:
4023                         val = kvm_read_cr4(&svm->vcpu);
4024                         break;
4025                 case 8:
4026                         val = kvm_get_cr8(&svm->vcpu);
4027                         break;
4028                 default:
4029                         WARN(1, "unhandled read from CR%d", cr);
4030                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4031                         return 1;
4032                 }
4033                 kvm_register_write(&svm->vcpu, reg, val);
4034         }
4035         return kvm_complete_insn_gp(&svm->vcpu, err);
4036 }
4037
4038 static int dr_interception(struct vcpu_svm *svm)
4039 {
4040         int reg, dr;
4041         unsigned long val;
4042
4043         if (svm->vcpu.guest_debug == 0) {
4044                 /*
4045                  * No more DR vmexits; force a reload of the debug registers
4046                  * and reenter on this instruction.  The next vmexit will
4047                  * retrieve the full state of the debug registers.
4048                  */
4049                 clr_dr_intercepts(svm);
4050                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4051                 return 1;
4052         }
4053
4054         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4055                 return emulate_on_interception(svm);
4056
4057         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4058         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4059
4060         if (dr >= 16) { /* mov to DRn */
4061                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4062                         return 1;
4063                 val = kvm_register_read(&svm->vcpu, reg);
4064                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4065         } else {
4066                 if (!kvm_require_dr(&svm->vcpu, dr))
4067                         return 1;
4068                 kvm_get_dr(&svm->vcpu, dr, &val);
4069                 kvm_register_write(&svm->vcpu, reg, val);
4070         }
4071
4072         return kvm_skip_emulated_instruction(&svm->vcpu);
4073 }
4074
4075 static int cr8_write_interception(struct vcpu_svm *svm)
4076 {
4077         struct kvm_run *kvm_run = svm->vcpu.run;
4078         int r;
4079
4080         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4081         /* instruction emulation calls kvm_set_cr8() */
4082         r = cr_interception(svm);
4083         if (lapic_in_kernel(&svm->vcpu))
4084                 return r;
4085         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4086                 return r;
4087         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4088         return 0;
4089 }
4090
4091 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4092 {
4093         msr->data = 0;
4094
4095         switch (msr->index) {
4096         case MSR_F10H_DECFG:
4097                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4098                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4099                 break;
4100         default:
4101                 return 1;
4102         }
4103
4104         return 0;
4105 }
4106
4107 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4108 {
4109         struct vcpu_svm *svm = to_svm(vcpu);
4110
4111         switch (msr_info->index) {
4112         case MSR_STAR:
4113                 msr_info->data = svm->vmcb->save.star;
4114                 break;
4115 #ifdef CONFIG_X86_64
4116         case MSR_LSTAR:
4117                 msr_info->data = svm->vmcb->save.lstar;
4118                 break;
4119         case MSR_CSTAR:
4120                 msr_info->data = svm->vmcb->save.cstar;
4121                 break;
4122         case MSR_KERNEL_GS_BASE:
4123                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4124                 break;
4125         case MSR_SYSCALL_MASK:
4126                 msr_info->data = svm->vmcb->save.sfmask;
4127                 break;
4128 #endif
4129         case MSR_IA32_SYSENTER_CS:
4130                 msr_info->data = svm->vmcb->save.sysenter_cs;
4131                 break;
4132         case MSR_IA32_SYSENTER_EIP:
4133                 msr_info->data = svm->sysenter_eip;
4134                 break;
4135         case MSR_IA32_SYSENTER_ESP:
4136                 msr_info->data = svm->sysenter_esp;
4137                 break;
4138         case MSR_TSC_AUX:
4139                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4140                         return 1;
4141                 msr_info->data = svm->tsc_aux;
4142                 break;
4143         /*
4144          * Nobody will change the following 5 values in the VMCB so we can
4145          * safely return them on rdmsr. They will always be 0 until LBRV is
4146          * implemented.
4147          */
4148         case MSR_IA32_DEBUGCTLMSR:
4149                 msr_info->data = svm->vmcb->save.dbgctl;
4150                 break;
4151         case MSR_IA32_LASTBRANCHFROMIP:
4152                 msr_info->data = svm->vmcb->save.br_from;
4153                 break;
4154         case MSR_IA32_LASTBRANCHTOIP:
4155                 msr_info->data = svm->vmcb->save.br_to;
4156                 break;
4157         case MSR_IA32_LASTINTFROMIP:
4158                 msr_info->data = svm->vmcb->save.last_excp_from;
4159                 break;
4160         case MSR_IA32_LASTINTTOIP:
4161                 msr_info->data = svm->vmcb->save.last_excp_to;
4162                 break;
4163         case MSR_VM_HSAVE_PA:
4164                 msr_info->data = svm->nested.hsave_msr;
4165                 break;
4166         case MSR_VM_CR:
4167                 msr_info->data = svm->nested.vm_cr_msr;
4168                 break;
4169         case MSR_IA32_SPEC_CTRL:
4170                 if (!msr_info->host_initiated &&
4171                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4172                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4173                         return 1;
4174
4175                 msr_info->data = svm->spec_ctrl;
4176                 break;
4177         case MSR_AMD64_VIRT_SPEC_CTRL:
4178                 if (!msr_info->host_initiated &&
4179                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4180                         return 1;
4181
4182                 msr_info->data = svm->virt_spec_ctrl;
4183                 break;
4184         case MSR_F15H_IC_CFG: {
4185
4186                 int family, model;
4187
4188                 family = guest_cpuid_family(vcpu);
4189                 model  = guest_cpuid_model(vcpu);
4190
4191                 if (family < 0 || model < 0)
4192                         return kvm_get_msr_common(vcpu, msr_info);
4193
4194                 msr_info->data = 0;
4195
4196                 if (family == 0x15 &&
4197                     (model >= 0x2 && model < 0x20))
4198                         msr_info->data = 0x1E;
4199                 }
4200                 break;
4201         case MSR_F10H_DECFG:
4202                 msr_info->data = svm->msr_decfg;
4203                 break;
4204         default:
4205                 return kvm_get_msr_common(vcpu, msr_info);
4206         }
4207         return 0;
4208 }
4209
4210 static int rdmsr_interception(struct vcpu_svm *svm)
4211 {
4212         u32 ecx = kvm_rcx_read(&svm->vcpu);
4213         struct msr_data msr_info;
4214
4215         msr_info.index = ecx;
4216         msr_info.host_initiated = false;
4217         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4218                 trace_kvm_msr_read_ex(ecx);
4219                 kvm_inject_gp(&svm->vcpu, 0);
4220                 return 1;
4221         } else {
4222                 trace_kvm_msr_read(ecx, msr_info.data);
4223
4224                 kvm_rax_write(&svm->vcpu, msr_info.data & 0xffffffff);
4225                 kvm_rdx_write(&svm->vcpu, msr_info.data >> 32);
4226                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4227                 return kvm_skip_emulated_instruction(&svm->vcpu);
4228         }
4229 }
4230
4231 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4232 {
4233         struct vcpu_svm *svm = to_svm(vcpu);
4234         int svm_dis, chg_mask;
4235
4236         if (data & ~SVM_VM_CR_VALID_MASK)
4237                 return 1;
4238
4239         chg_mask = SVM_VM_CR_VALID_MASK;
4240
4241         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4242                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4243
4244         svm->nested.vm_cr_msr &= ~chg_mask;
4245         svm->nested.vm_cr_msr |= (data & chg_mask);
4246
4247         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4248
4249         /* check for svm_disable while efer.svme is set */
4250         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4251                 return 1;
4252
4253         return 0;
4254 }
4255
4256 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4257 {
4258         struct vcpu_svm *svm = to_svm(vcpu);
4259
4260         u32 ecx = msr->index;
4261         u64 data = msr->data;
4262         switch (ecx) {
4263         case MSR_IA32_CR_PAT:
4264                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4265                         return 1;
4266                 vcpu->arch.pat = data;
4267                 svm->vmcb->save.g_pat = data;
4268                 mark_dirty(svm->vmcb, VMCB_NPT);
4269                 break;
4270         case MSR_IA32_SPEC_CTRL:
4271                 if (!msr->host_initiated &&
4272                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4273                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4274                         return 1;
4275
4276                 /* The STIBP bit doesn't fault even if it's not advertised */
4277                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4278                         return 1;
4279
4280                 svm->spec_ctrl = data;
4281
4282                 if (!data)
4283                         break;
4284
4285                 /*
4286                  * For non-nested:
4287                  * When it's written (to non-zero) for the first time, pass
4288                  * it through.
4289                  *
4290                  * For nested:
4291                  * The handling of the MSR bitmap for L2 guests is done in
4292                  * nested_svm_vmrun_msrpm.
4293                  * We update the L1 MSR bit as well since it will end up
4294                  * touching the MSR anyway now.
4295                  */
4296                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4297                 break;
4298         case MSR_IA32_PRED_CMD:
4299                 if (!msr->host_initiated &&
4300                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4301                         return 1;
4302
4303                 if (data & ~PRED_CMD_IBPB)
4304                         return 1;
4305
4306                 if (!data)
4307                         break;
4308
4309                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4310                 if (is_guest_mode(vcpu))
4311                         break;
4312                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4313                 break;
4314         case MSR_AMD64_VIRT_SPEC_CTRL:
4315                 if (!msr->host_initiated &&
4316                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4317                         return 1;
4318
4319                 if (data & ~SPEC_CTRL_SSBD)
4320                         return 1;
4321
4322                 svm->virt_spec_ctrl = data;
4323                 break;
4324         case MSR_STAR:
4325                 svm->vmcb->save.star = data;
4326                 break;
4327 #ifdef CONFIG_X86_64
4328         case MSR_LSTAR:
4329                 svm->vmcb->save.lstar = data;
4330                 break;
4331         case MSR_CSTAR:
4332                 svm->vmcb->save.cstar = data;
4333                 break;
4334         case MSR_KERNEL_GS_BASE:
4335                 svm->vmcb->save.kernel_gs_base = data;
4336                 break;
4337         case MSR_SYSCALL_MASK:
4338                 svm->vmcb->save.sfmask = data;
4339                 break;
4340 #endif
4341         case MSR_IA32_SYSENTER_CS:
4342                 svm->vmcb->save.sysenter_cs = data;
4343                 break;
4344         case MSR_IA32_SYSENTER_EIP:
4345                 svm->sysenter_eip = data;
4346                 svm->vmcb->save.sysenter_eip = data;
4347                 break;
4348         case MSR_IA32_SYSENTER_ESP:
4349                 svm->sysenter_esp = data;
4350                 svm->vmcb->save.sysenter_esp = data;
4351                 break;
4352         case MSR_TSC_AUX:
4353                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4354                         return 1;
4355
4356                 /*
4357                  * This is rare, so we update the MSR here instead of using
4358                  * direct_access_msrs.  Doing that would require a rdmsr in
4359                  * svm_vcpu_put.
4360                  */
4361                 svm->tsc_aux = data;
4362                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4363                 break;
4364         case MSR_IA32_DEBUGCTLMSR:
4365                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4366                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4367                                     __func__, data);
4368                         break;
4369                 }
4370                 if (data & DEBUGCTL_RESERVED_BITS)
4371                         return 1;
4372
4373                 svm->vmcb->save.dbgctl = data;
4374                 mark_dirty(svm->vmcb, VMCB_LBR);
4375                 if (data & (1ULL<<0))
4376                         svm_enable_lbrv(svm);
4377                 else
4378                         svm_disable_lbrv(svm);
4379                 break;
4380         case MSR_VM_HSAVE_PA:
4381                 svm->nested.hsave_msr = data;
4382                 break;
4383         case MSR_VM_CR:
4384                 return svm_set_vm_cr(vcpu, data);
4385         case MSR_VM_IGNNE:
4386                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4387                 break;
4388         case MSR_F10H_DECFG: {
4389                 struct kvm_msr_entry msr_entry;
4390
4391                 msr_entry.index = msr->index;
4392                 if (svm_get_msr_feature(&msr_entry))
4393                         return 1;
4394
4395                 /* Check the supported bits */
4396                 if (data & ~msr_entry.data)
4397                         return 1;
4398
4399                 /* Don't allow the guest to change a bit, #GP */
4400                 if (!msr->host_initiated && (data ^ msr_entry.data))
4401                         return 1;
4402
4403                 svm->msr_decfg = data;
4404                 break;
4405         }
4406         case MSR_IA32_APICBASE:
4407                 if (kvm_vcpu_apicv_active(vcpu))
4408                         avic_update_vapic_bar(to_svm(vcpu), data);
4409                 /* Fall through */
4410         default:
4411                 return kvm_set_msr_common(vcpu, msr);
4412         }
4413         return 0;
4414 }
4415
4416 static int wrmsr_interception(struct vcpu_svm *svm)
4417 {
4418         struct msr_data msr;
4419         u32 ecx = kvm_rcx_read(&svm->vcpu);
4420         u64 data = kvm_read_edx_eax(&svm->vcpu);
4421
4422         msr.data = data;
4423         msr.index = ecx;
4424         msr.host_initiated = false;
4425
4426         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4427         if (kvm_set_msr(&svm->vcpu, &msr)) {
4428                 trace_kvm_msr_write_ex(ecx, data);
4429                 kvm_inject_gp(&svm->vcpu, 0);
4430                 return 1;
4431         } else {
4432                 trace_kvm_msr_write(ecx, data);
4433                 return kvm_skip_emulated_instruction(&svm->vcpu);
4434         }
4435 }
4436
4437 static int msr_interception(struct vcpu_svm *svm)
4438 {
4439         if (svm->vmcb->control.exit_info_1)
4440                 return wrmsr_interception(svm);
4441         else
4442                 return rdmsr_interception(svm);
4443 }
4444
4445 static int interrupt_window_interception(struct vcpu_svm *svm)
4446 {
4447         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4448         svm_clear_vintr(svm);
4449         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4450         mark_dirty(svm->vmcb, VMCB_INTR);
4451         ++svm->vcpu.stat.irq_window_exits;
4452         return 1;
4453 }
4454
4455 static int pause_interception(struct vcpu_svm *svm)
4456 {
4457         struct kvm_vcpu *vcpu = &svm->vcpu;
4458         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4459
4460         if (pause_filter_thresh)
4461                 grow_ple_window(vcpu);
4462
4463         kvm_vcpu_on_spin(vcpu, in_kernel);
4464         return 1;
4465 }
4466
4467 static int nop_interception(struct vcpu_svm *svm)
4468 {
4469         return kvm_skip_emulated_instruction(&(svm->vcpu));
4470 }
4471
4472 static int monitor_interception(struct vcpu_svm *svm)
4473 {
4474         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4475         return nop_interception(svm);
4476 }
4477
4478 static int mwait_interception(struct vcpu_svm *svm)
4479 {
4480         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4481         return nop_interception(svm);
4482 }
4483
4484 enum avic_ipi_failure_cause {
4485         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4486         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4487         AVIC_IPI_FAILURE_INVALID_TARGET,
4488         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4489 };
4490
4491 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4492 {
4493         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4494         u32 icrl = svm->vmcb->control.exit_info_1;
4495         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4496         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4497         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4498
4499         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4500
4501         switch (id) {
4502         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4503                 /*
4504                  * AVIC hardware handles the generation of
4505                  * IPIs when the specified Message Type is Fixed
4506                  * (also known as fixed delivery mode) and
4507                  * the Trigger Mode is edge-triggered. The hardware
4508                  * also supports self and broadcast delivery modes
4509                  * specified via the Destination Shorthand(DSH)
4510                  * field of the ICRL. Logical and physical APIC ID
4511                  * formats are supported. All other IPI types cause
4512                  * a #VMEXIT, which needs to emulated.
4513                  */
4514                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4515                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4516                 break;
4517         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4518                 int i;
4519                 struct kvm_vcpu *vcpu;
4520                 struct kvm *kvm = svm->vcpu.kvm;
4521                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4522
4523                 /*
4524                  * At this point, we expect that the AVIC HW has already
4525                  * set the appropriate IRR bits on the valid target
4526                  * vcpus. So, we just need to kick the appropriate vcpu.
4527                  */
4528                 kvm_for_each_vcpu(i, vcpu, kvm) {
4529                         bool m = kvm_apic_match_dest(vcpu, apic,
4530                                                      icrl & KVM_APIC_SHORT_MASK,
4531                                                      GET_APIC_DEST_FIELD(icrh),
4532                                                      icrl & KVM_APIC_DEST_MASK);
4533
4534                         if (m && !avic_vcpu_is_running(vcpu))
4535                                 kvm_vcpu_wake_up(vcpu);
4536                 }
4537                 break;
4538         }
4539         case AVIC_IPI_FAILURE_INVALID_TARGET:
4540                 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4541                           index, svm->vcpu.vcpu_id, icrh, icrl);
4542                 break;
4543         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4544                 WARN_ONCE(1, "Invalid backing page\n");
4545                 break;
4546         default:
4547                 pr_err("Unknown IPI interception\n");
4548         }
4549
4550         return 1;
4551 }
4552
4553 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4554 {
4555         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4556         int index;
4557         u32 *logical_apic_id_table;
4558         int dlid = GET_APIC_LOGICAL_ID(ldr);
4559
4560         if (!dlid)
4561                 return NULL;
4562
4563         if (flat) { /* flat */
4564                 index = ffs(dlid) - 1;
4565                 if (index > 7)
4566                         return NULL;
4567         } else { /* cluster */
4568                 int cluster = (dlid & 0xf0) >> 4;
4569                 int apic = ffs(dlid & 0x0f) - 1;
4570
4571                 if ((apic < 0) || (apic > 7) ||
4572                     (cluster >= 0xf))
4573                         return NULL;
4574                 index = (cluster << 2) + apic;
4575         }
4576
4577         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4578
4579         return &logical_apic_id_table[index];
4580 }
4581
4582 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4583 {
4584         bool flat;
4585         u32 *entry, new_entry;
4586
4587         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4588         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4589         if (!entry)
4590                 return -EINVAL;
4591
4592         new_entry = READ_ONCE(*entry);
4593         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4594         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4595         new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4596         WRITE_ONCE(*entry, new_entry);
4597
4598         return 0;
4599 }
4600
4601 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4602 {
4603         struct vcpu_svm *svm = to_svm(vcpu);
4604         bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4605         u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4606
4607         if (entry)
4608                 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4609 }
4610
4611 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4612 {
4613         int ret = 0;
4614         struct vcpu_svm *svm = to_svm(vcpu);
4615         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4616
4617         if (ldr == svm->ldr_reg)
4618                 return 0;
4619
4620         avic_invalidate_logical_id_entry(vcpu);
4621
4622         if (ldr)
4623                 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4624
4625         if (!ret)
4626                 svm->ldr_reg = ldr;
4627
4628         return ret;
4629 }
4630
4631 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4632 {
4633         u64 *old, *new;
4634         struct vcpu_svm *svm = to_svm(vcpu);
4635         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4636         u32 id = (apic_id_reg >> 24) & 0xff;
4637
4638         if (vcpu->vcpu_id == id)
4639                 return 0;
4640
4641         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4642         new = avic_get_physical_id_entry(vcpu, id);
4643         if (!new || !old)
4644                 return 1;
4645
4646         /* We need to move physical_id_entry to new offset */
4647         *new = *old;
4648         *old = 0ULL;
4649         to_svm(vcpu)->avic_physical_id_cache = new;
4650
4651         /*
4652          * Also update the guest physical APIC ID in the logical
4653          * APIC ID table entry if already setup the LDR.
4654          */
4655         if (svm->ldr_reg)
4656                 avic_handle_ldr_update(vcpu);
4657
4658         return 0;
4659 }
4660
4661 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4662 {
4663         struct vcpu_svm *svm = to_svm(vcpu);
4664         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4665
4666         if (svm->dfr_reg == dfr)
4667                 return;
4668
4669         avic_invalidate_logical_id_entry(vcpu);
4670         svm->dfr_reg = dfr;
4671 }
4672
4673 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4674 {
4675         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4676         u32 offset = svm->vmcb->control.exit_info_1 &
4677                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4678
4679         switch (offset) {
4680         case APIC_ID:
4681                 if (avic_handle_apic_id_update(&svm->vcpu))
4682                         return 0;
4683                 break;
4684         case APIC_LDR:
4685                 if (avic_handle_ldr_update(&svm->vcpu))
4686                         return 0;
4687                 break;
4688         case APIC_DFR:
4689                 avic_handle_dfr_update(&svm->vcpu);
4690                 break;
4691         default:
4692                 break;
4693         }
4694
4695         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4696
4697         return 1;
4698 }
4699
4700 static bool is_avic_unaccelerated_access_trap(u32 offset)
4701 {
4702         bool ret = false;
4703
4704         switch (offset) {
4705         case APIC_ID:
4706         case APIC_EOI:
4707         case APIC_RRR:
4708         case APIC_LDR:
4709         case APIC_DFR:
4710         case APIC_SPIV:
4711         case APIC_ESR:
4712         case APIC_ICR:
4713         case APIC_LVTT:
4714         case APIC_LVTTHMR:
4715         case APIC_LVTPC:
4716         case APIC_LVT0:
4717         case APIC_LVT1:
4718         case APIC_LVTERR:
4719         case APIC_TMICT:
4720         case APIC_TDCR:
4721                 ret = true;
4722                 break;
4723         default:
4724                 break;
4725         }
4726         return ret;
4727 }
4728
4729 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4730 {
4731         int ret = 0;
4732         u32 offset = svm->vmcb->control.exit_info_1 &
4733                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4734         u32 vector = svm->vmcb->control.exit_info_2 &
4735                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4736         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4737                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4738         bool trap = is_avic_unaccelerated_access_trap(offset);
4739
4740         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4741                                             trap, write, vector);
4742         if (trap) {
4743                 /* Handling Trap */
4744                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4745                 ret = avic_unaccel_trap_write(svm);
4746         } else {
4747                 /* Handling Fault */
4748                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4749         }
4750
4751         return ret;
4752 }
4753
4754 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4755         [SVM_EXIT_READ_CR0]                     = cr_interception,
4756         [SVM_EXIT_READ_CR3]                     = cr_interception,
4757         [SVM_EXIT_READ_CR4]                     = cr_interception,
4758         [SVM_EXIT_READ_CR8]                     = cr_interception,
4759         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4760         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4761         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4762         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4763         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4764         [SVM_EXIT_READ_DR0]                     = dr_interception,
4765         [SVM_EXIT_READ_DR1]                     = dr_interception,
4766         [SVM_EXIT_READ_DR2]                     = dr_interception,
4767         [SVM_EXIT_READ_DR3]                     = dr_interception,
4768         [SVM_EXIT_READ_DR4]                     = dr_interception,
4769         [SVM_EXIT_READ_DR5]                     = dr_interception,
4770         [SVM_EXIT_READ_DR6]                     = dr_interception,
4771         [SVM_EXIT_READ_DR7]                     = dr_interception,
4772         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4773         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4774         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4775         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4776         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4777         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4778         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4779         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4780         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4781         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4782         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4783         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4784         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4785         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4786         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4787         [SVM_EXIT_INTR]                         = intr_interception,
4788         [SVM_EXIT_NMI]                          = nmi_interception,
4789         [SVM_EXIT_SMI]                          = nop_on_interception,
4790         [SVM_EXIT_INIT]                         = nop_on_interception,
4791         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4792         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4793         [SVM_EXIT_CPUID]                        = cpuid_interception,
4794         [SVM_EXIT_IRET]                         = iret_interception,
4795         [SVM_EXIT_INVD]                         = emulate_on_interception,
4796         [SVM_EXIT_PAUSE]                        = pause_interception,
4797         [SVM_EXIT_HLT]                          = halt_interception,
4798         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4799         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4800         [SVM_EXIT_IOIO]                         = io_interception,
4801         [SVM_EXIT_MSR]                          = msr_interception,
4802         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4803         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4804         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4805         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4806         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4807         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4808         [SVM_EXIT_STGI]                         = stgi_interception,
4809         [SVM_EXIT_CLGI]                         = clgi_interception,
4810         [SVM_EXIT_SKINIT]                       = skinit_interception,
4811         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4812         [SVM_EXIT_MONITOR]                      = monitor_interception,
4813         [SVM_EXIT_MWAIT]                        = mwait_interception,
4814         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4815         [SVM_EXIT_NPF]                          = npf_interception,
4816         [SVM_EXIT_RSM]                          = rsm_interception,
4817         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4818         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4819 };
4820
4821 static void dump_vmcb(struct kvm_vcpu *vcpu)
4822 {
4823         struct vcpu_svm *svm = to_svm(vcpu);
4824         struct vmcb_control_area *control = &svm->vmcb->control;
4825         struct vmcb_save_area *save = &svm->vmcb->save;
4826
4827         pr_err("VMCB Control Area:\n");
4828         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4829         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4830         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4831         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4832         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4833         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4834         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4835         pr_err("%-20s%d\n", "pause filter threshold:",
4836                control->pause_filter_thresh);
4837         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4838         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4839         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4840         pr_err("%-20s%d\n", "asid:", control->asid);
4841         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4842         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4843         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4844         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4845         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4846         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4847         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4848         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4849         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4850         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4851         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4852         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4853         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4854         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4855         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4856         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4857         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4858         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4859         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4860         pr_err("VMCB State Save Area:\n");
4861         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4862                "es:",
4863                save->es.selector, save->es.attrib,
4864                save->es.limit, save->es.base);
4865         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4866                "cs:",
4867                save->cs.selector, save->cs.attrib,
4868                save->cs.limit, save->cs.base);
4869         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4870                "ss:",
4871                save->ss.selector, save->ss.attrib,
4872                save->ss.limit, save->ss.base);
4873         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4874                "ds:",
4875                save->ds.selector, save->ds.attrib,
4876                save->ds.limit, save->ds.base);
4877         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4878                "fs:",
4879                save->fs.selector, save->fs.attrib,
4880                save->fs.limit, save->fs.base);
4881         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4882                "gs:",
4883                save->gs.selector, save->gs.attrib,
4884                save->gs.limit, save->gs.base);
4885         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4886                "gdtr:",
4887                save->gdtr.selector, save->gdtr.attrib,
4888                save->gdtr.limit, save->gdtr.base);
4889         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4890                "ldtr:",
4891                save->ldtr.selector, save->ldtr.attrib,
4892                save->ldtr.limit, save->ldtr.base);
4893         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4894                "idtr:",
4895                save->idtr.selector, save->idtr.attrib,
4896                save->idtr.limit, save->idtr.base);
4897         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4898                "tr:",
4899                save->tr.selector, save->tr.attrib,
4900                save->tr.limit, save->tr.base);
4901         pr_err("cpl:            %d                efer:         %016llx\n",
4902                 save->cpl, save->efer);
4903         pr_err("%-15s %016llx %-13s %016llx\n",
4904                "cr0:", save->cr0, "cr2:", save->cr2);
4905         pr_err("%-15s %016llx %-13s %016llx\n",
4906                "cr3:", save->cr3, "cr4:", save->cr4);
4907         pr_err("%-15s %016llx %-13s %016llx\n",
4908                "dr6:", save->dr6, "dr7:", save->dr7);
4909         pr_err("%-15s %016llx %-13s %016llx\n",
4910                "rip:", save->rip, "rflags:", save->rflags);
4911         pr_err("%-15s %016llx %-13s %016llx\n",
4912                "rsp:", save->rsp, "rax:", save->rax);
4913         pr_err("%-15s %016llx %-13s %016llx\n",
4914                "star:", save->star, "lstar:", save->lstar);
4915         pr_err("%-15s %016llx %-13s %016llx\n",
4916                "cstar:", save->cstar, "sfmask:", save->sfmask);
4917         pr_err("%-15s %016llx %-13s %016llx\n",
4918                "kernel_gs_base:", save->kernel_gs_base,
4919                "sysenter_cs:", save->sysenter_cs);
4920         pr_err("%-15s %016llx %-13s %016llx\n",
4921                "sysenter_esp:", save->sysenter_esp,
4922                "sysenter_eip:", save->sysenter_eip);
4923         pr_err("%-15s %016llx %-13s %016llx\n",
4924                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4925         pr_err("%-15s %016llx %-13s %016llx\n",
4926                "br_from:", save->br_from, "br_to:", save->br_to);
4927         pr_err("%-15s %016llx %-13s %016llx\n",
4928                "excp_from:", save->last_excp_from,
4929                "excp_to:", save->last_excp_to);
4930 }
4931
4932 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4933 {
4934         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4935
4936         *info1 = control->exit_info_1;
4937         *info2 = control->exit_info_2;
4938 }
4939
4940 static int handle_exit(struct kvm_vcpu *vcpu)
4941 {
4942         struct vcpu_svm *svm = to_svm(vcpu);
4943         struct kvm_run *kvm_run = vcpu->run;
4944         u32 exit_code = svm->vmcb->control.exit_code;
4945
4946         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4947
4948         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4949                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4950         if (npt_enabled)
4951                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4952
4953         if (unlikely(svm->nested.exit_required)) {
4954                 nested_svm_vmexit(svm);
4955                 svm->nested.exit_required = false;
4956
4957                 return 1;
4958         }
4959
4960         if (is_guest_mode(vcpu)) {
4961                 int vmexit;
4962
4963                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4964                                         svm->vmcb->control.exit_info_1,
4965                                         svm->vmcb->control.exit_info_2,
4966                                         svm->vmcb->control.exit_int_info,
4967                                         svm->vmcb->control.exit_int_info_err,
4968                                         KVM_ISA_SVM);
4969
4970                 vmexit = nested_svm_exit_special(svm);
4971
4972                 if (vmexit == NESTED_EXIT_CONTINUE)
4973                         vmexit = nested_svm_exit_handled(svm);
4974
4975                 if (vmexit == NESTED_EXIT_DONE)
4976                         return 1;
4977         }
4978
4979         svm_complete_interrupts(svm);
4980
4981         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4982                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4983                 kvm_run->fail_entry.hardware_entry_failure_reason
4984                         = svm->vmcb->control.exit_code;
4985                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4986                 dump_vmcb(vcpu);
4987                 return 0;
4988         }
4989
4990         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4991             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4992             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4993             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4994                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4995                        "exit_code 0x%x\n",
4996                        __func__, svm->vmcb->control.exit_int_info,
4997                        exit_code);
4998
4999         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5000             || !svm_exit_handlers[exit_code]) {
5001                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
5002                 kvm_queue_exception(vcpu, UD_VECTOR);
5003                 return 1;
5004         }
5005
5006         return svm_exit_handlers[exit_code](svm);
5007 }
5008
5009 static void reload_tss(struct kvm_vcpu *vcpu)
5010 {
5011         int cpu = raw_smp_processor_id();
5012
5013         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5014         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5015         load_TR_desc();
5016 }
5017
5018 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5019 {
5020         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5021         int asid = sev_get_asid(svm->vcpu.kvm);
5022
5023         /* Assign the asid allocated with this SEV guest */
5024         svm->vmcb->control.asid = asid;
5025
5026         /*
5027          * Flush guest TLB:
5028          *
5029          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5030          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5031          */
5032         if (sd->sev_vmcbs[asid] == svm->vmcb &&
5033             svm->last_cpu == cpu)
5034                 return;
5035
5036         svm->last_cpu = cpu;
5037         sd->sev_vmcbs[asid] = svm->vmcb;
5038         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5039         mark_dirty(svm->vmcb, VMCB_ASID);
5040 }
5041
5042 static void pre_svm_run(struct vcpu_svm *svm)
5043 {
5044         int cpu = raw_smp_processor_id();
5045
5046         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5047
5048         if (sev_guest(svm->vcpu.kvm))
5049                 return pre_sev_run(svm, cpu);
5050
5051         /* FIXME: handle wraparound of asid_generation */
5052         if (svm->asid_generation != sd->asid_generation)
5053                 new_asid(svm, sd);
5054 }
5055
5056 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5057 {
5058         struct vcpu_svm *svm = to_svm(vcpu);
5059
5060         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5061         vcpu->arch.hflags |= HF_NMI_MASK;
5062         set_intercept(svm, INTERCEPT_IRET);
5063         ++vcpu->stat.nmi_injections;
5064 }
5065
5066 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5067 {
5068         struct vmcb_control_area *control;
5069
5070         /* The following fields are ignored when AVIC is enabled */
5071         control = &svm->vmcb->control;
5072         control->int_vector = irq;
5073         control->int_ctl &= ~V_INTR_PRIO_MASK;
5074         control->int_ctl |= V_IRQ_MASK |
5075                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5076         mark_dirty(svm->vmcb, VMCB_INTR);
5077 }
5078
5079 static void svm_set_irq(struct kvm_vcpu *vcpu)
5080 {
5081         struct vcpu_svm *svm = to_svm(vcpu);
5082
5083         BUG_ON(!(gif_set(svm)));
5084
5085         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5086         ++vcpu->stat.irq_injections;
5087
5088         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5089                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5090 }
5091
5092 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5093 {
5094         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5095 }
5096
5097 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5098 {
5099         struct vcpu_svm *svm = to_svm(vcpu);
5100
5101         if (svm_nested_virtualize_tpr(vcpu) ||
5102             kvm_vcpu_apicv_active(vcpu))
5103                 return;
5104
5105         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5106
5107         if (irr == -1)
5108                 return;
5109
5110         if (tpr >= irr)
5111                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5112 }
5113
5114 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5115 {
5116         return;
5117 }
5118
5119 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5120 {
5121         return avic && irqchip_split(vcpu->kvm);
5122 }
5123
5124 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5125 {
5126 }
5127
5128 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5129 {
5130 }
5131
5132 /* Note: Currently only used by Hyper-V. */
5133 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5134 {
5135         struct vcpu_svm *svm = to_svm(vcpu);
5136         struct vmcb *vmcb = svm->vmcb;
5137
5138         if (kvm_vcpu_apicv_active(vcpu))
5139                 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5140         else
5141                 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5142         mark_dirty(vmcb, VMCB_AVIC);
5143 }
5144
5145 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5146 {
5147         return;
5148 }
5149
5150 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5151 {
5152         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5153         smp_mb__after_atomic();
5154
5155         if (avic_vcpu_is_running(vcpu))
5156                 wrmsrl(SVM_AVIC_DOORBELL,
5157                        kvm_cpu_get_apicid(vcpu->cpu));
5158         else
5159                 kvm_vcpu_wake_up(vcpu);
5160 }
5161
5162 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5163 {
5164         unsigned long flags;
5165         struct amd_svm_iommu_ir *cur;
5166
5167         spin_lock_irqsave(&svm->ir_list_lock, flags);
5168         list_for_each_entry(cur, &svm->ir_list, node) {
5169                 if (cur->data != pi->ir_data)
5170                         continue;
5171                 list_del(&cur->node);
5172                 kfree(cur);
5173                 break;
5174         }
5175         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5176 }
5177
5178 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5179 {
5180         int ret = 0;
5181         unsigned long flags;
5182         struct amd_svm_iommu_ir *ir;
5183
5184         /**
5185          * In some cases, the existing irte is updaed and re-set,
5186          * so we need to check here if it's already been * added
5187          * to the ir_list.
5188          */
5189         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5190                 struct kvm *kvm = svm->vcpu.kvm;
5191                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5192                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5193                 struct vcpu_svm *prev_svm;
5194
5195                 if (!prev_vcpu) {
5196                         ret = -EINVAL;
5197                         goto out;
5198                 }
5199
5200                 prev_svm = to_svm(prev_vcpu);
5201                 svm_ir_list_del(prev_svm, pi);
5202         }
5203
5204         /**
5205          * Allocating new amd_iommu_pi_data, which will get
5206          * add to the per-vcpu ir_list.
5207          */
5208         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5209         if (!ir) {
5210                 ret = -ENOMEM;
5211                 goto out;
5212         }
5213         ir->data = pi->ir_data;
5214
5215         spin_lock_irqsave(&svm->ir_list_lock, flags);
5216         list_add(&ir->node, &svm->ir_list);
5217         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5218 out:
5219         return ret;
5220 }
5221
5222 /**
5223  * Note:
5224  * The HW cannot support posting multicast/broadcast
5225  * interrupts to a vCPU. So, we still use legacy interrupt
5226  * remapping for these kind of interrupts.
5227  *
5228  * For lowest-priority interrupts, we only support
5229  * those with single CPU as the destination, e.g. user
5230  * configures the interrupts via /proc/irq or uses
5231  * irqbalance to make the interrupts single-CPU.
5232  */
5233 static int
5234 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5235                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5236 {
5237         struct kvm_lapic_irq irq;
5238         struct kvm_vcpu *vcpu = NULL;
5239
5240         kvm_set_msi_irq(kvm, e, &irq);
5241
5242         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5243                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5244                          __func__, irq.vector);
5245                 return -1;
5246         }
5247
5248         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5249                  irq.vector);
5250         *svm = to_svm(vcpu);
5251         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5252         vcpu_info->vector = irq.vector;
5253
5254         return 0;
5255 }
5256
5257 /*
5258  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5259  *
5260  * @kvm: kvm
5261  * @host_irq: host irq of the interrupt
5262  * @guest_irq: gsi of the interrupt
5263  * @set: set or unset PI
5264  * returns 0 on success, < 0 on failure
5265  */
5266 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5267                               uint32_t guest_irq, bool set)
5268 {
5269         struct kvm_kernel_irq_routing_entry *e;
5270         struct kvm_irq_routing_table *irq_rt;
5271         int idx, ret = -EINVAL;
5272
5273         if (!kvm_arch_has_assigned_device(kvm) ||
5274             !irq_remapping_cap(IRQ_POSTING_CAP))
5275                 return 0;
5276
5277         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5278                  __func__, host_irq, guest_irq, set);
5279
5280         idx = srcu_read_lock(&kvm->irq_srcu);
5281         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5282         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5283
5284         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5285                 struct vcpu_data vcpu_info;
5286                 struct vcpu_svm *svm = NULL;
5287
5288                 if (e->type != KVM_IRQ_ROUTING_MSI)
5289                         continue;
5290
5291                 /**
5292                  * Here, we setup with legacy mode in the following cases:
5293                  * 1. When cannot target interrupt to a specific vcpu.
5294                  * 2. Unsetting posted interrupt.
5295                  * 3. APIC virtialization is disabled for the vcpu.
5296                  */
5297                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5298                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5299                         struct amd_iommu_pi_data pi;
5300
5301                         /* Try to enable guest_mode in IRTE */
5302                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5303                                             AVIC_HPA_MASK);
5304                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5305                                                      svm->vcpu.vcpu_id);
5306                         pi.is_guest_mode = true;
5307                         pi.vcpu_data = &vcpu_info;
5308                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5309
5310                         /**
5311                          * Here, we successfully setting up vcpu affinity in
5312                          * IOMMU guest mode. Now, we need to store the posted
5313                          * interrupt information in a per-vcpu ir_list so that
5314                          * we can reference to them directly when we update vcpu
5315                          * scheduling information in IOMMU irte.
5316                          */
5317                         if (!ret && pi.is_guest_mode)
5318                                 svm_ir_list_add(svm, &pi);
5319                 } else {
5320                         /* Use legacy mode in IRTE */
5321                         struct amd_iommu_pi_data pi;
5322
5323                         /**
5324                          * Here, pi is used to:
5325                          * - Tell IOMMU to use legacy mode for this interrupt.
5326                          * - Retrieve ga_tag of prior interrupt remapping data.
5327                          */
5328                         pi.is_guest_mode = false;
5329                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5330
5331                         /**
5332                          * Check if the posted interrupt was previously
5333                          * setup with the guest_mode by checking if the ga_tag
5334                          * was cached. If so, we need to clean up the per-vcpu
5335                          * ir_list.
5336                          */
5337                         if (!ret && pi.prev_ga_tag) {
5338                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5339                                 struct kvm_vcpu *vcpu;
5340
5341                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5342                                 if (vcpu)
5343                                         svm_ir_list_del(to_svm(vcpu), &pi);
5344                         }
5345                 }
5346
5347                 if (!ret && svm) {
5348                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5349                                                  e->gsi, vcpu_info.vector,
5350                                                  vcpu_info.pi_desc_addr, set);
5351                 }
5352
5353                 if (ret < 0) {
5354                         pr_err("%s: failed to update PI IRTE\n", __func__);
5355                         goto out;
5356                 }
5357         }
5358
5359         ret = 0;
5360 out:
5361         srcu_read_unlock(&kvm->irq_srcu, idx);
5362         return ret;
5363 }
5364
5365 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5366 {
5367         struct vcpu_svm *svm = to_svm(vcpu);
5368         struct vmcb *vmcb = svm->vmcb;
5369         int ret;
5370         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5371               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5372         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5373
5374         return ret;
5375 }
5376
5377 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5378 {
5379         struct vcpu_svm *svm = to_svm(vcpu);
5380
5381         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5382 }
5383
5384 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5385 {
5386         struct vcpu_svm *svm = to_svm(vcpu);
5387
5388         if (masked) {
5389                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5390                 set_intercept(svm, INTERCEPT_IRET);
5391         } else {
5392                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5393                 clr_intercept(svm, INTERCEPT_IRET);
5394         }
5395 }
5396
5397 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5398 {
5399         struct vcpu_svm *svm = to_svm(vcpu);
5400         struct vmcb *vmcb = svm->vmcb;
5401         int ret;
5402
5403         if (!gif_set(svm) ||
5404              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5405                 return 0;
5406
5407         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5408
5409         if (is_guest_mode(vcpu))
5410                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5411
5412         return ret;
5413 }
5414
5415 static void enable_irq_window(struct kvm_vcpu *vcpu)
5416 {
5417         struct vcpu_svm *svm = to_svm(vcpu);
5418
5419         if (kvm_vcpu_apicv_active(vcpu))
5420                 return;
5421
5422         /*
5423          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5424          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5425          * get that intercept, this function will be called again though and
5426          * we'll get the vintr intercept. However, if the vGIF feature is
5427          * enabled, the STGI interception will not occur. Enable the irq
5428          * window under the assumption that the hardware will set the GIF.
5429          */
5430         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5431                 svm_set_vintr(svm);
5432                 svm_inject_irq(svm, 0x0);
5433         }
5434 }
5435
5436 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5437 {
5438         struct vcpu_svm *svm = to_svm(vcpu);
5439
5440         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5441             == HF_NMI_MASK)
5442                 return; /* IRET will cause a vm exit */
5443
5444         if (!gif_set(svm)) {
5445                 if (vgif_enabled(svm))
5446                         set_intercept(svm, INTERCEPT_STGI);
5447                 return; /* STGI will cause a vm exit */
5448         }
5449
5450         if (svm->nested.exit_required)
5451                 return; /* we're not going to run the guest yet */
5452
5453         /*
5454          * Something prevents NMI from been injected. Single step over possible
5455          * problem (IRET or exception injection or interrupt shadow)
5456          */
5457         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5458         svm->nmi_singlestep = true;
5459         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5460 }
5461
5462 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5463 {
5464         return 0;
5465 }
5466
5467 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5468 {
5469         return 0;
5470 }
5471
5472 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5473 {
5474         struct vcpu_svm *svm = to_svm(vcpu);
5475
5476         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5477                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5478         else
5479                 svm->asid_generation--;
5480 }
5481
5482 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5483 {
5484         struct vcpu_svm *svm = to_svm(vcpu);
5485
5486         invlpga(gva, svm->vmcb->control.asid);
5487 }
5488
5489 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5490 {
5491 }
5492
5493 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5494 {
5495         struct vcpu_svm *svm = to_svm(vcpu);
5496
5497         if (svm_nested_virtualize_tpr(vcpu))
5498                 return;
5499
5500         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5501                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5502                 kvm_set_cr8(vcpu, cr8);
5503         }
5504 }
5505
5506 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5507 {
5508         struct vcpu_svm *svm = to_svm(vcpu);
5509         u64 cr8;
5510
5511         if (svm_nested_virtualize_tpr(vcpu) ||
5512             kvm_vcpu_apicv_active(vcpu))
5513                 return;
5514
5515         cr8 = kvm_get_cr8(vcpu);
5516         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5517         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5518 }
5519
5520 static void svm_complete_interrupts(struct vcpu_svm *svm)
5521 {
5522         u8 vector;
5523         int type;
5524         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5525         unsigned int3_injected = svm->int3_injected;
5526
5527         svm->int3_injected = 0;
5528
5529         /*
5530          * If we've made progress since setting HF_IRET_MASK, we've
5531          * executed an IRET and can allow NMI injection.
5532          */
5533         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5534             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5535                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5536                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5537         }
5538
5539         svm->vcpu.arch.nmi_injected = false;
5540         kvm_clear_exception_queue(&svm->vcpu);
5541         kvm_clear_interrupt_queue(&svm->vcpu);
5542
5543         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5544                 return;
5545
5546         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5547
5548         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5549         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5550
5551         switch (type) {
5552         case SVM_EXITINTINFO_TYPE_NMI:
5553                 svm->vcpu.arch.nmi_injected = true;
5554                 break;
5555         case SVM_EXITINTINFO_TYPE_EXEPT:
5556                 /*
5557                  * In case of software exceptions, do not reinject the vector,
5558                  * but re-execute the instruction instead. Rewind RIP first
5559                  * if we emulated INT3 before.
5560                  */
5561                 if (kvm_exception_is_soft(vector)) {
5562                         if (vector == BP_VECTOR && int3_injected &&
5563                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5564                                 kvm_rip_write(&svm->vcpu,
5565                                               kvm_rip_read(&svm->vcpu) -
5566                                               int3_injected);
5567                         break;
5568                 }
5569                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5570                         u32 err = svm->vmcb->control.exit_int_info_err;
5571                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5572
5573                 } else
5574                         kvm_requeue_exception(&svm->vcpu, vector);
5575                 break;
5576         case SVM_EXITINTINFO_TYPE_INTR:
5577                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5578                 break;
5579         default:
5580                 break;
5581         }
5582 }
5583
5584 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5585 {
5586         struct vcpu_svm *svm = to_svm(vcpu);
5587         struct vmcb_control_area *control = &svm->vmcb->control;
5588
5589         control->exit_int_info = control->event_inj;
5590         control->exit_int_info_err = control->event_inj_err;
5591         control->event_inj = 0;
5592         svm_complete_interrupts(svm);
5593 }
5594
5595 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5596 {
5597         struct vcpu_svm *svm = to_svm(vcpu);
5598
5599         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5600         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5601         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5602
5603         /*
5604          * A vmexit emulation is required before the vcpu can be executed
5605          * again.
5606          */
5607         if (unlikely(svm->nested.exit_required))
5608                 return;
5609
5610         /*
5611          * Disable singlestep if we're injecting an interrupt/exception.
5612          * We don't want our modified rflags to be pushed on the stack where
5613          * we might not be able to easily reset them if we disabled NMI
5614          * singlestep later.
5615          */
5616         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5617                 /*
5618                  * Event injection happens before external interrupts cause a
5619                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5620                  * is enough to force an immediate vmexit.
5621                  */
5622                 disable_nmi_singlestep(svm);
5623                 smp_send_reschedule(vcpu->cpu);
5624         }
5625
5626         pre_svm_run(svm);
5627
5628         sync_lapic_to_cr8(vcpu);
5629
5630         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5631
5632         clgi();
5633         kvm_load_guest_xcr0(vcpu);
5634
5635         /*
5636          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5637          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5638          * is no need to worry about the conditional branch over the wrmsr
5639          * being speculatively taken.
5640          */
5641         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5642
5643         local_irq_enable();
5644
5645         asm volatile (
5646                 "push %%" _ASM_BP "; \n\t"
5647                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5648                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5649                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5650                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5651                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5652                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5653 #ifdef CONFIG_X86_64
5654                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5655                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5656                 "mov %c[r10](%[svm]), %%r10 \n\t"
5657                 "mov %c[r11](%[svm]), %%r11 \n\t"
5658                 "mov %c[r12](%[svm]), %%r12 \n\t"
5659                 "mov %c[r13](%[svm]), %%r13 \n\t"
5660                 "mov %c[r14](%[svm]), %%r14 \n\t"
5661                 "mov %c[r15](%[svm]), %%r15 \n\t"
5662 #endif
5663
5664                 /* Enter guest mode */
5665                 "push %%" _ASM_AX " \n\t"
5666                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5667                 __ex("vmload %%" _ASM_AX) "\n\t"
5668                 __ex("vmrun %%" _ASM_AX) "\n\t"
5669                 __ex("vmsave %%" _ASM_AX) "\n\t"
5670                 "pop %%" _ASM_AX " \n\t"
5671
5672                 /* Save guest registers, load host registers */
5673                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5674                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5675                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5676                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5677                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5678                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5679 #ifdef CONFIG_X86_64
5680                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5681                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5682                 "mov %%r10, %c[r10](%[svm]) \n\t"
5683                 "mov %%r11, %c[r11](%[svm]) \n\t"
5684                 "mov %%r12, %c[r12](%[svm]) \n\t"
5685                 "mov %%r13, %c[r13](%[svm]) \n\t"
5686                 "mov %%r14, %c[r14](%[svm]) \n\t"
5687                 "mov %%r15, %c[r15](%[svm]) \n\t"
5688                 /*
5689                 * Clear host registers marked as clobbered to prevent
5690                 * speculative use.
5691                 */
5692                 "xor %%r8d, %%r8d \n\t"
5693                 "xor %%r9d, %%r9d \n\t"
5694                 "xor %%r10d, %%r10d \n\t"
5695                 "xor %%r11d, %%r11d \n\t"
5696                 "xor %%r12d, %%r12d \n\t"
5697                 "xor %%r13d, %%r13d \n\t"
5698                 "xor %%r14d, %%r14d \n\t"
5699                 "xor %%r15d, %%r15d \n\t"
5700 #endif
5701                 "xor %%ebx, %%ebx \n\t"
5702                 "xor %%ecx, %%ecx \n\t"
5703                 "xor %%edx, %%edx \n\t"
5704                 "xor %%esi, %%esi \n\t"
5705                 "xor %%edi, %%edi \n\t"
5706                 "pop %%" _ASM_BP
5707                 :
5708                 : [svm]"a"(svm),
5709                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5710                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5711                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5712                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5713                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5714                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5715                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5716 #ifdef CONFIG_X86_64
5717                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5718                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5719                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5720                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5721                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5722                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5723                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5724                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5725 #endif
5726                 : "cc", "memory"
5727 #ifdef CONFIG_X86_64
5728                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5729                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5730 #else
5731                 , "ebx", "ecx", "edx", "esi", "edi"
5732 #endif
5733                 );
5734
5735         /* Eliminate branch target predictions from guest mode */
5736         vmexit_fill_RSB();
5737
5738 #ifdef CONFIG_X86_64
5739         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5740 #else
5741         loadsegment(fs, svm->host.fs);
5742 #ifndef CONFIG_X86_32_LAZY_GS
5743         loadsegment(gs, svm->host.gs);
5744 #endif
5745 #endif
5746
5747         /*
5748          * We do not use IBRS in the kernel. If this vCPU has used the
5749          * SPEC_CTRL MSR it may have left it on; save the value and
5750          * turn it off. This is much more efficient than blindly adding
5751          * it to the atomic save/restore list. Especially as the former
5752          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5753          *
5754          * For non-nested case:
5755          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5756          * save it.
5757          *
5758          * For nested case:
5759          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5760          * save it.
5761          */
5762         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5763                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5764
5765         reload_tss(vcpu);
5766
5767         local_irq_disable();
5768
5769         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5770
5771         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5772         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5773         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5774         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5775
5776         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5777                 kvm_before_interrupt(&svm->vcpu);
5778
5779         kvm_put_guest_xcr0(vcpu);
5780         stgi();
5781
5782         /* Any pending NMI will happen here */
5783
5784         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5785                 kvm_after_interrupt(&svm->vcpu);
5786
5787         sync_cr8_to_lapic(vcpu);
5788
5789         svm->next_rip = 0;
5790
5791         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5792
5793         /* if exit due to PF check for async PF */
5794         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5795                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5796
5797         if (npt_enabled) {
5798                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5799                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5800         }
5801
5802         /*
5803          * We need to handle MC intercepts here before the vcpu has a chance to
5804          * change the physical cpu
5805          */
5806         if (unlikely(svm->vmcb->control.exit_code ==
5807                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5808                 svm_handle_mce(svm);
5809
5810         mark_all_clean(svm->vmcb);
5811 }
5812 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5813
5814 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5815 {
5816         struct vcpu_svm *svm = to_svm(vcpu);
5817
5818         svm->vmcb->save.cr3 = __sme_set(root);
5819         mark_dirty(svm->vmcb, VMCB_CR);
5820 }
5821
5822 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5823 {
5824         struct vcpu_svm *svm = to_svm(vcpu);
5825
5826         svm->vmcb->control.nested_cr3 = __sme_set(root);
5827         mark_dirty(svm->vmcb, VMCB_NPT);
5828
5829         /* Also sync guest cr3 here in case we live migrate */
5830         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5831         mark_dirty(svm->vmcb, VMCB_CR);
5832 }
5833
5834 static int is_disabled(void)
5835 {
5836         u64 vm_cr;
5837
5838         rdmsrl(MSR_VM_CR, vm_cr);
5839         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5840                 return 1;
5841
5842         return 0;
5843 }
5844
5845 static void
5846 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5847 {
5848         /*
5849          * Patch in the VMMCALL instruction:
5850          */
5851         hypercall[0] = 0x0f;
5852         hypercall[1] = 0x01;
5853         hypercall[2] = 0xd9;
5854 }
5855
5856 static void svm_check_processor_compat(void *rtn)
5857 {
5858         *(int *)rtn = 0;
5859 }
5860
5861 static bool svm_cpu_has_accelerated_tpr(void)
5862 {
5863         return false;
5864 }
5865
5866 static bool svm_has_emulated_msr(int index)
5867 {
5868         switch (index) {
5869         case MSR_IA32_MCG_EXT_CTL:
5870                 return false;
5871         default:
5872                 break;
5873         }
5874
5875         return true;
5876 }
5877
5878 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5879 {
5880         return 0;
5881 }
5882
5883 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5884 {
5885         struct vcpu_svm *svm = to_svm(vcpu);
5886
5887         /* Update nrips enabled cache */
5888         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5889
5890         if (!kvm_vcpu_apicv_active(vcpu))
5891                 return;
5892
5893         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5894 }
5895
5896 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5897 {
5898         switch (func) {
5899         case 0x1:
5900                 if (avic)
5901                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5902                 break;
5903         case 0x80000001:
5904                 if (nested)
5905                         entry->ecx |= (1 << 2); /* Set SVM bit */
5906                 break;
5907         case 0x8000000A:
5908                 entry->eax = 1; /* SVM revision 1 */
5909                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5910                                    ASID emulation to nested SVM */
5911                 entry->ecx = 0; /* Reserved */
5912                 entry->edx = 0; /* Per default do not support any
5913                                    additional features */
5914
5915                 /* Support next_rip if host supports it */
5916                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5917                         entry->edx |= SVM_FEATURE_NRIP;
5918
5919                 /* Support NPT for the guest if enabled */
5920                 if (npt_enabled)
5921                         entry->edx |= SVM_FEATURE_NPT;
5922
5923                 break;
5924         case 0x8000001F:
5925                 /* Support memory encryption cpuid if host supports it */
5926                 if (boot_cpu_has(X86_FEATURE_SEV))
5927                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5928                                 &entry->ecx, &entry->edx);
5929
5930         }
5931 }
5932
5933 static int svm_get_lpage_level(void)
5934 {
5935         return PT_PDPE_LEVEL;
5936 }
5937
5938 static bool svm_rdtscp_supported(void)
5939 {
5940         return boot_cpu_has(X86_FEATURE_RDTSCP);
5941 }
5942
5943 static bool svm_invpcid_supported(void)
5944 {
5945         return false;
5946 }
5947
5948 static bool svm_mpx_supported(void)
5949 {
5950         return false;
5951 }
5952
5953 static bool svm_xsaves_supported(void)
5954 {
5955         return false;
5956 }
5957
5958 static bool svm_umip_emulated(void)
5959 {
5960         return false;
5961 }
5962
5963 static bool svm_pt_supported(void)
5964 {
5965         return false;
5966 }
5967
5968 static bool svm_has_wbinvd_exit(void)
5969 {
5970         return true;
5971 }
5972
5973 #define PRE_EX(exit)  { .exit_code = (exit), \
5974                         .stage = X86_ICPT_PRE_EXCEPT, }
5975 #define POST_EX(exit) { .exit_code = (exit), \
5976                         .stage = X86_ICPT_POST_EXCEPT, }
5977 #define POST_MEM(exit) { .exit_code = (exit), \
5978                         .stage = X86_ICPT_POST_MEMACCESS, }
5979
5980 static const struct __x86_intercept {
5981         u32 exit_code;
5982         enum x86_intercept_stage stage;
5983 } x86_intercept_map[] = {
5984         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5985         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5986         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5987         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5988         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5989         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5990         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5991         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5992         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5993         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5994         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5995         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5996         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5997         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5998         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5999         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
6000         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
6001         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
6002         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
6003         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
6004         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
6005         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
6006         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
6007         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
6008         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
6009         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
6010         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
6011         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
6012         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
6013         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
6014         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
6015         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
6016         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
6017         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
6018         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
6019         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
6020         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
6021         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
6022         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
6023         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
6024         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
6025         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
6026         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
6027         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
6028         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
6029         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
6030 };
6031
6032 #undef PRE_EX
6033 #undef POST_EX
6034 #undef POST_MEM
6035
6036 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6037                                struct x86_instruction_info *info,
6038                                enum x86_intercept_stage stage)
6039 {
6040         struct vcpu_svm *svm = to_svm(vcpu);
6041         int vmexit, ret = X86EMUL_CONTINUE;
6042         struct __x86_intercept icpt_info;
6043         struct vmcb *vmcb = svm->vmcb;
6044
6045         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6046                 goto out;
6047
6048         icpt_info = x86_intercept_map[info->intercept];
6049
6050         if (stage != icpt_info.stage)
6051                 goto out;
6052
6053         switch (icpt_info.exit_code) {
6054         case SVM_EXIT_READ_CR0:
6055                 if (info->intercept == x86_intercept_cr_read)
6056                         icpt_info.exit_code += info->modrm_reg;
6057                 break;
6058         case SVM_EXIT_WRITE_CR0: {
6059                 unsigned long cr0, val;
6060                 u64 intercept;
6061
6062                 if (info->intercept == x86_intercept_cr_write)
6063                         icpt_info.exit_code += info->modrm_reg;
6064
6065                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6066                     info->intercept == x86_intercept_clts)
6067                         break;
6068
6069                 intercept = svm->nested.intercept;
6070
6071                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6072                         break;
6073
6074                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6075                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6076
6077                 if (info->intercept == x86_intercept_lmsw) {
6078                         cr0 &= 0xfUL;
6079                         val &= 0xfUL;
6080                         /* lmsw can't clear PE - catch this here */
6081                         if (cr0 & X86_CR0_PE)
6082                                 val |= X86_CR0_PE;
6083                 }
6084
6085                 if (cr0 ^ val)
6086                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6087
6088                 break;
6089         }
6090         case SVM_EXIT_READ_DR0:
6091         case SVM_EXIT_WRITE_DR0:
6092                 icpt_info.exit_code += info->modrm_reg;
6093                 break;
6094         case SVM_EXIT_MSR:
6095                 if (info->intercept == x86_intercept_wrmsr)
6096                         vmcb->control.exit_info_1 = 1;
6097                 else
6098                         vmcb->control.exit_info_1 = 0;
6099                 break;
6100         case SVM_EXIT_PAUSE:
6101                 /*
6102                  * We get this for NOP only, but pause
6103                  * is rep not, check this here
6104                  */
6105                 if (info->rep_prefix != REPE_PREFIX)
6106                         goto out;
6107                 break;
6108         case SVM_EXIT_IOIO: {
6109                 u64 exit_info;
6110                 u32 bytes;
6111
6112                 if (info->intercept == x86_intercept_in ||
6113                     info->intercept == x86_intercept_ins) {
6114                         exit_info = ((info->src_val & 0xffff) << 16) |
6115                                 SVM_IOIO_TYPE_MASK;
6116                         bytes = info->dst_bytes;
6117                 } else {
6118                         exit_info = (info->dst_val & 0xffff) << 16;
6119                         bytes = info->src_bytes;
6120                 }
6121
6122                 if (info->intercept == x86_intercept_outs ||
6123                     info->intercept == x86_intercept_ins)
6124                         exit_info |= SVM_IOIO_STR_MASK;
6125
6126                 if (info->rep_prefix)
6127                         exit_info |= SVM_IOIO_REP_MASK;
6128
6129                 bytes = min(bytes, 4u);
6130
6131                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6132
6133                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6134
6135                 vmcb->control.exit_info_1 = exit_info;
6136                 vmcb->control.exit_info_2 = info->next_rip;
6137
6138                 break;
6139         }
6140         default:
6141                 break;
6142         }
6143
6144         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6145         if (static_cpu_has(X86_FEATURE_NRIPS))
6146                 vmcb->control.next_rip  = info->next_rip;
6147         vmcb->control.exit_code = icpt_info.exit_code;
6148         vmexit = nested_svm_exit_handled(svm);
6149
6150         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6151                                            : X86EMUL_CONTINUE;
6152
6153 out:
6154         return ret;
6155 }
6156
6157 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6158 {
6159         local_irq_enable();
6160         /*
6161          * We must have an instruction with interrupts enabled, so
6162          * the timer interrupt isn't delayed by the interrupt shadow.
6163          */
6164         asm("nop");
6165         local_irq_disable();
6166 }
6167
6168 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6169 {
6170         if (pause_filter_thresh)
6171                 shrink_ple_window(vcpu);
6172 }
6173
6174 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6175 {
6176         if (avic_handle_apic_id_update(vcpu) != 0)
6177                 return;
6178         avic_handle_dfr_update(vcpu);
6179         avic_handle_ldr_update(vcpu);
6180 }
6181
6182 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6183 {
6184         /* [63:9] are reserved. */
6185         vcpu->arch.mcg_cap &= 0x1ff;
6186 }
6187
6188 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6189 {
6190         struct vcpu_svm *svm = to_svm(vcpu);
6191
6192         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6193         if (!gif_set(svm))
6194                 return 0;
6195
6196         if (is_guest_mode(&svm->vcpu) &&
6197             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6198                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6199                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6200                 svm->nested.exit_required = true;
6201                 return 0;
6202         }
6203
6204         return 1;
6205 }
6206
6207 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6208 {
6209         struct vcpu_svm *svm = to_svm(vcpu);
6210         int ret;
6211
6212         if (is_guest_mode(vcpu)) {
6213                 /* FED8h - SVM Guest */
6214                 put_smstate(u64, smstate, 0x7ed8, 1);
6215                 /* FEE0h - SVM Guest VMCB Physical Address */
6216                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6217
6218                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6219                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6220                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6221
6222                 ret = nested_svm_vmexit(svm);
6223                 if (ret)
6224                         return ret;
6225         }
6226         return 0;
6227 }
6228
6229 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6230 {
6231         struct vcpu_svm *svm = to_svm(vcpu);
6232         struct vmcb *nested_vmcb;
6233         struct kvm_host_map map;
6234         u64 guest;
6235         u64 vmcb;
6236
6237         guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6238         vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6239
6240         if (guest) {
6241                 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6242                         return 1;
6243                 nested_vmcb = map.hva;
6244                 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6245         }
6246         return 0;
6247 }
6248
6249 static int enable_smi_window(struct kvm_vcpu *vcpu)
6250 {
6251         struct vcpu_svm *svm = to_svm(vcpu);
6252
6253         if (!gif_set(svm)) {
6254                 if (vgif_enabled(svm))
6255                         set_intercept(svm, INTERCEPT_STGI);
6256                 /* STGI will cause a vm exit */
6257                 return 1;
6258         }
6259         return 0;
6260 }
6261
6262 static int sev_asid_new(void)
6263 {
6264         int pos;
6265
6266         /*
6267          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6268          */
6269         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6270         if (pos >= max_sev_asid)
6271                 return -EBUSY;
6272
6273         set_bit(pos, sev_asid_bitmap);
6274         return pos + 1;
6275 }
6276
6277 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6278 {
6279         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6280         int asid, ret;
6281
6282         ret = -EBUSY;
6283         if (unlikely(sev->active))
6284                 return ret;
6285
6286         asid = sev_asid_new();
6287         if (asid < 0)
6288                 return ret;
6289
6290         ret = sev_platform_init(&argp->error);
6291         if (ret)
6292                 goto e_free;
6293
6294         sev->active = true;
6295         sev->asid = asid;
6296         INIT_LIST_HEAD(&sev->regions_list);
6297
6298         return 0;
6299
6300 e_free:
6301         __sev_asid_free(asid);
6302         return ret;
6303 }
6304
6305 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6306 {
6307         struct sev_data_activate *data;
6308         int asid = sev_get_asid(kvm);
6309         int ret;
6310
6311         wbinvd_on_all_cpus();
6312
6313         ret = sev_guest_df_flush(error);
6314         if (ret)
6315                 return ret;
6316
6317         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6318         if (!data)
6319                 return -ENOMEM;
6320
6321         /* activate ASID on the given handle */
6322         data->handle = handle;
6323         data->asid   = asid;
6324         ret = sev_guest_activate(data, error);
6325         kfree(data);
6326
6327         return ret;
6328 }
6329
6330 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6331 {
6332         struct fd f;
6333         int ret;
6334
6335         f = fdget(fd);
6336         if (!f.file)
6337                 return -EBADF;
6338
6339         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6340
6341         fdput(f);
6342         return ret;
6343 }
6344
6345 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6346 {
6347         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6348
6349         return __sev_issue_cmd(sev->fd, id, data, error);
6350 }
6351
6352 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6353 {
6354         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6355         struct sev_data_launch_start *start;
6356         struct kvm_sev_launch_start params;
6357         void *dh_blob, *session_blob;
6358         int *error = &argp->error;
6359         int ret;
6360
6361         if (!sev_guest(kvm))
6362                 return -ENOTTY;
6363
6364         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6365                 return -EFAULT;
6366
6367         start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6368         if (!start)
6369                 return -ENOMEM;
6370
6371         dh_blob = NULL;
6372         if (params.dh_uaddr) {
6373                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6374                 if (IS_ERR(dh_blob)) {
6375                         ret = PTR_ERR(dh_blob);
6376                         goto e_free;
6377                 }
6378
6379                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6380                 start->dh_cert_len = params.dh_len;
6381         }
6382
6383         session_blob = NULL;
6384         if (params.session_uaddr) {
6385                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6386                 if (IS_ERR(session_blob)) {
6387                         ret = PTR_ERR(session_blob);
6388                         goto e_free_dh;
6389                 }
6390
6391                 start->session_address = __sme_set(__pa(session_blob));
6392                 start->session_len = params.session_len;
6393         }
6394
6395         start->handle = params.handle;
6396         start->policy = params.policy;
6397
6398         /* create memory encryption context */
6399         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6400         if (ret)
6401                 goto e_free_session;
6402
6403         /* Bind ASID to this guest */
6404         ret = sev_bind_asid(kvm, start->handle, error);
6405         if (ret)
6406                 goto e_free_session;
6407
6408         /* return handle to userspace */
6409         params.handle = start->handle;
6410         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6411                 sev_unbind_asid(kvm, start->handle);
6412                 ret = -EFAULT;
6413                 goto e_free_session;
6414         }
6415
6416         sev->handle = start->handle;
6417         sev->fd = argp->sev_fd;
6418
6419 e_free_session:
6420         kfree(session_blob);
6421 e_free_dh:
6422         kfree(dh_blob);
6423 e_free:
6424         kfree(start);
6425         return ret;
6426 }
6427
6428 static unsigned long get_num_contig_pages(unsigned long idx,
6429                                 struct page **inpages, unsigned long npages)
6430 {
6431         unsigned long paddr, next_paddr;
6432         unsigned long i = idx + 1, pages = 1;
6433
6434         /* find the number of contiguous pages starting from idx */
6435         paddr = __sme_page_pa(inpages[idx]);
6436         while (i < npages) {
6437                 next_paddr = __sme_page_pa(inpages[i++]);
6438                 if ((paddr + PAGE_SIZE) == next_paddr) {
6439                         pages++;
6440                         paddr = next_paddr;
6441                         continue;
6442                 }
6443                 break;
6444         }
6445
6446         return pages;
6447 }
6448
6449 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6450 {
6451         unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6452         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6453         struct kvm_sev_launch_update_data params;
6454         struct sev_data_launch_update_data *data;
6455         struct page **inpages;
6456         int ret;
6457
6458         if (!sev_guest(kvm))
6459                 return -ENOTTY;
6460
6461         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6462                 return -EFAULT;
6463
6464         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6465         if (!data)
6466                 return -ENOMEM;
6467
6468         vaddr = params.uaddr;
6469         size = params.len;
6470         vaddr_end = vaddr + size;
6471
6472         /* Lock the user memory. */
6473         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6474         if (!inpages) {
6475                 ret = -ENOMEM;
6476                 goto e_free;
6477         }
6478
6479         /*
6480          * The LAUNCH_UPDATE command will perform in-place encryption of the
6481          * memory content (i.e it will write the same memory region with C=1).
6482          * It's possible that the cache may contain the data with C=0, i.e.,
6483          * unencrypted so invalidate it first.
6484          */
6485         sev_clflush_pages(inpages, npages);
6486
6487         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6488                 int offset, len;
6489
6490                 /*
6491                  * If the user buffer is not page-aligned, calculate the offset
6492                  * within the page.
6493                  */
6494                 offset = vaddr & (PAGE_SIZE - 1);
6495
6496                 /* Calculate the number of pages that can be encrypted in one go. */
6497                 pages = get_num_contig_pages(i, inpages, npages);
6498
6499                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6500
6501                 data->handle = sev->handle;
6502                 data->len = len;
6503                 data->address = __sme_page_pa(inpages[i]) + offset;
6504                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6505                 if (ret)
6506                         goto e_unpin;
6507
6508                 size -= len;
6509                 next_vaddr = vaddr + len;
6510         }
6511
6512 e_unpin:
6513         /* content of memory is updated, mark pages dirty */
6514         for (i = 0; i < npages; i++) {
6515                 set_page_dirty_lock(inpages[i]);
6516                 mark_page_accessed(inpages[i]);
6517         }
6518         /* unlock the user pages */
6519         sev_unpin_memory(kvm, inpages, npages);
6520 e_free:
6521         kfree(data);
6522         return ret;
6523 }
6524
6525 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6526 {
6527         void __user *measure = (void __user *)(uintptr_t)argp->data;
6528         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6529         struct sev_data_launch_measure *data;
6530         struct kvm_sev_launch_measure params;
6531         void __user *p = NULL;
6532         void *blob = NULL;
6533         int ret;
6534
6535         if (!sev_guest(kvm))
6536                 return -ENOTTY;
6537
6538         if (copy_from_user(&params, measure, sizeof(params)))
6539                 return -EFAULT;
6540
6541         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6542         if (!data)
6543                 return -ENOMEM;
6544
6545         /* User wants to query the blob length */
6546         if (!params.len)
6547                 goto cmd;
6548
6549         p = (void __user *)(uintptr_t)params.uaddr;
6550         if (p) {
6551                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6552                         ret = -EINVAL;
6553                         goto e_free;
6554                 }
6555
6556                 ret = -ENOMEM;
6557                 blob = kmalloc(params.len, GFP_KERNEL);
6558                 if (!blob)
6559                         goto e_free;
6560
6561                 data->address = __psp_pa(blob);
6562                 data->len = params.len;
6563         }
6564
6565 cmd:
6566         data->handle = sev->handle;
6567         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6568
6569         /*
6570          * If we query the session length, FW responded with expected data.
6571          */
6572         if (!params.len)
6573                 goto done;
6574
6575         if (ret)
6576                 goto e_free_blob;
6577
6578         if (blob) {
6579                 if (copy_to_user(p, blob, params.len))
6580                         ret = -EFAULT;
6581         }
6582
6583 done:
6584         params.len = data->len;
6585         if (copy_to_user(measure, &params, sizeof(params)))
6586                 ret = -EFAULT;
6587 e_free_blob:
6588         kfree(blob);
6589 e_free:
6590         kfree(data);
6591         return ret;
6592 }
6593
6594 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6595 {
6596         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6597         struct sev_data_launch_finish *data;
6598         int ret;
6599
6600         if (!sev_guest(kvm))
6601                 return -ENOTTY;
6602
6603         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6604         if (!data)
6605                 return -ENOMEM;
6606
6607         data->handle = sev->handle;
6608         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6609
6610         kfree(data);
6611         return ret;
6612 }
6613
6614 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6615 {
6616         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6617         struct kvm_sev_guest_status params;
6618         struct sev_data_guest_status *data;
6619         int ret;
6620
6621         if (!sev_guest(kvm))
6622                 return -ENOTTY;
6623
6624         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6625         if (!data)
6626                 return -ENOMEM;
6627
6628         data->handle = sev->handle;
6629         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6630         if (ret)
6631                 goto e_free;
6632
6633         params.policy = data->policy;
6634         params.state = data->state;
6635         params.handle = data->handle;
6636
6637         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6638                 ret = -EFAULT;
6639 e_free:
6640         kfree(data);
6641         return ret;
6642 }
6643
6644 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6645                                unsigned long dst, int size,
6646                                int *error, bool enc)
6647 {
6648         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6649         struct sev_data_dbg *data;
6650         int ret;
6651
6652         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6653         if (!data)
6654                 return -ENOMEM;
6655
6656         data->handle = sev->handle;
6657         data->dst_addr = dst;
6658         data->src_addr = src;
6659         data->len = size;
6660
6661         ret = sev_issue_cmd(kvm,
6662                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6663                             data, error);
6664         kfree(data);
6665         return ret;
6666 }
6667
6668 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6669                              unsigned long dst_paddr, int sz, int *err)
6670 {
6671         int offset;
6672
6673         /*
6674          * Its safe to read more than we are asked, caller should ensure that
6675          * destination has enough space.
6676          */
6677         src_paddr = round_down(src_paddr, 16);
6678         offset = src_paddr & 15;
6679         sz = round_up(sz + offset, 16);
6680
6681         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6682 }
6683
6684 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6685                                   unsigned long __user dst_uaddr,
6686                                   unsigned long dst_paddr,
6687                                   int size, int *err)
6688 {
6689         struct page *tpage = NULL;
6690         int ret, offset;
6691
6692         /* if inputs are not 16-byte then use intermediate buffer */
6693         if (!IS_ALIGNED(dst_paddr, 16) ||
6694             !IS_ALIGNED(paddr,     16) ||
6695             !IS_ALIGNED(size,      16)) {
6696                 tpage = (void *)alloc_page(GFP_KERNEL);
6697                 if (!tpage)
6698                         return -ENOMEM;
6699
6700                 dst_paddr = __sme_page_pa(tpage);
6701         }
6702
6703         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6704         if (ret)
6705                 goto e_free;
6706
6707         if (tpage) {
6708                 offset = paddr & 15;
6709                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6710                                  page_address(tpage) + offset, size))
6711                         ret = -EFAULT;
6712         }
6713
6714 e_free:
6715         if (tpage)
6716                 __free_page(tpage);
6717
6718         return ret;
6719 }
6720
6721 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6722                                   unsigned long __user vaddr,
6723                                   unsigned long dst_paddr,
6724                                   unsigned long __user dst_vaddr,
6725                                   int size, int *error)
6726 {
6727         struct page *src_tpage = NULL;
6728         struct page *dst_tpage = NULL;
6729         int ret, len = size;
6730
6731         /* If source buffer is not aligned then use an intermediate buffer */
6732         if (!IS_ALIGNED(vaddr, 16)) {
6733                 src_tpage = alloc_page(GFP_KERNEL);
6734                 if (!src_tpage)
6735                         return -ENOMEM;
6736
6737                 if (copy_from_user(page_address(src_tpage),
6738                                 (void __user *)(uintptr_t)vaddr, size)) {
6739                         __free_page(src_tpage);
6740                         return -EFAULT;
6741                 }
6742
6743                 paddr = __sme_page_pa(src_tpage);
6744         }
6745
6746         /*
6747          *  If destination buffer or length is not aligned then do read-modify-write:
6748          *   - decrypt destination in an intermediate buffer
6749          *   - copy the source buffer in an intermediate buffer
6750          *   - use the intermediate buffer as source buffer
6751          */
6752         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6753                 int dst_offset;
6754
6755                 dst_tpage = alloc_page(GFP_KERNEL);
6756                 if (!dst_tpage) {
6757                         ret = -ENOMEM;
6758                         goto e_free;
6759                 }
6760
6761                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6762                                         __sme_page_pa(dst_tpage), size, error);
6763                 if (ret)
6764                         goto e_free;
6765
6766                 /*
6767                  *  If source is kernel buffer then use memcpy() otherwise
6768                  *  copy_from_user().
6769                  */
6770                 dst_offset = dst_paddr & 15;
6771
6772                 if (src_tpage)
6773                         memcpy(page_address(dst_tpage) + dst_offset,
6774                                page_address(src_tpage), size);
6775                 else {
6776                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6777                                            (void __user *)(uintptr_t)vaddr, size)) {
6778                                 ret = -EFAULT;
6779                                 goto e_free;
6780                         }
6781                 }
6782
6783                 paddr = __sme_page_pa(dst_tpage);
6784                 dst_paddr = round_down(dst_paddr, 16);
6785                 len = round_up(size, 16);
6786         }
6787
6788         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6789
6790 e_free:
6791         if (src_tpage)
6792                 __free_page(src_tpage);
6793         if (dst_tpage)
6794                 __free_page(dst_tpage);
6795         return ret;
6796 }
6797
6798 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6799 {
6800         unsigned long vaddr, vaddr_end, next_vaddr;
6801         unsigned long dst_vaddr;
6802         struct page **src_p, **dst_p;
6803         struct kvm_sev_dbg debug;
6804         unsigned long n;
6805         unsigned int size;
6806         int ret;
6807
6808         if (!sev_guest(kvm))
6809                 return -ENOTTY;
6810
6811         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6812                 return -EFAULT;
6813
6814         if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6815                 return -EINVAL;
6816         if (!debug.dst_uaddr)
6817                 return -EINVAL;
6818
6819         vaddr = debug.src_uaddr;
6820         size = debug.len;
6821         vaddr_end = vaddr + size;
6822         dst_vaddr = debug.dst_uaddr;
6823
6824         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6825                 int len, s_off, d_off;
6826
6827                 /* lock userspace source and destination page */
6828                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6829                 if (!src_p)
6830                         return -EFAULT;
6831
6832                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6833                 if (!dst_p) {
6834                         sev_unpin_memory(kvm, src_p, n);
6835                         return -EFAULT;
6836                 }
6837
6838                 /*
6839                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6840                  * memory content (i.e it will write the same memory region with C=1).
6841                  * It's possible that the cache may contain the data with C=0, i.e.,
6842                  * unencrypted so invalidate it first.
6843                  */
6844                 sev_clflush_pages(src_p, 1);
6845                 sev_clflush_pages(dst_p, 1);
6846
6847                 /*
6848                  * Since user buffer may not be page aligned, calculate the
6849                  * offset within the page.
6850                  */
6851                 s_off = vaddr & ~PAGE_MASK;
6852                 d_off = dst_vaddr & ~PAGE_MASK;
6853                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6854
6855                 if (dec)
6856                         ret = __sev_dbg_decrypt_user(kvm,
6857                                                      __sme_page_pa(src_p[0]) + s_off,
6858                                                      dst_vaddr,
6859                                                      __sme_page_pa(dst_p[0]) + d_off,
6860                                                      len, &argp->error);
6861                 else
6862                         ret = __sev_dbg_encrypt_user(kvm,
6863                                                      __sme_page_pa(src_p[0]) + s_off,
6864                                                      vaddr,
6865                                                      __sme_page_pa(dst_p[0]) + d_off,
6866                                                      dst_vaddr,
6867                                                      len, &argp->error);
6868
6869                 sev_unpin_memory(kvm, src_p, n);
6870                 sev_unpin_memory(kvm, dst_p, n);
6871
6872                 if (ret)
6873                         goto err;
6874
6875                 next_vaddr = vaddr + len;
6876                 dst_vaddr = dst_vaddr + len;
6877                 size -= len;
6878         }
6879 err:
6880         return ret;
6881 }
6882
6883 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6884 {
6885         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6886         struct sev_data_launch_secret *data;
6887         struct kvm_sev_launch_secret params;
6888         struct page **pages;
6889         void *blob, *hdr;
6890         unsigned long n;
6891         int ret, offset;
6892
6893         if (!sev_guest(kvm))
6894                 return -ENOTTY;
6895
6896         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6897                 return -EFAULT;
6898
6899         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6900         if (!pages)
6901                 return -ENOMEM;
6902
6903         /*
6904          * The secret must be copied into contiguous memory region, lets verify
6905          * that userspace memory pages are contiguous before we issue command.
6906          */
6907         if (get_num_contig_pages(0, pages, n) != n) {
6908                 ret = -EINVAL;
6909                 goto e_unpin_memory;
6910         }
6911
6912         ret = -ENOMEM;
6913         data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6914         if (!data)
6915                 goto e_unpin_memory;
6916
6917         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6918         data->guest_address = __sme_page_pa(pages[0]) + offset;
6919         data->guest_len = params.guest_len;
6920
6921         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6922         if (IS_ERR(blob)) {
6923                 ret = PTR_ERR(blob);
6924                 goto e_free;
6925         }
6926
6927         data->trans_address = __psp_pa(blob);
6928         data->trans_len = params.trans_len;
6929
6930         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6931         if (IS_ERR(hdr)) {
6932                 ret = PTR_ERR(hdr);
6933                 goto e_free_blob;
6934         }
6935         data->hdr_address = __psp_pa(hdr);
6936         data->hdr_len = params.hdr_len;
6937
6938         data->handle = sev->handle;
6939         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6940
6941         kfree(hdr);
6942
6943 e_free_blob:
6944         kfree(blob);
6945 e_free:
6946         kfree(data);
6947 e_unpin_memory:
6948         sev_unpin_memory(kvm, pages, n);
6949         return ret;
6950 }
6951
6952 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6953 {
6954         struct kvm_sev_cmd sev_cmd;
6955         int r;
6956
6957         if (!svm_sev_enabled())
6958                 return -ENOTTY;
6959
6960         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6961                 return -EFAULT;
6962
6963         mutex_lock(&kvm->lock);
6964
6965         switch (sev_cmd.id) {
6966         case KVM_SEV_INIT:
6967                 r = sev_guest_init(kvm, &sev_cmd);
6968                 break;
6969         case KVM_SEV_LAUNCH_START:
6970                 r = sev_launch_start(kvm, &sev_cmd);
6971                 break;
6972         case KVM_SEV_LAUNCH_UPDATE_DATA:
6973                 r = sev_launch_update_data(kvm, &sev_cmd);
6974                 break;
6975         case KVM_SEV_LAUNCH_MEASURE:
6976                 r = sev_launch_measure(kvm, &sev_cmd);
6977                 break;
6978         case KVM_SEV_LAUNCH_FINISH:
6979                 r = sev_launch_finish(kvm, &sev_cmd);
6980                 break;
6981         case KVM_SEV_GUEST_STATUS:
6982                 r = sev_guest_status(kvm, &sev_cmd);
6983                 break;
6984         case KVM_SEV_DBG_DECRYPT:
6985                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6986                 break;
6987         case KVM_SEV_DBG_ENCRYPT:
6988                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6989                 break;
6990         case KVM_SEV_LAUNCH_SECRET:
6991                 r = sev_launch_secret(kvm, &sev_cmd);
6992                 break;
6993         default:
6994                 r = -EINVAL;
6995                 goto out;
6996         }
6997
6998         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6999                 r = -EFAULT;
7000
7001 out:
7002         mutex_unlock(&kvm->lock);
7003         return r;
7004 }
7005
7006 static int svm_register_enc_region(struct kvm *kvm,
7007                                    struct kvm_enc_region *range)
7008 {
7009         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7010         struct enc_region *region;
7011         int ret = 0;
7012
7013         if (!sev_guest(kvm))
7014                 return -ENOTTY;
7015
7016         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7017                 return -EINVAL;
7018
7019         region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7020         if (!region)
7021                 return -ENOMEM;
7022
7023         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
7024         if (!region->pages) {
7025                 ret = -ENOMEM;
7026                 goto e_free;
7027         }
7028
7029         /*
7030          * The guest may change the memory encryption attribute from C=0 -> C=1
7031          * or vice versa for this memory range. Lets make sure caches are
7032          * flushed to ensure that guest data gets written into memory with
7033          * correct C-bit.
7034          */
7035         sev_clflush_pages(region->pages, region->npages);
7036
7037         region->uaddr = range->addr;
7038         region->size = range->size;
7039
7040         mutex_lock(&kvm->lock);
7041         list_add_tail(&region->list, &sev->regions_list);
7042         mutex_unlock(&kvm->lock);
7043
7044         return ret;
7045
7046 e_free:
7047         kfree(region);
7048         return ret;
7049 }
7050
7051 static struct enc_region *
7052 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7053 {
7054         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7055         struct list_head *head = &sev->regions_list;
7056         struct enc_region *i;
7057
7058         list_for_each_entry(i, head, list) {
7059                 if (i->uaddr == range->addr &&
7060                     i->size == range->size)
7061                         return i;
7062         }
7063
7064         return NULL;
7065 }
7066
7067
7068 static int svm_unregister_enc_region(struct kvm *kvm,
7069                                      struct kvm_enc_region *range)
7070 {
7071         struct enc_region *region;
7072         int ret;
7073
7074         mutex_lock(&kvm->lock);
7075
7076         if (!sev_guest(kvm)) {
7077                 ret = -ENOTTY;
7078                 goto failed;
7079         }
7080
7081         region = find_enc_region(kvm, range);
7082         if (!region) {
7083                 ret = -EINVAL;
7084                 goto failed;
7085         }
7086
7087         __unregister_enc_region_locked(kvm, region);
7088
7089         mutex_unlock(&kvm->lock);
7090         return 0;
7091
7092 failed:
7093         mutex_unlock(&kvm->lock);
7094         return ret;
7095 }
7096
7097 static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
7098 {
7099         /* Not supported */
7100         return 0;
7101 }
7102
7103 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7104                                    uint16_t *vmcs_version)
7105 {
7106         /* Intel-only feature */
7107         return -ENODEV;
7108 }
7109
7110 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7111 {
7112         bool is_user, smap;
7113
7114         is_user = svm_get_cpl(vcpu) == 3;
7115         smap = !kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
7116
7117         /*
7118          * Detect and workaround Errata 1096 Fam_17h_00_0Fh
7119          *
7120          * In non SEV guest, hypervisor will be able to read the guest
7121          * memory to decode the instruction pointer when insn_len is zero
7122          * so we return true to indicate that decoding is possible.
7123          *
7124          * But in the SEV guest, the guest memory is encrypted with the
7125          * guest specific key and hypervisor will not be able to decode the
7126          * instruction pointer so we will not able to workaround it. Lets
7127          * print the error and request to kill the guest.
7128          */
7129         if (is_user && smap) {
7130                 if (!sev_guest(vcpu->kvm))
7131                         return true;
7132
7133                 pr_err_ratelimited("KVM: Guest triggered AMD Erratum 1096\n");
7134                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7135         }
7136
7137         return false;
7138 }
7139
7140 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7141         .cpu_has_kvm_support = has_svm,
7142         .disabled_by_bios = is_disabled,
7143         .hardware_setup = svm_hardware_setup,
7144         .hardware_unsetup = svm_hardware_unsetup,
7145         .check_processor_compatibility = svm_check_processor_compat,
7146         .hardware_enable = svm_hardware_enable,
7147         .hardware_disable = svm_hardware_disable,
7148         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7149         .has_emulated_msr = svm_has_emulated_msr,
7150
7151         .vcpu_create = svm_create_vcpu,
7152         .vcpu_free = svm_free_vcpu,
7153         .vcpu_reset = svm_vcpu_reset,
7154
7155         .vm_alloc = svm_vm_alloc,
7156         .vm_free = svm_vm_free,
7157         .vm_init = avic_vm_init,
7158         .vm_destroy = svm_vm_destroy,
7159
7160         .prepare_guest_switch = svm_prepare_guest_switch,
7161         .vcpu_load = svm_vcpu_load,
7162         .vcpu_put = svm_vcpu_put,
7163         .vcpu_blocking = svm_vcpu_blocking,
7164         .vcpu_unblocking = svm_vcpu_unblocking,
7165
7166         .update_bp_intercept = update_bp_intercept,
7167         .get_msr_feature = svm_get_msr_feature,
7168         .get_msr = svm_get_msr,
7169         .set_msr = svm_set_msr,
7170         .get_segment_base = svm_get_segment_base,
7171         .get_segment = svm_get_segment,
7172         .set_segment = svm_set_segment,
7173         .get_cpl = svm_get_cpl,
7174         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7175         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7176         .decache_cr3 = svm_decache_cr3,
7177         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7178         .set_cr0 = svm_set_cr0,
7179         .set_cr3 = svm_set_cr3,
7180         .set_cr4 = svm_set_cr4,
7181         .set_efer = svm_set_efer,
7182         .get_idt = svm_get_idt,
7183         .set_idt = svm_set_idt,
7184         .get_gdt = svm_get_gdt,
7185         .set_gdt = svm_set_gdt,
7186         .get_dr6 = svm_get_dr6,
7187         .set_dr6 = svm_set_dr6,
7188         .set_dr7 = svm_set_dr7,
7189         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7190         .cache_reg = svm_cache_reg,
7191         .get_rflags = svm_get_rflags,
7192         .set_rflags = svm_set_rflags,
7193
7194         .tlb_flush = svm_flush_tlb,
7195         .tlb_flush_gva = svm_flush_tlb_gva,
7196
7197         .run = svm_vcpu_run,
7198         .handle_exit = handle_exit,
7199         .skip_emulated_instruction = skip_emulated_instruction,
7200         .set_interrupt_shadow = svm_set_interrupt_shadow,
7201         .get_interrupt_shadow = svm_get_interrupt_shadow,
7202         .patch_hypercall = svm_patch_hypercall,
7203         .set_irq = svm_set_irq,
7204         .set_nmi = svm_inject_nmi,
7205         .queue_exception = svm_queue_exception,
7206         .cancel_injection = svm_cancel_injection,
7207         .interrupt_allowed = svm_interrupt_allowed,
7208         .nmi_allowed = svm_nmi_allowed,
7209         .get_nmi_mask = svm_get_nmi_mask,
7210         .set_nmi_mask = svm_set_nmi_mask,
7211         .enable_nmi_window = enable_nmi_window,
7212         .enable_irq_window = enable_irq_window,
7213         .update_cr8_intercept = update_cr8_intercept,
7214         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7215         .get_enable_apicv = svm_get_enable_apicv,
7216         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7217         .load_eoi_exitmap = svm_load_eoi_exitmap,
7218         .hwapic_irr_update = svm_hwapic_irr_update,
7219         .hwapic_isr_update = svm_hwapic_isr_update,
7220         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7221         .apicv_post_state_restore = avic_post_state_restore,
7222
7223         .set_tss_addr = svm_set_tss_addr,
7224         .set_identity_map_addr = svm_set_identity_map_addr,
7225         .get_tdp_level = get_npt_level,
7226         .get_mt_mask = svm_get_mt_mask,
7227
7228         .get_exit_info = svm_get_exit_info,
7229
7230         .get_lpage_level = svm_get_lpage_level,
7231
7232         .cpuid_update = svm_cpuid_update,
7233
7234         .rdtscp_supported = svm_rdtscp_supported,
7235         .invpcid_supported = svm_invpcid_supported,
7236         .mpx_supported = svm_mpx_supported,
7237         .xsaves_supported = svm_xsaves_supported,
7238         .umip_emulated = svm_umip_emulated,
7239         .pt_supported = svm_pt_supported,
7240
7241         .set_supported_cpuid = svm_set_supported_cpuid,
7242
7243         .has_wbinvd_exit = svm_has_wbinvd_exit,
7244
7245         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7246         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7247
7248         .set_tdp_cr3 = set_tdp_cr3,
7249
7250         .check_intercept = svm_check_intercept,
7251         .handle_external_intr = svm_handle_external_intr,
7252
7253         .request_immediate_exit = __kvm_request_immediate_exit,
7254
7255         .sched_in = svm_sched_in,
7256
7257         .pmu_ops = &amd_pmu_ops,
7258         .deliver_posted_interrupt = svm_deliver_avic_intr,
7259         .update_pi_irte = svm_update_pi_irte,
7260         .setup_mce = svm_setup_mce,
7261
7262         .smi_allowed = svm_smi_allowed,
7263         .pre_enter_smm = svm_pre_enter_smm,
7264         .pre_leave_smm = svm_pre_leave_smm,
7265         .enable_smi_window = enable_smi_window,
7266
7267         .mem_enc_op = svm_mem_enc_op,
7268         .mem_enc_reg_region = svm_register_enc_region,
7269         .mem_enc_unreg_region = svm_unregister_enc_region,
7270
7271         .nested_enable_evmcs = nested_enable_evmcs,
7272         .nested_get_evmcs_version = nested_get_evmcs_version,
7273
7274         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7275 };
7276
7277 static int __init svm_init(void)
7278 {
7279         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7280                         __alignof__(struct vcpu_svm), THIS_MODULE);
7281 }
7282
7283 static void __exit svm_exit(void)
7284 {
7285         kvm_exit();
7286 }
7287
7288 module_init(svm_init)
7289 module_exit(svm_exit)