arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         u32 ldr_mode;
 149         struct page *avic_logical_id_table_page;
 150         struct page *avic_physical_id_table_page;
 151         struct hlist_node hnode;
 152
 153         struct kvm_sev_info sev_info;
 154 };
 155
 156 struct kvm_vcpu;
 157
 158 struct nested_state {
 159         struct vmcb *hsave;
 160         u64 hsave_msr;
 161         u64 vm_cr_msr;
 162         u64 vmcb;
 163
 164         /* These are the merged vectors */
 165         u32 *msrpm;
 166
 167         /* gpa pointers to the real vectors */
 168         u64 vmcb_msrpm;
 169         u64 vmcb_iopm;
 170
 171         /* A VMEXIT is required but not yet emulated */
 172         bool exit_required;
 173
 174         /* cache for intercepts of the guest */
 175         u32 intercept_cr;
 176         u32 intercept_dr;
 177         u32 intercept_exceptions;
 178         u64 intercept;
 179
 180         /* Nested Paging related state */
 181         u64 nested_cr3;
 182 };
 183
 184 #define MSRPM_OFFSETS   16
 185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 186
 187 /*
 188  * Set osvw_len to higher value when updated Revision Guides
 189  * are published and we know what the new status bits are
 190  */
 191 static uint64_t osvw_len = 4, osvw_status;
 192
 193 struct vcpu_svm {
 194         struct kvm_vcpu vcpu;
 195         struct vmcb *vmcb;
 196         unsigned long vmcb_pa;
 197         struct svm_cpu_data *svm_data;
 198         uint64_t asid_generation;
 199         uint64_t sysenter_esp;
 200         uint64_t sysenter_eip;
 201         uint64_t tsc_aux;
 202
 203         u64 msr_decfg;
 204
 205         u64 next_rip;
 206
 207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 208         struct {
 209                 u16 fs;
 210                 u16 gs;
 211                 u16 ldt;
 212                 u64 gs_base;
 213         } host;
 214
 215         u64 spec_ctrl;
 216         /*
 217          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 218          * translated into the appropriate L2_CFG bits on the host to
 219          * perform speculative control.
 220          */
 221         u64 virt_spec_ctrl;
 222
 223         u32 *msrpm;
 224
 225         ulong nmi_iret_rip;
 226
 227         struct nested_state nested;
 228
 229         bool nmi_singlestep;
 230         u64 nmi_singlestep_guest_rflags;
 231
 232         unsigned int3_injected;
 233         unsigned long int3_rip;
 234
 235         /* cached guest cpuid flags for faster access */
 236         bool nrips_enabled      : 1;
 237
 238         u32 ldr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 266
 267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 271
 272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 274
 275 #define MSR_INVALID                     0xffffffffU
 276
 277 static const struct svm_direct_access_msrs {
 278         u32 index;   /* Index of the MSR */
 279         bool always; /* True if intercept is always on */
 280 } direct_access_msrs[] = {
 281         { .index = MSR_STAR,                            .always = true  },
 282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 283 #ifdef CONFIG_X86_64
 284         { .index = MSR_GS_BASE,                         .always = true  },
 285         { .index = MSR_FS_BASE,                         .always = true  },
 286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 287         { .index = MSR_LSTAR,                           .always = true  },
 288         { .index = MSR_CSTAR,                           .always = true  },
 289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 290 #endif
 291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 297         { .index = MSR_INVALID,                         .always = false },
 298 };
 299
 300 /* enable NPT for AMD64 and X86 with PAE */
 301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 302 static bool npt_enabled = true;
 303 #else
 304 static bool npt_enabled;
 305 #endif
 306
 307 /*
 308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 309  * pause_filter_count: On processors that support Pause filtering(indicated
 310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 311  *      count value. On VMRUN this value is loaded into an internal counter.
 312  *      Each time a pause instruction is executed, this counter is decremented
 313  *      until it reaches zero at which time a #VMEXIT is generated if pause
 314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 315  *      Intercept Filtering for more details.
 316  *      This also indicate if ple logic enabled.
 317  *
 318  * pause_filter_thresh: In addition, some processor families support advanced
 319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 320  *      the amount of time a guest is allowed to execute in a pause loop.
 321  *      In this mode, a 16-bit pause filter threshold field is added in the
 322  *      VMCB. The threshold value is a cycle count that is used to reset the
 323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 324  *      count value from VMCB into an internal counter. Then, on each pause
 325  *      instruction the hardware checks the elapsed number of cycles since
 326  *      the most recent pause instruction against the pause filter threshold.
 327  *      If the elapsed cycle count is greater than the pause filter threshold,
 328  *      then the internal pause count is reloaded from the VMCB and execution
 329  *      continues. If the elapsed cycle count is less than the pause filter
 330  *      threshold, then the internal pause count is decremented. If the count
 331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 332  *      triggered. If advanced pause filtering is supported and pause filter
 333  *      threshold field is set to zero, the filter will operate in the simpler,
 334  *      count only mode.
 335  */
 336
 337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 338 module_param(pause_filter_thresh, ushort, 0444);
 339
 340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 341 module_param(pause_filter_count, ushort, 0444);
 342
 343 /* Default doubles per-vcpu window every exit. */
 344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 345 module_param(pause_filter_count_grow, ushort, 0444);
 346
 347 /* Default resets per-vcpu window every exit to pause_filter_count. */
 348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 349 module_param(pause_filter_count_shrink, ushort, 0444);
 350
 351 /* Default is to compute the maximum so we can never overflow. */
 352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 353 module_param(pause_filter_count_max, ushort, 0444);
 354
 355 /* allow nested paging (virtualized MMU) for all guests */
 356 static int npt = true;
 357 module_param(npt, int, S_IRUGO);
 358
 359 /* allow nested virtualization in KVM/SVM */
 360 static int nested = true;
 361 module_param(nested, int, S_IRUGO);
 362
 363 /* enable / disable AVIC */
 364 static int avic;
 365 #ifdef CONFIG_X86_LOCAL_APIC
 366 module_param(avic, int, S_IRUGO);
 367 #endif
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 382
 383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 385 static void svm_complete_interrupts(struct vcpu_svm *svm);
 386
 387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 388 static int nested_svm_intercept(struct vcpu_svm *svm);
 389 static int nested_svm_vmexit(struct vcpu_svm *svm);
 390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 391                                       bool has_error_code, u32 error_code);
 392
 393 enum {
 394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 395                             pause filter count */
 396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 397         VMCB_ASID,       /* ASID */
 398         VMCB_INTR,       /* int_ctl, int_vector */
 399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 401         VMCB_DR,         /* DR6, DR7 */
 402         VMCB_DT,         /* GDT, IDT */
 403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 404         VMCB_CR2,        /* CR2 only */
 405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 407                           * AVIC PHYSICAL_TABLE pointer,
 408                           * AVIC LOGICAL_TABLE pointer
 409                           */
 410         VMCB_DIRTY_MAX,
 411 };
 412
 413 /* TPR and CR2 are always written before VMRUN */
 414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 415
 416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 417
 418 static unsigned int max_sev_asid;
 419 static unsigned int min_sev_asid;
 420 static unsigned long *sev_asid_bitmap;
 421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 422
 423 struct enc_region {
 424         struct list_head list;
 425         unsigned long npages;
 426         struct page **pages;
 427         unsigned long uaddr;
 428         unsigned long size;
 429 };
 430
 431
 432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 433 {
 434         return container_of(kvm, struct kvm_svm, kvm);
 435 }
 436
 437 static inline bool svm_sev_enabled(void)
 438 {
 439         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 440 }
 441
 442 static inline bool sev_guest(struct kvm *kvm)
 443 {
 444 #ifdef CONFIG_KVM_AMD_SEV
 445         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 446
 447         return sev->active;
 448 #else
 449         return false;
 450 #endif
 451 }
 452
 453 static inline int sev_get_asid(struct kvm *kvm)
 454 {
 455         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 456
 457         return sev->asid;
 458 }
 459
 460 static inline void mark_all_dirty(struct vmcb *vmcb)
 461 {
 462         vmcb->control.clean = 0;
 463 }
 464
 465 static inline void mark_all_clean(struct vmcb *vmcb)
 466 {
 467         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 468                                & ~VMCB_ALWAYS_DIRTY_MASK;
 469 }
 470
 471 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 472 {
 473         vmcb->control.clean &= ~(1 << bit);
 474 }
 475
 476 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 477 {
 478         return container_of(vcpu, struct vcpu_svm, vcpu);
 479 }
 480
 481 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 482 {
 483         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 484         mark_dirty(svm->vmcb, VMCB_AVIC);
 485 }
 486
 487 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 488 {
 489         struct vcpu_svm *svm = to_svm(vcpu);
 490         u64 *entry = svm->avic_physical_id_cache;
 491
 492         if (!entry)
 493                 return false;
 494
 495         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 496 }
 497
 498 static void recalc_intercepts(struct vcpu_svm *svm)
 499 {
 500         struct vmcb_control_area *c, *h;
 501         struct nested_state *g;
 502
 503         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 504
 505         if (!is_guest_mode(&svm->vcpu))
 506                 return;
 507
 508         c = &svm->vmcb->control;
 509         h = &svm->nested.hsave->control;
 510         g = &svm->nested;
 511
 512         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 513         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 514         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 515         c->intercept = h->intercept | g->intercept;
 516 }
 517
 518 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 519 {
 520         if (is_guest_mode(&svm->vcpu))
 521                 return svm->nested.hsave;
 522         else
 523                 return svm->vmcb;
 524 }
 525
 526 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 527 {
 528         struct vmcb *vmcb = get_host_vmcb(svm);
 529
 530         vmcb->control.intercept_cr |= (1U << bit);
 531
 532         recalc_intercepts(svm);
 533 }
 534
 535 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 536 {
 537         struct vmcb *vmcb = get_host_vmcb(svm);
 538
 539         vmcb->control.intercept_cr &= ~(1U << bit);
 540
 541         recalc_intercepts(svm);
 542 }
 543
 544 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 545 {
 546         struct vmcb *vmcb = get_host_vmcb(svm);
 547
 548         return vmcb->control.intercept_cr & (1U << bit);
 549 }
 550
 551 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 552 {
 553         struct vmcb *vmcb = get_host_vmcb(svm);
 554
 555         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 556                 | (1 << INTERCEPT_DR1_READ)
 557                 | (1 << INTERCEPT_DR2_READ)
 558                 | (1 << INTERCEPT_DR3_READ)
 559                 | (1 << INTERCEPT_DR4_READ)
 560                 | (1 << INTERCEPT_DR5_READ)
 561                 | (1 << INTERCEPT_DR6_READ)
 562                 | (1 << INTERCEPT_DR7_READ)
 563                 | (1 << INTERCEPT_DR0_WRITE)
 564                 | (1 << INTERCEPT_DR1_WRITE)
 565                 | (1 << INTERCEPT_DR2_WRITE)
 566                 | (1 << INTERCEPT_DR3_WRITE)
 567                 | (1 << INTERCEPT_DR4_WRITE)
 568                 | (1 << INTERCEPT_DR5_WRITE)
 569                 | (1 << INTERCEPT_DR6_WRITE)
 570                 | (1 << INTERCEPT_DR7_WRITE);
 571
 572         recalc_intercepts(svm);
 573 }
 574
 575 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 576 {
 577         struct vmcb *vmcb = get_host_vmcb(svm);
 578
 579         vmcb->control.intercept_dr = 0;
 580
 581         recalc_intercepts(svm);
 582 }
 583
 584 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 585 {
 586         struct vmcb *vmcb = get_host_vmcb(svm);
 587
 588         vmcb->control.intercept_exceptions |= (1U << bit);
 589
 590         recalc_intercepts(svm);
 591 }
 592
 593 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 594 {
 595         struct vmcb *vmcb = get_host_vmcb(svm);
 596
 597         vmcb->control.intercept_exceptions &= ~(1U << bit);
 598
 599         recalc_intercepts(svm);
 600 }
 601
 602 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 603 {
 604         struct vmcb *vmcb = get_host_vmcb(svm);
 605
 606         vmcb->control.intercept |= (1ULL << bit);
 607
 608         recalc_intercepts(svm);
 609 }
 610
 611 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 612 {
 613         struct vmcb *vmcb = get_host_vmcb(svm);
 614
 615         vmcb->control.intercept &= ~(1ULL << bit);
 616
 617         recalc_intercepts(svm);
 618 }
 619
 620 static inline bool vgif_enabled(struct vcpu_svm *svm)
 621 {
 622         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 623 }
 624
 625 static inline void enable_gif(struct vcpu_svm *svm)
 626 {
 627         if (vgif_enabled(svm))
 628                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 629         else
 630                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 631 }
 632
 633 static inline void disable_gif(struct vcpu_svm *svm)
 634 {
 635         if (vgif_enabled(svm))
 636                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 637         else
 638                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 639 }
 640
 641 static inline bool gif_set(struct vcpu_svm *svm)
 642 {
 643         if (vgif_enabled(svm))
 644                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 645         else
 646                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 647 }
 648
 649 static unsigned long iopm_base;
 650
 651 struct kvm_ldttss_desc {
 652         u16 limit0;
 653         u16 base0;
 654         unsigned base1:8, type:5, dpl:2, p:1;
 655         unsigned limit1:4, zero0:3, g:1, base2:8;
 656         u32 base3;
 657         u32 zero1;
 658 } __attribute__((packed));
 659
 660 struct svm_cpu_data {
 661         int cpu;
 662
 663         u64 asid_generation;
 664         u32 max_asid;
 665         u32 next_asid;
 666         u32 min_asid;
 667         struct kvm_ldttss_desc *tss_desc;
 668
 669         struct page *save_area;
 670         struct vmcb *current_vmcb;
 671
 672         /* index = sev_asid, value = vmcb pointer */
 673         struct vmcb **sev_vmcbs;
 674 };
 675
 676 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 677
 678 struct svm_init_data {
 679         int cpu;
 680         int r;
 681 };
 682
 683 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 684
 685 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 686 #define MSRS_RANGE_SIZE 2048
 687 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 688
 689 static u32 svm_msrpm_offset(u32 msr)
 690 {
 691         u32 offset;
 692         int i;
 693
 694         for (i = 0; i < NUM_MSR_MAPS; i++) {
 695                 if (msr < msrpm_ranges[i] ||
 696                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 697                         continue;
 698
 699                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 700                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 701
 702                 /* Now we have the u8 offset - but need the u32 offset */
 703                 return offset / 4;
 704         }
 705
 706         /* MSR not in any range */
 707         return MSR_INVALID;
 708 }
 709
 710 #define MAX_INST_SIZE 15
 711
 712 static inline void clgi(void)
 713 {
 714         asm volatile (__ex(SVM_CLGI));
 715 }
 716
 717 static inline void stgi(void)
 718 {
 719         asm volatile (__ex(SVM_STGI));
 720 }
 721
 722 static inline void invlpga(unsigned long addr, u32 asid)
 723 {
 724         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 725 }
 726
 727 static int get_npt_level(struct kvm_vcpu *vcpu)
 728 {
 729 #ifdef CONFIG_X86_64
 730         return PT64_ROOT_4LEVEL;
 731 #else
 732         return PT32E_ROOT_LEVEL;
 733 #endif
 734 }
 735
 736 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 737 {
 738         vcpu->arch.efer = efer;
 739         if (!npt_enabled && !(efer & EFER_LMA))
 740                 efer &= ~EFER_LME;
 741
 742         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 743         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 744 }
 745
 746 static int is_external_interrupt(u32 info)
 747 {
 748         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 749         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 750 }
 751
 752 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 753 {
 754         struct vcpu_svm *svm = to_svm(vcpu);
 755         u32 ret = 0;
 756
 757         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 758                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 759         return ret;
 760 }
 761
 762 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 763 {
 764         struct vcpu_svm *svm = to_svm(vcpu);
 765
 766         if (mask == 0)
 767                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 768         else
 769                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 770
 771 }
 772
 773 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 774 {
 775         struct vcpu_svm *svm = to_svm(vcpu);
 776
 777         if (svm->vmcb->control.next_rip != 0) {
 778                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 779                 svm->next_rip = svm->vmcb->control.next_rip;
 780         }
 781
 782         if (!svm->next_rip) {
 783                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 784                                 EMULATE_DONE)
 785                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 786                 return;
 787         }
 788         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 789                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 790                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 791
 792         kvm_rip_write(vcpu, svm->next_rip);
 793         svm_set_interrupt_shadow(vcpu, 0);
 794 }
 795
 796 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 797 {
 798         struct vcpu_svm *svm = to_svm(vcpu);
 799         unsigned nr = vcpu->arch.exception.nr;
 800         bool has_error_code = vcpu->arch.exception.has_error_code;
 801         bool reinject = vcpu->arch.exception.injected;
 802         u32 error_code = vcpu->arch.exception.error_code;
 803
 804         /*
 805          * If we are within a nested VM we'd better #VMEXIT and let the guest
 806          * handle the exception
 807          */
 808         if (!reinject &&
 809             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 810                 return;
 811
 812         kvm_deliver_exception_payload(&svm->vcpu);
 813
 814         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 815                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 816
 817                 /*
 818                  * For guest debugging where we have to reinject #BP if some
 819                  * INT3 is guest-owned:
 820                  * Emulate nRIP by moving RIP forward. Will fail if injection
 821                  * raises a fault that is not intercepted. Still better than
 822                  * failing in all cases.
 823                  */
 824                 skip_emulated_instruction(&svm->vcpu);
 825                 rip = kvm_rip_read(&svm->vcpu);
 826                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 827                 svm->int3_injected = rip - old_rip;
 828         }
 829
 830         svm->vmcb->control.event_inj = nr
 831                 | SVM_EVTINJ_VALID
 832                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 833                 | SVM_EVTINJ_TYPE_EXEPT;
 834         svm->vmcb->control.event_inj_err = error_code;
 835 }
 836
 837 static void svm_init_erratum_383(void)
 838 {
 839         u32 low, high;
 840         int err;
 841         u64 val;
 842
 843         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 844                 return;
 845
 846         /* Use _safe variants to not break nested virtualization */
 847         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 848         if (err)
 849                 return;
 850
 851         val |= (1ULL << 47);
 852
 853         low  = lower_32_bits(val);
 854         high = upper_32_bits(val);
 855
 856         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 857
 858         erratum_383_found = true;
 859 }
 860
 861 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 862 {
 863         /*
 864          * Guests should see errata 400 and 415 as fixed (assuming that
 865          * HLT and IO instructions are intercepted).
 866          */
 867         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 868         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 869
 870         /*
 871          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 872          * all osvw.status bits inside that length, including bit 0 (which is
 873          * reserved for erratum 298), are valid. However, if host processor's
 874          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 875          * be conservative here and therefore we tell the guest that erratum 298
 876          * is present (because we really don't know).
 877          */
 878         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 879                 vcpu->arch.osvw.status |= 1;
 880 }
 881
 882 static int has_svm(void)
 883 {
 884         const char *msg;
 885
 886         if (!cpu_has_svm(&msg)) {
 887                 printk(KERN_INFO "has_svm: %s\n", msg);
 888                 return 0;
 889         }
 890
 891         return 1;
 892 }
 893
 894 static void svm_hardware_disable(void)
 895 {
 896         /* Make sure we clean up behind us */
 897         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 898                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 899
 900         cpu_svm_disable();
 901
 902         amd_pmu_disable_virt();
 903 }
 904
 905 static int svm_hardware_enable(void)
 906 {
 907
 908         struct svm_cpu_data *sd;
 909         uint64_t efer;
 910         struct desc_struct *gdt;
 911         int me = raw_smp_processor_id();
 912
 913         rdmsrl(MSR_EFER, efer);
 914         if (efer & EFER_SVME)
 915                 return -EBUSY;
 916
 917         if (!has_svm()) {
 918                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 919                 return -EINVAL;
 920         }
 921         sd = per_cpu(svm_data, me);
 922         if (!sd) {
 923                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 924                 return -EINVAL;
 925         }
 926
 927         sd->asid_generation = 1;
 928         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 929         sd->next_asid = sd->max_asid + 1;
 930         sd->min_asid = max_sev_asid + 1;
 931
 932         gdt = get_current_gdt_rw();
 933         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 934
 935         wrmsrl(MSR_EFER, efer | EFER_SVME);
 936
 937         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 938
 939         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 940                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 941                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 942         }
 943
 944
 945         /*
 946          * Get OSVW bits.
 947          *
 948          * Note that it is possible to have a system with mixed processor
 949          * revisions and therefore different OSVW bits. If bits are not the same
 950          * on different processors then choose the worst case (i.e. if erratum
 951          * is present on one processor and not on another then assume that the
 952          * erratum is present everywhere).
 953          */
 954         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 955                 uint64_t len, status = 0;
 956                 int err;
 957
 958                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 959                 if (!err)
 960                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 961                                                       &err);
 962
 963                 if (err)
 964                         osvw_status = osvw_len = 0;
 965                 else {
 966                         if (len < osvw_len)
 967                                 osvw_len = len;
 968                         osvw_status |= status;
 969                         osvw_status &= (1ULL << osvw_len) - 1;
 970                 }
 971         } else
 972                 osvw_status = osvw_len = 0;
 973
 974         svm_init_erratum_383();
 975
 976         amd_pmu_enable_virt();
 977
 978         return 0;
 979 }
 980
 981 static void svm_cpu_uninit(int cpu)
 982 {
 983         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 984
 985         if (!sd)
 986                 return;
 987
 988         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 989         kfree(sd->sev_vmcbs);
 990         __free_page(sd->save_area);
 991         kfree(sd);
 992 }
 993
 994 static int svm_cpu_init(int cpu)
 995 {
 996         struct svm_cpu_data *sd;
 997         int r;
 998
 999         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1000         if (!sd)
1001                 return -ENOMEM;
1002         sd->cpu = cpu;
1003         r = -ENOMEM;
1004         sd->save_area = alloc_page(GFP_KERNEL);
1005         if (!sd->save_area)
1006                 goto err_1;
1007
1008         if (svm_sev_enabled()) {
1009                 r = -ENOMEM;
1010                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1011                                               sizeof(void *),
1012                                               GFP_KERNEL);
1013                 if (!sd->sev_vmcbs)
1014                         goto err_1;
1015         }
1016
1017         per_cpu(svm_data, cpu) = sd;
1018
1019         return 0;
1020
1021 err_1:
1022         kfree(sd);
1023         return r;
1024
1025 }
1026
1027 static bool valid_msr_intercept(u32 index)
1028 {
1029         int i;
1030
1031         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1032                 if (direct_access_msrs[i].index == index)
1033                         return true;
1034
1035         return false;
1036 }
1037
1038 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1039 {
1040         u8 bit_write;
1041         unsigned long tmp;
1042         u32 offset;
1043         u32 *msrpm;
1044
1045         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1046                                       to_svm(vcpu)->msrpm;
1047
1048         offset    = svm_msrpm_offset(msr);
1049         bit_write = 2 * (msr & 0x0f) + 1;
1050         tmp       = msrpm[offset];
1051
1052         BUG_ON(offset == MSR_INVALID);
1053
1054         return !!test_bit(bit_write,  &tmp);
1055 }
1056
1057 static void set_msr_interception(u32 *msrpm, unsigned msr,
1058                                  int read, int write)
1059 {
1060         u8 bit_read, bit_write;
1061         unsigned long tmp;
1062         u32 offset;
1063
1064         /*
1065          * If this warning triggers extend the direct_access_msrs list at the
1066          * beginning of the file
1067          */
1068         WARN_ON(!valid_msr_intercept(msr));
1069
1070         offset    = svm_msrpm_offset(msr);
1071         bit_read  = 2 * (msr & 0x0f);
1072         bit_write = 2 * (msr & 0x0f) + 1;
1073         tmp       = msrpm[offset];
1074
1075         BUG_ON(offset == MSR_INVALID);
1076
1077         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1078         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1079
1080         msrpm[offset] = tmp;
1081 }
1082
1083 static void svm_vcpu_init_msrpm(u32 *msrpm)
1084 {
1085         int i;
1086
1087         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1088
1089         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1090                 if (!direct_access_msrs[i].always)
1091                         continue;
1092
1093                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1094         }
1095 }
1096
1097 static void add_msr_offset(u32 offset)
1098 {
1099         int i;
1100
1101         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1102
1103                 /* Offset already in list? */
1104                 if (msrpm_offsets[i] == offset)
1105                         return;
1106
1107                 /* Slot used by another offset? */
1108                 if (msrpm_offsets[i] != MSR_INVALID)
1109                         continue;
1110
1111                 /* Add offset to list */
1112                 msrpm_offsets[i] = offset;
1113
1114                 return;
1115         }
1116
1117         /*
1118          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1119          * increase MSRPM_OFFSETS in this case.
1120          */
1121         BUG();
1122 }
1123
1124 static void init_msrpm_offsets(void)
1125 {
1126         int i;
1127
1128         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1129
1130         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1131                 u32 offset;
1132
1133                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1134                 BUG_ON(offset == MSR_INVALID);
1135
1136                 add_msr_offset(offset);
1137         }
1138 }
1139
1140 static void svm_enable_lbrv(struct vcpu_svm *svm)
1141 {
1142         u32 *msrpm = svm->msrpm;
1143
1144         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1145         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1146         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1147         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1148         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1149 }
1150
1151 static void svm_disable_lbrv(struct vcpu_svm *svm)
1152 {
1153         u32 *msrpm = svm->msrpm;
1154
1155         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1156         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1157         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1158         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1159         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1160 }
1161
1162 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1163 {
1164         svm->nmi_singlestep = false;
1165
1166         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1167                 /* Clear our flags if they were not set by the guest */
1168                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1169                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1170                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1171                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1172         }
1173 }
1174
1175 /* Note:
1176  * This hash table is used to map VM_ID to a struct kvm_svm,
1177  * when handling AMD IOMMU GALOG notification to schedule in
1178  * a particular vCPU.
1179  */
1180 #define SVM_VM_DATA_HASH_BITS   8
1181 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1182 static u32 next_vm_id = 0;
1183 static bool next_vm_id_wrapped = 0;
1184 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1185
1186 /* Note:
1187  * This function is called from IOMMU driver to notify
1188  * SVM to schedule in a particular vCPU of a particular VM.
1189  */
1190 static int avic_ga_log_notifier(u32 ga_tag)
1191 {
1192         unsigned long flags;
1193         struct kvm_svm *kvm_svm;
1194         struct kvm_vcpu *vcpu = NULL;
1195         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1196         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1197
1198         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1199
1200         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1201         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1202                 if (kvm_svm->avic_vm_id != vm_id)
1203                         continue;
1204                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1205                 break;
1206         }
1207         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1208
1209         /* Note:
1210          * At this point, the IOMMU should have already set the pending
1211          * bit in the vAPIC backing page. So, we just need to schedule
1212          * in the vcpu.
1213          */
1214         if (vcpu)
1215                 kvm_vcpu_wake_up(vcpu);
1216
1217         return 0;
1218 }
1219
1220 static __init int sev_hardware_setup(void)
1221 {
1222         struct sev_user_data_status *status;
1223         int rc;
1224
1225         /* Maximum number of encrypted guests supported simultaneously */
1226         max_sev_asid = cpuid_ecx(0x8000001F);
1227
1228         if (!max_sev_asid)
1229                 return 1;
1230
1231         /* Minimum ASID value that should be used for SEV guest */
1232         min_sev_asid = cpuid_edx(0x8000001F);
1233
1234         /* Initialize SEV ASID bitmap */
1235         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1236         if (!sev_asid_bitmap)
1237                 return 1;
1238
1239         status = kmalloc(sizeof(*status), GFP_KERNEL);
1240         if (!status)
1241                 return 1;
1242
1243         /*
1244          * Check SEV platform status.
1245          *
1246          * PLATFORM_STATUS can be called in any state, if we failed to query
1247          * the PLATFORM status then either PSP firmware does not support SEV
1248          * feature or SEV firmware is dead.
1249          */
1250         rc = sev_platform_status(status, NULL);
1251         if (rc)
1252                 goto err;
1253
1254         pr_info("SEV supported\n");
1255
1256 err:
1257         kfree(status);
1258         return rc;
1259 }
1260
1261 static void grow_ple_window(struct kvm_vcpu *vcpu)
1262 {
1263         struct vcpu_svm *svm = to_svm(vcpu);
1264         struct vmcb_control_area *control = &svm->vmcb->control;
1265         int old = control->pause_filter_count;
1266
1267         control->pause_filter_count = __grow_ple_window(old,
1268                                                         pause_filter_count,
1269                                                         pause_filter_count_grow,
1270                                                         pause_filter_count_max);
1271
1272         if (control->pause_filter_count != old)
1273                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1274
1275         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1276                                   control->pause_filter_count, old);
1277 }
1278
1279 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1280 {
1281         struct vcpu_svm *svm = to_svm(vcpu);
1282         struct vmcb_control_area *control = &svm->vmcb->control;
1283         int old = control->pause_filter_count;
1284
1285         control->pause_filter_count =
1286                                 __shrink_ple_window(old,
1287                                                     pause_filter_count,
1288                                                     pause_filter_count_shrink,
1289                                                     pause_filter_count);
1290         if (control->pause_filter_count != old)
1291                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1292
1293         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1294                                     control->pause_filter_count, old);
1295 }
1296
1297 static __init int svm_hardware_setup(void)
1298 {
1299         int cpu;
1300         struct page *iopm_pages;
1301         void *iopm_va;
1302         int r;
1303
1304         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1305
1306         if (!iopm_pages)
1307                 return -ENOMEM;
1308
1309         iopm_va = page_address(iopm_pages);
1310         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1311         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1312
1313         init_msrpm_offsets();
1314
1315         if (boot_cpu_has(X86_FEATURE_NX))
1316                 kvm_enable_efer_bits(EFER_NX);
1317
1318         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1319                 kvm_enable_efer_bits(EFER_FFXSR);
1320
1321         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1322                 kvm_has_tsc_control = true;
1323                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1324                 kvm_tsc_scaling_ratio_frac_bits = 32;
1325         }
1326
1327         /* Check for pause filtering support */
1328         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1329                 pause_filter_count = 0;
1330                 pause_filter_thresh = 0;
1331         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1332                 pause_filter_thresh = 0;
1333         }
1334
1335         if (nested) {
1336                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1337                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1338         }
1339
1340         if (sev) {
1341                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1342                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1343                         r = sev_hardware_setup();
1344                         if (r)
1345                                 sev = false;
1346                 } else {
1347                         sev = false;
1348                 }
1349         }
1350
1351         for_each_possible_cpu(cpu) {
1352                 r = svm_cpu_init(cpu);
1353                 if (r)
1354                         goto err;
1355         }
1356
1357         if (!boot_cpu_has(X86_FEATURE_NPT))
1358                 npt_enabled = false;
1359
1360         if (npt_enabled && !npt) {
1361                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1362                 npt_enabled = false;
1363         }
1364
1365         if (npt_enabled) {
1366                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1367                 kvm_enable_tdp();
1368         } else
1369                 kvm_disable_tdp();
1370
1371         if (avic) {
1372                 if (!npt_enabled ||
1373                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1374                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1375                         avic = false;
1376                 } else {
1377                         pr_info("AVIC enabled\n");
1378
1379                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1380                 }
1381         }
1382
1383         if (vls) {
1384                 if (!npt_enabled ||
1385                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1386                     !IS_ENABLED(CONFIG_X86_64)) {
1387                         vls = false;
1388                 } else {
1389                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1390                 }
1391         }
1392
1393         if (vgif) {
1394                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1395                         vgif = false;
1396                 else
1397                         pr_info("Virtual GIF supported\n");
1398         }
1399
1400         return 0;
1401
1402 err:
1403         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1404         iopm_base = 0;
1405         return r;
1406 }
1407
1408 static __exit void svm_hardware_unsetup(void)
1409 {
1410         int cpu;
1411
1412         if (svm_sev_enabled())
1413                 bitmap_free(sev_asid_bitmap);
1414
1415         for_each_possible_cpu(cpu)
1416                 svm_cpu_uninit(cpu);
1417
1418         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1419         iopm_base = 0;
1420 }
1421
1422 static void init_seg(struct vmcb_seg *seg)
1423 {
1424         seg->selector = 0;
1425         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1426                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1427         seg->limit = 0xffff;
1428         seg->base = 0;
1429 }
1430
1431 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1432 {
1433         seg->selector = 0;
1434         seg->attrib = SVM_SELECTOR_P_MASK | type;
1435         seg->limit = 0xffff;
1436         seg->base = 0;
1437 }
1438
1439 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1440 {
1441         struct vcpu_svm *svm = to_svm(vcpu);
1442
1443         if (is_guest_mode(vcpu))
1444                 return svm->nested.hsave->control.tsc_offset;
1445
1446         return vcpu->arch.tsc_offset;
1447 }
1448
1449 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1450 {
1451         struct vcpu_svm *svm = to_svm(vcpu);
1452         u64 g_tsc_offset = 0;
1453
1454         if (is_guest_mode(vcpu)) {
1455                 /* Write L1's TSC offset.  */
1456                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1457                                svm->nested.hsave->control.tsc_offset;
1458                 svm->nested.hsave->control.tsc_offset = offset;
1459         }
1460
1461         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1462                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1463                                    offset);
1464
1465         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1466
1467         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1468         return svm->vmcb->control.tsc_offset;
1469 }
1470
1471 static void avic_init_vmcb(struct vcpu_svm *svm)
1472 {
1473         struct vmcb *vmcb = svm->vmcb;
1474         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1475         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1476         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1477         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1478
1479         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1480         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1481         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1482         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1483         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1484 }
1485
1486 static void init_vmcb(struct vcpu_svm *svm)
1487 {
1488         struct vmcb_control_area *control = &svm->vmcb->control;
1489         struct vmcb_save_area *save = &svm->vmcb->save;
1490
1491         svm->vcpu.arch.hflags = 0;
1492
1493         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1494         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1495         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1496         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1497         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1498         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1499         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1500                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1501
1502         set_dr_intercepts(svm);
1503
1504         set_exception_intercept(svm, PF_VECTOR);
1505         set_exception_intercept(svm, UD_VECTOR);
1506         set_exception_intercept(svm, MC_VECTOR);
1507         set_exception_intercept(svm, AC_VECTOR);
1508         set_exception_intercept(svm, DB_VECTOR);
1509         /*
1510          * Guest access to VMware backdoor ports could legitimately
1511          * trigger #GP because of TSS I/O permission bitmap.
1512          * We intercept those #GP and allow access to them anyway
1513          * as VMware does.
1514          */
1515         if (enable_vmware_backdoor)
1516                 set_exception_intercept(svm, GP_VECTOR);
1517
1518         set_intercept(svm, INTERCEPT_INTR);
1519         set_intercept(svm, INTERCEPT_NMI);
1520         set_intercept(svm, INTERCEPT_SMI);
1521         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1522         set_intercept(svm, INTERCEPT_RDPMC);
1523         set_intercept(svm, INTERCEPT_CPUID);
1524         set_intercept(svm, INTERCEPT_INVD);
1525         set_intercept(svm, INTERCEPT_INVLPG);
1526         set_intercept(svm, INTERCEPT_INVLPGA);
1527         set_intercept(svm, INTERCEPT_IOIO_PROT);
1528         set_intercept(svm, INTERCEPT_MSR_PROT);
1529         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1530         set_intercept(svm, INTERCEPT_SHUTDOWN);
1531         set_intercept(svm, INTERCEPT_VMRUN);
1532         set_intercept(svm, INTERCEPT_VMMCALL);
1533         set_intercept(svm, INTERCEPT_VMLOAD);
1534         set_intercept(svm, INTERCEPT_VMSAVE);
1535         set_intercept(svm, INTERCEPT_STGI);
1536         set_intercept(svm, INTERCEPT_CLGI);
1537         set_intercept(svm, INTERCEPT_SKINIT);
1538         set_intercept(svm, INTERCEPT_WBINVD);
1539         set_intercept(svm, INTERCEPT_XSETBV);
1540         set_intercept(svm, INTERCEPT_RSM);
1541
1542         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1543                 set_intercept(svm, INTERCEPT_MONITOR);
1544                 set_intercept(svm, INTERCEPT_MWAIT);
1545         }
1546
1547         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1548                 set_intercept(svm, INTERCEPT_HLT);
1549
1550         control->iopm_base_pa = __sme_set(iopm_base);
1551         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1552         control->int_ctl = V_INTR_MASKING_MASK;
1553
1554         init_seg(&save->es);
1555         init_seg(&save->ss);
1556         init_seg(&save->ds);
1557         init_seg(&save->fs);
1558         init_seg(&save->gs);
1559
1560         save->cs.selector = 0xf000;
1561         save->cs.base = 0xffff0000;
1562         /* Executable/Readable Code Segment */
1563         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1564                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1565         save->cs.limit = 0xffff;
1566
1567         save->gdtr.limit = 0xffff;
1568         save->idtr.limit = 0xffff;
1569
1570         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1571         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1572
1573         svm_set_efer(&svm->vcpu, 0);
1574         save->dr6 = 0xffff0ff0;
1575         kvm_set_rflags(&svm->vcpu, 2);
1576         save->rip = 0x0000fff0;
1577         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1578
1579         /*
1580          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1581          * It also updates the guest-visible cr0 value.
1582          */
1583         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1584         kvm_mmu_reset_context(&svm->vcpu);
1585
1586         save->cr4 = X86_CR4_PAE;
1587         /* rdx = ?? */
1588
1589         if (npt_enabled) {
1590                 /* Setup VMCB for Nested Paging */
1591                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1592                 clr_intercept(svm, INTERCEPT_INVLPG);
1593                 clr_exception_intercept(svm, PF_VECTOR);
1594                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1595                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1596                 save->g_pat = svm->vcpu.arch.pat;
1597                 save->cr3 = 0;
1598                 save->cr4 = 0;
1599         }
1600         svm->asid_generation = 0;
1601
1602         svm->nested.vmcb = 0;
1603         svm->vcpu.arch.hflags = 0;
1604
1605         if (pause_filter_count) {
1606                 control->pause_filter_count = pause_filter_count;
1607                 if (pause_filter_thresh)
1608                         control->pause_filter_thresh = pause_filter_thresh;
1609                 set_intercept(svm, INTERCEPT_PAUSE);
1610         } else {
1611                 clr_intercept(svm, INTERCEPT_PAUSE);
1612         }
1613
1614         if (kvm_vcpu_apicv_active(&svm->vcpu))
1615                 avic_init_vmcb(svm);
1616
1617         /*
1618          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1619          * in VMCB and clear intercepts to avoid #VMEXIT.
1620          */
1621         if (vls) {
1622                 clr_intercept(svm, INTERCEPT_VMLOAD);
1623                 clr_intercept(svm, INTERCEPT_VMSAVE);
1624                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1625         }
1626
1627         if (vgif) {
1628                 clr_intercept(svm, INTERCEPT_STGI);
1629                 clr_intercept(svm, INTERCEPT_CLGI);
1630                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1631         }
1632
1633         if (sev_guest(svm->vcpu.kvm)) {
1634                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1635                 clr_exception_intercept(svm, UD_VECTOR);
1636         }
1637
1638         mark_all_dirty(svm->vmcb);
1639
1640         enable_gif(svm);
1641
1642 }
1643
1644 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1645                                        unsigned int index)
1646 {
1647         u64 *avic_physical_id_table;
1648         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1649
1650         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1651                 return NULL;
1652
1653         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1654
1655         return &avic_physical_id_table[index];
1656 }
1657
1658 /**
1659  * Note:
1660  * AVIC hardware walks the nested page table to check permissions,
1661  * but does not use the SPA address specified in the leaf page
1662  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1663  * field of the VMCB. Therefore, we set up the
1664  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1665  */
1666 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1667 {
1668         struct kvm *kvm = vcpu->kvm;
1669         int ret = 0;
1670
1671         mutex_lock(&kvm->slots_lock);
1672         if (kvm->arch.apic_access_page_done)
1673                 goto out;
1674
1675         ret = __x86_set_memory_region(kvm,
1676                                       APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1677                                       APIC_DEFAULT_PHYS_BASE,
1678                                       PAGE_SIZE);
1679         if (ret)
1680                 goto out;
1681
1682         kvm->arch.apic_access_page_done = true;
1683 out:
1684         mutex_unlock(&kvm->slots_lock);
1685         return ret;
1686 }
1687
1688 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1689 {
1690         int ret;
1691         u64 *entry, new_entry;
1692         int id = vcpu->vcpu_id;
1693         struct vcpu_svm *svm = to_svm(vcpu);
1694
1695         ret = avic_init_access_page(vcpu);
1696         if (ret)
1697                 return ret;
1698
1699         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1700                 return -EINVAL;
1701
1702         if (!svm->vcpu.arch.apic->regs)
1703                 return -EINVAL;
1704
1705         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1706
1707         /* Setting AVIC backing page address in the phy APIC ID table */
1708         entry = avic_get_physical_id_entry(vcpu, id);
1709         if (!entry)
1710                 return -EINVAL;
1711
1712         new_entry = READ_ONCE(*entry);
1713         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1714                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1715                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1716         WRITE_ONCE(*entry, new_entry);
1717
1718         svm->avic_physical_id_cache = entry;
1719
1720         return 0;
1721 }
1722
1723 static void __sev_asid_free(int asid)
1724 {
1725         struct svm_cpu_data *sd;
1726         int cpu, pos;
1727
1728         pos = asid - 1;
1729         clear_bit(pos, sev_asid_bitmap);
1730
1731         for_each_possible_cpu(cpu) {
1732                 sd = per_cpu(svm_data, cpu);
1733                 sd->sev_vmcbs[pos] = NULL;
1734         }
1735 }
1736
1737 static void sev_asid_free(struct kvm *kvm)
1738 {
1739         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1740
1741         __sev_asid_free(sev->asid);
1742 }
1743
1744 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1745 {
1746         struct sev_data_decommission *decommission;
1747         struct sev_data_deactivate *data;
1748
1749         if (!handle)
1750                 return;
1751
1752         data = kzalloc(sizeof(*data), GFP_KERNEL);
1753         if (!data)
1754                 return;
1755
1756         /* deactivate handle */
1757         data->handle = handle;
1758         sev_guest_deactivate(data, NULL);
1759
1760         wbinvd_on_all_cpus();
1761         sev_guest_df_flush(NULL);
1762         kfree(data);
1763
1764         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1765         if (!decommission)
1766                 return;
1767
1768         /* decommission handle */
1769         decommission->handle = handle;
1770         sev_guest_decommission(decommission, NULL);
1771
1772         kfree(decommission);
1773 }
1774
1775 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1776                                     unsigned long ulen, unsigned long *n,
1777                                     int write)
1778 {
1779         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1780         unsigned long npages, npinned, size;
1781         unsigned long locked, lock_limit;
1782         struct page **pages;
1783         unsigned long first, last;
1784
1785         if (ulen == 0 || uaddr + ulen < uaddr)
1786                 return NULL;
1787
1788         /* Calculate number of pages. */
1789         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1790         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1791         npages = (last - first + 1);
1792
1793         locked = sev->pages_locked + npages;
1794         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1795         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1796                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1797                 return NULL;
1798         }
1799
1800         /* Avoid using vmalloc for smaller buffers. */
1801         size = npages * sizeof(struct page *);
1802         if (size > PAGE_SIZE)
1803                 pages = vmalloc(size);
1804         else
1805                 pages = kmalloc(size, GFP_KERNEL);
1806
1807         if (!pages)
1808                 return NULL;
1809
1810         /* Pin the user virtual address. */
1811         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1812         if (npinned != npages) {
1813                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1814                 goto err;
1815         }
1816
1817         *n = npages;
1818         sev->pages_locked = locked;
1819
1820         return pages;
1821
1822 err:
1823         if (npinned > 0)
1824                 release_pages(pages, npinned);
1825
1826         kvfree(pages);
1827         return NULL;
1828 }
1829
1830 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1831                              unsigned long npages)
1832 {
1833         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1834
1835         release_pages(pages, npages);
1836         kvfree(pages);
1837         sev->pages_locked -= npages;
1838 }
1839
1840 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1841 {
1842         uint8_t *page_virtual;
1843         unsigned long i;
1844
1845         if (npages == 0 || pages == NULL)
1846                 return;
1847
1848         for (i = 0; i < npages; i++) {
1849                 page_virtual = kmap_atomic(pages[i]);
1850                 clflush_cache_range(page_virtual, PAGE_SIZE);
1851                 kunmap_atomic(page_virtual);
1852         }
1853 }
1854
1855 static void __unregister_enc_region_locked(struct kvm *kvm,
1856                                            struct enc_region *region)
1857 {
1858         /*
1859          * The guest may change the memory encryption attribute from C=0 -> C=1
1860          * or vice versa for this memory range. Lets make sure caches are
1861          * flushed to ensure that guest data gets written into memory with
1862          * correct C-bit.
1863          */
1864         sev_clflush_pages(region->pages, region->npages);
1865
1866         sev_unpin_memory(kvm, region->pages, region->npages);
1867         list_del(&region->list);
1868         kfree(region);
1869 }
1870
1871 static struct kvm *svm_vm_alloc(void)
1872 {
1873         struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1874         return &kvm_svm->kvm;
1875 }
1876
1877 static void svm_vm_free(struct kvm *kvm)
1878 {
1879         vfree(to_kvm_svm(kvm));
1880 }
1881
1882 static void sev_vm_destroy(struct kvm *kvm)
1883 {
1884         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1885         struct list_head *head = &sev->regions_list;
1886         struct list_head *pos, *q;
1887
1888         if (!sev_guest(kvm))
1889                 return;
1890
1891         mutex_lock(&kvm->lock);
1892
1893         /*
1894          * if userspace was terminated before unregistering the memory regions
1895          * then lets unpin all the registered memory.
1896          */
1897         if (!list_empty(head)) {
1898                 list_for_each_safe(pos, q, head) {
1899                         __unregister_enc_region_locked(kvm,
1900                                 list_entry(pos, struct enc_region, list));
1901                 }
1902         }
1903
1904         mutex_unlock(&kvm->lock);
1905
1906         sev_unbind_asid(kvm, sev->handle);
1907         sev_asid_free(kvm);
1908 }
1909
1910 static void avic_vm_destroy(struct kvm *kvm)
1911 {
1912         unsigned long flags;
1913         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1914
1915         if (!avic)
1916                 return;
1917
1918         if (kvm_svm->avic_logical_id_table_page)
1919                 __free_page(kvm_svm->avic_logical_id_table_page);
1920         if (kvm_svm->avic_physical_id_table_page)
1921                 __free_page(kvm_svm->avic_physical_id_table_page);
1922
1923         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1924         hash_del(&kvm_svm->hnode);
1925         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1926 }
1927
1928 static void svm_vm_destroy(struct kvm *kvm)
1929 {
1930         avic_vm_destroy(kvm);
1931         sev_vm_destroy(kvm);
1932 }
1933
1934 static int avic_vm_init(struct kvm *kvm)
1935 {
1936         unsigned long flags;
1937         int err = -ENOMEM;
1938         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1939         struct kvm_svm *k2;
1940         struct page *p_page;
1941         struct page *l_page;
1942         u32 vm_id;
1943
1944         if (!avic)
1945                 return 0;
1946
1947         /* Allocating physical APIC ID table (4KB) */
1948         p_page = alloc_page(GFP_KERNEL);
1949         if (!p_page)
1950                 goto free_avic;
1951
1952         kvm_svm->avic_physical_id_table_page = p_page;
1953         clear_page(page_address(p_page));
1954
1955         /* Allocating logical APIC ID table (4KB) */
1956         l_page = alloc_page(GFP_KERNEL);
1957         if (!l_page)
1958                 goto free_avic;
1959
1960         kvm_svm->avic_logical_id_table_page = l_page;
1961         clear_page(page_address(l_page));
1962
1963         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1964  again:
1965         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1966         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1967                 next_vm_id_wrapped = 1;
1968                 goto again;
1969         }
1970         /* Is it still in use? Only possible if wrapped at least once */
1971         if (next_vm_id_wrapped) {
1972                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1973                         if (k2->avic_vm_id == vm_id)
1974                                 goto again;
1975                 }
1976         }
1977         kvm_svm->avic_vm_id = vm_id;
1978         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1979         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1980
1981         return 0;
1982
1983 free_avic:
1984         avic_vm_destroy(kvm);
1985         return err;
1986 }
1987
1988 static inline int
1989 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1990 {
1991         int ret = 0;
1992         unsigned long flags;
1993         struct amd_svm_iommu_ir *ir;
1994         struct vcpu_svm *svm = to_svm(vcpu);
1995
1996         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1997                 return 0;
1998
1999         /*
2000          * Here, we go through the per-vcpu ir_list to update all existing
2001          * interrupt remapping table entry targeting this vcpu.
2002          */
2003         spin_lock_irqsave(&svm->ir_list_lock, flags);
2004
2005         if (list_empty(&svm->ir_list))
2006                 goto out;
2007
2008         list_for_each_entry(ir, &svm->ir_list, node) {
2009                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2010                 if (ret)
2011                         break;
2012         }
2013 out:
2014         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2015         return ret;
2016 }
2017
2018 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2019 {
2020         u64 entry;
2021         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2022         int h_physical_id = kvm_cpu_get_apicid(cpu);
2023         struct vcpu_svm *svm = to_svm(vcpu);
2024
2025         if (!kvm_vcpu_apicv_active(vcpu))
2026                 return;
2027
2028         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2029                 return;
2030
2031         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2032         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2033
2034         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2035         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2036
2037         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2038         if (svm->avic_is_running)
2039                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2040
2041         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2042         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2043                                         svm->avic_is_running);
2044 }
2045
2046 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2047 {
2048         u64 entry;
2049         struct vcpu_svm *svm = to_svm(vcpu);
2050
2051         if (!kvm_vcpu_apicv_active(vcpu))
2052                 return;
2053
2054         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2055         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2056                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2057
2058         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2059         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2060 }
2061
2062 /**
2063  * This function is called during VCPU halt/unhalt.
2064  */
2065 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2066 {
2067         struct vcpu_svm *svm = to_svm(vcpu);
2068
2069         svm->avic_is_running = is_run;
2070         if (is_run)
2071                 avic_vcpu_load(vcpu, vcpu->cpu);
2072         else
2073                 avic_vcpu_put(vcpu);
2074 }
2075
2076 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2077 {
2078         struct vcpu_svm *svm = to_svm(vcpu);
2079         u32 dummy;
2080         u32 eax = 1;
2081
2082         vcpu->arch.microcode_version = 0x01000065;
2083         svm->spec_ctrl = 0;
2084         svm->virt_spec_ctrl = 0;
2085
2086         if (!init_event) {
2087                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2088                                            MSR_IA32_APICBASE_ENABLE;
2089                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2090                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2091         }
2092         init_vmcb(svm);
2093
2094         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2095         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2096
2097         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2098                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2099 }
2100
2101 static int avic_init_vcpu(struct vcpu_svm *svm)
2102 {
2103         int ret;
2104
2105         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2106                 return 0;
2107
2108         ret = avic_init_backing_page(&svm->vcpu);
2109         if (ret)
2110                 return ret;
2111
2112         INIT_LIST_HEAD(&svm->ir_list);
2113         spin_lock_init(&svm->ir_list_lock);
2114
2115         return ret;
2116 }
2117
2118 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2119 {
2120         struct vcpu_svm *svm;
2121         struct page *page;
2122         struct page *msrpm_pages;
2123         struct page *hsave_page;
2124         struct page *nested_msrpm_pages;
2125         int err;
2126
2127         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2128         if (!svm) {
2129                 err = -ENOMEM;
2130                 goto out;
2131         }
2132
2133         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2134         if (err)
2135                 goto free_svm;
2136
2137         err = -ENOMEM;
2138         page = alloc_page(GFP_KERNEL);
2139         if (!page)
2140                 goto uninit;
2141
2142         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2143         if (!msrpm_pages)
2144                 goto free_page1;
2145
2146         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2147         if (!nested_msrpm_pages)
2148                 goto free_page2;
2149
2150         hsave_page = alloc_page(GFP_KERNEL);
2151         if (!hsave_page)
2152                 goto free_page3;
2153
2154         err = avic_init_vcpu(svm);
2155         if (err)
2156                 goto free_page4;
2157
2158         /* We initialize this flag to true to make sure that the is_running
2159          * bit would be set the first time the vcpu is loaded.
2160          */
2161         svm->avic_is_running = true;
2162
2163         svm->nested.hsave = page_address(hsave_page);
2164
2165         svm->msrpm = page_address(msrpm_pages);
2166         svm_vcpu_init_msrpm(svm->msrpm);
2167
2168         svm->nested.msrpm = page_address(nested_msrpm_pages);
2169         svm_vcpu_init_msrpm(svm->nested.msrpm);
2170
2171         svm->vmcb = page_address(page);
2172         clear_page(svm->vmcb);
2173         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2174         svm->asid_generation = 0;
2175         init_vmcb(svm);
2176
2177         svm_init_osvw(&svm->vcpu);
2178
2179         return &svm->vcpu;
2180
2181 free_page4:
2182         __free_page(hsave_page);
2183 free_page3:
2184         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2185 free_page2:
2186         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2187 free_page1:
2188         __free_page(page);
2189 uninit:
2190         kvm_vcpu_uninit(&svm->vcpu);
2191 free_svm:
2192         kmem_cache_free(kvm_vcpu_cache, svm);
2193 out:
2194         return ERR_PTR(err);
2195 }
2196
2197 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2198 {
2199         int i;
2200
2201         for_each_online_cpu(i)
2202                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2203 }
2204
2205 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2206 {
2207         struct vcpu_svm *svm = to_svm(vcpu);
2208
2209         /*
2210          * The vmcb page can be recycled, causing a false negative in
2211          * svm_vcpu_load(). So, ensure that no logical CPU has this
2212          * vmcb page recorded as its current vmcb.
2213          */
2214         svm_clear_current_vmcb(svm->vmcb);
2215
2216         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2217         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2218         __free_page(virt_to_page(svm->nested.hsave));
2219         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2220         kvm_vcpu_uninit(vcpu);
2221         kmem_cache_free(kvm_vcpu_cache, svm);
2222 }
2223
2224 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2225 {
2226         struct vcpu_svm *svm = to_svm(vcpu);
2227         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2228         int i;
2229
2230         if (unlikely(cpu != vcpu->cpu)) {
2231                 svm->asid_generation = 0;
2232                 mark_all_dirty(svm->vmcb);
2233         }
2234
2235 #ifdef CONFIG_X86_64
2236         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2237 #endif
2238         savesegment(fs, svm->host.fs);
2239         savesegment(gs, svm->host.gs);
2240         svm->host.ldt = kvm_read_ldt();
2241
2242         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2243                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2244
2245         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2246                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2247                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2248                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2249                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2250                 }
2251         }
2252         /* This assumes that the kernel never uses MSR_TSC_AUX */
2253         if (static_cpu_has(X86_FEATURE_RDTSCP))
2254                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2255
2256         if (sd->current_vmcb != svm->vmcb) {
2257                 sd->current_vmcb = svm->vmcb;
2258                 indirect_branch_prediction_barrier();
2259         }
2260         avic_vcpu_load(vcpu, cpu);
2261 }
2262
2263 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2264 {
2265         struct vcpu_svm *svm = to_svm(vcpu);
2266         int i;
2267
2268         avic_vcpu_put(vcpu);
2269
2270         ++vcpu->stat.host_state_reload;
2271         kvm_load_ldt(svm->host.ldt);
2272 #ifdef CONFIG_X86_64
2273         loadsegment(fs, svm->host.fs);
2274         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2275         load_gs_index(svm->host.gs);
2276 #else
2277 #ifdef CONFIG_X86_32_LAZY_GS
2278         loadsegment(gs, svm->host.gs);
2279 #endif
2280 #endif
2281         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2282                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2283 }
2284
2285 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2286 {
2287         avic_set_running(vcpu, false);
2288 }
2289
2290 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2291 {
2292         avic_set_running(vcpu, true);
2293 }
2294
2295 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2296 {
2297         struct vcpu_svm *svm = to_svm(vcpu);
2298         unsigned long rflags = svm->vmcb->save.rflags;
2299
2300         if (svm->nmi_singlestep) {
2301                 /* Hide our flags if they were not set by the guest */
2302                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2303                         rflags &= ~X86_EFLAGS_TF;
2304                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2305                         rflags &= ~X86_EFLAGS_RF;
2306         }
2307         return rflags;
2308 }
2309
2310 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2311 {
2312         if (to_svm(vcpu)->nmi_singlestep)
2313                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2314
2315        /*
2316         * Any change of EFLAGS.VM is accompanied by a reload of SS
2317         * (caused by either a task switch or an inter-privilege IRET),
2318         * so we do not need to update the CPL here.
2319         */
2320         to_svm(vcpu)->vmcb->save.rflags = rflags;
2321 }
2322
2323 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2324 {
2325         switch (reg) {
2326         case VCPU_EXREG_PDPTR:
2327                 BUG_ON(!npt_enabled);
2328                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2329                 break;
2330         default:
2331                 BUG();
2332         }
2333 }
2334
2335 static void svm_set_vintr(struct vcpu_svm *svm)
2336 {
2337         set_intercept(svm, INTERCEPT_VINTR);
2338 }
2339
2340 static void svm_clear_vintr(struct vcpu_svm *svm)
2341 {
2342         clr_intercept(svm, INTERCEPT_VINTR);
2343 }
2344
2345 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2346 {
2347         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2348
2349         switch (seg) {
2350         case VCPU_SREG_CS: return &save->cs;
2351         case VCPU_SREG_DS: return &save->ds;
2352         case VCPU_SREG_ES: return &save->es;
2353         case VCPU_SREG_FS: return &save->fs;
2354         case VCPU_SREG_GS: return &save->gs;
2355         case VCPU_SREG_SS: return &save->ss;
2356         case VCPU_SREG_TR: return &save->tr;
2357         case VCPU_SREG_LDTR: return &save->ldtr;
2358         }
2359         BUG();
2360         return NULL;
2361 }
2362
2363 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2364 {
2365         struct vmcb_seg *s = svm_seg(vcpu, seg);
2366
2367         return s->base;
2368 }
2369
2370 static void svm_get_segment(struct kvm_vcpu *vcpu,
2371                             struct kvm_segment *var, int seg)
2372 {
2373         struct vmcb_seg *s = svm_seg(vcpu, seg);
2374
2375         var->base = s->base;
2376         var->limit = s->limit;
2377         var->selector = s->selector;
2378         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2379         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2380         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2381         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2382         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2383         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2384         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2385
2386         /*
2387          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2388          * However, the SVM spec states that the G bit is not observed by the
2389          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2390          * So let's synthesize a legal G bit for all segments, this helps
2391          * running KVM nested. It also helps cross-vendor migration, because
2392          * Intel's vmentry has a check on the 'G' bit.
2393          */
2394         var->g = s->limit > 0xfffff;
2395
2396         /*
2397          * AMD's VMCB does not have an explicit unusable field, so emulate it
2398          * for cross vendor migration purposes by "not present"
2399          */
2400         var->unusable = !var->present;
2401
2402         switch (seg) {
2403         case VCPU_SREG_TR:
2404                 /*
2405                  * Work around a bug where the busy flag in the tr selector
2406                  * isn't exposed
2407                  */
2408                 var->type |= 0x2;
2409                 break;
2410         case VCPU_SREG_DS:
2411         case VCPU_SREG_ES:
2412         case VCPU_SREG_FS:
2413         case VCPU_SREG_GS:
2414                 /*
2415                  * The accessed bit must always be set in the segment
2416                  * descriptor cache, although it can be cleared in the
2417                  * descriptor, the cached bit always remains at 1. Since
2418                  * Intel has a check on this, set it here to support
2419                  * cross-vendor migration.
2420                  */
2421                 if (!var->unusable)
2422                         var->type |= 0x1;
2423                 break;
2424         case VCPU_SREG_SS:
2425                 /*
2426                  * On AMD CPUs sometimes the DB bit in the segment
2427                  * descriptor is left as 1, although the whole segment has
2428                  * been made unusable. Clear it here to pass an Intel VMX
2429                  * entry check when cross vendor migrating.
2430                  */
2431                 if (var->unusable)
2432                         var->db = 0;
2433                 /* This is symmetric with svm_set_segment() */
2434                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2435                 break;
2436         }
2437 }
2438
2439 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2440 {
2441         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2442
2443         return save->cpl;
2444 }
2445
2446 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2447 {
2448         struct vcpu_svm *svm = to_svm(vcpu);
2449
2450         dt->size = svm->vmcb->save.idtr.limit;
2451         dt->address = svm->vmcb->save.idtr.base;
2452 }
2453
2454 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2455 {
2456         struct vcpu_svm *svm = to_svm(vcpu);
2457
2458         svm->vmcb->save.idtr.limit = dt->size;
2459         svm->vmcb->save.idtr.base = dt->address ;
2460         mark_dirty(svm->vmcb, VMCB_DT);
2461 }
2462
2463 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2464 {
2465         struct vcpu_svm *svm = to_svm(vcpu);
2466
2467         dt->size = svm->vmcb->save.gdtr.limit;
2468         dt->address = svm->vmcb->save.gdtr.base;
2469 }
2470
2471 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2472 {
2473         struct vcpu_svm *svm = to_svm(vcpu);
2474
2475         svm->vmcb->save.gdtr.limit = dt->size;
2476         svm->vmcb->save.gdtr.base = dt->address ;
2477         mark_dirty(svm->vmcb, VMCB_DT);
2478 }
2479
2480 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2481 {
2482 }
2483
2484 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2485 {
2486 }
2487
2488 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2489 {
2490 }
2491
2492 static void update_cr0_intercept(struct vcpu_svm *svm)
2493 {
2494         ulong gcr0 = svm->vcpu.arch.cr0;
2495         u64 *hcr0 = &svm->vmcb->save.cr0;
2496
2497         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2498                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2499
2500         mark_dirty(svm->vmcb, VMCB_CR);
2501
2502         if (gcr0 == *hcr0) {
2503                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2504                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2505         } else {
2506                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2507                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2508         }
2509 }
2510
2511 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2512 {
2513         struct vcpu_svm *svm = to_svm(vcpu);
2514
2515 #ifdef CONFIG_X86_64
2516         if (vcpu->arch.efer & EFER_LME) {
2517                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2518                         vcpu->arch.efer |= EFER_LMA;
2519                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2520                 }
2521
2522                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2523                         vcpu->arch.efer &= ~EFER_LMA;
2524                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2525                 }
2526         }
2527 #endif
2528         vcpu->arch.cr0 = cr0;
2529
2530         if (!npt_enabled)
2531                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2532
2533         /*
2534          * re-enable caching here because the QEMU bios
2535          * does not do it - this results in some delay at
2536          * reboot
2537          */
2538         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2539                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2540         svm->vmcb->save.cr0 = cr0;
2541         mark_dirty(svm->vmcb, VMCB_CR);
2542         update_cr0_intercept(svm);
2543 }
2544
2545 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2546 {
2547         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2548         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2549
2550         if (cr4 & X86_CR4_VMXE)
2551                 return 1;
2552
2553         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2554                 svm_flush_tlb(vcpu, true);
2555
2556         vcpu->arch.cr4 = cr4;
2557         if (!npt_enabled)
2558                 cr4 |= X86_CR4_PAE;
2559         cr4 |= host_cr4_mce;
2560         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2561         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2562         return 0;
2563 }
2564
2565 static void svm_set_segment(struct kvm_vcpu *vcpu,
2566                             struct kvm_segment *var, int seg)
2567 {
2568         struct vcpu_svm *svm = to_svm(vcpu);
2569         struct vmcb_seg *s = svm_seg(vcpu, seg);
2570
2571         s->base = var->base;
2572         s->limit = var->limit;
2573         s->selector = var->selector;
2574         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2575         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2576         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2577         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2578         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2579         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2580         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2581         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2582
2583         /*
2584          * This is always accurate, except if SYSRET returned to a segment
2585          * with SS.DPL != 3.  Intel does not have this quirk, and always
2586          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2587          * would entail passing the CPL to userspace and back.
2588          */
2589         if (seg == VCPU_SREG_SS)
2590                 /* This is symmetric with svm_get_segment() */
2591                 svm->vmcb->save.cpl = (var->dpl & 3);
2592
2593         mark_dirty(svm->vmcb, VMCB_SEG);
2594 }
2595
2596 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2597 {
2598         struct vcpu_svm *svm = to_svm(vcpu);
2599
2600         clr_exception_intercept(svm, BP_VECTOR);
2601
2602         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2603                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2604                         set_exception_intercept(svm, BP_VECTOR);
2605         } else
2606                 vcpu->guest_debug = 0;
2607 }
2608
2609 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2610 {
2611         if (sd->next_asid > sd->max_asid) {
2612                 ++sd->asid_generation;
2613                 sd->next_asid = sd->min_asid;
2614                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2615         }
2616
2617         svm->asid_generation = sd->asid_generation;
2618         svm->vmcb->control.asid = sd->next_asid++;
2619
2620         mark_dirty(svm->vmcb, VMCB_ASID);
2621 }
2622
2623 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2624 {
2625         return to_svm(vcpu)->vmcb->save.dr6;
2626 }
2627
2628 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2629 {
2630         struct vcpu_svm *svm = to_svm(vcpu);
2631
2632         svm->vmcb->save.dr6 = value;
2633         mark_dirty(svm->vmcb, VMCB_DR);
2634 }
2635
2636 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2637 {
2638         struct vcpu_svm *svm = to_svm(vcpu);
2639
2640         get_debugreg(vcpu->arch.db[0], 0);
2641         get_debugreg(vcpu->arch.db[1], 1);
2642         get_debugreg(vcpu->arch.db[2], 2);
2643         get_debugreg(vcpu->arch.db[3], 3);
2644         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2645         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2646
2647         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2648         set_dr_intercepts(svm);
2649 }
2650
2651 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2652 {
2653         struct vcpu_svm *svm = to_svm(vcpu);
2654
2655         svm->vmcb->save.dr7 = value;
2656         mark_dirty(svm->vmcb, VMCB_DR);
2657 }
2658
2659 static int pf_interception(struct vcpu_svm *svm)
2660 {
2661         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2662         u64 error_code = svm->vmcb->control.exit_info_1;
2663
2664         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2665                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2666                         svm->vmcb->control.insn_bytes : NULL,
2667                         svm->vmcb->control.insn_len);
2668 }
2669
2670 static int npf_interception(struct vcpu_svm *svm)
2671 {
2672         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2673         u64 error_code = svm->vmcb->control.exit_info_1;
2674
2675         trace_kvm_page_fault(fault_address, error_code);
2676         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2677                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2678                         svm->vmcb->control.insn_bytes : NULL,
2679                         svm->vmcb->control.insn_len);
2680 }
2681
2682 static int db_interception(struct vcpu_svm *svm)
2683 {
2684         struct kvm_run *kvm_run = svm->vcpu.run;
2685
2686         if (!(svm->vcpu.guest_debug &
2687               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2688                 !svm->nmi_singlestep) {
2689                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2690                 return 1;
2691         }
2692
2693         if (svm->nmi_singlestep) {
2694                 disable_nmi_singlestep(svm);
2695         }
2696
2697         if (svm->vcpu.guest_debug &
2698             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2699                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2700                 kvm_run->debug.arch.pc =
2701                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2702                 kvm_run->debug.arch.exception = DB_VECTOR;
2703                 return 0;
2704         }
2705
2706         return 1;
2707 }
2708
2709 static int bp_interception(struct vcpu_svm *svm)
2710 {
2711         struct kvm_run *kvm_run = svm->vcpu.run;
2712
2713         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2714         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2715         kvm_run->debug.arch.exception = BP_VECTOR;
2716         return 0;
2717 }
2718
2719 static int ud_interception(struct vcpu_svm *svm)
2720 {
2721         return handle_ud(&svm->vcpu);
2722 }
2723
2724 static int ac_interception(struct vcpu_svm *svm)
2725 {
2726         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2727         return 1;
2728 }
2729
2730 static int gp_interception(struct vcpu_svm *svm)
2731 {
2732         struct kvm_vcpu *vcpu = &svm->vcpu;
2733         u32 error_code = svm->vmcb->control.exit_info_1;
2734         int er;
2735
2736         WARN_ON_ONCE(!enable_vmware_backdoor);
2737
2738         er = kvm_emulate_instruction(vcpu,
2739                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2740         if (er == EMULATE_USER_EXIT)
2741                 return 0;
2742         else if (er != EMULATE_DONE)
2743                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2744         return 1;
2745 }
2746
2747 static bool is_erratum_383(void)
2748 {
2749         int err, i;
2750         u64 value;
2751
2752         if (!erratum_383_found)
2753                 return false;
2754
2755         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2756         if (err)
2757                 return false;
2758
2759         /* Bit 62 may or may not be set for this mce */
2760         value &= ~(1ULL << 62);
2761
2762         if (value != 0xb600000000010015ULL)
2763                 return false;
2764
2765         /* Clear MCi_STATUS registers */
2766         for (i = 0; i < 6; ++i)
2767                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2768
2769         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2770         if (!err) {
2771                 u32 low, high;
2772
2773                 value &= ~(1ULL << 2);
2774                 low    = lower_32_bits(value);
2775                 high   = upper_32_bits(value);
2776
2777                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2778         }
2779
2780         /* Flush tlb to evict multi-match entries */
2781         __flush_tlb_all();
2782
2783         return true;
2784 }
2785
2786 static void svm_handle_mce(struct vcpu_svm *svm)
2787 {
2788         if (is_erratum_383()) {
2789                 /*
2790                  * Erratum 383 triggered. Guest state is corrupt so kill the
2791                  * guest.
2792                  */
2793                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2794
2795                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2796
2797                 return;
2798         }
2799
2800         /*
2801          * On an #MC intercept the MCE handler is not called automatically in
2802          * the host. So do it by hand here.
2803          */
2804         asm volatile (
2805                 "int $0x12\n");
2806         /* not sure if we ever come back to this point */
2807
2808         return;
2809 }
2810
2811 static int mc_interception(struct vcpu_svm *svm)
2812 {
2813         return 1;
2814 }
2815
2816 static int shutdown_interception(struct vcpu_svm *svm)
2817 {
2818         struct kvm_run *kvm_run = svm->vcpu.run;
2819
2820         /*
2821          * VMCB is undefined after a SHUTDOWN intercept
2822          * so reinitialize it.
2823          */
2824         clear_page(svm->vmcb);
2825         init_vmcb(svm);
2826
2827         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2828         return 0;
2829 }
2830
2831 static int io_interception(struct vcpu_svm *svm)
2832 {
2833         struct kvm_vcpu *vcpu = &svm->vcpu;
2834         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2835         int size, in, string;
2836         unsigned port;
2837
2838         ++svm->vcpu.stat.io_exits;
2839         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2840         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2841         if (string)
2842                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2843
2844         port = io_info >> 16;
2845         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2846         svm->next_rip = svm->vmcb->control.exit_info_2;
2847
2848         return kvm_fast_pio(&svm->vcpu, size, port, in);
2849 }
2850
2851 static int nmi_interception(struct vcpu_svm *svm)
2852 {
2853         return 1;
2854 }
2855
2856 static int intr_interception(struct vcpu_svm *svm)
2857 {
2858         ++svm->vcpu.stat.irq_exits;
2859         return 1;
2860 }
2861
2862 static int nop_on_interception(struct vcpu_svm *svm)
2863 {
2864         return 1;
2865 }
2866
2867 static int halt_interception(struct vcpu_svm *svm)
2868 {
2869         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2870         return kvm_emulate_halt(&svm->vcpu);
2871 }
2872
2873 static int vmmcall_interception(struct vcpu_svm *svm)
2874 {
2875         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2876         return kvm_emulate_hypercall(&svm->vcpu);
2877 }
2878
2879 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2880 {
2881         struct vcpu_svm *svm = to_svm(vcpu);
2882
2883         return svm->nested.nested_cr3;
2884 }
2885
2886 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2887 {
2888         struct vcpu_svm *svm = to_svm(vcpu);
2889         u64 cr3 = svm->nested.nested_cr3;
2890         u64 pdpte;
2891         int ret;
2892
2893         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2894                                        offset_in_page(cr3) + index * 8, 8);
2895         if (ret)
2896                 return 0;
2897         return pdpte;
2898 }
2899
2900 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2901                                    unsigned long root)
2902 {
2903         struct vcpu_svm *svm = to_svm(vcpu);
2904
2905         svm->vmcb->control.nested_cr3 = __sme_set(root);
2906         mark_dirty(svm->vmcb, VMCB_NPT);
2907 }
2908
2909 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2910                                        struct x86_exception *fault)
2911 {
2912         struct vcpu_svm *svm = to_svm(vcpu);
2913
2914         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2915                 /*
2916                  * TODO: track the cause of the nested page fault, and
2917                  * correctly fill in the high bits of exit_info_1.
2918                  */
2919                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2920                 svm->vmcb->control.exit_code_hi = 0;
2921                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2922                 svm->vmcb->control.exit_info_2 = fault->address;
2923         }
2924
2925         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2926         svm->vmcb->control.exit_info_1 |= fault->error_code;
2927
2928         /*
2929          * The present bit is always zero for page structure faults on real
2930          * hardware.
2931          */
2932         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2933                 svm->vmcb->control.exit_info_1 &= ~1;
2934
2935         nested_svm_vmexit(svm);
2936 }
2937
2938 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2939 {
2940         WARN_ON(mmu_is_nested(vcpu));
2941         kvm_init_shadow_mmu(vcpu);
2942         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2943         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2944         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2945         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2946         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2947         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2948         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2949 }
2950
2951 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2952 {
2953         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2954 }
2955
2956 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2957 {
2958         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2959             !is_paging(&svm->vcpu)) {
2960                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2961                 return 1;
2962         }
2963
2964         if (svm->vmcb->save.cpl) {
2965                 kvm_inject_gp(&svm->vcpu, 0);
2966                 return 1;
2967         }
2968
2969         return 0;
2970 }
2971
2972 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2973                                       bool has_error_code, u32 error_code)
2974 {
2975         int vmexit;
2976
2977         if (!is_guest_mode(&svm->vcpu))
2978                 return 0;
2979
2980         vmexit = nested_svm_intercept(svm);
2981         if (vmexit != NESTED_EXIT_DONE)
2982                 return 0;
2983
2984         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2985         svm->vmcb->control.exit_code_hi = 0;
2986         svm->vmcb->control.exit_info_1 = error_code;
2987
2988         /*
2989          * EXITINFO2 is undefined for all exception intercepts other
2990          * than #PF.
2991          */
2992         if (svm->vcpu.arch.exception.nested_apf)
2993                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2994         else if (svm->vcpu.arch.exception.has_payload)
2995                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
2996         else
2997                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2998
2999         svm->nested.exit_required = true;
3000         return vmexit;
3001 }
3002
3003 /* This function returns true if it is save to enable the irq window */
3004 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3005 {
3006         if (!is_guest_mode(&svm->vcpu))
3007                 return true;
3008
3009         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3010                 return true;
3011
3012         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3013                 return false;
3014
3015         /*
3016          * if vmexit was already requested (by intercepted exception
3017          * for instance) do not overwrite it with "external interrupt"
3018          * vmexit.
3019          */
3020         if (svm->nested.exit_required)
3021                 return false;
3022
3023         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3024         svm->vmcb->control.exit_info_1 = 0;
3025         svm->vmcb->control.exit_info_2 = 0;
3026
3027         if (svm->nested.intercept & 1ULL) {
3028                 /*
3029                  * The #vmexit can't be emulated here directly because this
3030                  * code path runs with irqs and preemption disabled. A
3031                  * #vmexit emulation might sleep. Only signal request for
3032                  * the #vmexit here.
3033                  */
3034                 svm->nested.exit_required = true;
3035                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3036                 return false;
3037         }
3038
3039         return true;
3040 }
3041
3042 /* This function returns true if it is save to enable the nmi window */
3043 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3044 {
3045         if (!is_guest_mode(&svm->vcpu))
3046                 return true;
3047
3048         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3049                 return true;
3050
3051         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3052         svm->nested.exit_required = true;
3053
3054         return false;
3055 }
3056
3057 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3058 {
3059         struct page *page;
3060
3061         might_sleep();
3062
3063         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3064         if (is_error_page(page))
3065                 goto error;
3066
3067         *_page = page;
3068
3069         return kmap(page);
3070
3071 error:
3072         kvm_inject_gp(&svm->vcpu, 0);
3073
3074         return NULL;
3075 }
3076
3077 static void nested_svm_unmap(struct page *page)
3078 {
3079         kunmap(page);
3080         kvm_release_page_dirty(page);
3081 }
3082
3083 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3084 {
3085         unsigned port, size, iopm_len;
3086         u16 val, mask;
3087         u8 start_bit;
3088         u64 gpa;
3089
3090         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3091                 return NESTED_EXIT_HOST;
3092
3093         port = svm->vmcb->control.exit_info_1 >> 16;
3094         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3095                 SVM_IOIO_SIZE_SHIFT;
3096         gpa  = svm->nested.vmcb_iopm + (port / 8);
3097         start_bit = port % 8;
3098         iopm_len = (start_bit + size > 8) ? 2 : 1;
3099         mask = (0xf >> (4 - size)) << start_bit;
3100         val = 0;
3101
3102         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3103                 return NESTED_EXIT_DONE;
3104
3105         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3106 }
3107
3108 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3109 {
3110         u32 offset, msr, value;
3111         int write, mask;
3112
3113         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3114                 return NESTED_EXIT_HOST;
3115
3116         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3117         offset = svm_msrpm_offset(msr);
3118         write  = svm->vmcb->control.exit_info_1 & 1;
3119         mask   = 1 << ((2 * (msr & 0xf)) + write);
3120
3121         if (offset == MSR_INVALID)
3122                 return NESTED_EXIT_DONE;
3123
3124         /* Offset is in 32 bit units but need in 8 bit units */
3125         offset *= 4;
3126
3127         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3128                 return NESTED_EXIT_DONE;
3129
3130         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3131 }
3132
3133 /* DB exceptions for our internal use must not cause vmexit */
3134 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3135 {
3136         unsigned long dr6;
3137
3138         /* if we're not singlestepping, it's not ours */
3139         if (!svm->nmi_singlestep)
3140                 return NESTED_EXIT_DONE;
3141
3142         /* if it's not a singlestep exception, it's not ours */
3143         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3144                 return NESTED_EXIT_DONE;
3145         if (!(dr6 & DR6_BS))
3146                 return NESTED_EXIT_DONE;
3147
3148         /* if the guest is singlestepping, it should get the vmexit */
3149         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3150                 disable_nmi_singlestep(svm);
3151                 return NESTED_EXIT_DONE;
3152         }
3153
3154         /* it's ours, the nested hypervisor must not see this one */
3155         return NESTED_EXIT_HOST;
3156 }
3157
3158 static int nested_svm_exit_special(struct vcpu_svm *svm)
3159 {
3160         u32 exit_code = svm->vmcb->control.exit_code;
3161
3162         switch (exit_code) {
3163         case SVM_EXIT_INTR:
3164         case SVM_EXIT_NMI:
3165         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3166                 return NESTED_EXIT_HOST;
3167         case SVM_EXIT_NPF:
3168                 /* For now we are always handling NPFs when using them */
3169                 if (npt_enabled)
3170                         return NESTED_EXIT_HOST;
3171                 break;
3172         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3173                 /* When we're shadowing, trap PFs, but not async PF */
3174                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3175                         return NESTED_EXIT_HOST;
3176                 break;
3177         default:
3178                 break;
3179         }
3180
3181         return NESTED_EXIT_CONTINUE;
3182 }
3183
3184 /*
3185  * If this function returns true, this #vmexit was already handled
3186  */
3187 static int nested_svm_intercept(struct vcpu_svm *svm)
3188 {
3189         u32 exit_code = svm->vmcb->control.exit_code;
3190         int vmexit = NESTED_EXIT_HOST;
3191
3192         switch (exit_code) {
3193         case SVM_EXIT_MSR:
3194                 vmexit = nested_svm_exit_handled_msr(svm);
3195                 break;
3196         case SVM_EXIT_IOIO:
3197                 vmexit = nested_svm_intercept_ioio(svm);
3198                 break;
3199         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3200                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3201                 if (svm->nested.intercept_cr & bit)
3202                         vmexit = NESTED_EXIT_DONE;
3203                 break;
3204         }
3205         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3206                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3207                 if (svm->nested.intercept_dr & bit)
3208                         vmexit = NESTED_EXIT_DONE;
3209                 break;
3210         }
3211         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3212                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3213                 if (svm->nested.intercept_exceptions & excp_bits) {
3214                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3215                                 vmexit = nested_svm_intercept_db(svm);
3216                         else
3217                                 vmexit = NESTED_EXIT_DONE;
3218                 }
3219                 /* async page fault always cause vmexit */
3220                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3221                          svm->vcpu.arch.exception.nested_apf != 0)
3222                         vmexit = NESTED_EXIT_DONE;
3223                 break;
3224         }
3225         case SVM_EXIT_ERR: {
3226                 vmexit = NESTED_EXIT_DONE;
3227                 break;
3228         }
3229         default: {
3230                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3231                 if (svm->nested.intercept & exit_bits)
3232                         vmexit = NESTED_EXIT_DONE;
3233         }
3234         }
3235
3236         return vmexit;
3237 }
3238
3239 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3240 {
3241         int vmexit;
3242
3243         vmexit = nested_svm_intercept(svm);
3244
3245         if (vmexit == NESTED_EXIT_DONE)
3246                 nested_svm_vmexit(svm);
3247
3248         return vmexit;
3249 }
3250
3251 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3252 {
3253         struct vmcb_control_area *dst  = &dst_vmcb->control;
3254         struct vmcb_control_area *from = &from_vmcb->control;
3255
3256         dst->intercept_cr         = from->intercept_cr;
3257         dst->intercept_dr         = from->intercept_dr;
3258         dst->intercept_exceptions = from->intercept_exceptions;
3259         dst->intercept            = from->intercept;
3260         dst->iopm_base_pa         = from->iopm_base_pa;
3261         dst->msrpm_base_pa        = from->msrpm_base_pa;
3262         dst->tsc_offset           = from->tsc_offset;
3263         dst->asid                 = from->asid;
3264         dst->tlb_ctl              = from->tlb_ctl;
3265         dst->int_ctl              = from->int_ctl;
3266         dst->int_vector           = from->int_vector;
3267         dst->int_state            = from->int_state;
3268         dst->exit_code            = from->exit_code;
3269         dst->exit_code_hi         = from->exit_code_hi;
3270         dst->exit_info_1          = from->exit_info_1;
3271         dst->exit_info_2          = from->exit_info_2;
3272         dst->exit_int_info        = from->exit_int_info;
3273         dst->exit_int_info_err    = from->exit_int_info_err;
3274         dst->nested_ctl           = from->nested_ctl;
3275         dst->event_inj            = from->event_inj;
3276         dst->event_inj_err        = from->event_inj_err;
3277         dst->nested_cr3           = from->nested_cr3;
3278         dst->virt_ext              = from->virt_ext;
3279 }
3280
3281 static int nested_svm_vmexit(struct vcpu_svm *svm)
3282 {
3283         struct vmcb *nested_vmcb;
3284         struct vmcb *hsave = svm->nested.hsave;
3285         struct vmcb *vmcb = svm->vmcb;
3286         struct page *page;
3287
3288         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3289                                        vmcb->control.exit_info_1,
3290                                        vmcb->control.exit_info_2,
3291                                        vmcb->control.exit_int_info,
3292                                        vmcb->control.exit_int_info_err,
3293                                        KVM_ISA_SVM);
3294
3295         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3296         if (!nested_vmcb)
3297                 return 1;
3298
3299         /* Exit Guest-Mode */
3300         leave_guest_mode(&svm->vcpu);
3301         svm->nested.vmcb = 0;
3302
3303         /* Give the current vmcb to the guest */
3304         disable_gif(svm);
3305
3306         nested_vmcb->save.es     = vmcb->save.es;
3307         nested_vmcb->save.cs     = vmcb->save.cs;
3308         nested_vmcb->save.ss     = vmcb->save.ss;
3309         nested_vmcb->save.ds     = vmcb->save.ds;
3310         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3311         nested_vmcb->save.idtr   = vmcb->save.idtr;
3312         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3313         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3314         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3315         nested_vmcb->save.cr2    = vmcb->save.cr2;
3316         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3317         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3318         nested_vmcb->save.rip    = vmcb->save.rip;
3319         nested_vmcb->save.rsp    = vmcb->save.rsp;
3320         nested_vmcb->save.rax    = vmcb->save.rax;
3321         nested_vmcb->save.dr7    = vmcb->save.dr7;
3322         nested_vmcb->save.dr6    = vmcb->save.dr6;
3323         nested_vmcb->save.cpl    = vmcb->save.cpl;
3324
3325         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3326         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3327         nested_vmcb->control.int_state         = vmcb->control.int_state;
3328         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3329         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3330         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3331         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3332         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3333         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3334
3335         if (svm->nrips_enabled)
3336                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3337
3338         /*
3339          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3340          * to make sure that we do not lose injected events. So check event_inj
3341          * here and copy it to exit_int_info if it is valid.
3342          * Exit_int_info and event_inj can't be both valid because the case
3343          * below only happens on a VMRUN instruction intercept which has
3344          * no valid exit_int_info set.
3345          */
3346         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3347                 struct vmcb_control_area *nc = &nested_vmcb->control;
3348
3349                 nc->exit_int_info     = vmcb->control.event_inj;
3350                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3351         }
3352
3353         nested_vmcb->control.tlb_ctl           = 0;
3354         nested_vmcb->control.event_inj         = 0;
3355         nested_vmcb->control.event_inj_err     = 0;
3356
3357         /* We always set V_INTR_MASKING and remember the old value in hflags */
3358         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3359                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3360
3361         /* Restore the original control entries */
3362         copy_vmcb_control_area(vmcb, hsave);
3363
3364         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3365         kvm_clear_exception_queue(&svm->vcpu);
3366         kvm_clear_interrupt_queue(&svm->vcpu);
3367
3368         svm->nested.nested_cr3 = 0;
3369
3370         /* Restore selected save entries */
3371         svm->vmcb->save.es = hsave->save.es;
3372         svm->vmcb->save.cs = hsave->save.cs;
3373         svm->vmcb->save.ss = hsave->save.ss;
3374         svm->vmcb->save.ds = hsave->save.ds;
3375         svm->vmcb->save.gdtr = hsave->save.gdtr;
3376         svm->vmcb->save.idtr = hsave->save.idtr;
3377         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3378         svm_set_efer(&svm->vcpu, hsave->save.efer);
3379         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3380         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3381         if (npt_enabled) {
3382                 svm->vmcb->save.cr3 = hsave->save.cr3;
3383                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3384         } else {
3385                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3386         }
3387         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3388         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3389         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3390         svm->vmcb->save.dr7 = 0;
3391         svm->vmcb->save.cpl = 0;
3392         svm->vmcb->control.exit_int_info = 0;
3393
3394         mark_all_dirty(svm->vmcb);
3395
3396         nested_svm_unmap(page);
3397
3398         nested_svm_uninit_mmu_context(&svm->vcpu);
3399         kvm_mmu_reset_context(&svm->vcpu);
3400         kvm_mmu_load(&svm->vcpu);
3401
3402         return 0;
3403 }
3404
3405 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3406 {
3407         /*
3408          * This function merges the msr permission bitmaps of kvm and the
3409          * nested vmcb. It is optimized in that it only merges the parts where
3410          * the kvm msr permission bitmap may contain zero bits
3411          */
3412         int i;
3413
3414         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3415                 return true;
3416
3417         for (i = 0; i < MSRPM_OFFSETS; i++) {
3418                 u32 value, p;
3419                 u64 offset;
3420
3421                 if (msrpm_offsets[i] == 0xffffffff)
3422                         break;
3423
3424                 p      = msrpm_offsets[i];
3425                 offset = svm->nested.vmcb_msrpm + (p * 4);
3426
3427                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3428                         return false;
3429
3430                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3431         }
3432
3433         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3434
3435         return true;
3436 }
3437
3438 static bool nested_vmcb_checks(struct vmcb *vmcb)
3439 {
3440         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3441                 return false;
3442
3443         if (vmcb->control.asid == 0)
3444                 return false;
3445
3446         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3447             !npt_enabled)
3448                 return false;
3449
3450         return true;
3451 }
3452
3453 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3454                                  struct vmcb *nested_vmcb, struct page *page)
3455 {
3456         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3457                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3458         else
3459                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3460
3461         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3462                 kvm_mmu_unload(&svm->vcpu);
3463                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3464                 nested_svm_init_mmu_context(&svm->vcpu);
3465         }
3466
3467         /* Load the nested guest state */
3468         svm->vmcb->save.es = nested_vmcb->save.es;
3469         svm->vmcb->save.cs = nested_vmcb->save.cs;
3470         svm->vmcb->save.ss = nested_vmcb->save.ss;
3471         svm->vmcb->save.ds = nested_vmcb->save.ds;
3472         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3473         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3474         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3475         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3476         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3477         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3478         if (npt_enabled) {
3479                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3480                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3481         } else
3482                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3483
3484         /* Guest paging mode is active - reset mmu */
3485         kvm_mmu_reset_context(&svm->vcpu);
3486
3487         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3488         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3489         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3490         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3491
3492         /* In case we don't even reach vcpu_run, the fields are not updated */
3493         svm->vmcb->save.rax = nested_vmcb->save.rax;
3494         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3495         svm->vmcb->save.rip = nested_vmcb->save.rip;
3496         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3497         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3498         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3499
3500         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3501         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3502
3503         /* cache intercepts */
3504         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3505         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3506         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3507         svm->nested.intercept            = nested_vmcb->control.intercept;
3508
3509         svm_flush_tlb(&svm->vcpu, true);
3510         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3511         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3512                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3513         else
3514                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3515
3516         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3517                 /* We only want the cr8 intercept bits of the guest */
3518                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3519                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3520         }
3521
3522         /* We don't want to see VMMCALLs from a nested guest */
3523         clr_intercept(svm, INTERCEPT_VMMCALL);
3524
3525         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3526         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3527
3528         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3529         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3530         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3531         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3532         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3533
3534         nested_svm_unmap(page);
3535
3536         /* Enter Guest-Mode */
3537         enter_guest_mode(&svm->vcpu);
3538
3539         /*
3540          * Merge guest and host intercepts - must be called  with vcpu in
3541          * guest-mode to take affect here
3542          */
3543         recalc_intercepts(svm);
3544
3545         svm->nested.vmcb = vmcb_gpa;
3546
3547         enable_gif(svm);
3548
3549         mark_all_dirty(svm->vmcb);
3550 }
3551
3552 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3553 {
3554         struct vmcb *nested_vmcb;
3555         struct vmcb *hsave = svm->nested.hsave;
3556         struct vmcb *vmcb = svm->vmcb;
3557         struct page *page;
3558         u64 vmcb_gpa;
3559
3560         vmcb_gpa = svm->vmcb->save.rax;
3561
3562         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3563         if (!nested_vmcb)
3564                 return false;
3565
3566         if (!nested_vmcb_checks(nested_vmcb)) {
3567                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3568                 nested_vmcb->control.exit_code_hi = 0;
3569                 nested_vmcb->control.exit_info_1  = 0;
3570                 nested_vmcb->control.exit_info_2  = 0;
3571
3572                 nested_svm_unmap(page);
3573
3574                 return false;
3575         }
3576
3577         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3578                                nested_vmcb->save.rip,
3579                                nested_vmcb->control.int_ctl,
3580                                nested_vmcb->control.event_inj,
3581                                nested_vmcb->control.nested_ctl);
3582
3583         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3584                                     nested_vmcb->control.intercept_cr >> 16,
3585                                     nested_vmcb->control.intercept_exceptions,
3586                                     nested_vmcb->control.intercept);
3587
3588         /* Clear internal status */
3589         kvm_clear_exception_queue(&svm->vcpu);
3590         kvm_clear_interrupt_queue(&svm->vcpu);
3591
3592         /*
3593          * Save the old vmcb, so we don't need to pick what we save, but can
3594          * restore everything when a VMEXIT occurs
3595          */
3596         hsave->save.es     = vmcb->save.es;
3597         hsave->save.cs     = vmcb->save.cs;
3598         hsave->save.ss     = vmcb->save.ss;
3599         hsave->save.ds     = vmcb->save.ds;
3600         hsave->save.gdtr   = vmcb->save.gdtr;
3601         hsave->save.idtr   = vmcb->save.idtr;
3602         hsave->save.efer   = svm->vcpu.arch.efer;
3603         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3604         hsave->save.cr4    = svm->vcpu.arch.cr4;
3605         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3606         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3607         hsave->save.rsp    = vmcb->save.rsp;
3608         hsave->save.rax    = vmcb->save.rax;
3609         if (npt_enabled)
3610                 hsave->save.cr3    = vmcb->save.cr3;
3611         else
3612                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3613
3614         copy_vmcb_control_area(hsave, vmcb);
3615
3616         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3617
3618         return true;
3619 }
3620
3621 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3622 {
3623         to_vmcb->save.fs = from_vmcb->save.fs;
3624         to_vmcb->save.gs = from_vmcb->save.gs;
3625         to_vmcb->save.tr = from_vmcb->save.tr;
3626         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3627         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3628         to_vmcb->save.star = from_vmcb->save.star;
3629         to_vmcb->save.lstar = from_vmcb->save.lstar;
3630         to_vmcb->save.cstar = from_vmcb->save.cstar;
3631         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3632         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3633         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3634         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3635 }
3636
3637 static int vmload_interception(struct vcpu_svm *svm)
3638 {
3639         struct vmcb *nested_vmcb;
3640         struct page *page;
3641         int ret;
3642
3643         if (nested_svm_check_permissions(svm))
3644                 return 1;
3645
3646         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3647         if (!nested_vmcb)
3648                 return 1;
3649
3650         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3651         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3652
3653         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3654         nested_svm_unmap(page);
3655
3656         return ret;
3657 }
3658
3659 static int vmsave_interception(struct vcpu_svm *svm)
3660 {
3661         struct vmcb *nested_vmcb;
3662         struct page *page;
3663         int ret;
3664
3665         if (nested_svm_check_permissions(svm))
3666                 return 1;
3667
3668         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3669         if (!nested_vmcb)
3670                 return 1;
3671
3672         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3673         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3674
3675         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3676         nested_svm_unmap(page);
3677
3678         return ret;
3679 }
3680
3681 static int vmrun_interception(struct vcpu_svm *svm)
3682 {
3683         if (nested_svm_check_permissions(svm))
3684                 return 1;
3685
3686         /* Save rip after vmrun instruction */
3687         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3688
3689         if (!nested_svm_vmrun(svm))
3690                 return 1;
3691
3692         if (!nested_svm_vmrun_msrpm(svm))
3693                 goto failed;
3694
3695         return 1;
3696
3697 failed:
3698
3699         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3700         svm->vmcb->control.exit_code_hi = 0;
3701         svm->vmcb->control.exit_info_1  = 0;
3702         svm->vmcb->control.exit_info_2  = 0;
3703
3704         nested_svm_vmexit(svm);
3705
3706         return 1;
3707 }
3708
3709 static int stgi_interception(struct vcpu_svm *svm)
3710 {
3711         int ret;
3712
3713         if (nested_svm_check_permissions(svm))
3714                 return 1;
3715
3716         /*
3717          * If VGIF is enabled, the STGI intercept is only added to
3718          * detect the opening of the SMI/NMI window; remove it now.
3719          */
3720         if (vgif_enabled(svm))
3721                 clr_intercept(svm, INTERCEPT_STGI);
3722
3723         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3724         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3725         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3726
3727         enable_gif(svm);
3728
3729         return ret;
3730 }
3731
3732 static int clgi_interception(struct vcpu_svm *svm)
3733 {
3734         int ret;
3735
3736         if (nested_svm_check_permissions(svm))
3737                 return 1;
3738
3739         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3740         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3741
3742         disable_gif(svm);
3743
3744         /* After a CLGI no interrupts should come */
3745         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3746                 svm_clear_vintr(svm);
3747                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3748                 mark_dirty(svm->vmcb, VMCB_INTR);
3749         }
3750
3751         return ret;
3752 }
3753
3754 static int invlpga_interception(struct vcpu_svm *svm)
3755 {
3756         struct kvm_vcpu *vcpu = &svm->vcpu;
3757
3758         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3759                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3760
3761         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3762         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3763
3764         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3765         return kvm_skip_emulated_instruction(&svm->vcpu);
3766 }
3767
3768 static int skinit_interception(struct vcpu_svm *svm)
3769 {
3770         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3771
3772         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3773         return 1;
3774 }
3775
3776 static int wbinvd_interception(struct vcpu_svm *svm)
3777 {
3778         return kvm_emulate_wbinvd(&svm->vcpu);
3779 }
3780
3781 static int xsetbv_interception(struct vcpu_svm *svm)
3782 {
3783         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3784         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3785
3786         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3787                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3788                 return kvm_skip_emulated_instruction(&svm->vcpu);
3789         }
3790
3791         return 1;
3792 }
3793
3794 static int task_switch_interception(struct vcpu_svm *svm)
3795 {
3796         u16 tss_selector;
3797         int reason;
3798         int int_type = svm->vmcb->control.exit_int_info &
3799                 SVM_EXITINTINFO_TYPE_MASK;
3800         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3801         uint32_t type =
3802                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3803         uint32_t idt_v =
3804                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3805         bool has_error_code = false;
3806         u32 error_code = 0;
3807
3808         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3809
3810         if (svm->vmcb->control.exit_info_2 &
3811             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3812                 reason = TASK_SWITCH_IRET;
3813         else if (svm->vmcb->control.exit_info_2 &
3814                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3815                 reason = TASK_SWITCH_JMP;
3816         else if (idt_v)
3817                 reason = TASK_SWITCH_GATE;
3818         else
3819                 reason = TASK_SWITCH_CALL;
3820
3821         if (reason == TASK_SWITCH_GATE) {
3822                 switch (type) {
3823                 case SVM_EXITINTINFO_TYPE_NMI:
3824                         svm->vcpu.arch.nmi_injected = false;
3825                         break;
3826                 case SVM_EXITINTINFO_TYPE_EXEPT:
3827                         if (svm->vmcb->control.exit_info_2 &
3828                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3829                                 has_error_code = true;
3830                                 error_code =
3831                                         (u32)svm->vmcb->control.exit_info_2;
3832                         }
3833                         kvm_clear_exception_queue(&svm->vcpu);
3834                         break;
3835                 case SVM_EXITINTINFO_TYPE_INTR:
3836                         kvm_clear_interrupt_queue(&svm->vcpu);
3837                         break;
3838                 default:
3839                         break;
3840                 }
3841         }
3842
3843         if (reason != TASK_SWITCH_GATE ||
3844             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3845             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3846              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3847                 skip_emulated_instruction(&svm->vcpu);
3848
3849         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3850                 int_vec = -1;
3851
3852         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3853                                 has_error_code, error_code) == EMULATE_FAIL) {
3854                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3855                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3856                 svm->vcpu.run->internal.ndata = 0;
3857                 return 0;
3858         }
3859         return 1;
3860 }
3861
3862 static int cpuid_interception(struct vcpu_svm *svm)
3863 {
3864         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3865         return kvm_emulate_cpuid(&svm->vcpu);
3866 }
3867
3868 static int iret_interception(struct vcpu_svm *svm)
3869 {
3870         ++svm->vcpu.stat.nmi_window_exits;
3871         clr_intercept(svm, INTERCEPT_IRET);
3872         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3873         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3874         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3875         return 1;
3876 }
3877
3878 static int invlpg_interception(struct vcpu_svm *svm)
3879 {
3880         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3881                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3882
3883         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3884         return kvm_skip_emulated_instruction(&svm->vcpu);
3885 }
3886
3887 static int emulate_on_interception(struct vcpu_svm *svm)
3888 {
3889         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3890 }
3891
3892 static int rsm_interception(struct vcpu_svm *svm)
3893 {
3894         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3895                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3896 }
3897
3898 static int rdpmc_interception(struct vcpu_svm *svm)
3899 {
3900         int err;
3901
3902         if (!static_cpu_has(X86_FEATURE_NRIPS))
3903                 return emulate_on_interception(svm);
3904
3905         err = kvm_rdpmc(&svm->vcpu);
3906         return kvm_complete_insn_gp(&svm->vcpu, err);
3907 }
3908
3909 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3910                                             unsigned long val)
3911 {
3912         unsigned long cr0 = svm->vcpu.arch.cr0;
3913         bool ret = false;
3914         u64 intercept;
3915
3916         intercept = svm->nested.intercept;
3917
3918         if (!is_guest_mode(&svm->vcpu) ||
3919             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3920                 return false;
3921
3922         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3923         val &= ~SVM_CR0_SELECTIVE_MASK;
3924
3925         if (cr0 ^ val) {
3926                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3927                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3928         }
3929
3930         return ret;
3931 }
3932
3933 #define CR_VALID (1ULL << 63)
3934
3935 static int cr_interception(struct vcpu_svm *svm)
3936 {
3937         int reg, cr;
3938         unsigned long val;
3939         int err;
3940
3941         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3942                 return emulate_on_interception(svm);
3943
3944         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3945                 return emulate_on_interception(svm);
3946
3947         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3948         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3949                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3950         else
3951                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3952
3953         err = 0;
3954         if (cr >= 16) { /* mov to cr */
3955                 cr -= 16;
3956                 val = kvm_register_read(&svm->vcpu, reg);
3957                 switch (cr) {
3958                 case 0:
3959                         if (!check_selective_cr0_intercepted(svm, val))
3960                                 err = kvm_set_cr0(&svm->vcpu, val);
3961                         else
3962                                 return 1;
3963
3964                         break;
3965                 case 3:
3966                         err = kvm_set_cr3(&svm->vcpu, val);
3967                         break;
3968                 case 4:
3969                         err = kvm_set_cr4(&svm->vcpu, val);
3970                         break;
3971                 case 8:
3972                         err = kvm_set_cr8(&svm->vcpu, val);
3973                         break;
3974                 default:
3975                         WARN(1, "unhandled write to CR%d", cr);
3976                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3977                         return 1;
3978                 }
3979         } else { /* mov from cr */
3980                 switch (cr) {
3981                 case 0:
3982                         val = kvm_read_cr0(&svm->vcpu);
3983                         break;
3984                 case 2:
3985                         val = svm->vcpu.arch.cr2;
3986                         break;
3987                 case 3:
3988                         val = kvm_read_cr3(&svm->vcpu);
3989                         break;
3990                 case 4:
3991                         val = kvm_read_cr4(&svm->vcpu);
3992                         break;
3993                 case 8:
3994                         val = kvm_get_cr8(&svm->vcpu);
3995                         break;
3996                 default:
3997                         WARN(1, "unhandled read from CR%d", cr);
3998                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3999                         return 1;
4000                 }
4001                 kvm_register_write(&svm->vcpu, reg, val);
4002         }
4003         return kvm_complete_insn_gp(&svm->vcpu, err);
4004 }
4005
4006 static int dr_interception(struct vcpu_svm *svm)
4007 {
4008         int reg, dr;
4009         unsigned long val;
4010
4011         if (svm->vcpu.guest_debug == 0) {
4012                 /*
4013                  * No more DR vmexits; force a reload of the debug registers
4014                  * and reenter on this instruction.  The next vmexit will
4015                  * retrieve the full state of the debug registers.
4016                  */
4017                 clr_dr_intercepts(svm);
4018                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4019                 return 1;
4020         }
4021
4022         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4023                 return emulate_on_interception(svm);
4024
4025         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4026         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4027
4028         if (dr >= 16) { /* mov to DRn */
4029                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4030                         return 1;
4031                 val = kvm_register_read(&svm->vcpu, reg);
4032                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4033         } else {
4034                 if (!kvm_require_dr(&svm->vcpu, dr))
4035                         return 1;
4036                 kvm_get_dr(&svm->vcpu, dr, &val);
4037                 kvm_register_write(&svm->vcpu, reg, val);
4038         }
4039
4040         return kvm_skip_emulated_instruction(&svm->vcpu);
4041 }
4042
4043 static int cr8_write_interception(struct vcpu_svm *svm)
4044 {
4045         struct kvm_run *kvm_run = svm->vcpu.run;
4046         int r;
4047
4048         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4049         /* instruction emulation calls kvm_set_cr8() */
4050         r = cr_interception(svm);
4051         if (lapic_in_kernel(&svm->vcpu))
4052                 return r;
4053         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4054                 return r;
4055         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4056         return 0;
4057 }
4058
4059 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4060 {
4061         msr->data = 0;
4062
4063         switch (msr->index) {
4064         case MSR_F10H_DECFG:
4065                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4066                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4067                 break;
4068         default:
4069                 return 1;
4070         }
4071
4072         return 0;
4073 }
4074
4075 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4076 {
4077         struct vcpu_svm *svm = to_svm(vcpu);
4078
4079         switch (msr_info->index) {
4080         case MSR_STAR:
4081                 msr_info->data = svm->vmcb->save.star;
4082                 break;
4083 #ifdef CONFIG_X86_64
4084         case MSR_LSTAR:
4085                 msr_info->data = svm->vmcb->save.lstar;
4086                 break;
4087         case MSR_CSTAR:
4088                 msr_info->data = svm->vmcb->save.cstar;
4089                 break;
4090         case MSR_KERNEL_GS_BASE:
4091                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4092                 break;
4093         case MSR_SYSCALL_MASK:
4094                 msr_info->data = svm->vmcb->save.sfmask;
4095                 break;
4096 #endif
4097         case MSR_IA32_SYSENTER_CS:
4098                 msr_info->data = svm->vmcb->save.sysenter_cs;
4099                 break;
4100         case MSR_IA32_SYSENTER_EIP:
4101                 msr_info->data = svm->sysenter_eip;
4102                 break;
4103         case MSR_IA32_SYSENTER_ESP:
4104                 msr_info->data = svm->sysenter_esp;
4105                 break;
4106         case MSR_TSC_AUX:
4107                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4108                         return 1;
4109                 msr_info->data = svm->tsc_aux;
4110                 break;
4111         /*
4112          * Nobody will change the following 5 values in the VMCB so we can
4113          * safely return them on rdmsr. They will always be 0 until LBRV is
4114          * implemented.
4115          */
4116         case MSR_IA32_DEBUGCTLMSR:
4117                 msr_info->data = svm->vmcb->save.dbgctl;
4118                 break;
4119         case MSR_IA32_LASTBRANCHFROMIP:
4120                 msr_info->data = svm->vmcb->save.br_from;
4121                 break;
4122         case MSR_IA32_LASTBRANCHTOIP:
4123                 msr_info->data = svm->vmcb->save.br_to;
4124                 break;
4125         case MSR_IA32_LASTINTFROMIP:
4126                 msr_info->data = svm->vmcb->save.last_excp_from;
4127                 break;
4128         case MSR_IA32_LASTINTTOIP:
4129                 msr_info->data = svm->vmcb->save.last_excp_to;
4130                 break;
4131         case MSR_VM_HSAVE_PA:
4132                 msr_info->data = svm->nested.hsave_msr;
4133                 break;
4134         case MSR_VM_CR:
4135                 msr_info->data = svm->nested.vm_cr_msr;
4136                 break;
4137         case MSR_IA32_SPEC_CTRL:
4138                 if (!msr_info->host_initiated &&
4139                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4140                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4141                         return 1;
4142
4143                 msr_info->data = svm->spec_ctrl;
4144                 break;
4145         case MSR_AMD64_VIRT_SPEC_CTRL:
4146                 if (!msr_info->host_initiated &&
4147                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4148                         return 1;
4149
4150                 msr_info->data = svm->virt_spec_ctrl;
4151                 break;
4152         case MSR_F15H_IC_CFG: {
4153
4154                 int family, model;
4155
4156                 family = guest_cpuid_family(vcpu);
4157                 model  = guest_cpuid_model(vcpu);
4158
4159                 if (family < 0 || model < 0)
4160                         return kvm_get_msr_common(vcpu, msr_info);
4161
4162                 msr_info->data = 0;
4163
4164                 if (family == 0x15 &&
4165                     (model >= 0x2 && model < 0x20))
4166                         msr_info->data = 0x1E;
4167                 }
4168                 break;
4169         case MSR_F10H_DECFG:
4170                 msr_info->data = svm->msr_decfg;
4171                 break;
4172         default:
4173                 return kvm_get_msr_common(vcpu, msr_info);
4174         }
4175         return 0;
4176 }
4177
4178 static int rdmsr_interception(struct vcpu_svm *svm)
4179 {
4180         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4181         struct msr_data msr_info;
4182
4183         msr_info.index = ecx;
4184         msr_info.host_initiated = false;
4185         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4186                 trace_kvm_msr_read_ex(ecx);
4187                 kvm_inject_gp(&svm->vcpu, 0);
4188                 return 1;
4189         } else {
4190                 trace_kvm_msr_read(ecx, msr_info.data);
4191
4192                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4193                                    msr_info.data & 0xffffffff);
4194                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4195                                    msr_info.data >> 32);
4196                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4197                 return kvm_skip_emulated_instruction(&svm->vcpu);
4198         }
4199 }
4200
4201 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4202 {
4203         struct vcpu_svm *svm = to_svm(vcpu);
4204         int svm_dis, chg_mask;
4205
4206         if (data & ~SVM_VM_CR_VALID_MASK)
4207                 return 1;
4208
4209         chg_mask = SVM_VM_CR_VALID_MASK;
4210
4211         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4212                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4213
4214         svm->nested.vm_cr_msr &= ~chg_mask;
4215         svm->nested.vm_cr_msr |= (data & chg_mask);
4216
4217         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4218
4219         /* check for svm_disable while efer.svme is set */
4220         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4221                 return 1;
4222
4223         return 0;
4224 }
4225
4226 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4227 {
4228         struct vcpu_svm *svm = to_svm(vcpu);
4229
4230         u32 ecx = msr->index;
4231         u64 data = msr->data;
4232         switch (ecx) {
4233         case MSR_IA32_CR_PAT:
4234                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4235                         return 1;
4236                 vcpu->arch.pat = data;
4237                 svm->vmcb->save.g_pat = data;
4238                 mark_dirty(svm->vmcb, VMCB_NPT);
4239                 break;
4240         case MSR_IA32_SPEC_CTRL:
4241                 if (!msr->host_initiated &&
4242                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4243                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4244                         return 1;
4245
4246                 /* The STIBP bit doesn't fault even if it's not advertised */
4247                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4248                         return 1;
4249
4250                 svm->spec_ctrl = data;
4251
4252                 if (!data)
4253                         break;
4254
4255                 /*
4256                  * For non-nested:
4257                  * When it's written (to non-zero) for the first time, pass
4258                  * it through.
4259                  *
4260                  * For nested:
4261                  * The handling of the MSR bitmap for L2 guests is done in
4262                  * nested_svm_vmrun_msrpm.
4263                  * We update the L1 MSR bit as well since it will end up
4264                  * touching the MSR anyway now.
4265                  */
4266                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4267                 break;
4268         case MSR_IA32_PRED_CMD:
4269                 if (!msr->host_initiated &&
4270                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4271                         return 1;
4272
4273                 if (data & ~PRED_CMD_IBPB)
4274                         return 1;
4275
4276                 if (!data)
4277                         break;
4278
4279                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4280                 if (is_guest_mode(vcpu))
4281                         break;
4282                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4283                 break;
4284         case MSR_AMD64_VIRT_SPEC_CTRL:
4285                 if (!msr->host_initiated &&
4286                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4287                         return 1;
4288
4289                 if (data & ~SPEC_CTRL_SSBD)
4290                         return 1;
4291
4292                 svm->virt_spec_ctrl = data;
4293                 break;
4294         case MSR_STAR:
4295                 svm->vmcb->save.star = data;
4296                 break;
4297 #ifdef CONFIG_X86_64
4298         case MSR_LSTAR:
4299                 svm->vmcb->save.lstar = data;
4300                 break;
4301         case MSR_CSTAR:
4302                 svm->vmcb->save.cstar = data;
4303                 break;
4304         case MSR_KERNEL_GS_BASE:
4305                 svm->vmcb->save.kernel_gs_base = data;
4306                 break;
4307         case MSR_SYSCALL_MASK:
4308                 svm->vmcb->save.sfmask = data;
4309                 break;
4310 #endif
4311         case MSR_IA32_SYSENTER_CS:
4312                 svm->vmcb->save.sysenter_cs = data;
4313                 break;
4314         case MSR_IA32_SYSENTER_EIP:
4315                 svm->sysenter_eip = data;
4316                 svm->vmcb->save.sysenter_eip = data;
4317                 break;
4318         case MSR_IA32_SYSENTER_ESP:
4319                 svm->sysenter_esp = data;
4320                 svm->vmcb->save.sysenter_esp = data;
4321                 break;
4322         case MSR_TSC_AUX:
4323                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4324                         return 1;
4325
4326                 /*
4327                  * This is rare, so we update the MSR here instead of using
4328                  * direct_access_msrs.  Doing that would require a rdmsr in
4329                  * svm_vcpu_put.
4330                  */
4331                 svm->tsc_aux = data;
4332                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4333                 break;
4334         case MSR_IA32_DEBUGCTLMSR:
4335                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4336                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4337                                     __func__, data);
4338                         break;
4339                 }
4340                 if (data & DEBUGCTL_RESERVED_BITS)
4341                         return 1;
4342
4343                 svm->vmcb->save.dbgctl = data;
4344                 mark_dirty(svm->vmcb, VMCB_LBR);
4345                 if (data & (1ULL<<0))
4346                         svm_enable_lbrv(svm);
4347                 else
4348                         svm_disable_lbrv(svm);
4349                 break;
4350         case MSR_VM_HSAVE_PA:
4351                 svm->nested.hsave_msr = data;
4352                 break;
4353         case MSR_VM_CR:
4354                 return svm_set_vm_cr(vcpu, data);
4355         case MSR_VM_IGNNE:
4356                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4357                 break;
4358         case MSR_F10H_DECFG: {
4359                 struct kvm_msr_entry msr_entry;
4360
4361                 msr_entry.index = msr->index;
4362                 if (svm_get_msr_feature(&msr_entry))
4363                         return 1;
4364
4365                 /* Check the supported bits */
4366                 if (data & ~msr_entry.data)
4367                         return 1;
4368
4369                 /* Don't allow the guest to change a bit, #GP */
4370                 if (!msr->host_initiated && (data ^ msr_entry.data))
4371                         return 1;
4372
4373                 svm->msr_decfg = data;
4374                 break;
4375         }
4376         case MSR_IA32_APICBASE:
4377                 if (kvm_vcpu_apicv_active(vcpu))
4378                         avic_update_vapic_bar(to_svm(vcpu), data);
4379                 /* Follow through */
4380         default:
4381                 return kvm_set_msr_common(vcpu, msr);
4382         }
4383         return 0;
4384 }
4385
4386 static int wrmsr_interception(struct vcpu_svm *svm)
4387 {
4388         struct msr_data msr;
4389         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4390         u64 data = kvm_read_edx_eax(&svm->vcpu);
4391
4392         msr.data = data;
4393         msr.index = ecx;
4394         msr.host_initiated = false;
4395
4396         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4397         if (kvm_set_msr(&svm->vcpu, &msr)) {
4398                 trace_kvm_msr_write_ex(ecx, data);
4399                 kvm_inject_gp(&svm->vcpu, 0);
4400                 return 1;
4401         } else {
4402                 trace_kvm_msr_write(ecx, data);
4403                 return kvm_skip_emulated_instruction(&svm->vcpu);
4404         }
4405 }
4406
4407 static int msr_interception(struct vcpu_svm *svm)
4408 {
4409         if (svm->vmcb->control.exit_info_1)
4410                 return wrmsr_interception(svm);
4411         else
4412                 return rdmsr_interception(svm);
4413 }
4414
4415 static int interrupt_window_interception(struct vcpu_svm *svm)
4416 {
4417         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4418         svm_clear_vintr(svm);
4419         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4420         mark_dirty(svm->vmcb, VMCB_INTR);
4421         ++svm->vcpu.stat.irq_window_exits;
4422         return 1;
4423 }
4424
4425 static int pause_interception(struct vcpu_svm *svm)
4426 {
4427         struct kvm_vcpu *vcpu = &svm->vcpu;
4428         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4429
4430         if (pause_filter_thresh)
4431                 grow_ple_window(vcpu);
4432
4433         kvm_vcpu_on_spin(vcpu, in_kernel);
4434         return 1;
4435 }
4436
4437 static int nop_interception(struct vcpu_svm *svm)
4438 {
4439         return kvm_skip_emulated_instruction(&(svm->vcpu));
4440 }
4441
4442 static int monitor_interception(struct vcpu_svm *svm)
4443 {
4444         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4445         return nop_interception(svm);
4446 }
4447
4448 static int mwait_interception(struct vcpu_svm *svm)
4449 {
4450         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4451         return nop_interception(svm);
4452 }
4453
4454 enum avic_ipi_failure_cause {
4455         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4456         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4457         AVIC_IPI_FAILURE_INVALID_TARGET,
4458         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4459 };
4460
4461 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4462 {
4463         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4464         u32 icrl = svm->vmcb->control.exit_info_1;
4465         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4466         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4467         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4468
4469         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4470
4471         switch (id) {
4472         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4473                 /*
4474                  * AVIC hardware handles the generation of
4475                  * IPIs when the specified Message Type is Fixed
4476                  * (also known as fixed delivery mode) and
4477                  * the Trigger Mode is edge-triggered. The hardware
4478                  * also supports self and broadcast delivery modes
4479                  * specified via the Destination Shorthand(DSH)
4480                  * field of the ICRL. Logical and physical APIC ID
4481                  * formats are supported. All other IPI types cause
4482                  * a #VMEXIT, which needs to emulated.
4483                  */
4484                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4485                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4486                 break;
4487         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4488                 int i;
4489                 struct kvm_vcpu *vcpu;
4490                 struct kvm *kvm = svm->vcpu.kvm;
4491                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4492
4493                 /*
4494                  * At this point, we expect that the AVIC HW has already
4495                  * set the appropriate IRR bits on the valid target
4496                  * vcpus. So, we just need to kick the appropriate vcpu.
4497                  */
4498                 kvm_for_each_vcpu(i, vcpu, kvm) {
4499                         bool m = kvm_apic_match_dest(vcpu, apic,
4500                                                      icrl & KVM_APIC_SHORT_MASK,
4501                                                      GET_APIC_DEST_FIELD(icrh),
4502                                                      icrl & KVM_APIC_DEST_MASK);
4503
4504                         if (m && !avic_vcpu_is_running(vcpu))
4505                                 kvm_vcpu_wake_up(vcpu);
4506                 }
4507                 break;
4508         }
4509         case AVIC_IPI_FAILURE_INVALID_TARGET:
4510                 break;
4511         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4512                 WARN_ONCE(1, "Invalid backing page\n");
4513                 break;
4514         default:
4515                 pr_err("Unknown IPI interception\n");
4516         }
4517
4518         return 1;
4519 }
4520
4521 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4522 {
4523         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4524         int index;
4525         u32 *logical_apic_id_table;
4526         int dlid = GET_APIC_LOGICAL_ID(ldr);
4527
4528         if (!dlid)
4529                 return NULL;
4530
4531         if (flat) { /* flat */
4532                 index = ffs(dlid) - 1;
4533                 if (index > 7)
4534                         return NULL;
4535         } else { /* cluster */
4536                 int cluster = (dlid & 0xf0) >> 4;
4537                 int apic = ffs(dlid & 0x0f) - 1;
4538
4539                 if ((apic < 0) || (apic > 7) ||
4540                     (cluster >= 0xf))
4541                         return NULL;
4542                 index = (cluster << 2) + apic;
4543         }
4544
4545         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4546
4547         return &logical_apic_id_table[index];
4548 }
4549
4550 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4551                           bool valid)
4552 {
4553         bool flat;
4554         u32 *entry, new_entry;
4555
4556         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4557         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4558         if (!entry)
4559                 return -EINVAL;
4560
4561         new_entry = READ_ONCE(*entry);
4562         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4563         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4564         if (valid)
4565                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4566         else
4567                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4568         WRITE_ONCE(*entry, new_entry);
4569
4570         return 0;
4571 }
4572
4573 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4574 {
4575         int ret;
4576         struct vcpu_svm *svm = to_svm(vcpu);
4577         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4578
4579         if (!ldr)
4580                 return 1;
4581
4582         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4583         if (ret && svm->ldr_reg) {
4584                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4585                 svm->ldr_reg = 0;
4586         } else {
4587                 svm->ldr_reg = ldr;
4588         }
4589         return ret;
4590 }
4591
4592 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4593 {
4594         u64 *old, *new;
4595         struct vcpu_svm *svm = to_svm(vcpu);
4596         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4597         u32 id = (apic_id_reg >> 24) & 0xff;
4598
4599         if (vcpu->vcpu_id == id)
4600                 return 0;
4601
4602         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4603         new = avic_get_physical_id_entry(vcpu, id);
4604         if (!new || !old)
4605                 return 1;
4606
4607         /* We need to move physical_id_entry to new offset */
4608         *new = *old;
4609         *old = 0ULL;
4610         to_svm(vcpu)->avic_physical_id_cache = new;
4611
4612         /*
4613          * Also update the guest physical APIC ID in the logical
4614          * APIC ID table entry if already setup the LDR.
4615          */
4616         if (svm->ldr_reg)
4617                 avic_handle_ldr_update(vcpu);
4618
4619         return 0;
4620 }
4621
4622 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4623 {
4624         struct vcpu_svm *svm = to_svm(vcpu);
4625         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4626         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4627         u32 mod = (dfr >> 28) & 0xf;
4628
4629         /*
4630          * We assume that all local APICs are using the same type.
4631          * If this changes, we need to flush the AVIC logical
4632          * APID id table.
4633          */
4634         if (kvm_svm->ldr_mode == mod)
4635                 return 0;
4636
4637         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4638         kvm_svm->ldr_mode = mod;
4639
4640         if (svm->ldr_reg)
4641                 avic_handle_ldr_update(vcpu);
4642         return 0;
4643 }
4644
4645 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4646 {
4647         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4648         u32 offset = svm->vmcb->control.exit_info_1 &
4649                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4650
4651         switch (offset) {
4652         case APIC_ID:
4653                 if (avic_handle_apic_id_update(&svm->vcpu))
4654                         return 0;
4655                 break;
4656         case APIC_LDR:
4657                 if (avic_handle_ldr_update(&svm->vcpu))
4658                         return 0;
4659                 break;
4660         case APIC_DFR:
4661                 avic_handle_dfr_update(&svm->vcpu);
4662                 break;
4663         default:
4664                 break;
4665         }
4666
4667         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4668
4669         return 1;
4670 }
4671
4672 static bool is_avic_unaccelerated_access_trap(u32 offset)
4673 {
4674         bool ret = false;
4675
4676         switch (offset) {
4677         case APIC_ID:
4678         case APIC_EOI:
4679         case APIC_RRR:
4680         case APIC_LDR:
4681         case APIC_DFR:
4682         case APIC_SPIV:
4683         case APIC_ESR:
4684         case APIC_ICR:
4685         case APIC_LVTT:
4686         case APIC_LVTTHMR:
4687         case APIC_LVTPC:
4688         case APIC_LVT0:
4689         case APIC_LVT1:
4690         case APIC_LVTERR:
4691         case APIC_TMICT:
4692         case APIC_TDCR:
4693                 ret = true;
4694                 break;
4695         default:
4696                 break;
4697         }
4698         return ret;
4699 }
4700
4701 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4702 {
4703         int ret = 0;
4704         u32 offset = svm->vmcb->control.exit_info_1 &
4705                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4706         u32 vector = svm->vmcb->control.exit_info_2 &
4707                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4708         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4709                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4710         bool trap = is_avic_unaccelerated_access_trap(offset);
4711
4712         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4713                                             trap, write, vector);
4714         if (trap) {
4715                 /* Handling Trap */
4716                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4717                 ret = avic_unaccel_trap_write(svm);
4718         } else {
4719                 /* Handling Fault */
4720                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4721         }
4722
4723         return ret;
4724 }
4725
4726 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4727         [SVM_EXIT_READ_CR0]                     = cr_interception,
4728         [SVM_EXIT_READ_CR3]                     = cr_interception,
4729         [SVM_EXIT_READ_CR4]                     = cr_interception,
4730         [SVM_EXIT_READ_CR8]                     = cr_interception,
4731         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4732         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4733         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4734         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4735         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4736         [SVM_EXIT_READ_DR0]                     = dr_interception,
4737         [SVM_EXIT_READ_DR1]                     = dr_interception,
4738         [SVM_EXIT_READ_DR2]                     = dr_interception,
4739         [SVM_EXIT_READ_DR3]                     = dr_interception,
4740         [SVM_EXIT_READ_DR4]                     = dr_interception,
4741         [SVM_EXIT_READ_DR5]                     = dr_interception,
4742         [SVM_EXIT_READ_DR6]                     = dr_interception,
4743         [SVM_EXIT_READ_DR7]                     = dr_interception,
4744         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4745         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4746         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4747         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4748         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4749         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4750         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4751         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4752         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4753         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4754         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4755         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4756         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4757         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4758         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4759         [SVM_EXIT_INTR]                         = intr_interception,
4760         [SVM_EXIT_NMI]                          = nmi_interception,
4761         [SVM_EXIT_SMI]                          = nop_on_interception,
4762         [SVM_EXIT_INIT]                         = nop_on_interception,
4763         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4764         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4765         [SVM_EXIT_CPUID]                        = cpuid_interception,
4766         [SVM_EXIT_IRET]                         = iret_interception,
4767         [SVM_EXIT_INVD]                         = emulate_on_interception,
4768         [SVM_EXIT_PAUSE]                        = pause_interception,
4769         [SVM_EXIT_HLT]                          = halt_interception,
4770         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4771         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4772         [SVM_EXIT_IOIO]                         = io_interception,
4773         [SVM_EXIT_MSR]                          = msr_interception,
4774         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4775         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4776         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4777         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4778         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4779         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4780         [SVM_EXIT_STGI]                         = stgi_interception,
4781         [SVM_EXIT_CLGI]                         = clgi_interception,
4782         [SVM_EXIT_SKINIT]                       = skinit_interception,
4783         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4784         [SVM_EXIT_MONITOR]                      = monitor_interception,
4785         [SVM_EXIT_MWAIT]                        = mwait_interception,
4786         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4787         [SVM_EXIT_NPF]                          = npf_interception,
4788         [SVM_EXIT_RSM]                          = rsm_interception,
4789         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4790         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4791 };
4792
4793 static void dump_vmcb(struct kvm_vcpu *vcpu)
4794 {
4795         struct vcpu_svm *svm = to_svm(vcpu);
4796         struct vmcb_control_area *control = &svm->vmcb->control;
4797         struct vmcb_save_area *save = &svm->vmcb->save;
4798
4799         pr_err("VMCB Control Area:\n");
4800         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4801         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4802         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4803         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4804         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4805         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4806         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4807         pr_err("%-20s%d\n", "pause filter threshold:",
4808                control->pause_filter_thresh);
4809         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4810         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4811         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4812         pr_err("%-20s%d\n", "asid:", control->asid);
4813         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4814         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4815         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4816         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4817         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4818         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4819         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4820         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4821         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4822         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4823         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4824         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4825         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4826         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4827         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4828         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4829         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4830         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4831         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4832         pr_err("VMCB State Save Area:\n");
4833         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4834                "es:",
4835                save->es.selector, save->es.attrib,
4836                save->es.limit, save->es.base);
4837         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4838                "cs:",
4839                save->cs.selector, save->cs.attrib,
4840                save->cs.limit, save->cs.base);
4841         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4842                "ss:",
4843                save->ss.selector, save->ss.attrib,
4844                save->ss.limit, save->ss.base);
4845         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4846                "ds:",
4847                save->ds.selector, save->ds.attrib,
4848                save->ds.limit, save->ds.base);
4849         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4850                "fs:",
4851                save->fs.selector, save->fs.attrib,
4852                save->fs.limit, save->fs.base);
4853         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4854                "gs:",
4855                save->gs.selector, save->gs.attrib,
4856                save->gs.limit, save->gs.base);
4857         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4858                "gdtr:",
4859                save->gdtr.selector, save->gdtr.attrib,
4860                save->gdtr.limit, save->gdtr.base);
4861         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4862                "ldtr:",
4863                save->ldtr.selector, save->ldtr.attrib,
4864                save->ldtr.limit, save->ldtr.base);
4865         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4866                "idtr:",
4867                save->idtr.selector, save->idtr.attrib,
4868                save->idtr.limit, save->idtr.base);
4869         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4870                "tr:",
4871                save->tr.selector, save->tr.attrib,
4872                save->tr.limit, save->tr.base);
4873         pr_err("cpl:            %d                efer:         %016llx\n",
4874                 save->cpl, save->efer);
4875         pr_err("%-15s %016llx %-13s %016llx\n",
4876                "cr0:", save->cr0, "cr2:", save->cr2);
4877         pr_err("%-15s %016llx %-13s %016llx\n",
4878                "cr3:", save->cr3, "cr4:", save->cr4);
4879         pr_err("%-15s %016llx %-13s %016llx\n",
4880                "dr6:", save->dr6, "dr7:", save->dr7);
4881         pr_err("%-15s %016llx %-13s %016llx\n",
4882                "rip:", save->rip, "rflags:", save->rflags);
4883         pr_err("%-15s %016llx %-13s %016llx\n",
4884                "rsp:", save->rsp, "rax:", save->rax);
4885         pr_err("%-15s %016llx %-13s %016llx\n",
4886                "star:", save->star, "lstar:", save->lstar);
4887         pr_err("%-15s %016llx %-13s %016llx\n",
4888                "cstar:", save->cstar, "sfmask:", save->sfmask);
4889         pr_err("%-15s %016llx %-13s %016llx\n",
4890                "kernel_gs_base:", save->kernel_gs_base,
4891                "sysenter_cs:", save->sysenter_cs);
4892         pr_err("%-15s %016llx %-13s %016llx\n",
4893                "sysenter_esp:", save->sysenter_esp,
4894                "sysenter_eip:", save->sysenter_eip);
4895         pr_err("%-15s %016llx %-13s %016llx\n",
4896                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4897         pr_err("%-15s %016llx %-13s %016llx\n",
4898                "br_from:", save->br_from, "br_to:", save->br_to);
4899         pr_err("%-15s %016llx %-13s %016llx\n",
4900                "excp_from:", save->last_excp_from,
4901                "excp_to:", save->last_excp_to);
4902 }
4903
4904 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4905 {
4906         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4907
4908         *info1 = control->exit_info_1;
4909         *info2 = control->exit_info_2;
4910 }
4911
4912 static int handle_exit(struct kvm_vcpu *vcpu)
4913 {
4914         struct vcpu_svm *svm = to_svm(vcpu);
4915         struct kvm_run *kvm_run = vcpu->run;
4916         u32 exit_code = svm->vmcb->control.exit_code;
4917
4918         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4919
4920         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4921                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4922         if (npt_enabled)
4923                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4924
4925         if (unlikely(svm->nested.exit_required)) {
4926                 nested_svm_vmexit(svm);
4927                 svm->nested.exit_required = false;
4928
4929                 return 1;
4930         }
4931
4932         if (is_guest_mode(vcpu)) {
4933                 int vmexit;
4934
4935                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4936                                         svm->vmcb->control.exit_info_1,
4937                                         svm->vmcb->control.exit_info_2,
4938                                         svm->vmcb->control.exit_int_info,
4939                                         svm->vmcb->control.exit_int_info_err,
4940                                         KVM_ISA_SVM);
4941
4942                 vmexit = nested_svm_exit_special(svm);
4943
4944                 if (vmexit == NESTED_EXIT_CONTINUE)
4945                         vmexit = nested_svm_exit_handled(svm);
4946
4947                 if (vmexit == NESTED_EXIT_DONE)
4948                         return 1;
4949         }
4950
4951         svm_complete_interrupts(svm);
4952
4953         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4954                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4955                 kvm_run->fail_entry.hardware_entry_failure_reason
4956                         = svm->vmcb->control.exit_code;
4957                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4958                 dump_vmcb(vcpu);
4959                 return 0;
4960         }
4961
4962         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4963             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4964             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4965             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4966                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4967                        "exit_code 0x%x\n",
4968                        __func__, svm->vmcb->control.exit_int_info,
4969                        exit_code);
4970
4971         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4972             || !svm_exit_handlers[exit_code]) {
4973                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4974                 kvm_queue_exception(vcpu, UD_VECTOR);
4975                 return 1;
4976         }
4977
4978         return svm_exit_handlers[exit_code](svm);
4979 }
4980
4981 static void reload_tss(struct kvm_vcpu *vcpu)
4982 {
4983         int cpu = raw_smp_processor_id();
4984
4985         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4986         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4987         load_TR_desc();
4988 }
4989
4990 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4991 {
4992         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4993         int asid = sev_get_asid(svm->vcpu.kvm);
4994
4995         /* Assign the asid allocated with this SEV guest */
4996         svm->vmcb->control.asid = asid;
4997
4998         /*
4999          * Flush guest TLB:
5000          *
5001          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5002          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5003          */
5004         if (sd->sev_vmcbs[asid] == svm->vmcb &&
5005             svm->last_cpu == cpu)
5006                 return;
5007
5008         svm->last_cpu = cpu;
5009         sd->sev_vmcbs[asid] = svm->vmcb;
5010         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5011         mark_dirty(svm->vmcb, VMCB_ASID);
5012 }
5013
5014 static void pre_svm_run(struct vcpu_svm *svm)
5015 {
5016         int cpu = raw_smp_processor_id();
5017
5018         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5019
5020         if (sev_guest(svm->vcpu.kvm))
5021                 return pre_sev_run(svm, cpu);
5022
5023         /* FIXME: handle wraparound of asid_generation */
5024         if (svm->asid_generation != sd->asid_generation)
5025                 new_asid(svm, sd);
5026 }
5027
5028 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5029 {
5030         struct vcpu_svm *svm = to_svm(vcpu);
5031
5032         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5033         vcpu->arch.hflags |= HF_NMI_MASK;
5034         set_intercept(svm, INTERCEPT_IRET);
5035         ++vcpu->stat.nmi_injections;
5036 }
5037
5038 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5039 {
5040         struct vmcb_control_area *control;
5041
5042         /* The following fields are ignored when AVIC is enabled */
5043         control = &svm->vmcb->control;
5044         control->int_vector = irq;
5045         control->int_ctl &= ~V_INTR_PRIO_MASK;
5046         control->int_ctl |= V_IRQ_MASK |
5047                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5048         mark_dirty(svm->vmcb, VMCB_INTR);
5049 }
5050
5051 static void svm_set_irq(struct kvm_vcpu *vcpu)
5052 {
5053         struct vcpu_svm *svm = to_svm(vcpu);
5054
5055         BUG_ON(!(gif_set(svm)));
5056
5057         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5058         ++vcpu->stat.irq_injections;
5059
5060         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5061                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5062 }
5063
5064 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5065 {
5066         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5067 }
5068
5069 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5070 {
5071         struct vcpu_svm *svm = to_svm(vcpu);
5072
5073         if (svm_nested_virtualize_tpr(vcpu) ||
5074             kvm_vcpu_apicv_active(vcpu))
5075                 return;
5076
5077         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5078
5079         if (irr == -1)
5080                 return;
5081
5082         if (tpr >= irr)
5083                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5084 }
5085
5086 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5087 {
5088         return;
5089 }
5090
5091 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5092 {
5093         return avic && irqchip_split(vcpu->kvm);
5094 }
5095
5096 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5097 {
5098 }
5099
5100 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5101 {
5102 }
5103
5104 /* Note: Currently only used by Hyper-V. */
5105 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5106 {
5107         struct vcpu_svm *svm = to_svm(vcpu);
5108         struct vmcb *vmcb = svm->vmcb;
5109
5110         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5111                 return;
5112
5113         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5114         mark_dirty(vmcb, VMCB_INTR);
5115 }
5116
5117 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5118 {
5119         return;
5120 }
5121
5122 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5123 {
5124         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5125         smp_mb__after_atomic();
5126
5127         if (avic_vcpu_is_running(vcpu))
5128                 wrmsrl(SVM_AVIC_DOORBELL,
5129                        kvm_cpu_get_apicid(vcpu->cpu));
5130         else
5131                 kvm_vcpu_wake_up(vcpu);
5132 }
5133
5134 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5135 {
5136         unsigned long flags;
5137         struct amd_svm_iommu_ir *cur;
5138
5139         spin_lock_irqsave(&svm->ir_list_lock, flags);
5140         list_for_each_entry(cur, &svm->ir_list, node) {
5141                 if (cur->data != pi->ir_data)
5142                         continue;
5143                 list_del(&cur->node);
5144                 kfree(cur);
5145                 break;
5146         }
5147         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5148 }
5149
5150 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5151 {
5152         int ret = 0;
5153         unsigned long flags;
5154         struct amd_svm_iommu_ir *ir;
5155
5156         /**
5157          * In some cases, the existing irte is updaed and re-set,
5158          * so we need to check here if it's already been * added
5159          * to the ir_list.
5160          */
5161         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5162                 struct kvm *kvm = svm->vcpu.kvm;
5163                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5164                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5165                 struct vcpu_svm *prev_svm;
5166
5167                 if (!prev_vcpu) {
5168                         ret = -EINVAL;
5169                         goto out;
5170                 }
5171
5172                 prev_svm = to_svm(prev_vcpu);
5173                 svm_ir_list_del(prev_svm, pi);
5174         }
5175
5176         /**
5177          * Allocating new amd_iommu_pi_data, which will get
5178          * add to the per-vcpu ir_list.
5179          */
5180         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5181         if (!ir) {
5182                 ret = -ENOMEM;
5183                 goto out;
5184         }
5185         ir->data = pi->ir_data;
5186
5187         spin_lock_irqsave(&svm->ir_list_lock, flags);
5188         list_add(&ir->node, &svm->ir_list);
5189         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5190 out:
5191         return ret;
5192 }
5193
5194 /**
5195  * Note:
5196  * The HW cannot support posting multicast/broadcast
5197  * interrupts to a vCPU. So, we still use legacy interrupt
5198  * remapping for these kind of interrupts.
5199  *
5200  * For lowest-priority interrupts, we only support
5201  * those with single CPU as the destination, e.g. user
5202  * configures the interrupts via /proc/irq or uses
5203  * irqbalance to make the interrupts single-CPU.
5204  */
5205 static int
5206 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5207                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5208 {
5209         struct kvm_lapic_irq irq;
5210         struct kvm_vcpu *vcpu = NULL;
5211
5212         kvm_set_msi_irq(kvm, e, &irq);
5213
5214         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5215                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5216                          __func__, irq.vector);
5217                 return -1;
5218         }
5219
5220         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5221                  irq.vector);
5222         *svm = to_svm(vcpu);
5223         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5224         vcpu_info->vector = irq.vector;
5225
5226         return 0;
5227 }
5228
5229 /*
5230  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5231  *
5232  * @kvm: kvm
5233  * @host_irq: host irq of the interrupt
5234  * @guest_irq: gsi of the interrupt
5235  * @set: set or unset PI
5236  * returns 0 on success, < 0 on failure
5237  */
5238 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5239                               uint32_t guest_irq, bool set)
5240 {
5241         struct kvm_kernel_irq_routing_entry *e;
5242         struct kvm_irq_routing_table *irq_rt;
5243         int idx, ret = -EINVAL;
5244
5245         if (!kvm_arch_has_assigned_device(kvm) ||
5246             !irq_remapping_cap(IRQ_POSTING_CAP))
5247                 return 0;
5248
5249         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5250                  __func__, host_irq, guest_irq, set);
5251
5252         idx = srcu_read_lock(&kvm->irq_srcu);
5253         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5254         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5255
5256         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5257                 struct vcpu_data vcpu_info;
5258                 struct vcpu_svm *svm = NULL;
5259
5260                 if (e->type != KVM_IRQ_ROUTING_MSI)
5261                         continue;
5262
5263                 /**
5264                  * Here, we setup with legacy mode in the following cases:
5265                  * 1. When cannot target interrupt to a specific vcpu.
5266                  * 2. Unsetting posted interrupt.
5267                  * 3. APIC virtialization is disabled for the vcpu.
5268                  */
5269                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5270                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5271                         struct amd_iommu_pi_data pi;
5272
5273                         /* Try to enable guest_mode in IRTE */
5274                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5275                                             AVIC_HPA_MASK);
5276                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5277                                                      svm->vcpu.vcpu_id);
5278                         pi.is_guest_mode = true;
5279                         pi.vcpu_data = &vcpu_info;
5280                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5281
5282                         /**
5283                          * Here, we successfully setting up vcpu affinity in
5284                          * IOMMU guest mode. Now, we need to store the posted
5285                          * interrupt information in a per-vcpu ir_list so that
5286                          * we can reference to them directly when we update vcpu
5287                          * scheduling information in IOMMU irte.
5288                          */
5289                         if (!ret && pi.is_guest_mode)
5290                                 svm_ir_list_add(svm, &pi);
5291                 } else {
5292                         /* Use legacy mode in IRTE */
5293                         struct amd_iommu_pi_data pi;
5294
5295                         /**
5296                          * Here, pi is used to:
5297                          * - Tell IOMMU to use legacy mode for this interrupt.
5298                          * - Retrieve ga_tag of prior interrupt remapping data.
5299                          */
5300                         pi.is_guest_mode = false;
5301                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5302
5303                         /**
5304                          * Check if the posted interrupt was previously
5305                          * setup with the guest_mode by checking if the ga_tag
5306                          * was cached. If so, we need to clean up the per-vcpu
5307                          * ir_list.
5308                          */
5309                         if (!ret && pi.prev_ga_tag) {
5310                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5311                                 struct kvm_vcpu *vcpu;
5312
5313                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5314                                 if (vcpu)
5315                                         svm_ir_list_del(to_svm(vcpu), &pi);
5316                         }
5317                 }
5318
5319                 if (!ret && svm) {
5320                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5321                                                  e->gsi, vcpu_info.vector,
5322                                                  vcpu_info.pi_desc_addr, set);
5323                 }
5324
5325                 if (ret < 0) {
5326                         pr_err("%s: failed to update PI IRTE\n", __func__);
5327                         goto out;
5328                 }
5329         }
5330
5331         ret = 0;
5332 out:
5333         srcu_read_unlock(&kvm->irq_srcu, idx);
5334         return ret;
5335 }
5336
5337 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5338 {
5339         struct vcpu_svm *svm = to_svm(vcpu);
5340         struct vmcb *vmcb = svm->vmcb;
5341         int ret;
5342         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5343               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5344         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5345
5346         return ret;
5347 }
5348
5349 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5350 {
5351         struct vcpu_svm *svm = to_svm(vcpu);
5352
5353         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5354 }
5355
5356 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5357 {
5358         struct vcpu_svm *svm = to_svm(vcpu);
5359
5360         if (masked) {
5361                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5362                 set_intercept(svm, INTERCEPT_IRET);
5363         } else {
5364                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5365                 clr_intercept(svm, INTERCEPT_IRET);
5366         }
5367 }
5368
5369 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5370 {
5371         struct vcpu_svm *svm = to_svm(vcpu);
5372         struct vmcb *vmcb = svm->vmcb;
5373         int ret;
5374
5375         if (!gif_set(svm) ||
5376              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5377                 return 0;
5378
5379         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5380
5381         if (is_guest_mode(vcpu))
5382                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5383
5384         return ret;
5385 }
5386
5387 static void enable_irq_window(struct kvm_vcpu *vcpu)
5388 {
5389         struct vcpu_svm *svm = to_svm(vcpu);
5390
5391         if (kvm_vcpu_apicv_active(vcpu))
5392                 return;
5393
5394         /*
5395          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5396          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5397          * get that intercept, this function will be called again though and
5398          * we'll get the vintr intercept. However, if the vGIF feature is
5399          * enabled, the STGI interception will not occur. Enable the irq
5400          * window under the assumption that the hardware will set the GIF.
5401          */
5402         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5403                 svm_set_vintr(svm);
5404                 svm_inject_irq(svm, 0x0);
5405         }
5406 }
5407
5408 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5409 {
5410         struct vcpu_svm *svm = to_svm(vcpu);
5411
5412         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5413             == HF_NMI_MASK)
5414                 return; /* IRET will cause a vm exit */
5415
5416         if (!gif_set(svm)) {
5417                 if (vgif_enabled(svm))
5418                         set_intercept(svm, INTERCEPT_STGI);
5419                 return; /* STGI will cause a vm exit */
5420         }
5421
5422         if (svm->nested.exit_required)
5423                 return; /* we're not going to run the guest yet */
5424
5425         /*
5426          * Something prevents NMI from been injected. Single step over possible
5427          * problem (IRET or exception injection or interrupt shadow)
5428          */
5429         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5430         svm->nmi_singlestep = true;
5431         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5432 }
5433
5434 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5435 {
5436         return 0;
5437 }
5438
5439 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5440 {
5441         return 0;
5442 }
5443
5444 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5445 {
5446         struct vcpu_svm *svm = to_svm(vcpu);
5447
5448         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5449                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5450         else
5451                 svm->asid_generation--;
5452 }
5453
5454 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5455 {
5456         struct vcpu_svm *svm = to_svm(vcpu);
5457
5458         invlpga(gva, svm->vmcb->control.asid);
5459 }
5460
5461 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5462 {
5463 }
5464
5465 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5466 {
5467         struct vcpu_svm *svm = to_svm(vcpu);
5468
5469         if (svm_nested_virtualize_tpr(vcpu))
5470                 return;
5471
5472         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5473                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5474                 kvm_set_cr8(vcpu, cr8);
5475         }
5476 }
5477
5478 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5479 {
5480         struct vcpu_svm *svm = to_svm(vcpu);
5481         u64 cr8;
5482
5483         if (svm_nested_virtualize_tpr(vcpu) ||
5484             kvm_vcpu_apicv_active(vcpu))
5485                 return;
5486
5487         cr8 = kvm_get_cr8(vcpu);
5488         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5489         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5490 }
5491
5492 static void svm_complete_interrupts(struct vcpu_svm *svm)
5493 {
5494         u8 vector;
5495         int type;
5496         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5497         unsigned int3_injected = svm->int3_injected;
5498
5499         svm->int3_injected = 0;
5500
5501         /*
5502          * If we've made progress since setting HF_IRET_MASK, we've
5503          * executed an IRET and can allow NMI injection.
5504          */
5505         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5506             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5507                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5508                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5509         }
5510
5511         svm->vcpu.arch.nmi_injected = false;
5512         kvm_clear_exception_queue(&svm->vcpu);
5513         kvm_clear_interrupt_queue(&svm->vcpu);
5514
5515         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5516                 return;
5517
5518         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5519
5520         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5521         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5522
5523         switch (type) {
5524         case SVM_EXITINTINFO_TYPE_NMI:
5525                 svm->vcpu.arch.nmi_injected = true;
5526                 break;
5527         case SVM_EXITINTINFO_TYPE_EXEPT:
5528                 /*
5529                  * In case of software exceptions, do not reinject the vector,
5530                  * but re-execute the instruction instead. Rewind RIP first
5531                  * if we emulated INT3 before.
5532                  */
5533                 if (kvm_exception_is_soft(vector)) {
5534                         if (vector == BP_VECTOR && int3_injected &&
5535                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5536                                 kvm_rip_write(&svm->vcpu,
5537                                               kvm_rip_read(&svm->vcpu) -
5538                                               int3_injected);
5539                         break;
5540                 }
5541                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5542                         u32 err = svm->vmcb->control.exit_int_info_err;
5543                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5544
5545                 } else
5546                         kvm_requeue_exception(&svm->vcpu, vector);
5547                 break;
5548         case SVM_EXITINTINFO_TYPE_INTR:
5549                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5550                 break;
5551         default:
5552                 break;
5553         }
5554 }
5555
5556 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5557 {
5558         struct vcpu_svm *svm = to_svm(vcpu);
5559         struct vmcb_control_area *control = &svm->vmcb->control;
5560
5561         control->exit_int_info = control->event_inj;
5562         control->exit_int_info_err = control->event_inj_err;
5563         control->event_inj = 0;
5564         svm_complete_interrupts(svm);
5565 }
5566
5567 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5568 {
5569         struct vcpu_svm *svm = to_svm(vcpu);
5570
5571         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5572         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5573         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5574
5575         /*
5576          * A vmexit emulation is required before the vcpu can be executed
5577          * again.
5578          */
5579         if (unlikely(svm->nested.exit_required))
5580                 return;
5581
5582         /*
5583          * Disable singlestep if we're injecting an interrupt/exception.
5584          * We don't want our modified rflags to be pushed on the stack where
5585          * we might not be able to easily reset them if we disabled NMI
5586          * singlestep later.
5587          */
5588         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5589                 /*
5590                  * Event injection happens before external interrupts cause a
5591                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5592                  * is enough to force an immediate vmexit.
5593                  */
5594                 disable_nmi_singlestep(svm);
5595                 smp_send_reschedule(vcpu->cpu);
5596         }
5597
5598         pre_svm_run(svm);
5599
5600         sync_lapic_to_cr8(vcpu);
5601
5602         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5603
5604         clgi();
5605
5606         /*
5607          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5608          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5609          * is no need to worry about the conditional branch over the wrmsr
5610          * being speculatively taken.
5611          */
5612         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5613
5614         local_irq_enable();
5615
5616         asm volatile (
5617                 "push %%" _ASM_BP "; \n\t"
5618                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5619                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5620                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5621                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5622                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5623                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5624 #ifdef CONFIG_X86_64
5625                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5626                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5627                 "mov %c[r10](%[svm]), %%r10 \n\t"
5628                 "mov %c[r11](%[svm]), %%r11 \n\t"
5629                 "mov %c[r12](%[svm]), %%r12 \n\t"
5630                 "mov %c[r13](%[svm]), %%r13 \n\t"
5631                 "mov %c[r14](%[svm]), %%r14 \n\t"
5632                 "mov %c[r15](%[svm]), %%r15 \n\t"
5633 #endif
5634
5635                 /* Enter guest mode */
5636                 "push %%" _ASM_AX " \n\t"
5637                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5638                 __ex(SVM_VMLOAD) "\n\t"
5639                 __ex(SVM_VMRUN) "\n\t"
5640                 __ex(SVM_VMSAVE) "\n\t"
5641                 "pop %%" _ASM_AX " \n\t"
5642
5643                 /* Save guest registers, load host registers */
5644                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5645                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5646                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5647                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5648                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5649                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5650 #ifdef CONFIG_X86_64
5651                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5652                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5653                 "mov %%r10, %c[r10](%[svm]) \n\t"
5654                 "mov %%r11, %c[r11](%[svm]) \n\t"
5655                 "mov %%r12, %c[r12](%[svm]) \n\t"
5656                 "mov %%r13, %c[r13](%[svm]) \n\t"
5657                 "mov %%r14, %c[r14](%[svm]) \n\t"
5658                 "mov %%r15, %c[r15](%[svm]) \n\t"
5659                 /*
5660                 * Clear host registers marked as clobbered to prevent
5661                 * speculative use.
5662                 */
5663                 "xor %%r8d, %%r8d \n\t"
5664                 "xor %%r9d, %%r9d \n\t"
5665                 "xor %%r10d, %%r10d \n\t"
5666                 "xor %%r11d, %%r11d \n\t"
5667                 "xor %%r12d, %%r12d \n\t"
5668                 "xor %%r13d, %%r13d \n\t"
5669                 "xor %%r14d, %%r14d \n\t"
5670                 "xor %%r15d, %%r15d \n\t"
5671 #endif
5672                 "xor %%ebx, %%ebx \n\t"
5673                 "xor %%ecx, %%ecx \n\t"
5674                 "xor %%edx, %%edx \n\t"
5675                 "xor %%esi, %%esi \n\t"
5676                 "xor %%edi, %%edi \n\t"
5677                 "pop %%" _ASM_BP
5678                 :
5679                 : [svm]"a"(svm),
5680                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5681                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5682                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5683                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5684                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5685                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5686                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5687 #ifdef CONFIG_X86_64
5688                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5689                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5690                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5691                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5692                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5693                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5694                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5695                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5696 #endif
5697                 : "cc", "memory"
5698 #ifdef CONFIG_X86_64
5699                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5700                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5701 #else
5702                 , "ebx", "ecx", "edx", "esi", "edi"
5703 #endif
5704                 );
5705
5706         /* Eliminate branch target predictions from guest mode */
5707         vmexit_fill_RSB();
5708
5709 #ifdef CONFIG_X86_64
5710         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5711 #else
5712         loadsegment(fs, svm->host.fs);
5713 #ifndef CONFIG_X86_32_LAZY_GS
5714         loadsegment(gs, svm->host.gs);
5715 #endif
5716 #endif
5717
5718         /*
5719          * We do not use IBRS in the kernel. If this vCPU has used the
5720          * SPEC_CTRL MSR it may have left it on; save the value and
5721          * turn it off. This is much more efficient than blindly adding
5722          * it to the atomic save/restore list. Especially as the former
5723          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5724          *
5725          * For non-nested case:
5726          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5727          * save it.
5728          *
5729          * For nested case:
5730          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5731          * save it.
5732          */
5733         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5734                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5735
5736         reload_tss(vcpu);
5737
5738         local_irq_disable();
5739
5740         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5741
5742         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5743         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5744         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5745         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5746
5747         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5748                 kvm_before_interrupt(&svm->vcpu);
5749
5750         stgi();
5751
5752         /* Any pending NMI will happen here */
5753
5754         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5755                 kvm_after_interrupt(&svm->vcpu);
5756
5757         sync_cr8_to_lapic(vcpu);
5758
5759         svm->next_rip = 0;
5760
5761         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5762
5763         /* if exit due to PF check for async PF */
5764         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5765                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5766
5767         if (npt_enabled) {
5768                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5769                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5770         }
5771
5772         /*
5773          * We need to handle MC intercepts here before the vcpu has a chance to
5774          * change the physical cpu
5775          */
5776         if (unlikely(svm->vmcb->control.exit_code ==
5777                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5778                 svm_handle_mce(svm);
5779
5780         mark_all_clean(svm->vmcb);
5781 }
5782 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5783
5784 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5785 {
5786         struct vcpu_svm *svm = to_svm(vcpu);
5787
5788         svm->vmcb->save.cr3 = __sme_set(root);
5789         mark_dirty(svm->vmcb, VMCB_CR);
5790 }
5791
5792 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5793 {
5794         struct vcpu_svm *svm = to_svm(vcpu);
5795
5796         svm->vmcb->control.nested_cr3 = __sme_set(root);
5797         mark_dirty(svm->vmcb, VMCB_NPT);
5798
5799         /* Also sync guest cr3 here in case we live migrate */
5800         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5801         mark_dirty(svm->vmcb, VMCB_CR);
5802 }
5803
5804 static int is_disabled(void)
5805 {
5806         u64 vm_cr;
5807
5808         rdmsrl(MSR_VM_CR, vm_cr);
5809         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5810                 return 1;
5811
5812         return 0;
5813 }
5814
5815 static void
5816 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5817 {
5818         /*
5819          * Patch in the VMMCALL instruction:
5820          */
5821         hypercall[0] = 0x0f;
5822         hypercall[1] = 0x01;
5823         hypercall[2] = 0xd9;
5824 }
5825
5826 static void svm_check_processor_compat(void *rtn)
5827 {
5828         *(int *)rtn = 0;
5829 }
5830
5831 static bool svm_cpu_has_accelerated_tpr(void)
5832 {
5833         return false;
5834 }
5835
5836 static bool svm_has_emulated_msr(int index)
5837 {
5838         return true;
5839 }
5840
5841 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5842 {
5843         return 0;
5844 }
5845
5846 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5847 {
5848         struct vcpu_svm *svm = to_svm(vcpu);
5849
5850         /* Update nrips enabled cache */
5851         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5852
5853         if (!kvm_vcpu_apicv_active(vcpu))
5854                 return;
5855
5856         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5857 }
5858
5859 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5860 {
5861         switch (func) {
5862         case 0x1:
5863                 if (avic)
5864                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5865                 break;
5866         case 0x80000001:
5867                 if (nested)
5868                         entry->ecx |= (1 << 2); /* Set SVM bit */
5869                 break;
5870         case 0x8000000A:
5871                 entry->eax = 1; /* SVM revision 1 */
5872                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5873                                    ASID emulation to nested SVM */
5874                 entry->ecx = 0; /* Reserved */
5875                 entry->edx = 0; /* Per default do not support any
5876                                    additional features */
5877
5878                 /* Support next_rip if host supports it */
5879                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5880                         entry->edx |= SVM_FEATURE_NRIP;
5881
5882                 /* Support NPT for the guest if enabled */
5883                 if (npt_enabled)
5884                         entry->edx |= SVM_FEATURE_NPT;
5885
5886                 break;
5887         case 0x8000001F:
5888                 /* Support memory encryption cpuid if host supports it */
5889                 if (boot_cpu_has(X86_FEATURE_SEV))
5890                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5891                                 &entry->ecx, &entry->edx);
5892
5893         }
5894 }
5895
5896 static int svm_get_lpage_level(void)
5897 {
5898         return PT_PDPE_LEVEL;
5899 }
5900
5901 static bool svm_rdtscp_supported(void)
5902 {
5903         return boot_cpu_has(X86_FEATURE_RDTSCP);
5904 }
5905
5906 static bool svm_invpcid_supported(void)
5907 {
5908         return false;
5909 }
5910
5911 static bool svm_mpx_supported(void)
5912 {
5913         return false;
5914 }
5915
5916 static bool svm_xsaves_supported(void)
5917 {
5918         return false;
5919 }
5920
5921 static bool svm_umip_emulated(void)
5922 {
5923         return false;
5924 }
5925
5926 static bool svm_has_wbinvd_exit(void)
5927 {
5928         return true;
5929 }
5930
5931 #define PRE_EX(exit)  { .exit_code = (exit), \
5932                         .stage = X86_ICPT_PRE_EXCEPT, }
5933 #define POST_EX(exit) { .exit_code = (exit), \
5934                         .stage = X86_ICPT_POST_EXCEPT, }
5935 #define POST_MEM(exit) { .exit_code = (exit), \
5936                         .stage = X86_ICPT_POST_MEMACCESS, }
5937
5938 static const struct __x86_intercept {
5939         u32 exit_code;
5940         enum x86_intercept_stage stage;
5941 } x86_intercept_map[] = {
5942         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5943         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5944         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5945         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5946         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5947         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5948         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5949         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5950         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5951         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5952         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5953         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5954         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5955         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5956         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5957         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5958         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5959         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5960         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5961         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5962         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5963         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5964         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5965         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5966         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5967         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5968         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5969         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5970         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5971         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5972         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5973         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5974         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5975         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5976         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5977         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5978         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5979         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5980         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5981         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5982         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5983         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5984         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5985         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5986         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5987         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5988 };
5989
5990 #undef PRE_EX
5991 #undef POST_EX
5992 #undef POST_MEM
5993
5994 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5995                                struct x86_instruction_info *info,
5996                                enum x86_intercept_stage stage)
5997 {
5998         struct vcpu_svm *svm = to_svm(vcpu);
5999         int vmexit, ret = X86EMUL_CONTINUE;
6000         struct __x86_intercept icpt_info;
6001         struct vmcb *vmcb = svm->vmcb;
6002
6003         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6004                 goto out;
6005
6006         icpt_info = x86_intercept_map[info->intercept];
6007
6008         if (stage != icpt_info.stage)
6009                 goto out;
6010
6011         switch (icpt_info.exit_code) {
6012         case SVM_EXIT_READ_CR0:
6013                 if (info->intercept == x86_intercept_cr_read)
6014                         icpt_info.exit_code += info->modrm_reg;
6015                 break;
6016         case SVM_EXIT_WRITE_CR0: {
6017                 unsigned long cr0, val;
6018                 u64 intercept;
6019
6020                 if (info->intercept == x86_intercept_cr_write)
6021                         icpt_info.exit_code += info->modrm_reg;
6022
6023                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6024                     info->intercept == x86_intercept_clts)
6025                         break;
6026
6027                 intercept = svm->nested.intercept;
6028
6029                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6030                         break;
6031
6032                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6033                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6034
6035                 if (info->intercept == x86_intercept_lmsw) {
6036                         cr0 &= 0xfUL;
6037                         val &= 0xfUL;
6038                         /* lmsw can't clear PE - catch this here */
6039                         if (cr0 & X86_CR0_PE)
6040                                 val |= X86_CR0_PE;
6041                 }
6042
6043                 if (cr0 ^ val)
6044                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6045
6046                 break;
6047         }
6048         case SVM_EXIT_READ_DR0:
6049         case SVM_EXIT_WRITE_DR0:
6050                 icpt_info.exit_code += info->modrm_reg;
6051                 break;
6052         case SVM_EXIT_MSR:
6053                 if (info->intercept == x86_intercept_wrmsr)
6054                         vmcb->control.exit_info_1 = 1;
6055                 else
6056                         vmcb->control.exit_info_1 = 0;
6057                 break;
6058         case SVM_EXIT_PAUSE:
6059                 /*
6060                  * We get this for NOP only, but pause
6061                  * is rep not, check this here
6062                  */
6063                 if (info->rep_prefix != REPE_PREFIX)
6064                         goto out;
6065                 break;
6066         case SVM_EXIT_IOIO: {
6067                 u64 exit_info;
6068                 u32 bytes;
6069
6070                 if (info->intercept == x86_intercept_in ||
6071                     info->intercept == x86_intercept_ins) {
6072                         exit_info = ((info->src_val & 0xffff) << 16) |
6073                                 SVM_IOIO_TYPE_MASK;
6074                         bytes = info->dst_bytes;
6075                 } else {
6076                         exit_info = (info->dst_val & 0xffff) << 16;
6077                         bytes = info->src_bytes;
6078                 }
6079
6080                 if (info->intercept == x86_intercept_outs ||
6081                     info->intercept == x86_intercept_ins)
6082                         exit_info |= SVM_IOIO_STR_MASK;
6083
6084                 if (info->rep_prefix)
6085                         exit_info |= SVM_IOIO_REP_MASK;
6086
6087                 bytes = min(bytes, 4u);
6088
6089                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6090
6091                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6092
6093                 vmcb->control.exit_info_1 = exit_info;
6094                 vmcb->control.exit_info_2 = info->next_rip;
6095
6096                 break;
6097         }
6098         default:
6099                 break;
6100         }
6101
6102         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6103         if (static_cpu_has(X86_FEATURE_NRIPS))
6104                 vmcb->control.next_rip  = info->next_rip;
6105         vmcb->control.exit_code = icpt_info.exit_code;
6106         vmexit = nested_svm_exit_handled(svm);
6107
6108         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6109                                            : X86EMUL_CONTINUE;
6110
6111 out:
6112         return ret;
6113 }
6114
6115 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6116 {
6117         local_irq_enable();
6118         /*
6119          * We must have an instruction with interrupts enabled, so
6120          * the timer interrupt isn't delayed by the interrupt shadow.
6121          */
6122         asm("nop");
6123         local_irq_disable();
6124 }
6125
6126 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6127 {
6128         if (pause_filter_thresh)
6129                 shrink_ple_window(vcpu);
6130 }
6131
6132 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6133 {
6134         if (avic_handle_apic_id_update(vcpu) != 0)
6135                 return;
6136         if (avic_handle_dfr_update(vcpu) != 0)
6137                 return;
6138         avic_handle_ldr_update(vcpu);
6139 }
6140
6141 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6142 {
6143         /* [63:9] are reserved. */
6144         vcpu->arch.mcg_cap &= 0x1ff;
6145 }
6146
6147 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6148 {
6149         struct vcpu_svm *svm = to_svm(vcpu);
6150
6151         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6152         if (!gif_set(svm))
6153                 return 0;
6154
6155         if (is_guest_mode(&svm->vcpu) &&
6156             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6157                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6158                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6159                 svm->nested.exit_required = true;
6160                 return 0;
6161         }
6162
6163         return 1;
6164 }
6165
6166 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6167 {
6168         struct vcpu_svm *svm = to_svm(vcpu);
6169         int ret;
6170
6171         if (is_guest_mode(vcpu)) {
6172                 /* FED8h - SVM Guest */
6173                 put_smstate(u64, smstate, 0x7ed8, 1);
6174                 /* FEE0h - SVM Guest VMCB Physical Address */
6175                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6176
6177                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6178                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6179                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6180
6181                 ret = nested_svm_vmexit(svm);
6182                 if (ret)
6183                         return ret;
6184         }
6185         return 0;
6186 }
6187
6188 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6189 {
6190         struct vcpu_svm *svm = to_svm(vcpu);
6191         struct vmcb *nested_vmcb;
6192         struct page *page;
6193         struct {
6194                 u64 guest;
6195                 u64 vmcb;
6196         } svm_state_save;
6197         int ret;
6198
6199         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6200                                   sizeof(svm_state_save));
6201         if (ret)
6202                 return ret;
6203
6204         if (svm_state_save.guest) {
6205                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6206                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6207                 if (nested_vmcb)
6208                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6209                 else
6210                         ret = 1;
6211                 vcpu->arch.hflags |= HF_SMM_MASK;
6212         }
6213         return ret;
6214 }
6215
6216 static int enable_smi_window(struct kvm_vcpu *vcpu)
6217 {
6218         struct vcpu_svm *svm = to_svm(vcpu);
6219
6220         if (!gif_set(svm)) {
6221                 if (vgif_enabled(svm))
6222                         set_intercept(svm, INTERCEPT_STGI);
6223                 /* STGI will cause a vm exit */
6224                 return 1;
6225         }
6226         return 0;
6227 }
6228
6229 static int sev_asid_new(void)
6230 {
6231         int pos;
6232
6233         /*
6234          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6235          */
6236         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6237         if (pos >= max_sev_asid)
6238                 return -EBUSY;
6239
6240         set_bit(pos, sev_asid_bitmap);
6241         return pos + 1;
6242 }
6243
6244 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6245 {
6246         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6247         int asid, ret;
6248
6249         ret = -EBUSY;
6250         asid = sev_asid_new();
6251         if (asid < 0)
6252                 return ret;
6253
6254         ret = sev_platform_init(&argp->error);
6255         if (ret)
6256                 goto e_free;
6257
6258         sev->active = true;
6259         sev->asid = asid;
6260         INIT_LIST_HEAD(&sev->regions_list);
6261
6262         return 0;
6263
6264 e_free:
6265         __sev_asid_free(asid);
6266         return ret;
6267 }
6268
6269 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6270 {
6271         struct sev_data_activate *data;
6272         int asid = sev_get_asid(kvm);
6273         int ret;
6274
6275         wbinvd_on_all_cpus();
6276
6277         ret = sev_guest_df_flush(error);
6278         if (ret)
6279                 return ret;
6280
6281         data = kzalloc(sizeof(*data), GFP_KERNEL);
6282         if (!data)
6283                 return -ENOMEM;
6284
6285         /* activate ASID on the given handle */
6286         data->handle = handle;
6287         data->asid   = asid;
6288         ret = sev_guest_activate(data, error);
6289         kfree(data);
6290
6291         return ret;
6292 }
6293
6294 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6295 {
6296         struct fd f;
6297         int ret;
6298
6299         f = fdget(fd);
6300         if (!f.file)
6301                 return -EBADF;
6302
6303         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6304
6305         fdput(f);
6306         return ret;
6307 }
6308
6309 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6310 {
6311         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6312
6313         return __sev_issue_cmd(sev->fd, id, data, error);
6314 }
6315
6316 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6317 {
6318         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6319         struct sev_data_launch_start *start;
6320         struct kvm_sev_launch_start params;
6321         void *dh_blob, *session_blob;
6322         int *error = &argp->error;
6323         int ret;
6324
6325         if (!sev_guest(kvm))
6326                 return -ENOTTY;
6327
6328         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6329                 return -EFAULT;
6330
6331         start = kzalloc(sizeof(*start), GFP_KERNEL);
6332         if (!start)
6333                 return -ENOMEM;
6334
6335         dh_blob = NULL;
6336         if (params.dh_uaddr) {
6337                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6338                 if (IS_ERR(dh_blob)) {
6339                         ret = PTR_ERR(dh_blob);
6340                         goto e_free;
6341                 }
6342
6343                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6344                 start->dh_cert_len = params.dh_len;
6345         }
6346
6347         session_blob = NULL;
6348         if (params.session_uaddr) {
6349                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6350                 if (IS_ERR(session_blob)) {
6351                         ret = PTR_ERR(session_blob);
6352                         goto e_free_dh;
6353                 }
6354
6355                 start->session_address = __sme_set(__pa(session_blob));
6356                 start->session_len = params.session_len;
6357         }
6358
6359         start->handle = params.handle;
6360         start->policy = params.policy;
6361
6362         /* create memory encryption context */
6363         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6364         if (ret)
6365                 goto e_free_session;
6366
6367         /* Bind ASID to this guest */
6368         ret = sev_bind_asid(kvm, start->handle, error);
6369         if (ret)
6370                 goto e_free_session;
6371
6372         /* return handle to userspace */
6373         params.handle = start->handle;
6374         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6375                 sev_unbind_asid(kvm, start->handle);
6376                 ret = -EFAULT;
6377                 goto e_free_session;
6378         }
6379
6380         sev->handle = start->handle;
6381         sev->fd = argp->sev_fd;
6382
6383 e_free_session:
6384         kfree(session_blob);
6385 e_free_dh:
6386         kfree(dh_blob);
6387 e_free:
6388         kfree(start);
6389         return ret;
6390 }
6391
6392 static int get_num_contig_pages(int idx, struct page **inpages,
6393                                 unsigned long npages)
6394 {
6395         unsigned long paddr, next_paddr;
6396         int i = idx + 1, pages = 1;
6397
6398         /* find the number of contiguous pages starting from idx */
6399         paddr = __sme_page_pa(inpages[idx]);
6400         while (i < npages) {
6401                 next_paddr = __sme_page_pa(inpages[i++]);
6402                 if ((paddr + PAGE_SIZE) == next_paddr) {
6403                         pages++;
6404                         paddr = next_paddr;
6405                         continue;
6406                 }
6407                 break;
6408         }
6409
6410         return pages;
6411 }
6412
6413 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6414 {
6415         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6416         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6417         struct kvm_sev_launch_update_data params;
6418         struct sev_data_launch_update_data *data;
6419         struct page **inpages;
6420         int i, ret, pages;
6421
6422         if (!sev_guest(kvm))
6423                 return -ENOTTY;
6424
6425         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6426                 return -EFAULT;
6427
6428         data = kzalloc(sizeof(*data), GFP_KERNEL);
6429         if (!data)
6430                 return -ENOMEM;
6431
6432         vaddr = params.uaddr;
6433         size = params.len;
6434         vaddr_end = vaddr + size;
6435
6436         /* Lock the user memory. */
6437         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6438         if (!inpages) {
6439                 ret = -ENOMEM;
6440                 goto e_free;
6441         }
6442
6443         /*
6444          * The LAUNCH_UPDATE command will perform in-place encryption of the
6445          * memory content (i.e it will write the same memory region with C=1).
6446          * It's possible that the cache may contain the data with C=0, i.e.,
6447          * unencrypted so invalidate it first.
6448          */
6449         sev_clflush_pages(inpages, npages);
6450
6451         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6452                 int offset, len;
6453
6454                 /*
6455                  * If the user buffer is not page-aligned, calculate the offset
6456                  * within the page.
6457                  */
6458                 offset = vaddr & (PAGE_SIZE - 1);
6459
6460                 /* Calculate the number of pages that can be encrypted in one go. */
6461                 pages = get_num_contig_pages(i, inpages, npages);
6462
6463                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6464
6465                 data->handle = sev->handle;
6466                 data->len = len;
6467                 data->address = __sme_page_pa(inpages[i]) + offset;
6468                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6469                 if (ret)
6470                         goto e_unpin;
6471
6472                 size -= len;
6473                 next_vaddr = vaddr + len;
6474         }
6475
6476 e_unpin:
6477         /* content of memory is updated, mark pages dirty */
6478         for (i = 0; i < npages; i++) {
6479                 set_page_dirty_lock(inpages[i]);
6480                 mark_page_accessed(inpages[i]);
6481         }
6482         /* unlock the user pages */
6483         sev_unpin_memory(kvm, inpages, npages);
6484 e_free:
6485         kfree(data);
6486         return ret;
6487 }
6488
6489 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6490 {
6491         void __user *measure = (void __user *)(uintptr_t)argp->data;
6492         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6493         struct sev_data_launch_measure *data;
6494         struct kvm_sev_launch_measure params;
6495         void __user *p = NULL;
6496         void *blob = NULL;
6497         int ret;
6498
6499         if (!sev_guest(kvm))
6500                 return -ENOTTY;
6501
6502         if (copy_from_user(&params, measure, sizeof(params)))
6503                 return -EFAULT;
6504
6505         data = kzalloc(sizeof(*data), GFP_KERNEL);
6506         if (!data)
6507                 return -ENOMEM;
6508
6509         /* User wants to query the blob length */
6510         if (!params.len)
6511                 goto cmd;
6512
6513         p = (void __user *)(uintptr_t)params.uaddr;
6514         if (p) {
6515                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6516                         ret = -EINVAL;
6517                         goto e_free;
6518                 }
6519
6520                 ret = -ENOMEM;
6521                 blob = kmalloc(params.len, GFP_KERNEL);
6522                 if (!blob)
6523                         goto e_free;
6524
6525                 data->address = __psp_pa(blob);
6526                 data->len = params.len;
6527         }
6528
6529 cmd:
6530         data->handle = sev->handle;
6531         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6532
6533         /*
6534          * If we query the session length, FW responded with expected data.
6535          */
6536         if (!params.len)
6537                 goto done;
6538
6539         if (ret)
6540                 goto e_free_blob;
6541
6542         if (blob) {
6543                 if (copy_to_user(p, blob, params.len))
6544                         ret = -EFAULT;
6545         }
6546
6547 done:
6548         params.len = data->len;
6549         if (copy_to_user(measure, &params, sizeof(params)))
6550                 ret = -EFAULT;
6551 e_free_blob:
6552         kfree(blob);
6553 e_free:
6554         kfree(data);
6555         return ret;
6556 }
6557
6558 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6559 {
6560         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6561         struct sev_data_launch_finish *data;
6562         int ret;
6563
6564         if (!sev_guest(kvm))
6565                 return -ENOTTY;
6566
6567         data = kzalloc(sizeof(*data), GFP_KERNEL);
6568         if (!data)
6569                 return -ENOMEM;
6570
6571         data->handle = sev->handle;
6572         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6573
6574         kfree(data);
6575         return ret;
6576 }
6577
6578 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6579 {
6580         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6581         struct kvm_sev_guest_status params;
6582         struct sev_data_guest_status *data;
6583         int ret;
6584
6585         if (!sev_guest(kvm))
6586                 return -ENOTTY;
6587
6588         data = kzalloc(sizeof(*data), GFP_KERNEL);
6589         if (!data)
6590                 return -ENOMEM;
6591
6592         data->handle = sev->handle;
6593         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6594         if (ret)
6595                 goto e_free;
6596
6597         params.policy = data->policy;
6598         params.state = data->state;
6599         params.handle = data->handle;
6600
6601         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6602                 ret = -EFAULT;
6603 e_free:
6604         kfree(data);
6605         return ret;
6606 }
6607
6608 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6609                                unsigned long dst, int size,
6610                                int *error, bool enc)
6611 {
6612         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6613         struct sev_data_dbg *data;
6614         int ret;
6615
6616         data = kzalloc(sizeof(*data), GFP_KERNEL);
6617         if (!data)
6618                 return -ENOMEM;
6619
6620         data->handle = sev->handle;
6621         data->dst_addr = dst;
6622         data->src_addr = src;
6623         data->len = size;
6624
6625         ret = sev_issue_cmd(kvm,
6626                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6627                             data, error);
6628         kfree(data);
6629         return ret;
6630 }
6631
6632 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6633                              unsigned long dst_paddr, int sz, int *err)
6634 {
6635         int offset;
6636
6637         /*
6638          * Its safe to read more than we are asked, caller should ensure that
6639          * destination has enough space.
6640          */
6641         src_paddr = round_down(src_paddr, 16);
6642         offset = src_paddr & 15;
6643         sz = round_up(sz + offset, 16);
6644
6645         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6646 }
6647
6648 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6649                                   unsigned long __user dst_uaddr,
6650                                   unsigned long dst_paddr,
6651                                   int size, int *err)
6652 {
6653         struct page *tpage = NULL;
6654         int ret, offset;
6655
6656         /* if inputs are not 16-byte then use intermediate buffer */
6657         if (!IS_ALIGNED(dst_paddr, 16) ||
6658             !IS_ALIGNED(paddr,     16) ||
6659             !IS_ALIGNED(size,      16)) {
6660                 tpage = (void *)alloc_page(GFP_KERNEL);
6661                 if (!tpage)
6662                         return -ENOMEM;
6663
6664                 dst_paddr = __sme_page_pa(tpage);
6665         }
6666
6667         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6668         if (ret)
6669                 goto e_free;
6670
6671         if (tpage) {
6672                 offset = paddr & 15;
6673                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6674                                  page_address(tpage) + offset, size))
6675                         ret = -EFAULT;
6676         }
6677
6678 e_free:
6679         if (tpage)
6680                 __free_page(tpage);
6681
6682         return ret;
6683 }
6684
6685 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6686                                   unsigned long __user vaddr,
6687                                   unsigned long dst_paddr,
6688                                   unsigned long __user dst_vaddr,
6689                                   int size, int *error)
6690 {
6691         struct page *src_tpage = NULL;
6692         struct page *dst_tpage = NULL;
6693         int ret, len = size;
6694
6695         /* If source buffer is not aligned then use an intermediate buffer */
6696         if (!IS_ALIGNED(vaddr, 16)) {
6697                 src_tpage = alloc_page(GFP_KERNEL);
6698                 if (!src_tpage)
6699                         return -ENOMEM;
6700
6701                 if (copy_from_user(page_address(src_tpage),
6702                                 (void __user *)(uintptr_t)vaddr, size)) {
6703                         __free_page(src_tpage);
6704                         return -EFAULT;
6705                 }
6706
6707                 paddr = __sme_page_pa(src_tpage);
6708         }
6709
6710         /*
6711          *  If destination buffer or length is not aligned then do read-modify-write:
6712          *   - decrypt destination in an intermediate buffer
6713          *   - copy the source buffer in an intermediate buffer
6714          *   - use the intermediate buffer as source buffer
6715          */
6716         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6717                 int dst_offset;
6718
6719                 dst_tpage = alloc_page(GFP_KERNEL);
6720                 if (!dst_tpage) {
6721                         ret = -ENOMEM;
6722                         goto e_free;
6723                 }
6724
6725                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6726                                         __sme_page_pa(dst_tpage), size, error);
6727                 if (ret)
6728                         goto e_free;
6729
6730                 /*
6731                  *  If source is kernel buffer then use memcpy() otherwise
6732                  *  copy_from_user().
6733                  */
6734                 dst_offset = dst_paddr & 15;
6735
6736                 if (src_tpage)
6737                         memcpy(page_address(dst_tpage) + dst_offset,
6738                                page_address(src_tpage), size);
6739                 else {
6740                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6741                                            (void __user *)(uintptr_t)vaddr, size)) {
6742                                 ret = -EFAULT;
6743                                 goto e_free;
6744                         }
6745                 }
6746
6747                 paddr = __sme_page_pa(dst_tpage);
6748                 dst_paddr = round_down(dst_paddr, 16);
6749                 len = round_up(size, 16);
6750         }
6751
6752         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6753
6754 e_free:
6755         if (src_tpage)
6756                 __free_page(src_tpage);
6757         if (dst_tpage)
6758                 __free_page(dst_tpage);
6759         return ret;
6760 }
6761
6762 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6763 {
6764         unsigned long vaddr, vaddr_end, next_vaddr;
6765         unsigned long dst_vaddr;
6766         struct page **src_p, **dst_p;
6767         struct kvm_sev_dbg debug;
6768         unsigned long n;
6769         int ret, size;
6770
6771         if (!sev_guest(kvm))
6772                 return -ENOTTY;
6773
6774         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6775                 return -EFAULT;
6776
6777         vaddr = debug.src_uaddr;
6778         size = debug.len;
6779         vaddr_end = vaddr + size;
6780         dst_vaddr = debug.dst_uaddr;
6781
6782         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6783                 int len, s_off, d_off;
6784
6785                 /* lock userspace source and destination page */
6786                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6787                 if (!src_p)
6788                         return -EFAULT;
6789
6790                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6791                 if (!dst_p) {
6792                         sev_unpin_memory(kvm, src_p, n);
6793                         return -EFAULT;
6794                 }
6795
6796                 /*
6797                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6798                  * memory content (i.e it will write the same memory region with C=1).
6799                  * It's possible that the cache may contain the data with C=0, i.e.,
6800                  * unencrypted so invalidate it first.
6801                  */
6802                 sev_clflush_pages(src_p, 1);
6803                 sev_clflush_pages(dst_p, 1);
6804
6805                 /*
6806                  * Since user buffer may not be page aligned, calculate the
6807                  * offset within the page.
6808                  */
6809                 s_off = vaddr & ~PAGE_MASK;
6810                 d_off = dst_vaddr & ~PAGE_MASK;
6811                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6812
6813                 if (dec)
6814                         ret = __sev_dbg_decrypt_user(kvm,
6815                                                      __sme_page_pa(src_p[0]) + s_off,
6816                                                      dst_vaddr,
6817                                                      __sme_page_pa(dst_p[0]) + d_off,
6818                                                      len, &argp->error);
6819                 else
6820                         ret = __sev_dbg_encrypt_user(kvm,
6821                                                      __sme_page_pa(src_p[0]) + s_off,
6822                                                      vaddr,
6823                                                      __sme_page_pa(dst_p[0]) + d_off,
6824                                                      dst_vaddr,
6825                                                      len, &argp->error);
6826
6827                 sev_unpin_memory(kvm, src_p, 1);
6828                 sev_unpin_memory(kvm, dst_p, 1);
6829
6830                 if (ret)
6831                         goto err;
6832
6833                 next_vaddr = vaddr + len;
6834                 dst_vaddr = dst_vaddr + len;
6835                 size -= len;
6836         }
6837 err:
6838         return ret;
6839 }
6840
6841 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6842 {
6843         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6844         struct sev_data_launch_secret *data;
6845         struct kvm_sev_launch_secret params;
6846         struct page **pages;
6847         void *blob, *hdr;
6848         unsigned long n;
6849         int ret, offset;
6850
6851         if (!sev_guest(kvm))
6852                 return -ENOTTY;
6853
6854         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6855                 return -EFAULT;
6856
6857         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6858         if (!pages)
6859                 return -ENOMEM;
6860
6861         /*
6862          * The secret must be copied into contiguous memory region, lets verify
6863          * that userspace memory pages are contiguous before we issue command.
6864          */
6865         if (get_num_contig_pages(0, pages, n) != n) {
6866                 ret = -EINVAL;
6867                 goto e_unpin_memory;
6868         }
6869
6870         ret = -ENOMEM;
6871         data = kzalloc(sizeof(*data), GFP_KERNEL);
6872         if (!data)
6873                 goto e_unpin_memory;
6874
6875         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6876         data->guest_address = __sme_page_pa(pages[0]) + offset;
6877         data->guest_len = params.guest_len;
6878
6879         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6880         if (IS_ERR(blob)) {
6881                 ret = PTR_ERR(blob);
6882                 goto e_free;
6883         }
6884
6885         data->trans_address = __psp_pa(blob);
6886         data->trans_len = params.trans_len;
6887
6888         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6889         if (IS_ERR(hdr)) {
6890                 ret = PTR_ERR(hdr);
6891                 goto e_free_blob;
6892         }
6893         data->hdr_address = __psp_pa(hdr);
6894         data->hdr_len = params.hdr_len;
6895
6896         data->handle = sev->handle;
6897         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6898
6899         kfree(hdr);
6900
6901 e_free_blob:
6902         kfree(blob);
6903 e_free:
6904         kfree(data);
6905 e_unpin_memory:
6906         sev_unpin_memory(kvm, pages, n);
6907         return ret;
6908 }
6909
6910 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6911 {
6912         struct kvm_sev_cmd sev_cmd;
6913         int r;
6914
6915         if (!svm_sev_enabled())
6916                 return -ENOTTY;
6917
6918         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6919                 return -EFAULT;
6920
6921         mutex_lock(&kvm->lock);
6922
6923         switch (sev_cmd.id) {
6924         case KVM_SEV_INIT:
6925                 r = sev_guest_init(kvm, &sev_cmd);
6926                 break;
6927         case KVM_SEV_LAUNCH_START:
6928                 r = sev_launch_start(kvm, &sev_cmd);
6929                 break;
6930         case KVM_SEV_LAUNCH_UPDATE_DATA:
6931                 r = sev_launch_update_data(kvm, &sev_cmd);
6932                 break;
6933         case KVM_SEV_LAUNCH_MEASURE:
6934                 r = sev_launch_measure(kvm, &sev_cmd);
6935                 break;
6936         case KVM_SEV_LAUNCH_FINISH:
6937                 r = sev_launch_finish(kvm, &sev_cmd);
6938                 break;
6939         case KVM_SEV_GUEST_STATUS:
6940                 r = sev_guest_status(kvm, &sev_cmd);
6941                 break;
6942         case KVM_SEV_DBG_DECRYPT:
6943                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6944                 break;
6945         case KVM_SEV_DBG_ENCRYPT:
6946                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6947                 break;
6948         case KVM_SEV_LAUNCH_SECRET:
6949                 r = sev_launch_secret(kvm, &sev_cmd);
6950                 break;
6951         default:
6952                 r = -EINVAL;
6953                 goto out;
6954         }
6955
6956         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6957                 r = -EFAULT;
6958
6959 out:
6960         mutex_unlock(&kvm->lock);
6961         return r;
6962 }
6963
6964 static int svm_register_enc_region(struct kvm *kvm,
6965                                    struct kvm_enc_region *range)
6966 {
6967         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6968         struct enc_region *region;
6969         int ret = 0;
6970
6971         if (!sev_guest(kvm))
6972                 return -ENOTTY;
6973
6974         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
6975                 return -EINVAL;
6976
6977         region = kzalloc(sizeof(*region), GFP_KERNEL);
6978         if (!region)
6979                 return -ENOMEM;
6980
6981         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
6982         if (!region->pages) {
6983                 ret = -ENOMEM;
6984                 goto e_free;
6985         }
6986
6987         /*
6988          * The guest may change the memory encryption attribute from C=0 -> C=1
6989          * or vice versa for this memory range. Lets make sure caches are
6990          * flushed to ensure that guest data gets written into memory with
6991          * correct C-bit.
6992          */
6993         sev_clflush_pages(region->pages, region->npages);
6994
6995         region->uaddr = range->addr;
6996         region->size = range->size;
6997
6998         mutex_lock(&kvm->lock);
6999         list_add_tail(&region->list, &sev->regions_list);
7000         mutex_unlock(&kvm->lock);
7001
7002         return ret;
7003
7004 e_free:
7005         kfree(region);
7006         return ret;
7007 }
7008
7009 static struct enc_region *
7010 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7011 {
7012         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7013         struct list_head *head = &sev->regions_list;
7014         struct enc_region *i;
7015
7016         list_for_each_entry(i, head, list) {
7017                 if (i->uaddr == range->addr &&
7018                     i->size == range->size)
7019                         return i;
7020         }
7021
7022         return NULL;
7023 }
7024
7025
7026 static int svm_unregister_enc_region(struct kvm *kvm,
7027                                      struct kvm_enc_region *range)
7028 {
7029         struct enc_region *region;
7030         int ret;
7031
7032         mutex_lock(&kvm->lock);
7033
7034         if (!sev_guest(kvm)) {
7035                 ret = -ENOTTY;
7036                 goto failed;
7037         }
7038
7039         region = find_enc_region(kvm, range);
7040         if (!region) {
7041                 ret = -EINVAL;
7042                 goto failed;
7043         }
7044
7045         __unregister_enc_region_locked(kvm, region);
7046
7047         mutex_unlock(&kvm->lock);
7048         return 0;
7049
7050 failed:
7051         mutex_unlock(&kvm->lock);
7052         return ret;
7053 }
7054
7055 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7056                                    uint16_t *vmcs_version)
7057 {
7058         /* Intel-only feature */
7059         return -ENODEV;
7060 }
7061
7062 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7063         .cpu_has_kvm_support = has_svm,
7064         .disabled_by_bios = is_disabled,
7065         .hardware_setup = svm_hardware_setup,
7066         .hardware_unsetup = svm_hardware_unsetup,
7067         .check_processor_compatibility = svm_check_processor_compat,
7068         .hardware_enable = svm_hardware_enable,
7069         .hardware_disable = svm_hardware_disable,
7070         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7071         .has_emulated_msr = svm_has_emulated_msr,
7072
7073         .vcpu_create = svm_create_vcpu,
7074         .vcpu_free = svm_free_vcpu,
7075         .vcpu_reset = svm_vcpu_reset,
7076
7077         .vm_alloc = svm_vm_alloc,
7078         .vm_free = svm_vm_free,
7079         .vm_init = avic_vm_init,
7080         .vm_destroy = svm_vm_destroy,
7081
7082         .prepare_guest_switch = svm_prepare_guest_switch,
7083         .vcpu_load = svm_vcpu_load,
7084         .vcpu_put = svm_vcpu_put,
7085         .vcpu_blocking = svm_vcpu_blocking,
7086         .vcpu_unblocking = svm_vcpu_unblocking,
7087
7088         .update_bp_intercept = update_bp_intercept,
7089         .get_msr_feature = svm_get_msr_feature,
7090         .get_msr = svm_get_msr,
7091         .set_msr = svm_set_msr,
7092         .get_segment_base = svm_get_segment_base,
7093         .get_segment = svm_get_segment,
7094         .set_segment = svm_set_segment,
7095         .get_cpl = svm_get_cpl,
7096         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7097         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7098         .decache_cr3 = svm_decache_cr3,
7099         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7100         .set_cr0 = svm_set_cr0,
7101         .set_cr3 = svm_set_cr3,
7102         .set_cr4 = svm_set_cr4,
7103         .set_efer = svm_set_efer,
7104         .get_idt = svm_get_idt,
7105         .set_idt = svm_set_idt,
7106         .get_gdt = svm_get_gdt,
7107         .set_gdt = svm_set_gdt,
7108         .get_dr6 = svm_get_dr6,
7109         .set_dr6 = svm_set_dr6,
7110         .set_dr7 = svm_set_dr7,
7111         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7112         .cache_reg = svm_cache_reg,
7113         .get_rflags = svm_get_rflags,
7114         .set_rflags = svm_set_rflags,
7115
7116         .tlb_flush = svm_flush_tlb,
7117         .tlb_flush_gva = svm_flush_tlb_gva,
7118
7119         .run = svm_vcpu_run,
7120         .handle_exit = handle_exit,
7121         .skip_emulated_instruction = skip_emulated_instruction,
7122         .set_interrupt_shadow = svm_set_interrupt_shadow,
7123         .get_interrupt_shadow = svm_get_interrupt_shadow,
7124         .patch_hypercall = svm_patch_hypercall,
7125         .set_irq = svm_set_irq,
7126         .set_nmi = svm_inject_nmi,
7127         .queue_exception = svm_queue_exception,
7128         .cancel_injection = svm_cancel_injection,
7129         .interrupt_allowed = svm_interrupt_allowed,
7130         .nmi_allowed = svm_nmi_allowed,
7131         .get_nmi_mask = svm_get_nmi_mask,
7132         .set_nmi_mask = svm_set_nmi_mask,
7133         .enable_nmi_window = enable_nmi_window,
7134         .enable_irq_window = enable_irq_window,
7135         .update_cr8_intercept = update_cr8_intercept,
7136         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7137         .get_enable_apicv = svm_get_enable_apicv,
7138         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7139         .load_eoi_exitmap = svm_load_eoi_exitmap,
7140         .hwapic_irr_update = svm_hwapic_irr_update,
7141         .hwapic_isr_update = svm_hwapic_isr_update,
7142         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7143         .apicv_post_state_restore = avic_post_state_restore,
7144
7145         .set_tss_addr = svm_set_tss_addr,
7146         .set_identity_map_addr = svm_set_identity_map_addr,
7147         .get_tdp_level = get_npt_level,
7148         .get_mt_mask = svm_get_mt_mask,
7149
7150         .get_exit_info = svm_get_exit_info,
7151
7152         .get_lpage_level = svm_get_lpage_level,
7153
7154         .cpuid_update = svm_cpuid_update,
7155
7156         .rdtscp_supported = svm_rdtscp_supported,
7157         .invpcid_supported = svm_invpcid_supported,
7158         .mpx_supported = svm_mpx_supported,
7159         .xsaves_supported = svm_xsaves_supported,
7160         .umip_emulated = svm_umip_emulated,
7161
7162         .set_supported_cpuid = svm_set_supported_cpuid,
7163
7164         .has_wbinvd_exit = svm_has_wbinvd_exit,
7165
7166         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7167         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7168
7169         .set_tdp_cr3 = set_tdp_cr3,
7170
7171         .check_intercept = svm_check_intercept,
7172         .handle_external_intr = svm_handle_external_intr,
7173
7174         .request_immediate_exit = __kvm_request_immediate_exit,
7175
7176         .sched_in = svm_sched_in,
7177
7178         .pmu_ops = &amd_pmu_ops,
7179         .deliver_posted_interrupt = svm_deliver_avic_intr,
7180         .update_pi_irte = svm_update_pi_irte,
7181         .setup_mce = svm_setup_mce,
7182
7183         .smi_allowed = svm_smi_allowed,
7184         .pre_enter_smm = svm_pre_enter_smm,
7185         .pre_leave_smm = svm_pre_leave_smm,
7186         .enable_smi_window = enable_smi_window,
7187
7188         .mem_enc_op = svm_mem_enc_op,
7189         .mem_enc_reg_region = svm_register_enc_region,
7190         .mem_enc_unreg_region = svm_unregister_enc_region,
7191
7192         .nested_enable_evmcs = nested_enable_evmcs,
7193 };
7194
7195 static int __init svm_init(void)
7196 {
7197         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7198                         __alignof__(struct vcpu_svm), THIS_MODULE);
7199 }
7200
7201 static void __exit svm_exit(void)
7202 {
7203         kvm_exit();
7204 }
7205
7206 module_init(svm_init)
7207 module_exit(svm_exit)