arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40
  41 #include <asm/apic.h>
  42 #include <asm/perf_event.h>
  43 #include <asm/tlbflush.h>
  44 #include <asm/desc.h>
  45 #include <asm/debugreg.h>
  46 #include <asm/kvm_para.h>
  47 #include <asm/irq_remapping.h>
  48
  49 #include <asm/virtext.h>
  50 #include "trace.h"
  51
  52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  53
  54 MODULE_AUTHOR("Qumranet");
  55 MODULE_LICENSE("GPL");
  56
  57 static const struct x86_cpu_id svm_cpu_id[] = {
  58         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  59         {}
  60 };
  61 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  62
  63 #define IOPM_ALLOC_ORDER 2
  64 #define MSRPM_ALLOC_ORDER 1
  65
  66 #define SEG_TYPE_LDT 2
  67 #define SEG_TYPE_BUSY_TSS16 3
  68
  69 #define SVM_FEATURE_NPT            (1 <<  0)
  70 #define SVM_FEATURE_LBRV           (1 <<  1)
  71 #define SVM_FEATURE_SVML           (1 <<  2)
  72 #define SVM_FEATURE_NRIP           (1 <<  3)
  73 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  74 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  75 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  76 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  77 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  78
  79 #define SVM_AVIC_DOORBELL       0xc001011b
  80
  81 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  82 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  83 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  84
  85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  86
  87 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  88 #define TSC_RATIO_MIN           0x0000000000000001ULL
  89 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  90
  91 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  92
  93 /*
  94  * 0xff is broadcast, so the max index allowed for physical APIC ID
  95  * table is 0xfe.  APIC IDs above 0xff are reserved.
  96  */
  97 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  98
  99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 102
 103 /* AVIC GATAG is encoded using VM and VCPU IDs */
 104 #define AVIC_VCPU_ID_BITS               8
 105 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 106
 107 #define AVIC_VM_ID_BITS                 24
 108 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 109 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 110
 111 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 112                                                 (y & AVIC_VCPU_ID_MASK))
 113 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 114 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 115
 116 static bool erratum_383_found __read_mostly;
 117
 118 static const u32 host_save_user_msrs[] = {
 119 #ifdef CONFIG_X86_64
 120         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 121         MSR_FS_BASE,
 122 #endif
 123         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 124         MSR_TSC_AUX,
 125 };
 126
 127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 128
 129 struct kvm_vcpu;
 130
 131 struct nested_state {
 132         struct vmcb *hsave;
 133         u64 hsave_msr;
 134         u64 vm_cr_msr;
 135         u64 vmcb;
 136
 137         /* These are the merged vectors */
 138         u32 *msrpm;
 139
 140         /* gpa pointers to the real vectors */
 141         u64 vmcb_msrpm;
 142         u64 vmcb_iopm;
 143
 144         /* A VMEXIT is required but not yet emulated */
 145         bool exit_required;
 146
 147         /* cache for intercepts of the guest */
 148         u32 intercept_cr;
 149         u32 intercept_dr;
 150         u32 intercept_exceptions;
 151         u64 intercept;
 152
 153         /* Nested Paging related state */
 154         u64 nested_cr3;
 155 };
 156
 157 #define MSRPM_OFFSETS   16
 158 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 159
 160 /*
 161  * Set osvw_len to higher value when updated Revision Guides
 162  * are published and we know what the new status bits are
 163  */
 164 static uint64_t osvw_len = 4, osvw_status;
 165
 166 struct vcpu_svm {
 167         struct kvm_vcpu vcpu;
 168         struct vmcb *vmcb;
 169         unsigned long vmcb_pa;
 170         struct svm_cpu_data *svm_data;
 171         uint64_t asid_generation;
 172         uint64_t sysenter_esp;
 173         uint64_t sysenter_eip;
 174         uint64_t tsc_aux;
 175
 176         u64 next_rip;
 177
 178         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 179         struct {
 180                 u16 fs;
 181                 u16 gs;
 182                 u16 ldt;
 183                 u64 gs_base;
 184         } host;
 185
 186         u32 *msrpm;
 187
 188         ulong nmi_iret_rip;
 189
 190         struct nested_state nested;
 191
 192         bool nmi_singlestep;
 193         u64 nmi_singlestep_guest_rflags;
 194
 195         unsigned int3_injected;
 196         unsigned long int3_rip;
 197         u32 apf_reason;
 198
 199         /* cached guest cpuid flags for faster access */
 200         bool nrips_enabled      : 1;
 201
 202         u32 ldr_reg;
 203         struct page *avic_backing_page;
 204         u64 *avic_physical_id_cache;
 205         bool avic_is_running;
 206
 207         /*
 208          * Per-vcpu list of struct amd_svm_iommu_ir:
 209          * This is used mainly to store interrupt remapping information used
 210          * when update the vcpu affinity. This avoids the need to scan for
 211          * IRTE and try to match ga_tag in the IOMMU driver.
 212          */
 213         struct list_head ir_list;
 214         spinlock_t ir_list_lock;
 215 };
 216
 217 /*
 218  * This is a wrapper of struct amd_iommu_ir_data.
 219  */
 220 struct amd_svm_iommu_ir {
 221         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 222         void *data;             /* Storing pointer to struct amd_ir_data */
 223 };
 224
 225 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 226 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 227
 228 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 229 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 230 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 231 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 232
 233 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 234 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 235
 236 #define MSR_INVALID                     0xffffffffU
 237
 238 static const struct svm_direct_access_msrs {
 239         u32 index;   /* Index of the MSR */
 240         bool always; /* True if intercept is always on */
 241 } direct_access_msrs[] = {
 242         { .index = MSR_STAR,                            .always = true  },
 243         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 244 #ifdef CONFIG_X86_64
 245         { .index = MSR_GS_BASE,                         .always = true  },
 246         { .index = MSR_FS_BASE,                         .always = true  },
 247         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 248         { .index = MSR_LSTAR,                           .always = true  },
 249         { .index = MSR_CSTAR,                           .always = true  },
 250         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 251 #endif
 252         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 253         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 254         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 255         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 256         { .index = MSR_INVALID,                         .always = false },
 257 };
 258
 259 /* enable NPT for AMD64 and X86 with PAE */
 260 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 261 static bool npt_enabled = true;
 262 #else
 263 static bool npt_enabled;
 264 #endif
 265
 266 /* allow nested paging (virtualized MMU) for all guests */
 267 static int npt = true;
 268 module_param(npt, int, S_IRUGO);
 269
 270 /* allow nested virtualization in KVM/SVM */
 271 static int nested = true;
 272 module_param(nested, int, S_IRUGO);
 273
 274 /* enable / disable AVIC */
 275 static int avic;
 276 #ifdef CONFIG_X86_LOCAL_APIC
 277 module_param(avic, int, S_IRUGO);
 278 #endif
 279
 280 /* AVIC VM ID bit masks and lock */
 281 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
 282 static DEFINE_SPINLOCK(avic_vm_id_lock);
 283
 284 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 285 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 286 static void svm_complete_interrupts(struct vcpu_svm *svm);
 287
 288 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 289 static int nested_svm_intercept(struct vcpu_svm *svm);
 290 static int nested_svm_vmexit(struct vcpu_svm *svm);
 291 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 292                                       bool has_error_code, u32 error_code);
 293
 294 enum {
 295         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 296                             pause filter count */
 297         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 298         VMCB_ASID,       /* ASID */
 299         VMCB_INTR,       /* int_ctl, int_vector */
 300         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 301         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 302         VMCB_DR,         /* DR6, DR7 */
 303         VMCB_DT,         /* GDT, IDT */
 304         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 305         VMCB_CR2,        /* CR2 only */
 306         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 307         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 308                           * AVIC PHYSICAL_TABLE pointer,
 309                           * AVIC LOGICAL_TABLE pointer
 310                           */
 311         VMCB_DIRTY_MAX,
 312 };
 313
 314 /* TPR and CR2 are always written before VMRUN */
 315 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 316
 317 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 318
 319 static inline void mark_all_dirty(struct vmcb *vmcb)
 320 {
 321         vmcb->control.clean = 0;
 322 }
 323
 324 static inline void mark_all_clean(struct vmcb *vmcb)
 325 {
 326         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 327                                & ~VMCB_ALWAYS_DIRTY_MASK;
 328 }
 329
 330 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 331 {
 332         vmcb->control.clean &= ~(1 << bit);
 333 }
 334
 335 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 336 {
 337         return container_of(vcpu, struct vcpu_svm, vcpu);
 338 }
 339
 340 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 341 {
 342         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 343         mark_dirty(svm->vmcb, VMCB_AVIC);
 344 }
 345
 346 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 347 {
 348         struct vcpu_svm *svm = to_svm(vcpu);
 349         u64 *entry = svm->avic_physical_id_cache;
 350
 351         if (!entry)
 352                 return false;
 353
 354         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 355 }
 356
 357 static void recalc_intercepts(struct vcpu_svm *svm)
 358 {
 359         struct vmcb_control_area *c, *h;
 360         struct nested_state *g;
 361
 362         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 363
 364         if (!is_guest_mode(&svm->vcpu))
 365                 return;
 366
 367         c = &svm->vmcb->control;
 368         h = &svm->nested.hsave->control;
 369         g = &svm->nested;
 370
 371         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 372         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 373         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 374         c->intercept = h->intercept | g->intercept;
 375 }
 376
 377 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 378 {
 379         if (is_guest_mode(&svm->vcpu))
 380                 return svm->nested.hsave;
 381         else
 382                 return svm->vmcb;
 383 }
 384
 385 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 386 {
 387         struct vmcb *vmcb = get_host_vmcb(svm);
 388
 389         vmcb->control.intercept_cr |= (1U << bit);
 390
 391         recalc_intercepts(svm);
 392 }
 393
 394 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 395 {
 396         struct vmcb *vmcb = get_host_vmcb(svm);
 397
 398         vmcb->control.intercept_cr &= ~(1U << bit);
 399
 400         recalc_intercepts(svm);
 401 }
 402
 403 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 404 {
 405         struct vmcb *vmcb = get_host_vmcb(svm);
 406
 407         return vmcb->control.intercept_cr & (1U << bit);
 408 }
 409
 410 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 411 {
 412         struct vmcb *vmcb = get_host_vmcb(svm);
 413
 414         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 415                 | (1 << INTERCEPT_DR1_READ)
 416                 | (1 << INTERCEPT_DR2_READ)
 417                 | (1 << INTERCEPT_DR3_READ)
 418                 | (1 << INTERCEPT_DR4_READ)
 419                 | (1 << INTERCEPT_DR5_READ)
 420                 | (1 << INTERCEPT_DR6_READ)
 421                 | (1 << INTERCEPT_DR7_READ)
 422                 | (1 << INTERCEPT_DR0_WRITE)
 423                 | (1 << INTERCEPT_DR1_WRITE)
 424                 | (1 << INTERCEPT_DR2_WRITE)
 425                 | (1 << INTERCEPT_DR3_WRITE)
 426                 | (1 << INTERCEPT_DR4_WRITE)
 427                 | (1 << INTERCEPT_DR5_WRITE)
 428                 | (1 << INTERCEPT_DR6_WRITE)
 429                 | (1 << INTERCEPT_DR7_WRITE);
 430
 431         recalc_intercepts(svm);
 432 }
 433
 434 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 435 {
 436         struct vmcb *vmcb = get_host_vmcb(svm);
 437
 438         vmcb->control.intercept_dr = 0;
 439
 440         recalc_intercepts(svm);
 441 }
 442
 443 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 444 {
 445         struct vmcb *vmcb = get_host_vmcb(svm);
 446
 447         vmcb->control.intercept_exceptions |= (1U << bit);
 448
 449         recalc_intercepts(svm);
 450 }
 451
 452 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 453 {
 454         struct vmcb *vmcb = get_host_vmcb(svm);
 455
 456         vmcb->control.intercept_exceptions &= ~(1U << bit);
 457
 458         recalc_intercepts(svm);
 459 }
 460
 461 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 462 {
 463         struct vmcb *vmcb = get_host_vmcb(svm);
 464
 465         vmcb->control.intercept |= (1ULL << bit);
 466
 467         recalc_intercepts(svm);
 468 }
 469
 470 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 471 {
 472         struct vmcb *vmcb = get_host_vmcb(svm);
 473
 474         vmcb->control.intercept &= ~(1ULL << bit);
 475
 476         recalc_intercepts(svm);
 477 }
 478
 479 static inline void enable_gif(struct vcpu_svm *svm)
 480 {
 481         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 482 }
 483
 484 static inline void disable_gif(struct vcpu_svm *svm)
 485 {
 486         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 487 }
 488
 489 static inline bool gif_set(struct vcpu_svm *svm)
 490 {
 491         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 492 }
 493
 494 static unsigned long iopm_base;
 495
 496 struct kvm_ldttss_desc {
 497         u16 limit0;
 498         u16 base0;
 499         unsigned base1:8, type:5, dpl:2, p:1;
 500         unsigned limit1:4, zero0:3, g:1, base2:8;
 501         u32 base3;
 502         u32 zero1;
 503 } __attribute__((packed));
 504
 505 struct svm_cpu_data {
 506         int cpu;
 507
 508         u64 asid_generation;
 509         u32 max_asid;
 510         u32 next_asid;
 511         struct kvm_ldttss_desc *tss_desc;
 512
 513         struct page *save_area;
 514 };
 515
 516 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 517
 518 struct svm_init_data {
 519         int cpu;
 520         int r;
 521 };
 522
 523 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 524
 525 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 526 #define MSRS_RANGE_SIZE 2048
 527 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 528
 529 static u32 svm_msrpm_offset(u32 msr)
 530 {
 531         u32 offset;
 532         int i;
 533
 534         for (i = 0; i < NUM_MSR_MAPS; i++) {
 535                 if (msr < msrpm_ranges[i] ||
 536                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 537                         continue;
 538
 539                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 540                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 541
 542                 /* Now we have the u8 offset - but need the u32 offset */
 543                 return offset / 4;
 544         }
 545
 546         /* MSR not in any range */
 547         return MSR_INVALID;
 548 }
 549
 550 #define MAX_INST_SIZE 15
 551
 552 static inline void clgi(void)
 553 {
 554         asm volatile (__ex(SVM_CLGI));
 555 }
 556
 557 static inline void stgi(void)
 558 {
 559         asm volatile (__ex(SVM_STGI));
 560 }
 561
 562 static inline void invlpga(unsigned long addr, u32 asid)
 563 {
 564         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 565 }
 566
 567 static int get_npt_level(void)
 568 {
 569 #ifdef CONFIG_X86_64
 570         return PT64_ROOT_LEVEL;
 571 #else
 572         return PT32E_ROOT_LEVEL;
 573 #endif
 574 }
 575
 576 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 577 {
 578         vcpu->arch.efer = efer;
 579         if (!npt_enabled && !(efer & EFER_LMA))
 580                 efer &= ~EFER_LME;
 581
 582         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 583         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 584 }
 585
 586 static int is_external_interrupt(u32 info)
 587 {
 588         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 589         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 590 }
 591
 592 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 593 {
 594         struct vcpu_svm *svm = to_svm(vcpu);
 595         u32 ret = 0;
 596
 597         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 598                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 599         return ret;
 600 }
 601
 602 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 603 {
 604         struct vcpu_svm *svm = to_svm(vcpu);
 605
 606         if (mask == 0)
 607                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 608         else
 609                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 610
 611 }
 612
 613 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 614 {
 615         struct vcpu_svm *svm = to_svm(vcpu);
 616
 617         if (svm->vmcb->control.next_rip != 0) {
 618                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 619                 svm->next_rip = svm->vmcb->control.next_rip;
 620         }
 621
 622         if (!svm->next_rip) {
 623                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 624                                 EMULATE_DONE)
 625                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 626                 return;
 627         }
 628         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 629                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 630                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 631
 632         kvm_rip_write(vcpu, svm->next_rip);
 633         svm_set_interrupt_shadow(vcpu, 0);
 634 }
 635
 636 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 637                                 bool has_error_code, u32 error_code,
 638                                 bool reinject)
 639 {
 640         struct vcpu_svm *svm = to_svm(vcpu);
 641
 642         /*
 643          * If we are within a nested VM we'd better #VMEXIT and let the guest
 644          * handle the exception
 645          */
 646         if (!reinject &&
 647             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 648                 return;
 649
 650         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 651                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 652
 653                 /*
 654                  * For guest debugging where we have to reinject #BP if some
 655                  * INT3 is guest-owned:
 656                  * Emulate nRIP by moving RIP forward. Will fail if injection
 657                  * raises a fault that is not intercepted. Still better than
 658                  * failing in all cases.
 659                  */
 660                 skip_emulated_instruction(&svm->vcpu);
 661                 rip = kvm_rip_read(&svm->vcpu);
 662                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 663                 svm->int3_injected = rip - old_rip;
 664         }
 665
 666         svm->vmcb->control.event_inj = nr
 667                 | SVM_EVTINJ_VALID
 668                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 669                 | SVM_EVTINJ_TYPE_EXEPT;
 670         svm->vmcb->control.event_inj_err = error_code;
 671 }
 672
 673 static void svm_init_erratum_383(void)
 674 {
 675         u32 low, high;
 676         int err;
 677         u64 val;
 678
 679         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 680                 return;
 681
 682         /* Use _safe variants to not break nested virtualization */
 683         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 684         if (err)
 685                 return;
 686
 687         val |= (1ULL << 47);
 688
 689         low  = lower_32_bits(val);
 690         high = upper_32_bits(val);
 691
 692         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 693
 694         erratum_383_found = true;
 695 }
 696
 697 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 698 {
 699         /*
 700          * Guests should see errata 400 and 415 as fixed (assuming that
 701          * HLT and IO instructions are intercepted).
 702          */
 703         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 704         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 705
 706         /*
 707          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 708          * all osvw.status bits inside that length, including bit 0 (which is
 709          * reserved for erratum 298), are valid. However, if host processor's
 710          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 711          * be conservative here and therefore we tell the guest that erratum 298
 712          * is present (because we really don't know).
 713          */
 714         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 715                 vcpu->arch.osvw.status |= 1;
 716 }
 717
 718 static int has_svm(void)
 719 {
 720         const char *msg;
 721
 722         if (!cpu_has_svm(&msg)) {
 723                 printk(KERN_INFO "has_svm: %s\n", msg);
 724                 return 0;
 725         }
 726
 727         return 1;
 728 }
 729
 730 static void svm_hardware_disable(void)
 731 {
 732         /* Make sure we clean up behind us */
 733         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 734                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 735
 736         cpu_svm_disable();
 737
 738         amd_pmu_disable_virt();
 739 }
 740
 741 static int svm_hardware_enable(void)
 742 {
 743
 744         struct svm_cpu_data *sd;
 745         uint64_t efer;
 746         struct desc_struct *gdt;
 747         int me = raw_smp_processor_id();
 748
 749         rdmsrl(MSR_EFER, efer);
 750         if (efer & EFER_SVME)
 751                 return -EBUSY;
 752
 753         if (!has_svm()) {
 754                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 755                 return -EINVAL;
 756         }
 757         sd = per_cpu(svm_data, me);
 758         if (!sd) {
 759                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 760                 return -EINVAL;
 761         }
 762
 763         sd->asid_generation = 1;
 764         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 765         sd->next_asid = sd->max_asid + 1;
 766
 767         gdt = get_current_gdt_rw();
 768         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 769
 770         wrmsrl(MSR_EFER, efer | EFER_SVME);
 771
 772         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 773
 774         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 775                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 776                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 777         }
 778
 779
 780         /*
 781          * Get OSVW bits.
 782          *
 783          * Note that it is possible to have a system with mixed processor
 784          * revisions and therefore different OSVW bits. If bits are not the same
 785          * on different processors then choose the worst case (i.e. if erratum
 786          * is present on one processor and not on another then assume that the
 787          * erratum is present everywhere).
 788          */
 789         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 790                 uint64_t len, status = 0;
 791                 int err;
 792
 793                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 794                 if (!err)
 795                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 796                                                       &err);
 797
 798                 if (err)
 799                         osvw_status = osvw_len = 0;
 800                 else {
 801                         if (len < osvw_len)
 802                                 osvw_len = len;
 803                         osvw_status |= status;
 804                         osvw_status &= (1ULL << osvw_len) - 1;
 805                 }
 806         } else
 807                 osvw_status = osvw_len = 0;
 808
 809         svm_init_erratum_383();
 810
 811         amd_pmu_enable_virt();
 812
 813         return 0;
 814 }
 815
 816 static void svm_cpu_uninit(int cpu)
 817 {
 818         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 819
 820         if (!sd)
 821                 return;
 822
 823         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 824         __free_page(sd->save_area);
 825         kfree(sd);
 826 }
 827
 828 static int svm_cpu_init(int cpu)
 829 {
 830         struct svm_cpu_data *sd;
 831         int r;
 832
 833         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 834         if (!sd)
 835                 return -ENOMEM;
 836         sd->cpu = cpu;
 837         sd->save_area = alloc_page(GFP_KERNEL);
 838         r = -ENOMEM;
 839         if (!sd->save_area)
 840                 goto err_1;
 841
 842         per_cpu(svm_data, cpu) = sd;
 843
 844         return 0;
 845
 846 err_1:
 847         kfree(sd);
 848         return r;
 849
 850 }
 851
 852 static bool valid_msr_intercept(u32 index)
 853 {
 854         int i;
 855
 856         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 857                 if (direct_access_msrs[i].index == index)
 858                         return true;
 859
 860         return false;
 861 }
 862
 863 static void set_msr_interception(u32 *msrpm, unsigned msr,
 864                                  int read, int write)
 865 {
 866         u8 bit_read, bit_write;
 867         unsigned long tmp;
 868         u32 offset;
 869
 870         /*
 871          * If this warning triggers extend the direct_access_msrs list at the
 872          * beginning of the file
 873          */
 874         WARN_ON(!valid_msr_intercept(msr));
 875
 876         offset    = svm_msrpm_offset(msr);
 877         bit_read  = 2 * (msr & 0x0f);
 878         bit_write = 2 * (msr & 0x0f) + 1;
 879         tmp       = msrpm[offset];
 880
 881         BUG_ON(offset == MSR_INVALID);
 882
 883         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 884         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 885
 886         msrpm[offset] = tmp;
 887 }
 888
 889 static void svm_vcpu_init_msrpm(u32 *msrpm)
 890 {
 891         int i;
 892
 893         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 894
 895         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 896                 if (!direct_access_msrs[i].always)
 897                         continue;
 898
 899                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 900         }
 901 }
 902
 903 static void add_msr_offset(u32 offset)
 904 {
 905         int i;
 906
 907         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 908
 909                 /* Offset already in list? */
 910                 if (msrpm_offsets[i] == offset)
 911                         return;
 912
 913                 /* Slot used by another offset? */
 914                 if (msrpm_offsets[i] != MSR_INVALID)
 915                         continue;
 916
 917                 /* Add offset to list */
 918                 msrpm_offsets[i] = offset;
 919
 920                 return;
 921         }
 922
 923         /*
 924          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 925          * increase MSRPM_OFFSETS in this case.
 926          */
 927         BUG();
 928 }
 929
 930 static void init_msrpm_offsets(void)
 931 {
 932         int i;
 933
 934         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 935
 936         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 937                 u32 offset;
 938
 939                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 940                 BUG_ON(offset == MSR_INVALID);
 941
 942                 add_msr_offset(offset);
 943         }
 944 }
 945
 946 static void svm_enable_lbrv(struct vcpu_svm *svm)
 947 {
 948         u32 *msrpm = svm->msrpm;
 949
 950         svm->vmcb->control.lbr_ctl = 1;
 951         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 952         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 953         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 954         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 955 }
 956
 957 static void svm_disable_lbrv(struct vcpu_svm *svm)
 958 {
 959         u32 *msrpm = svm->msrpm;
 960
 961         svm->vmcb->control.lbr_ctl = 0;
 962         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 963         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 964         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 965         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 966 }
 967
 968 static void disable_nmi_singlestep(struct vcpu_svm *svm)
 969 {
 970         svm->nmi_singlestep = false;
 971         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 972                 /* Clear our flags if they were not set by the guest */
 973                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 974                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 975                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 976                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 977         }
 978 }
 979
 980 /* Note:
 981  * This hash table is used to map VM_ID to a struct kvm_arch,
 982  * when handling AMD IOMMU GALOG notification to schedule in
 983  * a particular vCPU.
 984  */
 985 #define SVM_VM_DATA_HASH_BITS   8
 986 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
 987 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
 988
 989 /* Note:
 990  * This function is called from IOMMU driver to notify
 991  * SVM to schedule in a particular vCPU of a particular VM.
 992  */
 993 static int avic_ga_log_notifier(u32 ga_tag)
 994 {
 995         unsigned long flags;
 996         struct kvm_arch *ka = NULL;
 997         struct kvm_vcpu *vcpu = NULL;
 998         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
 999         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1000
1001         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1002
1003         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1004         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1005                 struct kvm *kvm = container_of(ka, struct kvm, arch);
1006                 struct kvm_arch *vm_data = &kvm->arch;
1007
1008                 if (vm_data->avic_vm_id != vm_id)
1009                         continue;
1010                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1011                 break;
1012         }
1013         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1014
1015         if (!vcpu)
1016                 return 0;
1017
1018         /* Note:
1019          * At this point, the IOMMU should have already set the pending
1020          * bit in the vAPIC backing page. So, we just need to schedule
1021          * in the vcpu.
1022          */
1023         if (vcpu->mode == OUTSIDE_GUEST_MODE)
1024                 kvm_vcpu_wake_up(vcpu);
1025
1026         return 0;
1027 }
1028
1029 static __init int svm_hardware_setup(void)
1030 {
1031         int cpu;
1032         struct page *iopm_pages;
1033         void *iopm_va;
1034         int r;
1035
1036         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1037
1038         if (!iopm_pages)
1039                 return -ENOMEM;
1040
1041         iopm_va = page_address(iopm_pages);
1042         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1043         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1044
1045         init_msrpm_offsets();
1046
1047         if (boot_cpu_has(X86_FEATURE_NX))
1048                 kvm_enable_efer_bits(EFER_NX);
1049
1050         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1051                 kvm_enable_efer_bits(EFER_FFXSR);
1052
1053         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1054                 kvm_has_tsc_control = true;
1055                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1056                 kvm_tsc_scaling_ratio_frac_bits = 32;
1057         }
1058
1059         if (nested) {
1060                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1061                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1062         }
1063
1064         for_each_possible_cpu(cpu) {
1065                 r = svm_cpu_init(cpu);
1066                 if (r)
1067                         goto err;
1068         }
1069
1070         if (!boot_cpu_has(X86_FEATURE_NPT))
1071                 npt_enabled = false;
1072
1073         if (npt_enabled && !npt) {
1074                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1075                 npt_enabled = false;
1076         }
1077
1078         if (npt_enabled) {
1079                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1080                 kvm_enable_tdp();
1081         } else
1082                 kvm_disable_tdp();
1083
1084         if (avic) {
1085                 if (!npt_enabled ||
1086                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1087                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1088                         avic = false;
1089                 } else {
1090                         pr_info("AVIC enabled\n");
1091
1092                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1093                 }
1094         }
1095
1096         return 0;
1097
1098 err:
1099         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1100         iopm_base = 0;
1101         return r;
1102 }
1103
1104 static __exit void svm_hardware_unsetup(void)
1105 {
1106         int cpu;
1107
1108         for_each_possible_cpu(cpu)
1109                 svm_cpu_uninit(cpu);
1110
1111         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1112         iopm_base = 0;
1113 }
1114
1115 static void init_seg(struct vmcb_seg *seg)
1116 {
1117         seg->selector = 0;
1118         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1119                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1120         seg->limit = 0xffff;
1121         seg->base = 0;
1122 }
1123
1124 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1125 {
1126         seg->selector = 0;
1127         seg->attrib = SVM_SELECTOR_P_MASK | type;
1128         seg->limit = 0xffff;
1129         seg->base = 0;
1130 }
1131
1132 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1133 {
1134         struct vcpu_svm *svm = to_svm(vcpu);
1135         u64 g_tsc_offset = 0;
1136
1137         if (is_guest_mode(vcpu)) {
1138                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1139                                svm->nested.hsave->control.tsc_offset;
1140                 svm->nested.hsave->control.tsc_offset = offset;
1141         } else
1142                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1143                                            svm->vmcb->control.tsc_offset,
1144                                            offset);
1145
1146         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1147
1148         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1149 }
1150
1151 static void avic_init_vmcb(struct vcpu_svm *svm)
1152 {
1153         struct vmcb *vmcb = svm->vmcb;
1154         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1155         phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1156         phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1157         phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1158
1159         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1160         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1161         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1162         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1163         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1164         svm->vcpu.arch.apicv_active = true;
1165 }
1166
1167 static void init_vmcb(struct vcpu_svm *svm)
1168 {
1169         struct vmcb_control_area *control = &svm->vmcb->control;
1170         struct vmcb_save_area *save = &svm->vmcb->save;
1171
1172         svm->vcpu.arch.hflags = 0;
1173
1174         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1175         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1176         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1177         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1178         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1179         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1180         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1181                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1182
1183         set_dr_intercepts(svm);
1184
1185         set_exception_intercept(svm, PF_VECTOR);
1186         set_exception_intercept(svm, UD_VECTOR);
1187         set_exception_intercept(svm, MC_VECTOR);
1188         set_exception_intercept(svm, AC_VECTOR);
1189         set_exception_intercept(svm, DB_VECTOR);
1190
1191         set_intercept(svm, INTERCEPT_INTR);
1192         set_intercept(svm, INTERCEPT_NMI);
1193         set_intercept(svm, INTERCEPT_SMI);
1194         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1195         set_intercept(svm, INTERCEPT_RDPMC);
1196         set_intercept(svm, INTERCEPT_CPUID);
1197         set_intercept(svm, INTERCEPT_INVD);
1198         set_intercept(svm, INTERCEPT_HLT);
1199         set_intercept(svm, INTERCEPT_INVLPG);
1200         set_intercept(svm, INTERCEPT_INVLPGA);
1201         set_intercept(svm, INTERCEPT_IOIO_PROT);
1202         set_intercept(svm, INTERCEPT_MSR_PROT);
1203         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1204         set_intercept(svm, INTERCEPT_SHUTDOWN);
1205         set_intercept(svm, INTERCEPT_VMRUN);
1206         set_intercept(svm, INTERCEPT_VMMCALL);
1207         set_intercept(svm, INTERCEPT_VMLOAD);
1208         set_intercept(svm, INTERCEPT_VMSAVE);
1209         set_intercept(svm, INTERCEPT_STGI);
1210         set_intercept(svm, INTERCEPT_CLGI);
1211         set_intercept(svm, INTERCEPT_SKINIT);
1212         set_intercept(svm, INTERCEPT_WBINVD);
1213         set_intercept(svm, INTERCEPT_XSETBV);
1214
1215         if (!kvm_mwait_in_guest()) {
1216                 set_intercept(svm, INTERCEPT_MONITOR);
1217                 set_intercept(svm, INTERCEPT_MWAIT);
1218         }
1219
1220         control->iopm_base_pa = iopm_base;
1221         control->msrpm_base_pa = __pa(svm->msrpm);
1222         control->int_ctl = V_INTR_MASKING_MASK;
1223
1224         init_seg(&save->es);
1225         init_seg(&save->ss);
1226         init_seg(&save->ds);
1227         init_seg(&save->fs);
1228         init_seg(&save->gs);
1229
1230         save->cs.selector = 0xf000;
1231         save->cs.base = 0xffff0000;
1232         /* Executable/Readable Code Segment */
1233         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1234                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1235         save->cs.limit = 0xffff;
1236
1237         save->gdtr.limit = 0xffff;
1238         save->idtr.limit = 0xffff;
1239
1240         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1241         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1242
1243         svm_set_efer(&svm->vcpu, 0);
1244         save->dr6 = 0xffff0ff0;
1245         kvm_set_rflags(&svm->vcpu, 2);
1246         save->rip = 0x0000fff0;
1247         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1248
1249         /*
1250          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1251          * It also updates the guest-visible cr0 value.
1252          */
1253         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1254         kvm_mmu_reset_context(&svm->vcpu);
1255
1256         save->cr4 = X86_CR4_PAE;
1257         /* rdx = ?? */
1258
1259         if (npt_enabled) {
1260                 /* Setup VMCB for Nested Paging */
1261                 control->nested_ctl = 1;
1262                 clr_intercept(svm, INTERCEPT_INVLPG);
1263                 clr_exception_intercept(svm, PF_VECTOR);
1264                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1265                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1266                 save->g_pat = svm->vcpu.arch.pat;
1267                 save->cr3 = 0;
1268                 save->cr4 = 0;
1269         }
1270         svm->asid_generation = 0;
1271
1272         svm->nested.vmcb = 0;
1273         svm->vcpu.arch.hflags = 0;
1274
1275         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1276                 control->pause_filter_count = 3000;
1277                 set_intercept(svm, INTERCEPT_PAUSE);
1278         }
1279
1280         if (avic)
1281                 avic_init_vmcb(svm);
1282
1283         mark_all_dirty(svm->vmcb);
1284
1285         enable_gif(svm);
1286
1287 }
1288
1289 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1290                                        unsigned int index)
1291 {
1292         u64 *avic_physical_id_table;
1293         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1294
1295         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1296                 return NULL;
1297
1298         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1299
1300         return &avic_physical_id_table[index];
1301 }
1302
1303 /**
1304  * Note:
1305  * AVIC hardware walks the nested page table to check permissions,
1306  * but does not use the SPA address specified in the leaf page
1307  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1308  * field of the VMCB. Therefore, we set up the
1309  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1310  */
1311 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1312 {
1313         struct kvm *kvm = vcpu->kvm;
1314         int ret;
1315
1316         if (kvm->arch.apic_access_page_done)
1317                 return 0;
1318
1319         ret = x86_set_memory_region(kvm,
1320                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1321                                     APIC_DEFAULT_PHYS_BASE,
1322                                     PAGE_SIZE);
1323         if (ret)
1324                 return ret;
1325
1326         kvm->arch.apic_access_page_done = true;
1327         return 0;
1328 }
1329
1330 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1331 {
1332         int ret;
1333         u64 *entry, new_entry;
1334         int id = vcpu->vcpu_id;
1335         struct vcpu_svm *svm = to_svm(vcpu);
1336
1337         ret = avic_init_access_page(vcpu);
1338         if (ret)
1339                 return ret;
1340
1341         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1342                 return -EINVAL;
1343
1344         if (!svm->vcpu.arch.apic->regs)
1345                 return -EINVAL;
1346
1347         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1348
1349         /* Setting AVIC backing page address in the phy APIC ID table */
1350         entry = avic_get_physical_id_entry(vcpu, id);
1351         if (!entry)
1352                 return -EINVAL;
1353
1354         new_entry = READ_ONCE(*entry);
1355         new_entry = (page_to_phys(svm->avic_backing_page) &
1356                      AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1357                      AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1358         WRITE_ONCE(*entry, new_entry);
1359
1360         svm->avic_physical_id_cache = entry;
1361
1362         return 0;
1363 }
1364
1365 static inline int avic_get_next_vm_id(void)
1366 {
1367         int id;
1368
1369         spin_lock(&avic_vm_id_lock);
1370
1371         /* AVIC VM ID is one-based. */
1372         id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1373         if (id <= AVIC_VM_ID_MASK)
1374                 __set_bit(id, avic_vm_id_bitmap);
1375         else
1376                 id = -EAGAIN;
1377
1378         spin_unlock(&avic_vm_id_lock);
1379         return id;
1380 }
1381
1382 static inline int avic_free_vm_id(int id)
1383 {
1384         if (id <= 0 || id > AVIC_VM_ID_MASK)
1385                 return -EINVAL;
1386
1387         spin_lock(&avic_vm_id_lock);
1388         __clear_bit(id, avic_vm_id_bitmap);
1389         spin_unlock(&avic_vm_id_lock);
1390         return 0;
1391 }
1392
1393 static void avic_vm_destroy(struct kvm *kvm)
1394 {
1395         unsigned long flags;
1396         struct kvm_arch *vm_data = &kvm->arch;
1397
1398         if (!avic)
1399                 return;
1400
1401         avic_free_vm_id(vm_data->avic_vm_id);
1402
1403         if (vm_data->avic_logical_id_table_page)
1404                 __free_page(vm_data->avic_logical_id_table_page);
1405         if (vm_data->avic_physical_id_table_page)
1406                 __free_page(vm_data->avic_physical_id_table_page);
1407
1408         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1409         hash_del(&vm_data->hnode);
1410         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1411 }
1412
1413 static int avic_vm_init(struct kvm *kvm)
1414 {
1415         unsigned long flags;
1416         int vm_id, err = -ENOMEM;
1417         struct kvm_arch *vm_data = &kvm->arch;
1418         struct page *p_page;
1419         struct page *l_page;
1420
1421         if (!avic)
1422                 return 0;
1423
1424         vm_id = avic_get_next_vm_id();
1425         if (vm_id < 0)
1426                 return vm_id;
1427         vm_data->avic_vm_id = (u32)vm_id;
1428
1429         /* Allocating physical APIC ID table (4KB) */
1430         p_page = alloc_page(GFP_KERNEL);
1431         if (!p_page)
1432                 goto free_avic;
1433
1434         vm_data->avic_physical_id_table_page = p_page;
1435         clear_page(page_address(p_page));
1436
1437         /* Allocating logical APIC ID table (4KB) */
1438         l_page = alloc_page(GFP_KERNEL);
1439         if (!l_page)
1440                 goto free_avic;
1441
1442         vm_data->avic_logical_id_table_page = l_page;
1443         clear_page(page_address(l_page));
1444
1445         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1446         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1447         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1448
1449         return 0;
1450
1451 free_avic:
1452         avic_vm_destroy(kvm);
1453         return err;
1454 }
1455
1456 static inline int
1457 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1458 {
1459         int ret = 0;
1460         unsigned long flags;
1461         struct amd_svm_iommu_ir *ir;
1462         struct vcpu_svm *svm = to_svm(vcpu);
1463
1464         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1465                 return 0;
1466
1467         /*
1468          * Here, we go through the per-vcpu ir_list to update all existing
1469          * interrupt remapping table entry targeting this vcpu.
1470          */
1471         spin_lock_irqsave(&svm->ir_list_lock, flags);
1472
1473         if (list_empty(&svm->ir_list))
1474                 goto out;
1475
1476         list_for_each_entry(ir, &svm->ir_list, node) {
1477                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1478                 if (ret)
1479                         break;
1480         }
1481 out:
1482         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1483         return ret;
1484 }
1485
1486 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1487 {
1488         u64 entry;
1489         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1490         int h_physical_id = kvm_cpu_get_apicid(cpu);
1491         struct vcpu_svm *svm = to_svm(vcpu);
1492
1493         if (!kvm_vcpu_apicv_active(vcpu))
1494                 return;
1495
1496         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1497                 return;
1498
1499         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1500         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1501
1502         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1503         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1504
1505         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1506         if (svm->avic_is_running)
1507                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1508
1509         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1510         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1511                                         svm->avic_is_running);
1512 }
1513
1514 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1515 {
1516         u64 entry;
1517         struct vcpu_svm *svm = to_svm(vcpu);
1518
1519         if (!kvm_vcpu_apicv_active(vcpu))
1520                 return;
1521
1522         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1523         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1524                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1525
1526         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1527         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1528 }
1529
1530 /**
1531  * This function is called during VCPU halt/unhalt.
1532  */
1533 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1534 {
1535         struct vcpu_svm *svm = to_svm(vcpu);
1536
1537         svm->avic_is_running = is_run;
1538         if (is_run)
1539                 avic_vcpu_load(vcpu, vcpu->cpu);
1540         else
1541                 avic_vcpu_put(vcpu);
1542 }
1543
1544 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1545 {
1546         struct vcpu_svm *svm = to_svm(vcpu);
1547         u32 dummy;
1548         u32 eax = 1;
1549
1550         if (!init_event) {
1551                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1552                                            MSR_IA32_APICBASE_ENABLE;
1553                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1554                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1555         }
1556         init_vmcb(svm);
1557
1558         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1559         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1560
1561         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1562                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1563 }
1564
1565 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1566 {
1567         struct vcpu_svm *svm;
1568         struct page *page;
1569         struct page *msrpm_pages;
1570         struct page *hsave_page;
1571         struct page *nested_msrpm_pages;
1572         int err;
1573
1574         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1575         if (!svm) {
1576                 err = -ENOMEM;
1577                 goto out;
1578         }
1579
1580         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1581         if (err)
1582                 goto free_svm;
1583
1584         err = -ENOMEM;
1585         page = alloc_page(GFP_KERNEL);
1586         if (!page)
1587                 goto uninit;
1588
1589         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1590         if (!msrpm_pages)
1591                 goto free_page1;
1592
1593         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1594         if (!nested_msrpm_pages)
1595                 goto free_page2;
1596
1597         hsave_page = alloc_page(GFP_KERNEL);
1598         if (!hsave_page)
1599                 goto free_page3;
1600
1601         if (avic) {
1602                 err = avic_init_backing_page(&svm->vcpu);
1603                 if (err)
1604                         goto free_page4;
1605
1606                 INIT_LIST_HEAD(&svm->ir_list);
1607                 spin_lock_init(&svm->ir_list_lock);
1608         }
1609
1610         /* We initialize this flag to true to make sure that the is_running
1611          * bit would be set the first time the vcpu is loaded.
1612          */
1613         svm->avic_is_running = true;
1614
1615         svm->nested.hsave = page_address(hsave_page);
1616
1617         svm->msrpm = page_address(msrpm_pages);
1618         svm_vcpu_init_msrpm(svm->msrpm);
1619
1620         svm->nested.msrpm = page_address(nested_msrpm_pages);
1621         svm_vcpu_init_msrpm(svm->nested.msrpm);
1622
1623         svm->vmcb = page_address(page);
1624         clear_page(svm->vmcb);
1625         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1626         svm->asid_generation = 0;
1627         init_vmcb(svm);
1628
1629         svm_init_osvw(&svm->vcpu);
1630
1631         return &svm->vcpu;
1632
1633 free_page4:
1634         __free_page(hsave_page);
1635 free_page3:
1636         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1637 free_page2:
1638         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1639 free_page1:
1640         __free_page(page);
1641 uninit:
1642         kvm_vcpu_uninit(&svm->vcpu);
1643 free_svm:
1644         kmem_cache_free(kvm_vcpu_cache, svm);
1645 out:
1646         return ERR_PTR(err);
1647 }
1648
1649 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1650 {
1651         struct vcpu_svm *svm = to_svm(vcpu);
1652
1653         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1654         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1655         __free_page(virt_to_page(svm->nested.hsave));
1656         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1657         kvm_vcpu_uninit(vcpu);
1658         kmem_cache_free(kvm_vcpu_cache, svm);
1659 }
1660
1661 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1662 {
1663         struct vcpu_svm *svm = to_svm(vcpu);
1664         int i;
1665
1666         if (unlikely(cpu != vcpu->cpu)) {
1667                 svm->asid_generation = 0;
1668                 mark_all_dirty(svm->vmcb);
1669         }
1670
1671 #ifdef CONFIG_X86_64
1672         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1673 #endif
1674         savesegment(fs, svm->host.fs);
1675         savesegment(gs, svm->host.gs);
1676         svm->host.ldt = kvm_read_ldt();
1677
1678         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1679                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1680
1681         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1682                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1683                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1684                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1685                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1686                 }
1687         }
1688         /* This assumes that the kernel never uses MSR_TSC_AUX */
1689         if (static_cpu_has(X86_FEATURE_RDTSCP))
1690                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1691
1692         avic_vcpu_load(vcpu, cpu);
1693 }
1694
1695 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1696 {
1697         struct vcpu_svm *svm = to_svm(vcpu);
1698         int i;
1699
1700         avic_vcpu_put(vcpu);
1701
1702         ++vcpu->stat.host_state_reload;
1703         kvm_load_ldt(svm->host.ldt);
1704 #ifdef CONFIG_X86_64
1705         loadsegment(fs, svm->host.fs);
1706         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1707         load_gs_index(svm->host.gs);
1708 #else
1709 #ifdef CONFIG_X86_32_LAZY_GS
1710         loadsegment(gs, svm->host.gs);
1711 #endif
1712 #endif
1713         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1714                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1715 }
1716
1717 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1718 {
1719         avic_set_running(vcpu, false);
1720 }
1721
1722 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1723 {
1724         avic_set_running(vcpu, true);
1725 }
1726
1727 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1728 {
1729         struct vcpu_svm *svm = to_svm(vcpu);
1730         unsigned long rflags = svm->vmcb->save.rflags;
1731
1732         if (svm->nmi_singlestep) {
1733                 /* Hide our flags if they were not set by the guest */
1734                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1735                         rflags &= ~X86_EFLAGS_TF;
1736                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1737                         rflags &= ~X86_EFLAGS_RF;
1738         }
1739         return rflags;
1740 }
1741
1742 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1743 {
1744         if (to_svm(vcpu)->nmi_singlestep)
1745                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1746
1747        /*
1748         * Any change of EFLAGS.VM is accompanied by a reload of SS
1749         * (caused by either a task switch or an inter-privilege IRET),
1750         * so we do not need to update the CPL here.
1751         */
1752         to_svm(vcpu)->vmcb->save.rflags = rflags;
1753 }
1754
1755 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1756 {
1757         return 0;
1758 }
1759
1760 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1761 {
1762         switch (reg) {
1763         case VCPU_EXREG_PDPTR:
1764                 BUG_ON(!npt_enabled);
1765                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1766                 break;
1767         default:
1768                 BUG();
1769         }
1770 }
1771
1772 static void svm_set_vintr(struct vcpu_svm *svm)
1773 {
1774         set_intercept(svm, INTERCEPT_VINTR);
1775 }
1776
1777 static void svm_clear_vintr(struct vcpu_svm *svm)
1778 {
1779         clr_intercept(svm, INTERCEPT_VINTR);
1780 }
1781
1782 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1783 {
1784         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1785
1786         switch (seg) {
1787         case VCPU_SREG_CS: return &save->cs;
1788         case VCPU_SREG_DS: return &save->ds;
1789         case VCPU_SREG_ES: return &save->es;
1790         case VCPU_SREG_FS: return &save->fs;
1791         case VCPU_SREG_GS: return &save->gs;
1792         case VCPU_SREG_SS: return &save->ss;
1793         case VCPU_SREG_TR: return &save->tr;
1794         case VCPU_SREG_LDTR: return &save->ldtr;
1795         }
1796         BUG();
1797         return NULL;
1798 }
1799
1800 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1801 {
1802         struct vmcb_seg *s = svm_seg(vcpu, seg);
1803
1804         return s->base;
1805 }
1806
1807 static void svm_get_segment(struct kvm_vcpu *vcpu,
1808                             struct kvm_segment *var, int seg)
1809 {
1810         struct vmcb_seg *s = svm_seg(vcpu, seg);
1811
1812         var->base = s->base;
1813         var->limit = s->limit;
1814         var->selector = s->selector;
1815         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1816         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1817         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1818         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1819         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1820         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1821         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1822
1823         /*
1824          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1825          * However, the SVM spec states that the G bit is not observed by the
1826          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1827          * So let's synthesize a legal G bit for all segments, this helps
1828          * running KVM nested. It also helps cross-vendor migration, because
1829          * Intel's vmentry has a check on the 'G' bit.
1830          */
1831         var->g = s->limit > 0xfffff;
1832
1833         /*
1834          * AMD's VMCB does not have an explicit unusable field, so emulate it
1835          * for cross vendor migration purposes by "not present"
1836          */
1837         var->unusable = !var->present;
1838
1839         switch (seg) {
1840         case VCPU_SREG_TR:
1841                 /*
1842                  * Work around a bug where the busy flag in the tr selector
1843                  * isn't exposed
1844                  */
1845                 var->type |= 0x2;
1846                 break;
1847         case VCPU_SREG_DS:
1848         case VCPU_SREG_ES:
1849         case VCPU_SREG_FS:
1850         case VCPU_SREG_GS:
1851                 /*
1852                  * The accessed bit must always be set in the segment
1853                  * descriptor cache, although it can be cleared in the
1854                  * descriptor, the cached bit always remains at 1. Since
1855                  * Intel has a check on this, set it here to support
1856                  * cross-vendor migration.
1857                  */
1858                 if (!var->unusable)
1859                         var->type |= 0x1;
1860                 break;
1861         case VCPU_SREG_SS:
1862                 /*
1863                  * On AMD CPUs sometimes the DB bit in the segment
1864                  * descriptor is left as 1, although the whole segment has
1865                  * been made unusable. Clear it here to pass an Intel VMX
1866                  * entry check when cross vendor migrating.
1867                  */
1868                 if (var->unusable)
1869                         var->db = 0;
1870                 /* This is symmetric with svm_set_segment() */
1871                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1872                 break;
1873         }
1874 }
1875
1876 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1877 {
1878         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1879
1880         return save->cpl;
1881 }
1882
1883 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1884 {
1885         struct vcpu_svm *svm = to_svm(vcpu);
1886
1887         dt->size = svm->vmcb->save.idtr.limit;
1888         dt->address = svm->vmcb->save.idtr.base;
1889 }
1890
1891 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1892 {
1893         struct vcpu_svm *svm = to_svm(vcpu);
1894
1895         svm->vmcb->save.idtr.limit = dt->size;
1896         svm->vmcb->save.idtr.base = dt->address ;
1897         mark_dirty(svm->vmcb, VMCB_DT);
1898 }
1899
1900 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1901 {
1902         struct vcpu_svm *svm = to_svm(vcpu);
1903
1904         dt->size = svm->vmcb->save.gdtr.limit;
1905         dt->address = svm->vmcb->save.gdtr.base;
1906 }
1907
1908 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1909 {
1910         struct vcpu_svm *svm = to_svm(vcpu);
1911
1912         svm->vmcb->save.gdtr.limit = dt->size;
1913         svm->vmcb->save.gdtr.base = dt->address ;
1914         mark_dirty(svm->vmcb, VMCB_DT);
1915 }
1916
1917 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1918 {
1919 }
1920
1921 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1922 {
1923 }
1924
1925 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1926 {
1927 }
1928
1929 static void update_cr0_intercept(struct vcpu_svm *svm)
1930 {
1931         ulong gcr0 = svm->vcpu.arch.cr0;
1932         u64 *hcr0 = &svm->vmcb->save.cr0;
1933
1934         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1935                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1936
1937         mark_dirty(svm->vmcb, VMCB_CR);
1938
1939         if (gcr0 == *hcr0) {
1940                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1941                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1942         } else {
1943                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1944                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1945         }
1946 }
1947
1948 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1949 {
1950         struct vcpu_svm *svm = to_svm(vcpu);
1951
1952 #ifdef CONFIG_X86_64
1953         if (vcpu->arch.efer & EFER_LME) {
1954                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1955                         vcpu->arch.efer |= EFER_LMA;
1956                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1957                 }
1958
1959                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1960                         vcpu->arch.efer &= ~EFER_LMA;
1961                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1962                 }
1963         }
1964 #endif
1965         vcpu->arch.cr0 = cr0;
1966
1967         if (!npt_enabled)
1968                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1969
1970         /*
1971          * re-enable caching here because the QEMU bios
1972          * does not do it - this results in some delay at
1973          * reboot
1974          */
1975         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1976                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1977         svm->vmcb->save.cr0 = cr0;
1978         mark_dirty(svm->vmcb, VMCB_CR);
1979         update_cr0_intercept(svm);
1980 }
1981
1982 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1983 {
1984         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1985         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1986
1987         if (cr4 & X86_CR4_VMXE)
1988                 return 1;
1989
1990         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1991                 svm_flush_tlb(vcpu);
1992
1993         vcpu->arch.cr4 = cr4;
1994         if (!npt_enabled)
1995                 cr4 |= X86_CR4_PAE;
1996         cr4 |= host_cr4_mce;
1997         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1998         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1999         return 0;
2000 }
2001
2002 static void svm_set_segment(struct kvm_vcpu *vcpu,
2003                             struct kvm_segment *var, int seg)
2004 {
2005         struct vcpu_svm *svm = to_svm(vcpu);
2006         struct vmcb_seg *s = svm_seg(vcpu, seg);
2007
2008         s->base = var->base;
2009         s->limit = var->limit;
2010         s->selector = var->selector;
2011         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2012         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2013         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2014         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2015         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2016         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2017         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2018         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2019
2020         /*
2021          * This is always accurate, except if SYSRET returned to a segment
2022          * with SS.DPL != 3.  Intel does not have this quirk, and always
2023          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2024          * would entail passing the CPL to userspace and back.
2025          */
2026         if (seg == VCPU_SREG_SS)
2027                 /* This is symmetric with svm_get_segment() */
2028                 svm->vmcb->save.cpl = (var->dpl & 3);
2029
2030         mark_dirty(svm->vmcb, VMCB_SEG);
2031 }
2032
2033 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2034 {
2035         struct vcpu_svm *svm = to_svm(vcpu);
2036
2037         clr_exception_intercept(svm, BP_VECTOR);
2038
2039         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2040                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2041                         set_exception_intercept(svm, BP_VECTOR);
2042         } else
2043                 vcpu->guest_debug = 0;
2044 }
2045
2046 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2047 {
2048         if (sd->next_asid > sd->max_asid) {
2049                 ++sd->asid_generation;
2050                 sd->next_asid = 1;
2051                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2052         }
2053
2054         svm->asid_generation = sd->asid_generation;
2055         svm->vmcb->control.asid = sd->next_asid++;
2056
2057         mark_dirty(svm->vmcb, VMCB_ASID);
2058 }
2059
2060 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2061 {
2062         return to_svm(vcpu)->vmcb->save.dr6;
2063 }
2064
2065 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2066 {
2067         struct vcpu_svm *svm = to_svm(vcpu);
2068
2069         svm->vmcb->save.dr6 = value;
2070         mark_dirty(svm->vmcb, VMCB_DR);
2071 }
2072
2073 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2074 {
2075         struct vcpu_svm *svm = to_svm(vcpu);
2076
2077         get_debugreg(vcpu->arch.db[0], 0);
2078         get_debugreg(vcpu->arch.db[1], 1);
2079         get_debugreg(vcpu->arch.db[2], 2);
2080         get_debugreg(vcpu->arch.db[3], 3);
2081         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2082         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2083
2084         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2085         set_dr_intercepts(svm);
2086 }
2087
2088 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2089 {
2090         struct vcpu_svm *svm = to_svm(vcpu);
2091
2092         svm->vmcb->save.dr7 = value;
2093         mark_dirty(svm->vmcb, VMCB_DR);
2094 }
2095
2096 static int pf_interception(struct vcpu_svm *svm)
2097 {
2098         u64 fault_address = svm->vmcb->control.exit_info_2;
2099         u64 error_code;
2100         int r = 1;
2101
2102         switch (svm->apf_reason) {
2103         default:
2104                 error_code = svm->vmcb->control.exit_info_1;
2105
2106                 trace_kvm_page_fault(fault_address, error_code);
2107                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2108                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2109                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2110                         svm->vmcb->control.insn_bytes,
2111                         svm->vmcb->control.insn_len);
2112                 break;
2113         case KVM_PV_REASON_PAGE_NOT_PRESENT:
2114                 svm->apf_reason = 0;
2115                 local_irq_disable();
2116                 kvm_async_pf_task_wait(fault_address);
2117                 local_irq_enable();
2118                 break;
2119         case KVM_PV_REASON_PAGE_READY:
2120                 svm->apf_reason = 0;
2121                 local_irq_disable();
2122                 kvm_async_pf_task_wake(fault_address);
2123                 local_irq_enable();
2124                 break;
2125         }
2126         return r;
2127 }
2128
2129 static int db_interception(struct vcpu_svm *svm)
2130 {
2131         struct kvm_run *kvm_run = svm->vcpu.run;
2132
2133         if (!(svm->vcpu.guest_debug &
2134               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2135                 !svm->nmi_singlestep) {
2136                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2137                 return 1;
2138         }
2139
2140         if (svm->nmi_singlestep) {
2141                 disable_nmi_singlestep(svm);
2142         }
2143
2144         if (svm->vcpu.guest_debug &
2145             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2146                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2147                 kvm_run->debug.arch.pc =
2148                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2149                 kvm_run->debug.arch.exception = DB_VECTOR;
2150                 return 0;
2151         }
2152
2153         return 1;
2154 }
2155
2156 static int bp_interception(struct vcpu_svm *svm)
2157 {
2158         struct kvm_run *kvm_run = svm->vcpu.run;
2159
2160         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2161         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2162         kvm_run->debug.arch.exception = BP_VECTOR;
2163         return 0;
2164 }
2165
2166 static int ud_interception(struct vcpu_svm *svm)
2167 {
2168         int er;
2169
2170         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2171         if (er != EMULATE_DONE)
2172                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2173         return 1;
2174 }
2175
2176 static int ac_interception(struct vcpu_svm *svm)
2177 {
2178         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2179         return 1;
2180 }
2181
2182 static bool is_erratum_383(void)
2183 {
2184         int err, i;
2185         u64 value;
2186
2187         if (!erratum_383_found)
2188                 return false;
2189
2190         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2191         if (err)
2192                 return false;
2193
2194         /* Bit 62 may or may not be set for this mce */
2195         value &= ~(1ULL << 62);
2196
2197         if (value != 0xb600000000010015ULL)
2198                 return false;
2199
2200         /* Clear MCi_STATUS registers */
2201         for (i = 0; i < 6; ++i)
2202                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2203
2204         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2205         if (!err) {
2206                 u32 low, high;
2207
2208                 value &= ~(1ULL << 2);
2209                 low    = lower_32_bits(value);
2210                 high   = upper_32_bits(value);
2211
2212                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2213         }
2214
2215         /* Flush tlb to evict multi-match entries */
2216         __flush_tlb_all();
2217
2218         return true;
2219 }
2220
2221 static void svm_handle_mce(struct vcpu_svm *svm)
2222 {
2223         if (is_erratum_383()) {
2224                 /*
2225                  * Erratum 383 triggered. Guest state is corrupt so kill the
2226                  * guest.
2227                  */
2228                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2229
2230                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2231
2232                 return;
2233         }
2234
2235         /*
2236          * On an #MC intercept the MCE handler is not called automatically in
2237          * the host. So do it by hand here.
2238          */
2239         asm volatile (
2240                 "int $0x12\n");
2241         /* not sure if we ever come back to this point */
2242
2243         return;
2244 }
2245
2246 static int mc_interception(struct vcpu_svm *svm)
2247 {
2248         return 1;
2249 }
2250
2251 static int shutdown_interception(struct vcpu_svm *svm)
2252 {
2253         struct kvm_run *kvm_run = svm->vcpu.run;
2254
2255         /*
2256          * VMCB is undefined after a SHUTDOWN intercept
2257          * so reinitialize it.
2258          */
2259         clear_page(svm->vmcb);
2260         init_vmcb(svm);
2261
2262         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2263         return 0;
2264 }
2265
2266 static int io_interception(struct vcpu_svm *svm)
2267 {
2268         struct kvm_vcpu *vcpu = &svm->vcpu;
2269         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2270         int size, in, string;
2271         unsigned port;
2272
2273         ++svm->vcpu.stat.io_exits;
2274         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2275         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2276         if (string)
2277                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2278
2279         port = io_info >> 16;
2280         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2281         svm->next_rip = svm->vmcb->control.exit_info_2;
2282         skip_emulated_instruction(&svm->vcpu);
2283
2284         return in ? kvm_fast_pio_in(vcpu, size, port)
2285                   : kvm_fast_pio_out(vcpu, size, port);
2286 }
2287
2288 static int nmi_interception(struct vcpu_svm *svm)
2289 {
2290         return 1;
2291 }
2292
2293 static int intr_interception(struct vcpu_svm *svm)
2294 {
2295         ++svm->vcpu.stat.irq_exits;
2296         return 1;
2297 }
2298
2299 static int nop_on_interception(struct vcpu_svm *svm)
2300 {
2301         return 1;
2302 }
2303
2304 static int halt_interception(struct vcpu_svm *svm)
2305 {
2306         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2307         return kvm_emulate_halt(&svm->vcpu);
2308 }
2309
2310 static int vmmcall_interception(struct vcpu_svm *svm)
2311 {
2312         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2313         return kvm_emulate_hypercall(&svm->vcpu);
2314 }
2315
2316 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2317 {
2318         struct vcpu_svm *svm = to_svm(vcpu);
2319
2320         return svm->nested.nested_cr3;
2321 }
2322
2323 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2324 {
2325         struct vcpu_svm *svm = to_svm(vcpu);
2326         u64 cr3 = svm->nested.nested_cr3;
2327         u64 pdpte;
2328         int ret;
2329
2330         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2331                                        offset_in_page(cr3) + index * 8, 8);
2332         if (ret)
2333                 return 0;
2334         return pdpte;
2335 }
2336
2337 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2338                                    unsigned long root)
2339 {
2340         struct vcpu_svm *svm = to_svm(vcpu);
2341
2342         svm->vmcb->control.nested_cr3 = root;
2343         mark_dirty(svm->vmcb, VMCB_NPT);
2344         svm_flush_tlb(vcpu);
2345 }
2346
2347 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2348                                        struct x86_exception *fault)
2349 {
2350         struct vcpu_svm *svm = to_svm(vcpu);
2351
2352         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2353                 /*
2354                  * TODO: track the cause of the nested page fault, and
2355                  * correctly fill in the high bits of exit_info_1.
2356                  */
2357                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2358                 svm->vmcb->control.exit_code_hi = 0;
2359                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2360                 svm->vmcb->control.exit_info_2 = fault->address;
2361         }
2362
2363         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2364         svm->vmcb->control.exit_info_1 |= fault->error_code;
2365
2366         /*
2367          * The present bit is always zero for page structure faults on real
2368          * hardware.
2369          */
2370         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2371                 svm->vmcb->control.exit_info_1 &= ~1;
2372
2373         nested_svm_vmexit(svm);
2374 }
2375
2376 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2377 {
2378         WARN_ON(mmu_is_nested(vcpu));
2379         kvm_init_shadow_mmu(vcpu);
2380         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2381         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2382         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2383         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2384         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2385         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2386         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2387 }
2388
2389 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2390 {
2391         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2392 }
2393
2394 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2395 {
2396         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2397             !is_paging(&svm->vcpu)) {
2398                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2399                 return 1;
2400         }
2401
2402         if (svm->vmcb->save.cpl) {
2403                 kvm_inject_gp(&svm->vcpu, 0);
2404                 return 1;
2405         }
2406
2407         return 0;
2408 }
2409
2410 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2411                                       bool has_error_code, u32 error_code)
2412 {
2413         int vmexit;
2414
2415         if (!is_guest_mode(&svm->vcpu))
2416                 return 0;
2417
2418         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2419         svm->vmcb->control.exit_code_hi = 0;
2420         svm->vmcb->control.exit_info_1 = error_code;
2421         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2422
2423         vmexit = nested_svm_intercept(svm);
2424         if (vmexit == NESTED_EXIT_DONE)
2425                 svm->nested.exit_required = true;
2426
2427         return vmexit;
2428 }
2429
2430 /* This function returns true if it is save to enable the irq window */
2431 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2432 {
2433         if (!is_guest_mode(&svm->vcpu))
2434                 return true;
2435
2436         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2437                 return true;
2438
2439         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2440                 return false;
2441
2442         /*
2443          * if vmexit was already requested (by intercepted exception
2444          * for instance) do not overwrite it with "external interrupt"
2445          * vmexit.
2446          */
2447         if (svm->nested.exit_required)
2448                 return false;
2449
2450         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2451         svm->vmcb->control.exit_info_1 = 0;
2452         svm->vmcb->control.exit_info_2 = 0;
2453
2454         if (svm->nested.intercept & 1ULL) {
2455                 /*
2456                  * The #vmexit can't be emulated here directly because this
2457                  * code path runs with irqs and preemption disabled. A
2458                  * #vmexit emulation might sleep. Only signal request for
2459                  * the #vmexit here.
2460                  */
2461                 svm->nested.exit_required = true;
2462                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2463                 return false;
2464         }
2465
2466         return true;
2467 }
2468
2469 /* This function returns true if it is save to enable the nmi window */
2470 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2471 {
2472         if (!is_guest_mode(&svm->vcpu))
2473                 return true;
2474
2475         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2476                 return true;
2477
2478         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2479         svm->nested.exit_required = true;
2480
2481         return false;
2482 }
2483
2484 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2485 {
2486         struct page *page;
2487
2488         might_sleep();
2489
2490         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2491         if (is_error_page(page))
2492                 goto error;
2493
2494         *_page = page;
2495
2496         return kmap(page);
2497
2498 error:
2499         kvm_inject_gp(&svm->vcpu, 0);
2500
2501         return NULL;
2502 }
2503
2504 static void nested_svm_unmap(struct page *page)
2505 {
2506         kunmap(page);
2507         kvm_release_page_dirty(page);
2508 }
2509
2510 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2511 {
2512         unsigned port, size, iopm_len;
2513         u16 val, mask;
2514         u8 start_bit;
2515         u64 gpa;
2516
2517         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2518                 return NESTED_EXIT_HOST;
2519
2520         port = svm->vmcb->control.exit_info_1 >> 16;
2521         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2522                 SVM_IOIO_SIZE_SHIFT;
2523         gpa  = svm->nested.vmcb_iopm + (port / 8);
2524         start_bit = port % 8;
2525         iopm_len = (start_bit + size > 8) ? 2 : 1;
2526         mask = (0xf >> (4 - size)) << start_bit;
2527         val = 0;
2528
2529         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2530                 return NESTED_EXIT_DONE;
2531
2532         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2533 }
2534
2535 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2536 {
2537         u32 offset, msr, value;
2538         int write, mask;
2539
2540         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2541                 return NESTED_EXIT_HOST;
2542
2543         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2544         offset = svm_msrpm_offset(msr);
2545         write  = svm->vmcb->control.exit_info_1 & 1;
2546         mask   = 1 << ((2 * (msr & 0xf)) + write);
2547
2548         if (offset == MSR_INVALID)
2549                 return NESTED_EXIT_DONE;
2550
2551         /* Offset is in 32 bit units but need in 8 bit units */
2552         offset *= 4;
2553
2554         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2555                 return NESTED_EXIT_DONE;
2556
2557         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2558 }
2559
2560 /* DB exceptions for our internal use must not cause vmexit */
2561 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2562 {
2563         unsigned long dr6;
2564
2565         /* if we're not singlestepping, it's not ours */
2566         if (!svm->nmi_singlestep)
2567                 return NESTED_EXIT_DONE;
2568
2569         /* if it's not a singlestep exception, it's not ours */
2570         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2571                 return NESTED_EXIT_DONE;
2572         if (!(dr6 & DR6_BS))
2573                 return NESTED_EXIT_DONE;
2574
2575         /* if the guest is singlestepping, it should get the vmexit */
2576         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2577                 disable_nmi_singlestep(svm);
2578                 return NESTED_EXIT_DONE;
2579         }
2580
2581         /* it's ours, the nested hypervisor must not see this one */
2582         return NESTED_EXIT_HOST;
2583 }
2584
2585 static int nested_svm_exit_special(struct vcpu_svm *svm)
2586 {
2587         u32 exit_code = svm->vmcb->control.exit_code;
2588
2589         switch (exit_code) {
2590         case SVM_EXIT_INTR:
2591         case SVM_EXIT_NMI:
2592         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2593                 return NESTED_EXIT_HOST;
2594         case SVM_EXIT_NPF:
2595                 /* For now we are always handling NPFs when using them */
2596                 if (npt_enabled)
2597                         return NESTED_EXIT_HOST;
2598                 break;
2599         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2600                 /* When we're shadowing, trap PFs, but not async PF */
2601                 if (!npt_enabled && svm->apf_reason == 0)
2602                         return NESTED_EXIT_HOST;
2603                 break;
2604         default:
2605                 break;
2606         }
2607
2608         return NESTED_EXIT_CONTINUE;
2609 }
2610
2611 /*
2612  * If this function returns true, this #vmexit was already handled
2613  */
2614 static int nested_svm_intercept(struct vcpu_svm *svm)
2615 {
2616         u32 exit_code = svm->vmcb->control.exit_code;
2617         int vmexit = NESTED_EXIT_HOST;
2618
2619         switch (exit_code) {
2620         case SVM_EXIT_MSR:
2621                 vmexit = nested_svm_exit_handled_msr(svm);
2622                 break;
2623         case SVM_EXIT_IOIO:
2624                 vmexit = nested_svm_intercept_ioio(svm);
2625                 break;
2626         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2627                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2628                 if (svm->nested.intercept_cr & bit)
2629                         vmexit = NESTED_EXIT_DONE;
2630                 break;
2631         }
2632         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2633                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2634                 if (svm->nested.intercept_dr & bit)
2635                         vmexit = NESTED_EXIT_DONE;
2636                 break;
2637         }
2638         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2639                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2640                 if (svm->nested.intercept_exceptions & excp_bits) {
2641                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2642                                 vmexit = nested_svm_intercept_db(svm);
2643                         else
2644                                 vmexit = NESTED_EXIT_DONE;
2645                 }
2646                 /* async page fault always cause vmexit */
2647                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2648                          svm->apf_reason != 0)
2649                         vmexit = NESTED_EXIT_DONE;
2650                 break;
2651         }
2652         case SVM_EXIT_ERR: {
2653                 vmexit = NESTED_EXIT_DONE;
2654                 break;
2655         }
2656         default: {
2657                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2658                 if (svm->nested.intercept & exit_bits)
2659                         vmexit = NESTED_EXIT_DONE;
2660         }
2661         }
2662
2663         return vmexit;
2664 }
2665
2666 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2667 {
2668         int vmexit;
2669
2670         vmexit = nested_svm_intercept(svm);
2671
2672         if (vmexit == NESTED_EXIT_DONE)
2673                 nested_svm_vmexit(svm);
2674
2675         return vmexit;
2676 }
2677
2678 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2679 {
2680         struct vmcb_control_area *dst  = &dst_vmcb->control;
2681         struct vmcb_control_area *from = &from_vmcb->control;
2682
2683         dst->intercept_cr         = from->intercept_cr;
2684         dst->intercept_dr         = from->intercept_dr;
2685         dst->intercept_exceptions = from->intercept_exceptions;
2686         dst->intercept            = from->intercept;
2687         dst->iopm_base_pa         = from->iopm_base_pa;
2688         dst->msrpm_base_pa        = from->msrpm_base_pa;
2689         dst->tsc_offset           = from->tsc_offset;
2690         dst->asid                 = from->asid;
2691         dst->tlb_ctl              = from->tlb_ctl;
2692         dst->int_ctl              = from->int_ctl;
2693         dst->int_vector           = from->int_vector;
2694         dst->int_state            = from->int_state;
2695         dst->exit_code            = from->exit_code;
2696         dst->exit_code_hi         = from->exit_code_hi;
2697         dst->exit_info_1          = from->exit_info_1;
2698         dst->exit_info_2          = from->exit_info_2;
2699         dst->exit_int_info        = from->exit_int_info;
2700         dst->exit_int_info_err    = from->exit_int_info_err;
2701         dst->nested_ctl           = from->nested_ctl;
2702         dst->event_inj            = from->event_inj;
2703         dst->event_inj_err        = from->event_inj_err;
2704         dst->nested_cr3           = from->nested_cr3;
2705         dst->lbr_ctl              = from->lbr_ctl;
2706 }
2707
2708 static int nested_svm_vmexit(struct vcpu_svm *svm)
2709 {
2710         struct vmcb *nested_vmcb;
2711         struct vmcb *hsave = svm->nested.hsave;
2712         struct vmcb *vmcb = svm->vmcb;
2713         struct page *page;
2714
2715         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2716                                        vmcb->control.exit_info_1,
2717                                        vmcb->control.exit_info_2,
2718                                        vmcb->control.exit_int_info,
2719                                        vmcb->control.exit_int_info_err,
2720                                        KVM_ISA_SVM);
2721
2722         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2723         if (!nested_vmcb)
2724                 return 1;
2725
2726         /* Exit Guest-Mode */
2727         leave_guest_mode(&svm->vcpu);
2728         svm->nested.vmcb = 0;
2729
2730         /* Give the current vmcb to the guest */
2731         disable_gif(svm);
2732
2733         nested_vmcb->save.es     = vmcb->save.es;
2734         nested_vmcb->save.cs     = vmcb->save.cs;
2735         nested_vmcb->save.ss     = vmcb->save.ss;
2736         nested_vmcb->save.ds     = vmcb->save.ds;
2737         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2738         nested_vmcb->save.idtr   = vmcb->save.idtr;
2739         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2740         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2741         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2742         nested_vmcb->save.cr2    = vmcb->save.cr2;
2743         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2744         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2745         nested_vmcb->save.rip    = vmcb->save.rip;
2746         nested_vmcb->save.rsp    = vmcb->save.rsp;
2747         nested_vmcb->save.rax    = vmcb->save.rax;
2748         nested_vmcb->save.dr7    = vmcb->save.dr7;
2749         nested_vmcb->save.dr6    = vmcb->save.dr6;
2750         nested_vmcb->save.cpl    = vmcb->save.cpl;
2751
2752         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2753         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2754         nested_vmcb->control.int_state         = vmcb->control.int_state;
2755         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2756         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2757         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2758         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2759         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2760         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2761
2762         if (svm->nrips_enabled)
2763                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2764
2765         /*
2766          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2767          * to make sure that we do not lose injected events. So check event_inj
2768          * here and copy it to exit_int_info if it is valid.
2769          * Exit_int_info and event_inj can't be both valid because the case
2770          * below only happens on a VMRUN instruction intercept which has
2771          * no valid exit_int_info set.
2772          */
2773         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2774                 struct vmcb_control_area *nc = &nested_vmcb->control;
2775
2776                 nc->exit_int_info     = vmcb->control.event_inj;
2777                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2778         }
2779
2780         nested_vmcb->control.tlb_ctl           = 0;
2781         nested_vmcb->control.event_inj         = 0;
2782         nested_vmcb->control.event_inj_err     = 0;
2783
2784         /* We always set V_INTR_MASKING and remember the old value in hflags */
2785         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2786                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2787
2788         /* Restore the original control entries */
2789         copy_vmcb_control_area(vmcb, hsave);
2790
2791         kvm_clear_exception_queue(&svm->vcpu);
2792         kvm_clear_interrupt_queue(&svm->vcpu);
2793
2794         svm->nested.nested_cr3 = 0;
2795
2796         /* Restore selected save entries */
2797         svm->vmcb->save.es = hsave->save.es;
2798         svm->vmcb->save.cs = hsave->save.cs;
2799         svm->vmcb->save.ss = hsave->save.ss;
2800         svm->vmcb->save.ds = hsave->save.ds;
2801         svm->vmcb->save.gdtr = hsave->save.gdtr;
2802         svm->vmcb->save.idtr = hsave->save.idtr;
2803         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2804         svm_set_efer(&svm->vcpu, hsave->save.efer);
2805         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2806         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2807         if (npt_enabled) {
2808                 svm->vmcb->save.cr3 = hsave->save.cr3;
2809                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2810         } else {
2811                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2812         }
2813         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2814         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2815         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2816         svm->vmcb->save.dr7 = 0;
2817         svm->vmcb->save.cpl = 0;
2818         svm->vmcb->control.exit_int_info = 0;
2819
2820         mark_all_dirty(svm->vmcb);
2821
2822         nested_svm_unmap(page);
2823
2824         nested_svm_uninit_mmu_context(&svm->vcpu);
2825         kvm_mmu_reset_context(&svm->vcpu);
2826         kvm_mmu_load(&svm->vcpu);
2827
2828         return 0;
2829 }
2830
2831 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2832 {
2833         /*
2834          * This function merges the msr permission bitmaps of kvm and the
2835          * nested vmcb. It is optimized in that it only merges the parts where
2836          * the kvm msr permission bitmap may contain zero bits
2837          */
2838         int i;
2839
2840         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2841                 return true;
2842
2843         for (i = 0; i < MSRPM_OFFSETS; i++) {
2844                 u32 value, p;
2845                 u64 offset;
2846
2847                 if (msrpm_offsets[i] == 0xffffffff)
2848                         break;
2849
2850                 p      = msrpm_offsets[i];
2851                 offset = svm->nested.vmcb_msrpm + (p * 4);
2852
2853                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2854                         return false;
2855
2856                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2857         }
2858
2859         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2860
2861         return true;
2862 }
2863
2864 static bool nested_vmcb_checks(struct vmcb *vmcb)
2865 {
2866         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2867                 return false;
2868
2869         if (vmcb->control.asid == 0)
2870                 return false;
2871
2872         if (vmcb->control.nested_ctl && !npt_enabled)
2873                 return false;
2874
2875         return true;
2876 }
2877
2878 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2879 {
2880         struct vmcb *nested_vmcb;
2881         struct vmcb *hsave = svm->nested.hsave;
2882         struct vmcb *vmcb = svm->vmcb;
2883         struct page *page;
2884         u64 vmcb_gpa;
2885
2886         vmcb_gpa = svm->vmcb->save.rax;
2887
2888         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2889         if (!nested_vmcb)
2890                 return false;
2891
2892         if (!nested_vmcb_checks(nested_vmcb)) {
2893                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2894                 nested_vmcb->control.exit_code_hi = 0;
2895                 nested_vmcb->control.exit_info_1  = 0;
2896                 nested_vmcb->control.exit_info_2  = 0;
2897
2898                 nested_svm_unmap(page);
2899
2900                 return false;
2901         }
2902
2903         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2904                                nested_vmcb->save.rip,
2905                                nested_vmcb->control.int_ctl,
2906                                nested_vmcb->control.event_inj,
2907                                nested_vmcb->control.nested_ctl);
2908
2909         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2910                                     nested_vmcb->control.intercept_cr >> 16,
2911                                     nested_vmcb->control.intercept_exceptions,
2912                                     nested_vmcb->control.intercept);
2913
2914         /* Clear internal status */
2915         kvm_clear_exception_queue(&svm->vcpu);
2916         kvm_clear_interrupt_queue(&svm->vcpu);
2917
2918         /*
2919          * Save the old vmcb, so we don't need to pick what we save, but can
2920          * restore everything when a VMEXIT occurs
2921          */
2922         hsave->save.es     = vmcb->save.es;
2923         hsave->save.cs     = vmcb->save.cs;
2924         hsave->save.ss     = vmcb->save.ss;
2925         hsave->save.ds     = vmcb->save.ds;
2926         hsave->save.gdtr   = vmcb->save.gdtr;
2927         hsave->save.idtr   = vmcb->save.idtr;
2928         hsave->save.efer   = svm->vcpu.arch.efer;
2929         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2930         hsave->save.cr4    = svm->vcpu.arch.cr4;
2931         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2932         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2933         hsave->save.rsp    = vmcb->save.rsp;
2934         hsave->save.rax    = vmcb->save.rax;
2935         if (npt_enabled)
2936                 hsave->save.cr3    = vmcb->save.cr3;
2937         else
2938                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2939
2940         copy_vmcb_control_area(hsave, vmcb);
2941
2942         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2943                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2944         else
2945                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2946
2947         if (nested_vmcb->control.nested_ctl) {
2948                 kvm_mmu_unload(&svm->vcpu);
2949                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2950                 nested_svm_init_mmu_context(&svm->vcpu);
2951         }
2952
2953         /* Load the nested guest state */
2954         svm->vmcb->save.es = nested_vmcb->save.es;
2955         svm->vmcb->save.cs = nested_vmcb->save.cs;
2956         svm->vmcb->save.ss = nested_vmcb->save.ss;
2957         svm->vmcb->save.ds = nested_vmcb->save.ds;
2958         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2959         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2960         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2961         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2962         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2963         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2964         if (npt_enabled) {
2965                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2966                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2967         } else
2968                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2969
2970         /* Guest paging mode is active - reset mmu */
2971         kvm_mmu_reset_context(&svm->vcpu);
2972
2973         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2974         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2975         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2976         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2977
2978         /* In case we don't even reach vcpu_run, the fields are not updated */
2979         svm->vmcb->save.rax = nested_vmcb->save.rax;
2980         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2981         svm->vmcb->save.rip = nested_vmcb->save.rip;
2982         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2983         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2984         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2985
2986         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2987         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2988
2989         /* cache intercepts */
2990         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2991         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2992         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2993         svm->nested.intercept            = nested_vmcb->control.intercept;
2994
2995         svm_flush_tlb(&svm->vcpu);
2996         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2997         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2998                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2999         else
3000                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3001
3002         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3003                 /* We only want the cr8 intercept bits of the guest */
3004                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3005                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3006         }
3007
3008         /* We don't want to see VMMCALLs from a nested guest */
3009         clr_intercept(svm, INTERCEPT_VMMCALL);
3010
3011         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3012         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3013         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3014         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3015         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3016         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3017
3018         nested_svm_unmap(page);
3019
3020         /* Enter Guest-Mode */
3021         enter_guest_mode(&svm->vcpu);
3022
3023         /*
3024          * Merge guest and host intercepts - must be called  with vcpu in
3025          * guest-mode to take affect here
3026          */
3027         recalc_intercepts(svm);
3028
3029         svm->nested.vmcb = vmcb_gpa;
3030
3031         enable_gif(svm);
3032
3033         mark_all_dirty(svm->vmcb);
3034
3035         return true;
3036 }
3037
3038 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3039 {
3040         to_vmcb->save.fs = from_vmcb->save.fs;
3041         to_vmcb->save.gs = from_vmcb->save.gs;
3042         to_vmcb->save.tr = from_vmcb->save.tr;
3043         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3044         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3045         to_vmcb->save.star = from_vmcb->save.star;
3046         to_vmcb->save.lstar = from_vmcb->save.lstar;
3047         to_vmcb->save.cstar = from_vmcb->save.cstar;
3048         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3049         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3050         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3051         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3052 }
3053
3054 static int vmload_interception(struct vcpu_svm *svm)
3055 {
3056         struct vmcb *nested_vmcb;
3057         struct page *page;
3058
3059         if (nested_svm_check_permissions(svm))
3060                 return 1;
3061
3062         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3063         if (!nested_vmcb)
3064                 return 1;
3065
3066         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3067         skip_emulated_instruction(&svm->vcpu);
3068
3069         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3070         nested_svm_unmap(page);
3071
3072         return 1;
3073 }
3074
3075 static int vmsave_interception(struct vcpu_svm *svm)
3076 {
3077         struct vmcb *nested_vmcb;
3078         struct page *page;
3079
3080         if (nested_svm_check_permissions(svm))
3081                 return 1;
3082
3083         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3084         if (!nested_vmcb)
3085                 return 1;
3086
3087         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3088         skip_emulated_instruction(&svm->vcpu);
3089
3090         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3091         nested_svm_unmap(page);
3092
3093         return 1;
3094 }
3095
3096 static int vmrun_interception(struct vcpu_svm *svm)
3097 {
3098         if (nested_svm_check_permissions(svm))
3099                 return 1;
3100
3101         /* Save rip after vmrun instruction */
3102         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3103
3104         if (!nested_svm_vmrun(svm))
3105                 return 1;
3106
3107         if (!nested_svm_vmrun_msrpm(svm))
3108                 goto failed;
3109
3110         return 1;
3111
3112 failed:
3113
3114         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3115         svm->vmcb->control.exit_code_hi = 0;
3116         svm->vmcb->control.exit_info_1  = 0;
3117         svm->vmcb->control.exit_info_2  = 0;
3118
3119         nested_svm_vmexit(svm);
3120
3121         return 1;
3122 }
3123
3124 static int stgi_interception(struct vcpu_svm *svm)
3125 {
3126         if (nested_svm_check_permissions(svm))
3127                 return 1;
3128
3129         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3130         skip_emulated_instruction(&svm->vcpu);
3131         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3132
3133         enable_gif(svm);
3134
3135         return 1;
3136 }
3137
3138 static int clgi_interception(struct vcpu_svm *svm)
3139 {
3140         if (nested_svm_check_permissions(svm))
3141                 return 1;
3142
3143         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3144         skip_emulated_instruction(&svm->vcpu);
3145
3146         disable_gif(svm);
3147
3148         /* After a CLGI no interrupts should come */
3149         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3150                 svm_clear_vintr(svm);
3151                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3152                 mark_dirty(svm->vmcb, VMCB_INTR);
3153         }
3154
3155         return 1;
3156 }
3157
3158 static int invlpga_interception(struct vcpu_svm *svm)
3159 {
3160         struct kvm_vcpu *vcpu = &svm->vcpu;
3161
3162         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3163                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3164
3165         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3166         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3167
3168         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3169         skip_emulated_instruction(&svm->vcpu);
3170         return 1;
3171 }
3172
3173 static int skinit_interception(struct vcpu_svm *svm)
3174 {
3175         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3176
3177         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3178         return 1;
3179 }
3180
3181 static int wbinvd_interception(struct vcpu_svm *svm)
3182 {
3183         return kvm_emulate_wbinvd(&svm->vcpu);
3184 }
3185
3186 static int xsetbv_interception(struct vcpu_svm *svm)
3187 {
3188         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3189         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3190
3191         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3192                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3193                 skip_emulated_instruction(&svm->vcpu);
3194         }
3195
3196         return 1;
3197 }
3198
3199 static int task_switch_interception(struct vcpu_svm *svm)
3200 {
3201         u16 tss_selector;
3202         int reason;
3203         int int_type = svm->vmcb->control.exit_int_info &
3204                 SVM_EXITINTINFO_TYPE_MASK;
3205         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3206         uint32_t type =
3207                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3208         uint32_t idt_v =
3209                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3210         bool has_error_code = false;
3211         u32 error_code = 0;
3212
3213         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3214
3215         if (svm->vmcb->control.exit_info_2 &
3216             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3217                 reason = TASK_SWITCH_IRET;
3218         else if (svm->vmcb->control.exit_info_2 &
3219                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3220                 reason = TASK_SWITCH_JMP;
3221         else if (idt_v)
3222                 reason = TASK_SWITCH_GATE;
3223         else
3224                 reason = TASK_SWITCH_CALL;
3225
3226         if (reason == TASK_SWITCH_GATE) {
3227                 switch (type) {
3228                 case SVM_EXITINTINFO_TYPE_NMI:
3229                         svm->vcpu.arch.nmi_injected = false;
3230                         break;
3231                 case SVM_EXITINTINFO_TYPE_EXEPT:
3232                         if (svm->vmcb->control.exit_info_2 &
3233                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3234                                 has_error_code = true;
3235                                 error_code =
3236                                         (u32)svm->vmcb->control.exit_info_2;
3237                         }
3238                         kvm_clear_exception_queue(&svm->vcpu);
3239                         break;
3240                 case SVM_EXITINTINFO_TYPE_INTR:
3241                         kvm_clear_interrupt_queue(&svm->vcpu);
3242                         break;
3243                 default:
3244                         break;
3245                 }
3246         }
3247
3248         if (reason != TASK_SWITCH_GATE ||
3249             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3250             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3251              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3252                 skip_emulated_instruction(&svm->vcpu);
3253
3254         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3255                 int_vec = -1;
3256
3257         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3258                                 has_error_code, error_code) == EMULATE_FAIL) {
3259                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3260                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3261                 svm->vcpu.run->internal.ndata = 0;
3262                 return 0;
3263         }
3264         return 1;
3265 }
3266
3267 static int cpuid_interception(struct vcpu_svm *svm)
3268 {
3269         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3270         return kvm_emulate_cpuid(&svm->vcpu);
3271 }
3272
3273 static int iret_interception(struct vcpu_svm *svm)
3274 {
3275         ++svm->vcpu.stat.nmi_window_exits;
3276         clr_intercept(svm, INTERCEPT_IRET);
3277         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3278         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3279         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3280         return 1;
3281 }
3282
3283 static int invlpg_interception(struct vcpu_svm *svm)
3284 {
3285         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3286                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3287
3288         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3289         skip_emulated_instruction(&svm->vcpu);
3290         return 1;
3291 }
3292
3293 static int emulate_on_interception(struct vcpu_svm *svm)
3294 {
3295         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3296 }
3297
3298 static int rdpmc_interception(struct vcpu_svm *svm)
3299 {
3300         int err;
3301
3302         if (!static_cpu_has(X86_FEATURE_NRIPS))
3303                 return emulate_on_interception(svm);
3304
3305         err = kvm_rdpmc(&svm->vcpu);
3306         return kvm_complete_insn_gp(&svm->vcpu, err);
3307 }
3308
3309 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3310                                             unsigned long val)
3311 {
3312         unsigned long cr0 = svm->vcpu.arch.cr0;
3313         bool ret = false;
3314         u64 intercept;
3315
3316         intercept = svm->nested.intercept;
3317
3318         if (!is_guest_mode(&svm->vcpu) ||
3319             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3320                 return false;
3321
3322         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3323         val &= ~SVM_CR0_SELECTIVE_MASK;
3324
3325         if (cr0 ^ val) {
3326                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3327                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3328         }
3329
3330         return ret;
3331 }
3332
3333 #define CR_VALID (1ULL << 63)
3334
3335 static int cr_interception(struct vcpu_svm *svm)
3336 {
3337         int reg, cr;
3338         unsigned long val;
3339         int err;
3340
3341         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3342                 return emulate_on_interception(svm);
3343
3344         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3345                 return emulate_on_interception(svm);
3346
3347         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3348         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3349                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3350         else
3351                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3352
3353         err = 0;
3354         if (cr >= 16) { /* mov to cr */
3355                 cr -= 16;
3356                 val = kvm_register_read(&svm->vcpu, reg);
3357                 switch (cr) {
3358                 case 0:
3359                         if (!check_selective_cr0_intercepted(svm, val))
3360                                 err = kvm_set_cr0(&svm->vcpu, val);
3361                         else
3362                                 return 1;
3363
3364                         break;
3365                 case 3:
3366                         err = kvm_set_cr3(&svm->vcpu, val);
3367                         break;
3368                 case 4:
3369                         err = kvm_set_cr4(&svm->vcpu, val);
3370                         break;
3371                 case 8:
3372                         err = kvm_set_cr8(&svm->vcpu, val);
3373                         break;
3374                 default:
3375                         WARN(1, "unhandled write to CR%d", cr);
3376                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3377                         return 1;
3378                 }
3379         } else { /* mov from cr */
3380                 switch (cr) {
3381                 case 0:
3382                         val = kvm_read_cr0(&svm->vcpu);
3383                         break;
3384                 case 2:
3385                         val = svm->vcpu.arch.cr2;
3386                         break;
3387                 case 3:
3388                         val = kvm_read_cr3(&svm->vcpu);
3389                         break;
3390                 case 4:
3391                         val = kvm_read_cr4(&svm->vcpu);
3392                         break;
3393                 case 8:
3394                         val = kvm_get_cr8(&svm->vcpu);
3395                         break;
3396                 default:
3397                         WARN(1, "unhandled read from CR%d", cr);
3398                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3399                         return 1;
3400                 }
3401                 kvm_register_write(&svm->vcpu, reg, val);
3402         }
3403         return kvm_complete_insn_gp(&svm->vcpu, err);
3404 }
3405
3406 static int dr_interception(struct vcpu_svm *svm)
3407 {
3408         int reg, dr;
3409         unsigned long val;
3410
3411         if (svm->vcpu.guest_debug == 0) {
3412                 /*
3413                  * No more DR vmexits; force a reload of the debug registers
3414                  * and reenter on this instruction.  The next vmexit will
3415                  * retrieve the full state of the debug registers.
3416                  */
3417                 clr_dr_intercepts(svm);
3418                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3419                 return 1;
3420         }
3421
3422         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3423                 return emulate_on_interception(svm);
3424
3425         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3426         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3427
3428         if (dr >= 16) { /* mov to DRn */
3429                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3430                         return 1;
3431                 val = kvm_register_read(&svm->vcpu, reg);
3432                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3433         } else {
3434                 if (!kvm_require_dr(&svm->vcpu, dr))
3435                         return 1;
3436                 kvm_get_dr(&svm->vcpu, dr, &val);
3437                 kvm_register_write(&svm->vcpu, reg, val);
3438         }
3439
3440         skip_emulated_instruction(&svm->vcpu);
3441
3442         return 1;
3443 }
3444
3445 static int cr8_write_interception(struct vcpu_svm *svm)
3446 {
3447         struct kvm_run *kvm_run = svm->vcpu.run;
3448         int r;
3449
3450         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3451         /* instruction emulation calls kvm_set_cr8() */
3452         r = cr_interception(svm);
3453         if (lapic_in_kernel(&svm->vcpu))
3454                 return r;
3455         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3456                 return r;
3457         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3458         return 0;
3459 }
3460
3461 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3462 {
3463         struct vcpu_svm *svm = to_svm(vcpu);
3464
3465         switch (msr_info->index) {
3466         case MSR_IA32_TSC: {
3467                 msr_info->data = svm->vmcb->control.tsc_offset +
3468                         kvm_scale_tsc(vcpu, rdtsc());
3469
3470                 break;
3471         }
3472         case MSR_STAR:
3473                 msr_info->data = svm->vmcb->save.star;
3474                 break;
3475 #ifdef CONFIG_X86_64
3476         case MSR_LSTAR:
3477                 msr_info->data = svm->vmcb->save.lstar;
3478                 break;
3479         case MSR_CSTAR:
3480                 msr_info->data = svm->vmcb->save.cstar;
3481                 break;
3482         case MSR_KERNEL_GS_BASE:
3483                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3484                 break;
3485         case MSR_SYSCALL_MASK:
3486                 msr_info->data = svm->vmcb->save.sfmask;
3487                 break;
3488 #endif
3489         case MSR_IA32_SYSENTER_CS:
3490                 msr_info->data = svm->vmcb->save.sysenter_cs;
3491                 break;
3492         case MSR_IA32_SYSENTER_EIP:
3493                 msr_info->data = svm->sysenter_eip;
3494                 break;
3495         case MSR_IA32_SYSENTER_ESP:
3496                 msr_info->data = svm->sysenter_esp;
3497                 break;
3498         case MSR_TSC_AUX:
3499                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3500                         return 1;
3501                 msr_info->data = svm->tsc_aux;
3502                 break;
3503         /*
3504          * Nobody will change the following 5 values in the VMCB so we can
3505          * safely return them on rdmsr. They will always be 0 until LBRV is
3506          * implemented.
3507          */
3508         case MSR_IA32_DEBUGCTLMSR:
3509                 msr_info->data = svm->vmcb->save.dbgctl;
3510                 break;
3511         case MSR_IA32_LASTBRANCHFROMIP:
3512                 msr_info->data = svm->vmcb->save.br_from;
3513                 break;
3514         case MSR_IA32_LASTBRANCHTOIP:
3515                 msr_info->data = svm->vmcb->save.br_to;
3516                 break;
3517         case MSR_IA32_LASTINTFROMIP:
3518                 msr_info->data = svm->vmcb->save.last_excp_from;
3519                 break;
3520         case MSR_IA32_LASTINTTOIP:
3521                 msr_info->data = svm->vmcb->save.last_excp_to;
3522                 break;
3523         case MSR_VM_HSAVE_PA:
3524                 msr_info->data = svm->nested.hsave_msr;
3525                 break;
3526         case MSR_VM_CR:
3527                 msr_info->data = svm->nested.vm_cr_msr;
3528                 break;
3529         case MSR_IA32_UCODE_REV:
3530                 msr_info->data = 0x01000065;
3531                 break;
3532         case MSR_F15H_IC_CFG: {
3533
3534                 int family, model;
3535
3536                 family = guest_cpuid_family(vcpu);
3537                 model  = guest_cpuid_model(vcpu);
3538
3539                 if (family < 0 || model < 0)
3540                         return kvm_get_msr_common(vcpu, msr_info);
3541
3542                 msr_info->data = 0;
3543
3544                 if (family == 0x15 &&
3545                     (model >= 0x2 && model < 0x20))
3546                         msr_info->data = 0x1E;
3547                 }
3548                 break;
3549         default:
3550                 return kvm_get_msr_common(vcpu, msr_info);
3551         }
3552         return 0;
3553 }
3554
3555 static int rdmsr_interception(struct vcpu_svm *svm)
3556 {
3557         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3558         struct msr_data msr_info;
3559
3560         msr_info.index = ecx;
3561         msr_info.host_initiated = false;
3562         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3563                 trace_kvm_msr_read_ex(ecx);
3564                 kvm_inject_gp(&svm->vcpu, 0);
3565         } else {
3566                 trace_kvm_msr_read(ecx, msr_info.data);
3567
3568                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3569                                    msr_info.data & 0xffffffff);
3570                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3571                                    msr_info.data >> 32);
3572                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3573                 skip_emulated_instruction(&svm->vcpu);
3574         }
3575         return 1;
3576 }
3577
3578 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3579 {
3580         struct vcpu_svm *svm = to_svm(vcpu);
3581         int svm_dis, chg_mask;
3582
3583         if (data & ~SVM_VM_CR_VALID_MASK)
3584                 return 1;
3585
3586         chg_mask = SVM_VM_CR_VALID_MASK;
3587
3588         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3589                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3590
3591         svm->nested.vm_cr_msr &= ~chg_mask;
3592         svm->nested.vm_cr_msr |= (data & chg_mask);
3593
3594         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3595
3596         /* check for svm_disable while efer.svme is set */
3597         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3598                 return 1;
3599
3600         return 0;
3601 }
3602
3603 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3604 {
3605         struct vcpu_svm *svm = to_svm(vcpu);
3606
3607         u32 ecx = msr->index;
3608         u64 data = msr->data;
3609         switch (ecx) {
3610         case MSR_IA32_TSC:
3611                 kvm_write_tsc(vcpu, msr);
3612                 break;
3613         case MSR_STAR:
3614                 svm->vmcb->save.star = data;
3615                 break;
3616 #ifdef CONFIG_X86_64
3617         case MSR_LSTAR:
3618                 svm->vmcb->save.lstar = data;
3619                 break;
3620         case MSR_CSTAR:
3621                 svm->vmcb->save.cstar = data;
3622                 break;
3623         case MSR_KERNEL_GS_BASE:
3624                 svm->vmcb->save.kernel_gs_base = data;
3625                 break;
3626         case MSR_SYSCALL_MASK:
3627                 svm->vmcb->save.sfmask = data;
3628                 break;
3629 #endif
3630         case MSR_IA32_SYSENTER_CS:
3631                 svm->vmcb->save.sysenter_cs = data;
3632                 break;
3633         case MSR_IA32_SYSENTER_EIP:
3634                 svm->sysenter_eip = data;
3635                 svm->vmcb->save.sysenter_eip = data;
3636                 break;
3637         case MSR_IA32_SYSENTER_ESP:
3638                 svm->sysenter_esp = data;
3639                 svm->vmcb->save.sysenter_esp = data;
3640                 break;
3641         case MSR_TSC_AUX:
3642                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3643                         return 1;
3644
3645                 /*
3646                  * This is rare, so we update the MSR here instead of using
3647                  * direct_access_msrs.  Doing that would require a rdmsr in
3648                  * svm_vcpu_put.
3649                  */
3650                 svm->tsc_aux = data;
3651                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3652                 break;
3653         case MSR_IA32_DEBUGCTLMSR:
3654                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3655                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3656                                     __func__, data);
3657                         break;
3658                 }
3659                 if (data & DEBUGCTL_RESERVED_BITS)
3660                         return 1;
3661
3662                 svm->vmcb->save.dbgctl = data;
3663                 mark_dirty(svm->vmcb, VMCB_LBR);
3664                 if (data & (1ULL<<0))
3665                         svm_enable_lbrv(svm);
3666                 else
3667                         svm_disable_lbrv(svm);
3668                 break;
3669         case MSR_VM_HSAVE_PA:
3670                 svm->nested.hsave_msr = data;
3671                 break;
3672         case MSR_VM_CR:
3673                 return svm_set_vm_cr(vcpu, data);
3674         case MSR_VM_IGNNE:
3675                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3676                 break;
3677         case MSR_IA32_APICBASE:
3678                 if (kvm_vcpu_apicv_active(vcpu))
3679                         avic_update_vapic_bar(to_svm(vcpu), data);
3680                 /* Follow through */
3681         default:
3682                 return kvm_set_msr_common(vcpu, msr);
3683         }
3684         return 0;
3685 }
3686
3687 static int wrmsr_interception(struct vcpu_svm *svm)
3688 {
3689         struct msr_data msr;
3690         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3691         u64 data = kvm_read_edx_eax(&svm->vcpu);
3692
3693         msr.data = data;
3694         msr.index = ecx;
3695         msr.host_initiated = false;
3696
3697         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3698         if (kvm_set_msr(&svm->vcpu, &msr)) {
3699                 trace_kvm_msr_write_ex(ecx, data);
3700                 kvm_inject_gp(&svm->vcpu, 0);
3701         } else {
3702                 trace_kvm_msr_write(ecx, data);
3703                 skip_emulated_instruction(&svm->vcpu);
3704         }
3705         return 1;
3706 }
3707
3708 static int msr_interception(struct vcpu_svm *svm)
3709 {
3710         if (svm->vmcb->control.exit_info_1)
3711                 return wrmsr_interception(svm);
3712         else
3713                 return rdmsr_interception(svm);
3714 }
3715
3716 static int interrupt_window_interception(struct vcpu_svm *svm)
3717 {
3718         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3719         svm_clear_vintr(svm);
3720         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3721         mark_dirty(svm->vmcb, VMCB_INTR);
3722         ++svm->vcpu.stat.irq_window_exits;
3723         return 1;
3724 }
3725
3726 static int pause_interception(struct vcpu_svm *svm)
3727 {
3728         kvm_vcpu_on_spin(&(svm->vcpu));
3729         return 1;
3730 }
3731
3732 static int nop_interception(struct vcpu_svm *svm)
3733 {
3734         skip_emulated_instruction(&(svm->vcpu));
3735         return 1;
3736 }
3737
3738 static int monitor_interception(struct vcpu_svm *svm)
3739 {
3740         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3741         return nop_interception(svm);
3742 }
3743
3744 static int mwait_interception(struct vcpu_svm *svm)
3745 {
3746         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3747         return nop_interception(svm);
3748 }
3749
3750 enum avic_ipi_failure_cause {
3751         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3752         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3753         AVIC_IPI_FAILURE_INVALID_TARGET,
3754         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3755 };
3756
3757 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3758 {
3759         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3760         u32 icrl = svm->vmcb->control.exit_info_1;
3761         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3762         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3763         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3764
3765         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3766
3767         switch (id) {
3768         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3769                 /*
3770                  * AVIC hardware handles the generation of
3771                  * IPIs when the specified Message Type is Fixed
3772                  * (also known as fixed delivery mode) and
3773                  * the Trigger Mode is edge-triggered. The hardware
3774                  * also supports self and broadcast delivery modes
3775                  * specified via the Destination Shorthand(DSH)
3776                  * field of the ICRL. Logical and physical APIC ID
3777                  * formats are supported. All other IPI types cause
3778                  * a #VMEXIT, which needs to emulated.
3779                  */
3780                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3781                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3782                 break;
3783         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3784                 int i;
3785                 struct kvm_vcpu *vcpu;
3786                 struct kvm *kvm = svm->vcpu.kvm;
3787                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3788
3789                 /*
3790                  * At this point, we expect that the AVIC HW has already
3791                  * set the appropriate IRR bits on the valid target
3792                  * vcpus. So, we just need to kick the appropriate vcpu.
3793                  */
3794                 kvm_for_each_vcpu(i, vcpu, kvm) {
3795                         bool m = kvm_apic_match_dest(vcpu, apic,
3796                                                      icrl & KVM_APIC_SHORT_MASK,
3797                                                      GET_APIC_DEST_FIELD(icrh),
3798                                                      icrl & KVM_APIC_DEST_MASK);
3799
3800                         if (m && !avic_vcpu_is_running(vcpu))
3801                                 kvm_vcpu_wake_up(vcpu);
3802                 }
3803                 break;
3804         }
3805         case AVIC_IPI_FAILURE_INVALID_TARGET:
3806                 break;
3807         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3808                 WARN_ONCE(1, "Invalid backing page\n");
3809                 break;
3810         default:
3811                 pr_err("Unknown IPI interception\n");
3812         }
3813
3814         return 1;
3815 }
3816
3817 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3818 {
3819         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3820         int index;
3821         u32 *logical_apic_id_table;
3822         int dlid = GET_APIC_LOGICAL_ID(ldr);
3823
3824         if (!dlid)
3825                 return NULL;
3826
3827         if (flat) { /* flat */
3828                 index = ffs(dlid) - 1;
3829                 if (index > 7)
3830                         return NULL;
3831         } else { /* cluster */
3832                 int cluster = (dlid & 0xf0) >> 4;
3833                 int apic = ffs(dlid & 0x0f) - 1;
3834
3835                 if ((apic < 0) || (apic > 7) ||
3836                     (cluster >= 0xf))
3837                         return NULL;
3838                 index = (cluster << 2) + apic;
3839         }
3840
3841         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3842
3843         return &logical_apic_id_table[index];
3844 }
3845
3846 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3847                           bool valid)
3848 {
3849         bool flat;
3850         u32 *entry, new_entry;
3851
3852         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3853         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3854         if (!entry)
3855                 return -EINVAL;
3856
3857         new_entry = READ_ONCE(*entry);
3858         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3859         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3860         if (valid)
3861                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3862         else
3863                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3864         WRITE_ONCE(*entry, new_entry);
3865
3866         return 0;
3867 }
3868
3869 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3870 {
3871         int ret;
3872         struct vcpu_svm *svm = to_svm(vcpu);
3873         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3874
3875         if (!ldr)
3876                 return 1;
3877
3878         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3879         if (ret && svm->ldr_reg) {
3880                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3881                 svm->ldr_reg = 0;
3882         } else {
3883                 svm->ldr_reg = ldr;
3884         }
3885         return ret;
3886 }
3887
3888 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3889 {
3890         u64 *old, *new;
3891         struct vcpu_svm *svm = to_svm(vcpu);
3892         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3893         u32 id = (apic_id_reg >> 24) & 0xff;
3894
3895         if (vcpu->vcpu_id == id)
3896                 return 0;
3897
3898         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3899         new = avic_get_physical_id_entry(vcpu, id);
3900         if (!new || !old)
3901                 return 1;
3902
3903         /* We need to move physical_id_entry to new offset */
3904         *new = *old;
3905         *old = 0ULL;
3906         to_svm(vcpu)->avic_physical_id_cache = new;
3907
3908         /*
3909          * Also update the guest physical APIC ID in the logical
3910          * APIC ID table entry if already setup the LDR.
3911          */
3912         if (svm->ldr_reg)
3913                 avic_handle_ldr_update(vcpu);
3914
3915         return 0;
3916 }
3917
3918 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3919 {
3920         struct vcpu_svm *svm = to_svm(vcpu);
3921         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3922         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3923         u32 mod = (dfr >> 28) & 0xf;
3924
3925         /*
3926          * We assume that all local APICs are using the same type.
3927          * If this changes, we need to flush the AVIC logical
3928          * APID id table.
3929          */
3930         if (vm_data->ldr_mode == mod)
3931                 return 0;
3932
3933         clear_page(page_address(vm_data->avic_logical_id_table_page));
3934         vm_data->ldr_mode = mod;
3935
3936         if (svm->ldr_reg)
3937                 avic_handle_ldr_update(vcpu);
3938         return 0;
3939 }
3940
3941 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3942 {
3943         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3944         u32 offset = svm->vmcb->control.exit_info_1 &
3945                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3946
3947         switch (offset) {
3948         case APIC_ID:
3949                 if (avic_handle_apic_id_update(&svm->vcpu))
3950                         return 0;
3951                 break;
3952         case APIC_LDR:
3953                 if (avic_handle_ldr_update(&svm->vcpu))
3954                         return 0;
3955                 break;
3956         case APIC_DFR:
3957                 avic_handle_dfr_update(&svm->vcpu);
3958                 break;
3959         default:
3960                 break;
3961         }
3962
3963         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3964
3965         return 1;
3966 }
3967
3968 static bool is_avic_unaccelerated_access_trap(u32 offset)
3969 {
3970         bool ret = false;
3971
3972         switch (offset) {
3973         case APIC_ID:
3974         case APIC_EOI:
3975         case APIC_RRR:
3976         case APIC_LDR:
3977         case APIC_DFR:
3978         case APIC_SPIV:
3979         case APIC_ESR:
3980         case APIC_ICR:
3981         case APIC_LVTT:
3982         case APIC_LVTTHMR:
3983         case APIC_LVTPC:
3984         case APIC_LVT0:
3985         case APIC_LVT1:
3986         case APIC_LVTERR:
3987         case APIC_TMICT:
3988         case APIC_TDCR:
3989                 ret = true;
3990                 break;
3991         default:
3992                 break;
3993         }
3994         return ret;
3995 }
3996
3997 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3998 {
3999         int ret = 0;
4000         u32 offset = svm->vmcb->control.exit_info_1 &
4001                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4002         u32 vector = svm->vmcb->control.exit_info_2 &
4003                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4004         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4005                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4006         bool trap = is_avic_unaccelerated_access_trap(offset);
4007
4008         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4009                                             trap, write, vector);
4010         if (trap) {
4011                 /* Handling Trap */
4012                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4013                 ret = avic_unaccel_trap_write(svm);
4014         } else {
4015                 /* Handling Fault */
4016                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4017         }
4018
4019         return ret;
4020 }
4021
4022 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4023         [SVM_EXIT_READ_CR0]                     = cr_interception,
4024         [SVM_EXIT_READ_CR3]                     = cr_interception,
4025         [SVM_EXIT_READ_CR4]                     = cr_interception,
4026         [SVM_EXIT_READ_CR8]                     = cr_interception,
4027         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4028         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4029         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4030         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4031         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4032         [SVM_EXIT_READ_DR0]                     = dr_interception,
4033         [SVM_EXIT_READ_DR1]                     = dr_interception,
4034         [SVM_EXIT_READ_DR2]                     = dr_interception,
4035         [SVM_EXIT_READ_DR3]                     = dr_interception,
4036         [SVM_EXIT_READ_DR4]                     = dr_interception,
4037         [SVM_EXIT_READ_DR5]                     = dr_interception,
4038         [SVM_EXIT_READ_DR6]                     = dr_interception,
4039         [SVM_EXIT_READ_DR7]                     = dr_interception,
4040         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4041         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4042         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4043         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4044         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4045         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4046         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4047         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4048         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4049         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4050         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4051         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4052         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4053         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4054         [SVM_EXIT_INTR]                         = intr_interception,
4055         [SVM_EXIT_NMI]                          = nmi_interception,
4056         [SVM_EXIT_SMI]                          = nop_on_interception,
4057         [SVM_EXIT_INIT]                         = nop_on_interception,
4058         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4059         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4060         [SVM_EXIT_CPUID]                        = cpuid_interception,
4061         [SVM_EXIT_IRET]                         = iret_interception,
4062         [SVM_EXIT_INVD]                         = emulate_on_interception,
4063         [SVM_EXIT_PAUSE]                        = pause_interception,
4064         [SVM_EXIT_HLT]                          = halt_interception,
4065         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4066         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4067         [SVM_EXIT_IOIO]                         = io_interception,
4068         [SVM_EXIT_MSR]                          = msr_interception,
4069         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4070         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4071         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4072         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4073         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4074         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4075         [SVM_EXIT_STGI]                         = stgi_interception,
4076         [SVM_EXIT_CLGI]                         = clgi_interception,
4077         [SVM_EXIT_SKINIT]                       = skinit_interception,
4078         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4079         [SVM_EXIT_MONITOR]                      = monitor_interception,
4080         [SVM_EXIT_MWAIT]                        = mwait_interception,
4081         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4082         [SVM_EXIT_NPF]                          = pf_interception,
4083         [SVM_EXIT_RSM]                          = emulate_on_interception,
4084         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4085         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4086 };
4087
4088 static void dump_vmcb(struct kvm_vcpu *vcpu)
4089 {
4090         struct vcpu_svm *svm = to_svm(vcpu);
4091         struct vmcb_control_area *control = &svm->vmcb->control;
4092         struct vmcb_save_area *save = &svm->vmcb->save;
4093
4094         pr_err("VMCB Control Area:\n");
4095         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4096         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4097         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4098         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4099         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4100         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4101         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4102         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4103         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4104         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4105         pr_err("%-20s%d\n", "asid:", control->asid);
4106         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4107         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4108         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4109         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4110         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4111         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4112         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4113         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4114         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4115         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4116         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4117         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4118         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4119         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4120         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4121         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4122         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4123         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4124         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4125         pr_err("VMCB State Save Area:\n");
4126         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4127                "es:",
4128                save->es.selector, save->es.attrib,
4129                save->es.limit, save->es.base);
4130         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4131                "cs:",
4132                save->cs.selector, save->cs.attrib,
4133                save->cs.limit, save->cs.base);
4134         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4135                "ss:",
4136                save->ss.selector, save->ss.attrib,
4137                save->ss.limit, save->ss.base);
4138         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4139                "ds:",
4140                save->ds.selector, save->ds.attrib,
4141                save->ds.limit, save->ds.base);
4142         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4143                "fs:",
4144                save->fs.selector, save->fs.attrib,
4145                save->fs.limit, save->fs.base);
4146         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4147                "gs:",
4148                save->gs.selector, save->gs.attrib,
4149                save->gs.limit, save->gs.base);
4150         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4151                "gdtr:",
4152                save->gdtr.selector, save->gdtr.attrib,
4153                save->gdtr.limit, save->gdtr.base);
4154         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4155                "ldtr:",
4156                save->ldtr.selector, save->ldtr.attrib,
4157                save->ldtr.limit, save->ldtr.base);
4158         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4159                "idtr:",
4160                save->idtr.selector, save->idtr.attrib,
4161                save->idtr.limit, save->idtr.base);
4162         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4163                "tr:",
4164                save->tr.selector, save->tr.attrib,
4165                save->tr.limit, save->tr.base);
4166         pr_err("cpl:            %d                efer:         %016llx\n",
4167                 save->cpl, save->efer);
4168         pr_err("%-15s %016llx %-13s %016llx\n",
4169                "cr0:", save->cr0, "cr2:", save->cr2);
4170         pr_err("%-15s %016llx %-13s %016llx\n",
4171                "cr3:", save->cr3, "cr4:", save->cr4);
4172         pr_err("%-15s %016llx %-13s %016llx\n",
4173                "dr6:", save->dr6, "dr7:", save->dr7);
4174         pr_err("%-15s %016llx %-13s %016llx\n",
4175                "rip:", save->rip, "rflags:", save->rflags);
4176         pr_err("%-15s %016llx %-13s %016llx\n",
4177                "rsp:", save->rsp, "rax:", save->rax);
4178         pr_err("%-15s %016llx %-13s %016llx\n",
4179                "star:", save->star, "lstar:", save->lstar);
4180         pr_err("%-15s %016llx %-13s %016llx\n",
4181                "cstar:", save->cstar, "sfmask:", save->sfmask);
4182         pr_err("%-15s %016llx %-13s %016llx\n",
4183                "kernel_gs_base:", save->kernel_gs_base,
4184                "sysenter_cs:", save->sysenter_cs);
4185         pr_err("%-15s %016llx %-13s %016llx\n",
4186                "sysenter_esp:", save->sysenter_esp,
4187                "sysenter_eip:", save->sysenter_eip);
4188         pr_err("%-15s %016llx %-13s %016llx\n",
4189                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4190         pr_err("%-15s %016llx %-13s %016llx\n",
4191                "br_from:", save->br_from, "br_to:", save->br_to);
4192         pr_err("%-15s %016llx %-13s %016llx\n",
4193                "excp_from:", save->last_excp_from,
4194                "excp_to:", save->last_excp_to);
4195 }
4196
4197 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4198 {
4199         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4200
4201         *info1 = control->exit_info_1;
4202         *info2 = control->exit_info_2;
4203 }
4204
4205 static int handle_exit(struct kvm_vcpu *vcpu)
4206 {
4207         struct vcpu_svm *svm = to_svm(vcpu);
4208         struct kvm_run *kvm_run = vcpu->run;
4209         u32 exit_code = svm->vmcb->control.exit_code;
4210
4211         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4212
4213         vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4214
4215         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4216                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4217         if (npt_enabled)
4218                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4219
4220         if (unlikely(svm->nested.exit_required)) {
4221                 nested_svm_vmexit(svm);
4222                 svm->nested.exit_required = false;
4223
4224                 return 1;
4225         }
4226
4227         if (is_guest_mode(vcpu)) {
4228                 int vmexit;
4229
4230                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4231                                         svm->vmcb->control.exit_info_1,
4232                                         svm->vmcb->control.exit_info_2,
4233                                         svm->vmcb->control.exit_int_info,
4234                                         svm->vmcb->control.exit_int_info_err,
4235                                         KVM_ISA_SVM);
4236
4237                 vmexit = nested_svm_exit_special(svm);
4238
4239                 if (vmexit == NESTED_EXIT_CONTINUE)
4240                         vmexit = nested_svm_exit_handled(svm);
4241
4242                 if (vmexit == NESTED_EXIT_DONE)
4243                         return 1;
4244         }
4245
4246         svm_complete_interrupts(svm);
4247
4248         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4249                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4250                 kvm_run->fail_entry.hardware_entry_failure_reason
4251                         = svm->vmcb->control.exit_code;
4252                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4253                 dump_vmcb(vcpu);
4254                 return 0;
4255         }
4256
4257         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4258             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4259             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4260             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4261                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4262                        "exit_code 0x%x\n",
4263                        __func__, svm->vmcb->control.exit_int_info,
4264                        exit_code);
4265
4266         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4267             || !svm_exit_handlers[exit_code]) {
4268                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4269                 kvm_queue_exception(vcpu, UD_VECTOR);
4270                 return 1;
4271         }
4272
4273         return svm_exit_handlers[exit_code](svm);
4274 }
4275
4276 static void reload_tss(struct kvm_vcpu *vcpu)
4277 {
4278         int cpu = raw_smp_processor_id();
4279
4280         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4281         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4282         load_TR_desc();
4283 }
4284
4285 static void pre_svm_run(struct vcpu_svm *svm)
4286 {
4287         int cpu = raw_smp_processor_id();
4288
4289         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4290
4291         /* FIXME: handle wraparound of asid_generation */
4292         if (svm->asid_generation != sd->asid_generation)
4293                 new_asid(svm, sd);
4294 }
4295
4296 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4297 {
4298         struct vcpu_svm *svm = to_svm(vcpu);
4299
4300         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4301         vcpu->arch.hflags |= HF_NMI_MASK;
4302         set_intercept(svm, INTERCEPT_IRET);
4303         ++vcpu->stat.nmi_injections;
4304 }
4305
4306 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4307 {
4308         struct vmcb_control_area *control;
4309
4310         /* The following fields are ignored when AVIC is enabled */
4311         control = &svm->vmcb->control;
4312         control->int_vector = irq;
4313         control->int_ctl &= ~V_INTR_PRIO_MASK;
4314         control->int_ctl |= V_IRQ_MASK |
4315                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4316         mark_dirty(svm->vmcb, VMCB_INTR);
4317 }
4318
4319 static void svm_set_irq(struct kvm_vcpu *vcpu)
4320 {
4321         struct vcpu_svm *svm = to_svm(vcpu);
4322
4323         BUG_ON(!(gif_set(svm)));
4324
4325         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4326         ++vcpu->stat.irq_injections;
4327
4328         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4329                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4330 }
4331
4332 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4333 {
4334         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4335 }
4336
4337 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4338 {
4339         struct vcpu_svm *svm = to_svm(vcpu);
4340
4341         if (svm_nested_virtualize_tpr(vcpu) ||
4342             kvm_vcpu_apicv_active(vcpu))
4343                 return;
4344
4345         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4346
4347         if (irr == -1)
4348                 return;
4349
4350         if (tpr >= irr)
4351                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4352 }
4353
4354 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4355 {
4356         return;
4357 }
4358
4359 static bool svm_get_enable_apicv(void)
4360 {
4361         return avic;
4362 }
4363
4364 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4365 {
4366 }
4367
4368 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4369 {
4370 }
4371
4372 /* Note: Currently only used by Hyper-V. */
4373 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4374 {
4375         struct vcpu_svm *svm = to_svm(vcpu);
4376         struct vmcb *vmcb = svm->vmcb;
4377
4378         if (!avic)
4379                 return;
4380
4381         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4382         mark_dirty(vmcb, VMCB_INTR);
4383 }
4384
4385 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4386 {
4387         return;
4388 }
4389
4390 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4391 {
4392         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4393         smp_mb__after_atomic();
4394
4395         if (avic_vcpu_is_running(vcpu))
4396                 wrmsrl(SVM_AVIC_DOORBELL,
4397                        kvm_cpu_get_apicid(vcpu->cpu));
4398         else
4399                 kvm_vcpu_wake_up(vcpu);
4400 }
4401
4402 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4403 {
4404         unsigned long flags;
4405         struct amd_svm_iommu_ir *cur;
4406
4407         spin_lock_irqsave(&svm->ir_list_lock, flags);
4408         list_for_each_entry(cur, &svm->ir_list, node) {
4409                 if (cur->data != pi->ir_data)
4410                         continue;
4411                 list_del(&cur->node);
4412                 kfree(cur);
4413                 break;
4414         }
4415         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4416 }
4417
4418 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4419 {
4420         int ret = 0;
4421         unsigned long flags;
4422         struct amd_svm_iommu_ir *ir;
4423
4424         /**
4425          * In some cases, the existing irte is updaed and re-set,
4426          * so we need to check here if it's already been * added
4427          * to the ir_list.
4428          */
4429         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4430                 struct kvm *kvm = svm->vcpu.kvm;
4431                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4432                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4433                 struct vcpu_svm *prev_svm;
4434
4435                 if (!prev_vcpu) {
4436                         ret = -EINVAL;
4437                         goto out;
4438                 }
4439
4440                 prev_svm = to_svm(prev_vcpu);
4441                 svm_ir_list_del(prev_svm, pi);
4442         }
4443
4444         /**
4445          * Allocating new amd_iommu_pi_data, which will get
4446          * add to the per-vcpu ir_list.
4447          */
4448         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4449         if (!ir) {
4450                 ret = -ENOMEM;
4451                 goto out;
4452         }
4453         ir->data = pi->ir_data;
4454
4455         spin_lock_irqsave(&svm->ir_list_lock, flags);
4456         list_add(&ir->node, &svm->ir_list);
4457         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4458 out:
4459         return ret;
4460 }
4461
4462 /**
4463  * Note:
4464  * The HW cannot support posting multicast/broadcast
4465  * interrupts to a vCPU. So, we still use legacy interrupt
4466  * remapping for these kind of interrupts.
4467  *
4468  * For lowest-priority interrupts, we only support
4469  * those with single CPU as the destination, e.g. user
4470  * configures the interrupts via /proc/irq or uses
4471  * irqbalance to make the interrupts single-CPU.
4472  */
4473 static int
4474 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4475                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4476 {
4477         struct kvm_lapic_irq irq;
4478         struct kvm_vcpu *vcpu = NULL;
4479
4480         kvm_set_msi_irq(kvm, e, &irq);
4481
4482         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4483                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4484                          __func__, irq.vector);
4485                 return -1;
4486         }
4487
4488         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4489                  irq.vector);
4490         *svm = to_svm(vcpu);
4491         vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4492         vcpu_info->vector = irq.vector;
4493
4494         return 0;
4495 }
4496
4497 /*
4498  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4499  *
4500  * @kvm: kvm
4501  * @host_irq: host irq of the interrupt
4502  * @guest_irq: gsi of the interrupt
4503  * @set: set or unset PI
4504  * returns 0 on success, < 0 on failure
4505  */
4506 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4507                               uint32_t guest_irq, bool set)
4508 {
4509         struct kvm_kernel_irq_routing_entry *e;
4510         struct kvm_irq_routing_table *irq_rt;
4511         int idx, ret = -EINVAL;
4512
4513         if (!kvm_arch_has_assigned_device(kvm) ||
4514             !irq_remapping_cap(IRQ_POSTING_CAP))
4515                 return 0;
4516
4517         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4518                  __func__, host_irq, guest_irq, set);
4519
4520         idx = srcu_read_lock(&kvm->irq_srcu);
4521         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4522         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4523
4524         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4525                 struct vcpu_data vcpu_info;
4526                 struct vcpu_svm *svm = NULL;
4527
4528                 if (e->type != KVM_IRQ_ROUTING_MSI)
4529                         continue;
4530
4531                 /**
4532                  * Here, we setup with legacy mode in the following cases:
4533                  * 1. When cannot target interrupt to a specific vcpu.
4534                  * 2. Unsetting posted interrupt.
4535                  * 3. APIC virtialization is disabled for the vcpu.
4536                  */
4537                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4538                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4539                         struct amd_iommu_pi_data pi;
4540
4541                         /* Try to enable guest_mode in IRTE */
4542                         pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4543                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4544                                                      svm->vcpu.vcpu_id);
4545                         pi.is_guest_mode = true;
4546                         pi.vcpu_data = &vcpu_info;
4547                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4548
4549                         /**
4550                          * Here, we successfully setting up vcpu affinity in
4551                          * IOMMU guest mode. Now, we need to store the posted
4552                          * interrupt information in a per-vcpu ir_list so that
4553                          * we can reference to them directly when we update vcpu
4554                          * scheduling information in IOMMU irte.
4555                          */
4556                         if (!ret && pi.is_guest_mode)
4557                                 svm_ir_list_add(svm, &pi);
4558                 } else {
4559                         /* Use legacy mode in IRTE */
4560                         struct amd_iommu_pi_data pi;
4561
4562                         /**
4563                          * Here, pi is used to:
4564                          * - Tell IOMMU to use legacy mode for this interrupt.
4565                          * - Retrieve ga_tag of prior interrupt remapping data.
4566                          */
4567                         pi.is_guest_mode = false;
4568                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4569
4570                         /**
4571                          * Check if the posted interrupt was previously
4572                          * setup with the guest_mode by checking if the ga_tag
4573                          * was cached. If so, we need to clean up the per-vcpu
4574                          * ir_list.
4575                          */
4576                         if (!ret && pi.prev_ga_tag) {
4577                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4578                                 struct kvm_vcpu *vcpu;
4579
4580                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4581                                 if (vcpu)
4582                                         svm_ir_list_del(to_svm(vcpu), &pi);
4583                         }
4584                 }
4585
4586                 if (!ret && svm) {
4587                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4588                                                  host_irq, e->gsi,
4589                                                  vcpu_info.vector,
4590                                                  vcpu_info.pi_desc_addr, set);
4591                 }
4592
4593                 if (ret < 0) {
4594                         pr_err("%s: failed to update PI IRTE\n", __func__);
4595                         goto out;
4596                 }
4597         }
4598
4599         ret = 0;
4600 out:
4601         srcu_read_unlock(&kvm->irq_srcu, idx);
4602         return ret;
4603 }
4604
4605 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4606 {
4607         struct vcpu_svm *svm = to_svm(vcpu);
4608         struct vmcb *vmcb = svm->vmcb;
4609         int ret;
4610         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4611               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4612         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4613
4614         return ret;
4615 }
4616
4617 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4618 {
4619         struct vcpu_svm *svm = to_svm(vcpu);
4620
4621         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4622 }
4623
4624 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4625 {
4626         struct vcpu_svm *svm = to_svm(vcpu);
4627
4628         if (masked) {
4629                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4630                 set_intercept(svm, INTERCEPT_IRET);
4631         } else {
4632                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4633                 clr_intercept(svm, INTERCEPT_IRET);
4634         }
4635 }
4636
4637 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4638 {
4639         struct vcpu_svm *svm = to_svm(vcpu);
4640         struct vmcb *vmcb = svm->vmcb;
4641         int ret;
4642
4643         if (!gif_set(svm) ||
4644              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4645                 return 0;
4646
4647         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4648
4649         if (is_guest_mode(vcpu))
4650                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4651
4652         return ret;
4653 }
4654
4655 static void enable_irq_window(struct kvm_vcpu *vcpu)
4656 {
4657         struct vcpu_svm *svm = to_svm(vcpu);
4658
4659         if (kvm_vcpu_apicv_active(vcpu))
4660                 return;
4661
4662         /*
4663          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4664          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4665          * get that intercept, this function will be called again though and
4666          * we'll get the vintr intercept.
4667          */
4668         if (gif_set(svm) && nested_svm_intr(svm)) {
4669                 svm_set_vintr(svm);
4670                 svm_inject_irq(svm, 0x0);
4671         }
4672 }
4673
4674 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4675 {
4676         struct vcpu_svm *svm = to_svm(vcpu);
4677
4678         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4679             == HF_NMI_MASK)
4680                 return; /* IRET will cause a vm exit */
4681
4682         if ((svm->vcpu.arch.hflags & HF_GIF_MASK) == 0)
4683                 return; /* STGI will cause a vm exit */
4684
4685         if (svm->nested.exit_required)
4686                 return; /* we're not going to run the guest yet */
4687
4688         /*
4689          * Something prevents NMI from been injected. Single step over possible
4690          * problem (IRET or exception injection or interrupt shadow)
4691          */
4692         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4693         svm->nmi_singlestep = true;
4694         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4695 }
4696
4697 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4698 {
4699         return 0;
4700 }
4701
4702 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4703 {
4704         struct vcpu_svm *svm = to_svm(vcpu);
4705
4706         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4707                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4708         else
4709                 svm->asid_generation--;
4710 }
4711
4712 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4713 {
4714 }
4715
4716 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4717 {
4718         struct vcpu_svm *svm = to_svm(vcpu);
4719
4720         if (svm_nested_virtualize_tpr(vcpu))
4721                 return;
4722
4723         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4724                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4725                 kvm_set_cr8(vcpu, cr8);
4726         }
4727 }
4728
4729 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4730 {
4731         struct vcpu_svm *svm = to_svm(vcpu);
4732         u64 cr8;
4733
4734         if (svm_nested_virtualize_tpr(vcpu) ||
4735             kvm_vcpu_apicv_active(vcpu))
4736                 return;
4737
4738         cr8 = kvm_get_cr8(vcpu);
4739         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4740         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4741 }
4742
4743 static void svm_complete_interrupts(struct vcpu_svm *svm)
4744 {
4745         u8 vector;
4746         int type;
4747         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4748         unsigned int3_injected = svm->int3_injected;
4749
4750         svm->int3_injected = 0;
4751
4752         /*
4753          * If we've made progress since setting HF_IRET_MASK, we've
4754          * executed an IRET and can allow NMI injection.
4755          */
4756         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4757             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4758                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4759                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4760         }
4761
4762         svm->vcpu.arch.nmi_injected = false;
4763         kvm_clear_exception_queue(&svm->vcpu);
4764         kvm_clear_interrupt_queue(&svm->vcpu);
4765
4766         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4767                 return;
4768
4769         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4770
4771         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4772         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4773
4774         switch (type) {
4775         case SVM_EXITINTINFO_TYPE_NMI:
4776                 svm->vcpu.arch.nmi_injected = true;
4777                 break;
4778         case SVM_EXITINTINFO_TYPE_EXEPT:
4779                 /*
4780                  * In case of software exceptions, do not reinject the vector,
4781                  * but re-execute the instruction instead. Rewind RIP first
4782                  * if we emulated INT3 before.
4783                  */
4784                 if (kvm_exception_is_soft(vector)) {
4785                         if (vector == BP_VECTOR && int3_injected &&
4786                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4787                                 kvm_rip_write(&svm->vcpu,
4788                                               kvm_rip_read(&svm->vcpu) -
4789                                               int3_injected);
4790                         break;
4791                 }
4792                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4793                         u32 err = svm->vmcb->control.exit_int_info_err;
4794                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4795
4796                 } else
4797                         kvm_requeue_exception(&svm->vcpu, vector);
4798                 break;
4799         case SVM_EXITINTINFO_TYPE_INTR:
4800                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4801                 break;
4802         default:
4803                 break;
4804         }
4805 }
4806
4807 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4808 {
4809         struct vcpu_svm *svm = to_svm(vcpu);
4810         struct vmcb_control_area *control = &svm->vmcb->control;
4811
4812         control->exit_int_info = control->event_inj;
4813         control->exit_int_info_err = control->event_inj_err;
4814         control->event_inj = 0;
4815         svm_complete_interrupts(svm);
4816 }
4817
4818 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4819 {
4820         struct vcpu_svm *svm = to_svm(vcpu);
4821
4822         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4823         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4824         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4825
4826         /*
4827          * A vmexit emulation is required before the vcpu can be executed
4828          * again.
4829          */
4830         if (unlikely(svm->nested.exit_required))
4831                 return;
4832
4833         /*
4834          * Disable singlestep if we're injecting an interrupt/exception.
4835          * We don't want our modified rflags to be pushed on the stack where
4836          * we might not be able to easily reset them if we disabled NMI
4837          * singlestep later.
4838          */
4839         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4840                 /*
4841                  * Event injection happens before external interrupts cause a
4842                  * vmexit and interrupts are disabled here, so smp_send_reschedule
4843                  * is enough to force an immediate vmexit.
4844                  */
4845                 disable_nmi_singlestep(svm);
4846                 smp_send_reschedule(vcpu->cpu);
4847         }
4848
4849         pre_svm_run(svm);
4850
4851         sync_lapic_to_cr8(vcpu);
4852
4853         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4854
4855         clgi();
4856
4857         local_irq_enable();
4858
4859         asm volatile (
4860                 "push %%" _ASM_BP "; \n\t"
4861                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4862                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4863                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4864                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4865                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4866                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4867 #ifdef CONFIG_X86_64
4868                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4869                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4870                 "mov %c[r10](%[svm]), %%r10 \n\t"
4871                 "mov %c[r11](%[svm]), %%r11 \n\t"
4872                 "mov %c[r12](%[svm]), %%r12 \n\t"
4873                 "mov %c[r13](%[svm]), %%r13 \n\t"
4874                 "mov %c[r14](%[svm]), %%r14 \n\t"
4875                 "mov %c[r15](%[svm]), %%r15 \n\t"
4876 #endif
4877
4878                 /* Enter guest mode */
4879                 "push %%" _ASM_AX " \n\t"
4880                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4881                 __ex(SVM_VMLOAD) "\n\t"
4882                 __ex(SVM_VMRUN) "\n\t"
4883                 __ex(SVM_VMSAVE) "\n\t"
4884                 "pop %%" _ASM_AX " \n\t"
4885
4886                 /* Save guest registers, load host registers */
4887                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4888                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4889                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4890                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4891                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4892                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4893 #ifdef CONFIG_X86_64
4894                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4895                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4896                 "mov %%r10, %c[r10](%[svm]) \n\t"
4897                 "mov %%r11, %c[r11](%[svm]) \n\t"
4898                 "mov %%r12, %c[r12](%[svm]) \n\t"
4899                 "mov %%r13, %c[r13](%[svm]) \n\t"
4900                 "mov %%r14, %c[r14](%[svm]) \n\t"
4901                 "mov %%r15, %c[r15](%[svm]) \n\t"
4902 #endif
4903                 "pop %%" _ASM_BP
4904                 :
4905                 : [svm]"a"(svm),
4906                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4907                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4908                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4909                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4910                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4911                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4912                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4913 #ifdef CONFIG_X86_64
4914                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4915                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4916                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4917                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4918                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4919                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4920                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4921                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4922 #endif
4923                 : "cc", "memory"
4924 #ifdef CONFIG_X86_64
4925                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4926                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4927 #else
4928                 , "ebx", "ecx", "edx", "esi", "edi"
4929 #endif
4930                 );
4931
4932 #ifdef CONFIG_X86_64
4933         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4934 #else
4935         loadsegment(fs, svm->host.fs);
4936 #ifndef CONFIG_X86_32_LAZY_GS
4937         loadsegment(gs, svm->host.gs);
4938 #endif
4939 #endif
4940
4941         reload_tss(vcpu);
4942
4943         local_irq_disable();
4944
4945         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4946         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4947         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4948         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4949
4950         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4951                 kvm_before_handle_nmi(&svm->vcpu);
4952
4953         stgi();
4954
4955         /* Any pending NMI will happen here */
4956
4957         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4958                 kvm_after_handle_nmi(&svm->vcpu);
4959
4960         sync_cr8_to_lapic(vcpu);
4961
4962         svm->next_rip = 0;
4963
4964         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4965
4966         /* if exit due to PF check for async PF */
4967         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4968                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4969
4970         if (npt_enabled) {
4971                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4972                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4973         }
4974
4975         /*
4976          * We need to handle MC intercepts here before the vcpu has a chance to
4977          * change the physical cpu
4978          */
4979         if (unlikely(svm->vmcb->control.exit_code ==
4980                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4981                 svm_handle_mce(svm);
4982
4983         mark_all_clean(svm->vmcb);
4984 }
4985 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
4986
4987 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4988 {
4989         struct vcpu_svm *svm = to_svm(vcpu);
4990
4991         svm->vmcb->save.cr3 = root;
4992         mark_dirty(svm->vmcb, VMCB_CR);
4993         svm_flush_tlb(vcpu);
4994 }
4995
4996 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4997 {
4998         struct vcpu_svm *svm = to_svm(vcpu);
4999
5000         svm->vmcb->control.nested_cr3 = root;
5001         mark_dirty(svm->vmcb, VMCB_NPT);
5002
5003         /* Also sync guest cr3 here in case we live migrate */
5004         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5005         mark_dirty(svm->vmcb, VMCB_CR);
5006
5007         svm_flush_tlb(vcpu);
5008 }
5009
5010 static int is_disabled(void)
5011 {
5012         u64 vm_cr;
5013
5014         rdmsrl(MSR_VM_CR, vm_cr);
5015         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5016                 return 1;
5017
5018         return 0;
5019 }
5020
5021 static void
5022 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5023 {
5024         /*
5025          * Patch in the VMMCALL instruction:
5026          */
5027         hypercall[0] = 0x0f;
5028         hypercall[1] = 0x01;
5029         hypercall[2] = 0xd9;
5030 }
5031
5032 static void svm_check_processor_compat(void *rtn)
5033 {
5034         *(int *)rtn = 0;
5035 }
5036
5037 static bool svm_cpu_has_accelerated_tpr(void)
5038 {
5039         return false;
5040 }
5041
5042 static bool svm_has_high_real_mode_segbase(void)
5043 {
5044         return true;
5045 }
5046
5047 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5048 {
5049         return 0;
5050 }
5051
5052 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5053 {
5054         struct vcpu_svm *svm = to_svm(vcpu);
5055         struct kvm_cpuid_entry2 *entry;
5056
5057         /* Update nrips enabled cache */
5058         svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5059
5060         if (!kvm_vcpu_apicv_active(vcpu))
5061                 return;
5062
5063         entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5064         if (entry)
5065                 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5066 }
5067
5068 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5069 {
5070         switch (func) {
5071         case 0x1:
5072                 if (avic)
5073                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5074                 break;
5075         case 0x80000001:
5076                 if (nested)
5077                         entry->ecx |= (1 << 2); /* Set SVM bit */
5078                 break;
5079         case 0x8000000A:
5080                 entry->eax = 1; /* SVM revision 1 */
5081                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5082                                    ASID emulation to nested SVM */
5083                 entry->ecx = 0; /* Reserved */
5084                 entry->edx = 0; /* Per default do not support any
5085                                    additional features */
5086
5087                 /* Support next_rip if host supports it */
5088                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5089                         entry->edx |= SVM_FEATURE_NRIP;
5090
5091                 /* Support NPT for the guest if enabled */
5092                 if (npt_enabled)
5093                         entry->edx |= SVM_FEATURE_NPT;
5094
5095                 break;
5096         }
5097 }
5098
5099 static int svm_get_lpage_level(void)
5100 {
5101         return PT_PDPE_LEVEL;
5102 }
5103
5104 static bool svm_rdtscp_supported(void)
5105 {
5106         return boot_cpu_has(X86_FEATURE_RDTSCP);
5107 }
5108
5109 static bool svm_invpcid_supported(void)
5110 {
5111         return false;
5112 }
5113
5114 static bool svm_mpx_supported(void)
5115 {
5116         return false;
5117 }
5118
5119 static bool svm_xsaves_supported(void)
5120 {
5121         return false;
5122 }
5123
5124 static bool svm_has_wbinvd_exit(void)
5125 {
5126         return true;
5127 }
5128
5129 #define PRE_EX(exit)  { .exit_code = (exit), \
5130                         .stage = X86_ICPT_PRE_EXCEPT, }
5131 #define POST_EX(exit) { .exit_code = (exit), \
5132                         .stage = X86_ICPT_POST_EXCEPT, }
5133 #define POST_MEM(exit) { .exit_code = (exit), \
5134                         .stage = X86_ICPT_POST_MEMACCESS, }
5135
5136 static const struct __x86_intercept {
5137         u32 exit_code;
5138         enum x86_intercept_stage stage;
5139 } x86_intercept_map[] = {
5140         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5141         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5142         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5143         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5144         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5145         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5146         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5147         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5148         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5149         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5150         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5151         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5152         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5153         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5154         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5155         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5156         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5157         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5158         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5159         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5160         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5161         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5162         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5163         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5164         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5165         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5166         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5167         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5168         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5169         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5170         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5171         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5172         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5173         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5174         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5175         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5176         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5177         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5178         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5179         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5180         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5181         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5182         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5183         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5184         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5185         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5186 };
5187
5188 #undef PRE_EX
5189 #undef POST_EX
5190 #undef POST_MEM
5191
5192 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5193                                struct x86_instruction_info *info,
5194                                enum x86_intercept_stage stage)
5195 {
5196         struct vcpu_svm *svm = to_svm(vcpu);
5197         int vmexit, ret = X86EMUL_CONTINUE;
5198         struct __x86_intercept icpt_info;
5199         struct vmcb *vmcb = svm->vmcb;
5200
5201         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5202                 goto out;
5203
5204         icpt_info = x86_intercept_map[info->intercept];
5205
5206         if (stage != icpt_info.stage)
5207                 goto out;
5208
5209         switch (icpt_info.exit_code) {
5210         case SVM_EXIT_READ_CR0:
5211                 if (info->intercept == x86_intercept_cr_read)
5212                         icpt_info.exit_code += info->modrm_reg;
5213                 break;
5214         case SVM_EXIT_WRITE_CR0: {
5215                 unsigned long cr0, val;
5216                 u64 intercept;
5217
5218                 if (info->intercept == x86_intercept_cr_write)
5219                         icpt_info.exit_code += info->modrm_reg;
5220
5221                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5222                     info->intercept == x86_intercept_clts)
5223                         break;
5224
5225                 intercept = svm->nested.intercept;
5226
5227                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5228                         break;
5229
5230                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5231                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5232
5233                 if (info->intercept == x86_intercept_lmsw) {
5234                         cr0 &= 0xfUL;
5235                         val &= 0xfUL;
5236                         /* lmsw can't clear PE - catch this here */
5237                         if (cr0 & X86_CR0_PE)
5238                                 val |= X86_CR0_PE;
5239                 }
5240
5241                 if (cr0 ^ val)
5242                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5243
5244                 break;
5245         }
5246         case SVM_EXIT_READ_DR0:
5247         case SVM_EXIT_WRITE_DR0:
5248                 icpt_info.exit_code += info->modrm_reg;
5249                 break;
5250         case SVM_EXIT_MSR:
5251                 if (info->intercept == x86_intercept_wrmsr)
5252                         vmcb->control.exit_info_1 = 1;
5253                 else
5254                         vmcb->control.exit_info_1 = 0;
5255                 break;
5256         case SVM_EXIT_PAUSE:
5257                 /*
5258                  * We get this for NOP only, but pause
5259                  * is rep not, check this here
5260                  */
5261                 if (info->rep_prefix != REPE_PREFIX)
5262                         goto out;
5263         case SVM_EXIT_IOIO: {
5264                 u64 exit_info;
5265                 u32 bytes;
5266
5267                 if (info->intercept == x86_intercept_in ||
5268                     info->intercept == x86_intercept_ins) {
5269                         exit_info = ((info->src_val & 0xffff) << 16) |
5270                                 SVM_IOIO_TYPE_MASK;
5271                         bytes = info->dst_bytes;
5272                 } else {
5273                         exit_info = (info->dst_val & 0xffff) << 16;
5274                         bytes = info->src_bytes;
5275                 }
5276
5277                 if (info->intercept == x86_intercept_outs ||
5278                     info->intercept == x86_intercept_ins)
5279                         exit_info |= SVM_IOIO_STR_MASK;
5280
5281                 if (info->rep_prefix)
5282                         exit_info |= SVM_IOIO_REP_MASK;
5283
5284                 bytes = min(bytes, 4u);
5285
5286                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5287
5288                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5289
5290                 vmcb->control.exit_info_1 = exit_info;
5291                 vmcb->control.exit_info_2 = info->next_rip;
5292
5293                 break;
5294         }
5295         default:
5296                 break;
5297         }
5298
5299         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5300         if (static_cpu_has(X86_FEATURE_NRIPS))
5301                 vmcb->control.next_rip  = info->next_rip;
5302         vmcb->control.exit_code = icpt_info.exit_code;
5303         vmexit = nested_svm_exit_handled(svm);
5304
5305         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5306                                            : X86EMUL_CONTINUE;
5307
5308 out:
5309         return ret;
5310 }
5311
5312 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5313 {
5314         local_irq_enable();
5315         /*
5316          * We must have an instruction with interrupts enabled, so
5317          * the timer interrupt isn't delayed by the interrupt shadow.
5318          */
5319         asm("nop");
5320         local_irq_disable();
5321 }
5322
5323 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5324 {
5325 }
5326
5327 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5328 {
5329         if (avic_handle_apic_id_update(vcpu) != 0)
5330                 return;
5331         if (avic_handle_dfr_update(vcpu) != 0)
5332                 return;
5333         avic_handle_ldr_update(vcpu);
5334 }
5335
5336 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5337 {
5338         /* [63:9] are reserved. */
5339         vcpu->arch.mcg_cap &= 0x1ff;
5340 }
5341
5342 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5343         .cpu_has_kvm_support = has_svm,
5344         .disabled_by_bios = is_disabled,
5345         .hardware_setup = svm_hardware_setup,
5346         .hardware_unsetup = svm_hardware_unsetup,
5347         .check_processor_compatibility = svm_check_processor_compat,
5348         .hardware_enable = svm_hardware_enable,
5349         .hardware_disable = svm_hardware_disable,
5350         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5351         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5352
5353         .vcpu_create = svm_create_vcpu,
5354         .vcpu_free = svm_free_vcpu,
5355         .vcpu_reset = svm_vcpu_reset,
5356
5357         .vm_init = avic_vm_init,
5358         .vm_destroy = avic_vm_destroy,
5359
5360         .prepare_guest_switch = svm_prepare_guest_switch,
5361         .vcpu_load = svm_vcpu_load,
5362         .vcpu_put = svm_vcpu_put,
5363         .vcpu_blocking = svm_vcpu_blocking,
5364         .vcpu_unblocking = svm_vcpu_unblocking,
5365
5366         .update_bp_intercept = update_bp_intercept,
5367         .get_msr = svm_get_msr,
5368         .set_msr = svm_set_msr,
5369         .get_segment_base = svm_get_segment_base,
5370         .get_segment = svm_get_segment,
5371         .set_segment = svm_set_segment,
5372         .get_cpl = svm_get_cpl,
5373         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5374         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5375         .decache_cr3 = svm_decache_cr3,
5376         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5377         .set_cr0 = svm_set_cr0,
5378         .set_cr3 = svm_set_cr3,
5379         .set_cr4 = svm_set_cr4,
5380         .set_efer = svm_set_efer,
5381         .get_idt = svm_get_idt,
5382         .set_idt = svm_set_idt,
5383         .get_gdt = svm_get_gdt,
5384         .set_gdt = svm_set_gdt,
5385         .get_dr6 = svm_get_dr6,
5386         .set_dr6 = svm_set_dr6,
5387         .set_dr7 = svm_set_dr7,
5388         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5389         .cache_reg = svm_cache_reg,
5390         .get_rflags = svm_get_rflags,
5391         .set_rflags = svm_set_rflags,
5392
5393         .get_pkru = svm_get_pkru,
5394
5395         .tlb_flush = svm_flush_tlb,
5396
5397         .run = svm_vcpu_run,
5398         .handle_exit = handle_exit,
5399         .skip_emulated_instruction = skip_emulated_instruction,
5400         .set_interrupt_shadow = svm_set_interrupt_shadow,
5401         .get_interrupt_shadow = svm_get_interrupt_shadow,
5402         .patch_hypercall = svm_patch_hypercall,
5403         .set_irq = svm_set_irq,
5404         .set_nmi = svm_inject_nmi,
5405         .queue_exception = svm_queue_exception,
5406         .cancel_injection = svm_cancel_injection,
5407         .interrupt_allowed = svm_interrupt_allowed,
5408         .nmi_allowed = svm_nmi_allowed,
5409         .get_nmi_mask = svm_get_nmi_mask,
5410         .set_nmi_mask = svm_set_nmi_mask,
5411         .enable_nmi_window = enable_nmi_window,
5412         .enable_irq_window = enable_irq_window,
5413         .update_cr8_intercept = update_cr8_intercept,
5414         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5415         .get_enable_apicv = svm_get_enable_apicv,
5416         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5417         .load_eoi_exitmap = svm_load_eoi_exitmap,
5418         .hwapic_irr_update = svm_hwapic_irr_update,
5419         .hwapic_isr_update = svm_hwapic_isr_update,
5420         .apicv_post_state_restore = avic_post_state_restore,
5421
5422         .set_tss_addr = svm_set_tss_addr,
5423         .get_tdp_level = get_npt_level,
5424         .get_mt_mask = svm_get_mt_mask,
5425
5426         .get_exit_info = svm_get_exit_info,
5427
5428         .get_lpage_level = svm_get_lpage_level,
5429
5430         .cpuid_update = svm_cpuid_update,
5431
5432         .rdtscp_supported = svm_rdtscp_supported,
5433         .invpcid_supported = svm_invpcid_supported,
5434         .mpx_supported = svm_mpx_supported,
5435         .xsaves_supported = svm_xsaves_supported,
5436
5437         .set_supported_cpuid = svm_set_supported_cpuid,
5438
5439         .has_wbinvd_exit = svm_has_wbinvd_exit,
5440
5441         .write_tsc_offset = svm_write_tsc_offset,
5442
5443         .set_tdp_cr3 = set_tdp_cr3,
5444
5445         .check_intercept = svm_check_intercept,
5446         .handle_external_intr = svm_handle_external_intr,
5447
5448         .sched_in = svm_sched_in,
5449
5450         .pmu_ops = &amd_pmu_ops,
5451         .deliver_posted_interrupt = svm_deliver_avic_intr,
5452         .update_pi_irte = svm_update_pi_irte,
5453         .setup_mce = svm_setup_mce,
5454 };
5455
5456 static int __init svm_init(void)
5457 {
5458         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5459                         __alignof__(struct vcpu_svm), THIS_MODULE);
5460 }
5461
5462 static void __exit svm_exit(void)
5463 {
5464         kvm_exit();
5465 }
5466
5467 module_init(svm_init)
5468 module_exit(svm_exit)