1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/hashtable.h>
36 #include <linux/frame.h>
37 #include <linux/psp-sev.h>
38 #include <linux/file.h>
39 #include <linux/pagemap.h>
40 #include <linux/swap.h>
41 #include <linux/rwsem.h>
44 #include <asm/perf_event.h>
45 #include <asm/tlbflush.h>
47 #include <asm/debugreg.h>
48 #include <asm/kvm_para.h>
49 #include <asm/irq_remapping.h>
50 #include <asm/spec-ctrl.h>
52 #include <asm/virtext.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
57 MODULE_AUTHOR("Qumranet");
58 MODULE_LICENSE("GPL");
60 static const struct x86_cpu_id svm_cpu_id[] = {
61 X86_FEATURE_MATCH(X86_FEATURE_SVM),
64 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
66 #define IOPM_ALLOC_ORDER 2
67 #define MSRPM_ALLOC_ORDER 1
69 #define SEG_TYPE_LDT 2
70 #define SEG_TYPE_BUSY_TSS16 3
72 #define SVM_FEATURE_LBRV (1 << 1)
73 #define SVM_FEATURE_SVML (1 << 2)
74 #define SVM_FEATURE_TSC_RATE (1 << 4)
75 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
76 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
77 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
78 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80 #define SVM_AVIC_DOORBELL 0xc001011b
82 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
83 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
84 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
86 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
88 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
89 #define TSC_RATIO_MIN 0x0000000000000001ULL
90 #define TSC_RATIO_MAX 0x000000ffffffffffULL
92 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
95 * 0xff is broadcast, so the max index allowed for physical APIC ID
96 * table is 0xfe. APIC IDs above 0xff are reserved.
98 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
100 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
101 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
102 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
104 /* AVIC GATAG is encoded using VM and VCPU IDs */
105 #define AVIC_VCPU_ID_BITS 8
106 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
108 #define AVIC_VM_ID_BITS 24
109 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
110 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
112 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
113 (y & AVIC_VCPU_ID_MASK))
114 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
115 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
117 static bool erratum_383_found __read_mostly;
119 static const u32 host_save_user_msrs[] = {
121 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
124 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
128 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
130 struct kvm_sev_info {
131 bool active; /* SEV enabled guest */
132 unsigned int asid; /* ASID used for this guest */
133 unsigned int handle; /* SEV firmware handle */
134 int fd; /* SEV device fd */
135 unsigned long pages_locked; /* Number of pages locked */
136 struct list_head regions_list; /* List of registered regions */
142 /* Struct members for AVIC */
144 struct page *avic_logical_id_table_page;
145 struct page *avic_physical_id_table_page;
146 struct hlist_node hnode;
148 struct kvm_sev_info sev_info;
153 struct nested_state {
159 /* These are the merged vectors */
162 /* gpa pointers to the real vectors */
166 /* A VMEXIT is required but not yet emulated */
169 /* cache for intercepts of the guest */
172 u32 intercept_exceptions;
175 /* Nested Paging related state */
179 #define MSRPM_OFFSETS 16
180 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
183 * Set osvw_len to higher value when updated Revision Guides
184 * are published and we know what the new status bits are
186 static uint64_t osvw_len = 4, osvw_status;
189 struct kvm_vcpu vcpu;
191 unsigned long vmcb_pa;
192 struct svm_cpu_data *svm_data;
193 uint64_t asid_generation;
194 uint64_t sysenter_esp;
195 uint64_t sysenter_eip;
202 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
212 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
213 * translated into the appropriate L2_CFG bits on the host to
214 * perform speculative control.
222 struct nested_state nested;
225 u64 nmi_singlestep_guest_rflags;
227 unsigned int3_injected;
228 unsigned long int3_rip;
230 /* cached guest cpuid flags for faster access */
231 bool nrips_enabled : 1;
235 struct page *avic_backing_page;
236 u64 *avic_physical_id_cache;
237 bool avic_is_running;
240 * Per-vcpu list of struct amd_svm_iommu_ir:
241 * This is used mainly to store interrupt remapping information used
242 * when update the vcpu affinity. This avoids the need to scan for
243 * IRTE and try to match ga_tag in the IOMMU driver.
245 struct list_head ir_list;
246 spinlock_t ir_list_lock;
248 /* which host CPU was used for running this vcpu */
249 unsigned int last_cpu;
253 * This is a wrapper of struct amd_iommu_ir_data.
255 struct amd_svm_iommu_ir {
256 struct list_head node; /* Used by SVM for per-vcpu ir_list */
257 void *data; /* Storing pointer to struct amd_ir_data */
260 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
261 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
262 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
264 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
265 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
266 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
267 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
269 static DEFINE_PER_CPU(u64, current_tsc_ratio);
270 #define TSC_RATIO_DEFAULT 0x0100000000ULL
272 #define MSR_INVALID 0xffffffffU
274 static const struct svm_direct_access_msrs {
275 u32 index; /* Index of the MSR */
276 bool always; /* True if intercept is always on */
277 } direct_access_msrs[] = {
278 { .index = MSR_STAR, .always = true },
279 { .index = MSR_IA32_SYSENTER_CS, .always = true },
281 { .index = MSR_GS_BASE, .always = true },
282 { .index = MSR_FS_BASE, .always = true },
283 { .index = MSR_KERNEL_GS_BASE, .always = true },
284 { .index = MSR_LSTAR, .always = true },
285 { .index = MSR_CSTAR, .always = true },
286 { .index = MSR_SYSCALL_MASK, .always = true },
288 { .index = MSR_IA32_SPEC_CTRL, .always = false },
289 { .index = MSR_IA32_PRED_CMD, .always = false },
290 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
291 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
292 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
293 { .index = MSR_IA32_LASTINTTOIP, .always = false },
294 { .index = MSR_INVALID, .always = false },
297 /* enable NPT for AMD64 and X86 with PAE */
298 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
299 static bool npt_enabled = true;
301 static bool npt_enabled;
305 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
306 * pause_filter_count: On processors that support Pause filtering(indicated
307 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
308 * count value. On VMRUN this value is loaded into an internal counter.
309 * Each time a pause instruction is executed, this counter is decremented
310 * until it reaches zero at which time a #VMEXIT is generated if pause
311 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
312 * Intercept Filtering for more details.
313 * This also indicate if ple logic enabled.
315 * pause_filter_thresh: In addition, some processor families support advanced
316 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
317 * the amount of time a guest is allowed to execute in a pause loop.
318 * In this mode, a 16-bit pause filter threshold field is added in the
319 * VMCB. The threshold value is a cycle count that is used to reset the
320 * pause counter. As with simple pause filtering, VMRUN loads the pause
321 * count value from VMCB into an internal counter. Then, on each pause
322 * instruction the hardware checks the elapsed number of cycles since
323 * the most recent pause instruction against the pause filter threshold.
324 * If the elapsed cycle count is greater than the pause filter threshold,
325 * then the internal pause count is reloaded from the VMCB and execution
326 * continues. If the elapsed cycle count is less than the pause filter
327 * threshold, then the internal pause count is decremented. If the count
328 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
329 * triggered. If advanced pause filtering is supported and pause filter
330 * threshold field is set to zero, the filter will operate in the simpler,
334 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
335 module_param(pause_filter_thresh, ushort, 0444);
337 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
338 module_param(pause_filter_count, ushort, 0444);
340 /* Default doubles per-vcpu window every exit. */
341 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
342 module_param(pause_filter_count_grow, ushort, 0444);
344 /* Default resets per-vcpu window every exit to pause_filter_count. */
345 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
346 module_param(pause_filter_count_shrink, ushort, 0444);
348 /* Default is to compute the maximum so we can never overflow. */
349 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
350 module_param(pause_filter_count_max, ushort, 0444);
352 /* allow nested paging (virtualized MMU) for all guests */
353 static int npt = true;
354 module_param(npt, int, S_IRUGO);
356 /* allow nested virtualization in KVM/SVM */
357 static int nested = true;
358 module_param(nested, int, S_IRUGO);
360 /* enable / disable AVIC */
362 #ifdef CONFIG_X86_LOCAL_APIC
363 module_param(avic, int, S_IRUGO);
366 /* enable/disable Next RIP Save */
367 static int nrips = true;
368 module_param(nrips, int, 0444);
370 /* enable/disable Virtual VMLOAD VMSAVE */
371 static int vls = true;
372 module_param(vls, int, 0444);
374 /* enable/disable Virtual GIF */
375 static int vgif = true;
376 module_param(vgif, int, 0444);
378 /* enable/disable SEV support */
379 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
380 module_param(sev, int, 0444);
382 static bool __read_mostly dump_invalid_vmcb = 0;
383 module_param(dump_invalid_vmcb, bool, 0644);
385 static u8 rsm_ins_bytes[] = "\x0f\xaa";
387 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
388 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
389 static void svm_complete_interrupts(struct vcpu_svm *svm);
390 static void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
391 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu);
393 static int nested_svm_exit_handled(struct vcpu_svm *svm);
394 static int nested_svm_intercept(struct vcpu_svm *svm);
395 static int nested_svm_vmexit(struct vcpu_svm *svm);
396 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
397 bool has_error_code, u32 error_code);
400 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
401 pause filter count */
402 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
403 VMCB_ASID, /* ASID */
404 VMCB_INTR, /* int_ctl, int_vector */
405 VMCB_NPT, /* npt_en, nCR3, gPAT */
406 VMCB_CR, /* CR0, CR3, CR4, EFER */
407 VMCB_DR, /* DR6, DR7 */
408 VMCB_DT, /* GDT, IDT */
409 VMCB_SEG, /* CS, DS, SS, ES, CPL */
410 VMCB_CR2, /* CR2 only */
411 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
412 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
413 * AVIC PHYSICAL_TABLE pointer,
414 * AVIC LOGICAL_TABLE pointer
419 /* TPR and CR2 are always written before VMRUN */
420 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
422 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
424 static int sev_flush_asids(void);
425 static DECLARE_RWSEM(sev_deactivate_lock);
426 static DEFINE_MUTEX(sev_bitmap_lock);
427 static unsigned int max_sev_asid;
428 static unsigned int min_sev_asid;
429 static unsigned long *sev_asid_bitmap;
430 static unsigned long *sev_reclaim_asid_bitmap;
431 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
434 struct list_head list;
435 unsigned long npages;
442 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
444 return container_of(kvm, struct kvm_svm, kvm);
447 static inline bool svm_sev_enabled(void)
449 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
452 static inline bool sev_guest(struct kvm *kvm)
454 #ifdef CONFIG_KVM_AMD_SEV
455 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
463 static inline int sev_get_asid(struct kvm *kvm)
465 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
470 static inline void mark_all_dirty(struct vmcb *vmcb)
472 vmcb->control.clean = 0;
475 static inline void mark_all_clean(struct vmcb *vmcb)
477 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
478 & ~VMCB_ALWAYS_DIRTY_MASK;
481 static inline void mark_dirty(struct vmcb *vmcb, int bit)
483 vmcb->control.clean &= ~(1 << bit);
486 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
488 return container_of(vcpu, struct vcpu_svm, vcpu);
491 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
493 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
494 mark_dirty(svm->vmcb, VMCB_AVIC);
497 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
499 struct vcpu_svm *svm = to_svm(vcpu);
500 u64 *entry = svm->avic_physical_id_cache;
505 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
508 static void recalc_intercepts(struct vcpu_svm *svm)
510 struct vmcb_control_area *c, *h;
511 struct nested_state *g;
513 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
515 if (!is_guest_mode(&svm->vcpu))
518 c = &svm->vmcb->control;
519 h = &svm->nested.hsave->control;
522 c->intercept_cr = h->intercept_cr | g->intercept_cr;
523 c->intercept_dr = h->intercept_dr | g->intercept_dr;
524 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
525 c->intercept = h->intercept | g->intercept;
528 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
530 if (is_guest_mode(&svm->vcpu))
531 return svm->nested.hsave;
536 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
538 struct vmcb *vmcb = get_host_vmcb(svm);
540 vmcb->control.intercept_cr |= (1U << bit);
542 recalc_intercepts(svm);
545 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
547 struct vmcb *vmcb = get_host_vmcb(svm);
549 vmcb->control.intercept_cr &= ~(1U << bit);
551 recalc_intercepts(svm);
554 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
556 struct vmcb *vmcb = get_host_vmcb(svm);
558 return vmcb->control.intercept_cr & (1U << bit);
561 static inline void set_dr_intercepts(struct vcpu_svm *svm)
563 struct vmcb *vmcb = get_host_vmcb(svm);
565 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
566 | (1 << INTERCEPT_DR1_READ)
567 | (1 << INTERCEPT_DR2_READ)
568 | (1 << INTERCEPT_DR3_READ)
569 | (1 << INTERCEPT_DR4_READ)
570 | (1 << INTERCEPT_DR5_READ)
571 | (1 << INTERCEPT_DR6_READ)
572 | (1 << INTERCEPT_DR7_READ)
573 | (1 << INTERCEPT_DR0_WRITE)
574 | (1 << INTERCEPT_DR1_WRITE)
575 | (1 << INTERCEPT_DR2_WRITE)
576 | (1 << INTERCEPT_DR3_WRITE)
577 | (1 << INTERCEPT_DR4_WRITE)
578 | (1 << INTERCEPT_DR5_WRITE)
579 | (1 << INTERCEPT_DR6_WRITE)
580 | (1 << INTERCEPT_DR7_WRITE);
582 recalc_intercepts(svm);
585 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
587 struct vmcb *vmcb = get_host_vmcb(svm);
589 vmcb->control.intercept_dr = 0;
591 recalc_intercepts(svm);
594 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
596 struct vmcb *vmcb = get_host_vmcb(svm);
598 vmcb->control.intercept_exceptions |= (1U << bit);
600 recalc_intercepts(svm);
603 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
605 struct vmcb *vmcb = get_host_vmcb(svm);
607 vmcb->control.intercept_exceptions &= ~(1U << bit);
609 recalc_intercepts(svm);
612 static inline void set_intercept(struct vcpu_svm *svm, int bit)
614 struct vmcb *vmcb = get_host_vmcb(svm);
616 vmcb->control.intercept |= (1ULL << bit);
618 recalc_intercepts(svm);
621 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
623 struct vmcb *vmcb = get_host_vmcb(svm);
625 vmcb->control.intercept &= ~(1ULL << bit);
627 recalc_intercepts(svm);
630 static inline bool vgif_enabled(struct vcpu_svm *svm)
632 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
635 static inline void enable_gif(struct vcpu_svm *svm)
637 if (vgif_enabled(svm))
638 svm->vmcb->control.int_ctl |= V_GIF_MASK;
640 svm->vcpu.arch.hflags |= HF_GIF_MASK;
643 static inline void disable_gif(struct vcpu_svm *svm)
645 if (vgif_enabled(svm))
646 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
648 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
651 static inline bool gif_set(struct vcpu_svm *svm)
653 if (vgif_enabled(svm))
654 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
656 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
659 static unsigned long iopm_base;
661 struct kvm_ldttss_desc {
664 unsigned base1:8, type:5, dpl:2, p:1;
665 unsigned limit1:4, zero0:3, g:1, base2:8;
668 } __attribute__((packed));
670 struct svm_cpu_data {
677 struct kvm_ldttss_desc *tss_desc;
679 struct page *save_area;
680 struct vmcb *current_vmcb;
682 /* index = sev_asid, value = vmcb pointer */
683 struct vmcb **sev_vmcbs;
686 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
688 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
690 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
691 #define MSRS_RANGE_SIZE 2048
692 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
694 static u32 svm_msrpm_offset(u32 msr)
699 for (i = 0; i < NUM_MSR_MAPS; i++) {
700 if (msr < msrpm_ranges[i] ||
701 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
704 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
705 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
707 /* Now we have the u8 offset - but need the u32 offset */
711 /* MSR not in any range */
715 #define MAX_INST_SIZE 15
717 static inline void clgi(void)
719 asm volatile (__ex("clgi"));
722 static inline void stgi(void)
724 asm volatile (__ex("stgi"));
727 static inline void invlpga(unsigned long addr, u32 asid)
729 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
732 static int get_npt_level(struct kvm_vcpu *vcpu)
735 return PT64_ROOT_4LEVEL;
737 return PT32E_ROOT_LEVEL;
741 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
743 vcpu->arch.efer = efer;
746 /* Shadow paging assumes NX to be available. */
749 if (!(efer & EFER_LMA))
753 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
754 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
757 static int is_external_interrupt(u32 info)
759 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
760 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
763 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
765 struct vcpu_svm *svm = to_svm(vcpu);
768 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
769 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
773 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
775 struct vcpu_svm *svm = to_svm(vcpu);
778 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
780 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
784 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
786 struct vcpu_svm *svm = to_svm(vcpu);
788 if (nrips && svm->vmcb->control.next_rip != 0) {
789 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
790 svm->next_rip = svm->vmcb->control.next_rip;
793 if (!svm->next_rip) {
794 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
797 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
798 pr_err("%s: ip 0x%lx next 0x%llx\n",
799 __func__, kvm_rip_read(vcpu), svm->next_rip);
800 kvm_rip_write(vcpu, svm->next_rip);
802 svm_set_interrupt_shadow(vcpu, 0);
807 static void svm_queue_exception(struct kvm_vcpu *vcpu)
809 struct vcpu_svm *svm = to_svm(vcpu);
810 unsigned nr = vcpu->arch.exception.nr;
811 bool has_error_code = vcpu->arch.exception.has_error_code;
812 bool reinject = vcpu->arch.exception.injected;
813 u32 error_code = vcpu->arch.exception.error_code;
816 * If we are within a nested VM we'd better #VMEXIT and let the guest
817 * handle the exception
820 nested_svm_check_exception(svm, nr, has_error_code, error_code))
823 kvm_deliver_exception_payload(&svm->vcpu);
825 if (nr == BP_VECTOR && !nrips) {
826 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
829 * For guest debugging where we have to reinject #BP if some
830 * INT3 is guest-owned:
831 * Emulate nRIP by moving RIP forward. Will fail if injection
832 * raises a fault that is not intercepted. Still better than
833 * failing in all cases.
835 (void)skip_emulated_instruction(&svm->vcpu);
836 rip = kvm_rip_read(&svm->vcpu);
837 svm->int3_rip = rip + svm->vmcb->save.cs.base;
838 svm->int3_injected = rip - old_rip;
841 svm->vmcb->control.event_inj = nr
843 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
844 | SVM_EVTINJ_TYPE_EXEPT;
845 svm->vmcb->control.event_inj_err = error_code;
848 static void svm_init_erratum_383(void)
854 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
857 /* Use _safe variants to not break nested virtualization */
858 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
864 low = lower_32_bits(val);
865 high = upper_32_bits(val);
867 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
869 erratum_383_found = true;
872 static void svm_init_osvw(struct kvm_vcpu *vcpu)
875 * Guests should see errata 400 and 415 as fixed (assuming that
876 * HLT and IO instructions are intercepted).
878 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
879 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
882 * By increasing VCPU's osvw.length to 3 we are telling the guest that
883 * all osvw.status bits inside that length, including bit 0 (which is
884 * reserved for erratum 298), are valid. However, if host processor's
885 * osvw_len is 0 then osvw_status[0] carries no information. We need to
886 * be conservative here and therefore we tell the guest that erratum 298
887 * is present (because we really don't know).
889 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
890 vcpu->arch.osvw.status |= 1;
893 static int has_svm(void)
897 if (!cpu_has_svm(&msg)) {
898 printk(KERN_INFO "has_svm: %s\n", msg);
905 static void svm_hardware_disable(void)
907 /* Make sure we clean up behind us */
908 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
909 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
913 amd_pmu_disable_virt();
916 static int svm_hardware_enable(void)
919 struct svm_cpu_data *sd;
921 struct desc_struct *gdt;
922 int me = raw_smp_processor_id();
924 rdmsrl(MSR_EFER, efer);
925 if (efer & EFER_SVME)
929 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
932 sd = per_cpu(svm_data, me);
934 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
938 sd->asid_generation = 1;
939 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
940 sd->next_asid = sd->max_asid + 1;
941 sd->min_asid = max_sev_asid + 1;
943 gdt = get_current_gdt_rw();
944 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
946 wrmsrl(MSR_EFER, efer | EFER_SVME);
948 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
950 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
951 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
952 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
959 * Note that it is possible to have a system with mixed processor
960 * revisions and therefore different OSVW bits. If bits are not the same
961 * on different processors then choose the worst case (i.e. if erratum
962 * is present on one processor and not on another then assume that the
963 * erratum is present everywhere).
965 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
966 uint64_t len, status = 0;
969 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
971 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
975 osvw_status = osvw_len = 0;
979 osvw_status |= status;
980 osvw_status &= (1ULL << osvw_len) - 1;
983 osvw_status = osvw_len = 0;
985 svm_init_erratum_383();
987 amd_pmu_enable_virt();
992 static void svm_cpu_uninit(int cpu)
994 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
999 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
1000 kfree(sd->sev_vmcbs);
1001 __free_page(sd->save_area);
1005 static int svm_cpu_init(int cpu)
1007 struct svm_cpu_data *sd;
1010 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1015 sd->save_area = alloc_page(GFP_KERNEL);
1019 if (svm_sev_enabled()) {
1021 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1028 per_cpu(svm_data, cpu) = sd;
1038 static bool valid_msr_intercept(u32 index)
1042 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1043 if (direct_access_msrs[i].index == index)
1049 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1056 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1057 to_svm(vcpu)->msrpm;
1059 offset = svm_msrpm_offset(msr);
1060 bit_write = 2 * (msr & 0x0f) + 1;
1061 tmp = msrpm[offset];
1063 BUG_ON(offset == MSR_INVALID);
1065 return !!test_bit(bit_write, &tmp);
1068 static void set_msr_interception(u32 *msrpm, unsigned msr,
1069 int read, int write)
1071 u8 bit_read, bit_write;
1076 * If this warning triggers extend the direct_access_msrs list at the
1077 * beginning of the file
1079 WARN_ON(!valid_msr_intercept(msr));
1081 offset = svm_msrpm_offset(msr);
1082 bit_read = 2 * (msr & 0x0f);
1083 bit_write = 2 * (msr & 0x0f) + 1;
1084 tmp = msrpm[offset];
1086 BUG_ON(offset == MSR_INVALID);
1088 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1089 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1091 msrpm[offset] = tmp;
1094 static void svm_vcpu_init_msrpm(u32 *msrpm)
1098 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1100 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1101 if (!direct_access_msrs[i].always)
1104 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1108 static void add_msr_offset(u32 offset)
1112 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1114 /* Offset already in list? */
1115 if (msrpm_offsets[i] == offset)
1118 /* Slot used by another offset? */
1119 if (msrpm_offsets[i] != MSR_INVALID)
1122 /* Add offset to list */
1123 msrpm_offsets[i] = offset;
1129 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1130 * increase MSRPM_OFFSETS in this case.
1135 static void init_msrpm_offsets(void)
1139 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1141 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1144 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1145 BUG_ON(offset == MSR_INVALID);
1147 add_msr_offset(offset);
1151 static void svm_enable_lbrv(struct vcpu_svm *svm)
1153 u32 *msrpm = svm->msrpm;
1155 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1156 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1157 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1158 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1159 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1162 static void svm_disable_lbrv(struct vcpu_svm *svm)
1164 u32 *msrpm = svm->msrpm;
1166 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1167 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1168 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1169 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1170 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1173 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1175 svm->nmi_singlestep = false;
1177 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1178 /* Clear our flags if they were not set by the guest */
1179 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1180 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1181 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1182 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1187 * This hash table is used to map VM_ID to a struct kvm_svm,
1188 * when handling AMD IOMMU GALOG notification to schedule in
1189 * a particular vCPU.
1191 #define SVM_VM_DATA_HASH_BITS 8
1192 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1193 static u32 next_vm_id = 0;
1194 static bool next_vm_id_wrapped = 0;
1195 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1198 * This function is called from IOMMU driver to notify
1199 * SVM to schedule in a particular vCPU of a particular VM.
1201 static int avic_ga_log_notifier(u32 ga_tag)
1203 unsigned long flags;
1204 struct kvm_svm *kvm_svm;
1205 struct kvm_vcpu *vcpu = NULL;
1206 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1207 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1209 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1211 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1212 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1213 if (kvm_svm->avic_vm_id != vm_id)
1215 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1218 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1221 * At this point, the IOMMU should have already set the pending
1222 * bit in the vAPIC backing page. So, we just need to schedule
1226 kvm_vcpu_wake_up(vcpu);
1231 static __init int sev_hardware_setup(void)
1233 struct sev_user_data_status *status;
1236 /* Maximum number of encrypted guests supported simultaneously */
1237 max_sev_asid = cpuid_ecx(0x8000001F);
1242 /* Minimum ASID value that should be used for SEV guest */
1243 min_sev_asid = cpuid_edx(0x8000001F);
1245 /* Initialize SEV ASID bitmaps */
1246 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1247 if (!sev_asid_bitmap)
1250 sev_reclaim_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1251 if (!sev_reclaim_asid_bitmap)
1254 status = kmalloc(sizeof(*status), GFP_KERNEL);
1259 * Check SEV platform status.
1261 * PLATFORM_STATUS can be called in any state, if we failed to query
1262 * the PLATFORM status then either PSP firmware does not support SEV
1263 * feature or SEV firmware is dead.
1265 rc = sev_platform_status(status, NULL);
1269 pr_info("SEV supported\n");
1276 static void grow_ple_window(struct kvm_vcpu *vcpu)
1278 struct vcpu_svm *svm = to_svm(vcpu);
1279 struct vmcb_control_area *control = &svm->vmcb->control;
1280 int old = control->pause_filter_count;
1282 control->pause_filter_count = __grow_ple_window(old,
1284 pause_filter_count_grow,
1285 pause_filter_count_max);
1287 if (control->pause_filter_count != old) {
1288 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1289 trace_kvm_ple_window_update(vcpu->vcpu_id,
1290 control->pause_filter_count, old);
1294 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1296 struct vcpu_svm *svm = to_svm(vcpu);
1297 struct vmcb_control_area *control = &svm->vmcb->control;
1298 int old = control->pause_filter_count;
1300 control->pause_filter_count =
1301 __shrink_ple_window(old,
1303 pause_filter_count_shrink,
1304 pause_filter_count);
1305 if (control->pause_filter_count != old) {
1306 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1307 trace_kvm_ple_window_update(vcpu->vcpu_id,
1308 control->pause_filter_count, old);
1313 * The default MMIO mask is a single bit (excluding the present bit),
1314 * which could conflict with the memory encryption bit. Check for
1315 * memory encryption support and override the default MMIO mask if
1316 * memory encryption is enabled.
1318 static __init void svm_adjust_mmio_mask(void)
1320 unsigned int enc_bit, mask_bit;
1323 /* If there is no memory encryption support, use existing mask */
1324 if (cpuid_eax(0x80000000) < 0x8000001f)
1327 /* If memory encryption is not enabled, use existing mask */
1328 rdmsrl(MSR_K8_SYSCFG, msr);
1329 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
1332 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
1333 mask_bit = boot_cpu_data.x86_phys_bits;
1335 /* Increment the mask bit if it is the same as the encryption bit */
1336 if (enc_bit == mask_bit)
1340 * If the mask bit location is below 52, then some bits above the
1341 * physical addressing limit will always be reserved, so use the
1342 * rsvd_bits() function to generate the mask. This mask, along with
1343 * the present bit, will be used to generate a page fault with
1346 * If the mask bit location is 52 (or above), then clear the mask.
1348 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
1350 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
1353 static __init int svm_hardware_setup(void)
1356 struct page *iopm_pages;
1360 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1365 iopm_va = page_address(iopm_pages);
1366 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1367 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1369 init_msrpm_offsets();
1371 if (boot_cpu_has(X86_FEATURE_NX))
1372 kvm_enable_efer_bits(EFER_NX);
1374 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1375 kvm_enable_efer_bits(EFER_FFXSR);
1377 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1378 kvm_has_tsc_control = true;
1379 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1380 kvm_tsc_scaling_ratio_frac_bits = 32;
1383 /* Check for pause filtering support */
1384 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1385 pause_filter_count = 0;
1386 pause_filter_thresh = 0;
1387 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1388 pause_filter_thresh = 0;
1392 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1393 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1397 if (boot_cpu_has(X86_FEATURE_SEV) &&
1398 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1399 r = sev_hardware_setup();
1407 svm_adjust_mmio_mask();
1409 for_each_possible_cpu(cpu) {
1410 r = svm_cpu_init(cpu);
1415 if (!boot_cpu_has(X86_FEATURE_NPT))
1416 npt_enabled = false;
1418 if (npt_enabled && !npt) {
1419 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1420 npt_enabled = false;
1424 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1430 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1436 !boot_cpu_has(X86_FEATURE_AVIC) ||
1437 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1440 pr_info("AVIC enabled\n");
1442 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1448 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1449 !IS_ENABLED(CONFIG_X86_64)) {
1452 pr_info("Virtual VMLOAD VMSAVE supported\n");
1457 if (!boot_cpu_has(X86_FEATURE_VGIF))
1460 pr_info("Virtual GIF supported\n");
1466 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1471 static __exit void svm_hardware_unsetup(void)
1475 if (svm_sev_enabled()) {
1476 bitmap_free(sev_asid_bitmap);
1477 bitmap_free(sev_reclaim_asid_bitmap);
1482 for_each_possible_cpu(cpu)
1483 svm_cpu_uninit(cpu);
1485 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1489 static void init_seg(struct vmcb_seg *seg)
1492 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1493 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1494 seg->limit = 0xffff;
1498 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1501 seg->attrib = SVM_SELECTOR_P_MASK | type;
1502 seg->limit = 0xffff;
1506 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1508 struct vcpu_svm *svm = to_svm(vcpu);
1510 if (is_guest_mode(vcpu))
1511 return svm->nested.hsave->control.tsc_offset;
1513 return vcpu->arch.tsc_offset;
1516 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1518 struct vcpu_svm *svm = to_svm(vcpu);
1519 u64 g_tsc_offset = 0;
1521 if (is_guest_mode(vcpu)) {
1522 /* Write L1's TSC offset. */
1523 g_tsc_offset = svm->vmcb->control.tsc_offset -
1524 svm->nested.hsave->control.tsc_offset;
1525 svm->nested.hsave->control.tsc_offset = offset;
1528 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1529 svm->vmcb->control.tsc_offset - g_tsc_offset,
1532 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1534 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1535 return svm->vmcb->control.tsc_offset;
1538 static void avic_init_vmcb(struct vcpu_svm *svm)
1540 struct vmcb *vmcb = svm->vmcb;
1541 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1542 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1543 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1544 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1546 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1547 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1548 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1549 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1550 if (kvm_apicv_activated(svm->vcpu.kvm))
1551 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1553 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
1556 static void init_vmcb(struct vcpu_svm *svm)
1558 struct vmcb_control_area *control = &svm->vmcb->control;
1559 struct vmcb_save_area *save = &svm->vmcb->save;
1561 svm->vcpu.arch.hflags = 0;
1563 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1564 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1565 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1566 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1567 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1568 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1569 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1570 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1572 set_dr_intercepts(svm);
1574 set_exception_intercept(svm, PF_VECTOR);
1575 set_exception_intercept(svm, UD_VECTOR);
1576 set_exception_intercept(svm, MC_VECTOR);
1577 set_exception_intercept(svm, AC_VECTOR);
1578 set_exception_intercept(svm, DB_VECTOR);
1580 * Guest access to VMware backdoor ports could legitimately
1581 * trigger #GP because of TSS I/O permission bitmap.
1582 * We intercept those #GP and allow access to them anyway
1585 if (enable_vmware_backdoor)
1586 set_exception_intercept(svm, GP_VECTOR);
1588 set_intercept(svm, INTERCEPT_INTR);
1589 set_intercept(svm, INTERCEPT_NMI);
1590 set_intercept(svm, INTERCEPT_SMI);
1591 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1592 set_intercept(svm, INTERCEPT_RDPMC);
1593 set_intercept(svm, INTERCEPT_CPUID);
1594 set_intercept(svm, INTERCEPT_INVD);
1595 set_intercept(svm, INTERCEPT_INVLPG);
1596 set_intercept(svm, INTERCEPT_INVLPGA);
1597 set_intercept(svm, INTERCEPT_IOIO_PROT);
1598 set_intercept(svm, INTERCEPT_MSR_PROT);
1599 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1600 set_intercept(svm, INTERCEPT_SHUTDOWN);
1601 set_intercept(svm, INTERCEPT_VMRUN);
1602 set_intercept(svm, INTERCEPT_VMMCALL);
1603 set_intercept(svm, INTERCEPT_VMLOAD);
1604 set_intercept(svm, INTERCEPT_VMSAVE);
1605 set_intercept(svm, INTERCEPT_STGI);
1606 set_intercept(svm, INTERCEPT_CLGI);
1607 set_intercept(svm, INTERCEPT_SKINIT);
1608 set_intercept(svm, INTERCEPT_WBINVD);
1609 set_intercept(svm, INTERCEPT_XSETBV);
1610 set_intercept(svm, INTERCEPT_RDPRU);
1611 set_intercept(svm, INTERCEPT_RSM);
1613 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1614 set_intercept(svm, INTERCEPT_MONITOR);
1615 set_intercept(svm, INTERCEPT_MWAIT);
1618 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1619 set_intercept(svm, INTERCEPT_HLT);
1621 control->iopm_base_pa = __sme_set(iopm_base);
1622 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1623 control->int_ctl = V_INTR_MASKING_MASK;
1625 init_seg(&save->es);
1626 init_seg(&save->ss);
1627 init_seg(&save->ds);
1628 init_seg(&save->fs);
1629 init_seg(&save->gs);
1631 save->cs.selector = 0xf000;
1632 save->cs.base = 0xffff0000;
1633 /* Executable/Readable Code Segment */
1634 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1635 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1636 save->cs.limit = 0xffff;
1638 save->gdtr.limit = 0xffff;
1639 save->idtr.limit = 0xffff;
1641 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1642 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1644 svm_set_efer(&svm->vcpu, 0);
1645 save->dr6 = 0xffff0ff0;
1646 kvm_set_rflags(&svm->vcpu, 2);
1647 save->rip = 0x0000fff0;
1648 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1651 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1652 * It also updates the guest-visible cr0 value.
1654 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1655 kvm_mmu_reset_context(&svm->vcpu);
1657 save->cr4 = X86_CR4_PAE;
1661 /* Setup VMCB for Nested Paging */
1662 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1663 clr_intercept(svm, INTERCEPT_INVLPG);
1664 clr_exception_intercept(svm, PF_VECTOR);
1665 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1666 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1667 save->g_pat = svm->vcpu.arch.pat;
1671 svm->asid_generation = 0;
1673 svm->nested.vmcb = 0;
1674 svm->vcpu.arch.hflags = 0;
1676 if (pause_filter_count) {
1677 control->pause_filter_count = pause_filter_count;
1678 if (pause_filter_thresh)
1679 control->pause_filter_thresh = pause_filter_thresh;
1680 set_intercept(svm, INTERCEPT_PAUSE);
1682 clr_intercept(svm, INTERCEPT_PAUSE);
1685 if (kvm_vcpu_apicv_active(&svm->vcpu))
1686 avic_init_vmcb(svm);
1689 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1690 * in VMCB and clear intercepts to avoid #VMEXIT.
1693 clr_intercept(svm, INTERCEPT_VMLOAD);
1694 clr_intercept(svm, INTERCEPT_VMSAVE);
1695 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1699 clr_intercept(svm, INTERCEPT_STGI);
1700 clr_intercept(svm, INTERCEPT_CLGI);
1701 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1704 if (sev_guest(svm->vcpu.kvm)) {
1705 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1706 clr_exception_intercept(svm, UD_VECTOR);
1709 mark_all_dirty(svm->vmcb);
1715 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1718 u64 *avic_physical_id_table;
1719 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1721 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1724 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1726 return &avic_physical_id_table[index];
1731 * AVIC hardware walks the nested page table to check permissions,
1732 * but does not use the SPA address specified in the leaf page
1733 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1734 * field of the VMCB. Therefore, we set up the
1735 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1737 static int avic_update_access_page(struct kvm *kvm, bool activate)
1741 mutex_lock(&kvm->slots_lock);
1743 * During kvm_destroy_vm(), kvm_pit_set_reinject() could trigger
1744 * APICv mode change, which update APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
1745 * memory region. So, we need to ensure that kvm->mm == current->mm.
1747 if ((kvm->arch.apic_access_page_done == activate) ||
1748 (kvm->mm != current->mm))
1751 ret = __x86_set_memory_region(kvm,
1752 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1753 APIC_DEFAULT_PHYS_BASE,
1754 activate ? PAGE_SIZE : 0);
1758 kvm->arch.apic_access_page_done = activate;
1760 mutex_unlock(&kvm->slots_lock);
1764 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1766 u64 *entry, new_entry;
1767 int id = vcpu->vcpu_id;
1768 struct vcpu_svm *svm = to_svm(vcpu);
1770 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1773 if (!svm->vcpu.arch.apic->regs)
1776 if (kvm_apicv_activated(vcpu->kvm)) {
1779 ret = avic_update_access_page(vcpu->kvm, true);
1784 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1786 /* Setting AVIC backing page address in the phy APIC ID table */
1787 entry = avic_get_physical_id_entry(vcpu, id);
1791 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1792 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1793 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1794 WRITE_ONCE(*entry, new_entry);
1796 svm->avic_physical_id_cache = entry;
1801 static void sev_asid_free(int asid)
1803 struct svm_cpu_data *sd;
1806 mutex_lock(&sev_bitmap_lock);
1809 __set_bit(pos, sev_reclaim_asid_bitmap);
1811 for_each_possible_cpu(cpu) {
1812 sd = per_cpu(svm_data, cpu);
1813 sd->sev_vmcbs[pos] = NULL;
1816 mutex_unlock(&sev_bitmap_lock);
1819 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1821 struct sev_data_decommission *decommission;
1822 struct sev_data_deactivate *data;
1827 data = kzalloc(sizeof(*data), GFP_KERNEL);
1831 /* deactivate handle */
1832 data->handle = handle;
1834 /* Guard DEACTIVATE against WBINVD/DF_FLUSH used in ASID recycling */
1835 down_read(&sev_deactivate_lock);
1836 sev_guest_deactivate(data, NULL);
1837 up_read(&sev_deactivate_lock);
1841 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1845 /* decommission handle */
1846 decommission->handle = handle;
1847 sev_guest_decommission(decommission, NULL);
1849 kfree(decommission);
1852 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1853 unsigned long ulen, unsigned long *n,
1856 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1857 unsigned long npages, npinned, size;
1858 unsigned long locked, lock_limit;
1859 struct page **pages;
1860 unsigned long first, last;
1862 if (ulen == 0 || uaddr + ulen < uaddr)
1865 /* Calculate number of pages. */
1866 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1867 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1868 npages = (last - first + 1);
1870 locked = sev->pages_locked + npages;
1871 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1872 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1873 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1877 /* Avoid using vmalloc for smaller buffers. */
1878 size = npages * sizeof(struct page *);
1879 if (size > PAGE_SIZE)
1880 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1883 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1888 /* Pin the user virtual address. */
1889 npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1890 if (npinned != npages) {
1891 pr_err("SEV: Failure locking %lu pages.\n", npages);
1896 sev->pages_locked = locked;
1902 release_pages(pages, npinned);
1908 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1909 unsigned long npages)
1911 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1913 release_pages(pages, npages);
1915 sev->pages_locked -= npages;
1918 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1920 uint8_t *page_virtual;
1923 if (npages == 0 || pages == NULL)
1926 for (i = 0; i < npages; i++) {
1927 page_virtual = kmap_atomic(pages[i]);
1928 clflush_cache_range(page_virtual, PAGE_SIZE);
1929 kunmap_atomic(page_virtual);
1933 static void __unregister_enc_region_locked(struct kvm *kvm,
1934 struct enc_region *region)
1937 * The guest may change the memory encryption attribute from C=0 -> C=1
1938 * or vice versa for this memory range. Lets make sure caches are
1939 * flushed to ensure that guest data gets written into memory with
1942 sev_clflush_pages(region->pages, region->npages);
1944 sev_unpin_memory(kvm, region->pages, region->npages);
1945 list_del(®ion->list);
1949 static struct kvm *svm_vm_alloc(void)
1951 struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1952 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1954 return &kvm_svm->kvm;
1957 static void svm_vm_free(struct kvm *kvm)
1959 vfree(to_kvm_svm(kvm));
1962 static void sev_vm_destroy(struct kvm *kvm)
1964 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1965 struct list_head *head = &sev->regions_list;
1966 struct list_head *pos, *q;
1968 if (!sev_guest(kvm))
1971 mutex_lock(&kvm->lock);
1974 * if userspace was terminated before unregistering the memory regions
1975 * then lets unpin all the registered memory.
1977 if (!list_empty(head)) {
1978 list_for_each_safe(pos, q, head) {
1979 __unregister_enc_region_locked(kvm,
1980 list_entry(pos, struct enc_region, list));
1984 mutex_unlock(&kvm->lock);
1986 sev_unbind_asid(kvm, sev->handle);
1987 sev_asid_free(sev->asid);
1990 static void avic_vm_destroy(struct kvm *kvm)
1992 unsigned long flags;
1993 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1998 if (kvm_svm->avic_logical_id_table_page)
1999 __free_page(kvm_svm->avic_logical_id_table_page);
2000 if (kvm_svm->avic_physical_id_table_page)
2001 __free_page(kvm_svm->avic_physical_id_table_page);
2003 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
2004 hash_del(&kvm_svm->hnode);
2005 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
2008 static void svm_vm_destroy(struct kvm *kvm)
2010 avic_vm_destroy(kvm);
2011 sev_vm_destroy(kvm);
2014 static int avic_vm_init(struct kvm *kvm)
2016 unsigned long flags;
2018 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
2020 struct page *p_page;
2021 struct page *l_page;
2027 /* Allocating physical APIC ID table (4KB) */
2028 p_page = alloc_page(GFP_KERNEL_ACCOUNT);
2032 kvm_svm->avic_physical_id_table_page = p_page;
2033 clear_page(page_address(p_page));
2035 /* Allocating logical APIC ID table (4KB) */
2036 l_page = alloc_page(GFP_KERNEL_ACCOUNT);
2040 kvm_svm->avic_logical_id_table_page = l_page;
2041 clear_page(page_address(l_page));
2043 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
2045 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
2046 if (vm_id == 0) { /* id is 1-based, zero is not okay */
2047 next_vm_id_wrapped = 1;
2050 /* Is it still in use? Only possible if wrapped at least once */
2051 if (next_vm_id_wrapped) {
2052 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
2053 if (k2->avic_vm_id == vm_id)
2057 kvm_svm->avic_vm_id = vm_id;
2058 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
2059 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
2064 avic_vm_destroy(kvm);
2068 static int svm_vm_init(struct kvm *kvm)
2071 int ret = avic_vm_init(kvm);
2076 kvm_apicv_init(kvm, avic && irqchip_split(kvm));
2081 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
2084 unsigned long flags;
2085 struct amd_svm_iommu_ir *ir;
2086 struct vcpu_svm *svm = to_svm(vcpu);
2088 if (!kvm_arch_has_assigned_device(vcpu->kvm))
2092 * Here, we go through the per-vcpu ir_list to update all existing
2093 * interrupt remapping table entry targeting this vcpu.
2095 spin_lock_irqsave(&svm->ir_list_lock, flags);
2097 if (list_empty(&svm->ir_list))
2100 list_for_each_entry(ir, &svm->ir_list, node) {
2101 ret = amd_iommu_update_ga(cpu, r, ir->data);
2106 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2110 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2113 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2114 int h_physical_id = kvm_cpu_get_apicid(cpu);
2115 struct vcpu_svm *svm = to_svm(vcpu);
2117 if (!kvm_vcpu_apicv_active(vcpu))
2121 * Since the host physical APIC id is 8 bits,
2122 * we can support host APIC ID upto 255.
2124 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
2127 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2128 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2130 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2131 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2133 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2134 if (svm->avic_is_running)
2135 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2137 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2138 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2139 svm->avic_is_running);
2142 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2145 struct vcpu_svm *svm = to_svm(vcpu);
2147 if (!kvm_vcpu_apicv_active(vcpu))
2150 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2151 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2152 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2154 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2155 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2159 * This function is called during VCPU halt/unhalt.
2161 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2163 struct vcpu_svm *svm = to_svm(vcpu);
2165 svm->avic_is_running = is_run;
2167 avic_vcpu_load(vcpu, vcpu->cpu);
2169 avic_vcpu_put(vcpu);
2172 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2174 struct vcpu_svm *svm = to_svm(vcpu);
2178 vcpu->arch.microcode_version = 0x01000065;
2180 svm->virt_spec_ctrl = 0;
2183 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2184 MSR_IA32_APICBASE_ENABLE;
2185 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2186 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2190 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2191 kvm_rdx_write(vcpu, eax);
2193 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2194 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2197 static int avic_init_vcpu(struct vcpu_svm *svm)
2201 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2204 ret = avic_init_backing_page(&svm->vcpu);
2208 INIT_LIST_HEAD(&svm->ir_list);
2209 spin_lock_init(&svm->ir_list_lock);
2210 svm->dfr_reg = APIC_DFR_FLAT;
2215 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
2217 struct vcpu_svm *svm;
2219 struct page *msrpm_pages;
2220 struct page *hsave_page;
2221 struct page *nested_msrpm_pages;
2224 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
2228 page = alloc_page(GFP_KERNEL_ACCOUNT);
2232 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2236 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2237 if (!nested_msrpm_pages)
2240 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2244 err = avic_init_vcpu(svm);
2248 /* We initialize this flag to true to make sure that the is_running
2249 * bit would be set the first time the vcpu is loaded.
2251 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
2252 svm->avic_is_running = true;
2254 svm->nested.hsave = page_address(hsave_page);
2256 svm->msrpm = page_address(msrpm_pages);
2257 svm_vcpu_init_msrpm(svm->msrpm);
2259 svm->nested.msrpm = page_address(nested_msrpm_pages);
2260 svm_vcpu_init_msrpm(svm->nested.msrpm);
2262 svm->vmcb = page_address(page);
2263 clear_page(svm->vmcb);
2264 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2265 svm->asid_generation = 0;
2268 svm_init_osvw(vcpu);
2273 __free_page(hsave_page);
2275 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2277 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2284 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2288 for_each_online_cpu(i)
2289 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2292 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2294 struct vcpu_svm *svm = to_svm(vcpu);
2297 * The vmcb page can be recycled, causing a false negative in
2298 * svm_vcpu_load(). So, ensure that no logical CPU has this
2299 * vmcb page recorded as its current vmcb.
2301 svm_clear_current_vmcb(svm->vmcb);
2303 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2304 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2305 __free_page(virt_to_page(svm->nested.hsave));
2306 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2309 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2311 struct vcpu_svm *svm = to_svm(vcpu);
2312 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2315 if (unlikely(cpu != vcpu->cpu)) {
2316 svm->asid_generation = 0;
2317 mark_all_dirty(svm->vmcb);
2320 #ifdef CONFIG_X86_64
2321 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2323 savesegment(fs, svm->host.fs);
2324 savesegment(gs, svm->host.gs);
2325 svm->host.ldt = kvm_read_ldt();
2327 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2328 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2330 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2331 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2332 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2333 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2334 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2337 /* This assumes that the kernel never uses MSR_TSC_AUX */
2338 if (static_cpu_has(X86_FEATURE_RDTSCP))
2339 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2341 if (sd->current_vmcb != svm->vmcb) {
2342 sd->current_vmcb = svm->vmcb;
2343 indirect_branch_prediction_barrier();
2345 avic_vcpu_load(vcpu, cpu);
2348 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2350 struct vcpu_svm *svm = to_svm(vcpu);
2353 avic_vcpu_put(vcpu);
2355 ++vcpu->stat.host_state_reload;
2356 kvm_load_ldt(svm->host.ldt);
2357 #ifdef CONFIG_X86_64
2358 loadsegment(fs, svm->host.fs);
2359 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2360 load_gs_index(svm->host.gs);
2362 #ifdef CONFIG_X86_32_LAZY_GS
2363 loadsegment(gs, svm->host.gs);
2366 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2367 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2370 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2372 avic_set_running(vcpu, false);
2375 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2377 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
2378 kvm_vcpu_update_apicv(vcpu);
2379 avic_set_running(vcpu, true);
2382 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2384 struct vcpu_svm *svm = to_svm(vcpu);
2385 unsigned long rflags = svm->vmcb->save.rflags;
2387 if (svm->nmi_singlestep) {
2388 /* Hide our flags if they were not set by the guest */
2389 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2390 rflags &= ~X86_EFLAGS_TF;
2391 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2392 rflags &= ~X86_EFLAGS_RF;
2397 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2399 if (to_svm(vcpu)->nmi_singlestep)
2400 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2403 * Any change of EFLAGS.VM is accompanied by a reload of SS
2404 * (caused by either a task switch or an inter-privilege IRET),
2405 * so we do not need to update the CPL here.
2407 to_svm(vcpu)->vmcb->save.rflags = rflags;
2410 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2413 case VCPU_EXREG_PDPTR:
2414 BUG_ON(!npt_enabled);
2415 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2422 static void svm_set_vintr(struct vcpu_svm *svm)
2424 set_intercept(svm, INTERCEPT_VINTR);
2427 static void svm_clear_vintr(struct vcpu_svm *svm)
2429 clr_intercept(svm, INTERCEPT_VINTR);
2432 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2434 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2437 case VCPU_SREG_CS: return &save->cs;
2438 case VCPU_SREG_DS: return &save->ds;
2439 case VCPU_SREG_ES: return &save->es;
2440 case VCPU_SREG_FS: return &save->fs;
2441 case VCPU_SREG_GS: return &save->gs;
2442 case VCPU_SREG_SS: return &save->ss;
2443 case VCPU_SREG_TR: return &save->tr;
2444 case VCPU_SREG_LDTR: return &save->ldtr;
2450 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2452 struct vmcb_seg *s = svm_seg(vcpu, seg);
2457 static void svm_get_segment(struct kvm_vcpu *vcpu,
2458 struct kvm_segment *var, int seg)
2460 struct vmcb_seg *s = svm_seg(vcpu, seg);
2462 var->base = s->base;
2463 var->limit = s->limit;
2464 var->selector = s->selector;
2465 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2466 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2467 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2468 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2469 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2470 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2471 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2474 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2475 * However, the SVM spec states that the G bit is not observed by the
2476 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2477 * So let's synthesize a legal G bit for all segments, this helps
2478 * running KVM nested. It also helps cross-vendor migration, because
2479 * Intel's vmentry has a check on the 'G' bit.
2481 var->g = s->limit > 0xfffff;
2484 * AMD's VMCB does not have an explicit unusable field, so emulate it
2485 * for cross vendor migration purposes by "not present"
2487 var->unusable = !var->present;
2492 * Work around a bug where the busy flag in the tr selector
2502 * The accessed bit must always be set in the segment
2503 * descriptor cache, although it can be cleared in the
2504 * descriptor, the cached bit always remains at 1. Since
2505 * Intel has a check on this, set it here to support
2506 * cross-vendor migration.
2513 * On AMD CPUs sometimes the DB bit in the segment
2514 * descriptor is left as 1, although the whole segment has
2515 * been made unusable. Clear it here to pass an Intel VMX
2516 * entry check when cross vendor migrating.
2520 /* This is symmetric with svm_set_segment() */
2521 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2526 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2528 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2533 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2535 struct vcpu_svm *svm = to_svm(vcpu);
2537 dt->size = svm->vmcb->save.idtr.limit;
2538 dt->address = svm->vmcb->save.idtr.base;
2541 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2543 struct vcpu_svm *svm = to_svm(vcpu);
2545 svm->vmcb->save.idtr.limit = dt->size;
2546 svm->vmcb->save.idtr.base = dt->address ;
2547 mark_dirty(svm->vmcb, VMCB_DT);
2550 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2552 struct vcpu_svm *svm = to_svm(vcpu);
2554 dt->size = svm->vmcb->save.gdtr.limit;
2555 dt->address = svm->vmcb->save.gdtr.base;
2558 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2560 struct vcpu_svm *svm = to_svm(vcpu);
2562 svm->vmcb->save.gdtr.limit = dt->size;
2563 svm->vmcb->save.gdtr.base = dt->address ;
2564 mark_dirty(svm->vmcb, VMCB_DT);
2567 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2571 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2575 static void update_cr0_intercept(struct vcpu_svm *svm)
2577 ulong gcr0 = svm->vcpu.arch.cr0;
2578 u64 *hcr0 = &svm->vmcb->save.cr0;
2580 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2581 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2583 mark_dirty(svm->vmcb, VMCB_CR);
2585 if (gcr0 == *hcr0) {
2586 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2587 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2589 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2590 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2594 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2596 struct vcpu_svm *svm = to_svm(vcpu);
2598 #ifdef CONFIG_X86_64
2599 if (vcpu->arch.efer & EFER_LME) {
2600 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2601 vcpu->arch.efer |= EFER_LMA;
2602 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2605 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2606 vcpu->arch.efer &= ~EFER_LMA;
2607 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2611 vcpu->arch.cr0 = cr0;
2614 cr0 |= X86_CR0_PG | X86_CR0_WP;
2617 * re-enable caching here because the QEMU bios
2618 * does not do it - this results in some delay at
2621 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2622 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2623 svm->vmcb->save.cr0 = cr0;
2624 mark_dirty(svm->vmcb, VMCB_CR);
2625 update_cr0_intercept(svm);
2628 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2630 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2631 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2633 if (cr4 & X86_CR4_VMXE)
2636 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2637 svm_flush_tlb(vcpu, true);
2639 vcpu->arch.cr4 = cr4;
2642 cr4 |= host_cr4_mce;
2643 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2644 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2648 static void svm_set_segment(struct kvm_vcpu *vcpu,
2649 struct kvm_segment *var, int seg)
2651 struct vcpu_svm *svm = to_svm(vcpu);
2652 struct vmcb_seg *s = svm_seg(vcpu, seg);
2654 s->base = var->base;
2655 s->limit = var->limit;
2656 s->selector = var->selector;
2657 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2658 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2659 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2660 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2661 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2662 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2663 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2664 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2667 * This is always accurate, except if SYSRET returned to a segment
2668 * with SS.DPL != 3. Intel does not have this quirk, and always
2669 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2670 * would entail passing the CPL to userspace and back.
2672 if (seg == VCPU_SREG_SS)
2673 /* This is symmetric with svm_get_segment() */
2674 svm->vmcb->save.cpl = (var->dpl & 3);
2676 mark_dirty(svm->vmcb, VMCB_SEG);
2679 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2681 struct vcpu_svm *svm = to_svm(vcpu);
2683 clr_exception_intercept(svm, BP_VECTOR);
2685 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2686 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2687 set_exception_intercept(svm, BP_VECTOR);
2689 vcpu->guest_debug = 0;
2692 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2694 if (sd->next_asid > sd->max_asid) {
2695 ++sd->asid_generation;
2696 sd->next_asid = sd->min_asid;
2697 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2700 svm->asid_generation = sd->asid_generation;
2701 svm->vmcb->control.asid = sd->next_asid++;
2703 mark_dirty(svm->vmcb, VMCB_ASID);
2706 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2708 return to_svm(vcpu)->vmcb->save.dr6;
2711 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2713 struct vcpu_svm *svm = to_svm(vcpu);
2715 svm->vmcb->save.dr6 = value;
2716 mark_dirty(svm->vmcb, VMCB_DR);
2719 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2721 struct vcpu_svm *svm = to_svm(vcpu);
2723 get_debugreg(vcpu->arch.db[0], 0);
2724 get_debugreg(vcpu->arch.db[1], 1);
2725 get_debugreg(vcpu->arch.db[2], 2);
2726 get_debugreg(vcpu->arch.db[3], 3);
2727 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2728 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2730 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2731 set_dr_intercepts(svm);
2734 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2736 struct vcpu_svm *svm = to_svm(vcpu);
2738 svm->vmcb->save.dr7 = value;
2739 mark_dirty(svm->vmcb, VMCB_DR);
2742 static int pf_interception(struct vcpu_svm *svm)
2744 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2745 u64 error_code = svm->vmcb->control.exit_info_1;
2747 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2748 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2749 svm->vmcb->control.insn_bytes : NULL,
2750 svm->vmcb->control.insn_len);
2753 static int npf_interception(struct vcpu_svm *svm)
2755 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2756 u64 error_code = svm->vmcb->control.exit_info_1;
2758 trace_kvm_page_fault(fault_address, error_code);
2759 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2760 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2761 svm->vmcb->control.insn_bytes : NULL,
2762 svm->vmcb->control.insn_len);
2765 static int db_interception(struct vcpu_svm *svm)
2767 struct kvm_run *kvm_run = svm->vcpu.run;
2768 struct kvm_vcpu *vcpu = &svm->vcpu;
2770 if (!(svm->vcpu.guest_debug &
2771 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2772 !svm->nmi_singlestep) {
2773 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2777 if (svm->nmi_singlestep) {
2778 disable_nmi_singlestep(svm);
2779 /* Make sure we check for pending NMIs upon entry */
2780 kvm_make_request(KVM_REQ_EVENT, vcpu);
2783 if (svm->vcpu.guest_debug &
2784 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2785 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2786 kvm_run->debug.arch.pc =
2787 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2788 kvm_run->debug.arch.exception = DB_VECTOR;
2795 static int bp_interception(struct vcpu_svm *svm)
2797 struct kvm_run *kvm_run = svm->vcpu.run;
2799 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2800 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2801 kvm_run->debug.arch.exception = BP_VECTOR;
2805 static int ud_interception(struct vcpu_svm *svm)
2807 return handle_ud(&svm->vcpu);
2810 static int ac_interception(struct vcpu_svm *svm)
2812 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2816 static int gp_interception(struct vcpu_svm *svm)
2818 struct kvm_vcpu *vcpu = &svm->vcpu;
2819 u32 error_code = svm->vmcb->control.exit_info_1;
2821 WARN_ON_ONCE(!enable_vmware_backdoor);
2824 * VMware backdoor emulation on #GP interception only handles IN{S},
2825 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
2828 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2831 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
2834 static bool is_erratum_383(void)
2839 if (!erratum_383_found)
2842 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2846 /* Bit 62 may or may not be set for this mce */
2847 value &= ~(1ULL << 62);
2849 if (value != 0xb600000000010015ULL)
2852 /* Clear MCi_STATUS registers */
2853 for (i = 0; i < 6; ++i)
2854 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2856 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2860 value &= ~(1ULL << 2);
2861 low = lower_32_bits(value);
2862 high = upper_32_bits(value);
2864 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2867 /* Flush tlb to evict multi-match entries */
2873 static void svm_handle_mce(struct vcpu_svm *svm)
2875 if (is_erratum_383()) {
2877 * Erratum 383 triggered. Guest state is corrupt so kill the
2880 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2882 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2888 * On an #MC intercept the MCE handler is not called automatically in
2889 * the host. So do it by hand here.
2893 /* not sure if we ever come back to this point */
2898 static int mc_interception(struct vcpu_svm *svm)
2903 static int shutdown_interception(struct vcpu_svm *svm)
2905 struct kvm_run *kvm_run = svm->vcpu.run;
2908 * VMCB is undefined after a SHUTDOWN intercept
2909 * so reinitialize it.
2911 clear_page(svm->vmcb);
2914 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2918 static int io_interception(struct vcpu_svm *svm)
2920 struct kvm_vcpu *vcpu = &svm->vcpu;
2921 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2922 int size, in, string;
2925 ++svm->vcpu.stat.io_exits;
2926 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2927 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2929 return kvm_emulate_instruction(vcpu, 0);
2931 port = io_info >> 16;
2932 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2933 svm->next_rip = svm->vmcb->control.exit_info_2;
2935 return kvm_fast_pio(&svm->vcpu, size, port, in);
2938 static int nmi_interception(struct vcpu_svm *svm)
2943 static int intr_interception(struct vcpu_svm *svm)
2945 ++svm->vcpu.stat.irq_exits;
2949 static int nop_on_interception(struct vcpu_svm *svm)
2954 static int halt_interception(struct vcpu_svm *svm)
2956 return kvm_emulate_halt(&svm->vcpu);
2959 static int vmmcall_interception(struct vcpu_svm *svm)
2961 return kvm_emulate_hypercall(&svm->vcpu);
2964 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2966 struct vcpu_svm *svm = to_svm(vcpu);
2968 return svm->nested.nested_cr3;
2971 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2973 struct vcpu_svm *svm = to_svm(vcpu);
2974 u64 cr3 = svm->nested.nested_cr3;
2978 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2979 offset_in_page(cr3) + index * 8, 8);
2985 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2988 struct vcpu_svm *svm = to_svm(vcpu);
2990 svm->vmcb->control.nested_cr3 = __sme_set(root);
2991 mark_dirty(svm->vmcb, VMCB_NPT);
2994 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2995 struct x86_exception *fault)
2997 struct vcpu_svm *svm = to_svm(vcpu);
2999 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
3001 * TODO: track the cause of the nested page fault, and
3002 * correctly fill in the high bits of exit_info_1.
3004 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
3005 svm->vmcb->control.exit_code_hi = 0;
3006 svm->vmcb->control.exit_info_1 = (1ULL << 32);
3007 svm->vmcb->control.exit_info_2 = fault->address;
3010 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
3011 svm->vmcb->control.exit_info_1 |= fault->error_code;
3014 * The present bit is always zero for page structure faults on real
3017 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
3018 svm->vmcb->control.exit_info_1 &= ~1;
3020 nested_svm_vmexit(svm);
3023 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
3025 WARN_ON(mmu_is_nested(vcpu));
3027 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
3028 kvm_init_shadow_mmu(vcpu);
3029 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
3030 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
3031 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
3032 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
3033 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
3034 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
3035 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
3038 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
3040 vcpu->arch.mmu = &vcpu->arch.root_mmu;
3041 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
3044 static int nested_svm_check_permissions(struct vcpu_svm *svm)
3046 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
3047 !is_paging(&svm->vcpu)) {
3048 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3052 if (svm->vmcb->save.cpl) {
3053 kvm_inject_gp(&svm->vcpu, 0);
3060 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
3061 bool has_error_code, u32 error_code)
3065 if (!is_guest_mode(&svm->vcpu))
3068 vmexit = nested_svm_intercept(svm);
3069 if (vmexit != NESTED_EXIT_DONE)
3072 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3073 svm->vmcb->control.exit_code_hi = 0;
3074 svm->vmcb->control.exit_info_1 = error_code;
3077 * EXITINFO2 is undefined for all exception intercepts other
3080 if (svm->vcpu.arch.exception.nested_apf)
3081 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3082 else if (svm->vcpu.arch.exception.has_payload)
3083 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3085 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3087 svm->nested.exit_required = true;
3091 /* This function returns true if it is save to enable the irq window */
3092 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3094 if (!is_guest_mode(&svm->vcpu))
3097 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3100 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3104 * if vmexit was already requested (by intercepted exception
3105 * for instance) do not overwrite it with "external interrupt"
3108 if (svm->nested.exit_required)
3111 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3112 svm->vmcb->control.exit_info_1 = 0;
3113 svm->vmcb->control.exit_info_2 = 0;
3115 if (svm->nested.intercept & 1ULL) {
3117 * The #vmexit can't be emulated here directly because this
3118 * code path runs with irqs and preemption disabled. A
3119 * #vmexit emulation might sleep. Only signal request for
3122 svm->nested.exit_required = true;
3123 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3130 /* This function returns true if it is save to enable the nmi window */
3131 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3133 if (!is_guest_mode(&svm->vcpu))
3136 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3139 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3140 svm->nested.exit_required = true;
3145 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3147 unsigned port, size, iopm_len;
3152 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3153 return NESTED_EXIT_HOST;
3155 port = svm->vmcb->control.exit_info_1 >> 16;
3156 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3157 SVM_IOIO_SIZE_SHIFT;
3158 gpa = svm->nested.vmcb_iopm + (port / 8);
3159 start_bit = port % 8;
3160 iopm_len = (start_bit + size > 8) ? 2 : 1;
3161 mask = (0xf >> (4 - size)) << start_bit;
3164 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3165 return NESTED_EXIT_DONE;
3167 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3170 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3172 u32 offset, msr, value;
3175 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3176 return NESTED_EXIT_HOST;
3178 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3179 offset = svm_msrpm_offset(msr);
3180 write = svm->vmcb->control.exit_info_1 & 1;
3181 mask = 1 << ((2 * (msr & 0xf)) + write);
3183 if (offset == MSR_INVALID)
3184 return NESTED_EXIT_DONE;
3186 /* Offset is in 32 bit units but need in 8 bit units */
3189 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3190 return NESTED_EXIT_DONE;
3192 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3195 /* DB exceptions for our internal use must not cause vmexit */
3196 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3200 /* if we're not singlestepping, it's not ours */
3201 if (!svm->nmi_singlestep)
3202 return NESTED_EXIT_DONE;
3204 /* if it's not a singlestep exception, it's not ours */
3205 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3206 return NESTED_EXIT_DONE;
3207 if (!(dr6 & DR6_BS))
3208 return NESTED_EXIT_DONE;
3210 /* if the guest is singlestepping, it should get the vmexit */
3211 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3212 disable_nmi_singlestep(svm);
3213 return NESTED_EXIT_DONE;
3216 /* it's ours, the nested hypervisor must not see this one */
3217 return NESTED_EXIT_HOST;
3220 static int nested_svm_exit_special(struct vcpu_svm *svm)
3222 u32 exit_code = svm->vmcb->control.exit_code;
3224 switch (exit_code) {
3227 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3228 return NESTED_EXIT_HOST;
3230 /* For now we are always handling NPFs when using them */
3232 return NESTED_EXIT_HOST;
3234 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3235 /* When we're shadowing, trap PFs, but not async PF */
3236 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3237 return NESTED_EXIT_HOST;
3243 return NESTED_EXIT_CONTINUE;
3247 * If this function returns true, this #vmexit was already handled
3249 static int nested_svm_intercept(struct vcpu_svm *svm)
3251 u32 exit_code = svm->vmcb->control.exit_code;
3252 int vmexit = NESTED_EXIT_HOST;
3254 switch (exit_code) {
3256 vmexit = nested_svm_exit_handled_msr(svm);
3259 vmexit = nested_svm_intercept_ioio(svm);
3261 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3262 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3263 if (svm->nested.intercept_cr & bit)
3264 vmexit = NESTED_EXIT_DONE;
3267 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3268 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3269 if (svm->nested.intercept_dr & bit)
3270 vmexit = NESTED_EXIT_DONE;
3273 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3274 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3275 if (svm->nested.intercept_exceptions & excp_bits) {
3276 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3277 vmexit = nested_svm_intercept_db(svm);
3279 vmexit = NESTED_EXIT_DONE;
3281 /* async page fault always cause vmexit */
3282 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3283 svm->vcpu.arch.exception.nested_apf != 0)
3284 vmexit = NESTED_EXIT_DONE;
3287 case SVM_EXIT_ERR: {
3288 vmexit = NESTED_EXIT_DONE;
3292 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3293 if (svm->nested.intercept & exit_bits)
3294 vmexit = NESTED_EXIT_DONE;
3301 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3305 vmexit = nested_svm_intercept(svm);
3307 if (vmexit == NESTED_EXIT_DONE)
3308 nested_svm_vmexit(svm);
3313 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3315 struct vmcb_control_area *dst = &dst_vmcb->control;
3316 struct vmcb_control_area *from = &from_vmcb->control;
3318 dst->intercept_cr = from->intercept_cr;
3319 dst->intercept_dr = from->intercept_dr;
3320 dst->intercept_exceptions = from->intercept_exceptions;
3321 dst->intercept = from->intercept;
3322 dst->iopm_base_pa = from->iopm_base_pa;
3323 dst->msrpm_base_pa = from->msrpm_base_pa;
3324 dst->tsc_offset = from->tsc_offset;
3325 dst->asid = from->asid;
3326 dst->tlb_ctl = from->tlb_ctl;
3327 dst->int_ctl = from->int_ctl;
3328 dst->int_vector = from->int_vector;
3329 dst->int_state = from->int_state;
3330 dst->exit_code = from->exit_code;
3331 dst->exit_code_hi = from->exit_code_hi;
3332 dst->exit_info_1 = from->exit_info_1;
3333 dst->exit_info_2 = from->exit_info_2;
3334 dst->exit_int_info = from->exit_int_info;
3335 dst->exit_int_info_err = from->exit_int_info_err;
3336 dst->nested_ctl = from->nested_ctl;
3337 dst->event_inj = from->event_inj;
3338 dst->event_inj_err = from->event_inj_err;
3339 dst->nested_cr3 = from->nested_cr3;
3340 dst->virt_ext = from->virt_ext;
3341 dst->pause_filter_count = from->pause_filter_count;
3342 dst->pause_filter_thresh = from->pause_filter_thresh;
3345 static int nested_svm_vmexit(struct vcpu_svm *svm)
3348 struct vmcb *nested_vmcb;
3349 struct vmcb *hsave = svm->nested.hsave;
3350 struct vmcb *vmcb = svm->vmcb;
3351 struct kvm_host_map map;
3353 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3354 vmcb->control.exit_info_1,
3355 vmcb->control.exit_info_2,
3356 vmcb->control.exit_int_info,
3357 vmcb->control.exit_int_info_err,
3360 rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
3363 kvm_inject_gp(&svm->vcpu, 0);
3367 nested_vmcb = map.hva;
3369 /* Exit Guest-Mode */
3370 leave_guest_mode(&svm->vcpu);
3371 svm->nested.vmcb = 0;
3373 /* Give the current vmcb to the guest */
3376 nested_vmcb->save.es = vmcb->save.es;
3377 nested_vmcb->save.cs = vmcb->save.cs;
3378 nested_vmcb->save.ss = vmcb->save.ss;
3379 nested_vmcb->save.ds = vmcb->save.ds;
3380 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3381 nested_vmcb->save.idtr = vmcb->save.idtr;
3382 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3383 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3384 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3385 nested_vmcb->save.cr2 = vmcb->save.cr2;
3386 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3387 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3388 nested_vmcb->save.rip = vmcb->save.rip;
3389 nested_vmcb->save.rsp = vmcb->save.rsp;
3390 nested_vmcb->save.rax = vmcb->save.rax;
3391 nested_vmcb->save.dr7 = vmcb->save.dr7;
3392 nested_vmcb->save.dr6 = vmcb->save.dr6;
3393 nested_vmcb->save.cpl = vmcb->save.cpl;
3395 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3396 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3397 nested_vmcb->control.int_state = vmcb->control.int_state;
3398 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3399 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3400 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3401 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3402 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3403 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3405 if (svm->nrips_enabled)
3406 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3409 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3410 * to make sure that we do not lose injected events. So check event_inj
3411 * here and copy it to exit_int_info if it is valid.
3412 * Exit_int_info and event_inj can't be both valid because the case
3413 * below only happens on a VMRUN instruction intercept which has
3414 * no valid exit_int_info set.
3416 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3417 struct vmcb_control_area *nc = &nested_vmcb->control;
3419 nc->exit_int_info = vmcb->control.event_inj;
3420 nc->exit_int_info_err = vmcb->control.event_inj_err;
3423 nested_vmcb->control.tlb_ctl = 0;
3424 nested_vmcb->control.event_inj = 0;
3425 nested_vmcb->control.event_inj_err = 0;
3427 nested_vmcb->control.pause_filter_count =
3428 svm->vmcb->control.pause_filter_count;
3429 nested_vmcb->control.pause_filter_thresh =
3430 svm->vmcb->control.pause_filter_thresh;
3432 /* We always set V_INTR_MASKING and remember the old value in hflags */
3433 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3434 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3436 /* Restore the original control entries */
3437 copy_vmcb_control_area(vmcb, hsave);
3439 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3440 kvm_clear_exception_queue(&svm->vcpu);
3441 kvm_clear_interrupt_queue(&svm->vcpu);
3443 svm->nested.nested_cr3 = 0;
3445 /* Restore selected save entries */
3446 svm->vmcb->save.es = hsave->save.es;
3447 svm->vmcb->save.cs = hsave->save.cs;
3448 svm->vmcb->save.ss = hsave->save.ss;
3449 svm->vmcb->save.ds = hsave->save.ds;
3450 svm->vmcb->save.gdtr = hsave->save.gdtr;
3451 svm->vmcb->save.idtr = hsave->save.idtr;
3452 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3453 svm_set_efer(&svm->vcpu, hsave->save.efer);
3454 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3455 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3457 svm->vmcb->save.cr3 = hsave->save.cr3;
3458 svm->vcpu.arch.cr3 = hsave->save.cr3;
3460 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3462 kvm_rax_write(&svm->vcpu, hsave->save.rax);
3463 kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3464 kvm_rip_write(&svm->vcpu, hsave->save.rip);
3465 svm->vmcb->save.dr7 = 0;
3466 svm->vmcb->save.cpl = 0;
3467 svm->vmcb->control.exit_int_info = 0;
3469 mark_all_dirty(svm->vmcb);
3471 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3473 nested_svm_uninit_mmu_context(&svm->vcpu);
3474 kvm_mmu_reset_context(&svm->vcpu);
3475 kvm_mmu_load(&svm->vcpu);
3478 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3479 * doesn't end up in L1.
3481 svm->vcpu.arch.nmi_injected = false;
3482 kvm_clear_exception_queue(&svm->vcpu);
3483 kvm_clear_interrupt_queue(&svm->vcpu);
3488 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3491 * This function merges the msr permission bitmaps of kvm and the
3492 * nested vmcb. It is optimized in that it only merges the parts where
3493 * the kvm msr permission bitmap may contain zero bits
3497 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3500 for (i = 0; i < MSRPM_OFFSETS; i++) {
3504 if (msrpm_offsets[i] == 0xffffffff)
3507 p = msrpm_offsets[i];
3508 offset = svm->nested.vmcb_msrpm + (p * 4);
3510 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3513 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3516 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3521 static bool nested_vmcb_checks(struct vmcb *vmcb)
3523 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3526 if (vmcb->control.asid == 0)
3529 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3536 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3537 struct vmcb *nested_vmcb, struct kvm_host_map *map)
3539 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3540 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3542 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3544 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3545 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3546 nested_svm_init_mmu_context(&svm->vcpu);
3549 /* Load the nested guest state */
3550 svm->vmcb->save.es = nested_vmcb->save.es;
3551 svm->vmcb->save.cs = nested_vmcb->save.cs;
3552 svm->vmcb->save.ss = nested_vmcb->save.ss;
3553 svm->vmcb->save.ds = nested_vmcb->save.ds;
3554 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3555 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3556 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3557 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3558 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3559 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3561 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3562 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3564 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3566 /* Guest paging mode is active - reset mmu */
3567 kvm_mmu_reset_context(&svm->vcpu);
3569 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3570 kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3571 kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3572 kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3574 /* In case we don't even reach vcpu_run, the fields are not updated */
3575 svm->vmcb->save.rax = nested_vmcb->save.rax;
3576 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3577 svm->vmcb->save.rip = nested_vmcb->save.rip;
3578 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3579 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3580 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3582 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3583 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3585 /* cache intercepts */
3586 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3587 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3588 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3589 svm->nested.intercept = nested_vmcb->control.intercept;
3591 svm_flush_tlb(&svm->vcpu, true);
3592 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3593 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3594 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3596 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3598 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3599 /* We only want the cr8 intercept bits of the guest */
3600 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3601 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3604 /* We don't want to see VMMCALLs from a nested guest */
3605 clr_intercept(svm, INTERCEPT_VMMCALL);
3607 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3608 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3610 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3611 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3612 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3613 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3614 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3616 svm->vmcb->control.pause_filter_count =
3617 nested_vmcb->control.pause_filter_count;
3618 svm->vmcb->control.pause_filter_thresh =
3619 nested_vmcb->control.pause_filter_thresh;
3621 kvm_vcpu_unmap(&svm->vcpu, map, true);
3623 /* Enter Guest-Mode */
3624 enter_guest_mode(&svm->vcpu);
3627 * Merge guest and host intercepts - must be called with vcpu in
3628 * guest-mode to take affect here
3630 recalc_intercepts(svm);
3632 svm->nested.vmcb = vmcb_gpa;
3636 mark_all_dirty(svm->vmcb);
3639 static int nested_svm_vmrun(struct vcpu_svm *svm)
3642 struct vmcb *nested_vmcb;
3643 struct vmcb *hsave = svm->nested.hsave;
3644 struct vmcb *vmcb = svm->vmcb;
3645 struct kvm_host_map map;
3648 vmcb_gpa = svm->vmcb->save.rax;
3650 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
3651 if (ret == -EINVAL) {
3652 kvm_inject_gp(&svm->vcpu, 0);
3655 return kvm_skip_emulated_instruction(&svm->vcpu);
3658 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3660 nested_vmcb = map.hva;
3662 if (!nested_vmcb_checks(nested_vmcb)) {
3663 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3664 nested_vmcb->control.exit_code_hi = 0;
3665 nested_vmcb->control.exit_info_1 = 0;
3666 nested_vmcb->control.exit_info_2 = 0;
3668 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3673 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3674 nested_vmcb->save.rip,
3675 nested_vmcb->control.int_ctl,
3676 nested_vmcb->control.event_inj,
3677 nested_vmcb->control.nested_ctl);
3679 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3680 nested_vmcb->control.intercept_cr >> 16,
3681 nested_vmcb->control.intercept_exceptions,
3682 nested_vmcb->control.intercept);
3684 /* Clear internal status */
3685 kvm_clear_exception_queue(&svm->vcpu);
3686 kvm_clear_interrupt_queue(&svm->vcpu);
3689 * Save the old vmcb, so we don't need to pick what we save, but can
3690 * restore everything when a VMEXIT occurs
3692 hsave->save.es = vmcb->save.es;
3693 hsave->save.cs = vmcb->save.cs;
3694 hsave->save.ss = vmcb->save.ss;
3695 hsave->save.ds = vmcb->save.ds;
3696 hsave->save.gdtr = vmcb->save.gdtr;
3697 hsave->save.idtr = vmcb->save.idtr;
3698 hsave->save.efer = svm->vcpu.arch.efer;
3699 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3700 hsave->save.cr4 = svm->vcpu.arch.cr4;
3701 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3702 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3703 hsave->save.rsp = vmcb->save.rsp;
3704 hsave->save.rax = vmcb->save.rax;
3706 hsave->save.cr3 = vmcb->save.cr3;
3708 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3710 copy_vmcb_control_area(hsave, vmcb);
3712 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3714 if (!nested_svm_vmrun_msrpm(svm)) {
3715 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3716 svm->vmcb->control.exit_code_hi = 0;
3717 svm->vmcb->control.exit_info_1 = 0;
3718 svm->vmcb->control.exit_info_2 = 0;
3720 nested_svm_vmexit(svm);
3726 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3728 to_vmcb->save.fs = from_vmcb->save.fs;
3729 to_vmcb->save.gs = from_vmcb->save.gs;
3730 to_vmcb->save.tr = from_vmcb->save.tr;
3731 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3732 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3733 to_vmcb->save.star = from_vmcb->save.star;
3734 to_vmcb->save.lstar = from_vmcb->save.lstar;
3735 to_vmcb->save.cstar = from_vmcb->save.cstar;
3736 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3737 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3738 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3739 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3742 static int vmload_interception(struct vcpu_svm *svm)
3744 struct vmcb *nested_vmcb;
3745 struct kvm_host_map map;
3748 if (nested_svm_check_permissions(svm))
3751 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3754 kvm_inject_gp(&svm->vcpu, 0);
3758 nested_vmcb = map.hva;
3760 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3762 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3763 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3768 static int vmsave_interception(struct vcpu_svm *svm)
3770 struct vmcb *nested_vmcb;
3771 struct kvm_host_map map;
3774 if (nested_svm_check_permissions(svm))
3777 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3780 kvm_inject_gp(&svm->vcpu, 0);
3784 nested_vmcb = map.hva;
3786 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3788 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3789 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3794 static int vmrun_interception(struct vcpu_svm *svm)
3796 if (nested_svm_check_permissions(svm))
3799 return nested_svm_vmrun(svm);
3802 static int stgi_interception(struct vcpu_svm *svm)
3806 if (nested_svm_check_permissions(svm))
3810 * If VGIF is enabled, the STGI intercept is only added to
3811 * detect the opening of the SMI/NMI window; remove it now.
3813 if (vgif_enabled(svm))
3814 clr_intercept(svm, INTERCEPT_STGI);
3816 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3817 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3824 static int clgi_interception(struct vcpu_svm *svm)
3828 if (nested_svm_check_permissions(svm))
3831 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3835 /* After a CLGI no interrupts should come */
3836 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3837 svm_clear_vintr(svm);
3838 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3839 mark_dirty(svm->vmcb, VMCB_INTR);
3845 static int invlpga_interception(struct vcpu_svm *svm)
3847 struct kvm_vcpu *vcpu = &svm->vcpu;
3849 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3850 kvm_rax_read(&svm->vcpu));
3852 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3853 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3855 return kvm_skip_emulated_instruction(&svm->vcpu);
3858 static int skinit_interception(struct vcpu_svm *svm)
3860 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3862 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3866 static int wbinvd_interception(struct vcpu_svm *svm)
3868 return kvm_emulate_wbinvd(&svm->vcpu);
3871 static int xsetbv_interception(struct vcpu_svm *svm)
3873 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3874 u32 index = kvm_rcx_read(&svm->vcpu);
3876 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3877 return kvm_skip_emulated_instruction(&svm->vcpu);
3883 static int rdpru_interception(struct vcpu_svm *svm)
3885 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3889 static int task_switch_interception(struct vcpu_svm *svm)
3893 int int_type = svm->vmcb->control.exit_int_info &
3894 SVM_EXITINTINFO_TYPE_MASK;
3895 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3897 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3899 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3900 bool has_error_code = false;
3903 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3905 if (svm->vmcb->control.exit_info_2 &
3906 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3907 reason = TASK_SWITCH_IRET;
3908 else if (svm->vmcb->control.exit_info_2 &
3909 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3910 reason = TASK_SWITCH_JMP;
3912 reason = TASK_SWITCH_GATE;
3914 reason = TASK_SWITCH_CALL;
3916 if (reason == TASK_SWITCH_GATE) {
3918 case SVM_EXITINTINFO_TYPE_NMI:
3919 svm->vcpu.arch.nmi_injected = false;
3921 case SVM_EXITINTINFO_TYPE_EXEPT:
3922 if (svm->vmcb->control.exit_info_2 &
3923 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3924 has_error_code = true;
3926 (u32)svm->vmcb->control.exit_info_2;
3928 kvm_clear_exception_queue(&svm->vcpu);
3930 case SVM_EXITINTINFO_TYPE_INTR:
3931 kvm_clear_interrupt_queue(&svm->vcpu);
3938 if (reason != TASK_SWITCH_GATE ||
3939 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3940 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3941 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
3942 if (!skip_emulated_instruction(&svm->vcpu))
3946 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3949 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3950 has_error_code, error_code);
3953 static int cpuid_interception(struct vcpu_svm *svm)
3955 return kvm_emulate_cpuid(&svm->vcpu);
3958 static int iret_interception(struct vcpu_svm *svm)
3960 ++svm->vcpu.stat.nmi_window_exits;
3961 clr_intercept(svm, INTERCEPT_IRET);
3962 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3963 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3964 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3968 static int invlpg_interception(struct vcpu_svm *svm)
3970 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3971 return kvm_emulate_instruction(&svm->vcpu, 0);
3973 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3974 return kvm_skip_emulated_instruction(&svm->vcpu);
3977 static int emulate_on_interception(struct vcpu_svm *svm)
3979 return kvm_emulate_instruction(&svm->vcpu, 0);
3982 static int rsm_interception(struct vcpu_svm *svm)
3984 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
3987 static int rdpmc_interception(struct vcpu_svm *svm)
3992 return emulate_on_interception(svm);
3994 err = kvm_rdpmc(&svm->vcpu);
3995 return kvm_complete_insn_gp(&svm->vcpu, err);
3998 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
4001 unsigned long cr0 = svm->vcpu.arch.cr0;
4005 intercept = svm->nested.intercept;
4007 if (!is_guest_mode(&svm->vcpu) ||
4008 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
4011 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
4012 val &= ~SVM_CR0_SELECTIVE_MASK;
4015 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4016 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
4022 #define CR_VALID (1ULL << 63)
4024 static int cr_interception(struct vcpu_svm *svm)
4030 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
4031 return emulate_on_interception(svm);
4033 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
4034 return emulate_on_interception(svm);
4036 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4037 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
4038 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
4040 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
4043 if (cr >= 16) { /* mov to cr */
4045 val = kvm_register_read(&svm->vcpu, reg);
4048 if (!check_selective_cr0_intercepted(svm, val))
4049 err = kvm_set_cr0(&svm->vcpu, val);
4055 err = kvm_set_cr3(&svm->vcpu, val);
4058 err = kvm_set_cr4(&svm->vcpu, val);
4061 err = kvm_set_cr8(&svm->vcpu, val);
4064 WARN(1, "unhandled write to CR%d", cr);
4065 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4068 } else { /* mov from cr */
4071 val = kvm_read_cr0(&svm->vcpu);
4074 val = svm->vcpu.arch.cr2;
4077 val = kvm_read_cr3(&svm->vcpu);
4080 val = kvm_read_cr4(&svm->vcpu);
4083 val = kvm_get_cr8(&svm->vcpu);
4086 WARN(1, "unhandled read from CR%d", cr);
4087 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4090 kvm_register_write(&svm->vcpu, reg, val);
4092 return kvm_complete_insn_gp(&svm->vcpu, err);
4095 static int dr_interception(struct vcpu_svm *svm)
4100 if (svm->vcpu.guest_debug == 0) {
4102 * No more DR vmexits; force a reload of the debug registers
4103 * and reenter on this instruction. The next vmexit will
4104 * retrieve the full state of the debug registers.
4106 clr_dr_intercepts(svm);
4107 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4111 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4112 return emulate_on_interception(svm);
4114 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4115 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4117 if (dr >= 16) { /* mov to DRn */
4118 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4120 val = kvm_register_read(&svm->vcpu, reg);
4121 kvm_set_dr(&svm->vcpu, dr - 16, val);
4123 if (!kvm_require_dr(&svm->vcpu, dr))
4125 kvm_get_dr(&svm->vcpu, dr, &val);
4126 kvm_register_write(&svm->vcpu, reg, val);
4129 return kvm_skip_emulated_instruction(&svm->vcpu);
4132 static int cr8_write_interception(struct vcpu_svm *svm)
4134 struct kvm_run *kvm_run = svm->vcpu.run;
4137 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4138 /* instruction emulation calls kvm_set_cr8() */
4139 r = cr_interception(svm);
4140 if (lapic_in_kernel(&svm->vcpu))
4142 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4144 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4148 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4152 switch (msr->index) {
4153 case MSR_F10H_DECFG:
4154 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4155 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4164 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4166 struct vcpu_svm *svm = to_svm(vcpu);
4168 switch (msr_info->index) {
4170 msr_info->data = svm->vmcb->save.star;
4172 #ifdef CONFIG_X86_64
4174 msr_info->data = svm->vmcb->save.lstar;
4177 msr_info->data = svm->vmcb->save.cstar;
4179 case MSR_KERNEL_GS_BASE:
4180 msr_info->data = svm->vmcb->save.kernel_gs_base;
4182 case MSR_SYSCALL_MASK:
4183 msr_info->data = svm->vmcb->save.sfmask;
4186 case MSR_IA32_SYSENTER_CS:
4187 msr_info->data = svm->vmcb->save.sysenter_cs;
4189 case MSR_IA32_SYSENTER_EIP:
4190 msr_info->data = svm->sysenter_eip;
4192 case MSR_IA32_SYSENTER_ESP:
4193 msr_info->data = svm->sysenter_esp;
4196 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4198 msr_info->data = svm->tsc_aux;
4201 * Nobody will change the following 5 values in the VMCB so we can
4202 * safely return them on rdmsr. They will always be 0 until LBRV is
4205 case MSR_IA32_DEBUGCTLMSR:
4206 msr_info->data = svm->vmcb->save.dbgctl;
4208 case MSR_IA32_LASTBRANCHFROMIP:
4209 msr_info->data = svm->vmcb->save.br_from;
4211 case MSR_IA32_LASTBRANCHTOIP:
4212 msr_info->data = svm->vmcb->save.br_to;
4214 case MSR_IA32_LASTINTFROMIP:
4215 msr_info->data = svm->vmcb->save.last_excp_from;
4217 case MSR_IA32_LASTINTTOIP:
4218 msr_info->data = svm->vmcb->save.last_excp_to;
4220 case MSR_VM_HSAVE_PA:
4221 msr_info->data = svm->nested.hsave_msr;
4224 msr_info->data = svm->nested.vm_cr_msr;
4226 case MSR_IA32_SPEC_CTRL:
4227 if (!msr_info->host_initiated &&
4228 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4229 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4232 msr_info->data = svm->spec_ctrl;
4234 case MSR_AMD64_VIRT_SPEC_CTRL:
4235 if (!msr_info->host_initiated &&
4236 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4239 msr_info->data = svm->virt_spec_ctrl;
4241 case MSR_F15H_IC_CFG: {
4245 family = guest_cpuid_family(vcpu);
4246 model = guest_cpuid_model(vcpu);
4248 if (family < 0 || model < 0)
4249 return kvm_get_msr_common(vcpu, msr_info);
4253 if (family == 0x15 &&
4254 (model >= 0x2 && model < 0x20))
4255 msr_info->data = 0x1E;
4258 case MSR_F10H_DECFG:
4259 msr_info->data = svm->msr_decfg;
4262 return kvm_get_msr_common(vcpu, msr_info);
4267 static int rdmsr_interception(struct vcpu_svm *svm)
4269 return kvm_emulate_rdmsr(&svm->vcpu);
4272 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4274 struct vcpu_svm *svm = to_svm(vcpu);
4275 int svm_dis, chg_mask;
4277 if (data & ~SVM_VM_CR_VALID_MASK)
4280 chg_mask = SVM_VM_CR_VALID_MASK;
4282 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4283 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4285 svm->nested.vm_cr_msr &= ~chg_mask;
4286 svm->nested.vm_cr_msr |= (data & chg_mask);
4288 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4290 /* check for svm_disable while efer.svme is set */
4291 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4297 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4299 struct vcpu_svm *svm = to_svm(vcpu);
4301 u32 ecx = msr->index;
4302 u64 data = msr->data;
4304 case MSR_IA32_CR_PAT:
4305 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4307 vcpu->arch.pat = data;
4308 svm->vmcb->save.g_pat = data;
4309 mark_dirty(svm->vmcb, VMCB_NPT);
4311 case MSR_IA32_SPEC_CTRL:
4312 if (!msr->host_initiated &&
4313 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4314 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4317 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
4320 svm->spec_ctrl = data;
4326 * When it's written (to non-zero) for the first time, pass
4330 * The handling of the MSR bitmap for L2 guests is done in
4331 * nested_svm_vmrun_msrpm.
4332 * We update the L1 MSR bit as well since it will end up
4333 * touching the MSR anyway now.
4335 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4337 case MSR_IA32_PRED_CMD:
4338 if (!msr->host_initiated &&
4339 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4342 if (data & ~PRED_CMD_IBPB)
4344 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
4349 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4350 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4352 case MSR_AMD64_VIRT_SPEC_CTRL:
4353 if (!msr->host_initiated &&
4354 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4357 if (data & ~SPEC_CTRL_SSBD)
4360 svm->virt_spec_ctrl = data;
4363 svm->vmcb->save.star = data;
4365 #ifdef CONFIG_X86_64
4367 svm->vmcb->save.lstar = data;
4370 svm->vmcb->save.cstar = data;
4372 case MSR_KERNEL_GS_BASE:
4373 svm->vmcb->save.kernel_gs_base = data;
4375 case MSR_SYSCALL_MASK:
4376 svm->vmcb->save.sfmask = data;
4379 case MSR_IA32_SYSENTER_CS:
4380 svm->vmcb->save.sysenter_cs = data;
4382 case MSR_IA32_SYSENTER_EIP:
4383 svm->sysenter_eip = data;
4384 svm->vmcb->save.sysenter_eip = data;
4386 case MSR_IA32_SYSENTER_ESP:
4387 svm->sysenter_esp = data;
4388 svm->vmcb->save.sysenter_esp = data;
4391 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4395 * This is rare, so we update the MSR here instead of using
4396 * direct_access_msrs. Doing that would require a rdmsr in
4399 svm->tsc_aux = data;
4400 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4402 case MSR_IA32_DEBUGCTLMSR:
4403 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4404 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4408 if (data & DEBUGCTL_RESERVED_BITS)
4411 svm->vmcb->save.dbgctl = data;
4412 mark_dirty(svm->vmcb, VMCB_LBR);
4413 if (data & (1ULL<<0))
4414 svm_enable_lbrv(svm);
4416 svm_disable_lbrv(svm);
4418 case MSR_VM_HSAVE_PA:
4419 svm->nested.hsave_msr = data;
4422 return svm_set_vm_cr(vcpu, data);
4424 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4426 case MSR_F10H_DECFG: {
4427 struct kvm_msr_entry msr_entry;
4429 msr_entry.index = msr->index;
4430 if (svm_get_msr_feature(&msr_entry))
4433 /* Check the supported bits */
4434 if (data & ~msr_entry.data)
4437 /* Don't allow the guest to change a bit, #GP */
4438 if (!msr->host_initiated && (data ^ msr_entry.data))
4441 svm->msr_decfg = data;
4444 case MSR_IA32_APICBASE:
4445 if (kvm_vcpu_apicv_active(vcpu))
4446 avic_update_vapic_bar(to_svm(vcpu), data);
4449 return kvm_set_msr_common(vcpu, msr);
4454 static int wrmsr_interception(struct vcpu_svm *svm)
4456 return kvm_emulate_wrmsr(&svm->vcpu);
4459 static int msr_interception(struct vcpu_svm *svm)
4461 if (svm->vmcb->control.exit_info_1)
4462 return wrmsr_interception(svm);
4464 return rdmsr_interception(svm);
4467 static int interrupt_window_interception(struct vcpu_svm *svm)
4469 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4470 svm_clear_vintr(svm);
4473 * For AVIC, the only reason to end up here is ExtINTs.
4474 * In this case AVIC was temporarily disabled for
4475 * requesting the IRQ window and we have to re-enable it.
4477 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
4479 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4480 mark_dirty(svm->vmcb, VMCB_INTR);
4481 ++svm->vcpu.stat.irq_window_exits;
4485 static int pause_interception(struct vcpu_svm *svm)
4487 struct kvm_vcpu *vcpu = &svm->vcpu;
4488 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4490 if (pause_filter_thresh)
4491 grow_ple_window(vcpu);
4493 kvm_vcpu_on_spin(vcpu, in_kernel);
4497 static int nop_interception(struct vcpu_svm *svm)
4499 return kvm_skip_emulated_instruction(&(svm->vcpu));
4502 static int monitor_interception(struct vcpu_svm *svm)
4504 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4505 return nop_interception(svm);
4508 static int mwait_interception(struct vcpu_svm *svm)
4510 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4511 return nop_interception(svm);
4514 enum avic_ipi_failure_cause {
4515 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4516 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4517 AVIC_IPI_FAILURE_INVALID_TARGET,
4518 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4521 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4523 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4524 u32 icrl = svm->vmcb->control.exit_info_1;
4525 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4526 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4527 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4529 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4532 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4534 * AVIC hardware handles the generation of
4535 * IPIs when the specified Message Type is Fixed
4536 * (also known as fixed delivery mode) and
4537 * the Trigger Mode is edge-triggered. The hardware
4538 * also supports self and broadcast delivery modes
4539 * specified via the Destination Shorthand(DSH)
4540 * field of the ICRL. Logical and physical APIC ID
4541 * formats are supported. All other IPI types cause
4542 * a #VMEXIT, which needs to emulated.
4544 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4545 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4547 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4549 struct kvm_vcpu *vcpu;
4550 struct kvm *kvm = svm->vcpu.kvm;
4551 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4554 * At this point, we expect that the AVIC HW has already
4555 * set the appropriate IRR bits on the valid target
4556 * vcpus. So, we just need to kick the appropriate vcpu.
4558 kvm_for_each_vcpu(i, vcpu, kvm) {
4559 bool m = kvm_apic_match_dest(vcpu, apic,
4560 icrl & APIC_SHORT_MASK,
4561 GET_APIC_DEST_FIELD(icrh),
4562 icrl & APIC_DEST_MASK);
4564 if (m && !avic_vcpu_is_running(vcpu))
4565 kvm_vcpu_wake_up(vcpu);
4569 case AVIC_IPI_FAILURE_INVALID_TARGET:
4570 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4571 index, svm->vcpu.vcpu_id, icrh, icrl);
4573 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4574 WARN_ONCE(1, "Invalid backing page\n");
4577 pr_err("Unknown IPI interception\n");
4583 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4585 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4587 u32 *logical_apic_id_table;
4588 int dlid = GET_APIC_LOGICAL_ID(ldr);
4593 if (flat) { /* flat */
4594 index = ffs(dlid) - 1;
4597 } else { /* cluster */
4598 int cluster = (dlid & 0xf0) >> 4;
4599 int apic = ffs(dlid & 0x0f) - 1;
4601 if ((apic < 0) || (apic > 7) ||
4604 index = (cluster << 2) + apic;
4607 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4609 return &logical_apic_id_table[index];
4612 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4615 u32 *entry, new_entry;
4617 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4618 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4622 new_entry = READ_ONCE(*entry);
4623 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4624 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4625 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4626 WRITE_ONCE(*entry, new_entry);
4631 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4633 struct vcpu_svm *svm = to_svm(vcpu);
4634 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4635 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4638 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4641 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4644 struct vcpu_svm *svm = to_svm(vcpu);
4645 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4646 u32 id = kvm_xapic_id(vcpu->arch.apic);
4648 if (ldr == svm->ldr_reg)
4651 avic_invalidate_logical_id_entry(vcpu);
4654 ret = avic_ldr_write(vcpu, id, ldr);
4662 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4665 struct vcpu_svm *svm = to_svm(vcpu);
4666 u32 id = kvm_xapic_id(vcpu->arch.apic);
4668 if (vcpu->vcpu_id == id)
4671 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4672 new = avic_get_physical_id_entry(vcpu, id);
4676 /* We need to move physical_id_entry to new offset */
4679 to_svm(vcpu)->avic_physical_id_cache = new;
4682 * Also update the guest physical APIC ID in the logical
4683 * APIC ID table entry if already setup the LDR.
4686 avic_handle_ldr_update(vcpu);
4691 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4693 struct vcpu_svm *svm = to_svm(vcpu);
4694 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4696 if (svm->dfr_reg == dfr)
4699 avic_invalidate_logical_id_entry(vcpu);
4703 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4705 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4706 u32 offset = svm->vmcb->control.exit_info_1 &
4707 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4711 if (avic_handle_apic_id_update(&svm->vcpu))
4715 if (avic_handle_ldr_update(&svm->vcpu))
4719 avic_handle_dfr_update(&svm->vcpu);
4725 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4730 static bool is_avic_unaccelerated_access_trap(u32 offset)
4759 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4762 u32 offset = svm->vmcb->control.exit_info_1 &
4763 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4764 u32 vector = svm->vmcb->control.exit_info_2 &
4765 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4766 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4767 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4768 bool trap = is_avic_unaccelerated_access_trap(offset);
4770 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4771 trap, write, vector);
4774 WARN_ONCE(!write, "svm: Handling trap read.\n");
4775 ret = avic_unaccel_trap_write(svm);
4777 /* Handling Fault */
4778 ret = kvm_emulate_instruction(&svm->vcpu, 0);
4784 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4785 [SVM_EXIT_READ_CR0] = cr_interception,
4786 [SVM_EXIT_READ_CR3] = cr_interception,
4787 [SVM_EXIT_READ_CR4] = cr_interception,
4788 [SVM_EXIT_READ_CR8] = cr_interception,
4789 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4790 [SVM_EXIT_WRITE_CR0] = cr_interception,
4791 [SVM_EXIT_WRITE_CR3] = cr_interception,
4792 [SVM_EXIT_WRITE_CR4] = cr_interception,
4793 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4794 [SVM_EXIT_READ_DR0] = dr_interception,
4795 [SVM_EXIT_READ_DR1] = dr_interception,
4796 [SVM_EXIT_READ_DR2] = dr_interception,
4797 [SVM_EXIT_READ_DR3] = dr_interception,
4798 [SVM_EXIT_READ_DR4] = dr_interception,
4799 [SVM_EXIT_READ_DR5] = dr_interception,
4800 [SVM_EXIT_READ_DR6] = dr_interception,
4801 [SVM_EXIT_READ_DR7] = dr_interception,
4802 [SVM_EXIT_WRITE_DR0] = dr_interception,
4803 [SVM_EXIT_WRITE_DR1] = dr_interception,
4804 [SVM_EXIT_WRITE_DR2] = dr_interception,
4805 [SVM_EXIT_WRITE_DR3] = dr_interception,
4806 [SVM_EXIT_WRITE_DR4] = dr_interception,
4807 [SVM_EXIT_WRITE_DR5] = dr_interception,
4808 [SVM_EXIT_WRITE_DR6] = dr_interception,
4809 [SVM_EXIT_WRITE_DR7] = dr_interception,
4810 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4811 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4812 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4813 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4814 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4815 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4816 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4817 [SVM_EXIT_INTR] = intr_interception,
4818 [SVM_EXIT_NMI] = nmi_interception,
4819 [SVM_EXIT_SMI] = nop_on_interception,
4820 [SVM_EXIT_INIT] = nop_on_interception,
4821 [SVM_EXIT_VINTR] = interrupt_window_interception,
4822 [SVM_EXIT_RDPMC] = rdpmc_interception,
4823 [SVM_EXIT_CPUID] = cpuid_interception,
4824 [SVM_EXIT_IRET] = iret_interception,
4825 [SVM_EXIT_INVD] = emulate_on_interception,
4826 [SVM_EXIT_PAUSE] = pause_interception,
4827 [SVM_EXIT_HLT] = halt_interception,
4828 [SVM_EXIT_INVLPG] = invlpg_interception,
4829 [SVM_EXIT_INVLPGA] = invlpga_interception,
4830 [SVM_EXIT_IOIO] = io_interception,
4831 [SVM_EXIT_MSR] = msr_interception,
4832 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4833 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4834 [SVM_EXIT_VMRUN] = vmrun_interception,
4835 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4836 [SVM_EXIT_VMLOAD] = vmload_interception,
4837 [SVM_EXIT_VMSAVE] = vmsave_interception,
4838 [SVM_EXIT_STGI] = stgi_interception,
4839 [SVM_EXIT_CLGI] = clgi_interception,
4840 [SVM_EXIT_SKINIT] = skinit_interception,
4841 [SVM_EXIT_WBINVD] = wbinvd_interception,
4842 [SVM_EXIT_MONITOR] = monitor_interception,
4843 [SVM_EXIT_MWAIT] = mwait_interception,
4844 [SVM_EXIT_XSETBV] = xsetbv_interception,
4845 [SVM_EXIT_RDPRU] = rdpru_interception,
4846 [SVM_EXIT_NPF] = npf_interception,
4847 [SVM_EXIT_RSM] = rsm_interception,
4848 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4849 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4852 static void dump_vmcb(struct kvm_vcpu *vcpu)
4854 struct vcpu_svm *svm = to_svm(vcpu);
4855 struct vmcb_control_area *control = &svm->vmcb->control;
4856 struct vmcb_save_area *save = &svm->vmcb->save;
4858 if (!dump_invalid_vmcb) {
4859 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
4863 pr_err("VMCB Control Area:\n");
4864 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4865 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4866 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4867 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4868 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4869 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4870 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4871 pr_err("%-20s%d\n", "pause filter threshold:",
4872 control->pause_filter_thresh);
4873 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4874 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4875 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4876 pr_err("%-20s%d\n", "asid:", control->asid);
4877 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4878 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4879 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4880 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4881 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4882 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4883 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4884 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4885 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4886 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4887 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4888 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4889 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4890 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4891 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4892 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4893 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4894 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4895 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4896 pr_err("VMCB State Save Area:\n");
4897 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4899 save->es.selector, save->es.attrib,
4900 save->es.limit, save->es.base);
4901 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4903 save->cs.selector, save->cs.attrib,
4904 save->cs.limit, save->cs.base);
4905 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4907 save->ss.selector, save->ss.attrib,
4908 save->ss.limit, save->ss.base);
4909 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4911 save->ds.selector, save->ds.attrib,
4912 save->ds.limit, save->ds.base);
4913 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4915 save->fs.selector, save->fs.attrib,
4916 save->fs.limit, save->fs.base);
4917 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4919 save->gs.selector, save->gs.attrib,
4920 save->gs.limit, save->gs.base);
4921 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4923 save->gdtr.selector, save->gdtr.attrib,
4924 save->gdtr.limit, save->gdtr.base);
4925 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4927 save->ldtr.selector, save->ldtr.attrib,
4928 save->ldtr.limit, save->ldtr.base);
4929 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4931 save->idtr.selector, save->idtr.attrib,
4932 save->idtr.limit, save->idtr.base);
4933 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4935 save->tr.selector, save->tr.attrib,
4936 save->tr.limit, save->tr.base);
4937 pr_err("cpl: %d efer: %016llx\n",
4938 save->cpl, save->efer);
4939 pr_err("%-15s %016llx %-13s %016llx\n",
4940 "cr0:", save->cr0, "cr2:", save->cr2);
4941 pr_err("%-15s %016llx %-13s %016llx\n",
4942 "cr3:", save->cr3, "cr4:", save->cr4);
4943 pr_err("%-15s %016llx %-13s %016llx\n",
4944 "dr6:", save->dr6, "dr7:", save->dr7);
4945 pr_err("%-15s %016llx %-13s %016llx\n",
4946 "rip:", save->rip, "rflags:", save->rflags);
4947 pr_err("%-15s %016llx %-13s %016llx\n",
4948 "rsp:", save->rsp, "rax:", save->rax);
4949 pr_err("%-15s %016llx %-13s %016llx\n",
4950 "star:", save->star, "lstar:", save->lstar);
4951 pr_err("%-15s %016llx %-13s %016llx\n",
4952 "cstar:", save->cstar, "sfmask:", save->sfmask);
4953 pr_err("%-15s %016llx %-13s %016llx\n",
4954 "kernel_gs_base:", save->kernel_gs_base,
4955 "sysenter_cs:", save->sysenter_cs);
4956 pr_err("%-15s %016llx %-13s %016llx\n",
4957 "sysenter_esp:", save->sysenter_esp,
4958 "sysenter_eip:", save->sysenter_eip);
4959 pr_err("%-15s %016llx %-13s %016llx\n",
4960 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4961 pr_err("%-15s %016llx %-13s %016llx\n",
4962 "br_from:", save->br_from, "br_to:", save->br_to);
4963 pr_err("%-15s %016llx %-13s %016llx\n",
4964 "excp_from:", save->last_excp_from,
4965 "excp_to:", save->last_excp_to);
4968 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4970 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4972 *info1 = control->exit_info_1;
4973 *info2 = control->exit_info_2;
4976 static int handle_exit(struct kvm_vcpu *vcpu,
4977 enum exit_fastpath_completion exit_fastpath)
4979 struct vcpu_svm *svm = to_svm(vcpu);
4980 struct kvm_run *kvm_run = vcpu->run;
4981 u32 exit_code = svm->vmcb->control.exit_code;
4983 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4985 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4986 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4988 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4990 if (unlikely(svm->nested.exit_required)) {
4991 nested_svm_vmexit(svm);
4992 svm->nested.exit_required = false;
4997 if (is_guest_mode(vcpu)) {
5000 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
5001 svm->vmcb->control.exit_info_1,
5002 svm->vmcb->control.exit_info_2,
5003 svm->vmcb->control.exit_int_info,
5004 svm->vmcb->control.exit_int_info_err,
5007 vmexit = nested_svm_exit_special(svm);
5009 if (vmexit == NESTED_EXIT_CONTINUE)
5010 vmexit = nested_svm_exit_handled(svm);
5012 if (vmexit == NESTED_EXIT_DONE)
5016 svm_complete_interrupts(svm);
5018 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
5019 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5020 kvm_run->fail_entry.hardware_entry_failure_reason
5021 = svm->vmcb->control.exit_code;
5026 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
5027 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
5028 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
5029 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
5030 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
5032 __func__, svm->vmcb->control.exit_int_info,
5035 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
5036 kvm_skip_emulated_instruction(vcpu);
5038 } else if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5039 || !svm_exit_handlers[exit_code]) {
5040 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
5042 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5043 vcpu->run->internal.suberror =
5044 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5045 vcpu->run->internal.ndata = 1;
5046 vcpu->run->internal.data[0] = exit_code;
5050 #ifdef CONFIG_RETPOLINE
5051 if (exit_code == SVM_EXIT_MSR)
5052 return msr_interception(svm);
5053 else if (exit_code == SVM_EXIT_VINTR)
5054 return interrupt_window_interception(svm);
5055 else if (exit_code == SVM_EXIT_INTR)
5056 return intr_interception(svm);
5057 else if (exit_code == SVM_EXIT_HLT)
5058 return halt_interception(svm);
5059 else if (exit_code == SVM_EXIT_NPF)
5060 return npf_interception(svm);
5062 return svm_exit_handlers[exit_code](svm);
5065 static void reload_tss(struct kvm_vcpu *vcpu)
5067 int cpu = raw_smp_processor_id();
5069 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5070 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5074 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5076 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5077 int asid = sev_get_asid(svm->vcpu.kvm);
5079 /* Assign the asid allocated with this SEV guest */
5080 svm->vmcb->control.asid = asid;
5085 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5086 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5088 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5089 svm->last_cpu == cpu)
5092 svm->last_cpu = cpu;
5093 sd->sev_vmcbs[asid] = svm->vmcb;
5094 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5095 mark_dirty(svm->vmcb, VMCB_ASID);
5098 static void pre_svm_run(struct vcpu_svm *svm)
5100 int cpu = raw_smp_processor_id();
5102 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5104 if (sev_guest(svm->vcpu.kvm))
5105 return pre_sev_run(svm, cpu);
5107 /* FIXME: handle wraparound of asid_generation */
5108 if (svm->asid_generation != sd->asid_generation)
5112 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5114 struct vcpu_svm *svm = to_svm(vcpu);
5116 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5117 vcpu->arch.hflags |= HF_NMI_MASK;
5118 set_intercept(svm, INTERCEPT_IRET);
5119 ++vcpu->stat.nmi_injections;
5122 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5124 struct vmcb_control_area *control;
5126 /* The following fields are ignored when AVIC is enabled */
5127 control = &svm->vmcb->control;
5128 control->int_vector = irq;
5129 control->int_ctl &= ~V_INTR_PRIO_MASK;
5130 control->int_ctl |= V_IRQ_MASK |
5131 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5132 mark_dirty(svm->vmcb, VMCB_INTR);
5135 static void svm_set_irq(struct kvm_vcpu *vcpu)
5137 struct vcpu_svm *svm = to_svm(vcpu);
5139 BUG_ON(!(gif_set(svm)));
5141 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5142 ++vcpu->stat.irq_injections;
5144 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5145 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5148 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5150 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5153 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5155 struct vcpu_svm *svm = to_svm(vcpu);
5157 if (svm_nested_virtualize_tpr(vcpu))
5160 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5166 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5169 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5174 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5178 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5182 static void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate)
5184 if (!avic || !lapic_in_kernel(vcpu))
5187 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5188 kvm_request_apicv_update(vcpu->kvm, activate,
5189 APICV_INHIBIT_REASON_IRQWIN);
5190 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5193 static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
5196 unsigned long flags;
5197 struct amd_svm_iommu_ir *ir;
5198 struct vcpu_svm *svm = to_svm(vcpu);
5200 if (!kvm_arch_has_assigned_device(vcpu->kvm))
5204 * Here, we go through the per-vcpu ir_list to update all existing
5205 * interrupt remapping table entry targeting this vcpu.
5207 spin_lock_irqsave(&svm->ir_list_lock, flags);
5209 if (list_empty(&svm->ir_list))
5212 list_for_each_entry(ir, &svm->ir_list, node) {
5214 ret = amd_iommu_activate_guest_mode(ir->data);
5216 ret = amd_iommu_deactivate_guest_mode(ir->data);
5221 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5225 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5227 struct vcpu_svm *svm = to_svm(vcpu);
5228 struct vmcb *vmcb = svm->vmcb;
5229 bool activated = kvm_vcpu_apicv_active(vcpu);
5233 * During AVIC temporary deactivation, guest could update
5234 * APIC ID, DFR and LDR registers, which would not be trapped
5235 * by avic_unaccelerated_access_interception(). In this case,
5236 * we need to check and update the AVIC logical APIC ID table
5237 * accordingly before re-activating.
5239 avic_post_state_restore(vcpu);
5240 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5242 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5244 mark_dirty(vmcb, VMCB_AVIC);
5246 svm_set_pi_irte_mode(vcpu, activated);
5249 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5254 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5256 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5257 smp_mb__after_atomic();
5259 if (avic_vcpu_is_running(vcpu)) {
5260 int cpuid = vcpu->cpu;
5262 if (cpuid != get_cpu())
5263 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
5266 kvm_vcpu_wake_up(vcpu);
5269 static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
5274 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5276 unsigned long flags;
5277 struct amd_svm_iommu_ir *cur;
5279 spin_lock_irqsave(&svm->ir_list_lock, flags);
5280 list_for_each_entry(cur, &svm->ir_list, node) {
5281 if (cur->data != pi->ir_data)
5283 list_del(&cur->node);
5287 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5290 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5293 unsigned long flags;
5294 struct amd_svm_iommu_ir *ir;
5297 * In some cases, the existing irte is updaed and re-set,
5298 * so we need to check here if it's already been * added
5301 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5302 struct kvm *kvm = svm->vcpu.kvm;
5303 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5304 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5305 struct vcpu_svm *prev_svm;
5312 prev_svm = to_svm(prev_vcpu);
5313 svm_ir_list_del(prev_svm, pi);
5317 * Allocating new amd_iommu_pi_data, which will get
5318 * add to the per-vcpu ir_list.
5320 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5325 ir->data = pi->ir_data;
5327 spin_lock_irqsave(&svm->ir_list_lock, flags);
5328 list_add(&ir->node, &svm->ir_list);
5329 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5336 * The HW cannot support posting multicast/broadcast
5337 * interrupts to a vCPU. So, we still use legacy interrupt
5338 * remapping for these kind of interrupts.
5340 * For lowest-priority interrupts, we only support
5341 * those with single CPU as the destination, e.g. user
5342 * configures the interrupts via /proc/irq or uses
5343 * irqbalance to make the interrupts single-CPU.
5346 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5347 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5349 struct kvm_lapic_irq irq;
5350 struct kvm_vcpu *vcpu = NULL;
5352 kvm_set_msi_irq(kvm, e, &irq);
5354 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
5355 !kvm_irq_is_postable(&irq)) {
5356 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5357 __func__, irq.vector);
5361 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5363 *svm = to_svm(vcpu);
5364 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5365 vcpu_info->vector = irq.vector;
5371 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5374 * @host_irq: host irq of the interrupt
5375 * @guest_irq: gsi of the interrupt
5376 * @set: set or unset PI
5377 * returns 0 on success, < 0 on failure
5379 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5380 uint32_t guest_irq, bool set)
5382 struct kvm_kernel_irq_routing_entry *e;
5383 struct kvm_irq_routing_table *irq_rt;
5384 int idx, ret = -EINVAL;
5386 if (!kvm_arch_has_assigned_device(kvm) ||
5387 !irq_remapping_cap(IRQ_POSTING_CAP))
5390 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5391 __func__, host_irq, guest_irq, set);
5393 idx = srcu_read_lock(&kvm->irq_srcu);
5394 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5395 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5397 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5398 struct vcpu_data vcpu_info;
5399 struct vcpu_svm *svm = NULL;
5401 if (e->type != KVM_IRQ_ROUTING_MSI)
5405 * Here, we setup with legacy mode in the following cases:
5406 * 1. When cannot target interrupt to a specific vcpu.
5407 * 2. Unsetting posted interrupt.
5408 * 3. APIC virtialization is disabled for the vcpu.
5409 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
5411 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5412 kvm_vcpu_apicv_active(&svm->vcpu)) {
5413 struct amd_iommu_pi_data pi;
5415 /* Try to enable guest_mode in IRTE */
5416 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5418 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5420 pi.is_guest_mode = true;
5421 pi.vcpu_data = &vcpu_info;
5422 ret = irq_set_vcpu_affinity(host_irq, &pi);
5425 * Here, we successfully setting up vcpu affinity in
5426 * IOMMU guest mode. Now, we need to store the posted
5427 * interrupt information in a per-vcpu ir_list so that
5428 * we can reference to them directly when we update vcpu
5429 * scheduling information in IOMMU irte.
5431 if (!ret && pi.is_guest_mode)
5432 svm_ir_list_add(svm, &pi);
5434 /* Use legacy mode in IRTE */
5435 struct amd_iommu_pi_data pi;
5438 * Here, pi is used to:
5439 * - Tell IOMMU to use legacy mode for this interrupt.
5440 * - Retrieve ga_tag of prior interrupt remapping data.
5442 pi.is_guest_mode = false;
5443 ret = irq_set_vcpu_affinity(host_irq, &pi);
5446 * Check if the posted interrupt was previously
5447 * setup with the guest_mode by checking if the ga_tag
5448 * was cached. If so, we need to clean up the per-vcpu
5451 if (!ret && pi.prev_ga_tag) {
5452 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5453 struct kvm_vcpu *vcpu;
5455 vcpu = kvm_get_vcpu_by_id(kvm, id);
5457 svm_ir_list_del(to_svm(vcpu), &pi);
5462 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5463 e->gsi, vcpu_info.vector,
5464 vcpu_info.pi_desc_addr, set);
5468 pr_err("%s: failed to update PI IRTE\n", __func__);
5475 srcu_read_unlock(&kvm->irq_srcu, idx);
5479 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5481 struct vcpu_svm *svm = to_svm(vcpu);
5482 struct vmcb *vmcb = svm->vmcb;
5484 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5485 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5486 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5491 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5493 struct vcpu_svm *svm = to_svm(vcpu);
5495 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5498 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5500 struct vcpu_svm *svm = to_svm(vcpu);
5503 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5504 set_intercept(svm, INTERCEPT_IRET);
5506 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5507 clr_intercept(svm, INTERCEPT_IRET);
5511 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5513 struct vcpu_svm *svm = to_svm(vcpu);
5514 struct vmcb *vmcb = svm->vmcb;
5517 if (!gif_set(svm) ||
5518 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5521 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5523 if (is_guest_mode(vcpu))
5524 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5529 static void enable_irq_window(struct kvm_vcpu *vcpu)
5531 struct vcpu_svm *svm = to_svm(vcpu);
5534 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5535 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5536 * get that intercept, this function will be called again though and
5537 * we'll get the vintr intercept. However, if the vGIF feature is
5538 * enabled, the STGI interception will not occur. Enable the irq
5539 * window under the assumption that the hardware will set the GIF.
5541 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5543 * IRQ window is not needed when AVIC is enabled,
5544 * unless we have pending ExtINT since it cannot be injected
5545 * via AVIC. In such case, we need to temporarily disable AVIC,
5546 * and fallback to injecting IRQ via V_IRQ.
5548 svm_toggle_avic_for_irq_window(vcpu, false);
5550 svm_inject_irq(svm, 0x0);
5554 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5556 struct vcpu_svm *svm = to_svm(vcpu);
5558 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5560 return; /* IRET will cause a vm exit */
5562 if (!gif_set(svm)) {
5563 if (vgif_enabled(svm))
5564 set_intercept(svm, INTERCEPT_STGI);
5565 return; /* STGI will cause a vm exit */
5568 if (svm->nested.exit_required)
5569 return; /* we're not going to run the guest yet */
5572 * Something prevents NMI from been injected. Single step over possible
5573 * problem (IRET or exception injection or interrupt shadow)
5575 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5576 svm->nmi_singlestep = true;
5577 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5580 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5585 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5590 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5592 struct vcpu_svm *svm = to_svm(vcpu);
5594 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5595 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5597 svm->asid_generation--;
5600 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5602 struct vcpu_svm *svm = to_svm(vcpu);
5604 invlpga(gva, svm->vmcb->control.asid);
5607 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5611 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5613 struct vcpu_svm *svm = to_svm(vcpu);
5615 if (svm_nested_virtualize_tpr(vcpu))
5618 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5619 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5620 kvm_set_cr8(vcpu, cr8);
5624 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5626 struct vcpu_svm *svm = to_svm(vcpu);
5629 if (svm_nested_virtualize_tpr(vcpu) ||
5630 kvm_vcpu_apicv_active(vcpu))
5633 cr8 = kvm_get_cr8(vcpu);
5634 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5635 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5638 static void svm_complete_interrupts(struct vcpu_svm *svm)
5642 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5643 unsigned int3_injected = svm->int3_injected;
5645 svm->int3_injected = 0;
5648 * If we've made progress since setting HF_IRET_MASK, we've
5649 * executed an IRET and can allow NMI injection.
5651 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5652 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5653 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5654 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5657 svm->vcpu.arch.nmi_injected = false;
5658 kvm_clear_exception_queue(&svm->vcpu);
5659 kvm_clear_interrupt_queue(&svm->vcpu);
5661 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5664 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5666 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5667 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5670 case SVM_EXITINTINFO_TYPE_NMI:
5671 svm->vcpu.arch.nmi_injected = true;
5673 case SVM_EXITINTINFO_TYPE_EXEPT:
5675 * In case of software exceptions, do not reinject the vector,
5676 * but re-execute the instruction instead. Rewind RIP first
5677 * if we emulated INT3 before.
5679 if (kvm_exception_is_soft(vector)) {
5680 if (vector == BP_VECTOR && int3_injected &&
5681 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5682 kvm_rip_write(&svm->vcpu,
5683 kvm_rip_read(&svm->vcpu) -
5687 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5688 u32 err = svm->vmcb->control.exit_int_info_err;
5689 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5692 kvm_requeue_exception(&svm->vcpu, vector);
5694 case SVM_EXITINTINFO_TYPE_INTR:
5695 kvm_queue_interrupt(&svm->vcpu, vector, false);
5702 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5704 struct vcpu_svm *svm = to_svm(vcpu);
5705 struct vmcb_control_area *control = &svm->vmcb->control;
5707 control->exit_int_info = control->event_inj;
5708 control->exit_int_info_err = control->event_inj_err;
5709 control->event_inj = 0;
5710 svm_complete_interrupts(svm);
5713 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5715 struct vcpu_svm *svm = to_svm(vcpu);
5717 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5718 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5719 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5722 * A vmexit emulation is required before the vcpu can be executed
5725 if (unlikely(svm->nested.exit_required))
5729 * Disable singlestep if we're injecting an interrupt/exception.
5730 * We don't want our modified rflags to be pushed on the stack where
5731 * we might not be able to easily reset them if we disabled NMI
5734 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5736 * Event injection happens before external interrupts cause a
5737 * vmexit and interrupts are disabled here, so smp_send_reschedule
5738 * is enough to force an immediate vmexit.
5740 disable_nmi_singlestep(svm);
5741 smp_send_reschedule(vcpu->cpu);
5746 sync_lapic_to_cr8(vcpu);
5748 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5751 kvm_load_guest_xsave_state(vcpu);
5753 if (lapic_in_kernel(vcpu) &&
5754 vcpu->arch.apic->lapic_timer.timer_advance_ns)
5755 kvm_wait_lapic_expire(vcpu);
5758 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5759 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5760 * is no need to worry about the conditional branch over the wrmsr
5761 * being speculatively taken.
5763 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5768 "push %%" _ASM_BP "; \n\t"
5769 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5770 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5771 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5772 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5773 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5774 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5775 #ifdef CONFIG_X86_64
5776 "mov %c[r8](%[svm]), %%r8 \n\t"
5777 "mov %c[r9](%[svm]), %%r9 \n\t"
5778 "mov %c[r10](%[svm]), %%r10 \n\t"
5779 "mov %c[r11](%[svm]), %%r11 \n\t"
5780 "mov %c[r12](%[svm]), %%r12 \n\t"
5781 "mov %c[r13](%[svm]), %%r13 \n\t"
5782 "mov %c[r14](%[svm]), %%r14 \n\t"
5783 "mov %c[r15](%[svm]), %%r15 \n\t"
5786 /* Enter guest mode */
5787 "push %%" _ASM_AX " \n\t"
5788 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5789 __ex("vmload %%" _ASM_AX) "\n\t"
5790 __ex("vmrun %%" _ASM_AX) "\n\t"
5791 __ex("vmsave %%" _ASM_AX) "\n\t"
5792 "pop %%" _ASM_AX " \n\t"
5794 /* Save guest registers, load host registers */
5795 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5796 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5797 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5798 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5799 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5800 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5801 #ifdef CONFIG_X86_64
5802 "mov %%r8, %c[r8](%[svm]) \n\t"
5803 "mov %%r9, %c[r9](%[svm]) \n\t"
5804 "mov %%r10, %c[r10](%[svm]) \n\t"
5805 "mov %%r11, %c[r11](%[svm]) \n\t"
5806 "mov %%r12, %c[r12](%[svm]) \n\t"
5807 "mov %%r13, %c[r13](%[svm]) \n\t"
5808 "mov %%r14, %c[r14](%[svm]) \n\t"
5809 "mov %%r15, %c[r15](%[svm]) \n\t"
5811 * Clear host registers marked as clobbered to prevent
5814 "xor %%r8d, %%r8d \n\t"
5815 "xor %%r9d, %%r9d \n\t"
5816 "xor %%r10d, %%r10d \n\t"
5817 "xor %%r11d, %%r11d \n\t"
5818 "xor %%r12d, %%r12d \n\t"
5819 "xor %%r13d, %%r13d \n\t"
5820 "xor %%r14d, %%r14d \n\t"
5821 "xor %%r15d, %%r15d \n\t"
5823 "xor %%ebx, %%ebx \n\t"
5824 "xor %%ecx, %%ecx \n\t"
5825 "xor %%edx, %%edx \n\t"
5826 "xor %%esi, %%esi \n\t"
5827 "xor %%edi, %%edi \n\t"
5831 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5832 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5833 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5834 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5835 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5836 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5837 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5838 #ifdef CONFIG_X86_64
5839 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5840 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5841 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5842 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5843 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5844 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5845 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5846 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5849 #ifdef CONFIG_X86_64
5850 , "rbx", "rcx", "rdx", "rsi", "rdi"
5851 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5853 , "ebx", "ecx", "edx", "esi", "edi"
5857 /* Eliminate branch target predictions from guest mode */
5860 #ifdef CONFIG_X86_64
5861 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5863 loadsegment(fs, svm->host.fs);
5864 #ifndef CONFIG_X86_32_LAZY_GS
5865 loadsegment(gs, svm->host.gs);
5870 * We do not use IBRS in the kernel. If this vCPU has used the
5871 * SPEC_CTRL MSR it may have left it on; save the value and
5872 * turn it off. This is much more efficient than blindly adding
5873 * it to the atomic save/restore list. Especially as the former
5874 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5876 * For non-nested case:
5877 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5881 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5884 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5885 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5889 local_irq_disable();
5891 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5893 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5894 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5895 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5896 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5898 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5899 kvm_before_interrupt(&svm->vcpu);
5901 kvm_load_host_xsave_state(vcpu);
5904 /* Any pending NMI will happen here */
5906 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5907 kvm_after_interrupt(&svm->vcpu);
5909 sync_cr8_to_lapic(vcpu);
5913 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5915 /* if exit due to PF check for async PF */
5916 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5917 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5920 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5921 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5925 * We need to handle MC intercepts here before the vcpu has a chance to
5926 * change the physical cpu
5928 if (unlikely(svm->vmcb->control.exit_code ==
5929 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5930 svm_handle_mce(svm);
5932 mark_all_clean(svm->vmcb);
5934 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5936 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5938 struct vcpu_svm *svm = to_svm(vcpu);
5940 svm->vmcb->save.cr3 = __sme_set(root);
5941 mark_dirty(svm->vmcb, VMCB_CR);
5944 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5946 struct vcpu_svm *svm = to_svm(vcpu);
5948 svm->vmcb->control.nested_cr3 = __sme_set(root);
5949 mark_dirty(svm->vmcb, VMCB_NPT);
5951 /* Also sync guest cr3 here in case we live migrate */
5952 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5953 mark_dirty(svm->vmcb, VMCB_CR);
5956 static int is_disabled(void)
5960 rdmsrl(MSR_VM_CR, vm_cr);
5961 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5968 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5971 * Patch in the VMMCALL instruction:
5973 hypercall[0] = 0x0f;
5974 hypercall[1] = 0x01;
5975 hypercall[2] = 0xd9;
5978 static int __init svm_check_processor_compat(void)
5983 static bool svm_cpu_has_accelerated_tpr(void)
5988 static bool svm_has_emulated_msr(int index)
5991 case MSR_IA32_MCG_EXT_CTL:
5992 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6001 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6006 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
6008 struct vcpu_svm *svm = to_svm(vcpu);
6010 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6011 boot_cpu_has(X86_FEATURE_XSAVE) &&
6012 boot_cpu_has(X86_FEATURE_XSAVES);
6014 /* Update nrips enabled cache */
6015 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
6017 if (!kvm_vcpu_apicv_active(vcpu))
6020 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
6023 * Currently, AVIC does not work with nested virtualization.
6024 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
6026 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
6027 kvm_request_apicv_update(vcpu->kvm, false,
6028 APICV_INHIBIT_REASON_NESTED);
6031 #define F feature_bit
6033 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6038 entry->ecx &= ~F(X2APIC);
6042 entry->ecx |= (1 << 2); /* Set SVM bit */
6045 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
6046 boot_cpu_has(X86_FEATURE_AMD_SSBD))
6047 entry->ebx |= F(VIRT_SSBD);
6050 entry->eax = 1; /* SVM revision 1 */
6051 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
6052 ASID emulation to nested SVM */
6053 entry->ecx = 0; /* Reserved */
6054 entry->edx = 0; /* Per default do not support any
6055 additional features */
6057 /* Support next_rip if host supports it */
6058 if (boot_cpu_has(X86_FEATURE_NRIPS))
6059 entry->edx |= F(NRIPS);
6061 /* Support NPT for the guest if enabled */
6063 entry->edx |= F(NPT);
6068 static int svm_get_lpage_level(void)
6070 return PT_PDPE_LEVEL;
6073 static bool svm_rdtscp_supported(void)
6075 return boot_cpu_has(X86_FEATURE_RDTSCP);
6078 static bool svm_invpcid_supported(void)
6083 static bool svm_mpx_supported(void)
6088 static bool svm_xsaves_supported(void)
6090 return boot_cpu_has(X86_FEATURE_XSAVES);
6093 static bool svm_umip_emulated(void)
6098 static bool svm_pt_supported(void)
6103 static bool svm_has_wbinvd_exit(void)
6108 static bool svm_pku_supported(void)
6113 #define PRE_EX(exit) { .exit_code = (exit), \
6114 .stage = X86_ICPT_PRE_EXCEPT, }
6115 #define POST_EX(exit) { .exit_code = (exit), \
6116 .stage = X86_ICPT_POST_EXCEPT, }
6117 #define POST_MEM(exit) { .exit_code = (exit), \
6118 .stage = X86_ICPT_POST_MEMACCESS, }
6120 static const struct __x86_intercept {
6122 enum x86_intercept_stage stage;
6123 } x86_intercept_map[] = {
6124 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
6125 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
6126 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
6127 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
6128 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
6129 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
6130 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
6131 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
6132 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
6133 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
6134 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
6135 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
6136 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
6137 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
6138 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
6139 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6140 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6141 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6142 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6143 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6144 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6145 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6146 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6147 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6148 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6149 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6150 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6151 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6152 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6153 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6154 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6155 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6156 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6157 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6158 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6159 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6160 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6161 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6162 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6163 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6164 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6165 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6166 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6167 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6168 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6169 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6170 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
6177 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6178 struct x86_instruction_info *info,
6179 enum x86_intercept_stage stage)
6181 struct vcpu_svm *svm = to_svm(vcpu);
6182 int vmexit, ret = X86EMUL_CONTINUE;
6183 struct __x86_intercept icpt_info;
6184 struct vmcb *vmcb = svm->vmcb;
6186 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6189 icpt_info = x86_intercept_map[info->intercept];
6191 if (stage != icpt_info.stage)
6194 switch (icpt_info.exit_code) {
6195 case SVM_EXIT_READ_CR0:
6196 if (info->intercept == x86_intercept_cr_read)
6197 icpt_info.exit_code += info->modrm_reg;
6199 case SVM_EXIT_WRITE_CR0: {
6200 unsigned long cr0, val;
6203 if (info->intercept == x86_intercept_cr_write)
6204 icpt_info.exit_code += info->modrm_reg;
6206 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6207 info->intercept == x86_intercept_clts)
6210 intercept = svm->nested.intercept;
6212 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6215 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6216 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6218 if (info->intercept == x86_intercept_lmsw) {
6221 /* lmsw can't clear PE - catch this here */
6222 if (cr0 & X86_CR0_PE)
6227 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6231 case SVM_EXIT_READ_DR0:
6232 case SVM_EXIT_WRITE_DR0:
6233 icpt_info.exit_code += info->modrm_reg;
6236 if (info->intercept == x86_intercept_wrmsr)
6237 vmcb->control.exit_info_1 = 1;
6239 vmcb->control.exit_info_1 = 0;
6241 case SVM_EXIT_PAUSE:
6243 * We get this for NOP only, but pause
6244 * is rep not, check this here
6246 if (info->rep_prefix != REPE_PREFIX)
6249 case SVM_EXIT_IOIO: {
6253 if (info->intercept == x86_intercept_in ||
6254 info->intercept == x86_intercept_ins) {
6255 exit_info = ((info->src_val & 0xffff) << 16) |
6257 bytes = info->dst_bytes;
6259 exit_info = (info->dst_val & 0xffff) << 16;
6260 bytes = info->src_bytes;
6263 if (info->intercept == x86_intercept_outs ||
6264 info->intercept == x86_intercept_ins)
6265 exit_info |= SVM_IOIO_STR_MASK;
6267 if (info->rep_prefix)
6268 exit_info |= SVM_IOIO_REP_MASK;
6270 bytes = min(bytes, 4u);
6272 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6274 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6276 vmcb->control.exit_info_1 = exit_info;
6277 vmcb->control.exit_info_2 = info->next_rip;
6285 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6286 if (static_cpu_has(X86_FEATURE_NRIPS))
6287 vmcb->control.next_rip = info->next_rip;
6288 vmcb->control.exit_code = icpt_info.exit_code;
6289 vmexit = nested_svm_exit_handled(svm);
6291 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6298 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu,
6299 enum exit_fastpath_completion *exit_fastpath)
6301 if (!is_guest_mode(vcpu) &&
6302 to_svm(vcpu)->vmcb->control.exit_code == EXIT_REASON_MSR_WRITE)
6303 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu);
6306 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6308 if (pause_filter_thresh)
6309 shrink_ple_window(vcpu);
6312 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6314 if (avic_handle_apic_id_update(vcpu) != 0)
6316 avic_handle_dfr_update(vcpu);
6317 avic_handle_ldr_update(vcpu);
6320 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6322 /* [63:9] are reserved. */
6323 vcpu->arch.mcg_cap &= 0x1ff;
6326 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6328 struct vcpu_svm *svm = to_svm(vcpu);
6330 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6334 if (is_guest_mode(&svm->vcpu) &&
6335 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6336 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6337 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6338 svm->nested.exit_required = true;
6345 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6347 struct vcpu_svm *svm = to_svm(vcpu);
6350 if (is_guest_mode(vcpu)) {
6351 /* FED8h - SVM Guest */
6352 put_smstate(u64, smstate, 0x7ed8, 1);
6353 /* FEE0h - SVM Guest VMCB Physical Address */
6354 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6356 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6357 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6358 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6360 ret = nested_svm_vmexit(svm);
6367 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6369 struct vcpu_svm *svm = to_svm(vcpu);
6370 struct vmcb *nested_vmcb;
6371 struct kvm_host_map map;
6375 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6376 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6379 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6381 nested_vmcb = map.hva;
6382 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6387 static int enable_smi_window(struct kvm_vcpu *vcpu)
6389 struct vcpu_svm *svm = to_svm(vcpu);
6391 if (!gif_set(svm)) {
6392 if (vgif_enabled(svm))
6393 set_intercept(svm, INTERCEPT_STGI);
6394 /* STGI will cause a vm exit */
6400 static int sev_flush_asids(void)
6405 * DEACTIVATE will clear the WBINVD indicator causing DF_FLUSH to fail,
6406 * so it must be guarded.
6408 down_write(&sev_deactivate_lock);
6410 wbinvd_on_all_cpus();
6411 ret = sev_guest_df_flush(&error);
6413 up_write(&sev_deactivate_lock);
6416 pr_err("SEV: DF_FLUSH failed, ret=%d, error=%#x\n", ret, error);
6421 /* Must be called with the sev_bitmap_lock held */
6422 static bool __sev_recycle_asids(void)
6426 /* Check if there are any ASIDs to reclaim before performing a flush */
6427 pos = find_next_bit(sev_reclaim_asid_bitmap,
6428 max_sev_asid, min_sev_asid - 1);
6429 if (pos >= max_sev_asid)
6432 if (sev_flush_asids())
6435 bitmap_xor(sev_asid_bitmap, sev_asid_bitmap, sev_reclaim_asid_bitmap,
6437 bitmap_zero(sev_reclaim_asid_bitmap, max_sev_asid);
6442 static int sev_asid_new(void)
6447 mutex_lock(&sev_bitmap_lock);
6450 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6453 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6454 if (pos >= max_sev_asid) {
6455 if (retry && __sev_recycle_asids()) {
6459 mutex_unlock(&sev_bitmap_lock);
6463 __set_bit(pos, sev_asid_bitmap);
6465 mutex_unlock(&sev_bitmap_lock);
6470 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6472 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6476 if (unlikely(sev->active))
6479 asid = sev_asid_new();
6483 ret = sev_platform_init(&argp->error);
6489 INIT_LIST_HEAD(&sev->regions_list);
6494 sev_asid_free(asid);
6498 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6500 struct sev_data_activate *data;
6501 int asid = sev_get_asid(kvm);
6504 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6508 /* activate ASID on the given handle */
6509 data->handle = handle;
6511 ret = sev_guest_activate(data, error);
6517 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6526 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6532 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6534 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6536 return __sev_issue_cmd(sev->fd, id, data, error);
6539 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6541 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6542 struct sev_data_launch_start *start;
6543 struct kvm_sev_launch_start params;
6544 void *dh_blob, *session_blob;
6545 int *error = &argp->error;
6548 if (!sev_guest(kvm))
6551 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6554 start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6559 if (params.dh_uaddr) {
6560 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6561 if (IS_ERR(dh_blob)) {
6562 ret = PTR_ERR(dh_blob);
6566 start->dh_cert_address = __sme_set(__pa(dh_blob));
6567 start->dh_cert_len = params.dh_len;
6570 session_blob = NULL;
6571 if (params.session_uaddr) {
6572 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6573 if (IS_ERR(session_blob)) {
6574 ret = PTR_ERR(session_blob);
6578 start->session_address = __sme_set(__pa(session_blob));
6579 start->session_len = params.session_len;
6582 start->handle = params.handle;
6583 start->policy = params.policy;
6585 /* create memory encryption context */
6586 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6588 goto e_free_session;
6590 /* Bind ASID to this guest */
6591 ret = sev_bind_asid(kvm, start->handle, error);
6593 goto e_free_session;
6595 /* return handle to userspace */
6596 params.handle = start->handle;
6597 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6598 sev_unbind_asid(kvm, start->handle);
6600 goto e_free_session;
6603 sev->handle = start->handle;
6604 sev->fd = argp->sev_fd;
6607 kfree(session_blob);
6615 static unsigned long get_num_contig_pages(unsigned long idx,
6616 struct page **inpages, unsigned long npages)
6618 unsigned long paddr, next_paddr;
6619 unsigned long i = idx + 1, pages = 1;
6621 /* find the number of contiguous pages starting from idx */
6622 paddr = __sme_page_pa(inpages[idx]);
6623 while (i < npages) {
6624 next_paddr = __sme_page_pa(inpages[i++]);
6625 if ((paddr + PAGE_SIZE) == next_paddr) {
6636 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6638 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6639 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6640 struct kvm_sev_launch_update_data params;
6641 struct sev_data_launch_update_data *data;
6642 struct page **inpages;
6645 if (!sev_guest(kvm))
6648 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6651 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6655 vaddr = params.uaddr;
6657 vaddr_end = vaddr + size;
6659 /* Lock the user memory. */
6660 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6667 * The LAUNCH_UPDATE command will perform in-place encryption of the
6668 * memory content (i.e it will write the same memory region with C=1).
6669 * It's possible that the cache may contain the data with C=0, i.e.,
6670 * unencrypted so invalidate it first.
6672 sev_clflush_pages(inpages, npages);
6674 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6678 * If the user buffer is not page-aligned, calculate the offset
6681 offset = vaddr & (PAGE_SIZE - 1);
6683 /* Calculate the number of pages that can be encrypted in one go. */
6684 pages = get_num_contig_pages(i, inpages, npages);
6686 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6688 data->handle = sev->handle;
6690 data->address = __sme_page_pa(inpages[i]) + offset;
6691 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6696 next_vaddr = vaddr + len;
6700 /* content of memory is updated, mark pages dirty */
6701 for (i = 0; i < npages; i++) {
6702 set_page_dirty_lock(inpages[i]);
6703 mark_page_accessed(inpages[i]);
6705 /* unlock the user pages */
6706 sev_unpin_memory(kvm, inpages, npages);
6712 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6714 void __user *measure = (void __user *)(uintptr_t)argp->data;
6715 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6716 struct sev_data_launch_measure *data;
6717 struct kvm_sev_launch_measure params;
6718 void __user *p = NULL;
6722 if (!sev_guest(kvm))
6725 if (copy_from_user(¶ms, measure, sizeof(params)))
6728 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6732 /* User wants to query the blob length */
6736 p = (void __user *)(uintptr_t)params.uaddr;
6738 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6744 blob = kmalloc(params.len, GFP_KERNEL);
6748 data->address = __psp_pa(blob);
6749 data->len = params.len;
6753 data->handle = sev->handle;
6754 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6757 * If we query the session length, FW responded with expected data.
6766 if (copy_to_user(p, blob, params.len))
6771 params.len = data->len;
6772 if (copy_to_user(measure, ¶ms, sizeof(params)))
6781 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6783 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6784 struct sev_data_launch_finish *data;
6787 if (!sev_guest(kvm))
6790 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6794 data->handle = sev->handle;
6795 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6801 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6803 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6804 struct kvm_sev_guest_status params;
6805 struct sev_data_guest_status *data;
6808 if (!sev_guest(kvm))
6811 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6815 data->handle = sev->handle;
6816 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6820 params.policy = data->policy;
6821 params.state = data->state;
6822 params.handle = data->handle;
6824 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6831 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6832 unsigned long dst, int size,
6833 int *error, bool enc)
6835 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6836 struct sev_data_dbg *data;
6839 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6843 data->handle = sev->handle;
6844 data->dst_addr = dst;
6845 data->src_addr = src;
6848 ret = sev_issue_cmd(kvm,
6849 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6855 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6856 unsigned long dst_paddr, int sz, int *err)
6861 * Its safe to read more than we are asked, caller should ensure that
6862 * destination has enough space.
6864 src_paddr = round_down(src_paddr, 16);
6865 offset = src_paddr & 15;
6866 sz = round_up(sz + offset, 16);
6868 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6871 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6872 unsigned long __user dst_uaddr,
6873 unsigned long dst_paddr,
6876 struct page *tpage = NULL;
6879 /* if inputs are not 16-byte then use intermediate buffer */
6880 if (!IS_ALIGNED(dst_paddr, 16) ||
6881 !IS_ALIGNED(paddr, 16) ||
6882 !IS_ALIGNED(size, 16)) {
6883 tpage = (void *)alloc_page(GFP_KERNEL);
6887 dst_paddr = __sme_page_pa(tpage);
6890 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6895 offset = paddr & 15;
6896 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6897 page_address(tpage) + offset, size))
6908 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6909 unsigned long __user vaddr,
6910 unsigned long dst_paddr,
6911 unsigned long __user dst_vaddr,
6912 int size, int *error)
6914 struct page *src_tpage = NULL;
6915 struct page *dst_tpage = NULL;
6916 int ret, len = size;
6918 /* If source buffer is not aligned then use an intermediate buffer */
6919 if (!IS_ALIGNED(vaddr, 16)) {
6920 src_tpage = alloc_page(GFP_KERNEL);
6924 if (copy_from_user(page_address(src_tpage),
6925 (void __user *)(uintptr_t)vaddr, size)) {
6926 __free_page(src_tpage);
6930 paddr = __sme_page_pa(src_tpage);
6934 * If destination buffer or length is not aligned then do read-modify-write:
6935 * - decrypt destination in an intermediate buffer
6936 * - copy the source buffer in an intermediate buffer
6937 * - use the intermediate buffer as source buffer
6939 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6942 dst_tpage = alloc_page(GFP_KERNEL);
6948 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6949 __sme_page_pa(dst_tpage), size, error);
6954 * If source is kernel buffer then use memcpy() otherwise
6957 dst_offset = dst_paddr & 15;
6960 memcpy(page_address(dst_tpage) + dst_offset,
6961 page_address(src_tpage), size);
6963 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6964 (void __user *)(uintptr_t)vaddr, size)) {
6970 paddr = __sme_page_pa(dst_tpage);
6971 dst_paddr = round_down(dst_paddr, 16);
6972 len = round_up(size, 16);
6975 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6979 __free_page(src_tpage);
6981 __free_page(dst_tpage);
6985 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6987 unsigned long vaddr, vaddr_end, next_vaddr;
6988 unsigned long dst_vaddr;
6989 struct page **src_p, **dst_p;
6990 struct kvm_sev_dbg debug;
6995 if (!sev_guest(kvm))
6998 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
7001 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
7003 if (!debug.dst_uaddr)
7006 vaddr = debug.src_uaddr;
7008 vaddr_end = vaddr + size;
7009 dst_vaddr = debug.dst_uaddr;
7011 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
7012 int len, s_off, d_off;
7014 /* lock userspace source and destination page */
7015 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
7019 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
7021 sev_unpin_memory(kvm, src_p, n);
7026 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
7027 * memory content (i.e it will write the same memory region with C=1).
7028 * It's possible that the cache may contain the data with C=0, i.e.,
7029 * unencrypted so invalidate it first.
7031 sev_clflush_pages(src_p, 1);
7032 sev_clflush_pages(dst_p, 1);
7035 * Since user buffer may not be page aligned, calculate the
7036 * offset within the page.
7038 s_off = vaddr & ~PAGE_MASK;
7039 d_off = dst_vaddr & ~PAGE_MASK;
7040 len = min_t(size_t, (PAGE_SIZE - s_off), size);
7043 ret = __sev_dbg_decrypt_user(kvm,
7044 __sme_page_pa(src_p[0]) + s_off,
7046 __sme_page_pa(dst_p[0]) + d_off,
7049 ret = __sev_dbg_encrypt_user(kvm,
7050 __sme_page_pa(src_p[0]) + s_off,
7052 __sme_page_pa(dst_p[0]) + d_off,
7056 sev_unpin_memory(kvm, src_p, n);
7057 sev_unpin_memory(kvm, dst_p, n);
7062 next_vaddr = vaddr + len;
7063 dst_vaddr = dst_vaddr + len;
7070 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
7072 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7073 struct sev_data_launch_secret *data;
7074 struct kvm_sev_launch_secret params;
7075 struct page **pages;
7080 if (!sev_guest(kvm))
7083 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
7086 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
7091 * The secret must be copied into contiguous memory region, lets verify
7092 * that userspace memory pages are contiguous before we issue command.
7094 if (get_num_contig_pages(0, pages, n) != n) {
7096 goto e_unpin_memory;
7100 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
7102 goto e_unpin_memory;
7104 offset = params.guest_uaddr & (PAGE_SIZE - 1);
7105 data->guest_address = __sme_page_pa(pages[0]) + offset;
7106 data->guest_len = params.guest_len;
7108 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
7110 ret = PTR_ERR(blob);
7114 data->trans_address = __psp_pa(blob);
7115 data->trans_len = params.trans_len;
7117 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
7122 data->hdr_address = __psp_pa(hdr);
7123 data->hdr_len = params.hdr_len;
7125 data->handle = sev->handle;
7126 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
7135 sev_unpin_memory(kvm, pages, n);
7139 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
7141 struct kvm_sev_cmd sev_cmd;
7144 if (!svm_sev_enabled())
7147 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
7150 mutex_lock(&kvm->lock);
7152 switch (sev_cmd.id) {
7154 r = sev_guest_init(kvm, &sev_cmd);
7156 case KVM_SEV_LAUNCH_START:
7157 r = sev_launch_start(kvm, &sev_cmd);
7159 case KVM_SEV_LAUNCH_UPDATE_DATA:
7160 r = sev_launch_update_data(kvm, &sev_cmd);
7162 case KVM_SEV_LAUNCH_MEASURE:
7163 r = sev_launch_measure(kvm, &sev_cmd);
7165 case KVM_SEV_LAUNCH_FINISH:
7166 r = sev_launch_finish(kvm, &sev_cmd);
7168 case KVM_SEV_GUEST_STATUS:
7169 r = sev_guest_status(kvm, &sev_cmd);
7171 case KVM_SEV_DBG_DECRYPT:
7172 r = sev_dbg_crypt(kvm, &sev_cmd, true);
7174 case KVM_SEV_DBG_ENCRYPT:
7175 r = sev_dbg_crypt(kvm, &sev_cmd, false);
7177 case KVM_SEV_LAUNCH_SECRET:
7178 r = sev_launch_secret(kvm, &sev_cmd);
7185 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7189 mutex_unlock(&kvm->lock);
7193 static int svm_register_enc_region(struct kvm *kvm,
7194 struct kvm_enc_region *range)
7196 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7197 struct enc_region *region;
7200 if (!sev_guest(kvm))
7203 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7206 region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7210 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7211 if (!region->pages) {
7217 * The guest may change the memory encryption attribute from C=0 -> C=1
7218 * or vice versa for this memory range. Lets make sure caches are
7219 * flushed to ensure that guest data gets written into memory with
7222 sev_clflush_pages(region->pages, region->npages);
7224 region->uaddr = range->addr;
7225 region->size = range->size;
7227 mutex_lock(&kvm->lock);
7228 list_add_tail(®ion->list, &sev->regions_list);
7229 mutex_unlock(&kvm->lock);
7238 static struct enc_region *
7239 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7241 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7242 struct list_head *head = &sev->regions_list;
7243 struct enc_region *i;
7245 list_for_each_entry(i, head, list) {
7246 if (i->uaddr == range->addr &&
7247 i->size == range->size)
7255 static int svm_unregister_enc_region(struct kvm *kvm,
7256 struct kvm_enc_region *range)
7258 struct enc_region *region;
7261 mutex_lock(&kvm->lock);
7263 if (!sev_guest(kvm)) {
7268 region = find_enc_region(kvm, range);
7274 __unregister_enc_region_locked(kvm, region);
7276 mutex_unlock(&kvm->lock);
7280 mutex_unlock(&kvm->lock);
7284 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7286 unsigned long cr4 = kvm_read_cr4(vcpu);
7287 bool smep = cr4 & X86_CR4_SMEP;
7288 bool smap = cr4 & X86_CR4_SMAP;
7289 bool is_user = svm_get_cpl(vcpu) == 3;
7292 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
7295 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
7296 * possible that CPU microcode implementing DecodeAssist will fail
7297 * to read bytes of instruction which caused #NPF. In this case,
7298 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
7299 * return 0 instead of the correct guest instruction bytes.
7301 * This happens because CPU microcode reading instruction bytes
7302 * uses a special opcode which attempts to read data using CPL=0
7303 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
7304 * fault, it gives up and returns no instruction bytes.
7307 * We reach here in case CPU supports DecodeAssist, raised #NPF and
7308 * returned 0 in GuestIntrBytes field of the VMCB.
7309 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
7310 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
7311 * in case vCPU CPL==3 (Because otherwise guest would have triggered
7312 * a SMEP fault instead of #NPF).
7313 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
7314 * As most guests enable SMAP if they have also enabled SMEP, use above
7315 * logic in order to attempt minimize false-positive of detecting errata
7316 * while still preserving all cases semantic correctness.
7319 * To determine what instruction the guest was executing, the hypervisor
7320 * will have to decode the instruction at the instruction pointer.
7322 * In non SEV guest, hypervisor will be able to read the guest
7323 * memory to decode the instruction pointer when insn_len is zero
7324 * so we return true to indicate that decoding is possible.
7326 * But in the SEV guest, the guest memory is encrypted with the
7327 * guest specific key and hypervisor will not be able to decode the
7328 * instruction pointer so we will not able to workaround it. Lets
7329 * print the error and request to kill the guest.
7331 if (smap && (!smep || is_user)) {
7332 if (!sev_guest(vcpu->kvm))
7335 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
7336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7342 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7344 struct vcpu_svm *svm = to_svm(vcpu);
7347 * TODO: Last condition latch INIT signals on vCPU when
7348 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
7349 * To properly emulate the INIT intercept, SVM should implement
7350 * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit()
7351 * there if an INIT signal is pending.
7353 return !gif_set(svm) ||
7354 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
7357 static bool svm_check_apicv_inhibit_reasons(ulong bit)
7359 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7360 BIT(APICV_INHIBIT_REASON_HYPERV) |
7361 BIT(APICV_INHIBIT_REASON_NESTED) |
7362 BIT(APICV_INHIBIT_REASON_IRQWIN) |
7363 BIT(APICV_INHIBIT_REASON_PIT_REINJ);
7365 return supported & BIT(bit);
7368 static void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate)
7370 avic_update_access_page(kvm, activate);
7373 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7374 .cpu_has_kvm_support = has_svm,
7375 .disabled_by_bios = is_disabled,
7376 .hardware_setup = svm_hardware_setup,
7377 .hardware_unsetup = svm_hardware_unsetup,
7378 .check_processor_compatibility = svm_check_processor_compat,
7379 .hardware_enable = svm_hardware_enable,
7380 .hardware_disable = svm_hardware_disable,
7381 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7382 .has_emulated_msr = svm_has_emulated_msr,
7384 .vcpu_create = svm_create_vcpu,
7385 .vcpu_free = svm_free_vcpu,
7386 .vcpu_reset = svm_vcpu_reset,
7388 .vm_alloc = svm_vm_alloc,
7389 .vm_free = svm_vm_free,
7390 .vm_init = svm_vm_init,
7391 .vm_destroy = svm_vm_destroy,
7393 .prepare_guest_switch = svm_prepare_guest_switch,
7394 .vcpu_load = svm_vcpu_load,
7395 .vcpu_put = svm_vcpu_put,
7396 .vcpu_blocking = svm_vcpu_blocking,
7397 .vcpu_unblocking = svm_vcpu_unblocking,
7399 .update_bp_intercept = update_bp_intercept,
7400 .get_msr_feature = svm_get_msr_feature,
7401 .get_msr = svm_get_msr,
7402 .set_msr = svm_set_msr,
7403 .get_segment_base = svm_get_segment_base,
7404 .get_segment = svm_get_segment,
7405 .set_segment = svm_set_segment,
7406 .get_cpl = svm_get_cpl,
7407 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7408 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7409 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7410 .set_cr0 = svm_set_cr0,
7411 .set_cr3 = svm_set_cr3,
7412 .set_cr4 = svm_set_cr4,
7413 .set_efer = svm_set_efer,
7414 .get_idt = svm_get_idt,
7415 .set_idt = svm_set_idt,
7416 .get_gdt = svm_get_gdt,
7417 .set_gdt = svm_set_gdt,
7418 .get_dr6 = svm_get_dr6,
7419 .set_dr6 = svm_set_dr6,
7420 .set_dr7 = svm_set_dr7,
7421 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7422 .cache_reg = svm_cache_reg,
7423 .get_rflags = svm_get_rflags,
7424 .set_rflags = svm_set_rflags,
7426 .tlb_flush = svm_flush_tlb,
7427 .tlb_flush_gva = svm_flush_tlb_gva,
7429 .run = svm_vcpu_run,
7430 .handle_exit = handle_exit,
7431 .skip_emulated_instruction = skip_emulated_instruction,
7432 .set_interrupt_shadow = svm_set_interrupt_shadow,
7433 .get_interrupt_shadow = svm_get_interrupt_shadow,
7434 .patch_hypercall = svm_patch_hypercall,
7435 .set_irq = svm_set_irq,
7436 .set_nmi = svm_inject_nmi,
7437 .queue_exception = svm_queue_exception,
7438 .cancel_injection = svm_cancel_injection,
7439 .interrupt_allowed = svm_interrupt_allowed,
7440 .nmi_allowed = svm_nmi_allowed,
7441 .get_nmi_mask = svm_get_nmi_mask,
7442 .set_nmi_mask = svm_set_nmi_mask,
7443 .enable_nmi_window = enable_nmi_window,
7444 .enable_irq_window = enable_irq_window,
7445 .update_cr8_intercept = update_cr8_intercept,
7446 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7447 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7448 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
7449 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
7450 .load_eoi_exitmap = svm_load_eoi_exitmap,
7451 .hwapic_irr_update = svm_hwapic_irr_update,
7452 .hwapic_isr_update = svm_hwapic_isr_update,
7453 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7454 .apicv_post_state_restore = avic_post_state_restore,
7456 .set_tss_addr = svm_set_tss_addr,
7457 .set_identity_map_addr = svm_set_identity_map_addr,
7458 .get_tdp_level = get_npt_level,
7459 .get_mt_mask = svm_get_mt_mask,
7461 .get_exit_info = svm_get_exit_info,
7463 .get_lpage_level = svm_get_lpage_level,
7465 .cpuid_update = svm_cpuid_update,
7467 .rdtscp_supported = svm_rdtscp_supported,
7468 .invpcid_supported = svm_invpcid_supported,
7469 .mpx_supported = svm_mpx_supported,
7470 .xsaves_supported = svm_xsaves_supported,
7471 .umip_emulated = svm_umip_emulated,
7472 .pt_supported = svm_pt_supported,
7473 .pku_supported = svm_pku_supported,
7475 .set_supported_cpuid = svm_set_supported_cpuid,
7477 .has_wbinvd_exit = svm_has_wbinvd_exit,
7479 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7480 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7482 .set_tdp_cr3 = set_tdp_cr3,
7484 .check_intercept = svm_check_intercept,
7485 .handle_exit_irqoff = svm_handle_exit_irqoff,
7487 .request_immediate_exit = __kvm_request_immediate_exit,
7489 .sched_in = svm_sched_in,
7491 .pmu_ops = &amd_pmu_ops,
7492 .deliver_posted_interrupt = svm_deliver_avic_intr,
7493 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
7494 .update_pi_irte = svm_update_pi_irte,
7495 .setup_mce = svm_setup_mce,
7497 .smi_allowed = svm_smi_allowed,
7498 .pre_enter_smm = svm_pre_enter_smm,
7499 .pre_leave_smm = svm_pre_leave_smm,
7500 .enable_smi_window = enable_smi_window,
7502 .mem_enc_op = svm_mem_enc_op,
7503 .mem_enc_reg_region = svm_register_enc_region,
7504 .mem_enc_unreg_region = svm_unregister_enc_region,
7506 .nested_enable_evmcs = NULL,
7507 .nested_get_evmcs_version = NULL,
7509 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7511 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
7514 static int __init svm_init(void)
7516 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7517 __alignof__(struct vcpu_svm), THIS_MODULE);
7520 static void __exit svm_exit(void)
7525 module_init(svm_init)
7526 module_exit(svm_exit)