2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
54 #include <asm/virtext.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id svm_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_SVM),
66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
68 #define IOPM_ALLOC_ORDER 2
69 #define MSRPM_ALLOC_ORDER 1
71 #define SEG_TYPE_LDT 2
72 #define SEG_TYPE_BUSY_TSS16 3
74 #define SVM_FEATURE_NPT (1 << 0)
75 #define SVM_FEATURE_LBRV (1 << 1)
76 #define SVM_FEATURE_SVML (1 << 2)
77 #define SVM_FEATURE_NRIP (1 << 3)
78 #define SVM_FEATURE_TSC_RATE (1 << 4)
79 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
80 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
81 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
82 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
84 #define SVM_AVIC_DOORBELL 0xc001011b
86 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
87 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
88 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
92 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
93 #define TSC_RATIO_MIN 0x0000000000000001ULL
94 #define TSC_RATIO_MAX 0x000000ffffffffffULL
96 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
99 * 0xff is broadcast, so the max index allowed for physical APIC ID
100 * table is 0xfe. APIC IDs above 0xff are reserved.
102 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS 8
110 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
112 #define AVIC_VM_ID_BITS 24
113 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
116 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
121 static bool erratum_383_found __read_mostly;
123 static const u32 host_save_user_msrs[] = {
125 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
128 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
134 struct kvm_sev_info {
135 bool active; /* SEV enabled guest */
136 unsigned int asid; /* ASID used for this guest */
137 unsigned int handle; /* SEV firmware handle */
138 int fd; /* SEV device fd */
139 unsigned long pages_locked; /* Number of pages locked */
140 struct list_head regions_list; /* List of registered regions */
146 /* Struct members for AVIC */
148 struct page *avic_logical_id_table_page;
149 struct page *avic_physical_id_table_page;
150 struct hlist_node hnode;
152 struct kvm_sev_info sev_info;
157 struct nested_state {
163 /* These are the merged vectors */
166 /* gpa pointers to the real vectors */
170 /* A VMEXIT is required but not yet emulated */
173 /* cache for intercepts of the guest */
176 u32 intercept_exceptions;
179 /* Nested Paging related state */
183 #define MSRPM_OFFSETS 16
184 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
187 * Set osvw_len to higher value when updated Revision Guides
188 * are published and we know what the new status bits are
190 static uint64_t osvw_len = 4, osvw_status;
193 struct kvm_vcpu vcpu;
195 unsigned long vmcb_pa;
196 struct svm_cpu_data *svm_data;
197 uint64_t asid_generation;
198 uint64_t sysenter_esp;
199 uint64_t sysenter_eip;
206 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
216 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
217 * translated into the appropriate L2_CFG bits on the host to
218 * perform speculative control.
226 struct nested_state nested;
229 u64 nmi_singlestep_guest_rflags;
231 unsigned int3_injected;
232 unsigned long int3_rip;
234 /* cached guest cpuid flags for faster access */
235 bool nrips_enabled : 1;
239 struct page *avic_backing_page;
240 u64 *avic_physical_id_cache;
241 bool avic_is_running;
244 * Per-vcpu list of struct amd_svm_iommu_ir:
245 * This is used mainly to store interrupt remapping information used
246 * when update the vcpu affinity. This avoids the need to scan for
247 * IRTE and try to match ga_tag in the IOMMU driver.
249 struct list_head ir_list;
250 spinlock_t ir_list_lock;
252 /* which host CPU was used for running this vcpu */
253 unsigned int last_cpu;
257 * This is a wrapper of struct amd_iommu_ir_data.
259 struct amd_svm_iommu_ir {
260 struct list_head node; /* Used by SVM for per-vcpu ir_list */
261 void *data; /* Storing pointer to struct amd_ir_data */
264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
265 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
266 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
268 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
269 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
270 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
271 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
273 static DEFINE_PER_CPU(u64, current_tsc_ratio);
274 #define TSC_RATIO_DEFAULT 0x0100000000ULL
276 #define MSR_INVALID 0xffffffffU
278 static const struct svm_direct_access_msrs {
279 u32 index; /* Index of the MSR */
280 bool always; /* True if intercept is always on */
281 } direct_access_msrs[] = {
282 { .index = MSR_STAR, .always = true },
283 { .index = MSR_IA32_SYSENTER_CS, .always = true },
285 { .index = MSR_GS_BASE, .always = true },
286 { .index = MSR_FS_BASE, .always = true },
287 { .index = MSR_KERNEL_GS_BASE, .always = true },
288 { .index = MSR_LSTAR, .always = true },
289 { .index = MSR_CSTAR, .always = true },
290 { .index = MSR_SYSCALL_MASK, .always = true },
292 { .index = MSR_IA32_SPEC_CTRL, .always = false },
293 { .index = MSR_IA32_PRED_CMD, .always = false },
294 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
295 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
296 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
297 { .index = MSR_IA32_LASTINTTOIP, .always = false },
298 { .index = MSR_INVALID, .always = false },
301 /* enable NPT for AMD64 and X86 with PAE */
302 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
303 static bool npt_enabled = true;
305 static bool npt_enabled;
309 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
310 * pause_filter_count: On processors that support Pause filtering(indicated
311 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
312 * count value. On VMRUN this value is loaded into an internal counter.
313 * Each time a pause instruction is executed, this counter is decremented
314 * until it reaches zero at which time a #VMEXIT is generated if pause
315 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
316 * Intercept Filtering for more details.
317 * This also indicate if ple logic enabled.
319 * pause_filter_thresh: In addition, some processor families support advanced
320 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
321 * the amount of time a guest is allowed to execute in a pause loop.
322 * In this mode, a 16-bit pause filter threshold field is added in the
323 * VMCB. The threshold value is a cycle count that is used to reset the
324 * pause counter. As with simple pause filtering, VMRUN loads the pause
325 * count value from VMCB into an internal counter. Then, on each pause
326 * instruction the hardware checks the elapsed number of cycles since
327 * the most recent pause instruction against the pause filter threshold.
328 * If the elapsed cycle count is greater than the pause filter threshold,
329 * then the internal pause count is reloaded from the VMCB and execution
330 * continues. If the elapsed cycle count is less than the pause filter
331 * threshold, then the internal pause count is decremented. If the count
332 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
333 * triggered. If advanced pause filtering is supported and pause filter
334 * threshold field is set to zero, the filter will operate in the simpler,
338 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
339 module_param(pause_filter_thresh, ushort, 0444);
341 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
342 module_param(pause_filter_count, ushort, 0444);
344 /* Default doubles per-vcpu window every exit. */
345 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
346 module_param(pause_filter_count_grow, ushort, 0444);
348 /* Default resets per-vcpu window every exit to pause_filter_count. */
349 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
350 module_param(pause_filter_count_shrink, ushort, 0444);
352 /* Default is to compute the maximum so we can never overflow. */
353 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
354 module_param(pause_filter_count_max, ushort, 0444);
356 /* allow nested paging (virtualized MMU) for all guests */
357 static int npt = true;
358 module_param(npt, int, S_IRUGO);
360 /* allow nested virtualization in KVM/SVM */
361 static int nested = true;
362 module_param(nested, int, S_IRUGO);
364 /* enable / disable AVIC */
366 #ifdef CONFIG_X86_LOCAL_APIC
367 module_param(avic, int, S_IRUGO);
370 /* enable/disable Virtual VMLOAD VMSAVE */
371 static int vls = true;
372 module_param(vls, int, 0444);
374 /* enable/disable Virtual GIF */
375 static int vgif = true;
376 module_param(vgif, int, 0444);
378 /* enable/disable SEV support */
379 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
380 module_param(sev, int, 0444);
382 static u8 rsm_ins_bytes[] = "\x0f\xaa";
384 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
385 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
386 static void svm_complete_interrupts(struct vcpu_svm *svm);
388 static int nested_svm_exit_handled(struct vcpu_svm *svm);
389 static int nested_svm_intercept(struct vcpu_svm *svm);
390 static int nested_svm_vmexit(struct vcpu_svm *svm);
391 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
392 bool has_error_code, u32 error_code);
395 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
396 pause filter count */
397 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
398 VMCB_ASID, /* ASID */
399 VMCB_INTR, /* int_ctl, int_vector */
400 VMCB_NPT, /* npt_en, nCR3, gPAT */
401 VMCB_CR, /* CR0, CR3, CR4, EFER */
402 VMCB_DR, /* DR6, DR7 */
403 VMCB_DT, /* GDT, IDT */
404 VMCB_SEG, /* CS, DS, SS, ES, CPL */
405 VMCB_CR2, /* CR2 only */
406 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
407 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
408 * AVIC PHYSICAL_TABLE pointer,
409 * AVIC LOGICAL_TABLE pointer
414 /* TPR and CR2 are always written before VMRUN */
415 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
417 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
419 static unsigned int max_sev_asid;
420 static unsigned int min_sev_asid;
421 static unsigned long *sev_asid_bitmap;
422 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
425 struct list_head list;
426 unsigned long npages;
433 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
435 return container_of(kvm, struct kvm_svm, kvm);
438 static inline bool svm_sev_enabled(void)
440 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
443 static inline bool sev_guest(struct kvm *kvm)
445 #ifdef CONFIG_KVM_AMD_SEV
446 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
454 static inline int sev_get_asid(struct kvm *kvm)
456 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
461 static inline void mark_all_dirty(struct vmcb *vmcb)
463 vmcb->control.clean = 0;
466 static inline void mark_all_clean(struct vmcb *vmcb)
468 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
469 & ~VMCB_ALWAYS_DIRTY_MASK;
472 static inline void mark_dirty(struct vmcb *vmcb, int bit)
474 vmcb->control.clean &= ~(1 << bit);
477 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
479 return container_of(vcpu, struct vcpu_svm, vcpu);
482 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
484 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
485 mark_dirty(svm->vmcb, VMCB_AVIC);
488 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
490 struct vcpu_svm *svm = to_svm(vcpu);
491 u64 *entry = svm->avic_physical_id_cache;
496 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
499 static void recalc_intercepts(struct vcpu_svm *svm)
501 struct vmcb_control_area *c, *h;
502 struct nested_state *g;
504 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
506 if (!is_guest_mode(&svm->vcpu))
509 c = &svm->vmcb->control;
510 h = &svm->nested.hsave->control;
513 c->intercept_cr = h->intercept_cr | g->intercept_cr;
514 c->intercept_dr = h->intercept_dr | g->intercept_dr;
515 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
516 c->intercept = h->intercept | g->intercept;
519 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
521 if (is_guest_mode(&svm->vcpu))
522 return svm->nested.hsave;
527 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
529 struct vmcb *vmcb = get_host_vmcb(svm);
531 vmcb->control.intercept_cr |= (1U << bit);
533 recalc_intercepts(svm);
536 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
538 struct vmcb *vmcb = get_host_vmcb(svm);
540 vmcb->control.intercept_cr &= ~(1U << bit);
542 recalc_intercepts(svm);
545 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
547 struct vmcb *vmcb = get_host_vmcb(svm);
549 return vmcb->control.intercept_cr & (1U << bit);
552 static inline void set_dr_intercepts(struct vcpu_svm *svm)
554 struct vmcb *vmcb = get_host_vmcb(svm);
556 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
557 | (1 << INTERCEPT_DR1_READ)
558 | (1 << INTERCEPT_DR2_READ)
559 | (1 << INTERCEPT_DR3_READ)
560 | (1 << INTERCEPT_DR4_READ)
561 | (1 << INTERCEPT_DR5_READ)
562 | (1 << INTERCEPT_DR6_READ)
563 | (1 << INTERCEPT_DR7_READ)
564 | (1 << INTERCEPT_DR0_WRITE)
565 | (1 << INTERCEPT_DR1_WRITE)
566 | (1 << INTERCEPT_DR2_WRITE)
567 | (1 << INTERCEPT_DR3_WRITE)
568 | (1 << INTERCEPT_DR4_WRITE)
569 | (1 << INTERCEPT_DR5_WRITE)
570 | (1 << INTERCEPT_DR6_WRITE)
571 | (1 << INTERCEPT_DR7_WRITE);
573 recalc_intercepts(svm);
576 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
578 struct vmcb *vmcb = get_host_vmcb(svm);
580 vmcb->control.intercept_dr = 0;
582 recalc_intercepts(svm);
585 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
587 struct vmcb *vmcb = get_host_vmcb(svm);
589 vmcb->control.intercept_exceptions |= (1U << bit);
591 recalc_intercepts(svm);
594 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
596 struct vmcb *vmcb = get_host_vmcb(svm);
598 vmcb->control.intercept_exceptions &= ~(1U << bit);
600 recalc_intercepts(svm);
603 static inline void set_intercept(struct vcpu_svm *svm, int bit)
605 struct vmcb *vmcb = get_host_vmcb(svm);
607 vmcb->control.intercept |= (1ULL << bit);
609 recalc_intercepts(svm);
612 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
614 struct vmcb *vmcb = get_host_vmcb(svm);
616 vmcb->control.intercept &= ~(1ULL << bit);
618 recalc_intercepts(svm);
621 static inline bool vgif_enabled(struct vcpu_svm *svm)
623 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
626 static inline void enable_gif(struct vcpu_svm *svm)
628 if (vgif_enabled(svm))
629 svm->vmcb->control.int_ctl |= V_GIF_MASK;
631 svm->vcpu.arch.hflags |= HF_GIF_MASK;
634 static inline void disable_gif(struct vcpu_svm *svm)
636 if (vgif_enabled(svm))
637 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
639 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
642 static inline bool gif_set(struct vcpu_svm *svm)
644 if (vgif_enabled(svm))
645 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
647 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
650 static unsigned long iopm_base;
652 struct kvm_ldttss_desc {
655 unsigned base1:8, type:5, dpl:2, p:1;
656 unsigned limit1:4, zero0:3, g:1, base2:8;
659 } __attribute__((packed));
661 struct svm_cpu_data {
668 struct kvm_ldttss_desc *tss_desc;
670 struct page *save_area;
671 struct vmcb *current_vmcb;
673 /* index = sev_asid, value = vmcb pointer */
674 struct vmcb **sev_vmcbs;
677 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
679 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
681 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
682 #define MSRS_RANGE_SIZE 2048
683 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
685 static u32 svm_msrpm_offset(u32 msr)
690 for (i = 0; i < NUM_MSR_MAPS; i++) {
691 if (msr < msrpm_ranges[i] ||
692 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
695 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
696 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
698 /* Now we have the u8 offset - but need the u32 offset */
702 /* MSR not in any range */
706 #define MAX_INST_SIZE 15
708 static inline void clgi(void)
710 asm volatile (__ex("clgi"));
713 static inline void stgi(void)
715 asm volatile (__ex("stgi"));
718 static inline void invlpga(unsigned long addr, u32 asid)
720 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
723 static int get_npt_level(struct kvm_vcpu *vcpu)
726 return PT64_ROOT_4LEVEL;
728 return PT32E_ROOT_LEVEL;
732 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
734 vcpu->arch.efer = efer;
735 if (!npt_enabled && !(efer & EFER_LMA))
738 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
739 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
742 static int is_external_interrupt(u32 info)
744 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
745 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
748 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
750 struct vcpu_svm *svm = to_svm(vcpu);
753 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
754 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
758 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
760 struct vcpu_svm *svm = to_svm(vcpu);
763 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
765 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
769 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
771 struct vcpu_svm *svm = to_svm(vcpu);
773 if (svm->vmcb->control.next_rip != 0) {
774 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
775 svm->next_rip = svm->vmcb->control.next_rip;
778 if (!svm->next_rip) {
779 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
781 printk(KERN_DEBUG "%s: NOP\n", __func__);
784 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
785 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
786 __func__, kvm_rip_read(vcpu), svm->next_rip);
788 kvm_rip_write(vcpu, svm->next_rip);
789 svm_set_interrupt_shadow(vcpu, 0);
792 static void svm_queue_exception(struct kvm_vcpu *vcpu)
794 struct vcpu_svm *svm = to_svm(vcpu);
795 unsigned nr = vcpu->arch.exception.nr;
796 bool has_error_code = vcpu->arch.exception.has_error_code;
797 bool reinject = vcpu->arch.exception.injected;
798 u32 error_code = vcpu->arch.exception.error_code;
801 * If we are within a nested VM we'd better #VMEXIT and let the guest
802 * handle the exception
805 nested_svm_check_exception(svm, nr, has_error_code, error_code))
808 kvm_deliver_exception_payload(&svm->vcpu);
810 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
811 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
814 * For guest debugging where we have to reinject #BP if some
815 * INT3 is guest-owned:
816 * Emulate nRIP by moving RIP forward. Will fail if injection
817 * raises a fault that is not intercepted. Still better than
818 * failing in all cases.
820 skip_emulated_instruction(&svm->vcpu);
821 rip = kvm_rip_read(&svm->vcpu);
822 svm->int3_rip = rip + svm->vmcb->save.cs.base;
823 svm->int3_injected = rip - old_rip;
826 svm->vmcb->control.event_inj = nr
828 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
829 | SVM_EVTINJ_TYPE_EXEPT;
830 svm->vmcb->control.event_inj_err = error_code;
833 static void svm_init_erratum_383(void)
839 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
842 /* Use _safe variants to not break nested virtualization */
843 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
849 low = lower_32_bits(val);
850 high = upper_32_bits(val);
852 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
854 erratum_383_found = true;
857 static void svm_init_osvw(struct kvm_vcpu *vcpu)
860 * Guests should see errata 400 and 415 as fixed (assuming that
861 * HLT and IO instructions are intercepted).
863 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
864 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
867 * By increasing VCPU's osvw.length to 3 we are telling the guest that
868 * all osvw.status bits inside that length, including bit 0 (which is
869 * reserved for erratum 298), are valid. However, if host processor's
870 * osvw_len is 0 then osvw_status[0] carries no information. We need to
871 * be conservative here and therefore we tell the guest that erratum 298
872 * is present (because we really don't know).
874 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
875 vcpu->arch.osvw.status |= 1;
878 static int has_svm(void)
882 if (!cpu_has_svm(&msg)) {
883 printk(KERN_INFO "has_svm: %s\n", msg);
890 static void svm_hardware_disable(void)
892 /* Make sure we clean up behind us */
893 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
894 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
898 amd_pmu_disable_virt();
901 static int svm_hardware_enable(void)
904 struct svm_cpu_data *sd;
906 struct desc_struct *gdt;
907 int me = raw_smp_processor_id();
909 rdmsrl(MSR_EFER, efer);
910 if (efer & EFER_SVME)
914 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
917 sd = per_cpu(svm_data, me);
919 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
923 sd->asid_generation = 1;
924 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
925 sd->next_asid = sd->max_asid + 1;
926 sd->min_asid = max_sev_asid + 1;
928 gdt = get_current_gdt_rw();
929 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
931 wrmsrl(MSR_EFER, efer | EFER_SVME);
933 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
935 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
936 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
937 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
944 * Note that it is possible to have a system with mixed processor
945 * revisions and therefore different OSVW bits. If bits are not the same
946 * on different processors then choose the worst case (i.e. if erratum
947 * is present on one processor and not on another then assume that the
948 * erratum is present everywhere).
950 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
951 uint64_t len, status = 0;
954 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
956 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
960 osvw_status = osvw_len = 0;
964 osvw_status |= status;
965 osvw_status &= (1ULL << osvw_len) - 1;
968 osvw_status = osvw_len = 0;
970 svm_init_erratum_383();
972 amd_pmu_enable_virt();
977 static void svm_cpu_uninit(int cpu)
979 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
984 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
985 kfree(sd->sev_vmcbs);
986 __free_page(sd->save_area);
990 static int svm_cpu_init(int cpu)
992 struct svm_cpu_data *sd;
995 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1000 sd->save_area = alloc_page(GFP_KERNEL);
1004 if (svm_sev_enabled()) {
1006 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1013 per_cpu(svm_data, cpu) = sd;
1023 static bool valid_msr_intercept(u32 index)
1027 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1028 if (direct_access_msrs[i].index == index)
1034 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1041 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1042 to_svm(vcpu)->msrpm;
1044 offset = svm_msrpm_offset(msr);
1045 bit_write = 2 * (msr & 0x0f) + 1;
1046 tmp = msrpm[offset];
1048 BUG_ON(offset == MSR_INVALID);
1050 return !!test_bit(bit_write, &tmp);
1053 static void set_msr_interception(u32 *msrpm, unsigned msr,
1054 int read, int write)
1056 u8 bit_read, bit_write;
1061 * If this warning triggers extend the direct_access_msrs list at the
1062 * beginning of the file
1064 WARN_ON(!valid_msr_intercept(msr));
1066 offset = svm_msrpm_offset(msr);
1067 bit_read = 2 * (msr & 0x0f);
1068 bit_write = 2 * (msr & 0x0f) + 1;
1069 tmp = msrpm[offset];
1071 BUG_ON(offset == MSR_INVALID);
1073 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1074 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1076 msrpm[offset] = tmp;
1079 static void svm_vcpu_init_msrpm(u32 *msrpm)
1083 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1085 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1086 if (!direct_access_msrs[i].always)
1089 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1093 static void add_msr_offset(u32 offset)
1097 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1099 /* Offset already in list? */
1100 if (msrpm_offsets[i] == offset)
1103 /* Slot used by another offset? */
1104 if (msrpm_offsets[i] != MSR_INVALID)
1107 /* Add offset to list */
1108 msrpm_offsets[i] = offset;
1114 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1115 * increase MSRPM_OFFSETS in this case.
1120 static void init_msrpm_offsets(void)
1124 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1126 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1129 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1130 BUG_ON(offset == MSR_INVALID);
1132 add_msr_offset(offset);
1136 static void svm_enable_lbrv(struct vcpu_svm *svm)
1138 u32 *msrpm = svm->msrpm;
1140 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1141 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1142 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1143 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1144 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1147 static void svm_disable_lbrv(struct vcpu_svm *svm)
1149 u32 *msrpm = svm->msrpm;
1151 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1152 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1153 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1154 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1155 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1158 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1160 svm->nmi_singlestep = false;
1162 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1163 /* Clear our flags if they were not set by the guest */
1164 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1165 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1166 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1167 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1172 * This hash table is used to map VM_ID to a struct kvm_svm,
1173 * when handling AMD IOMMU GALOG notification to schedule in
1174 * a particular vCPU.
1176 #define SVM_VM_DATA_HASH_BITS 8
1177 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1178 static u32 next_vm_id = 0;
1179 static bool next_vm_id_wrapped = 0;
1180 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1183 * This function is called from IOMMU driver to notify
1184 * SVM to schedule in a particular vCPU of a particular VM.
1186 static int avic_ga_log_notifier(u32 ga_tag)
1188 unsigned long flags;
1189 struct kvm_svm *kvm_svm;
1190 struct kvm_vcpu *vcpu = NULL;
1191 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1192 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1194 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1196 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1197 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1198 if (kvm_svm->avic_vm_id != vm_id)
1200 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1203 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1206 * At this point, the IOMMU should have already set the pending
1207 * bit in the vAPIC backing page. So, we just need to schedule
1211 kvm_vcpu_wake_up(vcpu);
1216 static __init int sev_hardware_setup(void)
1218 struct sev_user_data_status *status;
1221 /* Maximum number of encrypted guests supported simultaneously */
1222 max_sev_asid = cpuid_ecx(0x8000001F);
1227 /* Minimum ASID value that should be used for SEV guest */
1228 min_sev_asid = cpuid_edx(0x8000001F);
1230 /* Initialize SEV ASID bitmap */
1231 sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1232 if (!sev_asid_bitmap)
1235 status = kmalloc(sizeof(*status), GFP_KERNEL);
1240 * Check SEV platform status.
1242 * PLATFORM_STATUS can be called in any state, if we failed to query
1243 * the PLATFORM status then either PSP firmware does not support SEV
1244 * feature or SEV firmware is dead.
1246 rc = sev_platform_status(status, NULL);
1250 pr_info("SEV supported\n");
1257 static void grow_ple_window(struct kvm_vcpu *vcpu)
1259 struct vcpu_svm *svm = to_svm(vcpu);
1260 struct vmcb_control_area *control = &svm->vmcb->control;
1261 int old = control->pause_filter_count;
1263 control->pause_filter_count = __grow_ple_window(old,
1265 pause_filter_count_grow,
1266 pause_filter_count_max);
1268 if (control->pause_filter_count != old)
1269 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1271 trace_kvm_ple_window_grow(vcpu->vcpu_id,
1272 control->pause_filter_count, old);
1275 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1277 struct vcpu_svm *svm = to_svm(vcpu);
1278 struct vmcb_control_area *control = &svm->vmcb->control;
1279 int old = control->pause_filter_count;
1281 control->pause_filter_count =
1282 __shrink_ple_window(old,
1284 pause_filter_count_shrink,
1285 pause_filter_count);
1286 if (control->pause_filter_count != old)
1287 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1289 trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1290 control->pause_filter_count, old);
1293 static __init int svm_hardware_setup(void)
1296 struct page *iopm_pages;
1300 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1305 iopm_va = page_address(iopm_pages);
1306 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1307 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1309 init_msrpm_offsets();
1311 if (boot_cpu_has(X86_FEATURE_NX))
1312 kvm_enable_efer_bits(EFER_NX);
1314 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1315 kvm_enable_efer_bits(EFER_FFXSR);
1317 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1318 kvm_has_tsc_control = true;
1319 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1320 kvm_tsc_scaling_ratio_frac_bits = 32;
1323 /* Check for pause filtering support */
1324 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1325 pause_filter_count = 0;
1326 pause_filter_thresh = 0;
1327 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1328 pause_filter_thresh = 0;
1332 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1333 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1337 if (boot_cpu_has(X86_FEATURE_SEV) &&
1338 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1339 r = sev_hardware_setup();
1347 for_each_possible_cpu(cpu) {
1348 r = svm_cpu_init(cpu);
1353 if (!boot_cpu_has(X86_FEATURE_NPT))
1354 npt_enabled = false;
1356 if (npt_enabled && !npt) {
1357 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1358 npt_enabled = false;
1362 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1369 !boot_cpu_has(X86_FEATURE_AVIC) ||
1370 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1373 pr_info("AVIC enabled\n");
1375 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1381 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1382 !IS_ENABLED(CONFIG_X86_64)) {
1385 pr_info("Virtual VMLOAD VMSAVE supported\n");
1390 if (!boot_cpu_has(X86_FEATURE_VGIF))
1393 pr_info("Virtual GIF supported\n");
1399 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1404 static __exit void svm_hardware_unsetup(void)
1408 if (svm_sev_enabled())
1409 bitmap_free(sev_asid_bitmap);
1411 for_each_possible_cpu(cpu)
1412 svm_cpu_uninit(cpu);
1414 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1418 static void init_seg(struct vmcb_seg *seg)
1421 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1422 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1423 seg->limit = 0xffff;
1427 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1430 seg->attrib = SVM_SELECTOR_P_MASK | type;
1431 seg->limit = 0xffff;
1435 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1437 struct vcpu_svm *svm = to_svm(vcpu);
1439 if (is_guest_mode(vcpu))
1440 return svm->nested.hsave->control.tsc_offset;
1442 return vcpu->arch.tsc_offset;
1445 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1447 struct vcpu_svm *svm = to_svm(vcpu);
1448 u64 g_tsc_offset = 0;
1450 if (is_guest_mode(vcpu)) {
1451 /* Write L1's TSC offset. */
1452 g_tsc_offset = svm->vmcb->control.tsc_offset -
1453 svm->nested.hsave->control.tsc_offset;
1454 svm->nested.hsave->control.tsc_offset = offset;
1457 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1458 svm->vmcb->control.tsc_offset - g_tsc_offset,
1461 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1463 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1464 return svm->vmcb->control.tsc_offset;
1467 static void avic_init_vmcb(struct vcpu_svm *svm)
1469 struct vmcb *vmcb = svm->vmcb;
1470 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1471 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1472 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1473 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1475 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1476 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1477 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1478 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1479 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1482 static void init_vmcb(struct vcpu_svm *svm)
1484 struct vmcb_control_area *control = &svm->vmcb->control;
1485 struct vmcb_save_area *save = &svm->vmcb->save;
1487 svm->vcpu.arch.hflags = 0;
1489 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1490 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1491 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1492 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1493 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1494 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1495 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1496 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1498 set_dr_intercepts(svm);
1500 set_exception_intercept(svm, PF_VECTOR);
1501 set_exception_intercept(svm, UD_VECTOR);
1502 set_exception_intercept(svm, MC_VECTOR);
1503 set_exception_intercept(svm, AC_VECTOR);
1504 set_exception_intercept(svm, DB_VECTOR);
1506 * Guest access to VMware backdoor ports could legitimately
1507 * trigger #GP because of TSS I/O permission bitmap.
1508 * We intercept those #GP and allow access to them anyway
1511 if (enable_vmware_backdoor)
1512 set_exception_intercept(svm, GP_VECTOR);
1514 set_intercept(svm, INTERCEPT_INTR);
1515 set_intercept(svm, INTERCEPT_NMI);
1516 set_intercept(svm, INTERCEPT_SMI);
1517 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1518 set_intercept(svm, INTERCEPT_RDPMC);
1519 set_intercept(svm, INTERCEPT_CPUID);
1520 set_intercept(svm, INTERCEPT_INVD);
1521 set_intercept(svm, INTERCEPT_INVLPG);
1522 set_intercept(svm, INTERCEPT_INVLPGA);
1523 set_intercept(svm, INTERCEPT_IOIO_PROT);
1524 set_intercept(svm, INTERCEPT_MSR_PROT);
1525 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1526 set_intercept(svm, INTERCEPT_SHUTDOWN);
1527 set_intercept(svm, INTERCEPT_VMRUN);
1528 set_intercept(svm, INTERCEPT_VMMCALL);
1529 set_intercept(svm, INTERCEPT_VMLOAD);
1530 set_intercept(svm, INTERCEPT_VMSAVE);
1531 set_intercept(svm, INTERCEPT_STGI);
1532 set_intercept(svm, INTERCEPT_CLGI);
1533 set_intercept(svm, INTERCEPT_SKINIT);
1534 set_intercept(svm, INTERCEPT_WBINVD);
1535 set_intercept(svm, INTERCEPT_XSETBV);
1536 set_intercept(svm, INTERCEPT_RSM);
1538 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1539 set_intercept(svm, INTERCEPT_MONITOR);
1540 set_intercept(svm, INTERCEPT_MWAIT);
1543 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1544 set_intercept(svm, INTERCEPT_HLT);
1546 control->iopm_base_pa = __sme_set(iopm_base);
1547 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1548 control->int_ctl = V_INTR_MASKING_MASK;
1550 init_seg(&save->es);
1551 init_seg(&save->ss);
1552 init_seg(&save->ds);
1553 init_seg(&save->fs);
1554 init_seg(&save->gs);
1556 save->cs.selector = 0xf000;
1557 save->cs.base = 0xffff0000;
1558 /* Executable/Readable Code Segment */
1559 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1560 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1561 save->cs.limit = 0xffff;
1563 save->gdtr.limit = 0xffff;
1564 save->idtr.limit = 0xffff;
1566 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1567 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1569 svm_set_efer(&svm->vcpu, 0);
1570 save->dr6 = 0xffff0ff0;
1571 kvm_set_rflags(&svm->vcpu, 2);
1572 save->rip = 0x0000fff0;
1573 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1576 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1577 * It also updates the guest-visible cr0 value.
1579 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1580 kvm_mmu_reset_context(&svm->vcpu);
1582 save->cr4 = X86_CR4_PAE;
1586 /* Setup VMCB for Nested Paging */
1587 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1588 clr_intercept(svm, INTERCEPT_INVLPG);
1589 clr_exception_intercept(svm, PF_VECTOR);
1590 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1591 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1592 save->g_pat = svm->vcpu.arch.pat;
1596 svm->asid_generation = 0;
1598 svm->nested.vmcb = 0;
1599 svm->vcpu.arch.hflags = 0;
1601 if (pause_filter_count) {
1602 control->pause_filter_count = pause_filter_count;
1603 if (pause_filter_thresh)
1604 control->pause_filter_thresh = pause_filter_thresh;
1605 set_intercept(svm, INTERCEPT_PAUSE);
1607 clr_intercept(svm, INTERCEPT_PAUSE);
1610 if (kvm_vcpu_apicv_active(&svm->vcpu))
1611 avic_init_vmcb(svm);
1614 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1615 * in VMCB and clear intercepts to avoid #VMEXIT.
1618 clr_intercept(svm, INTERCEPT_VMLOAD);
1619 clr_intercept(svm, INTERCEPT_VMSAVE);
1620 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1624 clr_intercept(svm, INTERCEPT_STGI);
1625 clr_intercept(svm, INTERCEPT_CLGI);
1626 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1629 if (sev_guest(svm->vcpu.kvm)) {
1630 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1631 clr_exception_intercept(svm, UD_VECTOR);
1634 mark_all_dirty(svm->vmcb);
1640 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1643 u64 *avic_physical_id_table;
1644 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1646 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1649 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1651 return &avic_physical_id_table[index];
1656 * AVIC hardware walks the nested page table to check permissions,
1657 * but does not use the SPA address specified in the leaf page
1658 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1659 * field of the VMCB. Therefore, we set up the
1660 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1662 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1664 struct kvm *kvm = vcpu->kvm;
1667 mutex_lock(&kvm->slots_lock);
1668 if (kvm->arch.apic_access_page_done)
1671 ret = __x86_set_memory_region(kvm,
1672 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1673 APIC_DEFAULT_PHYS_BASE,
1678 kvm->arch.apic_access_page_done = true;
1680 mutex_unlock(&kvm->slots_lock);
1684 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1687 u64 *entry, new_entry;
1688 int id = vcpu->vcpu_id;
1689 struct vcpu_svm *svm = to_svm(vcpu);
1691 ret = avic_init_access_page(vcpu);
1695 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1698 if (!svm->vcpu.arch.apic->regs)
1701 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1703 /* Setting AVIC backing page address in the phy APIC ID table */
1704 entry = avic_get_physical_id_entry(vcpu, id);
1708 new_entry = READ_ONCE(*entry);
1709 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1710 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1711 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1712 WRITE_ONCE(*entry, new_entry);
1714 svm->avic_physical_id_cache = entry;
1719 static void __sev_asid_free(int asid)
1721 struct svm_cpu_data *sd;
1725 clear_bit(pos, sev_asid_bitmap);
1727 for_each_possible_cpu(cpu) {
1728 sd = per_cpu(svm_data, cpu);
1729 sd->sev_vmcbs[pos] = NULL;
1733 static void sev_asid_free(struct kvm *kvm)
1735 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1737 __sev_asid_free(sev->asid);
1740 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1742 struct sev_data_decommission *decommission;
1743 struct sev_data_deactivate *data;
1748 data = kzalloc(sizeof(*data), GFP_KERNEL);
1752 /* deactivate handle */
1753 data->handle = handle;
1754 sev_guest_deactivate(data, NULL);
1756 wbinvd_on_all_cpus();
1757 sev_guest_df_flush(NULL);
1760 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1764 /* decommission handle */
1765 decommission->handle = handle;
1766 sev_guest_decommission(decommission, NULL);
1768 kfree(decommission);
1771 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1772 unsigned long ulen, unsigned long *n,
1775 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1776 unsigned long npages, npinned, size;
1777 unsigned long locked, lock_limit;
1778 struct page **pages;
1779 unsigned long first, last;
1781 if (ulen == 0 || uaddr + ulen < uaddr)
1784 /* Calculate number of pages. */
1785 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1786 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1787 npages = (last - first + 1);
1789 locked = sev->pages_locked + npages;
1790 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1791 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1792 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1796 /* Avoid using vmalloc for smaller buffers. */
1797 size = npages * sizeof(struct page *);
1798 if (size > PAGE_SIZE)
1799 pages = __vmalloc(size, GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1802 pages = kmalloc(size, GFP_KERNEL_ACCOUNT);
1807 /* Pin the user virtual address. */
1808 npinned = get_user_pages_fast(uaddr, npages, FOLL_WRITE, pages);
1809 if (npinned != npages) {
1810 pr_err("SEV: Failure locking %lu pages.\n", npages);
1815 sev->pages_locked = locked;
1821 release_pages(pages, npinned);
1827 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1828 unsigned long npages)
1830 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1832 release_pages(pages, npages);
1834 sev->pages_locked -= npages;
1837 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1839 uint8_t *page_virtual;
1842 if (npages == 0 || pages == NULL)
1845 for (i = 0; i < npages; i++) {
1846 page_virtual = kmap_atomic(pages[i]);
1847 clflush_cache_range(page_virtual, PAGE_SIZE);
1848 kunmap_atomic(page_virtual);
1852 static void __unregister_enc_region_locked(struct kvm *kvm,
1853 struct enc_region *region)
1856 * The guest may change the memory encryption attribute from C=0 -> C=1
1857 * or vice versa for this memory range. Lets make sure caches are
1858 * flushed to ensure that guest data gets written into memory with
1861 sev_clflush_pages(region->pages, region->npages);
1863 sev_unpin_memory(kvm, region->pages, region->npages);
1864 list_del(®ion->list);
1868 static struct kvm *svm_vm_alloc(void)
1870 struct kvm_svm *kvm_svm = __vmalloc(sizeof(struct kvm_svm),
1871 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
1873 return &kvm_svm->kvm;
1876 static void svm_vm_free(struct kvm *kvm)
1878 vfree(to_kvm_svm(kvm));
1881 static void sev_vm_destroy(struct kvm *kvm)
1883 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1884 struct list_head *head = &sev->regions_list;
1885 struct list_head *pos, *q;
1887 if (!sev_guest(kvm))
1890 mutex_lock(&kvm->lock);
1893 * if userspace was terminated before unregistering the memory regions
1894 * then lets unpin all the registered memory.
1896 if (!list_empty(head)) {
1897 list_for_each_safe(pos, q, head) {
1898 __unregister_enc_region_locked(kvm,
1899 list_entry(pos, struct enc_region, list));
1903 mutex_unlock(&kvm->lock);
1905 sev_unbind_asid(kvm, sev->handle);
1909 static void avic_vm_destroy(struct kvm *kvm)
1911 unsigned long flags;
1912 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1917 if (kvm_svm->avic_logical_id_table_page)
1918 __free_page(kvm_svm->avic_logical_id_table_page);
1919 if (kvm_svm->avic_physical_id_table_page)
1920 __free_page(kvm_svm->avic_physical_id_table_page);
1922 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1923 hash_del(&kvm_svm->hnode);
1924 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1927 static void svm_vm_destroy(struct kvm *kvm)
1929 avic_vm_destroy(kvm);
1930 sev_vm_destroy(kvm);
1933 static int avic_vm_init(struct kvm *kvm)
1935 unsigned long flags;
1937 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1939 struct page *p_page;
1940 struct page *l_page;
1946 /* Allocating physical APIC ID table (4KB) */
1947 p_page = alloc_page(GFP_KERNEL_ACCOUNT);
1951 kvm_svm->avic_physical_id_table_page = p_page;
1952 clear_page(page_address(p_page));
1954 /* Allocating logical APIC ID table (4KB) */
1955 l_page = alloc_page(GFP_KERNEL_ACCOUNT);
1959 kvm_svm->avic_logical_id_table_page = l_page;
1960 clear_page(page_address(l_page));
1962 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1964 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1965 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1966 next_vm_id_wrapped = 1;
1969 /* Is it still in use? Only possible if wrapped at least once */
1970 if (next_vm_id_wrapped) {
1971 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1972 if (k2->avic_vm_id == vm_id)
1976 kvm_svm->avic_vm_id = vm_id;
1977 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1978 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1983 avic_vm_destroy(kvm);
1988 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1991 unsigned long flags;
1992 struct amd_svm_iommu_ir *ir;
1993 struct vcpu_svm *svm = to_svm(vcpu);
1995 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1999 * Here, we go through the per-vcpu ir_list to update all existing
2000 * interrupt remapping table entry targeting this vcpu.
2002 spin_lock_irqsave(&svm->ir_list_lock, flags);
2004 if (list_empty(&svm->ir_list))
2007 list_for_each_entry(ir, &svm->ir_list, node) {
2008 ret = amd_iommu_update_ga(cpu, r, ir->data);
2013 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2017 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2020 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2021 int h_physical_id = kvm_cpu_get_apicid(cpu);
2022 struct vcpu_svm *svm = to_svm(vcpu);
2024 if (!kvm_vcpu_apicv_active(vcpu))
2027 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2030 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2031 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2033 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2034 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2036 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2037 if (svm->avic_is_running)
2038 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2040 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2041 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2042 svm->avic_is_running);
2045 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2048 struct vcpu_svm *svm = to_svm(vcpu);
2050 if (!kvm_vcpu_apicv_active(vcpu))
2053 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2054 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2055 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2057 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2058 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2062 * This function is called during VCPU halt/unhalt.
2064 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2066 struct vcpu_svm *svm = to_svm(vcpu);
2068 svm->avic_is_running = is_run;
2070 avic_vcpu_load(vcpu, vcpu->cpu);
2072 avic_vcpu_put(vcpu);
2075 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2077 struct vcpu_svm *svm = to_svm(vcpu);
2081 vcpu->arch.microcode_version = 0x01000065;
2083 svm->virt_spec_ctrl = 0;
2086 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2087 MSR_IA32_APICBASE_ENABLE;
2088 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2089 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2093 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2094 kvm_rdx_write(vcpu, eax);
2096 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2097 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2100 static int avic_init_vcpu(struct vcpu_svm *svm)
2104 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2107 ret = avic_init_backing_page(&svm->vcpu);
2111 INIT_LIST_HEAD(&svm->ir_list);
2112 spin_lock_init(&svm->ir_list_lock);
2113 svm->dfr_reg = APIC_DFR_FLAT;
2118 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2120 struct vcpu_svm *svm;
2122 struct page *msrpm_pages;
2123 struct page *hsave_page;
2124 struct page *nested_msrpm_pages;
2127 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
2133 svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
2134 GFP_KERNEL_ACCOUNT);
2135 if (!svm->vcpu.arch.guest_fpu) {
2136 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2138 goto free_partial_svm;
2141 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2146 page = alloc_page(GFP_KERNEL_ACCOUNT);
2150 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2154 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
2155 if (!nested_msrpm_pages)
2158 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
2162 err = avic_init_vcpu(svm);
2166 /* We initialize this flag to true to make sure that the is_running
2167 * bit would be set the first time the vcpu is loaded.
2169 svm->avic_is_running = true;
2171 svm->nested.hsave = page_address(hsave_page);
2173 svm->msrpm = page_address(msrpm_pages);
2174 svm_vcpu_init_msrpm(svm->msrpm);
2176 svm->nested.msrpm = page_address(nested_msrpm_pages);
2177 svm_vcpu_init_msrpm(svm->nested.msrpm);
2179 svm->vmcb = page_address(page);
2180 clear_page(svm->vmcb);
2181 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2182 svm->asid_generation = 0;
2185 svm_init_osvw(&svm->vcpu);
2190 __free_page(hsave_page);
2192 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2194 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2198 kvm_vcpu_uninit(&svm->vcpu);
2200 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2202 kmem_cache_free(kvm_vcpu_cache, svm);
2204 return ERR_PTR(err);
2207 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2211 for_each_online_cpu(i)
2212 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2215 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2217 struct vcpu_svm *svm = to_svm(vcpu);
2220 * The vmcb page can be recycled, causing a false negative in
2221 * svm_vcpu_load(). So, ensure that no logical CPU has this
2222 * vmcb page recorded as its current vmcb.
2224 svm_clear_current_vmcb(svm->vmcb);
2226 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2227 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2228 __free_page(virt_to_page(svm->nested.hsave));
2229 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2230 kvm_vcpu_uninit(vcpu);
2231 kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2232 kmem_cache_free(kvm_vcpu_cache, svm);
2235 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2237 struct vcpu_svm *svm = to_svm(vcpu);
2238 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2241 if (unlikely(cpu != vcpu->cpu)) {
2242 svm->asid_generation = 0;
2243 mark_all_dirty(svm->vmcb);
2246 #ifdef CONFIG_X86_64
2247 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2249 savesegment(fs, svm->host.fs);
2250 savesegment(gs, svm->host.gs);
2251 svm->host.ldt = kvm_read_ldt();
2253 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2254 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2256 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2257 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2258 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2259 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2260 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2263 /* This assumes that the kernel never uses MSR_TSC_AUX */
2264 if (static_cpu_has(X86_FEATURE_RDTSCP))
2265 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2267 if (sd->current_vmcb != svm->vmcb) {
2268 sd->current_vmcb = svm->vmcb;
2269 indirect_branch_prediction_barrier();
2271 avic_vcpu_load(vcpu, cpu);
2274 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2276 struct vcpu_svm *svm = to_svm(vcpu);
2279 avic_vcpu_put(vcpu);
2281 ++vcpu->stat.host_state_reload;
2282 kvm_load_ldt(svm->host.ldt);
2283 #ifdef CONFIG_X86_64
2284 loadsegment(fs, svm->host.fs);
2285 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2286 load_gs_index(svm->host.gs);
2288 #ifdef CONFIG_X86_32_LAZY_GS
2289 loadsegment(gs, svm->host.gs);
2292 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2293 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2296 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2298 avic_set_running(vcpu, false);
2301 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2303 avic_set_running(vcpu, true);
2306 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2308 struct vcpu_svm *svm = to_svm(vcpu);
2309 unsigned long rflags = svm->vmcb->save.rflags;
2311 if (svm->nmi_singlestep) {
2312 /* Hide our flags if they were not set by the guest */
2313 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2314 rflags &= ~X86_EFLAGS_TF;
2315 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2316 rflags &= ~X86_EFLAGS_RF;
2321 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2323 if (to_svm(vcpu)->nmi_singlestep)
2324 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2327 * Any change of EFLAGS.VM is accompanied by a reload of SS
2328 * (caused by either a task switch or an inter-privilege IRET),
2329 * so we do not need to update the CPL here.
2331 to_svm(vcpu)->vmcb->save.rflags = rflags;
2334 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2337 case VCPU_EXREG_PDPTR:
2338 BUG_ON(!npt_enabled);
2339 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2346 static void svm_set_vintr(struct vcpu_svm *svm)
2348 set_intercept(svm, INTERCEPT_VINTR);
2351 static void svm_clear_vintr(struct vcpu_svm *svm)
2353 clr_intercept(svm, INTERCEPT_VINTR);
2356 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2358 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2361 case VCPU_SREG_CS: return &save->cs;
2362 case VCPU_SREG_DS: return &save->ds;
2363 case VCPU_SREG_ES: return &save->es;
2364 case VCPU_SREG_FS: return &save->fs;
2365 case VCPU_SREG_GS: return &save->gs;
2366 case VCPU_SREG_SS: return &save->ss;
2367 case VCPU_SREG_TR: return &save->tr;
2368 case VCPU_SREG_LDTR: return &save->ldtr;
2374 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2376 struct vmcb_seg *s = svm_seg(vcpu, seg);
2381 static void svm_get_segment(struct kvm_vcpu *vcpu,
2382 struct kvm_segment *var, int seg)
2384 struct vmcb_seg *s = svm_seg(vcpu, seg);
2386 var->base = s->base;
2387 var->limit = s->limit;
2388 var->selector = s->selector;
2389 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2390 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2391 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2392 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2393 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2394 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2395 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2398 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2399 * However, the SVM spec states that the G bit is not observed by the
2400 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2401 * So let's synthesize a legal G bit for all segments, this helps
2402 * running KVM nested. It also helps cross-vendor migration, because
2403 * Intel's vmentry has a check on the 'G' bit.
2405 var->g = s->limit > 0xfffff;
2408 * AMD's VMCB does not have an explicit unusable field, so emulate it
2409 * for cross vendor migration purposes by "not present"
2411 var->unusable = !var->present;
2416 * Work around a bug where the busy flag in the tr selector
2426 * The accessed bit must always be set in the segment
2427 * descriptor cache, although it can be cleared in the
2428 * descriptor, the cached bit always remains at 1. Since
2429 * Intel has a check on this, set it here to support
2430 * cross-vendor migration.
2437 * On AMD CPUs sometimes the DB bit in the segment
2438 * descriptor is left as 1, although the whole segment has
2439 * been made unusable. Clear it here to pass an Intel VMX
2440 * entry check when cross vendor migrating.
2444 /* This is symmetric with svm_set_segment() */
2445 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2450 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2452 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2457 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2459 struct vcpu_svm *svm = to_svm(vcpu);
2461 dt->size = svm->vmcb->save.idtr.limit;
2462 dt->address = svm->vmcb->save.idtr.base;
2465 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2467 struct vcpu_svm *svm = to_svm(vcpu);
2469 svm->vmcb->save.idtr.limit = dt->size;
2470 svm->vmcb->save.idtr.base = dt->address ;
2471 mark_dirty(svm->vmcb, VMCB_DT);
2474 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2476 struct vcpu_svm *svm = to_svm(vcpu);
2478 dt->size = svm->vmcb->save.gdtr.limit;
2479 dt->address = svm->vmcb->save.gdtr.base;
2482 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2484 struct vcpu_svm *svm = to_svm(vcpu);
2486 svm->vmcb->save.gdtr.limit = dt->size;
2487 svm->vmcb->save.gdtr.base = dt->address ;
2488 mark_dirty(svm->vmcb, VMCB_DT);
2491 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2495 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2499 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2503 static void update_cr0_intercept(struct vcpu_svm *svm)
2505 ulong gcr0 = svm->vcpu.arch.cr0;
2506 u64 *hcr0 = &svm->vmcb->save.cr0;
2508 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2509 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2511 mark_dirty(svm->vmcb, VMCB_CR);
2513 if (gcr0 == *hcr0) {
2514 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2515 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2517 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2518 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2522 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2524 struct vcpu_svm *svm = to_svm(vcpu);
2526 #ifdef CONFIG_X86_64
2527 if (vcpu->arch.efer & EFER_LME) {
2528 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2529 vcpu->arch.efer |= EFER_LMA;
2530 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2533 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2534 vcpu->arch.efer &= ~EFER_LMA;
2535 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2539 vcpu->arch.cr0 = cr0;
2542 cr0 |= X86_CR0_PG | X86_CR0_WP;
2545 * re-enable caching here because the QEMU bios
2546 * does not do it - this results in some delay at
2549 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2550 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2551 svm->vmcb->save.cr0 = cr0;
2552 mark_dirty(svm->vmcb, VMCB_CR);
2553 update_cr0_intercept(svm);
2556 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2558 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2559 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2561 if (cr4 & X86_CR4_VMXE)
2564 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2565 svm_flush_tlb(vcpu, true);
2567 vcpu->arch.cr4 = cr4;
2570 cr4 |= host_cr4_mce;
2571 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2572 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2576 static void svm_set_segment(struct kvm_vcpu *vcpu,
2577 struct kvm_segment *var, int seg)
2579 struct vcpu_svm *svm = to_svm(vcpu);
2580 struct vmcb_seg *s = svm_seg(vcpu, seg);
2582 s->base = var->base;
2583 s->limit = var->limit;
2584 s->selector = var->selector;
2585 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2586 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2587 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2588 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2589 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2590 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2591 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2592 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2595 * This is always accurate, except if SYSRET returned to a segment
2596 * with SS.DPL != 3. Intel does not have this quirk, and always
2597 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2598 * would entail passing the CPL to userspace and back.
2600 if (seg == VCPU_SREG_SS)
2601 /* This is symmetric with svm_get_segment() */
2602 svm->vmcb->save.cpl = (var->dpl & 3);
2604 mark_dirty(svm->vmcb, VMCB_SEG);
2607 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2609 struct vcpu_svm *svm = to_svm(vcpu);
2611 clr_exception_intercept(svm, BP_VECTOR);
2613 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2614 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2615 set_exception_intercept(svm, BP_VECTOR);
2617 vcpu->guest_debug = 0;
2620 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2622 if (sd->next_asid > sd->max_asid) {
2623 ++sd->asid_generation;
2624 sd->next_asid = sd->min_asid;
2625 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2628 svm->asid_generation = sd->asid_generation;
2629 svm->vmcb->control.asid = sd->next_asid++;
2631 mark_dirty(svm->vmcb, VMCB_ASID);
2634 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2636 return to_svm(vcpu)->vmcb->save.dr6;
2639 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2641 struct vcpu_svm *svm = to_svm(vcpu);
2643 svm->vmcb->save.dr6 = value;
2644 mark_dirty(svm->vmcb, VMCB_DR);
2647 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2649 struct vcpu_svm *svm = to_svm(vcpu);
2651 get_debugreg(vcpu->arch.db[0], 0);
2652 get_debugreg(vcpu->arch.db[1], 1);
2653 get_debugreg(vcpu->arch.db[2], 2);
2654 get_debugreg(vcpu->arch.db[3], 3);
2655 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2656 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2658 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2659 set_dr_intercepts(svm);
2662 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2664 struct vcpu_svm *svm = to_svm(vcpu);
2666 svm->vmcb->save.dr7 = value;
2667 mark_dirty(svm->vmcb, VMCB_DR);
2670 static int pf_interception(struct vcpu_svm *svm)
2672 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2673 u64 error_code = svm->vmcb->control.exit_info_1;
2675 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2676 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2677 svm->vmcb->control.insn_bytes : NULL,
2678 svm->vmcb->control.insn_len);
2681 static int npf_interception(struct vcpu_svm *svm)
2683 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2684 u64 error_code = svm->vmcb->control.exit_info_1;
2686 trace_kvm_page_fault(fault_address, error_code);
2687 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2688 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2689 svm->vmcb->control.insn_bytes : NULL,
2690 svm->vmcb->control.insn_len);
2693 static int db_interception(struct vcpu_svm *svm)
2695 struct kvm_run *kvm_run = svm->vcpu.run;
2696 struct kvm_vcpu *vcpu = &svm->vcpu;
2698 if (!(svm->vcpu.guest_debug &
2699 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2700 !svm->nmi_singlestep) {
2701 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2705 if (svm->nmi_singlestep) {
2706 disable_nmi_singlestep(svm);
2707 /* Make sure we check for pending NMIs upon entry */
2708 kvm_make_request(KVM_REQ_EVENT, vcpu);
2711 if (svm->vcpu.guest_debug &
2712 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2713 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2714 kvm_run->debug.arch.pc =
2715 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2716 kvm_run->debug.arch.exception = DB_VECTOR;
2723 static int bp_interception(struct vcpu_svm *svm)
2725 struct kvm_run *kvm_run = svm->vcpu.run;
2727 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2728 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2729 kvm_run->debug.arch.exception = BP_VECTOR;
2733 static int ud_interception(struct vcpu_svm *svm)
2735 return handle_ud(&svm->vcpu);
2738 static int ac_interception(struct vcpu_svm *svm)
2740 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2744 static int gp_interception(struct vcpu_svm *svm)
2746 struct kvm_vcpu *vcpu = &svm->vcpu;
2747 u32 error_code = svm->vmcb->control.exit_info_1;
2750 WARN_ON_ONCE(!enable_vmware_backdoor);
2752 er = kvm_emulate_instruction(vcpu,
2753 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2754 if (er == EMULATE_USER_EXIT)
2756 else if (er != EMULATE_DONE)
2757 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2761 static bool is_erratum_383(void)
2766 if (!erratum_383_found)
2769 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2773 /* Bit 62 may or may not be set for this mce */
2774 value &= ~(1ULL << 62);
2776 if (value != 0xb600000000010015ULL)
2779 /* Clear MCi_STATUS registers */
2780 for (i = 0; i < 6; ++i)
2781 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2783 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2787 value &= ~(1ULL << 2);
2788 low = lower_32_bits(value);
2789 high = upper_32_bits(value);
2791 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2794 /* Flush tlb to evict multi-match entries */
2800 static void svm_handle_mce(struct vcpu_svm *svm)
2802 if (is_erratum_383()) {
2804 * Erratum 383 triggered. Guest state is corrupt so kill the
2807 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2809 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2815 * On an #MC intercept the MCE handler is not called automatically in
2816 * the host. So do it by hand here.
2820 /* not sure if we ever come back to this point */
2825 static int mc_interception(struct vcpu_svm *svm)
2830 static int shutdown_interception(struct vcpu_svm *svm)
2832 struct kvm_run *kvm_run = svm->vcpu.run;
2835 * VMCB is undefined after a SHUTDOWN intercept
2836 * so reinitialize it.
2838 clear_page(svm->vmcb);
2841 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2845 static int io_interception(struct vcpu_svm *svm)
2847 struct kvm_vcpu *vcpu = &svm->vcpu;
2848 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2849 int size, in, string;
2852 ++svm->vcpu.stat.io_exits;
2853 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2854 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2856 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2858 port = io_info >> 16;
2859 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2860 svm->next_rip = svm->vmcb->control.exit_info_2;
2862 return kvm_fast_pio(&svm->vcpu, size, port, in);
2865 static int nmi_interception(struct vcpu_svm *svm)
2870 static int intr_interception(struct vcpu_svm *svm)
2872 ++svm->vcpu.stat.irq_exits;
2876 static int nop_on_interception(struct vcpu_svm *svm)
2881 static int halt_interception(struct vcpu_svm *svm)
2883 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2884 return kvm_emulate_halt(&svm->vcpu);
2887 static int vmmcall_interception(struct vcpu_svm *svm)
2889 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2890 return kvm_emulate_hypercall(&svm->vcpu);
2893 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2895 struct vcpu_svm *svm = to_svm(vcpu);
2897 return svm->nested.nested_cr3;
2900 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2902 struct vcpu_svm *svm = to_svm(vcpu);
2903 u64 cr3 = svm->nested.nested_cr3;
2907 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2908 offset_in_page(cr3) + index * 8, 8);
2914 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2917 struct vcpu_svm *svm = to_svm(vcpu);
2919 svm->vmcb->control.nested_cr3 = __sme_set(root);
2920 mark_dirty(svm->vmcb, VMCB_NPT);
2923 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2924 struct x86_exception *fault)
2926 struct vcpu_svm *svm = to_svm(vcpu);
2928 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2930 * TODO: track the cause of the nested page fault, and
2931 * correctly fill in the high bits of exit_info_1.
2933 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2934 svm->vmcb->control.exit_code_hi = 0;
2935 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2936 svm->vmcb->control.exit_info_2 = fault->address;
2939 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2940 svm->vmcb->control.exit_info_1 |= fault->error_code;
2943 * The present bit is always zero for page structure faults on real
2946 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2947 svm->vmcb->control.exit_info_1 &= ~1;
2949 nested_svm_vmexit(svm);
2952 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2954 WARN_ON(mmu_is_nested(vcpu));
2956 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2957 kvm_init_shadow_mmu(vcpu);
2958 vcpu->arch.mmu->set_cr3 = nested_svm_set_tdp_cr3;
2959 vcpu->arch.mmu->get_cr3 = nested_svm_get_tdp_cr3;
2960 vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
2961 vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2962 vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2963 reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2964 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2967 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2969 vcpu->arch.mmu = &vcpu->arch.root_mmu;
2970 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2973 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2975 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2976 !is_paging(&svm->vcpu)) {
2977 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2981 if (svm->vmcb->save.cpl) {
2982 kvm_inject_gp(&svm->vcpu, 0);
2989 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2990 bool has_error_code, u32 error_code)
2994 if (!is_guest_mode(&svm->vcpu))
2997 vmexit = nested_svm_intercept(svm);
2998 if (vmexit != NESTED_EXIT_DONE)
3001 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
3002 svm->vmcb->control.exit_code_hi = 0;
3003 svm->vmcb->control.exit_info_1 = error_code;
3006 * EXITINFO2 is undefined for all exception intercepts other
3009 if (svm->vcpu.arch.exception.nested_apf)
3010 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3011 else if (svm->vcpu.arch.exception.has_payload)
3012 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3014 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3016 svm->nested.exit_required = true;
3020 /* This function returns true if it is save to enable the irq window */
3021 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3023 if (!is_guest_mode(&svm->vcpu))
3026 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3029 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3033 * if vmexit was already requested (by intercepted exception
3034 * for instance) do not overwrite it with "external interrupt"
3037 if (svm->nested.exit_required)
3040 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
3041 svm->vmcb->control.exit_info_1 = 0;
3042 svm->vmcb->control.exit_info_2 = 0;
3044 if (svm->nested.intercept & 1ULL) {
3046 * The #vmexit can't be emulated here directly because this
3047 * code path runs with irqs and preemption disabled. A
3048 * #vmexit emulation might sleep. Only signal request for
3051 svm->nested.exit_required = true;
3052 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3059 /* This function returns true if it is save to enable the nmi window */
3060 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3062 if (!is_guest_mode(&svm->vcpu))
3065 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3068 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3069 svm->nested.exit_required = true;
3074 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3076 unsigned port, size, iopm_len;
3081 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3082 return NESTED_EXIT_HOST;
3084 port = svm->vmcb->control.exit_info_1 >> 16;
3085 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3086 SVM_IOIO_SIZE_SHIFT;
3087 gpa = svm->nested.vmcb_iopm + (port / 8);
3088 start_bit = port % 8;
3089 iopm_len = (start_bit + size > 8) ? 2 : 1;
3090 mask = (0xf >> (4 - size)) << start_bit;
3093 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3094 return NESTED_EXIT_DONE;
3096 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3099 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3101 u32 offset, msr, value;
3104 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3105 return NESTED_EXIT_HOST;
3107 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3108 offset = svm_msrpm_offset(msr);
3109 write = svm->vmcb->control.exit_info_1 & 1;
3110 mask = 1 << ((2 * (msr & 0xf)) + write);
3112 if (offset == MSR_INVALID)
3113 return NESTED_EXIT_DONE;
3115 /* Offset is in 32 bit units but need in 8 bit units */
3118 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3119 return NESTED_EXIT_DONE;
3121 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3124 /* DB exceptions for our internal use must not cause vmexit */
3125 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3129 /* if we're not singlestepping, it's not ours */
3130 if (!svm->nmi_singlestep)
3131 return NESTED_EXIT_DONE;
3133 /* if it's not a singlestep exception, it's not ours */
3134 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3135 return NESTED_EXIT_DONE;
3136 if (!(dr6 & DR6_BS))
3137 return NESTED_EXIT_DONE;
3139 /* if the guest is singlestepping, it should get the vmexit */
3140 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3141 disable_nmi_singlestep(svm);
3142 return NESTED_EXIT_DONE;
3145 /* it's ours, the nested hypervisor must not see this one */
3146 return NESTED_EXIT_HOST;
3149 static int nested_svm_exit_special(struct vcpu_svm *svm)
3151 u32 exit_code = svm->vmcb->control.exit_code;
3153 switch (exit_code) {
3156 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3157 return NESTED_EXIT_HOST;
3159 /* For now we are always handling NPFs when using them */
3161 return NESTED_EXIT_HOST;
3163 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3164 /* When we're shadowing, trap PFs, but not async PF */
3165 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3166 return NESTED_EXIT_HOST;
3172 return NESTED_EXIT_CONTINUE;
3176 * If this function returns true, this #vmexit was already handled
3178 static int nested_svm_intercept(struct vcpu_svm *svm)
3180 u32 exit_code = svm->vmcb->control.exit_code;
3181 int vmexit = NESTED_EXIT_HOST;
3183 switch (exit_code) {
3185 vmexit = nested_svm_exit_handled_msr(svm);
3188 vmexit = nested_svm_intercept_ioio(svm);
3190 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3191 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3192 if (svm->nested.intercept_cr & bit)
3193 vmexit = NESTED_EXIT_DONE;
3196 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3197 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3198 if (svm->nested.intercept_dr & bit)
3199 vmexit = NESTED_EXIT_DONE;
3202 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3203 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3204 if (svm->nested.intercept_exceptions & excp_bits) {
3205 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3206 vmexit = nested_svm_intercept_db(svm);
3208 vmexit = NESTED_EXIT_DONE;
3210 /* async page fault always cause vmexit */
3211 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3212 svm->vcpu.arch.exception.nested_apf != 0)
3213 vmexit = NESTED_EXIT_DONE;
3216 case SVM_EXIT_ERR: {
3217 vmexit = NESTED_EXIT_DONE;
3221 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3222 if (svm->nested.intercept & exit_bits)
3223 vmexit = NESTED_EXIT_DONE;
3230 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3234 vmexit = nested_svm_intercept(svm);
3236 if (vmexit == NESTED_EXIT_DONE)
3237 nested_svm_vmexit(svm);
3242 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3244 struct vmcb_control_area *dst = &dst_vmcb->control;
3245 struct vmcb_control_area *from = &from_vmcb->control;
3247 dst->intercept_cr = from->intercept_cr;
3248 dst->intercept_dr = from->intercept_dr;
3249 dst->intercept_exceptions = from->intercept_exceptions;
3250 dst->intercept = from->intercept;
3251 dst->iopm_base_pa = from->iopm_base_pa;
3252 dst->msrpm_base_pa = from->msrpm_base_pa;
3253 dst->tsc_offset = from->tsc_offset;
3254 dst->asid = from->asid;
3255 dst->tlb_ctl = from->tlb_ctl;
3256 dst->int_ctl = from->int_ctl;
3257 dst->int_vector = from->int_vector;
3258 dst->int_state = from->int_state;
3259 dst->exit_code = from->exit_code;
3260 dst->exit_code_hi = from->exit_code_hi;
3261 dst->exit_info_1 = from->exit_info_1;
3262 dst->exit_info_2 = from->exit_info_2;
3263 dst->exit_int_info = from->exit_int_info;
3264 dst->exit_int_info_err = from->exit_int_info_err;
3265 dst->nested_ctl = from->nested_ctl;
3266 dst->event_inj = from->event_inj;
3267 dst->event_inj_err = from->event_inj_err;
3268 dst->nested_cr3 = from->nested_cr3;
3269 dst->virt_ext = from->virt_ext;
3270 dst->pause_filter_count = from->pause_filter_count;
3271 dst->pause_filter_thresh = from->pause_filter_thresh;
3274 static int nested_svm_vmexit(struct vcpu_svm *svm)
3277 struct vmcb *nested_vmcb;
3278 struct vmcb *hsave = svm->nested.hsave;
3279 struct vmcb *vmcb = svm->vmcb;
3280 struct kvm_host_map map;
3282 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3283 vmcb->control.exit_info_1,
3284 vmcb->control.exit_info_2,
3285 vmcb->control.exit_int_info,
3286 vmcb->control.exit_int_info_err,
3289 rc = kvm_vcpu_map(&svm->vcpu, gfn_to_gpa(svm->nested.vmcb), &map);
3292 kvm_inject_gp(&svm->vcpu, 0);
3296 nested_vmcb = map.hva;
3298 /* Exit Guest-Mode */
3299 leave_guest_mode(&svm->vcpu);
3300 svm->nested.vmcb = 0;
3302 /* Give the current vmcb to the guest */
3305 nested_vmcb->save.es = vmcb->save.es;
3306 nested_vmcb->save.cs = vmcb->save.cs;
3307 nested_vmcb->save.ss = vmcb->save.ss;
3308 nested_vmcb->save.ds = vmcb->save.ds;
3309 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3310 nested_vmcb->save.idtr = vmcb->save.idtr;
3311 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3312 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3313 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3314 nested_vmcb->save.cr2 = vmcb->save.cr2;
3315 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3316 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3317 nested_vmcb->save.rip = vmcb->save.rip;
3318 nested_vmcb->save.rsp = vmcb->save.rsp;
3319 nested_vmcb->save.rax = vmcb->save.rax;
3320 nested_vmcb->save.dr7 = vmcb->save.dr7;
3321 nested_vmcb->save.dr6 = vmcb->save.dr6;
3322 nested_vmcb->save.cpl = vmcb->save.cpl;
3324 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3325 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3326 nested_vmcb->control.int_state = vmcb->control.int_state;
3327 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3328 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3329 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3330 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3331 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3332 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3334 if (svm->nrips_enabled)
3335 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3338 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3339 * to make sure that we do not lose injected events. So check event_inj
3340 * here and copy it to exit_int_info if it is valid.
3341 * Exit_int_info and event_inj can't be both valid because the case
3342 * below only happens on a VMRUN instruction intercept which has
3343 * no valid exit_int_info set.
3345 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3346 struct vmcb_control_area *nc = &nested_vmcb->control;
3348 nc->exit_int_info = vmcb->control.event_inj;
3349 nc->exit_int_info_err = vmcb->control.event_inj_err;
3352 nested_vmcb->control.tlb_ctl = 0;
3353 nested_vmcb->control.event_inj = 0;
3354 nested_vmcb->control.event_inj_err = 0;
3356 nested_vmcb->control.pause_filter_count =
3357 svm->vmcb->control.pause_filter_count;
3358 nested_vmcb->control.pause_filter_thresh =
3359 svm->vmcb->control.pause_filter_thresh;
3361 /* We always set V_INTR_MASKING and remember the old value in hflags */
3362 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3363 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3365 /* Restore the original control entries */
3366 copy_vmcb_control_area(vmcb, hsave);
3368 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3369 kvm_clear_exception_queue(&svm->vcpu);
3370 kvm_clear_interrupt_queue(&svm->vcpu);
3372 svm->nested.nested_cr3 = 0;
3374 /* Restore selected save entries */
3375 svm->vmcb->save.es = hsave->save.es;
3376 svm->vmcb->save.cs = hsave->save.cs;
3377 svm->vmcb->save.ss = hsave->save.ss;
3378 svm->vmcb->save.ds = hsave->save.ds;
3379 svm->vmcb->save.gdtr = hsave->save.gdtr;
3380 svm->vmcb->save.idtr = hsave->save.idtr;
3381 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3382 svm_set_efer(&svm->vcpu, hsave->save.efer);
3383 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3384 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3386 svm->vmcb->save.cr3 = hsave->save.cr3;
3387 svm->vcpu.arch.cr3 = hsave->save.cr3;
3389 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3391 kvm_rax_write(&svm->vcpu, hsave->save.rax);
3392 kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
3393 kvm_rip_write(&svm->vcpu, hsave->save.rip);
3394 svm->vmcb->save.dr7 = 0;
3395 svm->vmcb->save.cpl = 0;
3396 svm->vmcb->control.exit_int_info = 0;
3398 mark_all_dirty(svm->vmcb);
3400 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3402 nested_svm_uninit_mmu_context(&svm->vcpu);
3403 kvm_mmu_reset_context(&svm->vcpu);
3404 kvm_mmu_load(&svm->vcpu);
3407 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3408 * doesn't end up in L1.
3410 svm->vcpu.arch.nmi_injected = false;
3411 kvm_clear_exception_queue(&svm->vcpu);
3412 kvm_clear_interrupt_queue(&svm->vcpu);
3417 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3420 * This function merges the msr permission bitmaps of kvm and the
3421 * nested vmcb. It is optimized in that it only merges the parts where
3422 * the kvm msr permission bitmap may contain zero bits
3426 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3429 for (i = 0; i < MSRPM_OFFSETS; i++) {
3433 if (msrpm_offsets[i] == 0xffffffff)
3436 p = msrpm_offsets[i];
3437 offset = svm->nested.vmcb_msrpm + (p * 4);
3439 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3442 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3445 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3450 static bool nested_vmcb_checks(struct vmcb *vmcb)
3452 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3455 if (vmcb->control.asid == 0)
3458 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3465 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3466 struct vmcb *nested_vmcb, struct kvm_host_map *map)
3468 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3469 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3471 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3473 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3474 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3475 nested_svm_init_mmu_context(&svm->vcpu);
3478 /* Load the nested guest state */
3479 svm->vmcb->save.es = nested_vmcb->save.es;
3480 svm->vmcb->save.cs = nested_vmcb->save.cs;
3481 svm->vmcb->save.ss = nested_vmcb->save.ss;
3482 svm->vmcb->save.ds = nested_vmcb->save.ds;
3483 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3484 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3485 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3486 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3487 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3488 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3490 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3491 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3493 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3495 /* Guest paging mode is active - reset mmu */
3496 kvm_mmu_reset_context(&svm->vcpu);
3498 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3499 kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
3500 kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
3501 kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
3503 /* In case we don't even reach vcpu_run, the fields are not updated */
3504 svm->vmcb->save.rax = nested_vmcb->save.rax;
3505 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3506 svm->vmcb->save.rip = nested_vmcb->save.rip;
3507 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3508 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3509 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3511 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3512 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3514 /* cache intercepts */
3515 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3516 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3517 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3518 svm->nested.intercept = nested_vmcb->control.intercept;
3520 svm_flush_tlb(&svm->vcpu, true);
3521 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3522 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3523 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3525 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3527 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3528 /* We only want the cr8 intercept bits of the guest */
3529 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3530 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3533 /* We don't want to see VMMCALLs from a nested guest */
3534 clr_intercept(svm, INTERCEPT_VMMCALL);
3536 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3537 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3539 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3540 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3541 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3542 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3543 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3545 svm->vmcb->control.pause_filter_count =
3546 nested_vmcb->control.pause_filter_count;
3547 svm->vmcb->control.pause_filter_thresh =
3548 nested_vmcb->control.pause_filter_thresh;
3550 kvm_vcpu_unmap(&svm->vcpu, map, true);
3552 /* Enter Guest-Mode */
3553 enter_guest_mode(&svm->vcpu);
3556 * Merge guest and host intercepts - must be called with vcpu in
3557 * guest-mode to take affect here
3559 recalc_intercepts(svm);
3561 svm->nested.vmcb = vmcb_gpa;
3565 mark_all_dirty(svm->vmcb);
3568 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3571 struct vmcb *nested_vmcb;
3572 struct vmcb *hsave = svm->nested.hsave;
3573 struct vmcb *vmcb = svm->vmcb;
3574 struct kvm_host_map map;
3577 vmcb_gpa = svm->vmcb->save.rax;
3579 rc = kvm_vcpu_map(&svm->vcpu, gfn_to_gpa(vmcb_gpa), &map);
3582 kvm_inject_gp(&svm->vcpu, 0);
3586 nested_vmcb = map.hva;
3588 if (!nested_vmcb_checks(nested_vmcb)) {
3589 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3590 nested_vmcb->control.exit_code_hi = 0;
3591 nested_vmcb->control.exit_info_1 = 0;
3592 nested_vmcb->control.exit_info_2 = 0;
3594 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3599 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3600 nested_vmcb->save.rip,
3601 nested_vmcb->control.int_ctl,
3602 nested_vmcb->control.event_inj,
3603 nested_vmcb->control.nested_ctl);
3605 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3606 nested_vmcb->control.intercept_cr >> 16,
3607 nested_vmcb->control.intercept_exceptions,
3608 nested_vmcb->control.intercept);
3610 /* Clear internal status */
3611 kvm_clear_exception_queue(&svm->vcpu);
3612 kvm_clear_interrupt_queue(&svm->vcpu);
3615 * Save the old vmcb, so we don't need to pick what we save, but can
3616 * restore everything when a VMEXIT occurs
3618 hsave->save.es = vmcb->save.es;
3619 hsave->save.cs = vmcb->save.cs;
3620 hsave->save.ss = vmcb->save.ss;
3621 hsave->save.ds = vmcb->save.ds;
3622 hsave->save.gdtr = vmcb->save.gdtr;
3623 hsave->save.idtr = vmcb->save.idtr;
3624 hsave->save.efer = svm->vcpu.arch.efer;
3625 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3626 hsave->save.cr4 = svm->vcpu.arch.cr4;
3627 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3628 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3629 hsave->save.rsp = vmcb->save.rsp;
3630 hsave->save.rax = vmcb->save.rax;
3632 hsave->save.cr3 = vmcb->save.cr3;
3634 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3636 copy_vmcb_control_area(hsave, vmcb);
3638 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
3643 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3645 to_vmcb->save.fs = from_vmcb->save.fs;
3646 to_vmcb->save.gs = from_vmcb->save.gs;
3647 to_vmcb->save.tr = from_vmcb->save.tr;
3648 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3649 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3650 to_vmcb->save.star = from_vmcb->save.star;
3651 to_vmcb->save.lstar = from_vmcb->save.lstar;
3652 to_vmcb->save.cstar = from_vmcb->save.cstar;
3653 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3654 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3655 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3656 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3659 static int vmload_interception(struct vcpu_svm *svm)
3661 struct vmcb *nested_vmcb;
3662 struct kvm_host_map map;
3665 if (nested_svm_check_permissions(svm))
3668 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3671 kvm_inject_gp(&svm->vcpu, 0);
3675 nested_vmcb = map.hva;
3677 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3678 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3680 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3681 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3686 static int vmsave_interception(struct vcpu_svm *svm)
3688 struct vmcb *nested_vmcb;
3689 struct kvm_host_map map;
3692 if (nested_svm_check_permissions(svm))
3695 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
3698 kvm_inject_gp(&svm->vcpu, 0);
3702 nested_vmcb = map.hva;
3704 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3705 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3707 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3708 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3713 static int vmrun_interception(struct vcpu_svm *svm)
3715 if (nested_svm_check_permissions(svm))
3718 /* Save rip after vmrun instruction */
3719 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3721 if (!nested_svm_vmrun(svm))
3724 if (!nested_svm_vmrun_msrpm(svm))
3731 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3732 svm->vmcb->control.exit_code_hi = 0;
3733 svm->vmcb->control.exit_info_1 = 0;
3734 svm->vmcb->control.exit_info_2 = 0;
3736 nested_svm_vmexit(svm);
3741 static int stgi_interception(struct vcpu_svm *svm)
3745 if (nested_svm_check_permissions(svm))
3749 * If VGIF is enabled, the STGI intercept is only added to
3750 * detect the opening of the SMI/NMI window; remove it now.
3752 if (vgif_enabled(svm))
3753 clr_intercept(svm, INTERCEPT_STGI);
3755 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3756 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3757 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3764 static int clgi_interception(struct vcpu_svm *svm)
3768 if (nested_svm_check_permissions(svm))
3771 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3772 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3776 /* After a CLGI no interrupts should come */
3777 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3778 svm_clear_vintr(svm);
3779 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3780 mark_dirty(svm->vmcb, VMCB_INTR);
3786 static int invlpga_interception(struct vcpu_svm *svm)
3788 struct kvm_vcpu *vcpu = &svm->vcpu;
3790 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
3791 kvm_rax_read(&svm->vcpu));
3793 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3794 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
3796 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3797 return kvm_skip_emulated_instruction(&svm->vcpu);
3800 static int skinit_interception(struct vcpu_svm *svm)
3802 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
3804 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3808 static int wbinvd_interception(struct vcpu_svm *svm)
3810 return kvm_emulate_wbinvd(&svm->vcpu);
3813 static int xsetbv_interception(struct vcpu_svm *svm)
3815 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3816 u32 index = kvm_rcx_read(&svm->vcpu);
3818 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3819 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3820 return kvm_skip_emulated_instruction(&svm->vcpu);
3826 static int task_switch_interception(struct vcpu_svm *svm)
3830 int int_type = svm->vmcb->control.exit_int_info &
3831 SVM_EXITINTINFO_TYPE_MASK;
3832 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3834 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3836 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3837 bool has_error_code = false;
3840 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3842 if (svm->vmcb->control.exit_info_2 &
3843 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3844 reason = TASK_SWITCH_IRET;
3845 else if (svm->vmcb->control.exit_info_2 &
3846 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3847 reason = TASK_SWITCH_JMP;
3849 reason = TASK_SWITCH_GATE;
3851 reason = TASK_SWITCH_CALL;
3853 if (reason == TASK_SWITCH_GATE) {
3855 case SVM_EXITINTINFO_TYPE_NMI:
3856 svm->vcpu.arch.nmi_injected = false;
3858 case SVM_EXITINTINFO_TYPE_EXEPT:
3859 if (svm->vmcb->control.exit_info_2 &
3860 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3861 has_error_code = true;
3863 (u32)svm->vmcb->control.exit_info_2;
3865 kvm_clear_exception_queue(&svm->vcpu);
3867 case SVM_EXITINTINFO_TYPE_INTR:
3868 kvm_clear_interrupt_queue(&svm->vcpu);
3875 if (reason != TASK_SWITCH_GATE ||
3876 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3877 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3878 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3879 skip_emulated_instruction(&svm->vcpu);
3881 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3884 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3885 has_error_code, error_code) == EMULATE_FAIL) {
3886 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3887 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3888 svm->vcpu.run->internal.ndata = 0;
3894 static int cpuid_interception(struct vcpu_svm *svm)
3896 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3897 return kvm_emulate_cpuid(&svm->vcpu);
3900 static int iret_interception(struct vcpu_svm *svm)
3902 ++svm->vcpu.stat.nmi_window_exits;
3903 clr_intercept(svm, INTERCEPT_IRET);
3904 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3905 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3906 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3910 static int invlpg_interception(struct vcpu_svm *svm)
3912 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3913 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3915 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3916 return kvm_skip_emulated_instruction(&svm->vcpu);
3919 static int emulate_on_interception(struct vcpu_svm *svm)
3921 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3924 static int rsm_interception(struct vcpu_svm *svm)
3926 return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3927 rsm_ins_bytes, 2) == EMULATE_DONE;
3930 static int rdpmc_interception(struct vcpu_svm *svm)
3934 if (!static_cpu_has(X86_FEATURE_NRIPS))
3935 return emulate_on_interception(svm);
3937 err = kvm_rdpmc(&svm->vcpu);
3938 return kvm_complete_insn_gp(&svm->vcpu, err);
3941 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3944 unsigned long cr0 = svm->vcpu.arch.cr0;
3948 intercept = svm->nested.intercept;
3950 if (!is_guest_mode(&svm->vcpu) ||
3951 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3954 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3955 val &= ~SVM_CR0_SELECTIVE_MASK;
3958 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3959 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3965 #define CR_VALID (1ULL << 63)
3967 static int cr_interception(struct vcpu_svm *svm)
3973 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3974 return emulate_on_interception(svm);
3976 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3977 return emulate_on_interception(svm);
3979 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3980 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3981 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3983 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3986 if (cr >= 16) { /* mov to cr */
3988 val = kvm_register_read(&svm->vcpu, reg);
3991 if (!check_selective_cr0_intercepted(svm, val))
3992 err = kvm_set_cr0(&svm->vcpu, val);
3998 err = kvm_set_cr3(&svm->vcpu, val);
4001 err = kvm_set_cr4(&svm->vcpu, val);
4004 err = kvm_set_cr8(&svm->vcpu, val);
4007 WARN(1, "unhandled write to CR%d", cr);
4008 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4011 } else { /* mov from cr */
4014 val = kvm_read_cr0(&svm->vcpu);
4017 val = svm->vcpu.arch.cr2;
4020 val = kvm_read_cr3(&svm->vcpu);
4023 val = kvm_read_cr4(&svm->vcpu);
4026 val = kvm_get_cr8(&svm->vcpu);
4029 WARN(1, "unhandled read from CR%d", cr);
4030 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4033 kvm_register_write(&svm->vcpu, reg, val);
4035 return kvm_complete_insn_gp(&svm->vcpu, err);
4038 static int dr_interception(struct vcpu_svm *svm)
4043 if (svm->vcpu.guest_debug == 0) {
4045 * No more DR vmexits; force a reload of the debug registers
4046 * and reenter on this instruction. The next vmexit will
4047 * retrieve the full state of the debug registers.
4049 clr_dr_intercepts(svm);
4050 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4054 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4055 return emulate_on_interception(svm);
4057 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4058 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4060 if (dr >= 16) { /* mov to DRn */
4061 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4063 val = kvm_register_read(&svm->vcpu, reg);
4064 kvm_set_dr(&svm->vcpu, dr - 16, val);
4066 if (!kvm_require_dr(&svm->vcpu, dr))
4068 kvm_get_dr(&svm->vcpu, dr, &val);
4069 kvm_register_write(&svm->vcpu, reg, val);
4072 return kvm_skip_emulated_instruction(&svm->vcpu);
4075 static int cr8_write_interception(struct vcpu_svm *svm)
4077 struct kvm_run *kvm_run = svm->vcpu.run;
4080 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4081 /* instruction emulation calls kvm_set_cr8() */
4082 r = cr_interception(svm);
4083 if (lapic_in_kernel(&svm->vcpu))
4085 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4087 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4091 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4095 switch (msr->index) {
4096 case MSR_F10H_DECFG:
4097 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4098 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4107 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4109 struct vcpu_svm *svm = to_svm(vcpu);
4111 switch (msr_info->index) {
4113 msr_info->data = svm->vmcb->save.star;
4115 #ifdef CONFIG_X86_64
4117 msr_info->data = svm->vmcb->save.lstar;
4120 msr_info->data = svm->vmcb->save.cstar;
4122 case MSR_KERNEL_GS_BASE:
4123 msr_info->data = svm->vmcb->save.kernel_gs_base;
4125 case MSR_SYSCALL_MASK:
4126 msr_info->data = svm->vmcb->save.sfmask;
4129 case MSR_IA32_SYSENTER_CS:
4130 msr_info->data = svm->vmcb->save.sysenter_cs;
4132 case MSR_IA32_SYSENTER_EIP:
4133 msr_info->data = svm->sysenter_eip;
4135 case MSR_IA32_SYSENTER_ESP:
4136 msr_info->data = svm->sysenter_esp;
4139 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4141 msr_info->data = svm->tsc_aux;
4144 * Nobody will change the following 5 values in the VMCB so we can
4145 * safely return them on rdmsr. They will always be 0 until LBRV is
4148 case MSR_IA32_DEBUGCTLMSR:
4149 msr_info->data = svm->vmcb->save.dbgctl;
4151 case MSR_IA32_LASTBRANCHFROMIP:
4152 msr_info->data = svm->vmcb->save.br_from;
4154 case MSR_IA32_LASTBRANCHTOIP:
4155 msr_info->data = svm->vmcb->save.br_to;
4157 case MSR_IA32_LASTINTFROMIP:
4158 msr_info->data = svm->vmcb->save.last_excp_from;
4160 case MSR_IA32_LASTINTTOIP:
4161 msr_info->data = svm->vmcb->save.last_excp_to;
4163 case MSR_VM_HSAVE_PA:
4164 msr_info->data = svm->nested.hsave_msr;
4167 msr_info->data = svm->nested.vm_cr_msr;
4169 case MSR_IA32_SPEC_CTRL:
4170 if (!msr_info->host_initiated &&
4171 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4172 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4175 msr_info->data = svm->spec_ctrl;
4177 case MSR_AMD64_VIRT_SPEC_CTRL:
4178 if (!msr_info->host_initiated &&
4179 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4182 msr_info->data = svm->virt_spec_ctrl;
4184 case MSR_F15H_IC_CFG: {
4188 family = guest_cpuid_family(vcpu);
4189 model = guest_cpuid_model(vcpu);
4191 if (family < 0 || model < 0)
4192 return kvm_get_msr_common(vcpu, msr_info);
4196 if (family == 0x15 &&
4197 (model >= 0x2 && model < 0x20))
4198 msr_info->data = 0x1E;
4201 case MSR_F10H_DECFG:
4202 msr_info->data = svm->msr_decfg;
4205 return kvm_get_msr_common(vcpu, msr_info);
4210 static int rdmsr_interception(struct vcpu_svm *svm)
4212 u32 ecx = kvm_rcx_read(&svm->vcpu);
4213 struct msr_data msr_info;
4215 msr_info.index = ecx;
4216 msr_info.host_initiated = false;
4217 if (svm_get_msr(&svm->vcpu, &msr_info)) {
4218 trace_kvm_msr_read_ex(ecx);
4219 kvm_inject_gp(&svm->vcpu, 0);
4222 trace_kvm_msr_read(ecx, msr_info.data);
4224 kvm_rax_write(&svm->vcpu, msr_info.data & 0xffffffff);
4225 kvm_rdx_write(&svm->vcpu, msr_info.data >> 32);
4226 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4227 return kvm_skip_emulated_instruction(&svm->vcpu);
4231 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4233 struct vcpu_svm *svm = to_svm(vcpu);
4234 int svm_dis, chg_mask;
4236 if (data & ~SVM_VM_CR_VALID_MASK)
4239 chg_mask = SVM_VM_CR_VALID_MASK;
4241 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4242 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4244 svm->nested.vm_cr_msr &= ~chg_mask;
4245 svm->nested.vm_cr_msr |= (data & chg_mask);
4247 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4249 /* check for svm_disable while efer.svme is set */
4250 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4256 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4258 struct vcpu_svm *svm = to_svm(vcpu);
4260 u32 ecx = msr->index;
4261 u64 data = msr->data;
4263 case MSR_IA32_CR_PAT:
4264 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4266 vcpu->arch.pat = data;
4267 svm->vmcb->save.g_pat = data;
4268 mark_dirty(svm->vmcb, VMCB_NPT);
4270 case MSR_IA32_SPEC_CTRL:
4271 if (!msr->host_initiated &&
4272 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4273 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4276 /* The STIBP bit doesn't fault even if it's not advertised */
4277 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4280 svm->spec_ctrl = data;
4287 * When it's written (to non-zero) for the first time, pass
4291 * The handling of the MSR bitmap for L2 guests is done in
4292 * nested_svm_vmrun_msrpm.
4293 * We update the L1 MSR bit as well since it will end up
4294 * touching the MSR anyway now.
4296 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4298 case MSR_IA32_PRED_CMD:
4299 if (!msr->host_initiated &&
4300 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4303 if (data & ~PRED_CMD_IBPB)
4309 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4310 if (is_guest_mode(vcpu))
4312 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4314 case MSR_AMD64_VIRT_SPEC_CTRL:
4315 if (!msr->host_initiated &&
4316 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4319 if (data & ~SPEC_CTRL_SSBD)
4322 svm->virt_spec_ctrl = data;
4325 svm->vmcb->save.star = data;
4327 #ifdef CONFIG_X86_64
4329 svm->vmcb->save.lstar = data;
4332 svm->vmcb->save.cstar = data;
4334 case MSR_KERNEL_GS_BASE:
4335 svm->vmcb->save.kernel_gs_base = data;
4337 case MSR_SYSCALL_MASK:
4338 svm->vmcb->save.sfmask = data;
4341 case MSR_IA32_SYSENTER_CS:
4342 svm->vmcb->save.sysenter_cs = data;
4344 case MSR_IA32_SYSENTER_EIP:
4345 svm->sysenter_eip = data;
4346 svm->vmcb->save.sysenter_eip = data;
4348 case MSR_IA32_SYSENTER_ESP:
4349 svm->sysenter_esp = data;
4350 svm->vmcb->save.sysenter_esp = data;
4353 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4357 * This is rare, so we update the MSR here instead of using
4358 * direct_access_msrs. Doing that would require a rdmsr in
4361 svm->tsc_aux = data;
4362 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4364 case MSR_IA32_DEBUGCTLMSR:
4365 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4366 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4370 if (data & DEBUGCTL_RESERVED_BITS)
4373 svm->vmcb->save.dbgctl = data;
4374 mark_dirty(svm->vmcb, VMCB_LBR);
4375 if (data & (1ULL<<0))
4376 svm_enable_lbrv(svm);
4378 svm_disable_lbrv(svm);
4380 case MSR_VM_HSAVE_PA:
4381 svm->nested.hsave_msr = data;
4384 return svm_set_vm_cr(vcpu, data);
4386 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4388 case MSR_F10H_DECFG: {
4389 struct kvm_msr_entry msr_entry;
4391 msr_entry.index = msr->index;
4392 if (svm_get_msr_feature(&msr_entry))
4395 /* Check the supported bits */
4396 if (data & ~msr_entry.data)
4399 /* Don't allow the guest to change a bit, #GP */
4400 if (!msr->host_initiated && (data ^ msr_entry.data))
4403 svm->msr_decfg = data;
4406 case MSR_IA32_APICBASE:
4407 if (kvm_vcpu_apicv_active(vcpu))
4408 avic_update_vapic_bar(to_svm(vcpu), data);
4411 return kvm_set_msr_common(vcpu, msr);
4416 static int wrmsr_interception(struct vcpu_svm *svm)
4418 struct msr_data msr;
4419 u32 ecx = kvm_rcx_read(&svm->vcpu);
4420 u64 data = kvm_read_edx_eax(&svm->vcpu);
4424 msr.host_initiated = false;
4426 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4427 if (kvm_set_msr(&svm->vcpu, &msr)) {
4428 trace_kvm_msr_write_ex(ecx, data);
4429 kvm_inject_gp(&svm->vcpu, 0);
4432 trace_kvm_msr_write(ecx, data);
4433 return kvm_skip_emulated_instruction(&svm->vcpu);
4437 static int msr_interception(struct vcpu_svm *svm)
4439 if (svm->vmcb->control.exit_info_1)
4440 return wrmsr_interception(svm);
4442 return rdmsr_interception(svm);
4445 static int interrupt_window_interception(struct vcpu_svm *svm)
4447 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4448 svm_clear_vintr(svm);
4449 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4450 mark_dirty(svm->vmcb, VMCB_INTR);
4451 ++svm->vcpu.stat.irq_window_exits;
4455 static int pause_interception(struct vcpu_svm *svm)
4457 struct kvm_vcpu *vcpu = &svm->vcpu;
4458 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4460 if (pause_filter_thresh)
4461 grow_ple_window(vcpu);
4463 kvm_vcpu_on_spin(vcpu, in_kernel);
4467 static int nop_interception(struct vcpu_svm *svm)
4469 return kvm_skip_emulated_instruction(&(svm->vcpu));
4472 static int monitor_interception(struct vcpu_svm *svm)
4474 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4475 return nop_interception(svm);
4478 static int mwait_interception(struct vcpu_svm *svm)
4480 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4481 return nop_interception(svm);
4484 enum avic_ipi_failure_cause {
4485 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4486 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4487 AVIC_IPI_FAILURE_INVALID_TARGET,
4488 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4491 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4493 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4494 u32 icrl = svm->vmcb->control.exit_info_1;
4495 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4496 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4497 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4499 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4502 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4504 * AVIC hardware handles the generation of
4505 * IPIs when the specified Message Type is Fixed
4506 * (also known as fixed delivery mode) and
4507 * the Trigger Mode is edge-triggered. The hardware
4508 * also supports self and broadcast delivery modes
4509 * specified via the Destination Shorthand(DSH)
4510 * field of the ICRL. Logical and physical APIC ID
4511 * formats are supported. All other IPI types cause
4512 * a #VMEXIT, which needs to emulated.
4514 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4515 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4517 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4519 struct kvm_vcpu *vcpu;
4520 struct kvm *kvm = svm->vcpu.kvm;
4521 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4524 * At this point, we expect that the AVIC HW has already
4525 * set the appropriate IRR bits on the valid target
4526 * vcpus. So, we just need to kick the appropriate vcpu.
4528 kvm_for_each_vcpu(i, vcpu, kvm) {
4529 bool m = kvm_apic_match_dest(vcpu, apic,
4530 icrl & KVM_APIC_SHORT_MASK,
4531 GET_APIC_DEST_FIELD(icrh),
4532 icrl & KVM_APIC_DEST_MASK);
4534 if (m && !avic_vcpu_is_running(vcpu))
4535 kvm_vcpu_wake_up(vcpu);
4539 case AVIC_IPI_FAILURE_INVALID_TARGET:
4540 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4541 index, svm->vcpu.vcpu_id, icrh, icrl);
4543 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4544 WARN_ONCE(1, "Invalid backing page\n");
4547 pr_err("Unknown IPI interception\n");
4553 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4555 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4557 u32 *logical_apic_id_table;
4558 int dlid = GET_APIC_LOGICAL_ID(ldr);
4563 if (flat) { /* flat */
4564 index = ffs(dlid) - 1;
4567 } else { /* cluster */
4568 int cluster = (dlid & 0xf0) >> 4;
4569 int apic = ffs(dlid & 0x0f) - 1;
4571 if ((apic < 0) || (apic > 7) ||
4574 index = (cluster << 2) + apic;
4577 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4579 return &logical_apic_id_table[index];
4582 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
4585 u32 *entry, new_entry;
4587 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4588 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4592 new_entry = READ_ONCE(*entry);
4593 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4594 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4595 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4596 WRITE_ONCE(*entry, new_entry);
4601 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
4603 struct vcpu_svm *svm = to_svm(vcpu);
4604 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
4605 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
4608 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
4611 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4614 struct vcpu_svm *svm = to_svm(vcpu);
4615 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4617 if (ldr == svm->ldr_reg)
4620 avic_invalidate_logical_id_entry(vcpu);
4623 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr);
4631 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4634 struct vcpu_svm *svm = to_svm(vcpu);
4635 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4636 u32 id = (apic_id_reg >> 24) & 0xff;
4638 if (vcpu->vcpu_id == id)
4641 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4642 new = avic_get_physical_id_entry(vcpu, id);
4646 /* We need to move physical_id_entry to new offset */
4649 to_svm(vcpu)->avic_physical_id_cache = new;
4652 * Also update the guest physical APIC ID in the logical
4653 * APIC ID table entry if already setup the LDR.
4656 avic_handle_ldr_update(vcpu);
4661 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4663 struct vcpu_svm *svm = to_svm(vcpu);
4664 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4666 if (svm->dfr_reg == dfr)
4669 avic_invalidate_logical_id_entry(vcpu);
4673 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4675 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4676 u32 offset = svm->vmcb->control.exit_info_1 &
4677 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4681 if (avic_handle_apic_id_update(&svm->vcpu))
4685 if (avic_handle_ldr_update(&svm->vcpu))
4689 avic_handle_dfr_update(&svm->vcpu);
4695 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4700 static bool is_avic_unaccelerated_access_trap(u32 offset)
4729 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4732 u32 offset = svm->vmcb->control.exit_info_1 &
4733 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4734 u32 vector = svm->vmcb->control.exit_info_2 &
4735 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4736 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4737 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4738 bool trap = is_avic_unaccelerated_access_trap(offset);
4740 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4741 trap, write, vector);
4744 WARN_ONCE(!write, "svm: Handling trap read.\n");
4745 ret = avic_unaccel_trap_write(svm);
4747 /* Handling Fault */
4748 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4754 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4755 [SVM_EXIT_READ_CR0] = cr_interception,
4756 [SVM_EXIT_READ_CR3] = cr_interception,
4757 [SVM_EXIT_READ_CR4] = cr_interception,
4758 [SVM_EXIT_READ_CR8] = cr_interception,
4759 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4760 [SVM_EXIT_WRITE_CR0] = cr_interception,
4761 [SVM_EXIT_WRITE_CR3] = cr_interception,
4762 [SVM_EXIT_WRITE_CR4] = cr_interception,
4763 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4764 [SVM_EXIT_READ_DR0] = dr_interception,
4765 [SVM_EXIT_READ_DR1] = dr_interception,
4766 [SVM_EXIT_READ_DR2] = dr_interception,
4767 [SVM_EXIT_READ_DR3] = dr_interception,
4768 [SVM_EXIT_READ_DR4] = dr_interception,
4769 [SVM_EXIT_READ_DR5] = dr_interception,
4770 [SVM_EXIT_READ_DR6] = dr_interception,
4771 [SVM_EXIT_READ_DR7] = dr_interception,
4772 [SVM_EXIT_WRITE_DR0] = dr_interception,
4773 [SVM_EXIT_WRITE_DR1] = dr_interception,
4774 [SVM_EXIT_WRITE_DR2] = dr_interception,
4775 [SVM_EXIT_WRITE_DR3] = dr_interception,
4776 [SVM_EXIT_WRITE_DR4] = dr_interception,
4777 [SVM_EXIT_WRITE_DR5] = dr_interception,
4778 [SVM_EXIT_WRITE_DR6] = dr_interception,
4779 [SVM_EXIT_WRITE_DR7] = dr_interception,
4780 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4781 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4782 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4783 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4784 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4785 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4786 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4787 [SVM_EXIT_INTR] = intr_interception,
4788 [SVM_EXIT_NMI] = nmi_interception,
4789 [SVM_EXIT_SMI] = nop_on_interception,
4790 [SVM_EXIT_INIT] = nop_on_interception,
4791 [SVM_EXIT_VINTR] = interrupt_window_interception,
4792 [SVM_EXIT_RDPMC] = rdpmc_interception,
4793 [SVM_EXIT_CPUID] = cpuid_interception,
4794 [SVM_EXIT_IRET] = iret_interception,
4795 [SVM_EXIT_INVD] = emulate_on_interception,
4796 [SVM_EXIT_PAUSE] = pause_interception,
4797 [SVM_EXIT_HLT] = halt_interception,
4798 [SVM_EXIT_INVLPG] = invlpg_interception,
4799 [SVM_EXIT_INVLPGA] = invlpga_interception,
4800 [SVM_EXIT_IOIO] = io_interception,
4801 [SVM_EXIT_MSR] = msr_interception,
4802 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4803 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4804 [SVM_EXIT_VMRUN] = vmrun_interception,
4805 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4806 [SVM_EXIT_VMLOAD] = vmload_interception,
4807 [SVM_EXIT_VMSAVE] = vmsave_interception,
4808 [SVM_EXIT_STGI] = stgi_interception,
4809 [SVM_EXIT_CLGI] = clgi_interception,
4810 [SVM_EXIT_SKINIT] = skinit_interception,
4811 [SVM_EXIT_WBINVD] = wbinvd_interception,
4812 [SVM_EXIT_MONITOR] = monitor_interception,
4813 [SVM_EXIT_MWAIT] = mwait_interception,
4814 [SVM_EXIT_XSETBV] = xsetbv_interception,
4815 [SVM_EXIT_NPF] = npf_interception,
4816 [SVM_EXIT_RSM] = rsm_interception,
4817 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4818 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4821 static void dump_vmcb(struct kvm_vcpu *vcpu)
4823 struct vcpu_svm *svm = to_svm(vcpu);
4824 struct vmcb_control_area *control = &svm->vmcb->control;
4825 struct vmcb_save_area *save = &svm->vmcb->save;
4827 pr_err("VMCB Control Area:\n");
4828 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4829 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4830 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4831 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4832 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4833 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4834 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4835 pr_err("%-20s%d\n", "pause filter threshold:",
4836 control->pause_filter_thresh);
4837 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4838 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4839 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4840 pr_err("%-20s%d\n", "asid:", control->asid);
4841 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4842 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4843 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4844 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4845 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4846 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4847 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4848 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4849 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4850 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4851 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4852 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4853 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4854 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4855 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4856 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4857 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4858 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4859 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4860 pr_err("VMCB State Save Area:\n");
4861 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4863 save->es.selector, save->es.attrib,
4864 save->es.limit, save->es.base);
4865 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4867 save->cs.selector, save->cs.attrib,
4868 save->cs.limit, save->cs.base);
4869 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4871 save->ss.selector, save->ss.attrib,
4872 save->ss.limit, save->ss.base);
4873 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4875 save->ds.selector, save->ds.attrib,
4876 save->ds.limit, save->ds.base);
4877 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4879 save->fs.selector, save->fs.attrib,
4880 save->fs.limit, save->fs.base);
4881 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4883 save->gs.selector, save->gs.attrib,
4884 save->gs.limit, save->gs.base);
4885 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4887 save->gdtr.selector, save->gdtr.attrib,
4888 save->gdtr.limit, save->gdtr.base);
4889 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4891 save->ldtr.selector, save->ldtr.attrib,
4892 save->ldtr.limit, save->ldtr.base);
4893 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4895 save->idtr.selector, save->idtr.attrib,
4896 save->idtr.limit, save->idtr.base);
4897 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4899 save->tr.selector, save->tr.attrib,
4900 save->tr.limit, save->tr.base);
4901 pr_err("cpl: %d efer: %016llx\n",
4902 save->cpl, save->efer);
4903 pr_err("%-15s %016llx %-13s %016llx\n",
4904 "cr0:", save->cr0, "cr2:", save->cr2);
4905 pr_err("%-15s %016llx %-13s %016llx\n",
4906 "cr3:", save->cr3, "cr4:", save->cr4);
4907 pr_err("%-15s %016llx %-13s %016llx\n",
4908 "dr6:", save->dr6, "dr7:", save->dr7);
4909 pr_err("%-15s %016llx %-13s %016llx\n",
4910 "rip:", save->rip, "rflags:", save->rflags);
4911 pr_err("%-15s %016llx %-13s %016llx\n",
4912 "rsp:", save->rsp, "rax:", save->rax);
4913 pr_err("%-15s %016llx %-13s %016llx\n",
4914 "star:", save->star, "lstar:", save->lstar);
4915 pr_err("%-15s %016llx %-13s %016llx\n",
4916 "cstar:", save->cstar, "sfmask:", save->sfmask);
4917 pr_err("%-15s %016llx %-13s %016llx\n",
4918 "kernel_gs_base:", save->kernel_gs_base,
4919 "sysenter_cs:", save->sysenter_cs);
4920 pr_err("%-15s %016llx %-13s %016llx\n",
4921 "sysenter_esp:", save->sysenter_esp,
4922 "sysenter_eip:", save->sysenter_eip);
4923 pr_err("%-15s %016llx %-13s %016llx\n",
4924 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4925 pr_err("%-15s %016llx %-13s %016llx\n",
4926 "br_from:", save->br_from, "br_to:", save->br_to);
4927 pr_err("%-15s %016llx %-13s %016llx\n",
4928 "excp_from:", save->last_excp_from,
4929 "excp_to:", save->last_excp_to);
4932 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4934 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4936 *info1 = control->exit_info_1;
4937 *info2 = control->exit_info_2;
4940 static int handle_exit(struct kvm_vcpu *vcpu)
4942 struct vcpu_svm *svm = to_svm(vcpu);
4943 struct kvm_run *kvm_run = vcpu->run;
4944 u32 exit_code = svm->vmcb->control.exit_code;
4946 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4948 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4949 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4951 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4953 if (unlikely(svm->nested.exit_required)) {
4954 nested_svm_vmexit(svm);
4955 svm->nested.exit_required = false;
4960 if (is_guest_mode(vcpu)) {
4963 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4964 svm->vmcb->control.exit_info_1,
4965 svm->vmcb->control.exit_info_2,
4966 svm->vmcb->control.exit_int_info,
4967 svm->vmcb->control.exit_int_info_err,
4970 vmexit = nested_svm_exit_special(svm);
4972 if (vmexit == NESTED_EXIT_CONTINUE)
4973 vmexit = nested_svm_exit_handled(svm);
4975 if (vmexit == NESTED_EXIT_DONE)
4979 svm_complete_interrupts(svm);
4981 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4982 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4983 kvm_run->fail_entry.hardware_entry_failure_reason
4984 = svm->vmcb->control.exit_code;
4985 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4990 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4991 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4992 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4993 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4994 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4996 __func__, svm->vmcb->control.exit_int_info,
4999 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
5000 || !svm_exit_handlers[exit_code]) {
5001 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
5002 kvm_queue_exception(vcpu, UD_VECTOR);
5006 return svm_exit_handlers[exit_code](svm);
5009 static void reload_tss(struct kvm_vcpu *vcpu)
5011 int cpu = raw_smp_processor_id();
5013 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5014 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5018 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5020 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5021 int asid = sev_get_asid(svm->vcpu.kvm);
5023 /* Assign the asid allocated with this SEV guest */
5024 svm->vmcb->control.asid = asid;
5029 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5030 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5032 if (sd->sev_vmcbs[asid] == svm->vmcb &&
5033 svm->last_cpu == cpu)
5036 svm->last_cpu = cpu;
5037 sd->sev_vmcbs[asid] = svm->vmcb;
5038 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5039 mark_dirty(svm->vmcb, VMCB_ASID);
5042 static void pre_svm_run(struct vcpu_svm *svm)
5044 int cpu = raw_smp_processor_id();
5046 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5048 if (sev_guest(svm->vcpu.kvm))
5049 return pre_sev_run(svm, cpu);
5051 /* FIXME: handle wraparound of asid_generation */
5052 if (svm->asid_generation != sd->asid_generation)
5056 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5058 struct vcpu_svm *svm = to_svm(vcpu);
5060 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5061 vcpu->arch.hflags |= HF_NMI_MASK;
5062 set_intercept(svm, INTERCEPT_IRET);
5063 ++vcpu->stat.nmi_injections;
5066 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5068 struct vmcb_control_area *control;
5070 /* The following fields are ignored when AVIC is enabled */
5071 control = &svm->vmcb->control;
5072 control->int_vector = irq;
5073 control->int_ctl &= ~V_INTR_PRIO_MASK;
5074 control->int_ctl |= V_IRQ_MASK |
5075 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5076 mark_dirty(svm->vmcb, VMCB_INTR);
5079 static void svm_set_irq(struct kvm_vcpu *vcpu)
5081 struct vcpu_svm *svm = to_svm(vcpu);
5083 BUG_ON(!(gif_set(svm)));
5085 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5086 ++vcpu->stat.irq_injections;
5088 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5089 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5092 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5094 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5097 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5099 struct vcpu_svm *svm = to_svm(vcpu);
5101 if (svm_nested_virtualize_tpr(vcpu) ||
5102 kvm_vcpu_apicv_active(vcpu))
5105 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5111 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5114 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5119 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5121 return avic && irqchip_split(vcpu->kvm);
5124 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5128 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5132 /* Note: Currently only used by Hyper-V. */
5133 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5135 struct vcpu_svm *svm = to_svm(vcpu);
5136 struct vmcb *vmcb = svm->vmcb;
5138 if (kvm_vcpu_apicv_active(vcpu))
5139 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
5141 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5142 mark_dirty(vmcb, VMCB_AVIC);
5145 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5150 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5152 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5153 smp_mb__after_atomic();
5155 if (avic_vcpu_is_running(vcpu))
5156 wrmsrl(SVM_AVIC_DOORBELL,
5157 kvm_cpu_get_apicid(vcpu->cpu));
5159 kvm_vcpu_wake_up(vcpu);
5162 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5164 unsigned long flags;
5165 struct amd_svm_iommu_ir *cur;
5167 spin_lock_irqsave(&svm->ir_list_lock, flags);
5168 list_for_each_entry(cur, &svm->ir_list, node) {
5169 if (cur->data != pi->ir_data)
5171 list_del(&cur->node);
5175 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5178 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5181 unsigned long flags;
5182 struct amd_svm_iommu_ir *ir;
5185 * In some cases, the existing irte is updaed and re-set,
5186 * so we need to check here if it's already been * added
5189 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5190 struct kvm *kvm = svm->vcpu.kvm;
5191 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5192 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5193 struct vcpu_svm *prev_svm;
5200 prev_svm = to_svm(prev_vcpu);
5201 svm_ir_list_del(prev_svm, pi);
5205 * Allocating new amd_iommu_pi_data, which will get
5206 * add to the per-vcpu ir_list.
5208 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
5213 ir->data = pi->ir_data;
5215 spin_lock_irqsave(&svm->ir_list_lock, flags);
5216 list_add(&ir->node, &svm->ir_list);
5217 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5224 * The HW cannot support posting multicast/broadcast
5225 * interrupts to a vCPU. So, we still use legacy interrupt
5226 * remapping for these kind of interrupts.
5228 * For lowest-priority interrupts, we only support
5229 * those with single CPU as the destination, e.g. user
5230 * configures the interrupts via /proc/irq or uses
5231 * irqbalance to make the interrupts single-CPU.
5234 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5235 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5237 struct kvm_lapic_irq irq;
5238 struct kvm_vcpu *vcpu = NULL;
5240 kvm_set_msi_irq(kvm, e, &irq);
5242 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5243 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5244 __func__, irq.vector);
5248 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5250 *svm = to_svm(vcpu);
5251 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5252 vcpu_info->vector = irq.vector;
5258 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5261 * @host_irq: host irq of the interrupt
5262 * @guest_irq: gsi of the interrupt
5263 * @set: set or unset PI
5264 * returns 0 on success, < 0 on failure
5266 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5267 uint32_t guest_irq, bool set)
5269 struct kvm_kernel_irq_routing_entry *e;
5270 struct kvm_irq_routing_table *irq_rt;
5271 int idx, ret = -EINVAL;
5273 if (!kvm_arch_has_assigned_device(kvm) ||
5274 !irq_remapping_cap(IRQ_POSTING_CAP))
5277 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5278 __func__, host_irq, guest_irq, set);
5280 idx = srcu_read_lock(&kvm->irq_srcu);
5281 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5282 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5284 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5285 struct vcpu_data vcpu_info;
5286 struct vcpu_svm *svm = NULL;
5288 if (e->type != KVM_IRQ_ROUTING_MSI)
5292 * Here, we setup with legacy mode in the following cases:
5293 * 1. When cannot target interrupt to a specific vcpu.
5294 * 2. Unsetting posted interrupt.
5295 * 3. APIC virtialization is disabled for the vcpu.
5297 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5298 kvm_vcpu_apicv_active(&svm->vcpu)) {
5299 struct amd_iommu_pi_data pi;
5301 /* Try to enable guest_mode in IRTE */
5302 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5304 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5306 pi.is_guest_mode = true;
5307 pi.vcpu_data = &vcpu_info;
5308 ret = irq_set_vcpu_affinity(host_irq, &pi);
5311 * Here, we successfully setting up vcpu affinity in
5312 * IOMMU guest mode. Now, we need to store the posted
5313 * interrupt information in a per-vcpu ir_list so that
5314 * we can reference to them directly when we update vcpu
5315 * scheduling information in IOMMU irte.
5317 if (!ret && pi.is_guest_mode)
5318 svm_ir_list_add(svm, &pi);
5320 /* Use legacy mode in IRTE */
5321 struct amd_iommu_pi_data pi;
5324 * Here, pi is used to:
5325 * - Tell IOMMU to use legacy mode for this interrupt.
5326 * - Retrieve ga_tag of prior interrupt remapping data.
5328 pi.is_guest_mode = false;
5329 ret = irq_set_vcpu_affinity(host_irq, &pi);
5332 * Check if the posted interrupt was previously
5333 * setup with the guest_mode by checking if the ga_tag
5334 * was cached. If so, we need to clean up the per-vcpu
5337 if (!ret && pi.prev_ga_tag) {
5338 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5339 struct kvm_vcpu *vcpu;
5341 vcpu = kvm_get_vcpu_by_id(kvm, id);
5343 svm_ir_list_del(to_svm(vcpu), &pi);
5348 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5349 e->gsi, vcpu_info.vector,
5350 vcpu_info.pi_desc_addr, set);
5354 pr_err("%s: failed to update PI IRTE\n", __func__);
5361 srcu_read_unlock(&kvm->irq_srcu, idx);
5365 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5367 struct vcpu_svm *svm = to_svm(vcpu);
5368 struct vmcb *vmcb = svm->vmcb;
5370 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5371 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5372 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5377 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5379 struct vcpu_svm *svm = to_svm(vcpu);
5381 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5384 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5386 struct vcpu_svm *svm = to_svm(vcpu);
5389 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5390 set_intercept(svm, INTERCEPT_IRET);
5392 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5393 clr_intercept(svm, INTERCEPT_IRET);
5397 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5399 struct vcpu_svm *svm = to_svm(vcpu);
5400 struct vmcb *vmcb = svm->vmcb;
5403 if (!gif_set(svm) ||
5404 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5407 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5409 if (is_guest_mode(vcpu))
5410 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5415 static void enable_irq_window(struct kvm_vcpu *vcpu)
5417 struct vcpu_svm *svm = to_svm(vcpu);
5419 if (kvm_vcpu_apicv_active(vcpu))
5423 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5424 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5425 * get that intercept, this function will be called again though and
5426 * we'll get the vintr intercept. However, if the vGIF feature is
5427 * enabled, the STGI interception will not occur. Enable the irq
5428 * window under the assumption that the hardware will set the GIF.
5430 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5432 svm_inject_irq(svm, 0x0);
5436 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5438 struct vcpu_svm *svm = to_svm(vcpu);
5440 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5442 return; /* IRET will cause a vm exit */
5444 if (!gif_set(svm)) {
5445 if (vgif_enabled(svm))
5446 set_intercept(svm, INTERCEPT_STGI);
5447 return; /* STGI will cause a vm exit */
5450 if (svm->nested.exit_required)
5451 return; /* we're not going to run the guest yet */
5454 * Something prevents NMI from been injected. Single step over possible
5455 * problem (IRET or exception injection or interrupt shadow)
5457 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5458 svm->nmi_singlestep = true;
5459 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5462 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5467 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5472 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5474 struct vcpu_svm *svm = to_svm(vcpu);
5476 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5477 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5479 svm->asid_generation--;
5482 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5484 struct vcpu_svm *svm = to_svm(vcpu);
5486 invlpga(gva, svm->vmcb->control.asid);
5489 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5493 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5495 struct vcpu_svm *svm = to_svm(vcpu);
5497 if (svm_nested_virtualize_tpr(vcpu))
5500 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5501 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5502 kvm_set_cr8(vcpu, cr8);
5506 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5508 struct vcpu_svm *svm = to_svm(vcpu);
5511 if (svm_nested_virtualize_tpr(vcpu) ||
5512 kvm_vcpu_apicv_active(vcpu))
5515 cr8 = kvm_get_cr8(vcpu);
5516 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5517 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5520 static void svm_complete_interrupts(struct vcpu_svm *svm)
5524 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5525 unsigned int3_injected = svm->int3_injected;
5527 svm->int3_injected = 0;
5530 * If we've made progress since setting HF_IRET_MASK, we've
5531 * executed an IRET and can allow NMI injection.
5533 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5534 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5535 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5536 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5539 svm->vcpu.arch.nmi_injected = false;
5540 kvm_clear_exception_queue(&svm->vcpu);
5541 kvm_clear_interrupt_queue(&svm->vcpu);
5543 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5546 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5548 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5549 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5552 case SVM_EXITINTINFO_TYPE_NMI:
5553 svm->vcpu.arch.nmi_injected = true;
5555 case SVM_EXITINTINFO_TYPE_EXEPT:
5557 * In case of software exceptions, do not reinject the vector,
5558 * but re-execute the instruction instead. Rewind RIP first
5559 * if we emulated INT3 before.
5561 if (kvm_exception_is_soft(vector)) {
5562 if (vector == BP_VECTOR && int3_injected &&
5563 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5564 kvm_rip_write(&svm->vcpu,
5565 kvm_rip_read(&svm->vcpu) -
5569 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5570 u32 err = svm->vmcb->control.exit_int_info_err;
5571 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5574 kvm_requeue_exception(&svm->vcpu, vector);
5576 case SVM_EXITINTINFO_TYPE_INTR:
5577 kvm_queue_interrupt(&svm->vcpu, vector, false);
5584 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5586 struct vcpu_svm *svm = to_svm(vcpu);
5587 struct vmcb_control_area *control = &svm->vmcb->control;
5589 control->exit_int_info = control->event_inj;
5590 control->exit_int_info_err = control->event_inj_err;
5591 control->event_inj = 0;
5592 svm_complete_interrupts(svm);
5595 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5597 struct vcpu_svm *svm = to_svm(vcpu);
5599 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5600 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5601 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5604 * A vmexit emulation is required before the vcpu can be executed
5607 if (unlikely(svm->nested.exit_required))
5611 * Disable singlestep if we're injecting an interrupt/exception.
5612 * We don't want our modified rflags to be pushed on the stack where
5613 * we might not be able to easily reset them if we disabled NMI
5616 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5618 * Event injection happens before external interrupts cause a
5619 * vmexit and interrupts are disabled here, so smp_send_reschedule
5620 * is enough to force an immediate vmexit.
5622 disable_nmi_singlestep(svm);
5623 smp_send_reschedule(vcpu->cpu);
5628 sync_lapic_to_cr8(vcpu);
5630 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5633 kvm_load_guest_xcr0(vcpu);
5636 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5637 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5638 * is no need to worry about the conditional branch over the wrmsr
5639 * being speculatively taken.
5641 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5646 "push %%" _ASM_BP "; \n\t"
5647 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5648 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5649 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5650 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5651 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5652 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5653 #ifdef CONFIG_X86_64
5654 "mov %c[r8](%[svm]), %%r8 \n\t"
5655 "mov %c[r9](%[svm]), %%r9 \n\t"
5656 "mov %c[r10](%[svm]), %%r10 \n\t"
5657 "mov %c[r11](%[svm]), %%r11 \n\t"
5658 "mov %c[r12](%[svm]), %%r12 \n\t"
5659 "mov %c[r13](%[svm]), %%r13 \n\t"
5660 "mov %c[r14](%[svm]), %%r14 \n\t"
5661 "mov %c[r15](%[svm]), %%r15 \n\t"
5664 /* Enter guest mode */
5665 "push %%" _ASM_AX " \n\t"
5666 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5667 __ex("vmload %%" _ASM_AX) "\n\t"
5668 __ex("vmrun %%" _ASM_AX) "\n\t"
5669 __ex("vmsave %%" _ASM_AX) "\n\t"
5670 "pop %%" _ASM_AX " \n\t"
5672 /* Save guest registers, load host registers */
5673 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5674 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5675 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5676 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5677 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5678 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5679 #ifdef CONFIG_X86_64
5680 "mov %%r8, %c[r8](%[svm]) \n\t"
5681 "mov %%r9, %c[r9](%[svm]) \n\t"
5682 "mov %%r10, %c[r10](%[svm]) \n\t"
5683 "mov %%r11, %c[r11](%[svm]) \n\t"
5684 "mov %%r12, %c[r12](%[svm]) \n\t"
5685 "mov %%r13, %c[r13](%[svm]) \n\t"
5686 "mov %%r14, %c[r14](%[svm]) \n\t"
5687 "mov %%r15, %c[r15](%[svm]) \n\t"
5689 * Clear host registers marked as clobbered to prevent
5692 "xor %%r8d, %%r8d \n\t"
5693 "xor %%r9d, %%r9d \n\t"
5694 "xor %%r10d, %%r10d \n\t"
5695 "xor %%r11d, %%r11d \n\t"
5696 "xor %%r12d, %%r12d \n\t"
5697 "xor %%r13d, %%r13d \n\t"
5698 "xor %%r14d, %%r14d \n\t"
5699 "xor %%r15d, %%r15d \n\t"
5701 "xor %%ebx, %%ebx \n\t"
5702 "xor %%ecx, %%ecx \n\t"
5703 "xor %%edx, %%edx \n\t"
5704 "xor %%esi, %%esi \n\t"
5705 "xor %%edi, %%edi \n\t"
5709 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5710 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5711 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5712 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5713 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5714 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5715 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5716 #ifdef CONFIG_X86_64
5717 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5718 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5719 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5720 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5721 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5722 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5723 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5724 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5727 #ifdef CONFIG_X86_64
5728 , "rbx", "rcx", "rdx", "rsi", "rdi"
5729 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5731 , "ebx", "ecx", "edx", "esi", "edi"
5735 /* Eliminate branch target predictions from guest mode */
5738 #ifdef CONFIG_X86_64
5739 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5741 loadsegment(fs, svm->host.fs);
5742 #ifndef CONFIG_X86_32_LAZY_GS
5743 loadsegment(gs, svm->host.gs);
5748 * We do not use IBRS in the kernel. If this vCPU has used the
5749 * SPEC_CTRL MSR it may have left it on; save the value and
5750 * turn it off. This is much more efficient than blindly adding
5751 * it to the atomic save/restore list. Especially as the former
5752 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5754 * For non-nested case:
5755 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5759 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5762 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5763 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5767 local_irq_disable();
5769 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5771 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5772 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5773 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5774 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5776 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5777 kvm_before_interrupt(&svm->vcpu);
5779 kvm_put_guest_xcr0(vcpu);
5782 /* Any pending NMI will happen here */
5784 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5785 kvm_after_interrupt(&svm->vcpu);
5787 sync_cr8_to_lapic(vcpu);
5791 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5793 /* if exit due to PF check for async PF */
5794 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5795 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5798 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5799 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5803 * We need to handle MC intercepts here before the vcpu has a chance to
5804 * change the physical cpu
5806 if (unlikely(svm->vmcb->control.exit_code ==
5807 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5808 svm_handle_mce(svm);
5810 mark_all_clean(svm->vmcb);
5812 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5814 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5816 struct vcpu_svm *svm = to_svm(vcpu);
5818 svm->vmcb->save.cr3 = __sme_set(root);
5819 mark_dirty(svm->vmcb, VMCB_CR);
5822 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5824 struct vcpu_svm *svm = to_svm(vcpu);
5826 svm->vmcb->control.nested_cr3 = __sme_set(root);
5827 mark_dirty(svm->vmcb, VMCB_NPT);
5829 /* Also sync guest cr3 here in case we live migrate */
5830 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5831 mark_dirty(svm->vmcb, VMCB_CR);
5834 static int is_disabled(void)
5838 rdmsrl(MSR_VM_CR, vm_cr);
5839 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5846 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5849 * Patch in the VMMCALL instruction:
5851 hypercall[0] = 0x0f;
5852 hypercall[1] = 0x01;
5853 hypercall[2] = 0xd9;
5856 static void svm_check_processor_compat(void *rtn)
5861 static bool svm_cpu_has_accelerated_tpr(void)
5866 static bool svm_has_emulated_msr(int index)
5869 case MSR_IA32_MCG_EXT_CTL:
5878 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5883 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5885 struct vcpu_svm *svm = to_svm(vcpu);
5887 /* Update nrips enabled cache */
5888 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5890 if (!kvm_vcpu_apicv_active(vcpu))
5893 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5896 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5901 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5905 entry->ecx |= (1 << 2); /* Set SVM bit */
5908 entry->eax = 1; /* SVM revision 1 */
5909 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5910 ASID emulation to nested SVM */
5911 entry->ecx = 0; /* Reserved */
5912 entry->edx = 0; /* Per default do not support any
5913 additional features */
5915 /* Support next_rip if host supports it */
5916 if (boot_cpu_has(X86_FEATURE_NRIPS))
5917 entry->edx |= SVM_FEATURE_NRIP;
5919 /* Support NPT for the guest if enabled */
5921 entry->edx |= SVM_FEATURE_NPT;
5925 /* Support memory encryption cpuid if host supports it */
5926 if (boot_cpu_has(X86_FEATURE_SEV))
5927 cpuid(0x8000001f, &entry->eax, &entry->ebx,
5928 &entry->ecx, &entry->edx);
5933 static int svm_get_lpage_level(void)
5935 return PT_PDPE_LEVEL;
5938 static bool svm_rdtscp_supported(void)
5940 return boot_cpu_has(X86_FEATURE_RDTSCP);
5943 static bool svm_invpcid_supported(void)
5948 static bool svm_mpx_supported(void)
5953 static bool svm_xsaves_supported(void)
5958 static bool svm_umip_emulated(void)
5963 static bool svm_pt_supported(void)
5968 static bool svm_has_wbinvd_exit(void)
5973 #define PRE_EX(exit) { .exit_code = (exit), \
5974 .stage = X86_ICPT_PRE_EXCEPT, }
5975 #define POST_EX(exit) { .exit_code = (exit), \
5976 .stage = X86_ICPT_POST_EXCEPT, }
5977 #define POST_MEM(exit) { .exit_code = (exit), \
5978 .stage = X86_ICPT_POST_MEMACCESS, }
5980 static const struct __x86_intercept {
5982 enum x86_intercept_stage stage;
5983 } x86_intercept_map[] = {
5984 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5985 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5986 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5987 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5988 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5989 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5990 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5991 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5992 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5993 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5994 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5995 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5996 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5997 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5998 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5999 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
6000 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
6001 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
6002 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
6003 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
6004 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
6005 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
6006 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
6007 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
6008 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
6009 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
6010 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
6011 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
6012 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
6013 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
6014 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
6015 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
6016 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
6017 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
6018 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
6019 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
6020 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
6021 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
6022 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
6023 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
6024 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
6025 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
6026 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
6027 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
6028 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
6029 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
6036 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6037 struct x86_instruction_info *info,
6038 enum x86_intercept_stage stage)
6040 struct vcpu_svm *svm = to_svm(vcpu);
6041 int vmexit, ret = X86EMUL_CONTINUE;
6042 struct __x86_intercept icpt_info;
6043 struct vmcb *vmcb = svm->vmcb;
6045 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6048 icpt_info = x86_intercept_map[info->intercept];
6050 if (stage != icpt_info.stage)
6053 switch (icpt_info.exit_code) {
6054 case SVM_EXIT_READ_CR0:
6055 if (info->intercept == x86_intercept_cr_read)
6056 icpt_info.exit_code += info->modrm_reg;
6058 case SVM_EXIT_WRITE_CR0: {
6059 unsigned long cr0, val;
6062 if (info->intercept == x86_intercept_cr_write)
6063 icpt_info.exit_code += info->modrm_reg;
6065 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6066 info->intercept == x86_intercept_clts)
6069 intercept = svm->nested.intercept;
6071 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6074 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6075 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
6077 if (info->intercept == x86_intercept_lmsw) {
6080 /* lmsw can't clear PE - catch this here */
6081 if (cr0 & X86_CR0_PE)
6086 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6090 case SVM_EXIT_READ_DR0:
6091 case SVM_EXIT_WRITE_DR0:
6092 icpt_info.exit_code += info->modrm_reg;
6095 if (info->intercept == x86_intercept_wrmsr)
6096 vmcb->control.exit_info_1 = 1;
6098 vmcb->control.exit_info_1 = 0;
6100 case SVM_EXIT_PAUSE:
6102 * We get this for NOP only, but pause
6103 * is rep not, check this here
6105 if (info->rep_prefix != REPE_PREFIX)
6108 case SVM_EXIT_IOIO: {
6112 if (info->intercept == x86_intercept_in ||
6113 info->intercept == x86_intercept_ins) {
6114 exit_info = ((info->src_val & 0xffff) << 16) |
6116 bytes = info->dst_bytes;
6118 exit_info = (info->dst_val & 0xffff) << 16;
6119 bytes = info->src_bytes;
6122 if (info->intercept == x86_intercept_outs ||
6123 info->intercept == x86_intercept_ins)
6124 exit_info |= SVM_IOIO_STR_MASK;
6126 if (info->rep_prefix)
6127 exit_info |= SVM_IOIO_REP_MASK;
6129 bytes = min(bytes, 4u);
6131 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6133 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6135 vmcb->control.exit_info_1 = exit_info;
6136 vmcb->control.exit_info_2 = info->next_rip;
6144 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6145 if (static_cpu_has(X86_FEATURE_NRIPS))
6146 vmcb->control.next_rip = info->next_rip;
6147 vmcb->control.exit_code = icpt_info.exit_code;
6148 vmexit = nested_svm_exit_handled(svm);
6150 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6157 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6161 * We must have an instruction with interrupts enabled, so
6162 * the timer interrupt isn't delayed by the interrupt shadow.
6165 local_irq_disable();
6168 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6170 if (pause_filter_thresh)
6171 shrink_ple_window(vcpu);
6174 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6176 if (avic_handle_apic_id_update(vcpu) != 0)
6178 avic_handle_dfr_update(vcpu);
6179 avic_handle_ldr_update(vcpu);
6182 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6184 /* [63:9] are reserved. */
6185 vcpu->arch.mcg_cap &= 0x1ff;
6188 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6190 struct vcpu_svm *svm = to_svm(vcpu);
6192 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6196 if (is_guest_mode(&svm->vcpu) &&
6197 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6198 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6199 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6200 svm->nested.exit_required = true;
6207 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6209 struct vcpu_svm *svm = to_svm(vcpu);
6212 if (is_guest_mode(vcpu)) {
6213 /* FED8h - SVM Guest */
6214 put_smstate(u64, smstate, 0x7ed8, 1);
6215 /* FEE0h - SVM Guest VMCB Physical Address */
6216 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6218 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6219 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6220 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6222 ret = nested_svm_vmexit(svm);
6229 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
6231 struct vcpu_svm *svm = to_svm(vcpu);
6232 struct vmcb *nested_vmcb;
6233 struct kvm_host_map map;
6237 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
6238 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
6241 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
6243 nested_vmcb = map.hva;
6244 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
6249 static int enable_smi_window(struct kvm_vcpu *vcpu)
6251 struct vcpu_svm *svm = to_svm(vcpu);
6253 if (!gif_set(svm)) {
6254 if (vgif_enabled(svm))
6255 set_intercept(svm, INTERCEPT_STGI);
6256 /* STGI will cause a vm exit */
6262 static int sev_asid_new(void)
6267 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6269 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6270 if (pos >= max_sev_asid)
6273 set_bit(pos, sev_asid_bitmap);
6277 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6279 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6283 if (unlikely(sev->active))
6286 asid = sev_asid_new();
6290 ret = sev_platform_init(&argp->error);
6296 INIT_LIST_HEAD(&sev->regions_list);
6301 __sev_asid_free(asid);
6305 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6307 struct sev_data_activate *data;
6308 int asid = sev_get_asid(kvm);
6311 wbinvd_on_all_cpus();
6313 ret = sev_guest_df_flush(error);
6317 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6321 /* activate ASID on the given handle */
6322 data->handle = handle;
6324 ret = sev_guest_activate(data, error);
6330 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6339 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6345 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6347 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6349 return __sev_issue_cmd(sev->fd, id, data, error);
6352 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6354 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6355 struct sev_data_launch_start *start;
6356 struct kvm_sev_launch_start params;
6357 void *dh_blob, *session_blob;
6358 int *error = &argp->error;
6361 if (!sev_guest(kvm))
6364 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6367 start = kzalloc(sizeof(*start), GFP_KERNEL_ACCOUNT);
6372 if (params.dh_uaddr) {
6373 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6374 if (IS_ERR(dh_blob)) {
6375 ret = PTR_ERR(dh_blob);
6379 start->dh_cert_address = __sme_set(__pa(dh_blob));
6380 start->dh_cert_len = params.dh_len;
6383 session_blob = NULL;
6384 if (params.session_uaddr) {
6385 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6386 if (IS_ERR(session_blob)) {
6387 ret = PTR_ERR(session_blob);
6391 start->session_address = __sme_set(__pa(session_blob));
6392 start->session_len = params.session_len;
6395 start->handle = params.handle;
6396 start->policy = params.policy;
6398 /* create memory encryption context */
6399 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6401 goto e_free_session;
6403 /* Bind ASID to this guest */
6404 ret = sev_bind_asid(kvm, start->handle, error);
6406 goto e_free_session;
6408 /* return handle to userspace */
6409 params.handle = start->handle;
6410 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6411 sev_unbind_asid(kvm, start->handle);
6413 goto e_free_session;
6416 sev->handle = start->handle;
6417 sev->fd = argp->sev_fd;
6420 kfree(session_blob);
6428 static unsigned long get_num_contig_pages(unsigned long idx,
6429 struct page **inpages, unsigned long npages)
6431 unsigned long paddr, next_paddr;
6432 unsigned long i = idx + 1, pages = 1;
6434 /* find the number of contiguous pages starting from idx */
6435 paddr = __sme_page_pa(inpages[idx]);
6436 while (i < npages) {
6437 next_paddr = __sme_page_pa(inpages[i++]);
6438 if ((paddr + PAGE_SIZE) == next_paddr) {
6449 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6451 unsigned long vaddr, vaddr_end, next_vaddr, npages, pages, size, i;
6452 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6453 struct kvm_sev_launch_update_data params;
6454 struct sev_data_launch_update_data *data;
6455 struct page **inpages;
6458 if (!sev_guest(kvm))
6461 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6464 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6468 vaddr = params.uaddr;
6470 vaddr_end = vaddr + size;
6472 /* Lock the user memory. */
6473 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6480 * The LAUNCH_UPDATE command will perform in-place encryption of the
6481 * memory content (i.e it will write the same memory region with C=1).
6482 * It's possible that the cache may contain the data with C=0, i.e.,
6483 * unencrypted so invalidate it first.
6485 sev_clflush_pages(inpages, npages);
6487 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6491 * If the user buffer is not page-aligned, calculate the offset
6494 offset = vaddr & (PAGE_SIZE - 1);
6496 /* Calculate the number of pages that can be encrypted in one go. */
6497 pages = get_num_contig_pages(i, inpages, npages);
6499 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6501 data->handle = sev->handle;
6503 data->address = __sme_page_pa(inpages[i]) + offset;
6504 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6509 next_vaddr = vaddr + len;
6513 /* content of memory is updated, mark pages dirty */
6514 for (i = 0; i < npages; i++) {
6515 set_page_dirty_lock(inpages[i]);
6516 mark_page_accessed(inpages[i]);
6518 /* unlock the user pages */
6519 sev_unpin_memory(kvm, inpages, npages);
6525 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6527 void __user *measure = (void __user *)(uintptr_t)argp->data;
6528 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6529 struct sev_data_launch_measure *data;
6530 struct kvm_sev_launch_measure params;
6531 void __user *p = NULL;
6535 if (!sev_guest(kvm))
6538 if (copy_from_user(¶ms, measure, sizeof(params)))
6541 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6545 /* User wants to query the blob length */
6549 p = (void __user *)(uintptr_t)params.uaddr;
6551 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6557 blob = kmalloc(params.len, GFP_KERNEL);
6561 data->address = __psp_pa(blob);
6562 data->len = params.len;
6566 data->handle = sev->handle;
6567 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6570 * If we query the session length, FW responded with expected data.
6579 if (copy_to_user(p, blob, params.len))
6584 params.len = data->len;
6585 if (copy_to_user(measure, ¶ms, sizeof(params)))
6594 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6596 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6597 struct sev_data_launch_finish *data;
6600 if (!sev_guest(kvm))
6603 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6607 data->handle = sev->handle;
6608 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6614 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6616 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6617 struct kvm_sev_guest_status params;
6618 struct sev_data_guest_status *data;
6621 if (!sev_guest(kvm))
6624 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6628 data->handle = sev->handle;
6629 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6633 params.policy = data->policy;
6634 params.state = data->state;
6635 params.handle = data->handle;
6637 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6644 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6645 unsigned long dst, int size,
6646 int *error, bool enc)
6648 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6649 struct sev_data_dbg *data;
6652 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6656 data->handle = sev->handle;
6657 data->dst_addr = dst;
6658 data->src_addr = src;
6661 ret = sev_issue_cmd(kvm,
6662 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6668 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6669 unsigned long dst_paddr, int sz, int *err)
6674 * Its safe to read more than we are asked, caller should ensure that
6675 * destination has enough space.
6677 src_paddr = round_down(src_paddr, 16);
6678 offset = src_paddr & 15;
6679 sz = round_up(sz + offset, 16);
6681 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6684 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6685 unsigned long __user dst_uaddr,
6686 unsigned long dst_paddr,
6689 struct page *tpage = NULL;
6692 /* if inputs are not 16-byte then use intermediate buffer */
6693 if (!IS_ALIGNED(dst_paddr, 16) ||
6694 !IS_ALIGNED(paddr, 16) ||
6695 !IS_ALIGNED(size, 16)) {
6696 tpage = (void *)alloc_page(GFP_KERNEL);
6700 dst_paddr = __sme_page_pa(tpage);
6703 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6708 offset = paddr & 15;
6709 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6710 page_address(tpage) + offset, size))
6721 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6722 unsigned long __user vaddr,
6723 unsigned long dst_paddr,
6724 unsigned long __user dst_vaddr,
6725 int size, int *error)
6727 struct page *src_tpage = NULL;
6728 struct page *dst_tpage = NULL;
6729 int ret, len = size;
6731 /* If source buffer is not aligned then use an intermediate buffer */
6732 if (!IS_ALIGNED(vaddr, 16)) {
6733 src_tpage = alloc_page(GFP_KERNEL);
6737 if (copy_from_user(page_address(src_tpage),
6738 (void __user *)(uintptr_t)vaddr, size)) {
6739 __free_page(src_tpage);
6743 paddr = __sme_page_pa(src_tpage);
6747 * If destination buffer or length is not aligned then do read-modify-write:
6748 * - decrypt destination in an intermediate buffer
6749 * - copy the source buffer in an intermediate buffer
6750 * - use the intermediate buffer as source buffer
6752 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6755 dst_tpage = alloc_page(GFP_KERNEL);
6761 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6762 __sme_page_pa(dst_tpage), size, error);
6767 * If source is kernel buffer then use memcpy() otherwise
6770 dst_offset = dst_paddr & 15;
6773 memcpy(page_address(dst_tpage) + dst_offset,
6774 page_address(src_tpage), size);
6776 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6777 (void __user *)(uintptr_t)vaddr, size)) {
6783 paddr = __sme_page_pa(dst_tpage);
6784 dst_paddr = round_down(dst_paddr, 16);
6785 len = round_up(size, 16);
6788 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6792 __free_page(src_tpage);
6794 __free_page(dst_tpage);
6798 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6800 unsigned long vaddr, vaddr_end, next_vaddr;
6801 unsigned long dst_vaddr;
6802 struct page **src_p, **dst_p;
6803 struct kvm_sev_dbg debug;
6808 if (!sev_guest(kvm))
6811 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6814 if (!debug.len || debug.src_uaddr + debug.len < debug.src_uaddr)
6816 if (!debug.dst_uaddr)
6819 vaddr = debug.src_uaddr;
6821 vaddr_end = vaddr + size;
6822 dst_vaddr = debug.dst_uaddr;
6824 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6825 int len, s_off, d_off;
6827 /* lock userspace source and destination page */
6828 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6832 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6834 sev_unpin_memory(kvm, src_p, n);
6839 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6840 * memory content (i.e it will write the same memory region with C=1).
6841 * It's possible that the cache may contain the data with C=0, i.e.,
6842 * unencrypted so invalidate it first.
6844 sev_clflush_pages(src_p, 1);
6845 sev_clflush_pages(dst_p, 1);
6848 * Since user buffer may not be page aligned, calculate the
6849 * offset within the page.
6851 s_off = vaddr & ~PAGE_MASK;
6852 d_off = dst_vaddr & ~PAGE_MASK;
6853 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6856 ret = __sev_dbg_decrypt_user(kvm,
6857 __sme_page_pa(src_p[0]) + s_off,
6859 __sme_page_pa(dst_p[0]) + d_off,
6862 ret = __sev_dbg_encrypt_user(kvm,
6863 __sme_page_pa(src_p[0]) + s_off,
6865 __sme_page_pa(dst_p[0]) + d_off,
6869 sev_unpin_memory(kvm, src_p, n);
6870 sev_unpin_memory(kvm, dst_p, n);
6875 next_vaddr = vaddr + len;
6876 dst_vaddr = dst_vaddr + len;
6883 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6885 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6886 struct sev_data_launch_secret *data;
6887 struct kvm_sev_launch_secret params;
6888 struct page **pages;
6893 if (!sev_guest(kvm))
6896 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6899 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6904 * The secret must be copied into contiguous memory region, lets verify
6905 * that userspace memory pages are contiguous before we issue command.
6907 if (get_num_contig_pages(0, pages, n) != n) {
6909 goto e_unpin_memory;
6913 data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT);
6915 goto e_unpin_memory;
6917 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6918 data->guest_address = __sme_page_pa(pages[0]) + offset;
6919 data->guest_len = params.guest_len;
6921 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6923 ret = PTR_ERR(blob);
6927 data->trans_address = __psp_pa(blob);
6928 data->trans_len = params.trans_len;
6930 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6935 data->hdr_address = __psp_pa(hdr);
6936 data->hdr_len = params.hdr_len;
6938 data->handle = sev->handle;
6939 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6948 sev_unpin_memory(kvm, pages, n);
6952 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6954 struct kvm_sev_cmd sev_cmd;
6957 if (!svm_sev_enabled())
6960 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6963 mutex_lock(&kvm->lock);
6965 switch (sev_cmd.id) {
6967 r = sev_guest_init(kvm, &sev_cmd);
6969 case KVM_SEV_LAUNCH_START:
6970 r = sev_launch_start(kvm, &sev_cmd);
6972 case KVM_SEV_LAUNCH_UPDATE_DATA:
6973 r = sev_launch_update_data(kvm, &sev_cmd);
6975 case KVM_SEV_LAUNCH_MEASURE:
6976 r = sev_launch_measure(kvm, &sev_cmd);
6978 case KVM_SEV_LAUNCH_FINISH:
6979 r = sev_launch_finish(kvm, &sev_cmd);
6981 case KVM_SEV_GUEST_STATUS:
6982 r = sev_guest_status(kvm, &sev_cmd);
6984 case KVM_SEV_DBG_DECRYPT:
6985 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6987 case KVM_SEV_DBG_ENCRYPT:
6988 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6990 case KVM_SEV_LAUNCH_SECRET:
6991 r = sev_launch_secret(kvm, &sev_cmd);
6998 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
7002 mutex_unlock(&kvm->lock);
7006 static int svm_register_enc_region(struct kvm *kvm,
7007 struct kvm_enc_region *range)
7009 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7010 struct enc_region *region;
7013 if (!sev_guest(kvm))
7016 if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7019 region = kzalloc(sizeof(*region), GFP_KERNEL_ACCOUNT);
7023 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
7024 if (!region->pages) {
7030 * The guest may change the memory encryption attribute from C=0 -> C=1
7031 * or vice versa for this memory range. Lets make sure caches are
7032 * flushed to ensure that guest data gets written into memory with
7035 sev_clflush_pages(region->pages, region->npages);
7037 region->uaddr = range->addr;
7038 region->size = range->size;
7040 mutex_lock(&kvm->lock);
7041 list_add_tail(®ion->list, &sev->regions_list);
7042 mutex_unlock(&kvm->lock);
7051 static struct enc_region *
7052 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7054 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7055 struct list_head *head = &sev->regions_list;
7056 struct enc_region *i;
7058 list_for_each_entry(i, head, list) {
7059 if (i->uaddr == range->addr &&
7060 i->size == range->size)
7068 static int svm_unregister_enc_region(struct kvm *kvm,
7069 struct kvm_enc_region *range)
7071 struct enc_region *region;
7074 mutex_lock(&kvm->lock);
7076 if (!sev_guest(kvm)) {
7081 region = find_enc_region(kvm, range);
7087 __unregister_enc_region_locked(kvm, region);
7089 mutex_unlock(&kvm->lock);
7093 mutex_unlock(&kvm->lock);
7097 static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
7103 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7104 uint16_t *vmcs_version)
7106 /* Intel-only feature */
7110 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7114 is_user = svm_get_cpl(vcpu) == 3;
7115 smap = !kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
7118 * Detect and workaround Errata 1096 Fam_17h_00_0Fh
7120 * In non SEV guest, hypervisor will be able to read the guest
7121 * memory to decode the instruction pointer when insn_len is zero
7122 * so we return true to indicate that decoding is possible.
7124 * But in the SEV guest, the guest memory is encrypted with the
7125 * guest specific key and hypervisor will not be able to decode the
7126 * instruction pointer so we will not able to workaround it. Lets
7127 * print the error and request to kill the guest.
7129 if (is_user && smap) {
7130 if (!sev_guest(vcpu->kvm))
7133 pr_err_ratelimited("KVM: Guest triggered AMD Erratum 1096\n");
7134 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7140 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7141 .cpu_has_kvm_support = has_svm,
7142 .disabled_by_bios = is_disabled,
7143 .hardware_setup = svm_hardware_setup,
7144 .hardware_unsetup = svm_hardware_unsetup,
7145 .check_processor_compatibility = svm_check_processor_compat,
7146 .hardware_enable = svm_hardware_enable,
7147 .hardware_disable = svm_hardware_disable,
7148 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7149 .has_emulated_msr = svm_has_emulated_msr,
7151 .vcpu_create = svm_create_vcpu,
7152 .vcpu_free = svm_free_vcpu,
7153 .vcpu_reset = svm_vcpu_reset,
7155 .vm_alloc = svm_vm_alloc,
7156 .vm_free = svm_vm_free,
7157 .vm_init = avic_vm_init,
7158 .vm_destroy = svm_vm_destroy,
7160 .prepare_guest_switch = svm_prepare_guest_switch,
7161 .vcpu_load = svm_vcpu_load,
7162 .vcpu_put = svm_vcpu_put,
7163 .vcpu_blocking = svm_vcpu_blocking,
7164 .vcpu_unblocking = svm_vcpu_unblocking,
7166 .update_bp_intercept = update_bp_intercept,
7167 .get_msr_feature = svm_get_msr_feature,
7168 .get_msr = svm_get_msr,
7169 .set_msr = svm_set_msr,
7170 .get_segment_base = svm_get_segment_base,
7171 .get_segment = svm_get_segment,
7172 .set_segment = svm_set_segment,
7173 .get_cpl = svm_get_cpl,
7174 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7175 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7176 .decache_cr3 = svm_decache_cr3,
7177 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7178 .set_cr0 = svm_set_cr0,
7179 .set_cr3 = svm_set_cr3,
7180 .set_cr4 = svm_set_cr4,
7181 .set_efer = svm_set_efer,
7182 .get_idt = svm_get_idt,
7183 .set_idt = svm_set_idt,
7184 .get_gdt = svm_get_gdt,
7185 .set_gdt = svm_set_gdt,
7186 .get_dr6 = svm_get_dr6,
7187 .set_dr6 = svm_set_dr6,
7188 .set_dr7 = svm_set_dr7,
7189 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7190 .cache_reg = svm_cache_reg,
7191 .get_rflags = svm_get_rflags,
7192 .set_rflags = svm_set_rflags,
7194 .tlb_flush = svm_flush_tlb,
7195 .tlb_flush_gva = svm_flush_tlb_gva,
7197 .run = svm_vcpu_run,
7198 .handle_exit = handle_exit,
7199 .skip_emulated_instruction = skip_emulated_instruction,
7200 .set_interrupt_shadow = svm_set_interrupt_shadow,
7201 .get_interrupt_shadow = svm_get_interrupt_shadow,
7202 .patch_hypercall = svm_patch_hypercall,
7203 .set_irq = svm_set_irq,
7204 .set_nmi = svm_inject_nmi,
7205 .queue_exception = svm_queue_exception,
7206 .cancel_injection = svm_cancel_injection,
7207 .interrupt_allowed = svm_interrupt_allowed,
7208 .nmi_allowed = svm_nmi_allowed,
7209 .get_nmi_mask = svm_get_nmi_mask,
7210 .set_nmi_mask = svm_set_nmi_mask,
7211 .enable_nmi_window = enable_nmi_window,
7212 .enable_irq_window = enable_irq_window,
7213 .update_cr8_intercept = update_cr8_intercept,
7214 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7215 .get_enable_apicv = svm_get_enable_apicv,
7216 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7217 .load_eoi_exitmap = svm_load_eoi_exitmap,
7218 .hwapic_irr_update = svm_hwapic_irr_update,
7219 .hwapic_isr_update = svm_hwapic_isr_update,
7220 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7221 .apicv_post_state_restore = avic_post_state_restore,
7223 .set_tss_addr = svm_set_tss_addr,
7224 .set_identity_map_addr = svm_set_identity_map_addr,
7225 .get_tdp_level = get_npt_level,
7226 .get_mt_mask = svm_get_mt_mask,
7228 .get_exit_info = svm_get_exit_info,
7230 .get_lpage_level = svm_get_lpage_level,
7232 .cpuid_update = svm_cpuid_update,
7234 .rdtscp_supported = svm_rdtscp_supported,
7235 .invpcid_supported = svm_invpcid_supported,
7236 .mpx_supported = svm_mpx_supported,
7237 .xsaves_supported = svm_xsaves_supported,
7238 .umip_emulated = svm_umip_emulated,
7239 .pt_supported = svm_pt_supported,
7241 .set_supported_cpuid = svm_set_supported_cpuid,
7243 .has_wbinvd_exit = svm_has_wbinvd_exit,
7245 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7246 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7248 .set_tdp_cr3 = set_tdp_cr3,
7250 .check_intercept = svm_check_intercept,
7251 .handle_external_intr = svm_handle_external_intr,
7253 .request_immediate_exit = __kvm_request_immediate_exit,
7255 .sched_in = svm_sched_in,
7257 .pmu_ops = &amd_pmu_ops,
7258 .deliver_posted_interrupt = svm_deliver_avic_intr,
7259 .update_pi_irte = svm_update_pi_irte,
7260 .setup_mce = svm_setup_mce,
7262 .smi_allowed = svm_smi_allowed,
7263 .pre_enter_smm = svm_pre_enter_smm,
7264 .pre_leave_smm = svm_pre_leave_smm,
7265 .enable_smi_window = enable_smi_window,
7267 .mem_enc_op = svm_mem_enc_op,
7268 .mem_enc_reg_region = svm_register_enc_region,
7269 .mem_enc_unreg_region = svm_unregister_enc_region,
7271 .nested_enable_evmcs = nested_enable_evmcs,
7272 .nested_get_evmcs_version = nested_get_evmcs_version,
7274 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
7277 static int __init svm_init(void)
7279 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7280 __alignof__(struct vcpu_svm), THIS_MODULE);
7283 static void __exit svm_exit(void)
7288 module_init(svm_init)
7289 module_exit(svm_exit)