1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/frame.h>
4 #include <linux/percpu.h>
6 #include <asm/debugreg.h>
7 #include <asm/mmu_context.h>
17 static bool __read_mostly enable_shadow_vmcs = 1;
18 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
20 static bool __read_mostly nested_early_check = 0;
21 module_param(nested_early_check, bool, S_IRUGO);
23 #define CC(consistency_check) \
25 bool failed = (consistency_check); \
27 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
32 * Hyper-V requires all of these, so mark them as supported even though
33 * they are just treated the same as all-context.
35 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
36 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
37 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
38 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
39 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
41 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
48 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
50 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
51 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
53 struct shadow_vmcs_field {
57 static struct shadow_vmcs_field shadow_read_only_fields[] = {
58 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) },
59 #include "vmcs_shadow_fields.h"
61 static int max_shadow_read_only_fields =
62 ARRAY_SIZE(shadow_read_only_fields);
64 static struct shadow_vmcs_field shadow_read_write_fields[] = {
65 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) },
66 #include "vmcs_shadow_fields.h"
68 static int max_shadow_read_write_fields =
69 ARRAY_SIZE(shadow_read_write_fields);
71 static void init_vmcs_shadow_fields(void)
75 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
76 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
78 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
79 struct shadow_vmcs_field entry = shadow_read_only_fields[i];
80 u16 field = entry.encoding;
82 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
83 (i + 1 == max_shadow_read_only_fields ||
84 shadow_read_only_fields[i + 1].encoding != field + 1))
85 pr_err("Missing field from shadow_read_only_field %x\n",
88 clear_bit(field, vmx_vmread_bitmap);
93 entry.offset += sizeof(u32);
95 shadow_read_only_fields[j++] = entry;
97 max_shadow_read_only_fields = j;
99 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
100 struct shadow_vmcs_field entry = shadow_read_write_fields[i];
101 u16 field = entry.encoding;
103 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
104 (i + 1 == max_shadow_read_write_fields ||
105 shadow_read_write_fields[i + 1].encoding != field + 1))
106 pr_err("Missing field from shadow_read_write_field %x\n",
109 WARN_ONCE(field >= GUEST_ES_AR_BYTES &&
110 field <= GUEST_TR_AR_BYTES,
111 "Update vmcs12_write_any() to drop reserved bits from AR_BYTES");
114 * PML and the preemption timer can be emulated, but the
115 * processor cannot vmwrite to fields that don't exist
119 case GUEST_PML_INDEX:
120 if (!cpu_has_vmx_pml())
123 case VMX_PREEMPTION_TIMER_VALUE:
124 if (!cpu_has_vmx_preemption_timer())
127 case GUEST_INTR_STATUS:
128 if (!cpu_has_vmx_apicv())
135 clear_bit(field, vmx_vmwrite_bitmap);
136 clear_bit(field, vmx_vmread_bitmap);
141 entry.offset += sizeof(u32);
143 shadow_read_write_fields[j++] = entry;
145 max_shadow_read_write_fields = j;
149 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
150 * set the success or error code of an emulated VMX instruction (as specified
151 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
154 static int nested_vmx_succeed(struct kvm_vcpu *vcpu)
156 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
157 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
158 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
159 return kvm_skip_emulated_instruction(vcpu);
162 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
164 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
165 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
166 X86_EFLAGS_SF | X86_EFLAGS_OF))
168 return kvm_skip_emulated_instruction(vcpu);
171 static int nested_vmx_failValid(struct kvm_vcpu *vcpu,
172 u32 vm_instruction_error)
174 struct vcpu_vmx *vmx = to_vmx(vcpu);
177 * failValid writes the error number to the current VMCS, which
178 * can't be done if there isn't a current VMCS.
180 if (vmx->nested.current_vmptr == -1ull && !vmx->nested.hv_evmcs)
181 return nested_vmx_failInvalid(vcpu);
183 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
184 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
185 X86_EFLAGS_SF | X86_EFLAGS_OF))
187 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
189 * We don't need to force a shadow sync because
190 * VM_INSTRUCTION_ERROR is not shadowed
192 return kvm_skip_emulated_instruction(vcpu);
195 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
197 /* TODO: not to reset guest simply here. */
198 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
199 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
202 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
204 return fixed_bits_valid(control, low, high);
207 static inline u64 vmx_control_msr(u32 low, u32 high)
209 return low | ((u64)high << 32);
212 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
214 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
215 vmcs_write64(VMCS_LINK_POINTER, -1ull);
216 vmx->nested.need_vmcs12_to_shadow_sync = false;
219 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu)
221 struct vcpu_vmx *vmx = to_vmx(vcpu);
223 if (!vmx->nested.hv_evmcs)
226 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true);
227 vmx->nested.hv_evmcs_vmptr = -1ull;
228 vmx->nested.hv_evmcs = NULL;
232 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
233 * just stops using VMX.
235 static void free_nested(struct kvm_vcpu *vcpu)
237 struct vcpu_vmx *vmx = to_vmx(vcpu);
239 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
242 kvm_clear_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
244 vmx->nested.vmxon = false;
245 vmx->nested.smm.vmxon = false;
246 free_vpid(vmx->nested.vpid02);
247 vmx->nested.posted_intr_nv = -1;
248 vmx->nested.current_vmptr = -1ull;
249 if (enable_shadow_vmcs) {
250 vmx_disable_shadow_vmcs(vmx);
251 vmcs_clear(vmx->vmcs01.shadow_vmcs);
252 free_vmcs(vmx->vmcs01.shadow_vmcs);
253 vmx->vmcs01.shadow_vmcs = NULL;
255 kfree(vmx->nested.cached_vmcs12);
256 vmx->nested.cached_vmcs12 = NULL;
257 kfree(vmx->nested.cached_shadow_vmcs12);
258 vmx->nested.cached_shadow_vmcs12 = NULL;
259 /* Unpin physical memory we referred to in the vmcs02 */
260 if (vmx->nested.apic_access_page) {
261 kvm_release_page_clean(vmx->nested.apic_access_page);
262 vmx->nested.apic_access_page = NULL;
264 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
265 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
266 vmx->nested.pi_desc = NULL;
268 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
270 nested_release_evmcs(vcpu);
272 free_loaded_vmcs(&vmx->nested.vmcs02);
275 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx,
276 struct loaded_vmcs *prev)
278 struct vmcs_host_state *dest, *src;
280 if (unlikely(!vmx->guest_state_loaded))
283 src = &prev->host_state;
284 dest = &vmx->loaded_vmcs->host_state;
286 vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base);
287 dest->ldt_sel = src->ldt_sel;
289 dest->ds_sel = src->ds_sel;
290 dest->es_sel = src->es_sel;
294 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
296 struct vcpu_vmx *vmx = to_vmx(vcpu);
297 struct loaded_vmcs *prev;
300 if (vmx->loaded_vmcs == vmcs)
304 prev = vmx->loaded_vmcs;
305 vmx->loaded_vmcs = vmcs;
306 vmx_vcpu_load_vmcs(vcpu, cpu);
307 vmx_sync_vmcs_host_state(vmx, prev);
310 vmx_segment_cache_clear(vmx);
314 * Ensure that the current vmcs of the logical processor is the
315 * vmcs01 of the vcpu before calling free_nested().
317 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu)
320 vmx_leave_nested(vcpu);
321 vmx_switch_vmcs(vcpu, &to_vmx(vcpu)->vmcs01);
326 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
327 struct x86_exception *fault)
329 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
330 struct vcpu_vmx *vmx = to_vmx(vcpu);
332 unsigned long exit_qualification = vcpu->arch.exit_qualification;
334 if (vmx->nested.pml_full) {
335 exit_reason = EXIT_REASON_PML_FULL;
336 vmx->nested.pml_full = false;
337 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
338 } else if (fault->error_code & PFERR_RSVD_MASK)
339 exit_reason = EXIT_REASON_EPT_MISCONFIG;
341 exit_reason = EXIT_REASON_EPT_VIOLATION;
343 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
344 vmcs12->guest_physical_address = fault->address;
347 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
349 WARN_ON(mmu_is_nested(vcpu));
351 vcpu->arch.mmu = &vcpu->arch.guest_mmu;
352 kvm_init_shadow_ept_mmu(vcpu,
353 to_vmx(vcpu)->nested.msrs.ept_caps &
354 VMX_EPT_EXECUTE_ONLY_BIT,
355 nested_ept_ad_enabled(vcpu),
356 nested_ept_get_cr3(vcpu));
357 vcpu->arch.mmu->set_cr3 = vmx_set_cr3;
358 vcpu->arch.mmu->get_cr3 = nested_ept_get_cr3;
359 vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault;
360 vcpu->arch.mmu->get_pdptr = kvm_pdptr_read;
362 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
365 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
367 vcpu->arch.mmu = &vcpu->arch.root_mmu;
368 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
371 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
374 bool inequality, bit;
376 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
378 (error_code & vmcs12->page_fault_error_code_mask) !=
379 vmcs12->page_fault_error_code_match;
380 return inequality ^ bit;
385 * KVM wants to inject page-faults which it got to the guest. This function
386 * checks whether in a nested guest, we need to inject them to L1 or L2.
388 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
390 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
391 unsigned int nr = vcpu->arch.exception.nr;
392 bool has_payload = vcpu->arch.exception.has_payload;
393 unsigned long payload = vcpu->arch.exception.payload;
395 if (nr == PF_VECTOR) {
396 if (vcpu->arch.exception.nested_apf) {
397 *exit_qual = vcpu->arch.apf.nested_apf_token;
400 if (nested_vmx_is_page_fault_vmexit(vmcs12,
401 vcpu->arch.exception.error_code)) {
402 *exit_qual = has_payload ? payload : vcpu->arch.cr2;
405 } else if (vmcs12->exception_bitmap & (1u << nr)) {
406 if (nr == DB_VECTOR) {
408 payload = vcpu->arch.dr6;
409 payload &= ~(DR6_FIXED_1 | DR6_BT);
412 *exit_qual = payload;
422 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
423 struct x86_exception *fault)
425 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
427 WARN_ON(!is_guest_mode(vcpu));
429 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
430 !to_vmx(vcpu)->nested.nested_run_pending) {
431 vmcs12->vm_exit_intr_error_code = fault->error_code;
432 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
433 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
434 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
437 kvm_inject_page_fault(vcpu, fault);
441 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
443 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
446 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
447 struct vmcs12 *vmcs12)
449 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
452 if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) ||
453 CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b)))
459 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
460 struct vmcs12 *vmcs12)
462 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
465 if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap)))
471 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
472 struct vmcs12 *vmcs12)
474 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
477 if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)))
484 * Check if MSR is intercepted for L01 MSR bitmap.
486 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
488 unsigned long *msr_bitmap;
489 int f = sizeof(unsigned long);
491 if (!cpu_has_vmx_msr_bitmap())
494 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
497 return !!test_bit(msr, msr_bitmap + 0x800 / f);
498 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
500 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
507 * If a msr is allowed by L0, we should check whether it is allowed by L1.
508 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
510 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
511 unsigned long *msr_bitmap_nested,
514 int f = sizeof(unsigned long);
517 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
518 * have the write-low and read-high bitmap offsets the wrong way round.
519 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
522 if (type & MSR_TYPE_R &&
523 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
525 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
527 if (type & MSR_TYPE_W &&
528 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
530 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
532 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
534 if (type & MSR_TYPE_R &&
535 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
537 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
539 if (type & MSR_TYPE_W &&
540 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
542 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
547 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap) {
550 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
551 unsigned word = msr / BITS_PER_LONG;
553 msr_bitmap[word] = ~0;
554 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
559 * Merge L0's and L1's MSR bitmap, return false to indicate that
560 * we do not use the hardware.
562 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
563 struct vmcs12 *vmcs12)
566 unsigned long *msr_bitmap_l1;
567 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
568 struct kvm_host_map *map = &to_vmx(vcpu)->nested.msr_bitmap_map;
570 /* Nothing to do if the MSR bitmap is not in use. */
571 if (!cpu_has_vmx_msr_bitmap() ||
572 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
575 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map))
578 msr_bitmap_l1 = (unsigned long *)map->hva;
581 * To keep the control flow simple, pay eight 8-byte writes (sixteen
582 * 4-byte writes on 32-bit systems) up front to enable intercepts for
583 * the x2APIC MSR range and selectively disable them below.
585 enable_x2apic_msr_intercepts(msr_bitmap_l0);
587 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
588 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
590 * L0 need not intercept reads for MSRs between 0x800
591 * and 0x8ff, it just lets the processor take the value
592 * from the virtual-APIC page; take those 256 bits
593 * directly from the L1 bitmap.
595 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
596 unsigned word = msr / BITS_PER_LONG;
598 msr_bitmap_l0[word] = msr_bitmap_l1[word];
602 nested_vmx_disable_intercept_for_msr(
603 msr_bitmap_l1, msr_bitmap_l0,
604 X2APIC_MSR(APIC_TASKPRI),
605 MSR_TYPE_R | MSR_TYPE_W);
607 if (nested_cpu_has_vid(vmcs12)) {
608 nested_vmx_disable_intercept_for_msr(
609 msr_bitmap_l1, msr_bitmap_l0,
610 X2APIC_MSR(APIC_EOI),
612 nested_vmx_disable_intercept_for_msr(
613 msr_bitmap_l1, msr_bitmap_l0,
614 X2APIC_MSR(APIC_SELF_IPI),
619 /* KVM unconditionally exposes the FS/GS base MSRs to L1. */
620 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
621 MSR_FS_BASE, MSR_TYPE_RW);
623 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
624 MSR_GS_BASE, MSR_TYPE_RW);
626 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
627 MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
630 * Checking the L0->L1 bitmap is trying to verify two things:
632 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
633 * ensures that we do not accidentally generate an L02 MSR bitmap
634 * from the L12 MSR bitmap that is too permissive.
635 * 2. That L1 or L2s have actually used the MSR. This avoids
636 * unnecessarily merging of the bitmap if the MSR is unused. This
637 * works properly because we only update the L01 MSR bitmap lazily.
638 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
639 * updated to reflect this when L1 (or its L2s) actually write to
642 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL))
643 nested_vmx_disable_intercept_for_msr(
644 msr_bitmap_l1, msr_bitmap_l0,
646 MSR_TYPE_R | MSR_TYPE_W);
648 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD))
649 nested_vmx_disable_intercept_for_msr(
650 msr_bitmap_l1, msr_bitmap_l0,
654 kvm_vcpu_unmap(vcpu, &to_vmx(vcpu)->nested.msr_bitmap_map, false);
659 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
660 struct vmcs12 *vmcs12)
662 struct kvm_host_map map;
663 struct vmcs12 *shadow;
665 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
666 vmcs12->vmcs_link_pointer == -1ull)
669 shadow = get_shadow_vmcs12(vcpu);
671 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map))
674 memcpy(shadow, map.hva, VMCS12_SIZE);
675 kvm_vcpu_unmap(vcpu, &map, false);
678 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
679 struct vmcs12 *vmcs12)
681 struct vcpu_vmx *vmx = to_vmx(vcpu);
683 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
684 vmcs12->vmcs_link_pointer == -1ull)
687 kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
688 get_shadow_vmcs12(vcpu), VMCS12_SIZE);
692 * In nested virtualization, check if L1 has set
693 * VM_EXIT_ACK_INTR_ON_EXIT
695 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
697 return get_vmcs12(vcpu)->vm_exit_controls &
698 VM_EXIT_ACK_INTR_ON_EXIT;
701 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
703 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
706 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
707 struct vmcs12 *vmcs12)
709 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
710 CC(!page_address_valid(vcpu, vmcs12->apic_access_addr)))
716 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
717 struct vmcs12 *vmcs12)
719 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
720 !nested_cpu_has_apic_reg_virt(vmcs12) &&
721 !nested_cpu_has_vid(vmcs12) &&
722 !nested_cpu_has_posted_intr(vmcs12))
726 * If virtualize x2apic mode is enabled,
727 * virtualize apic access must be disabled.
729 if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) &&
730 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)))
734 * If virtual interrupt delivery is enabled,
735 * we must exit on external interrupts.
737 if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu)))
741 * bits 15:8 should be zero in posted_intr_nv,
742 * the descriptor address has been already checked
743 * in nested_get_vmcs12_pages.
745 * bits 5:0 of posted_intr_desc_addr should be zero.
747 if (nested_cpu_has_posted_intr(vmcs12) &&
748 (CC(!nested_cpu_has_vid(vmcs12)) ||
749 CC(!nested_exit_intr_ack_set(vcpu)) ||
750 CC((vmcs12->posted_intr_nv & 0xff00)) ||
751 CC((vmcs12->posted_intr_desc_addr & 0x3f)) ||
752 CC((vmcs12->posted_intr_desc_addr >> cpuid_maxphyaddr(vcpu)))))
755 /* tpr shadow is needed by all apicv features. */
756 if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)))
762 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
769 maxphyaddr = cpuid_maxphyaddr(vcpu);
770 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
771 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr)
777 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu,
778 struct vmcs12 *vmcs12)
780 if (CC(nested_vmx_check_msr_switch(vcpu,
781 vmcs12->vm_exit_msr_load_count,
782 vmcs12->vm_exit_msr_load_addr)) ||
783 CC(nested_vmx_check_msr_switch(vcpu,
784 vmcs12->vm_exit_msr_store_count,
785 vmcs12->vm_exit_msr_store_addr)))
791 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu,
792 struct vmcs12 *vmcs12)
794 if (CC(nested_vmx_check_msr_switch(vcpu,
795 vmcs12->vm_entry_msr_load_count,
796 vmcs12->vm_entry_msr_load_addr)))
802 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
803 struct vmcs12 *vmcs12)
805 if (!nested_cpu_has_pml(vmcs12))
808 if (CC(!nested_cpu_has_ept(vmcs12)) ||
809 CC(!page_address_valid(vcpu, vmcs12->pml_address)))
815 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu,
816 struct vmcs12 *vmcs12)
818 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) &&
819 !nested_cpu_has_ept(vmcs12)))
824 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu,
825 struct vmcs12 *vmcs12)
827 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) &&
828 !nested_cpu_has_ept(vmcs12)))
833 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
834 struct vmcs12 *vmcs12)
836 if (!nested_cpu_has_shadow_vmcs(vmcs12))
839 if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) ||
840 CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap)))
846 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
847 struct vmx_msr_entry *e)
849 /* x2APIC MSR accesses are not allowed */
850 if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8))
852 if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */
853 CC(e->index == MSR_IA32_UCODE_REV))
855 if (CC(e->reserved != 0))
860 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
861 struct vmx_msr_entry *e)
863 if (CC(e->index == MSR_FS_BASE) ||
864 CC(e->index == MSR_GS_BASE) ||
865 CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */
866 nested_vmx_msr_check_common(vcpu, e))
871 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
872 struct vmx_msr_entry *e)
874 if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */
875 nested_vmx_msr_check_common(vcpu, e))
880 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu)
882 struct vcpu_vmx *vmx = to_vmx(vcpu);
883 u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
884 vmx->nested.msrs.misc_high);
886 return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER;
890 * Load guest's/host's msr at nested entry/exit.
891 * return 0 for success, entry index for failure.
893 * One of the failure modes for MSR load/store is when a list exceeds the
894 * virtual hardware's capacity. To maintain compatibility with hardware inasmuch
895 * as possible, process all valid entries before failing rather than precheck
896 * for a capacity violation.
898 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
901 struct vmx_msr_entry e;
902 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
904 for (i = 0; i < count; i++) {
905 if (unlikely(i >= max_msr_list_size))
908 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
910 pr_debug_ratelimited(
911 "%s cannot read MSR entry (%u, 0x%08llx)\n",
912 __func__, i, gpa + i * sizeof(e));
915 if (nested_vmx_load_msr_check(vcpu, &e)) {
916 pr_debug_ratelimited(
917 "%s check failed (%u, 0x%x, 0x%x)\n",
918 __func__, i, e.index, e.reserved);
921 if (kvm_set_msr(vcpu, e.index, e.value)) {
922 pr_debug_ratelimited(
923 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
924 __func__, i, e.index, e.value);
933 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu,
937 struct vcpu_vmx *vmx = to_vmx(vcpu);
940 * If the L0 hypervisor stored a more accurate value for the TSC that
941 * does not include the time taken for emulation of the L2->L1
942 * VM-exit in L0, use the more accurate value.
944 if (msr_index == MSR_IA32_TSC) {
945 int index = vmx_find_msr_index(&vmx->msr_autostore.guest,
949 u64 val = vmx->msr_autostore.guest.val[index].value;
951 *data = kvm_read_l1_tsc(vcpu, val);
956 if (kvm_get_msr(vcpu, msr_index, data)) {
957 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__,
964 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i,
965 struct vmx_msr_entry *e)
967 if (kvm_vcpu_read_guest(vcpu,
968 gpa + i * sizeof(*e),
969 e, 2 * sizeof(u32))) {
970 pr_debug_ratelimited(
971 "%s cannot read MSR entry (%u, 0x%08llx)\n",
972 __func__, i, gpa + i * sizeof(*e));
975 if (nested_vmx_store_msr_check(vcpu, e)) {
976 pr_debug_ratelimited(
977 "%s check failed (%u, 0x%x, 0x%x)\n",
978 __func__, i, e->index, e->reserved);
984 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
988 struct vmx_msr_entry e;
989 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu);
991 for (i = 0; i < count; i++) {
992 if (unlikely(i >= max_msr_list_size))
995 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
998 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data))
1001 if (kvm_vcpu_write_guest(vcpu,
1002 gpa + i * sizeof(e) +
1003 offsetof(struct vmx_msr_entry, value),
1004 &data, sizeof(data))) {
1005 pr_debug_ratelimited(
1006 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
1007 __func__, i, e.index, data);
1014 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index)
1016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1017 u32 count = vmcs12->vm_exit_msr_store_count;
1018 u64 gpa = vmcs12->vm_exit_msr_store_addr;
1019 struct vmx_msr_entry e;
1022 for (i = 0; i < count; i++) {
1023 if (!read_and_check_msr_entry(vcpu, gpa, i, &e))
1026 if (e.index == msr_index)
1032 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu,
1035 struct vcpu_vmx *vmx = to_vmx(vcpu);
1036 struct vmx_msrs *autostore = &vmx->msr_autostore.guest;
1037 bool in_vmcs12_store_list;
1038 int msr_autostore_index;
1039 bool in_autostore_list;
1042 msr_autostore_index = vmx_find_msr_index(autostore, msr_index);
1043 in_autostore_list = msr_autostore_index >= 0;
1044 in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index);
1046 if (in_vmcs12_store_list && !in_autostore_list) {
1047 if (autostore->nr == NR_LOADSTORE_MSRS) {
1049 * Emulated VMEntry does not fail here. Instead a less
1050 * accurate value will be returned by
1051 * nested_vmx_get_vmexit_msr_value() using kvm_get_msr()
1052 * instead of reading the value from the vmcs02 VMExit
1055 pr_warn_ratelimited(
1056 "Not enough msr entries in msr_autostore. Can't add msr %x\n",
1060 last = autostore->nr++;
1061 autostore->val[last].index = msr_index;
1062 } else if (!in_vmcs12_store_list && in_autostore_list) {
1063 last = --autostore->nr;
1064 autostore->val[msr_autostore_index] = autostore->val[last];
1068 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
1070 unsigned long invalid_mask;
1072 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1073 return (val & invalid_mask) == 0;
1077 * Load guest's/host's cr3 at nested entry/exit. @nested_ept is true if we are
1078 * emulating VM-Entry into a guest with EPT enabled. On failure, the expected
1079 * Exit Qualification (for a VM-Entry consistency check VM-Exit) is assigned to
1080 * @entry_failure_code.
1082 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
1083 u32 *entry_failure_code)
1085 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
1086 if (CC(!nested_cr3_valid(vcpu, cr3))) {
1087 *entry_failure_code = ENTRY_FAIL_DEFAULT;
1092 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
1093 * must not be dereferenced.
1095 if (is_pae_paging(vcpu) && !nested_ept) {
1096 if (CC(!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))) {
1097 *entry_failure_code = ENTRY_FAIL_PDPTE;
1104 kvm_mmu_new_cr3(vcpu, cr3, false);
1106 vcpu->arch.cr3 = cr3;
1107 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1109 kvm_init_mmu(vcpu, false);
1115 * Returns if KVM is able to config CPU to tag TLB entries
1116 * populated by L2 differently than TLB entries populated
1119 * If L0 uses EPT, L1 and L2 run with different EPTP because
1120 * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries
1121 * are tagged with different EPTP.
1123 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
1124 * with different VPID (L1 entries are tagged with vmx->vpid
1125 * while L2 entries are tagged with vmx->nested.vpid02).
1127 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu)
1129 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1131 return enable_ept ||
1132 (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02);
1135 static u16 nested_get_vpid02(struct kvm_vcpu *vcpu)
1137 struct vcpu_vmx *vmx = to_vmx(vcpu);
1139 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid;
1142 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
1147 return (superset | subset) == superset;
1150 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
1152 const u64 feature_and_reserved =
1153 /* feature (except bit 48; see below) */
1154 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
1156 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
1157 u64 vmx_basic = vmx->nested.msrs.basic;
1159 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
1163 * KVM does not emulate a version of VMX that constrains physical
1164 * addresses of VMX structures (e.g. VMCS) to 32-bits.
1166 if (data & BIT_ULL(48))
1169 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
1170 vmx_basic_vmcs_revision_id(data))
1173 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
1176 vmx->nested.msrs.basic = data;
1181 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1186 switch (msr_index) {
1187 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1188 lowp = &vmx->nested.msrs.pinbased_ctls_low;
1189 highp = &vmx->nested.msrs.pinbased_ctls_high;
1191 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1192 lowp = &vmx->nested.msrs.procbased_ctls_low;
1193 highp = &vmx->nested.msrs.procbased_ctls_high;
1195 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1196 lowp = &vmx->nested.msrs.exit_ctls_low;
1197 highp = &vmx->nested.msrs.exit_ctls_high;
1199 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1200 lowp = &vmx->nested.msrs.entry_ctls_low;
1201 highp = &vmx->nested.msrs.entry_ctls_high;
1203 case MSR_IA32_VMX_PROCBASED_CTLS2:
1204 lowp = &vmx->nested.msrs.secondary_ctls_low;
1205 highp = &vmx->nested.msrs.secondary_ctls_high;
1211 supported = vmx_control_msr(*lowp, *highp);
1213 /* Check must-be-1 bits are still 1. */
1214 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
1217 /* Check must-be-0 bits are still 0. */
1218 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
1222 *highp = data >> 32;
1226 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
1228 const u64 feature_and_reserved_bits =
1230 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
1231 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
1233 GENMASK_ULL(13, 9) | BIT_ULL(31);
1236 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
1237 vmx->nested.msrs.misc_high);
1239 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
1242 if ((vmx->nested.msrs.pinbased_ctls_high &
1243 PIN_BASED_VMX_PREEMPTION_TIMER) &&
1244 vmx_misc_preemption_timer_rate(data) !=
1245 vmx_misc_preemption_timer_rate(vmx_misc))
1248 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
1251 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
1254 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
1257 vmx->nested.msrs.misc_low = data;
1258 vmx->nested.msrs.misc_high = data >> 32;
1263 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
1265 u64 vmx_ept_vpid_cap;
1267 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
1268 vmx->nested.msrs.vpid_caps);
1270 /* Every bit is either reserved or a feature bit. */
1271 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
1274 vmx->nested.msrs.ept_caps = data;
1275 vmx->nested.msrs.vpid_caps = data >> 32;
1279 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
1283 switch (msr_index) {
1284 case MSR_IA32_VMX_CR0_FIXED0:
1285 msr = &vmx->nested.msrs.cr0_fixed0;
1287 case MSR_IA32_VMX_CR4_FIXED0:
1288 msr = &vmx->nested.msrs.cr4_fixed0;
1295 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
1296 * must be 1 in the restored value.
1298 if (!is_bitwise_subset(data, *msr, -1ULL))
1306 * Called when userspace is restoring VMX MSRs.
1308 * Returns 0 on success, non-0 otherwise.
1310 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1312 struct vcpu_vmx *vmx = to_vmx(vcpu);
1315 * Don't allow changes to the VMX capability MSRs while the vCPU
1316 * is in VMX operation.
1318 if (vmx->nested.vmxon)
1321 switch (msr_index) {
1322 case MSR_IA32_VMX_BASIC:
1323 return vmx_restore_vmx_basic(vmx, data);
1324 case MSR_IA32_VMX_PINBASED_CTLS:
1325 case MSR_IA32_VMX_PROCBASED_CTLS:
1326 case MSR_IA32_VMX_EXIT_CTLS:
1327 case MSR_IA32_VMX_ENTRY_CTLS:
1329 * The "non-true" VMX capability MSRs are generated from the
1330 * "true" MSRs, so we do not support restoring them directly.
1332 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
1333 * should restore the "true" MSRs with the must-be-1 bits
1334 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
1335 * DEFAULT SETTINGS".
1338 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1339 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1340 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1341 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1342 case MSR_IA32_VMX_PROCBASED_CTLS2:
1343 return vmx_restore_control_msr(vmx, msr_index, data);
1344 case MSR_IA32_VMX_MISC:
1345 return vmx_restore_vmx_misc(vmx, data);
1346 case MSR_IA32_VMX_CR0_FIXED0:
1347 case MSR_IA32_VMX_CR4_FIXED0:
1348 return vmx_restore_fixed0_msr(vmx, msr_index, data);
1349 case MSR_IA32_VMX_CR0_FIXED1:
1350 case MSR_IA32_VMX_CR4_FIXED1:
1352 * These MSRs are generated based on the vCPU's CPUID, so we
1353 * do not support restoring them directly.
1356 case MSR_IA32_VMX_EPT_VPID_CAP:
1357 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
1358 case MSR_IA32_VMX_VMCS_ENUM:
1359 vmx->nested.msrs.vmcs_enum = data;
1361 case MSR_IA32_VMX_VMFUNC:
1362 if (data & ~vmx->nested.msrs.vmfunc_controls)
1364 vmx->nested.msrs.vmfunc_controls = data;
1368 * The rest of the VMX capability MSRs do not support restore.
1374 /* Returns 0 on success, non-0 otherwise. */
1375 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
1377 switch (msr_index) {
1378 case MSR_IA32_VMX_BASIC:
1379 *pdata = msrs->basic;
1381 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1382 case MSR_IA32_VMX_PINBASED_CTLS:
1383 *pdata = vmx_control_msr(
1384 msrs->pinbased_ctls_low,
1385 msrs->pinbased_ctls_high);
1386 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
1387 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1389 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1390 case MSR_IA32_VMX_PROCBASED_CTLS:
1391 *pdata = vmx_control_msr(
1392 msrs->procbased_ctls_low,
1393 msrs->procbased_ctls_high);
1394 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
1395 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
1397 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1398 case MSR_IA32_VMX_EXIT_CTLS:
1399 *pdata = vmx_control_msr(
1400 msrs->exit_ctls_low,
1401 msrs->exit_ctls_high);
1402 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
1403 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
1405 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1406 case MSR_IA32_VMX_ENTRY_CTLS:
1407 *pdata = vmx_control_msr(
1408 msrs->entry_ctls_low,
1409 msrs->entry_ctls_high);
1410 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
1411 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
1413 case MSR_IA32_VMX_MISC:
1414 *pdata = vmx_control_msr(
1418 case MSR_IA32_VMX_CR0_FIXED0:
1419 *pdata = msrs->cr0_fixed0;
1421 case MSR_IA32_VMX_CR0_FIXED1:
1422 *pdata = msrs->cr0_fixed1;
1424 case MSR_IA32_VMX_CR4_FIXED0:
1425 *pdata = msrs->cr4_fixed0;
1427 case MSR_IA32_VMX_CR4_FIXED1:
1428 *pdata = msrs->cr4_fixed1;
1430 case MSR_IA32_VMX_VMCS_ENUM:
1431 *pdata = msrs->vmcs_enum;
1433 case MSR_IA32_VMX_PROCBASED_CTLS2:
1434 *pdata = vmx_control_msr(
1435 msrs->secondary_ctls_low,
1436 msrs->secondary_ctls_high);
1438 case MSR_IA32_VMX_EPT_VPID_CAP:
1439 *pdata = msrs->ept_caps |
1440 ((u64)msrs->vpid_caps << 32);
1442 case MSR_IA32_VMX_VMFUNC:
1443 *pdata = msrs->vmfunc_controls;
1453 * Copy the writable VMCS shadow fields back to the VMCS12, in case they have
1454 * been modified by the L1 guest. Note, "writable" in this context means
1455 * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of
1456 * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only"
1457 * VM-exit information fields (which are actually writable if the vCPU is
1458 * configured to support "VMWRITE to any supported field in the VMCS").
1460 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
1462 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1463 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1464 struct shadow_vmcs_field field;
1468 if (WARN_ON(!shadow_vmcs))
1473 vmcs_load(shadow_vmcs);
1475 for (i = 0; i < max_shadow_read_write_fields; i++) {
1476 field = shadow_read_write_fields[i];
1477 val = __vmcs_readl(field.encoding);
1478 vmcs12_write_any(vmcs12, field.encoding, field.offset, val);
1481 vmcs_clear(shadow_vmcs);
1482 vmcs_load(vmx->loaded_vmcs->vmcs);
1487 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
1489 const struct shadow_vmcs_field *fields[] = {
1490 shadow_read_write_fields,
1491 shadow_read_only_fields
1493 const int max_fields[] = {
1494 max_shadow_read_write_fields,
1495 max_shadow_read_only_fields
1497 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
1498 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu);
1499 struct shadow_vmcs_field field;
1503 if (WARN_ON(!shadow_vmcs))
1506 vmcs_load(shadow_vmcs);
1508 for (q = 0; q < ARRAY_SIZE(fields); q++) {
1509 for (i = 0; i < max_fields[q]; i++) {
1510 field = fields[q][i];
1511 val = vmcs12_read_any(vmcs12, field.encoding,
1513 __vmcs_writel(field.encoding, val);
1517 vmcs_clear(shadow_vmcs);
1518 vmcs_load(vmx->loaded_vmcs->vmcs);
1521 static int copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx)
1523 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1524 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1526 /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */
1527 vmcs12->tpr_threshold = evmcs->tpr_threshold;
1528 vmcs12->guest_rip = evmcs->guest_rip;
1530 if (unlikely(!(evmcs->hv_clean_fields &
1531 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) {
1532 vmcs12->guest_rsp = evmcs->guest_rsp;
1533 vmcs12->guest_rflags = evmcs->guest_rflags;
1534 vmcs12->guest_interruptibility_info =
1535 evmcs->guest_interruptibility_info;
1538 if (unlikely(!(evmcs->hv_clean_fields &
1539 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) {
1540 vmcs12->cpu_based_vm_exec_control =
1541 evmcs->cpu_based_vm_exec_control;
1544 if (unlikely(!(evmcs->hv_clean_fields &
1545 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) {
1546 vmcs12->exception_bitmap = evmcs->exception_bitmap;
1549 if (unlikely(!(evmcs->hv_clean_fields &
1550 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) {
1551 vmcs12->vm_entry_controls = evmcs->vm_entry_controls;
1554 if (unlikely(!(evmcs->hv_clean_fields &
1555 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) {
1556 vmcs12->vm_entry_intr_info_field =
1557 evmcs->vm_entry_intr_info_field;
1558 vmcs12->vm_entry_exception_error_code =
1559 evmcs->vm_entry_exception_error_code;
1560 vmcs12->vm_entry_instruction_len =
1561 evmcs->vm_entry_instruction_len;
1564 if (unlikely(!(evmcs->hv_clean_fields &
1565 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) {
1566 vmcs12->host_ia32_pat = evmcs->host_ia32_pat;
1567 vmcs12->host_ia32_efer = evmcs->host_ia32_efer;
1568 vmcs12->host_cr0 = evmcs->host_cr0;
1569 vmcs12->host_cr3 = evmcs->host_cr3;
1570 vmcs12->host_cr4 = evmcs->host_cr4;
1571 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp;
1572 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip;
1573 vmcs12->host_rip = evmcs->host_rip;
1574 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs;
1575 vmcs12->host_es_selector = evmcs->host_es_selector;
1576 vmcs12->host_cs_selector = evmcs->host_cs_selector;
1577 vmcs12->host_ss_selector = evmcs->host_ss_selector;
1578 vmcs12->host_ds_selector = evmcs->host_ds_selector;
1579 vmcs12->host_fs_selector = evmcs->host_fs_selector;
1580 vmcs12->host_gs_selector = evmcs->host_gs_selector;
1581 vmcs12->host_tr_selector = evmcs->host_tr_selector;
1584 if (unlikely(!(evmcs->hv_clean_fields &
1585 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) {
1586 vmcs12->pin_based_vm_exec_control =
1587 evmcs->pin_based_vm_exec_control;
1588 vmcs12->vm_exit_controls = evmcs->vm_exit_controls;
1589 vmcs12->secondary_vm_exec_control =
1590 evmcs->secondary_vm_exec_control;
1593 if (unlikely(!(evmcs->hv_clean_fields &
1594 HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) {
1595 vmcs12->io_bitmap_a = evmcs->io_bitmap_a;
1596 vmcs12->io_bitmap_b = evmcs->io_bitmap_b;
1599 if (unlikely(!(evmcs->hv_clean_fields &
1600 HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) {
1601 vmcs12->msr_bitmap = evmcs->msr_bitmap;
1604 if (unlikely(!(evmcs->hv_clean_fields &
1605 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) {
1606 vmcs12->guest_es_base = evmcs->guest_es_base;
1607 vmcs12->guest_cs_base = evmcs->guest_cs_base;
1608 vmcs12->guest_ss_base = evmcs->guest_ss_base;
1609 vmcs12->guest_ds_base = evmcs->guest_ds_base;
1610 vmcs12->guest_fs_base = evmcs->guest_fs_base;
1611 vmcs12->guest_gs_base = evmcs->guest_gs_base;
1612 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base;
1613 vmcs12->guest_tr_base = evmcs->guest_tr_base;
1614 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base;
1615 vmcs12->guest_idtr_base = evmcs->guest_idtr_base;
1616 vmcs12->guest_es_limit = evmcs->guest_es_limit;
1617 vmcs12->guest_cs_limit = evmcs->guest_cs_limit;
1618 vmcs12->guest_ss_limit = evmcs->guest_ss_limit;
1619 vmcs12->guest_ds_limit = evmcs->guest_ds_limit;
1620 vmcs12->guest_fs_limit = evmcs->guest_fs_limit;
1621 vmcs12->guest_gs_limit = evmcs->guest_gs_limit;
1622 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit;
1623 vmcs12->guest_tr_limit = evmcs->guest_tr_limit;
1624 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit;
1625 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit;
1626 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes;
1627 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes;
1628 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes;
1629 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes;
1630 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes;
1631 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes;
1632 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes;
1633 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes;
1634 vmcs12->guest_es_selector = evmcs->guest_es_selector;
1635 vmcs12->guest_cs_selector = evmcs->guest_cs_selector;
1636 vmcs12->guest_ss_selector = evmcs->guest_ss_selector;
1637 vmcs12->guest_ds_selector = evmcs->guest_ds_selector;
1638 vmcs12->guest_fs_selector = evmcs->guest_fs_selector;
1639 vmcs12->guest_gs_selector = evmcs->guest_gs_selector;
1640 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector;
1641 vmcs12->guest_tr_selector = evmcs->guest_tr_selector;
1644 if (unlikely(!(evmcs->hv_clean_fields &
1645 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) {
1646 vmcs12->tsc_offset = evmcs->tsc_offset;
1647 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr;
1648 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap;
1651 if (unlikely(!(evmcs->hv_clean_fields &
1652 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) {
1653 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask;
1654 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask;
1655 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow;
1656 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow;
1657 vmcs12->guest_cr0 = evmcs->guest_cr0;
1658 vmcs12->guest_cr3 = evmcs->guest_cr3;
1659 vmcs12->guest_cr4 = evmcs->guest_cr4;
1660 vmcs12->guest_dr7 = evmcs->guest_dr7;
1663 if (unlikely(!(evmcs->hv_clean_fields &
1664 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) {
1665 vmcs12->host_fs_base = evmcs->host_fs_base;
1666 vmcs12->host_gs_base = evmcs->host_gs_base;
1667 vmcs12->host_tr_base = evmcs->host_tr_base;
1668 vmcs12->host_gdtr_base = evmcs->host_gdtr_base;
1669 vmcs12->host_idtr_base = evmcs->host_idtr_base;
1670 vmcs12->host_rsp = evmcs->host_rsp;
1673 if (unlikely(!(evmcs->hv_clean_fields &
1674 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) {
1675 vmcs12->ept_pointer = evmcs->ept_pointer;
1676 vmcs12->virtual_processor_id = evmcs->virtual_processor_id;
1679 if (unlikely(!(evmcs->hv_clean_fields &
1680 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) {
1681 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer;
1682 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl;
1683 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat;
1684 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer;
1685 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0;
1686 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1;
1687 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2;
1688 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3;
1689 vmcs12->guest_pending_dbg_exceptions =
1690 evmcs->guest_pending_dbg_exceptions;
1691 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp;
1692 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip;
1693 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs;
1694 vmcs12->guest_activity_state = evmcs->guest_activity_state;
1695 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs;
1700 * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr;
1701 * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr;
1702 * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr;
1703 * vmcs12->cr3_target_value0 = evmcs->cr3_target_value0;
1704 * vmcs12->cr3_target_value1 = evmcs->cr3_target_value1;
1705 * vmcs12->cr3_target_value2 = evmcs->cr3_target_value2;
1706 * vmcs12->cr3_target_value3 = evmcs->cr3_target_value3;
1707 * vmcs12->page_fault_error_code_mask =
1708 * evmcs->page_fault_error_code_mask;
1709 * vmcs12->page_fault_error_code_match =
1710 * evmcs->page_fault_error_code_match;
1711 * vmcs12->cr3_target_count = evmcs->cr3_target_count;
1712 * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count;
1713 * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count;
1714 * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count;
1719 * vmcs12->guest_physical_address = evmcs->guest_physical_address;
1720 * vmcs12->vm_instruction_error = evmcs->vm_instruction_error;
1721 * vmcs12->vm_exit_reason = evmcs->vm_exit_reason;
1722 * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info;
1723 * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code;
1724 * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field;
1725 * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code;
1726 * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len;
1727 * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info;
1728 * vmcs12->exit_qualification = evmcs->exit_qualification;
1729 * vmcs12->guest_linear_address = evmcs->guest_linear_address;
1731 * Not present in struct vmcs12:
1732 * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx;
1733 * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi;
1734 * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi;
1735 * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip;
1741 static int copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx)
1743 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12;
1744 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs;
1747 * Should not be changed by KVM:
1749 * evmcs->host_es_selector = vmcs12->host_es_selector;
1750 * evmcs->host_cs_selector = vmcs12->host_cs_selector;
1751 * evmcs->host_ss_selector = vmcs12->host_ss_selector;
1752 * evmcs->host_ds_selector = vmcs12->host_ds_selector;
1753 * evmcs->host_fs_selector = vmcs12->host_fs_selector;
1754 * evmcs->host_gs_selector = vmcs12->host_gs_selector;
1755 * evmcs->host_tr_selector = vmcs12->host_tr_selector;
1756 * evmcs->host_ia32_pat = vmcs12->host_ia32_pat;
1757 * evmcs->host_ia32_efer = vmcs12->host_ia32_efer;
1758 * evmcs->host_cr0 = vmcs12->host_cr0;
1759 * evmcs->host_cr3 = vmcs12->host_cr3;
1760 * evmcs->host_cr4 = vmcs12->host_cr4;
1761 * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp;
1762 * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip;
1763 * evmcs->host_rip = vmcs12->host_rip;
1764 * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs;
1765 * evmcs->host_fs_base = vmcs12->host_fs_base;
1766 * evmcs->host_gs_base = vmcs12->host_gs_base;
1767 * evmcs->host_tr_base = vmcs12->host_tr_base;
1768 * evmcs->host_gdtr_base = vmcs12->host_gdtr_base;
1769 * evmcs->host_idtr_base = vmcs12->host_idtr_base;
1770 * evmcs->host_rsp = vmcs12->host_rsp;
1771 * sync_vmcs02_to_vmcs12() doesn't read these:
1772 * evmcs->io_bitmap_a = vmcs12->io_bitmap_a;
1773 * evmcs->io_bitmap_b = vmcs12->io_bitmap_b;
1774 * evmcs->msr_bitmap = vmcs12->msr_bitmap;
1775 * evmcs->ept_pointer = vmcs12->ept_pointer;
1776 * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap;
1777 * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr;
1778 * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr;
1779 * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr;
1780 * evmcs->cr3_target_value0 = vmcs12->cr3_target_value0;
1781 * evmcs->cr3_target_value1 = vmcs12->cr3_target_value1;
1782 * evmcs->cr3_target_value2 = vmcs12->cr3_target_value2;
1783 * evmcs->cr3_target_value3 = vmcs12->cr3_target_value3;
1784 * evmcs->tpr_threshold = vmcs12->tpr_threshold;
1785 * evmcs->virtual_processor_id = vmcs12->virtual_processor_id;
1786 * evmcs->exception_bitmap = vmcs12->exception_bitmap;
1787 * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer;
1788 * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control;
1789 * evmcs->vm_exit_controls = vmcs12->vm_exit_controls;
1790 * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control;
1791 * evmcs->page_fault_error_code_mask =
1792 * vmcs12->page_fault_error_code_mask;
1793 * evmcs->page_fault_error_code_match =
1794 * vmcs12->page_fault_error_code_match;
1795 * evmcs->cr3_target_count = vmcs12->cr3_target_count;
1796 * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr;
1797 * evmcs->tsc_offset = vmcs12->tsc_offset;
1798 * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl;
1799 * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask;
1800 * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask;
1801 * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow;
1802 * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow;
1803 * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count;
1804 * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count;
1805 * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count;
1807 * Not present in struct vmcs12:
1808 * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx;
1809 * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi;
1810 * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi;
1811 * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip;
1814 evmcs->guest_es_selector = vmcs12->guest_es_selector;
1815 evmcs->guest_cs_selector = vmcs12->guest_cs_selector;
1816 evmcs->guest_ss_selector = vmcs12->guest_ss_selector;
1817 evmcs->guest_ds_selector = vmcs12->guest_ds_selector;
1818 evmcs->guest_fs_selector = vmcs12->guest_fs_selector;
1819 evmcs->guest_gs_selector = vmcs12->guest_gs_selector;
1820 evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector;
1821 evmcs->guest_tr_selector = vmcs12->guest_tr_selector;
1823 evmcs->guest_es_limit = vmcs12->guest_es_limit;
1824 evmcs->guest_cs_limit = vmcs12->guest_cs_limit;
1825 evmcs->guest_ss_limit = vmcs12->guest_ss_limit;
1826 evmcs->guest_ds_limit = vmcs12->guest_ds_limit;
1827 evmcs->guest_fs_limit = vmcs12->guest_fs_limit;
1828 evmcs->guest_gs_limit = vmcs12->guest_gs_limit;
1829 evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit;
1830 evmcs->guest_tr_limit = vmcs12->guest_tr_limit;
1831 evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit;
1832 evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit;
1834 evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes;
1835 evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes;
1836 evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes;
1837 evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes;
1838 evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes;
1839 evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes;
1840 evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes;
1841 evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes;
1843 evmcs->guest_es_base = vmcs12->guest_es_base;
1844 evmcs->guest_cs_base = vmcs12->guest_cs_base;
1845 evmcs->guest_ss_base = vmcs12->guest_ss_base;
1846 evmcs->guest_ds_base = vmcs12->guest_ds_base;
1847 evmcs->guest_fs_base = vmcs12->guest_fs_base;
1848 evmcs->guest_gs_base = vmcs12->guest_gs_base;
1849 evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base;
1850 evmcs->guest_tr_base = vmcs12->guest_tr_base;
1851 evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base;
1852 evmcs->guest_idtr_base = vmcs12->guest_idtr_base;
1854 evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat;
1855 evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer;
1857 evmcs->guest_pdptr0 = vmcs12->guest_pdptr0;
1858 evmcs->guest_pdptr1 = vmcs12->guest_pdptr1;
1859 evmcs->guest_pdptr2 = vmcs12->guest_pdptr2;
1860 evmcs->guest_pdptr3 = vmcs12->guest_pdptr3;
1862 evmcs->guest_pending_dbg_exceptions =
1863 vmcs12->guest_pending_dbg_exceptions;
1864 evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp;
1865 evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip;
1867 evmcs->guest_activity_state = vmcs12->guest_activity_state;
1868 evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs;
1870 evmcs->guest_cr0 = vmcs12->guest_cr0;
1871 evmcs->guest_cr3 = vmcs12->guest_cr3;
1872 evmcs->guest_cr4 = vmcs12->guest_cr4;
1873 evmcs->guest_dr7 = vmcs12->guest_dr7;
1875 evmcs->guest_physical_address = vmcs12->guest_physical_address;
1877 evmcs->vm_instruction_error = vmcs12->vm_instruction_error;
1878 evmcs->vm_exit_reason = vmcs12->vm_exit_reason;
1879 evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info;
1880 evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code;
1881 evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field;
1882 evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code;
1883 evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len;
1884 evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info;
1886 evmcs->exit_qualification = vmcs12->exit_qualification;
1888 evmcs->guest_linear_address = vmcs12->guest_linear_address;
1889 evmcs->guest_rsp = vmcs12->guest_rsp;
1890 evmcs->guest_rflags = vmcs12->guest_rflags;
1892 evmcs->guest_interruptibility_info =
1893 vmcs12->guest_interruptibility_info;
1894 evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control;
1895 evmcs->vm_entry_controls = vmcs12->vm_entry_controls;
1896 evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field;
1897 evmcs->vm_entry_exception_error_code =
1898 vmcs12->vm_entry_exception_error_code;
1899 evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len;
1901 evmcs->guest_rip = vmcs12->guest_rip;
1903 evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs;
1909 * This is an equivalent of the nested hypervisor executing the vmptrld
1912 static int nested_vmx_handle_enlightened_vmptrld(struct kvm_vcpu *vcpu,
1915 struct vcpu_vmx *vmx = to_vmx(vcpu);
1916 bool evmcs_gpa_changed = false;
1919 if (likely(!vmx->nested.enlightened_vmcs_enabled))
1922 if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa))
1925 if (unlikely(evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) {
1926 if (!vmx->nested.hv_evmcs)
1927 vmx->nested.current_vmptr = -1ull;
1929 nested_release_evmcs(vcpu);
1931 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa),
1932 &vmx->nested.hv_evmcs_map))
1935 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva;
1938 * Currently, KVM only supports eVMCS version 1
1939 * (== KVM_EVMCS_VERSION) and thus we expect guest to set this
1940 * value to first u32 field of eVMCS which should specify eVMCS
1943 * Guest should be aware of supported eVMCS versions by host by
1944 * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is
1945 * expected to set this CPUID leaf according to the value
1946 * returned in vmcs_version from nested_enable_evmcs().
1948 * However, it turns out that Microsoft Hyper-V fails to comply
1949 * to their own invented interface: When Hyper-V use eVMCS, it
1950 * just sets first u32 field of eVMCS to revision_id specified
1951 * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number
1952 * which is one of the supported versions specified in
1953 * CPUID.0x4000000A.EAX[0:15].
1955 * To overcome Hyper-V bug, we accept here either a supported
1956 * eVMCS version or VMCS12 revision_id as valid values for first
1957 * u32 field of eVMCS.
1959 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) &&
1960 (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) {
1961 nested_release_evmcs(vcpu);
1965 vmx->nested.dirty_vmcs12 = true;
1966 vmx->nested.hv_evmcs_vmptr = evmcs_gpa;
1968 evmcs_gpa_changed = true;
1970 * Unlike normal vmcs12, enlightened vmcs12 is not fully
1971 * reloaded from guest's memory (read only fields, fields not
1972 * present in struct hv_enlightened_vmcs, ...). Make sure there
1976 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1977 memset(vmcs12, 0, sizeof(*vmcs12));
1978 vmcs12->hdr.revision_id = VMCS12_REVISION;
1984 * Clean fields data can't de used on VMLAUNCH and when we switch
1985 * between different L2 guests as KVM keeps a single VMCS12 per L1.
1987 if (from_launch || evmcs_gpa_changed)
1988 vmx->nested.hv_evmcs->hv_clean_fields &=
1989 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
1994 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu)
1996 struct vcpu_vmx *vmx = to_vmx(vcpu);
1999 * hv_evmcs may end up being not mapped after migration (when
2000 * L2 was running), map it here to make sure vmcs12 changes are
2001 * properly reflected.
2003 if (vmx->nested.enlightened_vmcs_enabled && !vmx->nested.hv_evmcs)
2004 nested_vmx_handle_enlightened_vmptrld(vcpu, false);
2006 if (vmx->nested.hv_evmcs) {
2007 copy_vmcs12_to_enlightened(vmx);
2008 /* All fields are clean */
2009 vmx->nested.hv_evmcs->hv_clean_fields |=
2010 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
2012 copy_vmcs12_to_shadow(vmx);
2015 vmx->nested.need_vmcs12_to_shadow_sync = false;
2018 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
2020 struct vcpu_vmx *vmx =
2021 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
2023 vmx->nested.preemption_timer_expired = true;
2024 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
2025 kvm_vcpu_kick(&vmx->vcpu);
2027 return HRTIMER_NORESTART;
2030 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
2032 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
2033 struct vcpu_vmx *vmx = to_vmx(vcpu);
2036 * A timer value of zero is architecturally guaranteed to cause
2037 * a VMExit prior to executing any instructions in the guest.
2039 if (preemption_timeout == 0) {
2040 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
2044 if (vcpu->arch.virtual_tsc_khz == 0)
2047 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
2048 preemption_timeout *= 1000000;
2049 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
2050 hrtimer_start(&vmx->nested.preemption_timer,
2051 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
2054 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2056 if (vmx->nested.nested_run_pending &&
2057 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
2058 return vmcs12->guest_ia32_efer;
2059 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
2060 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME);
2062 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME);
2065 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
2068 * If vmcs02 hasn't been initialized, set the constant vmcs02 state
2069 * according to L0's settings (vmcs12 is irrelevant here). Host
2070 * fields that come from L0 and are not constant, e.g. HOST_CR3,
2071 * will be set as needed prior to VMLAUNCH/VMRESUME.
2073 if (vmx->nested.vmcs02_initialized)
2075 vmx->nested.vmcs02_initialized = true;
2078 * We don't care what the EPTP value is we just need to guarantee
2079 * it's valid so we don't get a false positive when doing early
2080 * consistency checks.
2082 if (enable_ept && nested_early_check)
2083 vmcs_write64(EPT_POINTER, construct_eptp(&vmx->vcpu, 0));
2085 /* All VMFUNCs are currently emulated through L0 vmexits. */
2086 if (cpu_has_vmx_vmfunc())
2087 vmcs_write64(VM_FUNCTION_CONTROL, 0);
2089 if (cpu_has_vmx_posted_intr())
2090 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
2092 if (cpu_has_vmx_msr_bitmap())
2093 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
2096 * The PML address never changes, so it is constant in vmcs02.
2097 * Conceptually we want to copy the PML index from vmcs01 here,
2098 * and then back to vmcs01 on nested vmexit. But since we flush
2099 * the log and reset GUEST_PML_INDEX on each vmexit, the PML
2100 * index is also effectively constant in vmcs02.
2103 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
2104 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
2107 if (cpu_has_vmx_encls_vmexit())
2108 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
2111 * Set the MSR load/store lists to match L0's settings. Only the
2112 * addresses are constant (for vmcs02), the counts can change based
2113 * on L2's behavior, e.g. switching to/from long mode.
2115 vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val));
2116 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2117 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
2119 vmx_set_constant_host_state(vmx);
2122 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx,
2123 struct vmcs12 *vmcs12)
2125 prepare_vmcs02_constant_state(vmx);
2127 vmcs_write64(VMCS_LINK_POINTER, -1ull);
2130 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
2131 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
2133 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2137 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2139 u32 exec_control, vmcs12_exec_ctrl;
2140 u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12);
2142 if (vmx->nested.dirty_vmcs12 || vmx->nested.hv_evmcs)
2143 prepare_vmcs02_early_rare(vmx, vmcs12);
2148 exec_control = vmx_pin_based_exec_ctrl(vmx);
2149 exec_control |= (vmcs12->pin_based_vm_exec_control &
2150 ~PIN_BASED_VMX_PREEMPTION_TIMER);
2152 /* Posted interrupts setting is only taken from vmcs12. */
2153 if (nested_cpu_has_posted_intr(vmcs12)) {
2154 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
2155 vmx->nested.pi_pending = false;
2157 exec_control &= ~PIN_BASED_POSTED_INTR;
2159 pin_controls_set(vmx, exec_control);
2164 exec_control = vmx_exec_control(vmx); /* L0's desires */
2165 exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING;
2166 exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING;
2167 exec_control &= ~CPU_BASED_TPR_SHADOW;
2168 exec_control |= vmcs12->cpu_based_vm_exec_control;
2170 vmx->nested.l1_tpr_threshold = -1;
2171 if (exec_control & CPU_BASED_TPR_SHADOW)
2172 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
2173 #ifdef CONFIG_X86_64
2175 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
2176 CPU_BASED_CR8_STORE_EXITING;
2180 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
2181 * for I/O port accesses.
2183 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
2184 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
2187 * This bit will be computed in nested_get_vmcs12_pages, because
2188 * we do not have access to L1's MSR bitmap yet. For now, keep
2189 * the same bit as before, hoping to avoid multiple VMWRITEs that
2190 * only set/clear this bit.
2192 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
2193 exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS;
2195 exec_controls_set(vmx, exec_control);
2198 * SECONDARY EXEC CONTROLS
2200 if (cpu_has_secondary_exec_ctrls()) {
2201 exec_control = vmx->secondary_exec_control;
2203 /* Take the following fields only from vmcs12 */
2204 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2205 SECONDARY_EXEC_ENABLE_INVPCID |
2206 SECONDARY_EXEC_RDTSCP |
2207 SECONDARY_EXEC_XSAVES |
2208 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2209 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2210 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2211 SECONDARY_EXEC_ENABLE_VMFUNC);
2212 if (nested_cpu_has(vmcs12,
2213 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
2214 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
2215 ~SECONDARY_EXEC_ENABLE_PML;
2216 exec_control |= vmcs12_exec_ctrl;
2219 /* VMCS shadowing for L2 is emulated for now */
2220 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
2223 * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4()
2224 * will not have to rewrite the controls just for this bit.
2226 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
2227 (vmcs12->guest_cr4 & X86_CR4_UMIP))
2228 exec_control |= SECONDARY_EXEC_DESC;
2230 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
2231 vmcs_write16(GUEST_INTR_STATUS,
2232 vmcs12->guest_intr_status);
2234 secondary_exec_controls_set(vmx, exec_control);
2240 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
2241 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
2242 * on the related bits (if supported by the CPU) in the hope that
2243 * we can avoid VMWrites during vmx_set_efer().
2245 exec_control = (vmcs12->vm_entry_controls | vmx_vmentry_ctrl()) &
2246 ~VM_ENTRY_IA32E_MODE & ~VM_ENTRY_LOAD_IA32_EFER;
2247 if (cpu_has_load_ia32_efer()) {
2248 if (guest_efer & EFER_LMA)
2249 exec_control |= VM_ENTRY_IA32E_MODE;
2250 if (guest_efer != host_efer)
2251 exec_control |= VM_ENTRY_LOAD_IA32_EFER;
2253 vm_entry_controls_set(vmx, exec_control);
2258 * L2->L1 exit controls are emulated - the hardware exit is to L0 so
2259 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
2260 * bits may be modified by vmx_set_efer() in prepare_vmcs02().
2262 exec_control = vmx_vmexit_ctrl();
2263 if (cpu_has_load_ia32_efer() && guest_efer != host_efer)
2264 exec_control |= VM_EXIT_LOAD_IA32_EFER;
2265 vm_exit_controls_set(vmx, exec_control);
2268 * Interrupt/Exception Fields
2270 if (vmx->nested.nested_run_pending) {
2271 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2272 vmcs12->vm_entry_intr_info_field);
2273 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2274 vmcs12->vm_entry_exception_error_code);
2275 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2276 vmcs12->vm_entry_instruction_len);
2277 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2278 vmcs12->guest_interruptibility_info);
2279 vmx->loaded_vmcs->nmi_known_unmasked =
2280 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
2282 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
2286 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
2288 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs;
2290 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2291 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) {
2292 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
2293 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
2294 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
2295 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
2296 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
2297 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
2298 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
2299 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
2300 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
2301 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
2302 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
2303 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
2304 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
2305 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
2306 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
2307 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
2308 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
2309 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
2310 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
2311 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
2312 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
2313 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
2314 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
2315 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
2316 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
2317 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
2318 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
2319 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
2320 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
2321 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
2322 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
2323 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
2324 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
2325 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
2326 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
2327 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
2330 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields &
2331 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) {
2332 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
2333 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
2334 vmcs12->guest_pending_dbg_exceptions);
2335 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
2336 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
2339 * L1 may access the L2's PDPTR, so save them to construct
2343 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2344 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2345 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2346 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2349 if (kvm_mpx_supported() && vmx->nested.nested_run_pending &&
2350 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
2351 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
2354 if (nested_cpu_has_xsaves(vmcs12))
2355 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
2358 * Whether page-faults are trapped is determined by a combination of
2359 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
2360 * If enable_ept, L0 doesn't care about page faults and we should
2361 * set all of these to L1's desires. However, if !enable_ept, L0 does
2362 * care about (at least some) page faults, and because it is not easy
2363 * (if at all possible?) to merge L0 and L1's desires, we simply ask
2364 * to exit on each and every L2 page fault. This is done by setting
2365 * MASK=MATCH=0 and (see below) EB.PF=1.
2366 * Note that below we don't need special code to set EB.PF beyond the
2367 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
2368 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
2369 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
2371 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
2372 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
2373 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
2374 enable_ept ? vmcs12->page_fault_error_code_match : 0);
2376 if (cpu_has_vmx_apicv()) {
2377 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
2378 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
2379 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
2380 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
2384 * Make sure the msr_autostore list is up to date before we set the
2385 * count in the vmcs02.
2387 prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC);
2389 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr);
2390 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
2391 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
2393 set_cr4_guest_host_mask(vmx);
2397 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
2398 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
2399 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
2400 * guest in a way that will both be appropriate to L1's requests, and our
2401 * needs. In addition to modifying the active vmcs (which is vmcs02), this
2402 * function also has additional necessary side-effects, like setting various
2403 * vcpu->arch fields.
2404 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
2405 * is assigned to entry_failure_code on failure.
2407 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
2408 u32 *entry_failure_code)
2410 struct vcpu_vmx *vmx = to_vmx(vcpu);
2411 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs;
2412 bool load_guest_pdptrs_vmcs12 = false;
2414 if (vmx->nested.dirty_vmcs12 || hv_evmcs) {
2415 prepare_vmcs02_rare(vmx, vmcs12);
2416 vmx->nested.dirty_vmcs12 = false;
2418 load_guest_pdptrs_vmcs12 = !hv_evmcs ||
2419 !(hv_evmcs->hv_clean_fields &
2420 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1);
2423 if (vmx->nested.nested_run_pending &&
2424 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
2425 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
2426 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
2428 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
2429 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
2431 if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending ||
2432 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
2433 vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
2434 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
2436 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
2437 * bitwise-or of what L1 wants to trap for L2, and what we want to
2438 * trap. Note that CR0.TS also needs updating - we do this later.
2440 update_exception_bitmap(vcpu);
2441 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
2442 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2444 if (vmx->nested.nested_run_pending &&
2445 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
2446 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
2447 vcpu->arch.pat = vmcs12->guest_ia32_pat;
2448 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2449 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
2452 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
2454 if (kvm_has_tsc_control)
2455 decache_tsc_multiplier(vmx);
2459 * There is no direct mapping between vpid02 and vpid12, the
2460 * vpid02 is per-vCPU for L0 and reused while the value of
2461 * vpid12 is changed w/ one invvpid during nested vmentry.
2462 * The vpid12 is allocated by L1 for L2, so it will not
2463 * influence global bitmap(for vpid01 and vpid02 allocation)
2464 * even if spawn a lot of nested vCPUs.
2466 if (nested_cpu_has_vpid(vmcs12) && nested_has_guest_tlb_tag(vcpu)) {
2467 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
2468 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
2469 __vmx_flush_tlb(vcpu, nested_get_vpid02(vcpu), false);
2473 * If L1 use EPT, then L0 needs to execute INVEPT on
2474 * EPTP02 instead of EPTP01. Therefore, delay TLB
2475 * flush until vmcs02->eptp is fully updated by
2476 * KVM_REQ_LOAD_CR3. Note that this assumes
2477 * KVM_REQ_TLB_FLUSH is evaluated after
2478 * KVM_REQ_LOAD_CR3 in vcpu_enter_guest().
2480 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2484 if (nested_cpu_has_ept(vmcs12))
2485 nested_ept_init_mmu_context(vcpu);
2488 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
2489 * bits which we consider mandatory enabled.
2490 * The CR0_READ_SHADOW is what L2 should have expected to read given
2491 * the specifications by L1; It's not enough to take
2492 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
2493 * have more bits than L1 expected.
2495 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
2496 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2498 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
2499 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
2501 vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12);
2502 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
2503 vmx_set_efer(vcpu, vcpu->arch.efer);
2506 * Guest state is invalid and unrestricted guest is disabled,
2507 * which means L1 attempted VMEntry to L2 with invalid state.
2510 if (vmx->emulation_required) {
2511 *entry_failure_code = ENTRY_FAIL_DEFAULT;
2515 /* Shadow page tables on either EPT or shadow page tables. */
2516 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
2517 entry_failure_code))
2521 * Immediately write vmcs02.GUEST_CR3. It will be propagated to vmcs12
2522 * on nested VM-Exit, which can occur without actually running L2 and
2523 * thus without hitting vmx_set_cr3(), e.g. if L1 is entering L2 with
2524 * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the
2525 * transition to HLT instead of running L2.
2528 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3);
2530 /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */
2531 if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) &&
2532 is_pae_paging(vcpu)) {
2533 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
2534 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
2535 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
2536 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
2540 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
2542 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2543 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
2544 vmcs12->guest_ia32_perf_global_ctrl)))
2547 kvm_rsp_write(vcpu, vmcs12->guest_rsp);
2548 kvm_rip_write(vcpu, vmcs12->guest_rip);
2552 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
2554 if (CC(!nested_cpu_has_nmi_exiting(vmcs12) &&
2555 nested_cpu_has_virtual_nmis(vmcs12)))
2558 if (CC(!nested_cpu_has_virtual_nmis(vmcs12) &&
2559 nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING)))
2565 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
2567 struct vcpu_vmx *vmx = to_vmx(vcpu);
2568 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2570 /* Check for memory type validity */
2571 switch (address & VMX_EPTP_MT_MASK) {
2572 case VMX_EPTP_MT_UC:
2573 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT)))
2576 case VMX_EPTP_MT_WB:
2577 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT)))
2584 /* only 4 levels page-walk length are valid */
2585 if (CC((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4))
2588 /* Reserved bits should not be set */
2589 if (CC(address >> maxphyaddr || ((address >> 7) & 0x1f)))
2592 /* AD, if set, should be supported */
2593 if (address & VMX_EPTP_AD_ENABLE_BIT) {
2594 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT)))
2602 * Checks related to VM-Execution Control Fields
2604 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu,
2605 struct vmcs12 *vmcs12)
2607 struct vcpu_vmx *vmx = to_vmx(vcpu);
2609 if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control,
2610 vmx->nested.msrs.pinbased_ctls_low,
2611 vmx->nested.msrs.pinbased_ctls_high)) ||
2612 CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
2613 vmx->nested.msrs.procbased_ctls_low,
2614 vmx->nested.msrs.procbased_ctls_high)))
2617 if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
2618 CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control,
2619 vmx->nested.msrs.secondary_ctls_low,
2620 vmx->nested.msrs.secondary_ctls_high)))
2623 if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) ||
2624 nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) ||
2625 nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) ||
2626 nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) ||
2627 nested_vmx_check_apic_access_controls(vcpu, vmcs12) ||
2628 nested_vmx_check_apicv_controls(vcpu, vmcs12) ||
2629 nested_vmx_check_nmi_controls(vmcs12) ||
2630 nested_vmx_check_pml_controls(vcpu, vmcs12) ||
2631 nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) ||
2632 nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) ||
2633 nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) ||
2634 CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id))
2637 if (!nested_cpu_has_preemption_timer(vmcs12) &&
2638 nested_cpu_has_save_preemption_timer(vmcs12))
2641 if (nested_cpu_has_ept(vmcs12) &&
2642 CC(!valid_ept_address(vcpu, vmcs12->ept_pointer)))
2645 if (nested_cpu_has_vmfunc(vmcs12)) {
2646 if (CC(vmcs12->vm_function_control &
2647 ~vmx->nested.msrs.vmfunc_controls))
2650 if (nested_cpu_has_eptp_switching(vmcs12)) {
2651 if (CC(!nested_cpu_has_ept(vmcs12)) ||
2652 CC(!page_address_valid(vcpu, vmcs12->eptp_list_address)))
2661 * Checks related to VM-Exit Control Fields
2663 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu,
2664 struct vmcs12 *vmcs12)
2666 struct vcpu_vmx *vmx = to_vmx(vcpu);
2668 if (CC(!vmx_control_verify(vmcs12->vm_exit_controls,
2669 vmx->nested.msrs.exit_ctls_low,
2670 vmx->nested.msrs.exit_ctls_high)) ||
2671 CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12)))
2678 * Checks related to VM-Entry Control Fields
2680 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu,
2681 struct vmcs12 *vmcs12)
2683 struct vcpu_vmx *vmx = to_vmx(vcpu);
2685 if (CC(!vmx_control_verify(vmcs12->vm_entry_controls,
2686 vmx->nested.msrs.entry_ctls_low,
2687 vmx->nested.msrs.entry_ctls_high)))
2691 * From the Intel SDM, volume 3:
2692 * Fields relevant to VM-entry event injection must be set properly.
2693 * These fields are the VM-entry interruption-information field, the
2694 * VM-entry exception error code, and the VM-entry instruction length.
2696 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
2697 u32 intr_info = vmcs12->vm_entry_intr_info_field;
2698 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
2699 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
2700 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
2701 bool should_have_error_code;
2702 bool urg = nested_cpu_has2(vmcs12,
2703 SECONDARY_EXEC_UNRESTRICTED_GUEST);
2704 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
2706 /* VM-entry interruption-info field: interruption type */
2707 if (CC(intr_type == INTR_TYPE_RESERVED) ||
2708 CC(intr_type == INTR_TYPE_OTHER_EVENT &&
2709 !nested_cpu_supports_monitor_trap_flag(vcpu)))
2712 /* VM-entry interruption-info field: vector */
2713 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
2714 CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
2715 CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
2718 /* VM-entry interruption-info field: deliver error code */
2719 should_have_error_code =
2720 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
2721 x86_exception_has_error_code(vector);
2722 if (CC(has_error_code != should_have_error_code))
2725 /* VM-entry exception error code */
2726 if (CC(has_error_code &&
2727 vmcs12->vm_entry_exception_error_code & GENMASK(31, 16)))
2730 /* VM-entry interruption-info field: reserved bits */
2731 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK))
2734 /* VM-entry instruction length */
2735 switch (intr_type) {
2736 case INTR_TYPE_SOFT_EXCEPTION:
2737 case INTR_TYPE_SOFT_INTR:
2738 case INTR_TYPE_PRIV_SW_EXCEPTION:
2739 if (CC(vmcs12->vm_entry_instruction_len > 15) ||
2740 CC(vmcs12->vm_entry_instruction_len == 0 &&
2741 CC(!nested_cpu_has_zero_length_injection(vcpu))))
2746 if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12))
2752 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu,
2753 struct vmcs12 *vmcs12)
2755 if (nested_check_vm_execution_controls(vcpu, vmcs12) ||
2756 nested_check_vm_exit_controls(vcpu, vmcs12) ||
2757 nested_check_vm_entry_controls(vcpu, vmcs12))
2760 if (to_vmx(vcpu)->nested.enlightened_vmcs_enabled)
2761 return nested_evmcs_check_controls(vmcs12);
2766 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu,
2767 struct vmcs12 *vmcs12)
2771 if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) ||
2772 CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) ||
2773 CC(!nested_cr3_valid(vcpu, vmcs12->host_cr3)))
2776 if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) ||
2777 CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu)))
2780 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) &&
2781 CC(!kvm_pat_valid(vmcs12->host_ia32_pat)))
2784 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2785 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2786 vmcs12->host_ia32_perf_global_ctrl)))
2789 #ifdef CONFIG_X86_64
2790 ia32e = !!(vcpu->arch.efer & EFER_LMA);
2796 if (CC(!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)) ||
2797 CC(!(vmcs12->host_cr4 & X86_CR4_PAE)))
2800 if (CC(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) ||
2801 CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) ||
2802 CC(vmcs12->host_cr4 & X86_CR4_PCIDE) ||
2803 CC((vmcs12->host_rip) >> 32))
2807 if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2808 CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2809 CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2810 CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2811 CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2812 CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2813 CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) ||
2814 CC(vmcs12->host_cs_selector == 0) ||
2815 CC(vmcs12->host_tr_selector == 0) ||
2816 CC(vmcs12->host_ss_selector == 0 && !ia32e))
2819 if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) ||
2820 CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) ||
2821 CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) ||
2822 CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) ||
2823 CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) ||
2824 CC(is_noncanonical_address(vmcs12->host_rip, vcpu)))
2828 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
2829 * IA32_EFER MSR must be 0 in the field for that register. In addition,
2830 * the values of the LMA and LME bits in the field must each be that of
2831 * the host address-space size VM-exit control.
2833 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
2834 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) ||
2835 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) ||
2836 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)))
2843 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
2844 struct vmcs12 *vmcs12)
2847 struct vmcs12 *shadow;
2848 struct kvm_host_map map;
2850 if (vmcs12->vmcs_link_pointer == -1ull)
2853 if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer)))
2856 if (CC(kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map)))
2861 if (CC(shadow->hdr.revision_id != VMCS12_REVISION) ||
2862 CC(shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12)))
2865 kvm_vcpu_unmap(vcpu, &map, false);
2870 * Checks related to Guest Non-register State
2872 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12)
2874 if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
2875 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT))
2881 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu,
2882 struct vmcs12 *vmcs12,
2887 *exit_qual = ENTRY_FAIL_DEFAULT;
2889 if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) ||
2890 CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)))
2893 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) &&
2894 CC(!kvm_dr7_valid(vmcs12->guest_dr7)))
2897 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) &&
2898 CC(!kvm_pat_valid(vmcs12->guest_ia32_pat)))
2901 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
2902 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
2906 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
2907 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu),
2908 vmcs12->guest_ia32_perf_global_ctrl)))
2912 * If the load IA32_EFER VM-entry control is 1, the following checks
2913 * are performed on the field for the IA32_EFER MSR:
2914 * - Bits reserved in the IA32_EFER MSR must be 0.
2915 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
2916 * the IA-32e mode guest VM-exit control. It must also be identical
2917 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
2920 if (to_vmx(vcpu)->nested.nested_run_pending &&
2921 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
2922 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
2923 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) ||
2924 CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) ||
2925 CC(((vmcs12->guest_cr0 & X86_CR0_PG) &&
2926 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))))
2930 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
2931 (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) ||
2932 CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))))
2935 if (nested_check_guest_non_reg_state(vmcs12))
2941 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu)
2943 struct vcpu_vmx *vmx = to_vmx(vcpu);
2944 unsigned long cr3, cr4;
2947 if (!nested_early_check)
2950 if (vmx->msr_autoload.host.nr)
2951 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2952 if (vmx->msr_autoload.guest.nr)
2953 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2957 vmx_prepare_switch_to_guest(vcpu);
2960 * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS,
2961 * which is reserved to '1' by hardware. GUEST_RFLAGS is guaranteed to
2962 * be written (by preparve_vmcs02()) before the "real" VMEnter, i.e.
2963 * there is no need to preserve other bits or save/restore the field.
2965 vmcs_writel(GUEST_RFLAGS, 0);
2967 cr3 = __get_current_cr3_fast();
2968 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
2969 vmcs_writel(HOST_CR3, cr3);
2970 vmx->loaded_vmcs->host_state.cr3 = cr3;
2973 cr4 = cr4_read_shadow();
2974 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
2975 vmcs_writel(HOST_CR4, cr4);
2976 vmx->loaded_vmcs->host_state.cr4 = cr4;
2980 "sub $%c[wordsize], %%" _ASM_SP "\n\t" /* temporarily adjust RSP for CALL */
2981 "cmp %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t"
2983 __ex("vmwrite %%" _ASM_SP ", %[HOST_RSP]") "\n\t"
2984 "mov %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t"
2986 "add $%c[wordsize], %%" _ASM_SP "\n\t" /* un-adjust RSP */
2988 /* Check if vmlaunch or vmresume is needed */
2989 "cmpb $0, %c[launched](%[loaded_vmcs])\n\t"
2992 * VMLAUNCH and VMRESUME clear RFLAGS.{CF,ZF} on VM-Exit, set
2993 * RFLAGS.CF on VM-Fail Invalid and set RFLAGS.ZF on VM-Fail
2994 * Valid. vmx_vmenter() directly "returns" RFLAGS, and so the
2995 * results of VM-Enter is captured via CC_{SET,OUT} to vm_fail.
2997 "call vmx_vmenter\n\t"
3000 : ASM_CALL_CONSTRAINT, CC_OUT(be) (vm_fail)
3001 : [HOST_RSP]"r"((unsigned long)HOST_RSP),
3002 [loaded_vmcs]"r"(vmx->loaded_vmcs),
3003 [launched]"i"(offsetof(struct loaded_vmcs, launched)),
3004 [host_state_rsp]"i"(offsetof(struct loaded_vmcs, host_state.rsp)),
3005 [wordsize]"i"(sizeof(ulong))
3009 if (vmx->msr_autoload.host.nr)
3010 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
3011 if (vmx->msr_autoload.guest.nr)
3012 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
3015 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR);
3019 trace_kvm_nested_vmenter_failed(
3020 "early hardware check VM-instruction error: ", error);
3021 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3026 * VMExit clears RFLAGS.IF and DR7, even on a consistency check.
3029 if (hw_breakpoint_active())
3030 set_debugreg(__this_cpu_read(cpu_dr7), 7);
3034 * A non-failing VMEntry means we somehow entered guest mode with
3035 * an illegal RIP, and that's just the tip of the iceberg. There
3036 * is no telling what memory has been modified or what state has
3037 * been exposed to unknown code. Hitting this all but guarantees
3038 * a (very critical) hardware issue.
3040 WARN_ON(!(vmcs_read32(VM_EXIT_REASON) &
3041 VMX_EXIT_REASONS_FAILED_VMENTRY));
3046 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
3048 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3049 struct vcpu_vmx *vmx = to_vmx(vcpu);
3050 struct kvm_host_map *map;
3054 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3056 * Translate L1 physical address to host physical
3057 * address for vmcs02. Keep the page pinned, so this
3058 * physical address remains valid. We keep a reference
3059 * to it so we can release it later.
3061 if (vmx->nested.apic_access_page) { /* shouldn't happen */
3062 kvm_release_page_clean(vmx->nested.apic_access_page);
3063 vmx->nested.apic_access_page = NULL;
3065 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
3066 if (!is_error_page(page)) {
3067 vmx->nested.apic_access_page = page;
3068 hpa = page_to_phys(vmx->nested.apic_access_page);
3069 vmcs_write64(APIC_ACCESS_ADDR, hpa);
3071 pr_debug_ratelimited("%s: no backing 'struct page' for APIC-access address in vmcs12\n",
3073 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3074 vcpu->run->internal.suberror =
3075 KVM_INTERNAL_ERROR_EMULATION;
3076 vcpu->run->internal.ndata = 0;
3081 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3082 map = &vmx->nested.virtual_apic_map;
3084 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) {
3085 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn));
3086 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) &&
3087 nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) &&
3088 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
3090 * The processor will never use the TPR shadow, simply
3091 * clear the bit from the execution control. Such a
3092 * configuration is useless, but it happens in tests.
3093 * For any other configuration, failing the vm entry is
3094 * _not_ what the processor does but it's basically the
3095 * only possibility we have.
3097 exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW);
3100 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to
3101 * force VM-Entry to fail.
3103 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
3107 if (nested_cpu_has_posted_intr(vmcs12)) {
3108 map = &vmx->nested.pi_desc_map;
3110 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) {
3111 vmx->nested.pi_desc =
3112 (struct pi_desc *)(((void *)map->hva) +
3113 offset_in_page(vmcs12->posted_intr_desc_addr));
3114 vmcs_write64(POSTED_INTR_DESC_ADDR,
3115 pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr));
3118 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
3119 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3121 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS);
3126 * Intel's VMX Instruction Reference specifies a common set of prerequisites
3127 * for running VMX instructions (except VMXON, whose prerequisites are
3128 * slightly different). It also specifies what exception to inject otherwise.
3129 * Note that many of these exceptions have priority over VM exits, so they
3130 * don't have to be checked again here.
3132 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
3134 if (!to_vmx(vcpu)->nested.vmxon) {
3135 kvm_queue_exception(vcpu, UD_VECTOR);
3139 if (vmx_get_cpl(vcpu)) {
3140 kvm_inject_gp(vcpu, 0);
3147 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
3149 u8 rvi = vmx_get_rvi();
3150 u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
3152 return ((rvi & 0xf0) > (vppr & 0xf0));
3155 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
3156 struct vmcs12 *vmcs12);
3159 * If from_vmentry is false, this is being called from state restore (either RSM
3160 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
3163 * NVMX_ENTRY_SUCCESS: Entered VMX non-root mode
3164 * NVMX_ENTRY_VMFAIL: Consistency check VMFail
3165 * NVMX_ENTRY_VMEXIT: Consistency check VMExit
3166 * NVMX_ENTRY_KVM_INTERNAL_ERROR: KVM internal error
3168 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
3171 struct vcpu_vmx *vmx = to_vmx(vcpu);
3172 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3173 bool evaluate_pending_interrupts;
3174 u32 exit_reason = EXIT_REASON_INVALID_STATE;
3177 evaluate_pending_interrupts = exec_controls_get(vmx) &
3178 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING);
3179 if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
3180 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
3182 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
3183 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
3184 if (kvm_mpx_supported() &&
3185 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
3186 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
3189 * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and*
3190 * nested early checks are disabled. In the event of a "late" VM-Fail,
3191 * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its
3192 * software model to the pre-VMEntry host state. When EPT is disabled,
3193 * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes
3194 * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3. Stuffing
3195 * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to
3196 * the correct value. Smashing vmcs01.GUEST_CR3 is safe because nested
3197 * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is
3198 * guaranteed to be overwritten with a shadow CR3 prior to re-entering
3199 * L1. Don't stuff vmcs01.GUEST_CR3 when using nested early checks as
3200 * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks
3201 * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail
3202 * path would need to manually save/restore vmcs01.GUEST_CR3.
3204 if (!enable_ept && !nested_early_check)
3205 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3207 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
3209 prepare_vmcs02_early(vmx, vmcs12);
3212 if (unlikely(!nested_get_vmcs12_pages(vcpu)))
3213 return NVMX_VMENTRY_KVM_INTERNAL_ERROR;
3215 if (nested_vmx_check_vmentry_hw(vcpu)) {
3216 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3217 return NVMX_VMENTRY_VMFAIL;
3220 if (nested_vmx_check_guest_state(vcpu, vmcs12, &exit_qual))
3221 goto vmentry_fail_vmexit;
3224 enter_guest_mode(vcpu);
3225 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
3226 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
3228 if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
3229 goto vmentry_fail_vmexit_guest_mode;
3232 exit_reason = EXIT_REASON_MSR_LOAD_FAIL;
3233 exit_qual = nested_vmx_load_msr(vcpu,
3234 vmcs12->vm_entry_msr_load_addr,
3235 vmcs12->vm_entry_msr_load_count);
3237 goto vmentry_fail_vmexit_guest_mode;
3240 * The MMU is not initialized to point at the right entities yet and
3241 * "get pages" would need to read data from the guest (i.e. we will
3242 * need to perform gpa to hpa translation). Request a call
3243 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs
3244 * have already been set at vmentry time and should not be reset.
3246 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
3250 * If L1 had a pending IRQ/NMI until it executed
3251 * VMLAUNCH/VMRESUME which wasn't delivered because it was
3252 * disallowed (e.g. interrupts disabled), L0 needs to
3253 * evaluate if this pending event should cause an exit from L2
3254 * to L1 or delivered directly to L2 (e.g. In case L1 don't
3255 * intercept EXTERNAL_INTERRUPT).
3257 * Usually this would be handled by the processor noticing an
3258 * IRQ/NMI window request, or checking RVI during evaluation of
3259 * pending virtual interrupts. However, this setting was done
3260 * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
3261 * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
3263 if (unlikely(evaluate_pending_interrupts))
3264 kvm_make_request(KVM_REQ_EVENT, vcpu);
3267 * Do not start the preemption timer hrtimer until after we know
3268 * we are successful, so that only nested_vmx_vmexit needs to cancel
3271 vmx->nested.preemption_timer_expired = false;
3272 if (nested_cpu_has_preemption_timer(vmcs12))
3273 vmx_start_preemption_timer(vcpu);
3276 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
3277 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
3278 * returned as far as L1 is concerned. It will only return (and set
3279 * the success flag) when L2 exits (see nested_vmx_vmexit()).
3281 return NVMX_VMENTRY_SUCCESS;
3284 * A failed consistency check that leads to a VMExit during L1's
3285 * VMEnter to L2 is a variation of a normal VMexit, as explained in
3286 * 26.7 "VM-entry failures during or after loading guest state".
3288 vmentry_fail_vmexit_guest_mode:
3289 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
3290 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
3291 leave_guest_mode(vcpu);
3293 vmentry_fail_vmexit:
3294 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
3297 return NVMX_VMENTRY_VMEXIT;
3299 load_vmcs12_host_state(vcpu, vmcs12);
3300 vmcs12->vm_exit_reason = exit_reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
3301 vmcs12->exit_qualification = exit_qual;
3302 if (enable_shadow_vmcs || vmx->nested.hv_evmcs)
3303 vmx->nested.need_vmcs12_to_shadow_sync = true;
3304 return NVMX_VMENTRY_VMEXIT;
3308 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
3309 * for running an L2 nested guest.
3311 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
3313 struct vmcs12 *vmcs12;
3314 enum nvmx_vmentry_status status;
3315 struct vcpu_vmx *vmx = to_vmx(vcpu);
3316 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
3318 if (!nested_vmx_check_permission(vcpu))
3321 if (!nested_vmx_handle_enlightened_vmptrld(vcpu, launch))
3324 if (!vmx->nested.hv_evmcs && vmx->nested.current_vmptr == -1ull)
3325 return nested_vmx_failInvalid(vcpu);
3327 vmcs12 = get_vmcs12(vcpu);
3330 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
3331 * that there *is* a valid VMCS pointer, RFLAGS.CF is set
3332 * rather than RFLAGS.ZF, and no error number is stored to the
3333 * VM-instruction error field.
3335 if (vmcs12->hdr.shadow_vmcs)
3336 return nested_vmx_failInvalid(vcpu);
3338 if (vmx->nested.hv_evmcs) {
3339 copy_enlightened_to_vmcs12(vmx);
3340 /* Enlightened VMCS doesn't have launch state */
3341 vmcs12->launch_state = !launch;
3342 } else if (enable_shadow_vmcs) {
3343 copy_shadow_to_vmcs12(vmx);
3347 * The nested entry process starts with enforcing various prerequisites
3348 * on vmcs12 as required by the Intel SDM, and act appropriately when
3349 * they fail: As the SDM explains, some conditions should cause the
3350 * instruction to fail, while others will cause the instruction to seem
3351 * to succeed, but return an EXIT_REASON_INVALID_STATE.
3352 * To speed up the normal (success) code path, we should avoid checking
3353 * for misconfigurations which will anyway be caught by the processor
3354 * when using the merged vmcs02.
3356 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS)
3357 return nested_vmx_failValid(vcpu,
3358 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
3360 if (vmcs12->launch_state == launch)
3361 return nested_vmx_failValid(vcpu,
3362 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
3363 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
3365 if (nested_vmx_check_controls(vcpu, vmcs12))
3366 return nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3368 if (nested_vmx_check_host_state(vcpu, vmcs12))
3369 return nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
3372 * We're finally done with prerequisite checking, and can start with
3375 vmx->nested.nested_run_pending = 1;
3376 status = nested_vmx_enter_non_root_mode(vcpu, true);
3377 if (unlikely(status != NVMX_VMENTRY_SUCCESS))
3378 goto vmentry_failed;
3380 /* Hide L1D cache contents from the nested guest. */
3381 vmx->vcpu.arch.l1tf_flush_l1d = true;
3384 * Must happen outside of nested_vmx_enter_non_root_mode() as it will
3385 * also be used as part of restoring nVMX state for
3386 * snapshot restore (migration).
3388 * In this flow, it is assumed that vmcs12 cache was
3389 * trasferred as part of captured nVMX state and should
3390 * therefore not be read from guest memory (which may not
3391 * exist on destination host yet).
3393 nested_cache_shadow_vmcs12(vcpu, vmcs12);
3396 * If we're entering a halted L2 vcpu and the L2 vcpu won't be
3397 * awakened by event injection or by an NMI-window VM-exit or
3398 * by an interrupt-window VM-exit, halt the vcpu.
3400 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
3401 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) &&
3402 !(vmcs12->cpu_based_vm_exec_control & CPU_BASED_NMI_WINDOW_EXITING) &&
3403 !((vmcs12->cpu_based_vm_exec_control & CPU_BASED_INTR_WINDOW_EXITING) &&
3404 (vmcs12->guest_rflags & X86_EFLAGS_IF))) {
3405 vmx->nested.nested_run_pending = 0;
3406 return kvm_vcpu_halt(vcpu);
3411 vmx->nested.nested_run_pending = 0;
3412 if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR)
3414 if (status == NVMX_VMENTRY_VMEXIT)
3416 WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL);
3417 return nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3421 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
3422 * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK).
3423 * This function returns the new value we should put in vmcs12.guest_cr0.
3424 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
3425 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
3426 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
3427 * didn't trap the bit, because if L1 did, so would L0).
3428 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
3429 * been modified by L2, and L1 knows it. So just leave the old value of
3430 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
3431 * isn't relevant, because if L0 traps this bit it can set it to anything.
3432 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
3433 * changed these bits, and therefore they need to be updated, but L0
3434 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
3435 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
3437 static inline unsigned long
3438 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3441 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
3442 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
3443 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
3444 vcpu->arch.cr0_guest_owned_bits));
3447 static inline unsigned long
3448 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3451 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
3452 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
3453 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
3454 vcpu->arch.cr4_guest_owned_bits));
3457 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
3458 struct vmcs12 *vmcs12)
3463 if (vcpu->arch.exception.injected) {
3464 nr = vcpu->arch.exception.nr;
3465 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3467 if (kvm_exception_is_soft(nr)) {
3468 vmcs12->vm_exit_instruction_len =
3469 vcpu->arch.event_exit_inst_len;
3470 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
3472 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
3474 if (vcpu->arch.exception.has_error_code) {
3475 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
3476 vmcs12->idt_vectoring_error_code =
3477 vcpu->arch.exception.error_code;
3480 vmcs12->idt_vectoring_info_field = idt_vectoring;
3481 } else if (vcpu->arch.nmi_injected) {
3482 vmcs12->idt_vectoring_info_field =
3483 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
3484 } else if (vcpu->arch.interrupt.injected) {
3485 nr = vcpu->arch.interrupt.nr;
3486 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
3488 if (vcpu->arch.interrupt.soft) {
3489 idt_vectoring |= INTR_TYPE_SOFT_INTR;
3490 vmcs12->vm_entry_instruction_len =
3491 vcpu->arch.event_exit_inst_len;
3493 idt_vectoring |= INTR_TYPE_EXT_INTR;
3495 vmcs12->idt_vectoring_info_field = idt_vectoring;
3500 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
3502 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3506 * Don't need to mark the APIC access page dirty; it is never
3507 * written to by the CPU during APIC virtualization.
3510 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
3511 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
3512 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3515 if (nested_cpu_has_posted_intr(vmcs12)) {
3516 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
3517 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3521 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
3523 struct vcpu_vmx *vmx = to_vmx(vcpu);
3528 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
3531 vmx->nested.pi_pending = false;
3532 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
3535 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
3536 if (max_irr != 256) {
3537 vapic_page = vmx->nested.virtual_apic_map.hva;
3541 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
3542 vapic_page, &max_irr);
3543 status = vmcs_read16(GUEST_INTR_STATUS);
3544 if ((u8)max_irr > ((u8)status & 0xff)) {
3546 status |= (u8)max_irr;
3547 vmcs_write16(GUEST_INTR_STATUS, status);
3551 nested_mark_vmcs12_pages_dirty(vcpu);
3554 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3555 unsigned long exit_qual)
3557 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3558 unsigned int nr = vcpu->arch.exception.nr;
3559 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3561 if (vcpu->arch.exception.has_error_code) {
3562 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3563 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3566 if (kvm_exception_is_soft(nr))
3567 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3569 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3571 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3572 vmx_get_nmi_mask(vcpu))
3573 intr_info |= INTR_INFO_UNBLOCK_NMI;
3575 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3578 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
3580 struct vcpu_vmx *vmx = to_vmx(vcpu);
3581 unsigned long exit_qual;
3582 bool block_nested_events =
3583 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
3584 struct kvm_lapic *apic = vcpu->arch.apic;
3586 if (lapic_in_kernel(vcpu) &&
3587 test_bit(KVM_APIC_INIT, &apic->pending_events)) {
3588 if (block_nested_events)
3590 clear_bit(KVM_APIC_INIT, &apic->pending_events);
3591 nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0);
3595 if (vcpu->arch.exception.pending &&
3596 nested_vmx_check_exception(vcpu, &exit_qual)) {
3597 if (block_nested_events)
3599 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
3603 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
3604 vmx->nested.preemption_timer_expired) {
3605 if (block_nested_events)
3607 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
3611 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
3612 if (block_nested_events)
3614 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
3615 NMI_VECTOR | INTR_TYPE_NMI_INTR |
3616 INTR_INFO_VALID_MASK, 0);
3618 * The NMI-triggered VM exit counts as injection:
3619 * clear this one and block further NMIs.
3621 vcpu->arch.nmi_pending = 0;
3622 vmx_set_nmi_mask(vcpu, true);
3626 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
3627 nested_exit_on_intr(vcpu)) {
3628 if (block_nested_events)
3630 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
3634 vmx_complete_nested_posted_interrupt(vcpu);
3638 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
3641 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
3644 if (ktime_to_ns(remaining) <= 0)
3647 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
3648 do_div(value, 1000000);
3649 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
3652 static bool is_vmcs12_ext_field(unsigned long field)
3655 case GUEST_ES_SELECTOR:
3656 case GUEST_CS_SELECTOR:
3657 case GUEST_SS_SELECTOR:
3658 case GUEST_DS_SELECTOR:
3659 case GUEST_FS_SELECTOR:
3660 case GUEST_GS_SELECTOR:
3661 case GUEST_LDTR_SELECTOR:
3662 case GUEST_TR_SELECTOR:
3663 case GUEST_ES_LIMIT:
3664 case GUEST_CS_LIMIT:
3665 case GUEST_SS_LIMIT:
3666 case GUEST_DS_LIMIT:
3667 case GUEST_FS_LIMIT:
3668 case GUEST_GS_LIMIT:
3669 case GUEST_LDTR_LIMIT:
3670 case GUEST_TR_LIMIT:
3671 case GUEST_GDTR_LIMIT:
3672 case GUEST_IDTR_LIMIT:
3673 case GUEST_ES_AR_BYTES:
3674 case GUEST_DS_AR_BYTES:
3675 case GUEST_FS_AR_BYTES:
3676 case GUEST_GS_AR_BYTES:
3677 case GUEST_LDTR_AR_BYTES:
3678 case GUEST_TR_AR_BYTES:
3685 case GUEST_LDTR_BASE:
3687 case GUEST_GDTR_BASE:
3688 case GUEST_IDTR_BASE:
3689 case GUEST_PENDING_DBG_EXCEPTIONS:
3699 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
3700 struct vmcs12 *vmcs12)
3702 struct vcpu_vmx *vmx = to_vmx(vcpu);
3704 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
3705 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
3706 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
3707 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
3708 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
3709 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
3710 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
3711 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
3712 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
3713 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
3714 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
3715 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
3716 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
3717 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
3718 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
3719 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
3720 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
3721 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
3722 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
3723 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
3724 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
3725 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
3726 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
3727 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
3728 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
3729 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
3730 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
3731 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
3732 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
3733 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
3734 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
3735 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
3736 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
3737 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
3738 vmcs12->guest_pending_dbg_exceptions =
3739 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3740 if (kvm_mpx_supported())
3741 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
3743 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false;
3746 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
3747 struct vmcs12 *vmcs12)
3749 struct vcpu_vmx *vmx = to_vmx(vcpu);
3752 if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare)
3756 WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01);
3759 vmx->loaded_vmcs = &vmx->nested.vmcs02;
3760 vmx_vcpu_load(&vmx->vcpu, cpu);
3762 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
3764 vmx->loaded_vmcs = &vmx->vmcs01;
3765 vmx_vcpu_load(&vmx->vcpu, cpu);
3770 * Update the guest state fields of vmcs12 to reflect changes that
3771 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
3772 * VM-entry controls is also updated, since this is really a guest
3775 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
3777 struct vcpu_vmx *vmx = to_vmx(vcpu);
3779 if (vmx->nested.hv_evmcs)
3780 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
3782 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = !vmx->nested.hv_evmcs;
3784 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
3785 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
3787 vmcs12->guest_rsp = kvm_rsp_read(vcpu);
3788 vmcs12->guest_rip = kvm_rip_read(vcpu);
3789 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
3791 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
3792 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
3794 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
3795 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
3796 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
3798 vmcs12->guest_interruptibility_info =
3799 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3801 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3802 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
3804 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
3806 if (nested_cpu_has_preemption_timer(vmcs12) &&
3807 vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
3808 vmcs12->vmx_preemption_timer_value =
3809 vmx_get_preemption_timer_value(vcpu);
3812 * In some cases (usually, nested EPT), L2 is allowed to change its
3813 * own CR3 without exiting. If it has changed it, we must keep it.
3814 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
3815 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
3817 * Additionally, restore L2's PDPTR to vmcs12.
3820 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
3821 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
3822 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
3823 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
3824 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
3825 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
3829 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
3831 if (nested_cpu_has_vid(vmcs12))
3832 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
3834 vmcs12->vm_entry_controls =
3835 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
3836 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
3838 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS)
3839 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
3841 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
3842 vmcs12->guest_ia32_efer = vcpu->arch.efer;
3846 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
3847 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
3848 * and this function updates it to reflect the changes to the guest state while
3849 * L2 was running (and perhaps made some exits which were handled directly by L0
3850 * without going back to L1), and to reflect the exit reason.
3851 * Note that we do not have to copy here all VMCS fields, just those that
3852 * could have changed by the L2 guest or the exit - i.e., the guest-state and
3853 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
3854 * which already writes to vmcs12 directly.
3856 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
3857 u32 exit_reason, u32 exit_intr_info,
3858 unsigned long exit_qualification)
3860 /* update exit information fields: */
3861 vmcs12->vm_exit_reason = exit_reason;
3862 vmcs12->exit_qualification = exit_qualification;
3863 vmcs12->vm_exit_intr_info = exit_intr_info;
3865 vmcs12->idt_vectoring_info_field = 0;
3866 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3867 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
3869 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
3870 vmcs12->launch_state = 1;
3872 /* vm_entry_intr_info_field is cleared on exit. Emulate this
3873 * instead of reading the real value. */
3874 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
3877 * Transfer the event that L0 or L1 may wanted to inject into
3878 * L2 to IDT_VECTORING_INFO_FIELD.
3880 vmcs12_save_pending_event(vcpu, vmcs12);
3883 * According to spec, there's no need to store the guest's
3884 * MSRs if the exit is due to a VM-entry failure that occurs
3885 * during or after loading the guest state. Since this exit
3886 * does not fall in that category, we need to save the MSRs.
3888 if (nested_vmx_store_msr(vcpu,
3889 vmcs12->vm_exit_msr_store_addr,
3890 vmcs12->vm_exit_msr_store_count))
3891 nested_vmx_abort(vcpu,
3892 VMX_ABORT_SAVE_GUEST_MSR_FAIL);
3896 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
3897 * preserved above and would only end up incorrectly in L1.
3899 vcpu->arch.nmi_injected = false;
3900 kvm_clear_exception_queue(vcpu);
3901 kvm_clear_interrupt_queue(vcpu);
3905 * A part of what we need to when the nested L2 guest exits and we want to
3906 * run its L1 parent, is to reset L1's guest state to the host state specified
3908 * This function is to be called not only on normal nested exit, but also on
3909 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
3910 * Failures During or After Loading Guest State").
3911 * This function should be called when the active VMCS is L1's (vmcs01).
3913 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
3914 struct vmcs12 *vmcs12)
3916 struct kvm_segment seg;
3917 u32 entry_failure_code;
3919 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
3920 vcpu->arch.efer = vmcs12->host_ia32_efer;
3921 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
3922 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
3924 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
3925 vmx_set_efer(vcpu, vcpu->arch.efer);
3927 kvm_rsp_write(vcpu, vmcs12->host_rsp);
3928 kvm_rip_write(vcpu, vmcs12->host_rip);
3929 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
3930 vmx_set_interrupt_shadow(vcpu, 0);
3933 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
3934 * actually changed, because vmx_set_cr0 refers to efer set above.
3936 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
3937 * (KVM doesn't change it);
3939 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
3940 vmx_set_cr0(vcpu, vmcs12->host_cr0);
3942 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
3943 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
3944 vmx_set_cr4(vcpu, vmcs12->host_cr4);
3946 nested_ept_uninit_mmu_context(vcpu);
3949 * Only PDPTE load can fail as the value of cr3 was checked on entry and
3950 * couldn't have changed.
3952 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
3953 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
3956 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3959 * If vmcs01 doesn't use VPID, CPU flushes TLB on every
3960 * VMEntry/VMExit. Thus, no need to flush TLB.
3962 * If vmcs12 doesn't use VPID, L1 expects TLB to be
3963 * flushed on every VMEntry/VMExit.
3965 * Otherwise, we can preserve TLB entries as long as we are
3966 * able to tag L1 TLB entries differently than L2 TLB entries.
3968 * If vmcs12 uses EPT, we need to execute this flush on EPTP01
3969 * and therefore we request the TLB flush to happen only after VMCS EPTP
3970 * has been set by KVM_REQ_LOAD_CR3.
3973 (!nested_cpu_has_vpid(vmcs12) || !nested_has_guest_tlb_tag(vcpu))) {
3974 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3977 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
3978 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
3979 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
3980 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
3981 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
3982 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
3983 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
3985 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
3986 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
3987 vmcs_write64(GUEST_BNDCFGS, 0);
3989 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
3990 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
3991 vcpu->arch.pat = vmcs12->host_ia32_pat;
3993 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
3994 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
3995 vmcs12->host_ia32_perf_global_ctrl));
3997 /* Set L1 segment info according to Intel SDM
3998 27.5.2 Loading Host Segment and Descriptor-Table Registers */
3999 seg = (struct kvm_segment) {
4001 .limit = 0xFFFFFFFF,
4002 .selector = vmcs12->host_cs_selector,
4008 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4012 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
4013 seg = (struct kvm_segment) {
4015 .limit = 0xFFFFFFFF,
4022 seg.selector = vmcs12->host_ds_selector;
4023 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
4024 seg.selector = vmcs12->host_es_selector;
4025 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
4026 seg.selector = vmcs12->host_ss_selector;
4027 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
4028 seg.selector = vmcs12->host_fs_selector;
4029 seg.base = vmcs12->host_fs_base;
4030 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
4031 seg.selector = vmcs12->host_gs_selector;
4032 seg.base = vmcs12->host_gs_base;
4033 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
4034 seg = (struct kvm_segment) {
4035 .base = vmcs12->host_tr_base,
4037 .selector = vmcs12->host_tr_selector,
4041 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
4043 kvm_set_dr(vcpu, 7, 0x400);
4044 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4046 if (cpu_has_vmx_msr_bitmap())
4047 vmx_update_msr_bitmap(vcpu);
4049 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
4050 vmcs12->vm_exit_msr_load_count))
4051 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4054 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
4056 struct shared_msr_entry *efer_msr;
4059 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
4060 return vmcs_read64(GUEST_IA32_EFER);
4062 if (cpu_has_load_ia32_efer())
4065 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
4066 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
4067 return vmx->msr_autoload.guest.val[i].value;
4070 efer_msr = find_msr_entry(vmx, MSR_EFER);
4072 return efer_msr->data;
4077 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
4079 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4080 struct vcpu_vmx *vmx = to_vmx(vcpu);
4081 struct vmx_msr_entry g, h;
4085 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
4087 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
4089 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
4090 * as vmcs01.GUEST_DR7 contains a userspace defined value
4091 * and vcpu->arch.dr7 is not squirreled away before the
4092 * nested VMENTER (not worth adding a variable in nested_vmx).
4094 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
4095 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
4097 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
4101 * Note that calling vmx_set_{efer,cr0,cr4} is important as they
4102 * handle a variety of side effects to KVM's software model.
4104 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
4106 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
4107 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
4109 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
4110 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
4112 nested_ept_uninit_mmu_context(vcpu);
4113 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4114 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
4117 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
4118 * from vmcs01 (if necessary). The PDPTRs are not loaded on
4119 * VMFail, like everything else we just need to ensure our
4120 * software model is up-to-date.
4123 ept_save_pdptrs(vcpu);
4125 kvm_mmu_reset_context(vcpu);
4127 if (cpu_has_vmx_msr_bitmap())
4128 vmx_update_msr_bitmap(vcpu);
4131 * This nasty bit of open coding is a compromise between blindly
4132 * loading L1's MSRs using the exit load lists (incorrect emulation
4133 * of VMFail), leaving the nested VM's MSRs in the software model
4134 * (incorrect behavior) and snapshotting the modified MSRs (too
4135 * expensive since the lists are unbound by hardware). For each
4136 * MSR that was (prematurely) loaded from the nested VMEntry load
4137 * list, reload it from the exit load list if it exists and differs
4138 * from the guest value. The intent is to stuff host state as
4139 * silently as possible, not to fully process the exit load list.
4141 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
4142 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
4143 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
4144 pr_debug_ratelimited(
4145 "%s read MSR index failed (%u, 0x%08llx)\n",
4150 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
4151 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
4152 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
4153 pr_debug_ratelimited(
4154 "%s read MSR failed (%u, 0x%08llx)\n",
4158 if (h.index != g.index)
4160 if (h.value == g.value)
4163 if (nested_vmx_load_msr_check(vcpu, &h)) {
4164 pr_debug_ratelimited(
4165 "%s check failed (%u, 0x%x, 0x%x)\n",
4166 __func__, j, h.index, h.reserved);
4170 if (kvm_set_msr(vcpu, h.index, h.value)) {
4171 pr_debug_ratelimited(
4172 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
4173 __func__, j, h.index, h.value);
4182 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4186 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
4187 * and modify vmcs12 to make it see what it would expect to see there if
4188 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
4190 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
4191 u32 exit_intr_info, unsigned long exit_qualification)
4193 struct vcpu_vmx *vmx = to_vmx(vcpu);
4194 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4196 /* trying to cancel vmlaunch/vmresume is a bug */
4197 WARN_ON_ONCE(vmx->nested.nested_run_pending);
4199 leave_guest_mode(vcpu);
4201 if (nested_cpu_has_preemption_timer(vmcs12))
4202 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
4204 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
4205 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
4207 if (likely(!vmx->fail)) {
4208 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
4210 if (exit_reason != -1)
4211 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
4212 exit_qualification);
4215 * Must happen outside of sync_vmcs02_to_vmcs12() as it will
4216 * also be used to capture vmcs12 cache as part of
4217 * capturing nVMX state for snapshot (migration).
4219 * Otherwise, this flush will dirty guest memory at a
4220 * point it is already assumed by user-space to be
4223 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
4226 * The only expected VM-instruction error is "VM entry with
4227 * invalid control field(s)." Anything else indicates a
4228 * problem with L0. And we should never get here with a
4229 * VMFail of any type if early consistency checks are enabled.
4231 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) !=
4232 VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4233 WARN_ON_ONCE(nested_early_check);
4236 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
4238 /* Update any VMCS fields that might have changed while L2 ran */
4239 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
4240 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
4241 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
4242 if (vmx->nested.l1_tpr_threshold != -1)
4243 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold);
4245 if (kvm_has_tsc_control)
4246 decache_tsc_multiplier(vmx);
4248 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
4249 vmx->nested.change_vmcs01_virtual_apic_mode = false;
4250 vmx_set_virtual_apic_mode(vcpu);
4253 /* Unpin physical memory we referred to in vmcs02 */
4254 if (vmx->nested.apic_access_page) {
4255 kvm_release_page_clean(vmx->nested.apic_access_page);
4256 vmx->nested.apic_access_page = NULL;
4258 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
4259 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
4260 vmx->nested.pi_desc = NULL;
4263 * We are now running in L2, mmu_notifier will force to reload the
4264 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
4266 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4268 if ((exit_reason != -1) && (enable_shadow_vmcs || vmx->nested.hv_evmcs))
4269 vmx->nested.need_vmcs12_to_shadow_sync = true;
4271 /* in case we halted in L2 */
4272 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4274 if (likely(!vmx->fail)) {
4276 * TODO: SDM says that with acknowledge interrupt on
4277 * exit, bit 31 of the VM-exit interrupt information
4278 * (valid interrupt) is always set to 1 on
4279 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
4280 * need kvm_cpu_has_interrupt(). See the commit
4281 * message for details.
4283 if (nested_exit_intr_ack_set(vcpu) &&
4284 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
4285 kvm_cpu_has_interrupt(vcpu)) {
4286 int irq = kvm_cpu_get_interrupt(vcpu);
4288 vmcs12->vm_exit_intr_info = irq |
4289 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
4292 if (exit_reason != -1)
4293 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
4294 vmcs12->exit_qualification,
4295 vmcs12->idt_vectoring_info_field,
4296 vmcs12->vm_exit_intr_info,
4297 vmcs12->vm_exit_intr_error_code,
4300 load_vmcs12_host_state(vcpu, vmcs12);
4306 * After an early L2 VM-entry failure, we're now back
4307 * in L1 which thinks it just finished a VMLAUNCH or
4308 * VMRESUME instruction, so we need to set the failure
4309 * flag and the VM-instruction error field of the VMCS
4310 * accordingly, and skip the emulated instruction.
4312 (void)nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
4315 * Restore L1's host state to KVM's software model. We're here
4316 * because a consistency check was caught by hardware, which
4317 * means some amount of guest state has been propagated to KVM's
4318 * model and needs to be unwound to the host's state.
4320 nested_vmx_restore_host_state(vcpu);
4326 * Decode the memory-address operand of a vmx instruction, as recorded on an
4327 * exit caused by such an instruction (run by a guest hypervisor).
4328 * On success, returns 0. When the operand is invalid, returns 1 and throws
4331 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
4332 u32 vmx_instruction_info, bool wr, int len, gva_t *ret)
4336 struct kvm_segment s;
4339 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4340 * Execution", on an exit, vmx_instruction_info holds most of the
4341 * addressing components of the operand. Only the displacement part
4342 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4343 * For how an actual address is calculated from all these components,
4344 * refer to Vol. 1, "Operand Addressing".
4346 int scaling = vmx_instruction_info & 3;
4347 int addr_size = (vmx_instruction_info >> 7) & 7;
4348 bool is_reg = vmx_instruction_info & (1u << 10);
4349 int seg_reg = (vmx_instruction_info >> 15) & 7;
4350 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4351 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4352 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4353 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4356 kvm_queue_exception(vcpu, UD_VECTOR);
4360 /* Addr = segment_base + offset */
4361 /* offset = base + [index * scale] + displacement */
4362 off = exit_qualification; /* holds the displacement */
4364 off = (gva_t)sign_extend64(off, 31);
4365 else if (addr_size == 0)
4366 off = (gva_t)sign_extend64(off, 15);
4368 off += kvm_register_read(vcpu, base_reg);
4370 off += kvm_register_read(vcpu, index_reg)<<scaling;
4371 vmx_get_segment(vcpu, &s, seg_reg);
4374 * The effective address, i.e. @off, of a memory operand is truncated
4375 * based on the address size of the instruction. Note that this is
4376 * the *effective address*, i.e. the address prior to accounting for
4377 * the segment's base.
4379 if (addr_size == 1) /* 32 bit */
4381 else if (addr_size == 0) /* 16 bit */
4384 /* Checks for #GP/#SS exceptions. */
4386 if (is_long_mode(vcpu)) {
4388 * The virtual/linear address is never truncated in 64-bit
4389 * mode, e.g. a 32-bit address size can yield a 64-bit virtual
4390 * address when using FS/GS with a non-zero base.
4392 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS)
4393 *ret = s.base + off;
4397 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
4398 * non-canonical form. This is the only check on the memory
4399 * destination for long mode!
4401 exn = is_noncanonical_address(*ret, vcpu);
4404 * When not in long mode, the virtual/linear address is
4405 * unconditionally truncated to 32 bits regardless of the
4408 *ret = (s.base + off) & 0xffffffff;
4410 /* Protected mode: apply checks for segment validity in the
4412 * - segment type check (#GP(0) may be thrown)
4413 * - usability check (#GP(0)/#SS(0))
4414 * - limit check (#GP(0)/#SS(0))
4417 /* #GP(0) if the destination operand is located in a
4418 * read-only data segment or any code segment.
4420 exn = ((s.type & 0xa) == 0 || (s.type & 8));
4422 /* #GP(0) if the source operand is located in an
4423 * execute-only code segment
4425 exn = ((s.type & 0xa) == 8);
4427 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4430 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
4432 exn = (s.unusable != 0);
4435 * Protected mode: #GP(0)/#SS(0) if the memory operand is
4436 * outside the segment limit. All CPUs that support VMX ignore
4437 * limit checks for flat segments, i.e. segments with base==0,
4438 * limit==0xffffffff and of type expand-up data or code.
4440 if (!(s.base == 0 && s.limit == 0xffffffff &&
4441 ((s.type & 8) || !(s.type & 4))))
4442 exn = exn || ((u64)off + len - 1 > s.limit);
4445 kvm_queue_exception_e(vcpu,
4446 seg_reg == VCPU_SREG_SS ?
4447 SS_VECTOR : GP_VECTOR,
4455 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
4457 struct vcpu_vmx *vmx;
4459 if (!nested_vmx_allowed(vcpu))
4463 if (kvm_x86_ops->pmu_ops->is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)) {
4464 vmx->nested.msrs.entry_ctls_high |=
4465 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4466 vmx->nested.msrs.exit_ctls_high |=
4467 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
4469 vmx->nested.msrs.entry_ctls_high &=
4470 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4471 vmx->nested.msrs.exit_ctls_high &=
4472 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
4476 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
4479 struct x86_exception e;
4481 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4482 vmcs_read32(VMX_INSTRUCTION_INFO), false,
4483 sizeof(*vmpointer), &gva))
4486 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
4487 kvm_inject_page_fault(vcpu, &e);
4495 * Allocate a shadow VMCS and associate it with the currently loaded
4496 * VMCS, unless such a shadow VMCS already exists. The newly allocated
4497 * VMCS is also VMCLEARed, so that it is ready for use.
4499 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
4501 struct vcpu_vmx *vmx = to_vmx(vcpu);
4502 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
4505 * We should allocate a shadow vmcs for vmcs01 only when L1
4506 * executes VMXON and free it when L1 executes VMXOFF.
4507 * As it is invalid to execute VMXON twice, we shouldn't reach
4508 * here when vmcs01 already have an allocated shadow vmcs.
4510 WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
4512 if (!loaded_vmcs->shadow_vmcs) {
4513 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
4514 if (loaded_vmcs->shadow_vmcs)
4515 vmcs_clear(loaded_vmcs->shadow_vmcs);
4517 return loaded_vmcs->shadow_vmcs;
4520 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
4522 struct vcpu_vmx *vmx = to_vmx(vcpu);
4525 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
4529 vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4530 if (!vmx->nested.cached_vmcs12)
4531 goto out_cached_vmcs12;
4533 vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT);
4534 if (!vmx->nested.cached_shadow_vmcs12)
4535 goto out_cached_shadow_vmcs12;
4537 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
4538 goto out_shadow_vmcs;
4540 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
4541 HRTIMER_MODE_REL_PINNED);
4542 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
4544 vmx->nested.vpid02 = allocate_vpid();
4546 vmx->nested.vmcs02_initialized = false;
4547 vmx->nested.vmxon = true;
4549 if (pt_mode == PT_MODE_HOST_GUEST) {
4550 vmx->pt_desc.guest.ctl = 0;
4551 pt_update_intercept_for_msr(vmx);
4557 kfree(vmx->nested.cached_shadow_vmcs12);
4559 out_cached_shadow_vmcs12:
4560 kfree(vmx->nested.cached_vmcs12);
4563 free_loaded_vmcs(&vmx->nested.vmcs02);
4570 * Emulate the VMXON instruction.
4571 * Currently, we just remember that VMX is active, and do not save or even
4572 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4573 * do not currently need to store anything in that guest-allocated memory
4574 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4575 * argument is different from the VMXON pointer (which the spec says they do).
4577 static int handle_vmon(struct kvm_vcpu *vcpu)
4582 struct vcpu_vmx *vmx = to_vmx(vcpu);
4583 const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED
4584 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
4587 * The Intel VMX Instruction Reference lists a bunch of bits that are
4588 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
4589 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
4590 * Otherwise, we should fail with #UD. But most faulting conditions
4591 * have already been checked by hardware, prior to the VM-exit for
4592 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
4593 * that bit set to 1 in non-root mode.
4595 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
4596 kvm_queue_exception(vcpu, UD_VECTOR);
4600 /* CPL=0 must be checked manually. */
4601 if (vmx_get_cpl(vcpu)) {
4602 kvm_inject_gp(vcpu, 0);
4606 if (vmx->nested.vmxon)
4607 return nested_vmx_failValid(vcpu,
4608 VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
4610 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
4611 != VMXON_NEEDED_FEATURES) {
4612 kvm_inject_gp(vcpu, 0);
4616 if (nested_vmx_get_vmptr(vcpu, &vmptr))
4621 * The first 4 bytes of VMXON region contain the supported
4622 * VMCS revision identifier
4624 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
4625 * which replaces physical address width with 32
4627 if (!page_address_valid(vcpu, vmptr))
4628 return nested_vmx_failInvalid(vcpu);
4630 if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) ||
4631 revision != VMCS12_REVISION)
4632 return nested_vmx_failInvalid(vcpu);
4634 vmx->nested.vmxon_ptr = vmptr;
4635 ret = enter_vmx_operation(vcpu);
4639 return nested_vmx_succeed(vcpu);
4642 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu)
4644 struct vcpu_vmx *vmx = to_vmx(vcpu);
4646 if (vmx->nested.current_vmptr == -1ull)
4649 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu));
4651 if (enable_shadow_vmcs) {
4652 /* copy to memory all shadowed fields in case
4653 they were modified */
4654 copy_shadow_to_vmcs12(vmx);
4655 vmx_disable_shadow_vmcs(vmx);
4657 vmx->nested.posted_intr_nv = -1;
4659 /* Flush VMCS12 to guest memory */
4660 kvm_vcpu_write_guest_page(vcpu,
4661 vmx->nested.current_vmptr >> PAGE_SHIFT,
4662 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
4664 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4666 vmx->nested.current_vmptr = -1ull;
4669 /* Emulate the VMXOFF instruction */
4670 static int handle_vmoff(struct kvm_vcpu *vcpu)
4672 if (!nested_vmx_check_permission(vcpu))
4677 /* Process a latched INIT during time CPU was in VMX operation */
4678 kvm_make_request(KVM_REQ_EVENT, vcpu);
4680 return nested_vmx_succeed(vcpu);
4683 /* Emulate the VMCLEAR instruction */
4684 static int handle_vmclear(struct kvm_vcpu *vcpu)
4686 struct vcpu_vmx *vmx = to_vmx(vcpu);
4691 if (!nested_vmx_check_permission(vcpu))
4694 if (nested_vmx_get_vmptr(vcpu, &vmptr))
4697 if (!page_address_valid(vcpu, vmptr))
4698 return nested_vmx_failValid(vcpu,
4699 VMXERR_VMCLEAR_INVALID_ADDRESS);
4701 if (vmptr == vmx->nested.vmxon_ptr)
4702 return nested_vmx_failValid(vcpu,
4703 VMXERR_VMCLEAR_VMXON_POINTER);
4706 * When Enlightened VMEntry is enabled on the calling CPU we treat
4707 * memory area pointer by vmptr as Enlightened VMCS (as there's no good
4708 * way to distinguish it from VMCS12) and we must not corrupt it by
4709 * writing to the non-existent 'launch_state' field. The area doesn't
4710 * have to be the currently active EVMCS on the calling CPU and there's
4711 * nothing KVM has to do to transition it from 'active' to 'non-active'
4712 * state. It is possible that the area will stay mapped as
4713 * vmx->nested.hv_evmcs but this shouldn't be a problem.
4715 if (likely(!vmx->nested.enlightened_vmcs_enabled ||
4716 !nested_enlightened_vmentry(vcpu, &evmcs_gpa))) {
4717 if (vmptr == vmx->nested.current_vmptr)
4718 nested_release_vmcs12(vcpu);
4720 kvm_vcpu_write_guest(vcpu,
4721 vmptr + offsetof(struct vmcs12,
4723 &zero, sizeof(zero));
4726 return nested_vmx_succeed(vcpu);
4729 /* Emulate the VMLAUNCH instruction */
4730 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
4732 return nested_vmx_run(vcpu, true);
4735 /* Emulate the VMRESUME instruction */
4736 static int handle_vmresume(struct kvm_vcpu *vcpu)
4739 return nested_vmx_run(vcpu, false);
4742 static int handle_vmread(struct kvm_vcpu *vcpu)
4744 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
4746 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4747 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4748 struct vcpu_vmx *vmx = to_vmx(vcpu);
4749 struct x86_exception e;
4750 unsigned long field;
4756 if (!nested_vmx_check_permission(vcpu))
4760 * In VMX non-root operation, when the VMCS-link pointer is -1ull,
4761 * any VMREAD sets the ALU flags for VMfailInvalid.
4763 if (vmx->nested.current_vmptr == -1ull ||
4764 (is_guest_mode(vcpu) &&
4765 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull))
4766 return nested_vmx_failInvalid(vcpu);
4768 /* Decode instruction info and find the field to read */
4769 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf));
4771 offset = vmcs_field_to_offset(field);
4773 return nested_vmx_failValid(vcpu,
4774 VMXERR_UNSUPPORTED_VMCS_COMPONENT);
4776 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field))
4777 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4779 /* Read the field, zero-extended to a u64 value */
4780 value = vmcs12_read_any(vmcs12, field, offset);
4783 * Now copy part of this value to register or memory, as requested.
4784 * Note that the number of bits actually copied is 32 or 64 depending
4785 * on the guest's mode (32 or 64 bit), not on the given field's length.
4787 if (instr_info & BIT(10)) {
4788 kvm_register_writel(vcpu, (((instr_info) >> 3) & 0xf), value);
4790 len = is_64_bit_mode(vcpu) ? 8 : 4;
4791 if (get_vmx_mem_address(vcpu, exit_qualification,
4792 instr_info, true, len, &gva))
4794 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
4795 if (kvm_write_guest_virt_system(vcpu, gva, &value, len, &e)) {
4796 kvm_inject_page_fault(vcpu, &e);
4801 return nested_vmx_succeed(vcpu);
4804 static bool is_shadow_field_rw(unsigned long field)
4807 #define SHADOW_FIELD_RW(x, y) case x:
4808 #include "vmcs_shadow_fields.h"
4816 static bool is_shadow_field_ro(unsigned long field)
4819 #define SHADOW_FIELD_RO(x, y) case x:
4820 #include "vmcs_shadow_fields.h"
4828 static int handle_vmwrite(struct kvm_vcpu *vcpu)
4830 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu)
4832 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4833 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4834 struct vcpu_vmx *vmx = to_vmx(vcpu);
4835 struct x86_exception e;
4836 unsigned long field;
4842 * The value to write might be 32 or 64 bits, depending on L1's long
4843 * mode, and eventually we need to write that into a field of several
4844 * possible lengths. The code below first zero-extends the value to 64
4845 * bit (value), and then copies only the appropriate number of
4846 * bits into the vmcs12 field.
4850 if (!nested_vmx_check_permission(vcpu))
4854 * In VMX non-root operation, when the VMCS-link pointer is -1ull,
4855 * any VMWRITE sets the ALU flags for VMfailInvalid.
4857 if (vmx->nested.current_vmptr == -1ull ||
4858 (is_guest_mode(vcpu) &&
4859 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull))
4860 return nested_vmx_failInvalid(vcpu);
4862 if (instr_info & BIT(10))
4863 value = kvm_register_readl(vcpu, (((instr_info) >> 3) & 0xf));
4865 len = is_64_bit_mode(vcpu) ? 8 : 4;
4866 if (get_vmx_mem_address(vcpu, exit_qualification,
4867 instr_info, false, len, &gva))
4869 if (kvm_read_guest_virt(vcpu, gva, &value, len, &e)) {
4870 kvm_inject_page_fault(vcpu, &e);
4875 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf));
4877 offset = vmcs_field_to_offset(field);
4879 return nested_vmx_failValid(vcpu,
4880 VMXERR_UNSUPPORTED_VMCS_COMPONENT);
4883 * If the vCPU supports "VMWRITE to any supported field in the
4884 * VMCS," then the "read-only" fields are actually read/write.
4886 if (vmcs_field_readonly(field) &&
4887 !nested_cpu_has_vmwrite_any_field(vcpu))
4888 return nested_vmx_failValid(vcpu,
4889 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
4892 * Ensure vmcs12 is up-to-date before any VMWRITE that dirties
4893 * vmcs12, else we may crush a field or consume a stale value.
4895 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field))
4896 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
4899 * Some Intel CPUs intentionally drop the reserved bits of the AR byte
4900 * fields on VMWRITE. Emulate this behavior to ensure consistent KVM
4901 * behavior regardless of the underlying hardware, e.g. if an AR_BYTE
4902 * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD
4903 * from L1 will return a different value than VMREAD from L2 (L1 sees
4904 * the stripped down value, L2 sees the full value as stored by KVM).
4906 if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES)
4909 vmcs12_write_any(vmcs12, field, offset, value);
4912 * Do not track vmcs12 dirty-state if in guest-mode as we actually
4913 * dirty shadow vmcs12 instead of vmcs12. Fields that can be updated
4914 * by L1 without a vmexit are always updated in the vmcs02, i.e. don't
4915 * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path.
4917 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) {
4919 * L1 can read these fields without exiting, ensure the
4920 * shadow VMCS is up-to-date.
4922 if (enable_shadow_vmcs && is_shadow_field_ro(field)) {
4924 vmcs_load(vmx->vmcs01.shadow_vmcs);
4926 __vmcs_writel(field, value);
4928 vmcs_clear(vmx->vmcs01.shadow_vmcs);
4929 vmcs_load(vmx->loaded_vmcs->vmcs);
4932 vmx->nested.dirty_vmcs12 = true;
4935 return nested_vmx_succeed(vcpu);
4938 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
4940 vmx->nested.current_vmptr = vmptr;
4941 if (enable_shadow_vmcs) {
4942 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS);
4943 vmcs_write64(VMCS_LINK_POINTER,
4944 __pa(vmx->vmcs01.shadow_vmcs));
4945 vmx->nested.need_vmcs12_to_shadow_sync = true;
4947 vmx->nested.dirty_vmcs12 = true;
4950 /* Emulate the VMPTRLD instruction */
4951 static int handle_vmptrld(struct kvm_vcpu *vcpu)
4953 struct vcpu_vmx *vmx = to_vmx(vcpu);
4956 if (!nested_vmx_check_permission(vcpu))
4959 if (nested_vmx_get_vmptr(vcpu, &vmptr))
4962 if (!page_address_valid(vcpu, vmptr))
4963 return nested_vmx_failValid(vcpu,
4964 VMXERR_VMPTRLD_INVALID_ADDRESS);
4966 if (vmptr == vmx->nested.vmxon_ptr)
4967 return nested_vmx_failValid(vcpu,
4968 VMXERR_VMPTRLD_VMXON_POINTER);
4970 /* Forbid normal VMPTRLD if Enlightened version was used */
4971 if (vmx->nested.hv_evmcs)
4974 if (vmx->nested.current_vmptr != vmptr) {
4975 struct kvm_host_map map;
4976 struct vmcs12 *new_vmcs12;
4978 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmptr), &map)) {
4980 * Reads from an unbacked page return all 1s,
4981 * which means that the 32 bits located at the
4982 * given physical address won't match the required
4983 * VMCS12_REVISION identifier.
4985 return nested_vmx_failValid(vcpu,
4986 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
4989 new_vmcs12 = map.hva;
4991 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
4992 (new_vmcs12->hdr.shadow_vmcs &&
4993 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
4994 kvm_vcpu_unmap(vcpu, &map, false);
4995 return nested_vmx_failValid(vcpu,
4996 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
4999 nested_release_vmcs12(vcpu);
5002 * Load VMCS12 from guest memory since it is not already
5005 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
5006 kvm_vcpu_unmap(vcpu, &map, false);
5008 set_current_vmptr(vmx, vmptr);
5011 return nested_vmx_succeed(vcpu);
5014 /* Emulate the VMPTRST instruction */
5015 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5017 unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION);
5018 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5019 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
5020 struct x86_exception e;
5023 if (!nested_vmx_check_permission(vcpu))
5026 if (unlikely(to_vmx(vcpu)->nested.hv_evmcs))
5029 if (get_vmx_mem_address(vcpu, exit_qual, instr_info,
5030 true, sizeof(gpa_t), &gva))
5032 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
5033 if (kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr,
5034 sizeof(gpa_t), &e)) {
5035 kvm_inject_page_fault(vcpu, &e);
5038 return nested_vmx_succeed(vcpu);
5041 /* Emulate the INVEPT instruction */
5042 static int handle_invept(struct kvm_vcpu *vcpu)
5044 struct vcpu_vmx *vmx = to_vmx(vcpu);
5045 u32 vmx_instruction_info, types;
5048 struct x86_exception e;
5053 if (!(vmx->nested.msrs.secondary_ctls_high &
5054 SECONDARY_EXEC_ENABLE_EPT) ||
5055 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
5056 kvm_queue_exception(vcpu, UD_VECTOR);
5060 if (!nested_vmx_check_permission(vcpu))
5063 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5064 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5066 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
5068 if (type >= 32 || !(types & (1 << type)))
5069 return nested_vmx_failValid(vcpu,
5070 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5072 /* According to the Intel VMX instruction reference, the memory
5073 * operand is read even if it isn't needed (e.g., for type==global)
5075 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5076 vmx_instruction_info, false, sizeof(operand), &gva))
5078 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5079 kvm_inject_page_fault(vcpu, &e);
5084 case VMX_EPT_EXTENT_GLOBAL:
5085 case VMX_EPT_EXTENT_CONTEXT:
5087 * TODO: Sync the necessary shadow EPT roots here, rather than
5088 * at the next emulated VM-entry.
5096 return nested_vmx_succeed(vcpu);
5099 static int handle_invvpid(struct kvm_vcpu *vcpu)
5101 struct vcpu_vmx *vmx = to_vmx(vcpu);
5102 u32 vmx_instruction_info;
5103 unsigned long type, types;
5105 struct x86_exception e;
5112 if (!(vmx->nested.msrs.secondary_ctls_high &
5113 SECONDARY_EXEC_ENABLE_VPID) ||
5114 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
5115 kvm_queue_exception(vcpu, UD_VECTOR);
5119 if (!nested_vmx_check_permission(vcpu))
5122 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5123 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5125 types = (vmx->nested.msrs.vpid_caps &
5126 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
5128 if (type >= 32 || !(types & (1 << type)))
5129 return nested_vmx_failValid(vcpu,
5130 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5132 /* according to the intel vmx instruction reference, the memory
5133 * operand is read even if it isn't needed (e.g., for type==global)
5135 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5136 vmx_instruction_info, false, sizeof(operand), &gva))
5138 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5139 kvm_inject_page_fault(vcpu, &e);
5142 if (operand.vpid >> 16)
5143 return nested_vmx_failValid(vcpu,
5144 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5146 vpid02 = nested_get_vpid02(vcpu);
5148 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
5149 if (!operand.vpid ||
5150 is_noncanonical_address(operand.gla, vcpu))
5151 return nested_vmx_failValid(vcpu,
5152 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5153 if (cpu_has_vmx_invvpid_individual_addr()) {
5154 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
5155 vpid02, operand.gla);
5157 __vmx_flush_tlb(vcpu, vpid02, false);
5159 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
5160 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
5162 return nested_vmx_failValid(vcpu,
5163 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
5164 __vmx_flush_tlb(vcpu, vpid02, false);
5166 case VMX_VPID_EXTENT_ALL_CONTEXT:
5167 __vmx_flush_tlb(vcpu, vpid02, false);
5171 return kvm_skip_emulated_instruction(vcpu);
5174 return nested_vmx_succeed(vcpu);
5177 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
5178 struct vmcs12 *vmcs12)
5180 u32 index = kvm_rcx_read(vcpu);
5182 bool accessed_dirty;
5183 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5185 if (!nested_cpu_has_eptp_switching(vmcs12) ||
5186 !nested_cpu_has_ept(vmcs12))
5189 if (index >= VMFUNC_EPTP_ENTRIES)
5193 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
5194 &address, index * 8, 8))
5197 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
5200 * If the (L2) guest does a vmfunc to the currently
5201 * active ept pointer, we don't have to do anything else
5203 if (vmcs12->ept_pointer != address) {
5204 if (!valid_ept_address(vcpu, address))
5207 kvm_mmu_unload(vcpu);
5208 mmu->ept_ad = accessed_dirty;
5209 mmu->mmu_role.base.ad_disabled = !accessed_dirty;
5210 vmcs12->ept_pointer = address;
5212 * TODO: Check what's the correct approach in case
5213 * mmu reload fails. Currently, we just let the next
5214 * reload potentially fail
5216 kvm_mmu_reload(vcpu);
5222 static int handle_vmfunc(struct kvm_vcpu *vcpu)
5224 struct vcpu_vmx *vmx = to_vmx(vcpu);
5225 struct vmcs12 *vmcs12;
5226 u32 function = kvm_rax_read(vcpu);
5229 * VMFUNC is only supported for nested guests, but we always enable the
5230 * secondary control for simplicity; for non-nested mode, fake that we
5231 * didn't by injecting #UD.
5233 if (!is_guest_mode(vcpu)) {
5234 kvm_queue_exception(vcpu, UD_VECTOR);
5238 vmcs12 = get_vmcs12(vcpu);
5239 if ((vmcs12->vm_function_control & (1 << function)) == 0)
5244 if (nested_vmx_eptp_switching(vcpu, vmcs12))
5250 return kvm_skip_emulated_instruction(vcpu);
5253 nested_vmx_vmexit(vcpu, vmx->exit_reason,
5254 vmcs_read32(VM_EXIT_INTR_INFO),
5255 vmcs_readl(EXIT_QUALIFICATION));
5260 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5261 struct vmcs12 *vmcs12)
5263 unsigned long exit_qualification;
5264 gpa_t bitmap, last_bitmap;
5269 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5270 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
5272 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5274 port = exit_qualification >> 16;
5275 size = (exit_qualification & 7) + 1;
5277 last_bitmap = (gpa_t)-1;
5282 bitmap = vmcs12->io_bitmap_a;
5283 else if (port < 0x10000)
5284 bitmap = vmcs12->io_bitmap_b;
5287 bitmap += (port & 0x7fff) / 8;
5289 if (last_bitmap != bitmap)
5290 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
5292 if (b & (1 << (port & 7)))
5297 last_bitmap = bitmap;
5304 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5305 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5306 * disinterest in the current event (read or write a specific MSR) by using an
5307 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5309 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5310 struct vmcs12 *vmcs12, u32 exit_reason)
5312 u32 msr_index = kvm_rcx_read(vcpu);
5315 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5319 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5320 * for the four combinations of read/write and low/high MSR numbers.
5321 * First we need to figure out which of the four to use:
5323 bitmap = vmcs12->msr_bitmap;
5324 if (exit_reason == EXIT_REASON_MSR_WRITE)
5326 if (msr_index >= 0xc0000000) {
5327 msr_index -= 0xc0000000;
5331 /* Then read the msr_index'th bit from this bitmap: */
5332 if (msr_index < 1024*8) {
5334 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
5336 return 1 & (b >> (msr_index & 7));
5338 return true; /* let L1 handle the wrong parameter */
5342 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5343 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5344 * intercept (via guest_host_mask etc.) the current event.
5346 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5347 struct vmcs12 *vmcs12)
5349 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5350 int cr = exit_qualification & 15;
5354 switch ((exit_qualification >> 4) & 3) {
5355 case 0: /* mov to cr */
5356 reg = (exit_qualification >> 8) & 15;
5357 val = kvm_register_readl(vcpu, reg);
5360 if (vmcs12->cr0_guest_host_mask &
5361 (val ^ vmcs12->cr0_read_shadow))
5365 if ((vmcs12->cr3_target_count >= 1 &&
5366 vmcs12->cr3_target_value0 == val) ||
5367 (vmcs12->cr3_target_count >= 2 &&
5368 vmcs12->cr3_target_value1 == val) ||
5369 (vmcs12->cr3_target_count >= 3 &&
5370 vmcs12->cr3_target_value2 == val) ||
5371 (vmcs12->cr3_target_count >= 4 &&
5372 vmcs12->cr3_target_value3 == val))
5374 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5378 if (vmcs12->cr4_guest_host_mask &
5379 (vmcs12->cr4_read_shadow ^ val))
5383 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5389 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5390 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5393 case 1: /* mov from cr */
5396 if (vmcs12->cpu_based_vm_exec_control &
5397 CPU_BASED_CR3_STORE_EXITING)
5401 if (vmcs12->cpu_based_vm_exec_control &
5402 CPU_BASED_CR8_STORE_EXITING)
5409 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5410 * cr0. Other attempted changes are ignored, with no exit.
5412 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5413 if (vmcs12->cr0_guest_host_mask & 0xe &
5414 (val ^ vmcs12->cr0_read_shadow))
5416 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5417 !(vmcs12->cr0_read_shadow & 0x1) &&
5425 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
5426 struct vmcs12 *vmcs12, gpa_t bitmap)
5428 u32 vmx_instruction_info;
5429 unsigned long field;
5432 if (!nested_cpu_has_shadow_vmcs(vmcs12))
5435 /* Decode instruction info and find the field to access */
5436 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5437 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5439 /* Out-of-range fields always cause a VM exit from L2 to L1 */
5443 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
5446 return 1 & (b >> (field & 7));
5450 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5451 * should handle it ourselves in L0 (and then continue L2). Only call this
5452 * when in is_guest_mode (L2).
5454 bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
5456 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5457 struct vcpu_vmx *vmx = to_vmx(vcpu);
5458 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5460 if (vmx->nested.nested_run_pending)
5463 if (unlikely(vmx->fail)) {
5464 trace_kvm_nested_vmenter_failed(
5465 "hardware VM-instruction error: ",
5466 vmcs_read32(VM_INSTRUCTION_ERROR));
5471 * The host physical addresses of some pages of guest memory
5472 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5473 * Page). The CPU may write to these pages via their host
5474 * physical address while L2 is running, bypassing any
5475 * address-translation-based dirty tracking (e.g. EPT write
5478 * Mark them dirty on every exit from L2 to prevent them from
5479 * getting out of sync with dirty tracking.
5481 nested_mark_vmcs12_pages_dirty(vcpu);
5483 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
5484 vmcs_readl(EXIT_QUALIFICATION),
5485 vmx->idt_vectoring_info,
5487 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5490 switch (exit_reason) {
5491 case EXIT_REASON_EXCEPTION_NMI:
5492 if (is_nmi(intr_info))
5494 else if (is_page_fault(intr_info))
5495 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
5496 else if (is_debug(intr_info) &&
5498 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5500 else if (is_breakpoint(intr_info) &&
5501 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5503 return vmcs12->exception_bitmap &
5504 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5505 case EXIT_REASON_EXTERNAL_INTERRUPT:
5507 case EXIT_REASON_TRIPLE_FAULT:
5509 case EXIT_REASON_INTERRUPT_WINDOW:
5510 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING);
5511 case EXIT_REASON_NMI_WINDOW:
5512 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING);
5513 case EXIT_REASON_TASK_SWITCH:
5515 case EXIT_REASON_CPUID:
5517 case EXIT_REASON_HLT:
5518 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5519 case EXIT_REASON_INVD:
5521 case EXIT_REASON_INVLPG:
5522 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5523 case EXIT_REASON_RDPMC:
5524 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5525 case EXIT_REASON_RDRAND:
5526 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
5527 case EXIT_REASON_RDSEED:
5528 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
5529 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
5530 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5531 case EXIT_REASON_VMREAD:
5532 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
5533 vmcs12->vmread_bitmap);
5534 case EXIT_REASON_VMWRITE:
5535 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
5536 vmcs12->vmwrite_bitmap);
5537 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5538 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5539 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
5540 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5541 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
5543 * VMX instructions trap unconditionally. This allows L1 to
5544 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5547 case EXIT_REASON_CR_ACCESS:
5548 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5549 case EXIT_REASON_DR_ACCESS:
5550 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5551 case EXIT_REASON_IO_INSTRUCTION:
5552 return nested_vmx_exit_handled_io(vcpu, vmcs12);
5553 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
5554 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
5555 case EXIT_REASON_MSR_READ:
5556 case EXIT_REASON_MSR_WRITE:
5557 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5558 case EXIT_REASON_INVALID_STATE:
5560 case EXIT_REASON_MWAIT_INSTRUCTION:
5561 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5562 case EXIT_REASON_MONITOR_TRAP_FLAG:
5563 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
5564 case EXIT_REASON_MONITOR_INSTRUCTION:
5565 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5566 case EXIT_REASON_PAUSE_INSTRUCTION:
5567 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5568 nested_cpu_has2(vmcs12,
5569 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5570 case EXIT_REASON_MCE_DURING_VMENTRY:
5572 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5573 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
5574 case EXIT_REASON_APIC_ACCESS:
5575 case EXIT_REASON_APIC_WRITE:
5576 case EXIT_REASON_EOI_INDUCED:
5578 * The controls for "virtualize APIC accesses," "APIC-
5579 * register virtualization," and "virtual-interrupt
5580 * delivery" only come from vmcs12.
5583 case EXIT_REASON_EPT_VIOLATION:
5585 * L0 always deals with the EPT violation. If nested EPT is
5586 * used, and the nested mmu code discovers that the address is
5587 * missing in the guest EPT table (EPT12), the EPT violation
5588 * will be injected with nested_ept_inject_page_fault()
5591 case EXIT_REASON_EPT_MISCONFIG:
5593 * L2 never uses directly L1's EPT, but rather L0's own EPT
5594 * table (shadow on EPT) or a merged EPT table that L0 built
5595 * (EPT on EPT). So any problems with the structure of the
5596 * table is L0's fault.
5599 case EXIT_REASON_INVPCID:
5601 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
5602 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5603 case EXIT_REASON_WBINVD:
5604 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5605 case EXIT_REASON_XSETBV:
5607 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
5609 * This should never happen, since it is not possible to
5610 * set XSS to a non-zero value---neither in L1 nor in L2.
5611 * If if it were, XSS would have to be checked against
5612 * the XSS exit bitmap in vmcs12.
5614 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
5615 case EXIT_REASON_PREEMPTION_TIMER:
5617 case EXIT_REASON_PML_FULL:
5618 /* We emulate PML support to L1. */
5620 case EXIT_REASON_VMFUNC:
5621 /* VM functions are emulated through L2->L0 vmexits. */
5623 case EXIT_REASON_ENCLS:
5624 /* SGX is never exposed to L1 */
5626 case EXIT_REASON_UMWAIT:
5627 case EXIT_REASON_TPAUSE:
5628 return nested_cpu_has2(vmcs12,
5629 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE);
5636 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
5637 struct kvm_nested_state __user *user_kvm_nested_state,
5640 struct vcpu_vmx *vmx;
5641 struct vmcs12 *vmcs12;
5642 struct kvm_nested_state kvm_state = {
5644 .format = KVM_STATE_NESTED_FORMAT_VMX,
5645 .size = sizeof(kvm_state),
5646 .hdr.vmx.vmxon_pa = -1ull,
5647 .hdr.vmx.vmcs12_pa = -1ull,
5649 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
5650 &user_kvm_nested_state->data.vmx[0];
5653 return kvm_state.size + sizeof(*user_vmx_nested_state);
5656 vmcs12 = get_vmcs12(vcpu);
5658 if (nested_vmx_allowed(vcpu) &&
5659 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
5660 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
5661 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr;
5663 if (vmx_has_valid_vmcs12(vcpu)) {
5664 kvm_state.size += sizeof(user_vmx_nested_state->vmcs12);
5666 if (vmx->nested.hv_evmcs)
5667 kvm_state.flags |= KVM_STATE_NESTED_EVMCS;
5669 if (is_guest_mode(vcpu) &&
5670 nested_cpu_has_shadow_vmcs(vmcs12) &&
5671 vmcs12->vmcs_link_pointer != -1ull)
5672 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12);
5675 if (vmx->nested.smm.vmxon)
5676 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
5678 if (vmx->nested.smm.guest_mode)
5679 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
5681 if (is_guest_mode(vcpu)) {
5682 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
5684 if (vmx->nested.nested_run_pending)
5685 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
5689 if (user_data_size < kvm_state.size)
5692 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
5695 if (!vmx_has_valid_vmcs12(vcpu))
5699 * When running L2, the authoritative vmcs12 state is in the
5700 * vmcs02. When running L1, the authoritative vmcs12 state is
5701 * in the shadow or enlightened vmcs linked to vmcs01, unless
5702 * need_vmcs12_to_shadow_sync is set, in which case, the authoritative
5703 * vmcs12 state is in the vmcs12 already.
5705 if (is_guest_mode(vcpu)) {
5706 sync_vmcs02_to_vmcs12(vcpu, vmcs12);
5707 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12);
5708 } else if (!vmx->nested.need_vmcs12_to_shadow_sync) {
5709 if (vmx->nested.hv_evmcs)
5710 copy_enlightened_to_vmcs12(vmx);
5711 else if (enable_shadow_vmcs)
5712 copy_shadow_to_vmcs12(vmx);
5715 BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE);
5716 BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE);
5719 * Copy over the full allocated size of vmcs12 rather than just the size
5722 if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE))
5725 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
5726 vmcs12->vmcs_link_pointer != -1ull) {
5727 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12,
5728 get_shadow_vmcs12(vcpu), VMCS12_SIZE))
5733 return kvm_state.size;
5737 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
5739 void vmx_leave_nested(struct kvm_vcpu *vcpu)
5741 if (is_guest_mode(vcpu)) {
5742 to_vmx(vcpu)->nested.nested_run_pending = 0;
5743 nested_vmx_vmexit(vcpu, -1, 0, 0);
5748 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
5749 struct kvm_nested_state __user *user_kvm_nested_state,
5750 struct kvm_nested_state *kvm_state)
5752 struct vcpu_vmx *vmx = to_vmx(vcpu);
5753 struct vmcs12 *vmcs12;
5755 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state =
5756 &user_kvm_nested_state->data.vmx[0];
5759 if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX)
5762 if (kvm_state->hdr.vmx.vmxon_pa == -1ull) {
5763 if (kvm_state->hdr.vmx.smm.flags)
5766 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull)
5770 * KVM_STATE_NESTED_EVMCS used to signal that KVM should
5771 * enable eVMCS capability on vCPU. However, since then
5772 * code was changed such that flag signals vmcs12 should
5773 * be copied into eVMCS in guest memory.
5775 * To preserve backwards compatability, allow user
5776 * to set this flag even when there is no VMXON region.
5778 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS)
5781 if (!nested_vmx_allowed(vcpu))
5784 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa))
5788 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
5789 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
5792 if (kvm_state->hdr.vmx.smm.flags &
5793 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
5797 * SMM temporarily disables VMX, so we cannot be in guest mode,
5798 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags
5803 (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING))
5804 : kvm_state->hdr.vmx.smm.flags)
5807 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
5808 !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
5811 if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) &&
5812 (!nested_vmx_allowed(vcpu) || !vmx->nested.enlightened_vmcs_enabled))
5815 vmx_leave_nested(vcpu);
5817 if (kvm_state->hdr.vmx.vmxon_pa == -1ull)
5820 vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa;
5821 ret = enter_vmx_operation(vcpu);
5825 /* Empty 'VMXON' state is permitted */
5826 if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12))
5829 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull) {
5830 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa ||
5831 !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa))
5834 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa);
5835 } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) {
5837 * Sync eVMCS upon entry as we may not have
5838 * HV_X64_MSR_VP_ASSIST_PAGE set up yet.
5840 vmx->nested.need_vmcs12_to_shadow_sync = true;
5845 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
5846 vmx->nested.smm.vmxon = true;
5847 vmx->nested.vmxon = false;
5849 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
5850 vmx->nested.smm.guest_mode = true;
5853 vmcs12 = get_vmcs12(vcpu);
5854 if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12)))
5857 if (vmcs12->hdr.revision_id != VMCS12_REVISION)
5860 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
5863 vmx->nested.nested_run_pending =
5864 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
5867 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
5868 vmcs12->vmcs_link_pointer != -1ull) {
5869 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
5871 if (kvm_state->size <
5872 sizeof(*kvm_state) +
5873 sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12))
5874 goto error_guest_mode;
5876 if (copy_from_user(shadow_vmcs12,
5877 user_vmx_nested_state->shadow_vmcs12,
5878 sizeof(*shadow_vmcs12))) {
5880 goto error_guest_mode;
5883 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
5884 !shadow_vmcs12->hdr.shadow_vmcs)
5885 goto error_guest_mode;
5888 if (nested_vmx_check_controls(vcpu, vmcs12) ||
5889 nested_vmx_check_host_state(vcpu, vmcs12) ||
5890 nested_vmx_check_guest_state(vcpu, vmcs12, &exit_qual))
5891 goto error_guest_mode;
5893 vmx->nested.dirty_vmcs12 = true;
5894 ret = nested_vmx_enter_non_root_mode(vcpu, false);
5896 goto error_guest_mode;
5901 vmx->nested.nested_run_pending = 0;
5905 void nested_vmx_set_vmcs_shadowing_bitmap(void)
5907 if (enable_shadow_vmcs) {
5908 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5909 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5914 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
5915 * returned for the various VMX controls MSRs when nested VMX is enabled.
5916 * The same values should also be used to verify that vmcs12 control fields are
5917 * valid during nested entry from L1 to L2.
5918 * Each of these control msrs has a low and high 32-bit half: A low bit is on
5919 * if the corresponding bit in the (32-bit) control field *must* be on, and a
5920 * bit in the high half is on if the corresponding bit in the control field
5921 * may be on. See also vmx_control_verify().
5923 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
5927 * Note that as a general rule, the high half of the MSRs (bits in
5928 * the control fields which may be 1) should be initialized by the
5929 * intersection of the underlying hardware's MSR (i.e., features which
5930 * can be supported) and the list of features we want to expose -
5931 * because they are known to be properly supported in our code.
5932 * Also, usually, the low half of the MSRs (bits which must be 1) can
5933 * be set to 0, meaning that L1 may turn off any of these bits. The
5934 * reason is that if one of these bits is necessary, it will appear
5935 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
5936 * fields of vmcs01 and vmcs02, will turn these bits off - and
5937 * nested_vmx_exit_reflected() will not pass related exits to L1.
5938 * These rules have exceptions below.
5941 /* pin-based controls */
5942 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
5943 msrs->pinbased_ctls_low,
5944 msrs->pinbased_ctls_high);
5945 msrs->pinbased_ctls_low |=
5946 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
5947 msrs->pinbased_ctls_high &=
5948 PIN_BASED_EXT_INTR_MASK |
5949 PIN_BASED_NMI_EXITING |
5950 PIN_BASED_VIRTUAL_NMIS |
5951 (apicv ? PIN_BASED_POSTED_INTR : 0);
5952 msrs->pinbased_ctls_high |=
5953 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
5954 PIN_BASED_VMX_PREEMPTION_TIMER;
5957 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
5958 msrs->exit_ctls_low,
5959 msrs->exit_ctls_high);
5960 msrs->exit_ctls_low =
5961 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
5963 msrs->exit_ctls_high &=
5964 #ifdef CONFIG_X86_64
5965 VM_EXIT_HOST_ADDR_SPACE_SIZE |
5967 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
5968 msrs->exit_ctls_high |=
5969 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
5970 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
5971 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
5973 /* We support free control of debug control saving. */
5974 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
5976 /* entry controls */
5977 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
5978 msrs->entry_ctls_low,
5979 msrs->entry_ctls_high);
5980 msrs->entry_ctls_low =
5981 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
5982 msrs->entry_ctls_high &=
5983 #ifdef CONFIG_X86_64
5984 VM_ENTRY_IA32E_MODE |
5986 VM_ENTRY_LOAD_IA32_PAT;
5987 msrs->entry_ctls_high |=
5988 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
5990 /* We support free control of debug control loading. */
5991 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
5993 /* cpu-based controls */
5994 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
5995 msrs->procbased_ctls_low,
5996 msrs->procbased_ctls_high);
5997 msrs->procbased_ctls_low =
5998 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
5999 msrs->procbased_ctls_high &=
6000 CPU_BASED_INTR_WINDOW_EXITING |
6001 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING |
6002 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
6003 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
6004 CPU_BASED_CR3_STORE_EXITING |
6005 #ifdef CONFIG_X86_64
6006 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
6008 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
6009 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
6010 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
6011 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
6012 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
6014 * We can allow some features even when not supported by the
6015 * hardware. For example, L1 can specify an MSR bitmap - and we
6016 * can use it to avoid exits to L1 - even when L0 runs L2
6017 * without MSR bitmaps.
6019 msrs->procbased_ctls_high |=
6020 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
6021 CPU_BASED_USE_MSR_BITMAPS;
6023 /* We support free control of CR3 access interception. */
6024 msrs->procbased_ctls_low &=
6025 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
6028 * secondary cpu-based controls. Do not include those that
6029 * depend on CPUID bits, they are added later by vmx_cpuid_update.
6031 if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
6032 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
6033 msrs->secondary_ctls_low,
6034 msrs->secondary_ctls_high);
6036 msrs->secondary_ctls_low = 0;
6037 msrs->secondary_ctls_high &=
6038 SECONDARY_EXEC_DESC |
6039 SECONDARY_EXEC_RDTSCP |
6040 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6041 SECONDARY_EXEC_WBINVD_EXITING |
6042 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6043 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
6044 SECONDARY_EXEC_RDRAND_EXITING |
6045 SECONDARY_EXEC_ENABLE_INVPCID |
6046 SECONDARY_EXEC_RDSEED_EXITING |
6047 SECONDARY_EXEC_XSAVES;
6050 * We can emulate "VMCS shadowing," even if the hardware
6051 * doesn't support it.
6053 msrs->secondary_ctls_high |=
6054 SECONDARY_EXEC_SHADOW_VMCS;
6057 /* nested EPT: emulate EPT also to L1 */
6058 msrs->secondary_ctls_high |=
6059 SECONDARY_EXEC_ENABLE_EPT;
6060 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
6061 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
6062 if (cpu_has_vmx_ept_execute_only())
6064 VMX_EPT_EXECUTE_ONLY_BIT;
6065 msrs->ept_caps &= ept_caps;
6066 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
6067 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
6068 VMX_EPT_1GB_PAGE_BIT;
6069 if (enable_ept_ad_bits) {
6070 msrs->secondary_ctls_high |=
6071 SECONDARY_EXEC_ENABLE_PML;
6072 msrs->ept_caps |= VMX_EPT_AD_BIT;
6076 if (cpu_has_vmx_vmfunc()) {
6077 msrs->secondary_ctls_high |=
6078 SECONDARY_EXEC_ENABLE_VMFUNC;
6080 * Advertise EPTP switching unconditionally
6081 * since we emulate it
6084 msrs->vmfunc_controls =
6085 VMX_VMFUNC_EPTP_SWITCHING;
6089 * Old versions of KVM use the single-context version without
6090 * checking for support, so declare that it is supported even
6091 * though it is treated as global context. The alternative is
6092 * not failing the single-context invvpid, and it is worse.
6095 msrs->secondary_ctls_high |=
6096 SECONDARY_EXEC_ENABLE_VPID;
6097 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
6098 VMX_VPID_EXTENT_SUPPORTED_MASK;
6101 if (enable_unrestricted_guest)
6102 msrs->secondary_ctls_high |=
6103 SECONDARY_EXEC_UNRESTRICTED_GUEST;
6105 if (flexpriority_enabled)
6106 msrs->secondary_ctls_high |=
6107 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6109 /* miscellaneous data */
6110 rdmsr(MSR_IA32_VMX_MISC,
6113 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
6115 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
6116 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
6117 VMX_MISC_ACTIVITY_HLT;
6118 msrs->misc_high = 0;
6121 * This MSR reports some information about VMX support. We
6122 * should return information about the VMX we emulate for the
6123 * guest, and the VMCS structure we give it - not about the
6124 * VMX support of the underlying hardware.
6128 VMX_BASIC_TRUE_CTLS |
6129 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
6130 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
6132 if (cpu_has_vmx_basic_inout())
6133 msrs->basic |= VMX_BASIC_INOUT;
6136 * These MSRs specify bits which the guest must keep fixed on
6137 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
6138 * We picked the standard core2 setting.
6140 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
6141 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
6142 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
6143 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
6145 /* These MSRs specify bits which the guest must keep fixed off. */
6146 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
6147 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
6149 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
6150 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
6153 void nested_vmx_hardware_unsetup(void)
6157 if (enable_shadow_vmcs) {
6158 for (i = 0; i < VMX_BITMAP_NR; i++)
6159 free_page((unsigned long)vmx_bitmap[i]);
6163 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *))
6167 if (!cpu_has_vmx_shadow_vmcs())
6168 enable_shadow_vmcs = 0;
6169 if (enable_shadow_vmcs) {
6170 for (i = 0; i < VMX_BITMAP_NR; i++) {
6172 * The vmx_bitmap is not tied to a VM and so should
6173 * not be charged to a memcg.
6175 vmx_bitmap[i] = (unsigned long *)
6176 __get_free_page(GFP_KERNEL);
6177 if (!vmx_bitmap[i]) {
6178 nested_vmx_hardware_unsetup();
6183 init_vmcs_shadow_fields();
6186 exit_handlers[EXIT_REASON_VMCLEAR] = handle_vmclear;
6187 exit_handlers[EXIT_REASON_VMLAUNCH] = handle_vmlaunch;
6188 exit_handlers[EXIT_REASON_VMPTRLD] = handle_vmptrld;
6189 exit_handlers[EXIT_REASON_VMPTRST] = handle_vmptrst;
6190 exit_handlers[EXIT_REASON_VMREAD] = handle_vmread;
6191 exit_handlers[EXIT_REASON_VMRESUME] = handle_vmresume;
6192 exit_handlers[EXIT_REASON_VMWRITE] = handle_vmwrite;
6193 exit_handlers[EXIT_REASON_VMOFF] = handle_vmoff;
6194 exit_handlers[EXIT_REASON_VMON] = handle_vmon;
6195 exit_handlers[EXIT_REASON_INVEPT] = handle_invept;
6196 exit_handlers[EXIT_REASON_INVVPID] = handle_invvpid;
6197 exit_handlers[EXIT_REASON_VMFUNC] = handle_vmfunc;
6199 kvm_x86_ops->check_nested_events = vmx_check_nested_events;
6200 kvm_x86_ops->get_nested_state = vmx_get_nested_state;
6201 kvm_x86_ops->set_nested_state = vmx_set_nested_state;
6202 kvm_x86_ops->get_vmcs12_pages = nested_get_vmcs12_pages;
6203 kvm_x86_ops->nested_enable_evmcs = nested_enable_evmcs;
6204 kvm_x86_ops->nested_get_evmcs_version = nested_get_evmcs_version;