1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 static u64 __read_mostly host_xss;
111 bool __read_mostly enable_pml = 1;
112 module_param_named(pml, enable_pml, bool, S_IRUGO);
114 static bool __read_mostly dump_invalid_vmcs = 0;
115 module_param(dump_invalid_vmcs, bool, 0644);
117 #define MSR_BITMAP_MODE_X2APIC 1
118 #define MSR_BITMAP_MODE_X2APIC_APICV 2
120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123 static int __read_mostly cpu_preemption_timer_multi;
124 static bool __read_mostly enable_preemption_timer = 1;
126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131 #define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
134 #define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
227 /* If set to auto use the default l1tf mitigation method */
228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
229 switch (l1tf_mitigation) {
230 case L1TF_MITIGATION_OFF:
231 l1tf = VMENTER_L1D_FLUSH_NEVER;
233 case L1TF_MITIGATION_FLUSH_NOWARN:
234 case L1TF_MITIGATION_FLUSH:
235 case L1TF_MITIGATION_FLUSH_NOSMT:
236 l1tf = VMENTER_L1D_FLUSH_COND;
238 case L1TF_MITIGATION_FULL:
239 case L1TF_MITIGATION_FULL_FORCE:
240 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
244 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
250 * This allocation for vmx_l1d_flush_pages is not tied to a VM
251 * lifetime and so should not be charged to a memcg.
253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
256 vmx_l1d_flush_pages = page_address(page);
259 * Initialize each page with a different pattern in
260 * order to protect against KSM in the nested
261 * virtualization case.
263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
269 l1tf_vmx_mitigation = l1tf;
271 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
272 static_branch_enable(&vmx_l1d_should_flush);
274 static_branch_disable(&vmx_l1d_should_flush);
276 if (l1tf == VMENTER_L1D_FLUSH_COND)
277 static_branch_enable(&vmx_l1d_flush_cond);
279 static_branch_disable(&vmx_l1d_flush_cond);
283 static int vmentry_l1d_flush_parse(const char *s)
288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
289 if (vmentry_l1d_param[i].for_parse &&
290 sysfs_streq(s, vmentry_l1d_param[i].option))
297 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301 l1tf = vmentry_l1d_flush_parse(s);
305 if (!boot_cpu_has(X86_BUG_L1TF))
309 * Has vmx_init() run already? If not then this is the pre init
310 * parameter parsing. In that case just store the value and let
311 * vmx_init() do the proper setup after enable_ept has been
314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
315 vmentry_l1d_flush_param = l1tf;
319 mutex_lock(&vmx_l1d_flush_mutex);
320 ret = vmx_setup_l1d_flush(l1tf);
321 mutex_unlock(&vmx_l1d_flush_mutex);
325 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
328 return sprintf(s, "???\n");
330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
333 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
334 .set = vmentry_l1d_flush_set,
335 .get = vmentry_l1d_flush_get,
337 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
339 static bool guest_state_valid(struct kvm_vcpu *vcpu);
340 static u32 vmx_segment_access_rights(struct kvm_segment *var);
341 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
344 void vmx_vmexit(void);
346 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
347 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
352 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
356 * can find which vCPU should be waken up.
358 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
359 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
361 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
362 static DEFINE_SPINLOCK(vmx_vpid_lock);
364 struct vmcs_config vmcs_config;
365 struct vmx_capability vmx_capability;
367 #define VMX_SEGMENT_FIELD(seg) \
368 [VCPU_SREG_##seg] = { \
369 .selector = GUEST_##seg##_SELECTOR, \
370 .base = GUEST_##seg##_BASE, \
371 .limit = GUEST_##seg##_LIMIT, \
372 .ar_bytes = GUEST_##seg##_AR_BYTES, \
375 static const struct kvm_vmx_segment_field {
380 } kvm_vmx_segment_fields[] = {
381 VMX_SEGMENT_FIELD(CS),
382 VMX_SEGMENT_FIELD(DS),
383 VMX_SEGMENT_FIELD(ES),
384 VMX_SEGMENT_FIELD(FS),
385 VMX_SEGMENT_FIELD(GS),
386 VMX_SEGMENT_FIELD(SS),
387 VMX_SEGMENT_FIELD(TR),
388 VMX_SEGMENT_FIELD(LDTR),
392 static unsigned long host_idt_base;
395 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
396 * will emulate SYSCALL in legacy mode if the vendor string in guest
397 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
398 * support this emulation, IA32_STAR must always be included in
399 * vmx_msr_index[], even in i386 builds.
401 const u32 vmx_msr_index[] = {
403 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
405 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
408 #if IS_ENABLED(CONFIG_HYPERV)
409 static bool __read_mostly enlightened_vmcs = true;
410 module_param(enlightened_vmcs, bool, 0444);
412 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
413 static void check_ept_pointer_match(struct kvm *kvm)
415 struct kvm_vcpu *vcpu;
416 u64 tmp_eptp = INVALID_PAGE;
419 kvm_for_each_vcpu(i, vcpu, kvm) {
420 if (!VALID_PAGE(tmp_eptp)) {
421 tmp_eptp = to_vmx(vcpu)->ept_pointer;
422 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
423 to_kvm_vmx(kvm)->ept_pointers_match
424 = EPT_POINTERS_MISMATCH;
429 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
432 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
435 struct kvm_tlb_range *range = data;
437 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
441 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
442 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
444 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
447 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
448 * of the base of EPT PML4 table, strip off EPT configuration
452 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
453 kvm_fill_hv_flush_list_func, (void *)range);
455 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
458 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
459 struct kvm_tlb_range *range)
461 struct kvm_vcpu *vcpu;
464 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
466 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
467 check_ept_pointer_match(kvm);
469 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
470 kvm_for_each_vcpu(i, vcpu, kvm) {
471 /* If ept_pointer is invalid pointer, bypass flush request. */
472 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
473 ret |= __hv_remote_flush_tlb_with_range(
477 ret = __hv_remote_flush_tlb_with_range(kvm,
478 kvm_get_vcpu(kvm, 0), range);
481 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
484 static int hv_remote_flush_tlb(struct kvm *kvm)
486 return hv_remote_flush_tlb_with_range(kvm, NULL);
489 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
491 struct hv_enlightened_vmcs *evmcs;
492 struct hv_partition_assist_pg **p_hv_pa_pg =
493 &vcpu->kvm->arch.hyperv.hv_pa_pg;
495 * Synthetic VM-Exit is not enabled in current code and so All
496 * evmcs in singe VM shares same assist page.
499 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
502 pr_debug("KVM: Hyper-V: allocated PA_PG for %llx\n",
506 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
508 evmcs->partition_assist_page =
510 evmcs->hv_vm_id = (u64)vcpu->kvm;
511 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
513 pr_debug("KVM: Hyper-V: enabled DIRECT flush for %llx\n",
518 #endif /* IS_ENABLED(CONFIG_HYPERV) */
521 * Comment's format: document - errata name - stepping - processor name.
523 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
525 static u32 vmx_preemption_cpu_tfms[] = {
526 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
528 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
529 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
530 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
532 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
534 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
535 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
537 * 320767.pdf - AAP86 - B1 -
538 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
541 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
543 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
545 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
547 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
548 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
549 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
551 /* Xeon E3-1220 V2 */
555 static inline bool cpu_has_broken_vmx_preemption_timer(void)
557 u32 eax = cpuid_eax(0x00000001), i;
559 /* Clear the reserved bits */
560 eax &= ~(0x3U << 14 | 0xfU << 28);
561 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
562 if (eax == vmx_preemption_cpu_tfms[i])
568 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
570 return flexpriority_enabled && lapic_in_kernel(vcpu);
573 static inline bool report_flexpriority(void)
575 return flexpriority_enabled;
578 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
582 for (i = 0; i < vmx->nmsrs; ++i)
583 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
588 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
592 i = __find_msr_index(vmx, msr);
594 return &vmx->guest_msrs[i];
598 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
600 vmcs_clear(loaded_vmcs->vmcs);
601 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
602 vmcs_clear(loaded_vmcs->shadow_vmcs);
603 loaded_vmcs->cpu = -1;
604 loaded_vmcs->launched = 0;
607 #ifdef CONFIG_KEXEC_CORE
609 * This bitmap is used to indicate whether the vmclear
610 * operation is enabled on all cpus. All disabled by
613 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
615 static inline void crash_enable_local_vmclear(int cpu)
617 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
620 static inline void crash_disable_local_vmclear(int cpu)
622 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
625 static inline int crash_local_vmclear_enabled(int cpu)
627 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
630 static void crash_vmclear_local_loaded_vmcss(void)
632 int cpu = raw_smp_processor_id();
633 struct loaded_vmcs *v;
635 if (!crash_local_vmclear_enabled(cpu))
638 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
639 loaded_vmcss_on_cpu_link)
643 static inline void crash_enable_local_vmclear(int cpu) { }
644 static inline void crash_disable_local_vmclear(int cpu) { }
645 #endif /* CONFIG_KEXEC_CORE */
647 static void __loaded_vmcs_clear(void *arg)
649 struct loaded_vmcs *loaded_vmcs = arg;
650 int cpu = raw_smp_processor_id();
652 if (loaded_vmcs->cpu != cpu)
653 return; /* vcpu migration can race with cpu offline */
654 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
655 per_cpu(current_vmcs, cpu) = NULL;
656 crash_disable_local_vmclear(cpu);
657 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
660 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
661 * is before setting loaded_vmcs->vcpu to -1 which is done in
662 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
663 * then adds the vmcs into percpu list before it is deleted.
667 loaded_vmcs_init(loaded_vmcs);
668 crash_enable_local_vmclear(cpu);
671 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
673 int cpu = loaded_vmcs->cpu;
676 smp_call_function_single(cpu,
677 __loaded_vmcs_clear, loaded_vmcs, 1);
680 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
684 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
686 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
687 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
688 vmx->segment_cache.bitmask = 0;
690 ret = vmx->segment_cache.bitmask & mask;
691 vmx->segment_cache.bitmask |= mask;
695 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
697 u16 *p = &vmx->segment_cache.seg[seg].selector;
699 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
700 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
704 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
706 ulong *p = &vmx->segment_cache.seg[seg].base;
708 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
709 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
713 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
715 u32 *p = &vmx->segment_cache.seg[seg].limit;
717 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
718 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
722 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
724 u32 *p = &vmx->segment_cache.seg[seg].ar;
726 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
727 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
731 void update_exception_bitmap(struct kvm_vcpu *vcpu)
735 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
736 (1u << DB_VECTOR) | (1u << AC_VECTOR);
738 * Guest access to VMware backdoor ports could legitimately
739 * trigger #GP because of TSS I/O permission bitmap.
740 * We intercept those #GP and allow access to them anyway
743 if (enable_vmware_backdoor)
744 eb |= (1u << GP_VECTOR);
745 if ((vcpu->guest_debug &
746 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
747 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
748 eb |= 1u << BP_VECTOR;
749 if (to_vmx(vcpu)->rmode.vm86_active)
752 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
754 /* When we are running a nested L2 guest and L1 specified for it a
755 * certain exception bitmap, we must trap the same exceptions and pass
756 * them to L1. When running L2, we will only handle the exceptions
757 * specified above if L1 did not want them.
759 if (is_guest_mode(vcpu))
760 eb |= get_vmcs12(vcpu)->exception_bitmap;
762 vmcs_write32(EXCEPTION_BITMAP, eb);
766 * Check if MSR is intercepted for currently loaded MSR bitmap.
768 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
770 unsigned long *msr_bitmap;
771 int f = sizeof(unsigned long);
773 if (!cpu_has_vmx_msr_bitmap())
776 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
779 return !!test_bit(msr, msr_bitmap + 0x800 / f);
780 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
782 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
788 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
789 unsigned long entry, unsigned long exit)
791 vm_entry_controls_clearbit(vmx, entry);
792 vm_exit_controls_clearbit(vmx, exit);
795 static int find_msr(struct vmx_msrs *m, unsigned int msr)
799 for (i = 0; i < m->nr; ++i) {
800 if (m->val[i].index == msr)
806 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
809 struct msr_autoload *m = &vmx->msr_autoload;
813 if (cpu_has_load_ia32_efer()) {
814 clear_atomic_switch_msr_special(vmx,
815 VM_ENTRY_LOAD_IA32_EFER,
816 VM_EXIT_LOAD_IA32_EFER);
820 case MSR_CORE_PERF_GLOBAL_CTRL:
821 if (cpu_has_load_perf_global_ctrl()) {
822 clear_atomic_switch_msr_special(vmx,
823 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
824 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
829 i = find_msr(&m->guest, msr);
833 m->guest.val[i] = m->guest.val[m->guest.nr];
834 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
837 i = find_msr(&m->host, msr);
842 m->host.val[i] = m->host.val[m->host.nr];
843 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
846 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
847 unsigned long entry, unsigned long exit,
848 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
849 u64 guest_val, u64 host_val)
851 vmcs_write64(guest_val_vmcs, guest_val);
852 if (host_val_vmcs != HOST_IA32_EFER)
853 vmcs_write64(host_val_vmcs, host_val);
854 vm_entry_controls_setbit(vmx, entry);
855 vm_exit_controls_setbit(vmx, exit);
858 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
859 u64 guest_val, u64 host_val, bool entry_only)
862 struct msr_autoload *m = &vmx->msr_autoload;
866 if (cpu_has_load_ia32_efer()) {
867 add_atomic_switch_msr_special(vmx,
868 VM_ENTRY_LOAD_IA32_EFER,
869 VM_EXIT_LOAD_IA32_EFER,
872 guest_val, host_val);
876 case MSR_CORE_PERF_GLOBAL_CTRL:
877 if (cpu_has_load_perf_global_ctrl()) {
878 add_atomic_switch_msr_special(vmx,
879 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
880 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
881 GUEST_IA32_PERF_GLOBAL_CTRL,
882 HOST_IA32_PERF_GLOBAL_CTRL,
883 guest_val, host_val);
887 case MSR_IA32_PEBS_ENABLE:
888 /* PEBS needs a quiescent period after being disabled (to write
889 * a record). Disabling PEBS through VMX MSR swapping doesn't
890 * provide that period, so a CPU could write host's record into
893 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
896 i = find_msr(&m->guest, msr);
898 j = find_msr(&m->host, msr);
900 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
901 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
902 printk_once(KERN_WARNING "Not enough msr switch entries. "
903 "Can't add msr %x\n", msr);
908 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
910 m->guest.val[i].index = msr;
911 m->guest.val[i].value = guest_val;
918 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
920 m->host.val[j].index = msr;
921 m->host.val[j].value = host_val;
924 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
926 u64 guest_efer = vmx->vcpu.arch.efer;
931 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
932 * host CPUID is more efficient than testing guest CPUID
933 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
935 if (boot_cpu_has(X86_FEATURE_SMEP))
936 guest_efer |= EFER_NX;
937 else if (!(guest_efer & EFER_NX))
938 ignore_bits |= EFER_NX;
942 * LMA and LME handled by hardware; SCE meaningless outside long mode.
944 ignore_bits |= EFER_SCE;
946 ignore_bits |= EFER_LMA | EFER_LME;
947 /* SCE is meaningful only in long mode on Intel */
948 if (guest_efer & EFER_LMA)
949 ignore_bits &= ~(u64)EFER_SCE;
953 * On EPT, we can't emulate NX, so we must switch EFER atomically.
954 * On CPUs that support "load IA32_EFER", always switch EFER
955 * atomically, since it's faster than switching it manually.
957 if (cpu_has_load_ia32_efer() ||
958 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
959 if (!(guest_efer & EFER_LMA))
960 guest_efer &= ~EFER_LME;
961 if (guest_efer != host_efer)
962 add_atomic_switch_msr(vmx, MSR_EFER,
963 guest_efer, host_efer, false);
965 clear_atomic_switch_msr(vmx, MSR_EFER);
968 clear_atomic_switch_msr(vmx, MSR_EFER);
970 guest_efer &= ~ignore_bits;
971 guest_efer |= host_efer & ignore_bits;
973 vmx->guest_msrs[efer_offset].data = guest_efer;
974 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
982 * On 32-bit kernels, VM exits still load the FS and GS bases from the
983 * VMCS rather than the segment table. KVM uses this helper to figure
984 * out the current bases to poke them into the VMCS before entry.
986 static unsigned long segment_base(u16 selector)
988 struct desc_struct *table;
991 if (!(selector & ~SEGMENT_RPL_MASK))
994 table = get_current_gdt_ro();
996 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
997 u16 ldt_selector = kvm_read_ldt();
999 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1002 table = (struct desc_struct *)segment_base(ldt_selector);
1004 v = get_desc_base(&table[selector >> 3]);
1009 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1013 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1014 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1015 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1016 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1017 for (i = 0; i < addr_range; i++) {
1018 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1019 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1023 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1027 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1028 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1029 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1030 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1031 for (i = 0; i < addr_range; i++) {
1032 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1033 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1037 static void pt_guest_enter(struct vcpu_vmx *vmx)
1039 if (pt_mode == PT_MODE_SYSTEM)
1043 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1044 * Save host state before VM entry.
1046 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1047 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1048 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1049 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1050 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1054 static void pt_guest_exit(struct vcpu_vmx *vmx)
1056 if (pt_mode == PT_MODE_SYSTEM)
1059 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1060 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1061 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1064 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1065 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1068 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1069 unsigned long fs_base, unsigned long gs_base)
1071 if (unlikely(fs_sel != host->fs_sel)) {
1073 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1075 vmcs_write16(HOST_FS_SELECTOR, 0);
1076 host->fs_sel = fs_sel;
1078 if (unlikely(gs_sel != host->gs_sel)) {
1080 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1082 vmcs_write16(HOST_GS_SELECTOR, 0);
1083 host->gs_sel = gs_sel;
1085 if (unlikely(fs_base != host->fs_base)) {
1086 vmcs_writel(HOST_FS_BASE, fs_base);
1087 host->fs_base = fs_base;
1089 if (unlikely(gs_base != host->gs_base)) {
1090 vmcs_writel(HOST_GS_BASE, gs_base);
1091 host->gs_base = gs_base;
1095 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1097 struct vcpu_vmx *vmx = to_vmx(vcpu);
1098 struct vmcs_host_state *host_state;
1099 #ifdef CONFIG_X86_64
1100 int cpu = raw_smp_processor_id();
1102 unsigned long fs_base, gs_base;
1106 vmx->req_immediate_exit = false;
1109 * Note that guest MSRs to be saved/restored can also be changed
1110 * when guest state is loaded. This happens when guest transitions
1111 * to/from long-mode by setting MSR_EFER.LMA.
1113 if (!vmx->guest_msrs_ready) {
1114 vmx->guest_msrs_ready = true;
1115 for (i = 0; i < vmx->save_nmsrs; ++i)
1116 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1117 vmx->guest_msrs[i].data,
1118 vmx->guest_msrs[i].mask);
1121 if (vmx->guest_state_loaded)
1124 host_state = &vmx->loaded_vmcs->host_state;
1127 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1128 * allow segment selectors with cpl > 0 or ti == 1.
1130 host_state->ldt_sel = kvm_read_ldt();
1132 #ifdef CONFIG_X86_64
1133 savesegment(ds, host_state->ds_sel);
1134 savesegment(es, host_state->es_sel);
1136 gs_base = cpu_kernelmode_gs_base(cpu);
1137 if (likely(is_64bit_mm(current->mm))) {
1138 save_fsgs_for_kvm();
1139 fs_sel = current->thread.fsindex;
1140 gs_sel = current->thread.gsindex;
1141 fs_base = current->thread.fsbase;
1142 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1144 savesegment(fs, fs_sel);
1145 savesegment(gs, gs_sel);
1146 fs_base = read_msr(MSR_FS_BASE);
1147 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1150 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1152 savesegment(fs, fs_sel);
1153 savesegment(gs, gs_sel);
1154 fs_base = segment_base(fs_sel);
1155 gs_base = segment_base(gs_sel);
1158 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1159 vmx->guest_state_loaded = true;
1162 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1164 struct vmcs_host_state *host_state;
1166 if (!vmx->guest_state_loaded)
1169 host_state = &vmx->loaded_vmcs->host_state;
1171 ++vmx->vcpu.stat.host_state_reload;
1173 #ifdef CONFIG_X86_64
1174 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1176 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1177 kvm_load_ldt(host_state->ldt_sel);
1178 #ifdef CONFIG_X86_64
1179 load_gs_index(host_state->gs_sel);
1181 loadsegment(gs, host_state->gs_sel);
1184 if (host_state->fs_sel & 7)
1185 loadsegment(fs, host_state->fs_sel);
1186 #ifdef CONFIG_X86_64
1187 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1188 loadsegment(ds, host_state->ds_sel);
1189 loadsegment(es, host_state->es_sel);
1192 invalidate_tss_limit();
1193 #ifdef CONFIG_X86_64
1194 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1196 load_fixmap_gdt(raw_smp_processor_id());
1197 vmx->guest_state_loaded = false;
1198 vmx->guest_msrs_ready = false;
1201 #ifdef CONFIG_X86_64
1202 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1205 if (vmx->guest_state_loaded)
1206 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1208 return vmx->msr_guest_kernel_gs_base;
1211 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1214 if (vmx->guest_state_loaded)
1215 wrmsrl(MSR_KERNEL_GS_BASE, data);
1217 vmx->msr_guest_kernel_gs_base = data;
1221 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1223 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1224 struct pi_desc old, new;
1228 * In case of hot-plug or hot-unplug, we may have to undo
1229 * vmx_vcpu_pi_put even if there is no assigned device. And we
1230 * always keep PI.NDST up to date for simplicity: it makes the
1231 * code easier, and CPU migration is not a fast path.
1233 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1236 /* The full case. */
1238 old.control = new.control = pi_desc->control;
1240 dest = cpu_physical_id(cpu);
1242 if (x2apic_enabled())
1245 new.ndst = (dest << 8) & 0xFF00;
1248 } while (cmpxchg64(&pi_desc->control, old.control,
1249 new.control) != old.control);
1252 * Clear SN before reading the bitmap. The VT-d firmware
1253 * writes the bitmap and reads SN atomically (5.2.3 in the
1254 * spec), so it doesn't really have a memory barrier that
1255 * pairs with this, but we cannot do that and we need one.
1257 smp_mb__after_atomic();
1259 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1263 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1265 struct vcpu_vmx *vmx = to_vmx(vcpu);
1266 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1268 if (!already_loaded) {
1269 loaded_vmcs_clear(vmx->loaded_vmcs);
1270 local_irq_disable();
1271 crash_disable_local_vmclear(cpu);
1274 * Read loaded_vmcs->cpu should be before fetching
1275 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1276 * See the comments in __loaded_vmcs_clear().
1280 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1281 &per_cpu(loaded_vmcss_on_cpu, cpu));
1282 crash_enable_local_vmclear(cpu);
1286 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1287 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1288 vmcs_load(vmx->loaded_vmcs->vmcs);
1289 indirect_branch_prediction_barrier();
1292 if (!already_loaded) {
1293 void *gdt = get_current_gdt_ro();
1294 unsigned long sysenter_esp;
1296 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1299 * Linux uses per-cpu TSS and GDT, so set these when switching
1300 * processors. See 22.2.4.
1302 vmcs_writel(HOST_TR_BASE,
1303 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1304 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1307 * VM exits change the host TR limit to 0x67 after a VM
1308 * exit. This is okay, since 0x67 covers everything except
1309 * the IO bitmap and have have code to handle the IO bitmap
1310 * being lost after a VM exit.
1312 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1314 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1315 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1317 vmx->loaded_vmcs->cpu = cpu;
1320 /* Setup TSC multiplier */
1321 if (kvm_has_tsc_control &&
1322 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1323 decache_tsc_multiplier(vmx);
1327 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1328 * vcpu mutex is already taken.
1330 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1332 struct vcpu_vmx *vmx = to_vmx(vcpu);
1334 vmx_vcpu_load_vmcs(vcpu, cpu);
1336 vmx_vcpu_pi_load(vcpu, cpu);
1338 vmx->host_pkru = read_pkru();
1339 vmx->host_debugctlmsr = get_debugctlmsr();
1342 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1344 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1346 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1347 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1348 !kvm_vcpu_apicv_active(vcpu))
1351 /* Set SN when the vCPU is preempted */
1352 if (vcpu->preempted)
1356 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1358 vmx_vcpu_pi_put(vcpu);
1360 vmx_prepare_switch_to_host(to_vmx(vcpu));
1363 static bool emulation_required(struct kvm_vcpu *vcpu)
1365 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1368 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1370 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1372 unsigned long rflags, save_rflags;
1374 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1375 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1376 rflags = vmcs_readl(GUEST_RFLAGS);
1377 if (to_vmx(vcpu)->rmode.vm86_active) {
1378 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1379 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1380 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1382 to_vmx(vcpu)->rflags = rflags;
1384 return to_vmx(vcpu)->rflags;
1387 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1389 unsigned long old_rflags = vmx_get_rflags(vcpu);
1391 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1392 to_vmx(vcpu)->rflags = rflags;
1393 if (to_vmx(vcpu)->rmode.vm86_active) {
1394 to_vmx(vcpu)->rmode.save_rflags = rflags;
1395 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1397 vmcs_writel(GUEST_RFLAGS, rflags);
1399 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1400 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1403 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1405 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1408 if (interruptibility & GUEST_INTR_STATE_STI)
1409 ret |= KVM_X86_SHADOW_INT_STI;
1410 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1411 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1416 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1418 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1419 u32 interruptibility = interruptibility_old;
1421 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1423 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1424 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1425 else if (mask & KVM_X86_SHADOW_INT_STI)
1426 interruptibility |= GUEST_INTR_STATE_STI;
1428 if ((interruptibility != interruptibility_old))
1429 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1432 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1434 struct vcpu_vmx *vmx = to_vmx(vcpu);
1435 unsigned long value;
1438 * Any MSR write that attempts to change bits marked reserved will
1441 if (data & vmx->pt_desc.ctl_bitmask)
1445 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1446 * result in a #GP unless the same write also clears TraceEn.
1448 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1449 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1453 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1454 * and FabricEn would cause #GP, if
1455 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1457 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1458 !(data & RTIT_CTL_FABRIC_EN) &&
1459 !intel_pt_validate_cap(vmx->pt_desc.caps,
1460 PT_CAP_single_range_output))
1464 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1465 * utilize encodings marked reserved will casue a #GP fault.
1467 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1468 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1469 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1470 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1472 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1473 PT_CAP_cycle_thresholds);
1474 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1475 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1476 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1478 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1479 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1480 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1481 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1485 * If ADDRx_CFG is reserved or the encodings is >2 will
1486 * cause a #GP fault.
1488 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1489 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1491 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1492 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1494 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1495 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1497 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1498 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1504 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1509 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1510 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1511 * set when EPT misconfig occurs. In practice, real hardware updates
1512 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1513 * (namely Hyper-V) don't set it due to it being undefined behavior,
1514 * i.e. we end up advancing IP with some random value.
1516 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1517 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1518 rip = kvm_rip_read(vcpu);
1519 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1520 kvm_rip_write(vcpu, rip);
1522 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1526 /* skipping an emulated instruction also counts */
1527 vmx_set_interrupt_shadow(vcpu, 0);
1532 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1535 * Ensure that we clear the HLT state in the VMCS. We don't need to
1536 * explicitly skip the instruction because if the HLT state is set,
1537 * then the instruction is already executing and RIP has already been
1540 if (kvm_hlt_in_guest(vcpu->kvm) &&
1541 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1542 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1545 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1547 struct vcpu_vmx *vmx = to_vmx(vcpu);
1548 unsigned nr = vcpu->arch.exception.nr;
1549 bool has_error_code = vcpu->arch.exception.has_error_code;
1550 u32 error_code = vcpu->arch.exception.error_code;
1551 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1553 kvm_deliver_exception_payload(vcpu);
1555 if (has_error_code) {
1556 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1557 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1560 if (vmx->rmode.vm86_active) {
1562 if (kvm_exception_is_soft(nr))
1563 inc_eip = vcpu->arch.event_exit_inst_len;
1564 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1568 WARN_ON_ONCE(vmx->emulation_required);
1570 if (kvm_exception_is_soft(nr)) {
1571 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1572 vmx->vcpu.arch.event_exit_inst_len);
1573 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1575 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1577 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1579 vmx_clear_hlt(vcpu);
1582 static bool vmx_rdtscp_supported(void)
1584 return cpu_has_vmx_rdtscp();
1587 static bool vmx_invpcid_supported(void)
1589 return cpu_has_vmx_invpcid();
1593 * Swap MSR entry in host/guest MSR entry array.
1595 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1597 struct shared_msr_entry tmp;
1599 tmp = vmx->guest_msrs[to];
1600 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1601 vmx->guest_msrs[from] = tmp;
1605 * Set up the vmcs to automatically save and restore system
1606 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1607 * mode, as fiddling with msrs is very expensive.
1609 static void setup_msrs(struct vcpu_vmx *vmx)
1611 int save_nmsrs, index;
1614 #ifdef CONFIG_X86_64
1616 * The SYSCALL MSRs are only needed on long mode guests, and only
1617 * when EFER.SCE is set.
1619 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1620 index = __find_msr_index(vmx, MSR_STAR);
1622 move_msr_up(vmx, index, save_nmsrs++);
1623 index = __find_msr_index(vmx, MSR_LSTAR);
1625 move_msr_up(vmx, index, save_nmsrs++);
1626 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1628 move_msr_up(vmx, index, save_nmsrs++);
1631 index = __find_msr_index(vmx, MSR_EFER);
1632 if (index >= 0 && update_transition_efer(vmx, index))
1633 move_msr_up(vmx, index, save_nmsrs++);
1634 index = __find_msr_index(vmx, MSR_TSC_AUX);
1635 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1636 move_msr_up(vmx, index, save_nmsrs++);
1638 vmx->save_nmsrs = save_nmsrs;
1639 vmx->guest_msrs_ready = false;
1641 if (cpu_has_vmx_msr_bitmap())
1642 vmx_update_msr_bitmap(&vmx->vcpu);
1645 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1647 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1649 if (is_guest_mode(vcpu) &&
1650 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1651 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1653 return vcpu->arch.tsc_offset;
1656 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1658 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1659 u64 g_tsc_offset = 0;
1662 * We're here if L1 chose not to trap WRMSR to TSC. According
1663 * to the spec, this should set L1's TSC; The offset that L1
1664 * set for L2 remains unchanged, and still needs to be added
1665 * to the newly set TSC to get L2's TSC.
1667 if (is_guest_mode(vcpu) &&
1668 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1669 g_tsc_offset = vmcs12->tsc_offset;
1671 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1672 vcpu->arch.tsc_offset - g_tsc_offset,
1674 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1675 return offset + g_tsc_offset;
1679 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1680 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1681 * all guests if the "nested" module option is off, and can also be disabled
1682 * for a single guest by disabling its VMX cpuid bit.
1684 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1686 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1689 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1692 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1694 return !(val & ~valid_bits);
1697 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1699 switch (msr->index) {
1700 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1703 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1712 * Reads an msr value (of 'msr_index') into 'pdata'.
1713 * Returns 0 on success, non-0 otherwise.
1714 * Assumes vcpu_load() was already called.
1716 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1718 struct vcpu_vmx *vmx = to_vmx(vcpu);
1719 struct shared_msr_entry *msr;
1722 switch (msr_info->index) {
1723 #ifdef CONFIG_X86_64
1725 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1728 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1730 case MSR_KERNEL_GS_BASE:
1731 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1735 return kvm_get_msr_common(vcpu, msr_info);
1736 case MSR_IA32_UMWAIT_CONTROL:
1737 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1740 msr_info->data = vmx->msr_ia32_umwait_control;
1742 case MSR_IA32_SPEC_CTRL:
1743 if (!msr_info->host_initiated &&
1744 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1747 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1749 case MSR_IA32_SYSENTER_CS:
1750 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1752 case MSR_IA32_SYSENTER_EIP:
1753 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1755 case MSR_IA32_SYSENTER_ESP:
1756 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1758 case MSR_IA32_BNDCFGS:
1759 if (!kvm_mpx_supported() ||
1760 (!msr_info->host_initiated &&
1761 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1763 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1765 case MSR_IA32_MCG_EXT_CTL:
1766 if (!msr_info->host_initiated &&
1767 !(vmx->msr_ia32_feature_control &
1768 FEATURE_CONTROL_LMCE))
1770 msr_info->data = vcpu->arch.mcg_ext_ctl;
1772 case MSR_IA32_FEATURE_CONTROL:
1773 msr_info->data = vmx->msr_ia32_feature_control;
1775 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1776 if (!nested_vmx_allowed(vcpu))
1778 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1781 if (!vmx_xsaves_supported() ||
1782 (!msr_info->host_initiated &&
1783 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1784 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1786 msr_info->data = vcpu->arch.ia32_xss;
1788 case MSR_IA32_RTIT_CTL:
1789 if (pt_mode != PT_MODE_HOST_GUEST)
1791 msr_info->data = vmx->pt_desc.guest.ctl;
1793 case MSR_IA32_RTIT_STATUS:
1794 if (pt_mode != PT_MODE_HOST_GUEST)
1796 msr_info->data = vmx->pt_desc.guest.status;
1798 case MSR_IA32_RTIT_CR3_MATCH:
1799 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1800 !intel_pt_validate_cap(vmx->pt_desc.caps,
1801 PT_CAP_cr3_filtering))
1803 msr_info->data = vmx->pt_desc.guest.cr3_match;
1805 case MSR_IA32_RTIT_OUTPUT_BASE:
1806 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1807 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1808 PT_CAP_topa_output) &&
1809 !intel_pt_validate_cap(vmx->pt_desc.caps,
1810 PT_CAP_single_range_output)))
1812 msr_info->data = vmx->pt_desc.guest.output_base;
1814 case MSR_IA32_RTIT_OUTPUT_MASK:
1815 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1816 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1817 PT_CAP_topa_output) &&
1818 !intel_pt_validate_cap(vmx->pt_desc.caps,
1819 PT_CAP_single_range_output)))
1821 msr_info->data = vmx->pt_desc.guest.output_mask;
1823 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1824 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1825 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1826 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1827 PT_CAP_num_address_ranges)))
1830 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1832 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1835 if (!msr_info->host_initiated &&
1836 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1838 /* Else, falls through */
1840 msr = find_msr_entry(vmx, msr_info->index);
1842 msr_info->data = msr->data;
1845 return kvm_get_msr_common(vcpu, msr_info);
1852 * Writes msr value into into the appropriate "register".
1853 * Returns 0 on success, non-0 otherwise.
1854 * Assumes vcpu_load() was already called.
1856 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1858 struct vcpu_vmx *vmx = to_vmx(vcpu);
1859 struct shared_msr_entry *msr;
1861 u32 msr_index = msr_info->index;
1862 u64 data = msr_info->data;
1865 switch (msr_index) {
1867 ret = kvm_set_msr_common(vcpu, msr_info);
1869 #ifdef CONFIG_X86_64
1871 vmx_segment_cache_clear(vmx);
1872 vmcs_writel(GUEST_FS_BASE, data);
1875 vmx_segment_cache_clear(vmx);
1876 vmcs_writel(GUEST_GS_BASE, data);
1878 case MSR_KERNEL_GS_BASE:
1879 vmx_write_guest_kernel_gs_base(vmx, data);
1882 case MSR_IA32_SYSENTER_CS:
1883 if (is_guest_mode(vcpu))
1884 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1885 vmcs_write32(GUEST_SYSENTER_CS, data);
1887 case MSR_IA32_SYSENTER_EIP:
1888 if (is_guest_mode(vcpu))
1889 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1890 vmcs_writel(GUEST_SYSENTER_EIP, data);
1892 case MSR_IA32_SYSENTER_ESP:
1893 if (is_guest_mode(vcpu))
1894 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1895 vmcs_writel(GUEST_SYSENTER_ESP, data);
1897 case MSR_IA32_DEBUGCTLMSR:
1898 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1899 VM_EXIT_SAVE_DEBUG_CONTROLS)
1900 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1902 ret = kvm_set_msr_common(vcpu, msr_info);
1905 case MSR_IA32_BNDCFGS:
1906 if (!kvm_mpx_supported() ||
1907 (!msr_info->host_initiated &&
1908 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1910 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1911 (data & MSR_IA32_BNDCFGS_RSVD))
1913 vmcs_write64(GUEST_BNDCFGS, data);
1915 case MSR_IA32_UMWAIT_CONTROL:
1916 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1919 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
1920 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
1923 vmx->msr_ia32_umwait_control = data;
1925 case MSR_IA32_SPEC_CTRL:
1926 if (!msr_info->host_initiated &&
1927 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1930 /* The STIBP bit doesn't fault even if it's not advertised */
1931 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1934 vmx->spec_ctrl = data;
1941 * When it's written (to non-zero) for the first time, pass
1945 * The handling of the MSR bitmap for L2 guests is done in
1946 * nested_vmx_merge_msr_bitmap. We should not touch the
1947 * vmcs02.msr_bitmap here since it gets completely overwritten
1948 * in the merging. We update the vmcs01 here for L1 as well
1949 * since it will end up touching the MSR anyway now.
1951 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1955 case MSR_IA32_PRED_CMD:
1956 if (!msr_info->host_initiated &&
1957 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1960 if (data & ~PRED_CMD_IBPB)
1966 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1970 * When it's written (to non-zero) for the first time, pass
1974 * The handling of the MSR bitmap for L2 guests is done in
1975 * nested_vmx_merge_msr_bitmap. We should not touch the
1976 * vmcs02.msr_bitmap here since it gets completely overwritten
1979 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1982 case MSR_IA32_CR_PAT:
1983 if (!kvm_pat_valid(data))
1986 if (is_guest_mode(vcpu) &&
1987 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
1988 get_vmcs12(vcpu)->guest_ia32_pat = data;
1990 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1991 vmcs_write64(GUEST_IA32_PAT, data);
1992 vcpu->arch.pat = data;
1995 ret = kvm_set_msr_common(vcpu, msr_info);
1997 case MSR_IA32_TSC_ADJUST:
1998 ret = kvm_set_msr_common(vcpu, msr_info);
2000 case MSR_IA32_MCG_EXT_CTL:
2001 if ((!msr_info->host_initiated &&
2002 !(to_vmx(vcpu)->msr_ia32_feature_control &
2003 FEATURE_CONTROL_LMCE)) ||
2004 (data & ~MCG_EXT_CTL_LMCE_EN))
2006 vcpu->arch.mcg_ext_ctl = data;
2008 case MSR_IA32_FEATURE_CONTROL:
2009 if (!vmx_feature_control_msr_valid(vcpu, data) ||
2010 (to_vmx(vcpu)->msr_ia32_feature_control &
2011 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2013 vmx->msr_ia32_feature_control = data;
2014 if (msr_info->host_initiated && data == 0)
2015 vmx_leave_nested(vcpu);
2017 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2018 if (!msr_info->host_initiated)
2019 return 1; /* they are read-only */
2020 if (!nested_vmx_allowed(vcpu))
2022 return vmx_set_vmx_msr(vcpu, msr_index, data);
2024 if (!vmx_xsaves_supported() ||
2025 (!msr_info->host_initiated &&
2026 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2027 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
2030 * The only supported bit as of Skylake is bit 8, but
2031 * it is not supported on KVM.
2035 vcpu->arch.ia32_xss = data;
2036 if (vcpu->arch.ia32_xss != host_xss)
2037 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2038 vcpu->arch.ia32_xss, host_xss, false);
2040 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2042 case MSR_IA32_RTIT_CTL:
2043 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2044 vmx_rtit_ctl_check(vcpu, data) ||
2047 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2048 vmx->pt_desc.guest.ctl = data;
2049 pt_update_intercept_for_msr(vmx);
2051 case MSR_IA32_RTIT_STATUS:
2052 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2053 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2054 (data & MSR_IA32_RTIT_STATUS_MASK))
2056 vmx->pt_desc.guest.status = data;
2058 case MSR_IA32_RTIT_CR3_MATCH:
2059 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2060 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2061 !intel_pt_validate_cap(vmx->pt_desc.caps,
2062 PT_CAP_cr3_filtering))
2064 vmx->pt_desc.guest.cr3_match = data;
2066 case MSR_IA32_RTIT_OUTPUT_BASE:
2067 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2068 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2069 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2070 PT_CAP_topa_output) &&
2071 !intel_pt_validate_cap(vmx->pt_desc.caps,
2072 PT_CAP_single_range_output)) ||
2073 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2075 vmx->pt_desc.guest.output_base = data;
2077 case MSR_IA32_RTIT_OUTPUT_MASK:
2078 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2079 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2080 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2081 PT_CAP_topa_output) &&
2082 !intel_pt_validate_cap(vmx->pt_desc.caps,
2083 PT_CAP_single_range_output)))
2085 vmx->pt_desc.guest.output_mask = data;
2087 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2088 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2089 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2090 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2091 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2092 PT_CAP_num_address_ranges)))
2095 vmx->pt_desc.guest.addr_b[index / 2] = data;
2097 vmx->pt_desc.guest.addr_a[index / 2] = data;
2100 if (!msr_info->host_initiated &&
2101 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2103 /* Check reserved bit, higher 32 bits should be zero */
2104 if ((data >> 32) != 0)
2106 /* Else, falls through */
2108 msr = find_msr_entry(vmx, msr_index);
2110 u64 old_msr_data = msr->data;
2112 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2114 ret = kvm_set_shared_msr(msr->index, msr->data,
2118 msr->data = old_msr_data;
2122 ret = kvm_set_msr_common(vcpu, msr_info);
2128 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2130 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2133 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2136 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2138 case VCPU_EXREG_PDPTR:
2140 ept_save_pdptrs(vcpu);
2147 static __init int cpu_has_kvm_support(void)
2149 return cpu_has_vmx();
2152 static __init int vmx_disabled_by_bios(void)
2156 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2157 if (msr & FEATURE_CONTROL_LOCKED) {
2158 /* launched w/ TXT and VMX disabled */
2159 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2162 /* launched w/o TXT and VMX only enabled w/ TXT */
2163 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2164 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2165 && !tboot_enabled()) {
2166 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2167 "activate TXT before enabling KVM\n");
2170 /* launched w/o TXT and VMX disabled */
2171 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2172 && !tboot_enabled())
2179 static void kvm_cpu_vmxon(u64 addr)
2181 cr4_set_bits(X86_CR4_VMXE);
2182 intel_pt_handle_vmx(1);
2184 asm volatile ("vmxon %0" : : "m"(addr));
2187 static int hardware_enable(void)
2189 int cpu = raw_smp_processor_id();
2190 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2193 if (cr4_read_shadow() & X86_CR4_VMXE)
2197 * This can happen if we hot-added a CPU but failed to allocate
2198 * VP assist page for it.
2200 if (static_branch_unlikely(&enable_evmcs) &&
2201 !hv_get_vp_assist_page(cpu))
2204 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2205 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2206 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2209 * Now we can enable the vmclear operation in kdump
2210 * since the loaded_vmcss_on_cpu list on this cpu
2211 * has been initialized.
2213 * Though the cpu is not in VMX operation now, there
2214 * is no problem to enable the vmclear operation
2215 * for the loaded_vmcss_on_cpu list is empty!
2217 crash_enable_local_vmclear(cpu);
2219 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2221 test_bits = FEATURE_CONTROL_LOCKED;
2222 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2223 if (tboot_enabled())
2224 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2226 if ((old & test_bits) != test_bits) {
2227 /* enable and lock */
2228 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2230 kvm_cpu_vmxon(phys_addr);
2237 static void vmclear_local_loaded_vmcss(void)
2239 int cpu = raw_smp_processor_id();
2240 struct loaded_vmcs *v, *n;
2242 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2243 loaded_vmcss_on_cpu_link)
2244 __loaded_vmcs_clear(v);
2248 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2251 static void kvm_cpu_vmxoff(void)
2253 asm volatile (__ex("vmxoff"));
2255 intel_pt_handle_vmx(0);
2256 cr4_clear_bits(X86_CR4_VMXE);
2259 static void hardware_disable(void)
2261 vmclear_local_loaded_vmcss();
2265 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2266 u32 msr, u32 *result)
2268 u32 vmx_msr_low, vmx_msr_high;
2269 u32 ctl = ctl_min | ctl_opt;
2271 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2273 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2274 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2276 /* Ensure minimum (required) set of control bits are supported. */
2284 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2285 struct vmx_capability *vmx_cap)
2287 u32 vmx_msr_low, vmx_msr_high;
2288 u32 min, opt, min2, opt2;
2289 u32 _pin_based_exec_control = 0;
2290 u32 _cpu_based_exec_control = 0;
2291 u32 _cpu_based_2nd_exec_control = 0;
2292 u32 _vmexit_control = 0;
2293 u32 _vmentry_control = 0;
2295 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2296 min = CPU_BASED_HLT_EXITING |
2297 #ifdef CONFIG_X86_64
2298 CPU_BASED_CR8_LOAD_EXITING |
2299 CPU_BASED_CR8_STORE_EXITING |
2301 CPU_BASED_CR3_LOAD_EXITING |
2302 CPU_BASED_CR3_STORE_EXITING |
2303 CPU_BASED_UNCOND_IO_EXITING |
2304 CPU_BASED_MOV_DR_EXITING |
2305 CPU_BASED_USE_TSC_OFFSETING |
2306 CPU_BASED_MWAIT_EXITING |
2307 CPU_BASED_MONITOR_EXITING |
2308 CPU_BASED_INVLPG_EXITING |
2309 CPU_BASED_RDPMC_EXITING;
2311 opt = CPU_BASED_TPR_SHADOW |
2312 CPU_BASED_USE_MSR_BITMAPS |
2313 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2314 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2315 &_cpu_based_exec_control) < 0)
2317 #ifdef CONFIG_X86_64
2318 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2319 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2320 ~CPU_BASED_CR8_STORE_EXITING;
2322 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2324 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2325 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2326 SECONDARY_EXEC_WBINVD_EXITING |
2327 SECONDARY_EXEC_ENABLE_VPID |
2328 SECONDARY_EXEC_ENABLE_EPT |
2329 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2330 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2331 SECONDARY_EXEC_DESC |
2332 SECONDARY_EXEC_RDTSCP |
2333 SECONDARY_EXEC_ENABLE_INVPCID |
2334 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2335 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2336 SECONDARY_EXEC_SHADOW_VMCS |
2337 SECONDARY_EXEC_XSAVES |
2338 SECONDARY_EXEC_RDSEED_EXITING |
2339 SECONDARY_EXEC_RDRAND_EXITING |
2340 SECONDARY_EXEC_ENABLE_PML |
2341 SECONDARY_EXEC_TSC_SCALING |
2342 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2343 SECONDARY_EXEC_PT_USE_GPA |
2344 SECONDARY_EXEC_PT_CONCEAL_VMX |
2345 SECONDARY_EXEC_ENABLE_VMFUNC |
2346 SECONDARY_EXEC_ENCLS_EXITING;
2347 if (adjust_vmx_controls(min2, opt2,
2348 MSR_IA32_VMX_PROCBASED_CTLS2,
2349 &_cpu_based_2nd_exec_control) < 0)
2352 #ifndef CONFIG_X86_64
2353 if (!(_cpu_based_2nd_exec_control &
2354 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2355 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2358 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2359 _cpu_based_2nd_exec_control &= ~(
2360 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2361 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2362 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2364 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2365 &vmx_cap->ept, &vmx_cap->vpid);
2367 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2368 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2370 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2371 CPU_BASED_CR3_STORE_EXITING |
2372 CPU_BASED_INVLPG_EXITING);
2373 } else if (vmx_cap->ept) {
2375 pr_warn_once("EPT CAP should not exist if not support "
2376 "1-setting enable EPT VM-execution control\n");
2378 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2381 pr_warn_once("VPID CAP should not exist if not support "
2382 "1-setting enable VPID VM-execution control\n");
2385 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2386 #ifdef CONFIG_X86_64
2387 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2389 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2390 VM_EXIT_LOAD_IA32_PAT |
2391 VM_EXIT_LOAD_IA32_EFER |
2392 VM_EXIT_CLEAR_BNDCFGS |
2393 VM_EXIT_PT_CONCEAL_PIP |
2394 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2395 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2396 &_vmexit_control) < 0)
2399 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2400 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2401 PIN_BASED_VMX_PREEMPTION_TIMER;
2402 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2403 &_pin_based_exec_control) < 0)
2406 if (cpu_has_broken_vmx_preemption_timer())
2407 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2408 if (!(_cpu_based_2nd_exec_control &
2409 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2410 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2412 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2413 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2414 VM_ENTRY_LOAD_IA32_PAT |
2415 VM_ENTRY_LOAD_IA32_EFER |
2416 VM_ENTRY_LOAD_BNDCFGS |
2417 VM_ENTRY_PT_CONCEAL_PIP |
2418 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2419 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2420 &_vmentry_control) < 0)
2424 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2425 * can't be used due to an errata where VM Exit may incorrectly clear
2426 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2427 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2429 if (boot_cpu_data.x86 == 0x6) {
2430 switch (boot_cpu_data.x86_model) {
2431 case 26: /* AAK155 */
2432 case 30: /* AAP115 */
2433 case 37: /* AAT100 */
2434 case 44: /* BC86,AAY89,BD102 */
2436 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2437 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2438 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2439 "does not work properly. Using workaround\n");
2447 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2449 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2450 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2453 #ifdef CONFIG_X86_64
2454 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2455 if (vmx_msr_high & (1u<<16))
2459 /* Require Write-Back (WB) memory type for VMCS accesses. */
2460 if (((vmx_msr_high >> 18) & 15) != 6)
2463 vmcs_conf->size = vmx_msr_high & 0x1fff;
2464 vmcs_conf->order = get_order(vmcs_conf->size);
2465 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2467 vmcs_conf->revision_id = vmx_msr_low;
2469 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2470 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2471 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2472 vmcs_conf->vmexit_ctrl = _vmexit_control;
2473 vmcs_conf->vmentry_ctrl = _vmentry_control;
2475 if (static_branch_unlikely(&enable_evmcs))
2476 evmcs_sanitize_exec_ctrls(vmcs_conf);
2481 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2483 int node = cpu_to_node(cpu);
2487 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2490 vmcs = page_address(pages);
2491 memset(vmcs, 0, vmcs_config.size);
2493 /* KVM supports Enlightened VMCS v1 only */
2494 if (static_branch_unlikely(&enable_evmcs))
2495 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2497 vmcs->hdr.revision_id = vmcs_config.revision_id;
2500 vmcs->hdr.shadow_vmcs = 1;
2504 void free_vmcs(struct vmcs *vmcs)
2506 free_pages((unsigned long)vmcs, vmcs_config.order);
2510 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2512 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2514 if (!loaded_vmcs->vmcs)
2516 loaded_vmcs_clear(loaded_vmcs);
2517 free_vmcs(loaded_vmcs->vmcs);
2518 loaded_vmcs->vmcs = NULL;
2519 if (loaded_vmcs->msr_bitmap)
2520 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2521 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2524 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2526 loaded_vmcs->vmcs = alloc_vmcs(false);
2527 if (!loaded_vmcs->vmcs)
2530 loaded_vmcs->shadow_vmcs = NULL;
2531 loaded_vmcs->hv_timer_soft_disabled = false;
2532 loaded_vmcs_init(loaded_vmcs);
2534 if (cpu_has_vmx_msr_bitmap()) {
2535 loaded_vmcs->msr_bitmap = (unsigned long *)
2536 __get_free_page(GFP_KERNEL_ACCOUNT);
2537 if (!loaded_vmcs->msr_bitmap)
2539 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2541 if (IS_ENABLED(CONFIG_HYPERV) &&
2542 static_branch_unlikely(&enable_evmcs) &&
2543 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2544 struct hv_enlightened_vmcs *evmcs =
2545 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2547 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2551 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2552 memset(&loaded_vmcs->controls_shadow, 0,
2553 sizeof(struct vmcs_controls_shadow));
2558 free_loaded_vmcs(loaded_vmcs);
2562 static void free_kvm_area(void)
2566 for_each_possible_cpu(cpu) {
2567 free_vmcs(per_cpu(vmxarea, cpu));
2568 per_cpu(vmxarea, cpu) = NULL;
2572 static __init int alloc_kvm_area(void)
2576 for_each_possible_cpu(cpu) {
2579 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2586 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2587 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2588 * revision_id reported by MSR_IA32_VMX_BASIC.
2590 * However, even though not explicitly documented by
2591 * TLFS, VMXArea passed as VMXON argument should
2592 * still be marked with revision_id reported by
2595 if (static_branch_unlikely(&enable_evmcs))
2596 vmcs->hdr.revision_id = vmcs_config.revision_id;
2598 per_cpu(vmxarea, cpu) = vmcs;
2603 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2604 struct kvm_segment *save)
2606 if (!emulate_invalid_guest_state) {
2608 * CS and SS RPL should be equal during guest entry according
2609 * to VMX spec, but in reality it is not always so. Since vcpu
2610 * is in the middle of the transition from real mode to
2611 * protected mode it is safe to assume that RPL 0 is a good
2614 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2615 save->selector &= ~SEGMENT_RPL_MASK;
2616 save->dpl = save->selector & SEGMENT_RPL_MASK;
2619 vmx_set_segment(vcpu, save, seg);
2622 static void enter_pmode(struct kvm_vcpu *vcpu)
2624 unsigned long flags;
2625 struct vcpu_vmx *vmx = to_vmx(vcpu);
2628 * Update real mode segment cache. It may be not up-to-date if sement
2629 * register was written while vcpu was in a guest mode.
2631 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2632 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2633 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2634 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2635 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2636 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2638 vmx->rmode.vm86_active = 0;
2640 vmx_segment_cache_clear(vmx);
2642 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2644 flags = vmcs_readl(GUEST_RFLAGS);
2645 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2646 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2647 vmcs_writel(GUEST_RFLAGS, flags);
2649 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2650 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2652 update_exception_bitmap(vcpu);
2654 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2655 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2656 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2657 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2658 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2659 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2662 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2664 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2665 struct kvm_segment var = *save;
2668 if (seg == VCPU_SREG_CS)
2671 if (!emulate_invalid_guest_state) {
2672 var.selector = var.base >> 4;
2673 var.base = var.base & 0xffff0;
2683 if (save->base & 0xf)
2684 printk_once(KERN_WARNING "kvm: segment base is not "
2685 "paragraph aligned when entering "
2686 "protected mode (seg=%d)", seg);
2689 vmcs_write16(sf->selector, var.selector);
2690 vmcs_writel(sf->base, var.base);
2691 vmcs_write32(sf->limit, var.limit);
2692 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2695 static void enter_rmode(struct kvm_vcpu *vcpu)
2697 unsigned long flags;
2698 struct vcpu_vmx *vmx = to_vmx(vcpu);
2699 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2701 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2702 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2703 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2704 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2705 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2706 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2707 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2709 vmx->rmode.vm86_active = 1;
2712 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2713 * vcpu. Warn the user that an update is overdue.
2715 if (!kvm_vmx->tss_addr)
2716 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2717 "called before entering vcpu\n");
2719 vmx_segment_cache_clear(vmx);
2721 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2722 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2723 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2725 flags = vmcs_readl(GUEST_RFLAGS);
2726 vmx->rmode.save_rflags = flags;
2728 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2730 vmcs_writel(GUEST_RFLAGS, flags);
2731 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2732 update_exception_bitmap(vcpu);
2734 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2735 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2736 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2737 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2738 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2739 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2741 kvm_mmu_reset_context(vcpu);
2744 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2746 struct vcpu_vmx *vmx = to_vmx(vcpu);
2747 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2752 vcpu->arch.efer = efer;
2753 if (efer & EFER_LMA) {
2754 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2757 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2759 msr->data = efer & ~EFER_LME;
2764 #ifdef CONFIG_X86_64
2766 static void enter_lmode(struct kvm_vcpu *vcpu)
2770 vmx_segment_cache_clear(to_vmx(vcpu));
2772 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2773 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2774 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2776 vmcs_write32(GUEST_TR_AR_BYTES,
2777 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2778 | VMX_AR_TYPE_BUSY_64_TSS);
2780 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2783 static void exit_lmode(struct kvm_vcpu *vcpu)
2785 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2786 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2791 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2793 int vpid = to_vmx(vcpu)->vpid;
2795 if (!vpid_sync_vcpu_addr(vpid, addr))
2796 vpid_sync_context(vpid);
2799 * If VPIDs are not supported or enabled, then the above is a no-op.
2800 * But we don't really need a TLB flush in that case anyway, because
2801 * each VM entry/exit includes an implicit flush when VPID is 0.
2805 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2807 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2809 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2810 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2813 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2815 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2816 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2817 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2820 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2822 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2824 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2825 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2828 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2830 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2832 if (!test_bit(VCPU_EXREG_PDPTR,
2833 (unsigned long *)&vcpu->arch.regs_dirty))
2836 if (is_pae_paging(vcpu)) {
2837 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2838 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2839 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2840 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2844 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2846 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2848 if (is_pae_paging(vcpu)) {
2849 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2850 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2851 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2852 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2855 __set_bit(VCPU_EXREG_PDPTR,
2856 (unsigned long *)&vcpu->arch.regs_avail);
2857 __set_bit(VCPU_EXREG_PDPTR,
2858 (unsigned long *)&vcpu->arch.regs_dirty);
2861 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2863 struct kvm_vcpu *vcpu)
2865 struct vcpu_vmx *vmx = to_vmx(vcpu);
2867 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2868 vmx_decache_cr3(vcpu);
2869 if (!(cr0 & X86_CR0_PG)) {
2870 /* From paging/starting to nonpaging */
2871 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2872 CPU_BASED_CR3_STORE_EXITING);
2873 vcpu->arch.cr0 = cr0;
2874 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2875 } else if (!is_paging(vcpu)) {
2876 /* From nonpaging to paging */
2877 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2878 CPU_BASED_CR3_STORE_EXITING);
2879 vcpu->arch.cr0 = cr0;
2880 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2883 if (!(cr0 & X86_CR0_WP))
2884 *hw_cr0 &= ~X86_CR0_WP;
2887 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2889 struct vcpu_vmx *vmx = to_vmx(vcpu);
2890 unsigned long hw_cr0;
2892 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2893 if (enable_unrestricted_guest)
2894 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2896 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2898 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2901 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2905 #ifdef CONFIG_X86_64
2906 if (vcpu->arch.efer & EFER_LME) {
2907 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2909 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2914 if (enable_ept && !enable_unrestricted_guest)
2915 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2917 vmcs_writel(CR0_READ_SHADOW, cr0);
2918 vmcs_writel(GUEST_CR0, hw_cr0);
2919 vcpu->arch.cr0 = cr0;
2921 /* depends on vcpu->arch.cr0 to be set to a new value */
2922 vmx->emulation_required = emulation_required(vcpu);
2925 static int get_ept_level(struct kvm_vcpu *vcpu)
2927 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2932 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2934 u64 eptp = VMX_EPTP_MT_WB;
2936 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2938 if (enable_ept_ad_bits &&
2939 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2940 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2941 eptp |= (root_hpa & PAGE_MASK);
2946 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2948 struct kvm *kvm = vcpu->kvm;
2949 unsigned long guest_cr3;
2954 eptp = construct_eptp(vcpu, cr3);
2955 vmcs_write64(EPT_POINTER, eptp);
2957 if (kvm_x86_ops->tlb_remote_flush) {
2958 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2959 to_vmx(vcpu)->ept_pointer = eptp;
2960 to_kvm_vmx(kvm)->ept_pointers_match
2961 = EPT_POINTERS_CHECK;
2962 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2965 if (enable_unrestricted_guest || is_paging(vcpu) ||
2966 is_guest_mode(vcpu))
2967 guest_cr3 = kvm_read_cr3(vcpu);
2969 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
2970 ept_load_pdptrs(vcpu);
2973 vmcs_writel(GUEST_CR3, guest_cr3);
2976 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2978 struct vcpu_vmx *vmx = to_vmx(vcpu);
2980 * Pass through host's Machine Check Enable value to hw_cr4, which
2981 * is in force while we are in guest mode. Do not let guests control
2982 * this bit, even if host CR4.MCE == 0.
2984 unsigned long hw_cr4;
2986 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2987 if (enable_unrestricted_guest)
2988 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2989 else if (vmx->rmode.vm86_active)
2990 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2992 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
2994 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2995 if (cr4 & X86_CR4_UMIP) {
2996 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
2997 hw_cr4 &= ~X86_CR4_UMIP;
2998 } else if (!is_guest_mode(vcpu) ||
2999 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3000 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3004 if (cr4 & X86_CR4_VMXE) {
3006 * To use VMXON (and later other VMX instructions), a guest
3007 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3008 * So basically the check on whether to allow nested VMX
3009 * is here. We operate under the default treatment of SMM,
3010 * so VMX cannot be enabled under SMM.
3012 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
3016 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3019 vcpu->arch.cr4 = cr4;
3021 if (!enable_unrestricted_guest) {
3023 if (!is_paging(vcpu)) {
3024 hw_cr4 &= ~X86_CR4_PAE;
3025 hw_cr4 |= X86_CR4_PSE;
3026 } else if (!(cr4 & X86_CR4_PAE)) {
3027 hw_cr4 &= ~X86_CR4_PAE;
3032 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3033 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3034 * to be manually disabled when guest switches to non-paging
3037 * If !enable_unrestricted_guest, the CPU is always running
3038 * with CR0.PG=1 and CR4 needs to be modified.
3039 * If enable_unrestricted_guest, the CPU automatically
3040 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3042 if (!is_paging(vcpu))
3043 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3046 vmcs_writel(CR4_READ_SHADOW, cr4);
3047 vmcs_writel(GUEST_CR4, hw_cr4);
3051 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3053 struct vcpu_vmx *vmx = to_vmx(vcpu);
3056 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3057 *var = vmx->rmode.segs[seg];
3058 if (seg == VCPU_SREG_TR
3059 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3061 var->base = vmx_read_guest_seg_base(vmx, seg);
3062 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3065 var->base = vmx_read_guest_seg_base(vmx, seg);
3066 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3067 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3068 ar = vmx_read_guest_seg_ar(vmx, seg);
3069 var->unusable = (ar >> 16) & 1;
3070 var->type = ar & 15;
3071 var->s = (ar >> 4) & 1;
3072 var->dpl = (ar >> 5) & 3;
3074 * Some userspaces do not preserve unusable property. Since usable
3075 * segment has to be present according to VMX spec we can use present
3076 * property to amend userspace bug by making unusable segment always
3077 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3078 * segment as unusable.
3080 var->present = !var->unusable;
3081 var->avl = (ar >> 12) & 1;
3082 var->l = (ar >> 13) & 1;
3083 var->db = (ar >> 14) & 1;
3084 var->g = (ar >> 15) & 1;
3087 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3089 struct kvm_segment s;
3091 if (to_vmx(vcpu)->rmode.vm86_active) {
3092 vmx_get_segment(vcpu, &s, seg);
3095 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3098 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3100 struct vcpu_vmx *vmx = to_vmx(vcpu);
3102 if (unlikely(vmx->rmode.vm86_active))
3105 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3106 return VMX_AR_DPL(ar);
3110 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3114 if (var->unusable || !var->present)
3117 ar = var->type & 15;
3118 ar |= (var->s & 1) << 4;
3119 ar |= (var->dpl & 3) << 5;
3120 ar |= (var->present & 1) << 7;
3121 ar |= (var->avl & 1) << 12;
3122 ar |= (var->l & 1) << 13;
3123 ar |= (var->db & 1) << 14;
3124 ar |= (var->g & 1) << 15;
3130 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3132 struct vcpu_vmx *vmx = to_vmx(vcpu);
3133 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3135 vmx_segment_cache_clear(vmx);
3137 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3138 vmx->rmode.segs[seg] = *var;
3139 if (seg == VCPU_SREG_TR)
3140 vmcs_write16(sf->selector, var->selector);
3142 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3146 vmcs_writel(sf->base, var->base);
3147 vmcs_write32(sf->limit, var->limit);
3148 vmcs_write16(sf->selector, var->selector);
3151 * Fix the "Accessed" bit in AR field of segment registers for older
3153 * IA32 arch specifies that at the time of processor reset the
3154 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3155 * is setting it to 0 in the userland code. This causes invalid guest
3156 * state vmexit when "unrestricted guest" mode is turned on.
3157 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3158 * tree. Newer qemu binaries with that qemu fix would not need this
3161 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3162 var->type |= 0x1; /* Accessed */
3164 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3167 vmx->emulation_required = emulation_required(vcpu);
3170 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3172 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3174 *db = (ar >> 14) & 1;
3175 *l = (ar >> 13) & 1;
3178 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3180 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3181 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3184 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3186 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3187 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3190 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3192 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3193 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3196 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3198 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3199 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3202 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3204 struct kvm_segment var;
3207 vmx_get_segment(vcpu, &var, seg);
3209 if (seg == VCPU_SREG_CS)
3211 ar = vmx_segment_access_rights(&var);
3213 if (var.base != (var.selector << 4))
3215 if (var.limit != 0xffff)
3223 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3225 struct kvm_segment cs;
3226 unsigned int cs_rpl;
3228 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3229 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3233 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3237 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3238 if (cs.dpl > cs_rpl)
3241 if (cs.dpl != cs_rpl)
3247 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3251 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3253 struct kvm_segment ss;
3254 unsigned int ss_rpl;
3256 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3257 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3261 if (ss.type != 3 && ss.type != 7)
3265 if (ss.dpl != ss_rpl) /* DPL != RPL */
3273 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3275 struct kvm_segment var;
3278 vmx_get_segment(vcpu, &var, seg);
3279 rpl = var.selector & SEGMENT_RPL_MASK;
3287 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3288 if (var.dpl < rpl) /* DPL < RPL */
3292 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3298 static bool tr_valid(struct kvm_vcpu *vcpu)
3300 struct kvm_segment tr;
3302 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3306 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3308 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3316 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3318 struct kvm_segment ldtr;
3320 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3324 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3334 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3336 struct kvm_segment cs, ss;
3338 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3339 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3341 return ((cs.selector & SEGMENT_RPL_MASK) ==
3342 (ss.selector & SEGMENT_RPL_MASK));
3346 * Check if guest state is valid. Returns true if valid, false if
3348 * We assume that registers are always usable
3350 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3352 if (enable_unrestricted_guest)
3355 /* real mode guest state checks */
3356 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3357 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3359 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3361 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3363 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3365 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3367 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3370 /* protected mode guest state checks */
3371 if (!cs_ss_rpl_check(vcpu))
3373 if (!code_segment_valid(vcpu))
3375 if (!stack_segment_valid(vcpu))
3377 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3379 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3381 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3383 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3385 if (!tr_valid(vcpu))
3387 if (!ldtr_valid(vcpu))
3391 * - Add checks on RIP
3392 * - Add checks on RFLAGS
3398 static int init_rmode_tss(struct kvm *kvm)
3404 idx = srcu_read_lock(&kvm->srcu);
3405 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3406 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3409 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3410 r = kvm_write_guest_page(kvm, fn++, &data,
3411 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3414 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3417 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3421 r = kvm_write_guest_page(kvm, fn, &data,
3422 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3425 srcu_read_unlock(&kvm->srcu, idx);
3429 static int init_rmode_identity_map(struct kvm *kvm)
3431 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3433 kvm_pfn_t identity_map_pfn;
3436 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3437 mutex_lock(&kvm->slots_lock);
3439 if (likely(kvm_vmx->ept_identity_pagetable_done))
3442 if (!kvm_vmx->ept_identity_map_addr)
3443 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3444 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3446 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3447 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3451 idx = srcu_read_lock(&kvm->srcu);
3452 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3455 /* Set up identity-mapping pagetable for EPT in real mode */
3456 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3457 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3458 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3459 r = kvm_write_guest_page(kvm, identity_map_pfn,
3460 &tmp, i * sizeof(tmp), sizeof(tmp));
3464 kvm_vmx->ept_identity_pagetable_done = true;
3467 srcu_read_unlock(&kvm->srcu, idx);
3470 mutex_unlock(&kvm->slots_lock);
3474 static void seg_setup(int seg)
3476 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3479 vmcs_write16(sf->selector, 0);
3480 vmcs_writel(sf->base, 0);
3481 vmcs_write32(sf->limit, 0xffff);
3483 if (seg == VCPU_SREG_CS)
3484 ar |= 0x08; /* code segment */
3486 vmcs_write32(sf->ar_bytes, ar);
3489 static int alloc_apic_access_page(struct kvm *kvm)
3494 mutex_lock(&kvm->slots_lock);
3495 if (kvm->arch.apic_access_page_done)
3497 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3498 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3502 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3503 if (is_error_page(page)) {
3509 * Do not pin the page in memory, so that memory hot-unplug
3510 * is able to migrate it.
3513 kvm->arch.apic_access_page_done = true;
3515 mutex_unlock(&kvm->slots_lock);
3519 int allocate_vpid(void)
3525 spin_lock(&vmx_vpid_lock);
3526 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3527 if (vpid < VMX_NR_VPIDS)
3528 __set_bit(vpid, vmx_vpid_bitmap);
3531 spin_unlock(&vmx_vpid_lock);
3535 void free_vpid(int vpid)
3537 if (!enable_vpid || vpid == 0)
3539 spin_lock(&vmx_vpid_lock);
3540 __clear_bit(vpid, vmx_vpid_bitmap);
3541 spin_unlock(&vmx_vpid_lock);
3544 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3547 int f = sizeof(unsigned long);
3549 if (!cpu_has_vmx_msr_bitmap())
3552 if (static_branch_unlikely(&enable_evmcs))
3553 evmcs_touch_msr_bitmap();
3556 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3557 * have the write-low and read-high bitmap offsets the wrong way round.
3558 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3560 if (msr <= 0x1fff) {
3561 if (type & MSR_TYPE_R)
3563 __clear_bit(msr, msr_bitmap + 0x000 / f);
3565 if (type & MSR_TYPE_W)
3567 __clear_bit(msr, msr_bitmap + 0x800 / f);
3569 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3571 if (type & MSR_TYPE_R)
3573 __clear_bit(msr, msr_bitmap + 0x400 / f);
3575 if (type & MSR_TYPE_W)
3577 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3582 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3585 int f = sizeof(unsigned long);
3587 if (!cpu_has_vmx_msr_bitmap())
3590 if (static_branch_unlikely(&enable_evmcs))
3591 evmcs_touch_msr_bitmap();
3594 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3595 * have the write-low and read-high bitmap offsets the wrong way round.
3596 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3598 if (msr <= 0x1fff) {
3599 if (type & MSR_TYPE_R)
3601 __set_bit(msr, msr_bitmap + 0x000 / f);
3603 if (type & MSR_TYPE_W)
3605 __set_bit(msr, msr_bitmap + 0x800 / f);
3607 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3609 if (type & MSR_TYPE_R)
3611 __set_bit(msr, msr_bitmap + 0x400 / f);
3613 if (type & MSR_TYPE_W)
3615 __set_bit(msr, msr_bitmap + 0xc00 / f);
3620 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3621 u32 msr, int type, bool value)
3624 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3626 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3629 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3633 if (cpu_has_secondary_exec_ctrls() &&
3634 (secondary_exec_controls_get(to_vmx(vcpu)) &
3635 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3636 mode |= MSR_BITMAP_MODE_X2APIC;
3637 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3638 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3644 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3649 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3650 unsigned word = msr / BITS_PER_LONG;
3651 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3652 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3655 if (mode & MSR_BITMAP_MODE_X2APIC) {
3657 * TPR reads and writes can be virtualized even if virtual interrupt
3658 * delivery is not in use.
3660 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3661 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3662 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3663 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3664 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3669 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3671 struct vcpu_vmx *vmx = to_vmx(vcpu);
3672 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3673 u8 mode = vmx_msr_bitmap_mode(vcpu);
3674 u8 changed = mode ^ vmx->msr_bitmap_mode;
3679 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3680 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3682 vmx->msr_bitmap_mode = mode;
3685 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3687 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3688 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3691 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3693 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3695 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3697 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3699 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3700 vmx_set_intercept_for_msr(msr_bitmap,
3701 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3702 vmx_set_intercept_for_msr(msr_bitmap,
3703 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3707 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3709 return enable_apicv;
3712 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3714 struct vcpu_vmx *vmx = to_vmx(vcpu);
3719 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3720 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3721 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3724 rvi = vmx_get_rvi();
3726 vapic_page = vmx->nested.virtual_apic_map.hva;
3727 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3729 return ((rvi & 0xf0) > (vppr & 0xf0));
3732 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3736 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3738 if (vcpu->mode == IN_GUEST_MODE) {
3740 * The vector of interrupt to be delivered to vcpu had
3741 * been set in PIR before this function.
3743 * Following cases will be reached in this block, and
3744 * we always send a notification event in all cases as
3747 * Case 1: vcpu keeps in non-root mode. Sending a
3748 * notification event posts the interrupt to vcpu.
3750 * Case 2: vcpu exits to root mode and is still
3751 * runnable. PIR will be synced to vIRR before the
3752 * next vcpu entry. Sending a notification event in
3753 * this case has no effect, as vcpu is not in root
3756 * Case 3: vcpu exits to root mode and is blocked.
3757 * vcpu_block() has already synced PIR to vIRR and
3758 * never blocks vcpu if vIRR is not cleared. Therefore,
3759 * a blocked vcpu here does not wait for any requested
3760 * interrupts in PIR, and sending a notification event
3761 * which has no effect is safe here.
3764 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3771 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3774 struct vcpu_vmx *vmx = to_vmx(vcpu);
3776 if (is_guest_mode(vcpu) &&
3777 vector == vmx->nested.posted_intr_nv) {
3779 * If a posted intr is not recognized by hardware,
3780 * we will accomplish it in the next vmentry.
3782 vmx->nested.pi_pending = true;
3783 kvm_make_request(KVM_REQ_EVENT, vcpu);
3784 /* the PIR and ON have been set by L1. */
3785 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3786 kvm_vcpu_kick(vcpu);
3792 * Send interrupt to vcpu via posted interrupt way.
3793 * 1. If target vcpu is running(non-root mode), send posted interrupt
3794 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3795 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3796 * interrupt from PIR in next vmentry.
3798 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3800 struct vcpu_vmx *vmx = to_vmx(vcpu);
3803 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3807 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3810 /* If a previous notification has sent the IPI, nothing to do. */
3811 if (pi_test_and_set_on(&vmx->pi_desc))
3814 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3815 kvm_vcpu_kick(vcpu);
3819 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3820 * will not change in the lifetime of the guest.
3821 * Note that host-state that does change is set elsewhere. E.g., host-state
3822 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3824 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3828 unsigned long cr0, cr3, cr4;
3831 WARN_ON(cr0 & X86_CR0_TS);
3832 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3835 * Save the most likely value for this task's CR3 in the VMCS.
3836 * We can't use __get_current_cr3_fast() because we're not atomic.
3839 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3840 vmx->loaded_vmcs->host_state.cr3 = cr3;
3842 /* Save the most likely value for this task's CR4 in the VMCS. */
3843 cr4 = cr4_read_shadow();
3844 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3845 vmx->loaded_vmcs->host_state.cr4 = cr4;
3847 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3848 #ifdef CONFIG_X86_64
3850 * Load null selectors, so we can avoid reloading them in
3851 * vmx_prepare_switch_to_host(), in case userspace uses
3852 * the null selectors too (the expected case).
3854 vmcs_write16(HOST_DS_SELECTOR, 0);
3855 vmcs_write16(HOST_ES_SELECTOR, 0);
3857 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3858 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3860 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3861 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3863 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3865 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3867 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3868 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3869 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3870 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3872 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3873 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3874 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3877 if (cpu_has_load_ia32_efer())
3878 vmcs_write64(HOST_IA32_EFER, host_efer);
3881 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3883 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3885 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3886 if (is_guest_mode(&vmx->vcpu))
3887 vmx->vcpu.arch.cr4_guest_owned_bits &=
3888 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3889 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3892 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3894 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3896 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3897 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3900 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3902 if (!enable_preemption_timer)
3903 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3905 return pin_based_exec_ctrl;
3908 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3910 struct vcpu_vmx *vmx = to_vmx(vcpu);
3912 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3913 if (cpu_has_secondary_exec_ctrls()) {
3914 if (kvm_vcpu_apicv_active(vcpu))
3915 secondary_exec_controls_setbit(vmx,
3916 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3917 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3919 secondary_exec_controls_clearbit(vmx,
3920 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3921 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3924 if (cpu_has_vmx_msr_bitmap())
3925 vmx_update_msr_bitmap(vcpu);
3928 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3930 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3932 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3933 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3935 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3936 exec_control &= ~CPU_BASED_TPR_SHADOW;
3937 #ifdef CONFIG_X86_64
3938 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3939 CPU_BASED_CR8_LOAD_EXITING;
3943 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3944 CPU_BASED_CR3_LOAD_EXITING |
3945 CPU_BASED_INVLPG_EXITING;
3946 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3947 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3948 CPU_BASED_MONITOR_EXITING);
3949 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3950 exec_control &= ~CPU_BASED_HLT_EXITING;
3951 return exec_control;
3955 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3957 struct kvm_vcpu *vcpu = &vmx->vcpu;
3959 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3961 if (pt_mode == PT_MODE_SYSTEM)
3962 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3963 if (!cpu_need_virtualize_apic_accesses(vcpu))
3964 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3966 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3968 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3969 enable_unrestricted_guest = 0;
3971 if (!enable_unrestricted_guest)
3972 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3973 if (kvm_pause_in_guest(vmx->vcpu.kvm))
3974 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3975 if (!kvm_vcpu_apicv_active(vcpu))
3976 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3977 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3978 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3980 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3981 * in vmx_set_cr4. */
3982 exec_control &= ~SECONDARY_EXEC_DESC;
3984 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3986 We can NOT enable shadow_vmcs here because we don't have yet
3989 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
3992 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
3994 if (vmx_xsaves_supported()) {
3995 /* Exposing XSAVES only when XSAVE is exposed */
3996 bool xsaves_enabled =
3997 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3998 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4000 if (!xsaves_enabled)
4001 exec_control &= ~SECONDARY_EXEC_XSAVES;
4005 vmx->nested.msrs.secondary_ctls_high |=
4006 SECONDARY_EXEC_XSAVES;
4008 vmx->nested.msrs.secondary_ctls_high &=
4009 ~SECONDARY_EXEC_XSAVES;
4013 if (vmx_rdtscp_supported()) {
4014 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
4015 if (!rdtscp_enabled)
4016 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4020 vmx->nested.msrs.secondary_ctls_high |=
4021 SECONDARY_EXEC_RDTSCP;
4023 vmx->nested.msrs.secondary_ctls_high &=
4024 ~SECONDARY_EXEC_RDTSCP;
4028 if (vmx_invpcid_supported()) {
4029 /* Exposing INVPCID only when PCID is exposed */
4030 bool invpcid_enabled =
4031 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4032 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4034 if (!invpcid_enabled) {
4035 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4036 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4040 if (invpcid_enabled)
4041 vmx->nested.msrs.secondary_ctls_high |=
4042 SECONDARY_EXEC_ENABLE_INVPCID;
4044 vmx->nested.msrs.secondary_ctls_high &=
4045 ~SECONDARY_EXEC_ENABLE_INVPCID;
4049 if (vmx_rdrand_supported()) {
4050 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4052 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4056 vmx->nested.msrs.secondary_ctls_high |=
4057 SECONDARY_EXEC_RDRAND_EXITING;
4059 vmx->nested.msrs.secondary_ctls_high &=
4060 ~SECONDARY_EXEC_RDRAND_EXITING;
4064 if (vmx_rdseed_supported()) {
4065 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4067 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4071 vmx->nested.msrs.secondary_ctls_high |=
4072 SECONDARY_EXEC_RDSEED_EXITING;
4074 vmx->nested.msrs.secondary_ctls_high &=
4075 ~SECONDARY_EXEC_RDSEED_EXITING;
4079 if (vmx_waitpkg_supported()) {
4080 bool waitpkg_enabled =
4081 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG);
4083 if (!waitpkg_enabled)
4084 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4087 if (waitpkg_enabled)
4088 vmx->nested.msrs.secondary_ctls_high |=
4089 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4091 vmx->nested.msrs.secondary_ctls_high &=
4092 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
4096 vmx->secondary_exec_control = exec_control;
4099 static void ept_set_mmio_spte_mask(void)
4102 * EPT Misconfigurations can be generated if the value of bits 2:0
4103 * of an EPT paging-structure entry is 110b (write/execute).
4105 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4106 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4109 #define VMX_XSS_EXIT_BITMAP 0
4112 * Sets up the vmcs for emulated real mode.
4114 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4119 nested_vmx_vcpu_setup();
4121 if (cpu_has_vmx_msr_bitmap())
4122 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4124 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4127 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4128 vmx->hv_deadline_tsc = -1;
4130 exec_controls_set(vmx, vmx_exec_control(vmx));
4132 if (cpu_has_secondary_exec_ctrls()) {
4133 vmx_compute_secondary_exec_control(vmx);
4134 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4137 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4138 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4139 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4140 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4141 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4143 vmcs_write16(GUEST_INTR_STATUS, 0);
4145 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4146 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4149 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4150 vmcs_write32(PLE_GAP, ple_gap);
4151 vmx->ple_window = ple_window;
4152 vmx->ple_window_dirty = true;
4155 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4156 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4157 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4159 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4160 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4161 vmx_set_constant_host_state(vmx);
4162 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4163 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4165 if (cpu_has_vmx_vmfunc())
4166 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4168 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4169 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4170 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4171 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4172 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4174 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4175 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4177 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4178 u32 index = vmx_msr_index[i];
4179 u32 data_low, data_high;
4182 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4184 if (wrmsr_safe(index, data_low, data_high) < 0)
4186 vmx->guest_msrs[j].index = i;
4187 vmx->guest_msrs[j].data = 0;
4188 vmx->guest_msrs[j].mask = -1ull;
4192 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4194 /* 22.2.1, 20.8.1 */
4195 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4197 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4198 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4200 set_cr4_guest_host_mask(vmx);
4202 if (vmx_xsaves_supported())
4203 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4206 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4207 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4210 if (cpu_has_vmx_encls_vmexit())
4211 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4213 if (pt_mode == PT_MODE_HOST_GUEST) {
4214 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4215 /* Bit[6~0] are forced to 1, writes are ignored. */
4216 vmx->pt_desc.guest.output_mask = 0x7F;
4217 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4221 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4223 struct vcpu_vmx *vmx = to_vmx(vcpu);
4224 struct msr_data apic_base_msr;
4227 vmx->rmode.vm86_active = 0;
4230 vmx->msr_ia32_umwait_control = 0;
4232 vcpu->arch.microcode_version = 0x100000000ULL;
4233 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4234 vmx->hv_deadline_tsc = -1;
4235 kvm_set_cr8(vcpu, 0);
4238 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4239 MSR_IA32_APICBASE_ENABLE;
4240 if (kvm_vcpu_is_reset_bsp(vcpu))
4241 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4242 apic_base_msr.host_initiated = true;
4243 kvm_set_apic_base(vcpu, &apic_base_msr);
4246 vmx_segment_cache_clear(vmx);
4248 seg_setup(VCPU_SREG_CS);
4249 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4250 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4252 seg_setup(VCPU_SREG_DS);
4253 seg_setup(VCPU_SREG_ES);
4254 seg_setup(VCPU_SREG_FS);
4255 seg_setup(VCPU_SREG_GS);
4256 seg_setup(VCPU_SREG_SS);
4258 vmcs_write16(GUEST_TR_SELECTOR, 0);
4259 vmcs_writel(GUEST_TR_BASE, 0);
4260 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4261 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4263 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4264 vmcs_writel(GUEST_LDTR_BASE, 0);
4265 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4266 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4269 vmcs_write32(GUEST_SYSENTER_CS, 0);
4270 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4271 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4272 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4275 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4276 kvm_rip_write(vcpu, 0xfff0);
4278 vmcs_writel(GUEST_GDTR_BASE, 0);
4279 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4281 vmcs_writel(GUEST_IDTR_BASE, 0);
4282 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4284 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4285 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4286 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4287 if (kvm_mpx_supported())
4288 vmcs_write64(GUEST_BNDCFGS, 0);
4292 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4294 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4295 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4296 if (cpu_need_tpr_shadow(vcpu))
4297 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4298 __pa(vcpu->arch.apic->regs));
4299 vmcs_write32(TPR_THRESHOLD, 0);
4302 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4305 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4307 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4308 vmx->vcpu.arch.cr0 = cr0;
4309 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4310 vmx_set_cr4(vcpu, 0);
4311 vmx_set_efer(vcpu, 0);
4313 update_exception_bitmap(vcpu);
4315 vpid_sync_context(vmx->vpid);
4317 vmx_clear_hlt(vcpu);
4320 static void enable_irq_window(struct kvm_vcpu *vcpu)
4322 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4325 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4328 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4329 enable_irq_window(vcpu);
4333 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4336 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4338 struct vcpu_vmx *vmx = to_vmx(vcpu);
4340 int irq = vcpu->arch.interrupt.nr;
4342 trace_kvm_inj_virq(irq);
4344 ++vcpu->stat.irq_injections;
4345 if (vmx->rmode.vm86_active) {
4347 if (vcpu->arch.interrupt.soft)
4348 inc_eip = vcpu->arch.event_exit_inst_len;
4349 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4352 intr = irq | INTR_INFO_VALID_MASK;
4353 if (vcpu->arch.interrupt.soft) {
4354 intr |= INTR_TYPE_SOFT_INTR;
4355 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4356 vmx->vcpu.arch.event_exit_inst_len);
4358 intr |= INTR_TYPE_EXT_INTR;
4359 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4361 vmx_clear_hlt(vcpu);
4364 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4366 struct vcpu_vmx *vmx = to_vmx(vcpu);
4370 * Tracking the NMI-blocked state in software is built upon
4371 * finding the next open IRQ window. This, in turn, depends on
4372 * well-behaving guests: They have to keep IRQs disabled at
4373 * least as long as the NMI handler runs. Otherwise we may
4374 * cause NMI nesting, maybe breaking the guest. But as this is
4375 * highly unlikely, we can live with the residual risk.
4377 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4378 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4381 ++vcpu->stat.nmi_injections;
4382 vmx->loaded_vmcs->nmi_known_unmasked = false;
4384 if (vmx->rmode.vm86_active) {
4385 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4389 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4390 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4392 vmx_clear_hlt(vcpu);
4395 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4397 struct vcpu_vmx *vmx = to_vmx(vcpu);
4401 return vmx->loaded_vmcs->soft_vnmi_blocked;
4402 if (vmx->loaded_vmcs->nmi_known_unmasked)
4404 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4405 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4409 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4411 struct vcpu_vmx *vmx = to_vmx(vcpu);
4414 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4415 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4416 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4419 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4421 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4422 GUEST_INTR_STATE_NMI);
4424 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4425 GUEST_INTR_STATE_NMI);
4429 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4431 if (to_vmx(vcpu)->nested.nested_run_pending)
4435 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4438 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4439 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4440 | GUEST_INTR_STATE_NMI));
4443 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4445 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4446 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4447 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4448 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4451 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4455 if (enable_unrestricted_guest)
4458 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4462 to_kvm_vmx(kvm)->tss_addr = addr;
4463 return init_rmode_tss(kvm);
4466 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4468 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4472 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4477 * Update instruction length as we may reinject the exception
4478 * from user space while in guest debugging mode.
4480 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4481 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4482 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4486 if (vcpu->guest_debug &
4487 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4504 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4505 int vec, u32 err_code)
4508 * Instruction with address size override prefix opcode 0x67
4509 * Cause the #SS fault with 0 error code in VM86 mode.
4511 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4512 if (kvm_emulate_instruction(vcpu, 0)) {
4513 if (vcpu->arch.halt_request) {
4514 vcpu->arch.halt_request = 0;
4515 return kvm_vcpu_halt(vcpu);
4523 * Forward all other exceptions that are valid in real mode.
4524 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4525 * the required debugging infrastructure rework.
4527 kvm_queue_exception(vcpu, vec);
4532 * Trigger machine check on the host. We assume all the MSRs are already set up
4533 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4534 * We pass a fake environment to the machine check handler because we want
4535 * the guest to be always treated like user space, no matter what context
4536 * it used internally.
4538 static void kvm_machine_check(void)
4540 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4541 struct pt_regs regs = {
4542 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4543 .flags = X86_EFLAGS_IF,
4546 do_machine_check(®s, 0);
4550 static int handle_machine_check(struct kvm_vcpu *vcpu)
4552 /* handled by vmx_vcpu_run() */
4556 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4558 struct vcpu_vmx *vmx = to_vmx(vcpu);
4559 struct kvm_run *kvm_run = vcpu->run;
4560 u32 intr_info, ex_no, error_code;
4561 unsigned long cr2, rip, dr6;
4564 vect_info = vmx->idt_vectoring_info;
4565 intr_info = vmx->exit_intr_info;
4567 if (is_machine_check(intr_info) || is_nmi(intr_info))
4568 return 1; /* handled by handle_exception_nmi_irqoff() */
4570 if (is_invalid_opcode(intr_info))
4571 return handle_ud(vcpu);
4574 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4575 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4577 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4578 WARN_ON_ONCE(!enable_vmware_backdoor);
4581 * VMware backdoor emulation on #GP interception only handles
4582 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4583 * error code on #GP.
4586 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4589 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4593 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4594 * MMIO, it is better to report an internal error.
4595 * See the comments in vmx_handle_exit.
4597 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4598 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4599 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4600 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4601 vcpu->run->internal.ndata = 3;
4602 vcpu->run->internal.data[0] = vect_info;
4603 vcpu->run->internal.data[1] = intr_info;
4604 vcpu->run->internal.data[2] = error_code;
4608 if (is_page_fault(intr_info)) {
4609 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4610 /* EPT won't cause page fault directly */
4611 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4612 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4615 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4617 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4618 return handle_rmode_exception(vcpu, ex_no, error_code);
4622 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4625 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4626 if (!(vcpu->guest_debug &
4627 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4628 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4629 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4630 if (is_icebp(intr_info))
4631 WARN_ON(!skip_emulated_instruction(vcpu));
4633 kvm_queue_exception(vcpu, DB_VECTOR);
4636 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4637 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4641 * Update instruction length as we may reinject #BP from
4642 * user space while in guest debugging mode. Reading it for
4643 * #DB as well causes no harm, it is not used in that case.
4645 vmx->vcpu.arch.event_exit_inst_len =
4646 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4647 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4648 rip = kvm_rip_read(vcpu);
4649 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4650 kvm_run->debug.arch.exception = ex_no;
4653 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4654 kvm_run->ex.exception = ex_no;
4655 kvm_run->ex.error_code = error_code;
4661 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4663 ++vcpu->stat.irq_exits;
4667 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4669 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4670 vcpu->mmio_needed = 0;
4674 static int handle_io(struct kvm_vcpu *vcpu)
4676 unsigned long exit_qualification;
4677 int size, in, string;
4680 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4681 string = (exit_qualification & 16) != 0;
4683 ++vcpu->stat.io_exits;
4686 return kvm_emulate_instruction(vcpu, 0);
4688 port = exit_qualification >> 16;
4689 size = (exit_qualification & 7) + 1;
4690 in = (exit_qualification & 8) != 0;
4692 return kvm_fast_pio(vcpu, size, port, in);
4696 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4699 * Patch in the VMCALL instruction:
4701 hypercall[0] = 0x0f;
4702 hypercall[1] = 0x01;
4703 hypercall[2] = 0xc1;
4706 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4707 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4709 if (is_guest_mode(vcpu)) {
4710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4711 unsigned long orig_val = val;
4714 * We get here when L2 changed cr0 in a way that did not change
4715 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4716 * but did change L0 shadowed bits. So we first calculate the
4717 * effective cr0 value that L1 would like to write into the
4718 * hardware. It consists of the L2-owned bits from the new
4719 * value combined with the L1-owned bits from L1's guest_cr0.
4721 val = (val & ~vmcs12->cr0_guest_host_mask) |
4722 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4724 if (!nested_guest_cr0_valid(vcpu, val))
4727 if (kvm_set_cr0(vcpu, val))
4729 vmcs_writel(CR0_READ_SHADOW, orig_val);
4732 if (to_vmx(vcpu)->nested.vmxon &&
4733 !nested_host_cr0_valid(vcpu, val))
4736 return kvm_set_cr0(vcpu, val);
4740 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4742 if (is_guest_mode(vcpu)) {
4743 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4744 unsigned long orig_val = val;
4746 /* analogously to handle_set_cr0 */
4747 val = (val & ~vmcs12->cr4_guest_host_mask) |
4748 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4749 if (kvm_set_cr4(vcpu, val))
4751 vmcs_writel(CR4_READ_SHADOW, orig_val);
4754 return kvm_set_cr4(vcpu, val);
4757 static int handle_desc(struct kvm_vcpu *vcpu)
4759 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4760 return kvm_emulate_instruction(vcpu, 0);
4763 static int handle_cr(struct kvm_vcpu *vcpu)
4765 unsigned long exit_qualification, val;
4771 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4772 cr = exit_qualification & 15;
4773 reg = (exit_qualification >> 8) & 15;
4774 switch ((exit_qualification >> 4) & 3) {
4775 case 0: /* mov to cr */
4776 val = kvm_register_readl(vcpu, reg);
4777 trace_kvm_cr_write(cr, val);
4780 err = handle_set_cr0(vcpu, val);
4781 return kvm_complete_insn_gp(vcpu, err);
4783 WARN_ON_ONCE(enable_unrestricted_guest);
4784 err = kvm_set_cr3(vcpu, val);
4785 return kvm_complete_insn_gp(vcpu, err);
4787 err = handle_set_cr4(vcpu, val);
4788 return kvm_complete_insn_gp(vcpu, err);
4790 u8 cr8_prev = kvm_get_cr8(vcpu);
4792 err = kvm_set_cr8(vcpu, cr8);
4793 ret = kvm_complete_insn_gp(vcpu, err);
4794 if (lapic_in_kernel(vcpu))
4796 if (cr8_prev <= cr8)
4799 * TODO: we might be squashing a
4800 * KVM_GUESTDBG_SINGLESTEP-triggered
4801 * KVM_EXIT_DEBUG here.
4803 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4809 WARN_ONCE(1, "Guest should always own CR0.TS");
4810 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4811 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4812 return kvm_skip_emulated_instruction(vcpu);
4813 case 1: /*mov from cr*/
4816 WARN_ON_ONCE(enable_unrestricted_guest);
4817 val = kvm_read_cr3(vcpu);
4818 kvm_register_write(vcpu, reg, val);
4819 trace_kvm_cr_read(cr, val);
4820 return kvm_skip_emulated_instruction(vcpu);
4822 val = kvm_get_cr8(vcpu);
4823 kvm_register_write(vcpu, reg, val);
4824 trace_kvm_cr_read(cr, val);
4825 return kvm_skip_emulated_instruction(vcpu);
4829 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4830 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4831 kvm_lmsw(vcpu, val);
4833 return kvm_skip_emulated_instruction(vcpu);
4837 vcpu->run->exit_reason = 0;
4838 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4839 (int)(exit_qualification >> 4) & 3, cr);
4843 static int handle_dr(struct kvm_vcpu *vcpu)
4845 unsigned long exit_qualification;
4848 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4849 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4851 /* First, if DR does not exist, trigger UD */
4852 if (!kvm_require_dr(vcpu, dr))
4855 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4856 if (!kvm_require_cpl(vcpu, 0))
4858 dr7 = vmcs_readl(GUEST_DR7);
4861 * As the vm-exit takes precedence over the debug trap, we
4862 * need to emulate the latter, either for the host or the
4863 * guest debugging itself.
4865 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4866 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4867 vcpu->run->debug.arch.dr7 = dr7;
4868 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4869 vcpu->run->debug.arch.exception = DB_VECTOR;
4870 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4873 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4874 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4875 kvm_queue_exception(vcpu, DB_VECTOR);
4880 if (vcpu->guest_debug == 0) {
4881 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4884 * No more DR vmexits; force a reload of the debug registers
4885 * and reenter on this instruction. The next vmexit will
4886 * retrieve the full state of the debug registers.
4888 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4892 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4893 if (exit_qualification & TYPE_MOV_FROM_DR) {
4896 if (kvm_get_dr(vcpu, dr, &val))
4898 kvm_register_write(vcpu, reg, val);
4900 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4903 return kvm_skip_emulated_instruction(vcpu);
4906 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4908 return vcpu->arch.dr6;
4911 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4915 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4917 get_debugreg(vcpu->arch.db[0], 0);
4918 get_debugreg(vcpu->arch.db[1], 1);
4919 get_debugreg(vcpu->arch.db[2], 2);
4920 get_debugreg(vcpu->arch.db[3], 3);
4921 get_debugreg(vcpu->arch.dr6, 6);
4922 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4924 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4925 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4928 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4930 vmcs_writel(GUEST_DR7, val);
4933 static int handle_cpuid(struct kvm_vcpu *vcpu)
4935 return kvm_emulate_cpuid(vcpu);
4938 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4940 return kvm_emulate_rdmsr(vcpu);
4943 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4945 return kvm_emulate_wrmsr(vcpu);
4948 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4950 kvm_apic_update_ppr(vcpu);
4954 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4956 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4958 kvm_make_request(KVM_REQ_EVENT, vcpu);
4960 ++vcpu->stat.irq_window_exits;
4964 static int handle_halt(struct kvm_vcpu *vcpu)
4966 return kvm_emulate_halt(vcpu);
4969 static int handle_vmcall(struct kvm_vcpu *vcpu)
4971 return kvm_emulate_hypercall(vcpu);
4974 static int handle_invd(struct kvm_vcpu *vcpu)
4976 return kvm_emulate_instruction(vcpu, 0);
4979 static int handle_invlpg(struct kvm_vcpu *vcpu)
4981 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4983 kvm_mmu_invlpg(vcpu, exit_qualification);
4984 return kvm_skip_emulated_instruction(vcpu);
4987 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4991 err = kvm_rdpmc(vcpu);
4992 return kvm_complete_insn_gp(vcpu, err);
4995 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4997 return kvm_emulate_wbinvd(vcpu);
5000 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5002 u64 new_bv = kvm_read_edx_eax(vcpu);
5003 u32 index = kvm_rcx_read(vcpu);
5005 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5006 return kvm_skip_emulated_instruction(vcpu);
5010 static int handle_xsaves(struct kvm_vcpu *vcpu)
5012 kvm_skip_emulated_instruction(vcpu);
5013 WARN(1, "this should never happen\n");
5017 static int handle_xrstors(struct kvm_vcpu *vcpu)
5019 kvm_skip_emulated_instruction(vcpu);
5020 WARN(1, "this should never happen\n");
5024 static int handle_apic_access(struct kvm_vcpu *vcpu)
5026 if (likely(fasteoi)) {
5027 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5028 int access_type, offset;
5030 access_type = exit_qualification & APIC_ACCESS_TYPE;
5031 offset = exit_qualification & APIC_ACCESS_OFFSET;
5033 * Sane guest uses MOV to write EOI, with written value
5034 * not cared. So make a short-circuit here by avoiding
5035 * heavy instruction emulation.
5037 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5038 (offset == APIC_EOI)) {
5039 kvm_lapic_set_eoi(vcpu);
5040 return kvm_skip_emulated_instruction(vcpu);
5043 return kvm_emulate_instruction(vcpu, 0);
5046 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5048 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5049 int vector = exit_qualification & 0xff;
5051 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5052 kvm_apic_set_eoi_accelerated(vcpu, vector);
5056 static int handle_apic_write(struct kvm_vcpu *vcpu)
5058 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5059 u32 offset = exit_qualification & 0xfff;
5061 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5062 kvm_apic_write_nodecode(vcpu, offset);
5066 static int handle_task_switch(struct kvm_vcpu *vcpu)
5068 struct vcpu_vmx *vmx = to_vmx(vcpu);
5069 unsigned long exit_qualification;
5070 bool has_error_code = false;
5073 int reason, type, idt_v, idt_index;
5075 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5076 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5077 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5079 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5081 reason = (u32)exit_qualification >> 30;
5082 if (reason == TASK_SWITCH_GATE && idt_v) {
5084 case INTR_TYPE_NMI_INTR:
5085 vcpu->arch.nmi_injected = false;
5086 vmx_set_nmi_mask(vcpu, true);
5088 case INTR_TYPE_EXT_INTR:
5089 case INTR_TYPE_SOFT_INTR:
5090 kvm_clear_interrupt_queue(vcpu);
5092 case INTR_TYPE_HARD_EXCEPTION:
5093 if (vmx->idt_vectoring_info &
5094 VECTORING_INFO_DELIVER_CODE_MASK) {
5095 has_error_code = true;
5097 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5100 case INTR_TYPE_SOFT_EXCEPTION:
5101 kvm_clear_exception_queue(vcpu);
5107 tss_selector = exit_qualification;
5109 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5110 type != INTR_TYPE_EXT_INTR &&
5111 type != INTR_TYPE_NMI_INTR))
5112 WARN_ON(!skip_emulated_instruction(vcpu));
5115 * TODO: What about debug traps on tss switch?
5116 * Are we supposed to inject them and update dr6?
5118 return kvm_task_switch(vcpu, tss_selector,
5119 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5120 reason, has_error_code, error_code);
5123 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5125 unsigned long exit_qualification;
5129 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5132 * EPT violation happened while executing iret from NMI,
5133 * "blocked by NMI" bit has to be set before next VM entry.
5134 * There are errata that may cause this bit to not be set:
5137 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5139 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5140 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5142 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5143 trace_kvm_page_fault(gpa, exit_qualification);
5145 /* Is it a read fault? */
5146 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5147 ? PFERR_USER_MASK : 0;
5148 /* Is it a write fault? */
5149 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5150 ? PFERR_WRITE_MASK : 0;
5151 /* Is it a fetch fault? */
5152 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5153 ? PFERR_FETCH_MASK : 0;
5154 /* ept page table entry is present? */
5155 error_code |= (exit_qualification &
5156 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5157 EPT_VIOLATION_EXECUTABLE))
5158 ? PFERR_PRESENT_MASK : 0;
5160 error_code |= (exit_qualification & 0x100) != 0 ?
5161 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5163 vcpu->arch.exit_qualification = exit_qualification;
5164 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5167 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5172 * A nested guest cannot optimize MMIO vmexits, because we have an
5173 * nGPA here instead of the required GPA.
5175 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5176 if (!is_guest_mode(vcpu) &&
5177 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5178 trace_kvm_fast_mmio(gpa);
5179 return kvm_skip_emulated_instruction(vcpu);
5182 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5185 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5187 WARN_ON_ONCE(!enable_vnmi);
5188 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5189 ++vcpu->stat.nmi_window_exits;
5190 kvm_make_request(KVM_REQ_EVENT, vcpu);
5195 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5197 struct vcpu_vmx *vmx = to_vmx(vcpu);
5198 bool intr_window_requested;
5199 unsigned count = 130;
5202 * We should never reach the point where we are emulating L2
5203 * due to invalid guest state as that means we incorrectly
5204 * allowed a nested VMEntry with an invalid vmcs12.
5206 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5208 intr_window_requested = exec_controls_get(vmx) &
5209 CPU_BASED_VIRTUAL_INTR_PENDING;
5211 while (vmx->emulation_required && count-- != 0) {
5212 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5213 return handle_interrupt_window(&vmx->vcpu);
5215 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5218 if (!kvm_emulate_instruction(vcpu, 0))
5221 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5222 vcpu->arch.exception.pending) {
5223 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5224 vcpu->run->internal.suberror =
5225 KVM_INTERNAL_ERROR_EMULATION;
5226 vcpu->run->internal.ndata = 0;
5230 if (vcpu->arch.halt_request) {
5231 vcpu->arch.halt_request = 0;
5232 return kvm_vcpu_halt(vcpu);
5236 * Note, return 1 and not 0, vcpu_run() is responsible for
5237 * morphing the pending signal into the proper return code.
5239 if (signal_pending(current))
5249 static void grow_ple_window(struct kvm_vcpu *vcpu)
5251 struct vcpu_vmx *vmx = to_vmx(vcpu);
5252 unsigned int old = vmx->ple_window;
5254 vmx->ple_window = __grow_ple_window(old, ple_window,
5258 if (vmx->ple_window != old) {
5259 vmx->ple_window_dirty = true;
5260 trace_kvm_ple_window_update(vcpu->vcpu_id,
5261 vmx->ple_window, old);
5265 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5267 struct vcpu_vmx *vmx = to_vmx(vcpu);
5268 unsigned int old = vmx->ple_window;
5270 vmx->ple_window = __shrink_ple_window(old, ple_window,
5274 if (vmx->ple_window != old) {
5275 vmx->ple_window_dirty = true;
5276 trace_kvm_ple_window_update(vcpu->vcpu_id,
5277 vmx->ple_window, old);
5282 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5284 static void wakeup_handler(void)
5286 struct kvm_vcpu *vcpu;
5287 int cpu = smp_processor_id();
5289 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5290 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5291 blocked_vcpu_list) {
5292 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5294 if (pi_test_on(pi_desc) == 1)
5295 kvm_vcpu_kick(vcpu);
5297 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5300 static void vmx_enable_tdp(void)
5302 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5303 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5304 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5305 0ull, VMX_EPT_EXECUTABLE_MASK,
5306 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5307 VMX_EPT_RWX_MASK, 0ull);
5309 ept_set_mmio_spte_mask();
5314 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5315 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5317 static int handle_pause(struct kvm_vcpu *vcpu)
5319 if (!kvm_pause_in_guest(vcpu->kvm))
5320 grow_ple_window(vcpu);
5323 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5324 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5325 * never set PAUSE_EXITING and just set PLE if supported,
5326 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5328 kvm_vcpu_on_spin(vcpu, true);
5329 return kvm_skip_emulated_instruction(vcpu);
5332 static int handle_nop(struct kvm_vcpu *vcpu)
5334 return kvm_skip_emulated_instruction(vcpu);
5337 static int handle_mwait(struct kvm_vcpu *vcpu)
5339 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5340 return handle_nop(vcpu);
5343 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5345 kvm_queue_exception(vcpu, UD_VECTOR);
5349 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5354 static int handle_monitor(struct kvm_vcpu *vcpu)
5356 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5357 return handle_nop(vcpu);
5360 static int handle_invpcid(struct kvm_vcpu *vcpu)
5362 u32 vmx_instruction_info;
5366 struct x86_exception e;
5368 unsigned long roots_to_free = 0;
5374 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5375 kvm_queue_exception(vcpu, UD_VECTOR);
5379 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5380 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5383 kvm_inject_gp(vcpu, 0);
5387 /* According to the Intel instruction reference, the memory operand
5388 * is read even if it isn't needed (e.g., for type==all)
5390 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5391 vmx_instruction_info, false,
5392 sizeof(operand), &gva))
5395 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5396 kvm_inject_page_fault(vcpu, &e);
5400 if (operand.pcid >> 12 != 0) {
5401 kvm_inject_gp(vcpu, 0);
5405 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5408 case INVPCID_TYPE_INDIV_ADDR:
5409 if ((!pcid_enabled && (operand.pcid != 0)) ||
5410 is_noncanonical_address(operand.gla, vcpu)) {
5411 kvm_inject_gp(vcpu, 0);
5414 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5415 return kvm_skip_emulated_instruction(vcpu);
5417 case INVPCID_TYPE_SINGLE_CTXT:
5418 if (!pcid_enabled && (operand.pcid != 0)) {
5419 kvm_inject_gp(vcpu, 0);
5423 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5424 kvm_mmu_sync_roots(vcpu);
5425 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5428 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5429 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5431 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5433 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5435 * If neither the current cr3 nor any of the prev_roots use the
5436 * given PCID, then nothing needs to be done here because a
5437 * resync will happen anyway before switching to any other CR3.
5440 return kvm_skip_emulated_instruction(vcpu);
5442 case INVPCID_TYPE_ALL_NON_GLOBAL:
5444 * Currently, KVM doesn't mark global entries in the shadow
5445 * page tables, so a non-global flush just degenerates to a
5446 * global flush. If needed, we could optimize this later by
5447 * keeping track of global entries in shadow page tables.
5451 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5452 kvm_mmu_unload(vcpu);
5453 return kvm_skip_emulated_instruction(vcpu);
5456 BUG(); /* We have already checked above that type <= 3 */
5460 static int handle_pml_full(struct kvm_vcpu *vcpu)
5462 unsigned long exit_qualification;
5464 trace_kvm_pml_full(vcpu->vcpu_id);
5466 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5469 * PML buffer FULL happened while executing iret from NMI,
5470 * "blocked by NMI" bit has to be set before next VM entry.
5472 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5474 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5475 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5476 GUEST_INTR_STATE_NMI);
5479 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5480 * here.., and there's no userspace involvement needed for PML.
5485 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5487 struct vcpu_vmx *vmx = to_vmx(vcpu);
5489 if (!vmx->req_immediate_exit &&
5490 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5491 kvm_lapic_expired_hv_timer(vcpu);
5497 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5498 * are overwritten by nested_vmx_setup() when nested=1.
5500 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5502 kvm_queue_exception(vcpu, UD_VECTOR);
5506 static int handle_encls(struct kvm_vcpu *vcpu)
5509 * SGX virtualization is not yet supported. There is no software
5510 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5511 * to prevent the guest from executing ENCLS.
5513 kvm_queue_exception(vcpu, UD_VECTOR);
5518 * The exit handlers return 1 if the exit was handled fully and guest execution
5519 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5520 * to be done to userspace and return 0.
5522 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5523 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5524 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5525 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5526 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5527 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5528 [EXIT_REASON_CR_ACCESS] = handle_cr,
5529 [EXIT_REASON_DR_ACCESS] = handle_dr,
5530 [EXIT_REASON_CPUID] = handle_cpuid,
5531 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5532 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5533 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5534 [EXIT_REASON_HLT] = handle_halt,
5535 [EXIT_REASON_INVD] = handle_invd,
5536 [EXIT_REASON_INVLPG] = handle_invlpg,
5537 [EXIT_REASON_RDPMC] = handle_rdpmc,
5538 [EXIT_REASON_VMCALL] = handle_vmcall,
5539 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5540 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5541 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5542 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5543 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5544 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5545 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5546 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5547 [EXIT_REASON_VMON] = handle_vmx_instruction,
5548 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5549 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5550 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5551 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5552 [EXIT_REASON_WBINVD] = handle_wbinvd,
5553 [EXIT_REASON_XSETBV] = handle_xsetbv,
5554 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5555 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5556 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5557 [EXIT_REASON_LDTR_TR] = handle_desc,
5558 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5559 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5560 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5561 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5562 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5563 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5564 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5565 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5566 [EXIT_REASON_RDRAND] = handle_invalid_op,
5567 [EXIT_REASON_RDSEED] = handle_invalid_op,
5568 [EXIT_REASON_XSAVES] = handle_xsaves,
5569 [EXIT_REASON_XRSTORS] = handle_xrstors,
5570 [EXIT_REASON_PML_FULL] = handle_pml_full,
5571 [EXIT_REASON_INVPCID] = handle_invpcid,
5572 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5573 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5574 [EXIT_REASON_ENCLS] = handle_encls,
5577 static const int kvm_vmx_max_exit_handlers =
5578 ARRAY_SIZE(kvm_vmx_exit_handlers);
5580 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5582 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5583 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5586 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5589 __free_page(vmx->pml_pg);
5594 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5596 struct vcpu_vmx *vmx = to_vmx(vcpu);
5600 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5602 /* Do nothing if PML buffer is empty */
5603 if (pml_idx == (PML_ENTITY_NUM - 1))
5606 /* PML index always points to next available PML buffer entity */
5607 if (pml_idx >= PML_ENTITY_NUM)
5612 pml_buf = page_address(vmx->pml_pg);
5613 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5616 gpa = pml_buf[pml_idx];
5617 WARN_ON(gpa & (PAGE_SIZE - 1));
5618 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5621 /* reset PML index */
5622 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5626 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5627 * Called before reporting dirty_bitmap to userspace.
5629 static void kvm_flush_pml_buffers(struct kvm *kvm)
5632 struct kvm_vcpu *vcpu;
5634 * We only need to kick vcpu out of guest mode here, as PML buffer
5635 * is flushed at beginning of all VMEXITs, and it's obvious that only
5636 * vcpus running in guest are possible to have unflushed GPAs in PML
5639 kvm_for_each_vcpu(i, vcpu, kvm)
5640 kvm_vcpu_kick(vcpu);
5643 static void vmx_dump_sel(char *name, uint32_t sel)
5645 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5646 name, vmcs_read16(sel),
5647 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5648 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5649 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5652 static void vmx_dump_dtsel(char *name, uint32_t limit)
5654 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5655 name, vmcs_read32(limit),
5656 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5659 void dump_vmcs(void)
5661 u32 vmentry_ctl, vmexit_ctl;
5662 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5667 if (!dump_invalid_vmcs) {
5668 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5672 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5673 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5674 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5675 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5676 cr4 = vmcs_readl(GUEST_CR4);
5677 efer = vmcs_read64(GUEST_IA32_EFER);
5678 secondary_exec_control = 0;
5679 if (cpu_has_secondary_exec_ctrls())
5680 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5682 pr_err("*** Guest State ***\n");
5683 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5684 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5685 vmcs_readl(CR0_GUEST_HOST_MASK));
5686 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5687 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5688 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5689 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5690 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5692 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5693 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5694 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5695 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5697 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5698 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5699 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5700 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5701 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5702 vmcs_readl(GUEST_SYSENTER_ESP),
5703 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5704 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5705 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5706 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5707 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5708 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5709 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5710 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5711 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5712 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5713 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5714 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5715 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5716 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5717 efer, vmcs_read64(GUEST_IA32_PAT));
5718 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5719 vmcs_read64(GUEST_IA32_DEBUGCTL),
5720 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5721 if (cpu_has_load_perf_global_ctrl() &&
5722 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5723 pr_err("PerfGlobCtl = 0x%016llx\n",
5724 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5725 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5726 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5727 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5728 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5729 vmcs_read32(GUEST_ACTIVITY_STATE));
5730 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5731 pr_err("InterruptStatus = %04x\n",
5732 vmcs_read16(GUEST_INTR_STATUS));
5734 pr_err("*** Host State ***\n");
5735 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5736 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5737 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5738 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5739 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5740 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5741 vmcs_read16(HOST_TR_SELECTOR));
5742 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5743 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5744 vmcs_readl(HOST_TR_BASE));
5745 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5746 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5747 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5748 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5749 vmcs_readl(HOST_CR4));
5750 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5751 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5752 vmcs_read32(HOST_IA32_SYSENTER_CS),
5753 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5754 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5755 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5756 vmcs_read64(HOST_IA32_EFER),
5757 vmcs_read64(HOST_IA32_PAT));
5758 if (cpu_has_load_perf_global_ctrl() &&
5759 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5760 pr_err("PerfGlobCtl = 0x%016llx\n",
5761 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5763 pr_err("*** Control State ***\n");
5764 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5765 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5766 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5767 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5768 vmcs_read32(EXCEPTION_BITMAP),
5769 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5770 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5771 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5772 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5773 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5774 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5775 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5776 vmcs_read32(VM_EXIT_INTR_INFO),
5777 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5778 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5779 pr_err(" reason=%08x qualification=%016lx\n",
5780 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5781 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5782 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5783 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5784 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5785 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5786 pr_err("TSC Multiplier = 0x%016llx\n",
5787 vmcs_read64(TSC_MULTIPLIER));
5788 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5789 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5790 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5791 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5793 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5794 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5795 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5796 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5798 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5799 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5800 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5801 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5802 n = vmcs_read32(CR3_TARGET_COUNT);
5803 for (i = 0; i + 1 < n; i += 4)
5804 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5805 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5806 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5808 pr_err("CR3 target%u=%016lx\n",
5809 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5810 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5811 pr_err("PLE Gap=%08x Window=%08x\n",
5812 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5813 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5814 pr_err("Virtual processor ID = 0x%04x\n",
5815 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5819 * The guest has exited. See if we can fix it or if we need userspace
5822 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5824 struct vcpu_vmx *vmx = to_vmx(vcpu);
5825 u32 exit_reason = vmx->exit_reason;
5826 u32 vectoring_info = vmx->idt_vectoring_info;
5828 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5831 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5832 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5833 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5834 * mode as if vcpus is in root mode, the PML buffer must has been
5838 vmx_flush_pml_buffer(vcpu);
5840 /* If guest state is invalid, start emulating */
5841 if (vmx->emulation_required)
5842 return handle_invalid_guest_state(vcpu);
5844 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5845 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5847 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5849 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5850 vcpu->run->fail_entry.hardware_entry_failure_reason
5855 if (unlikely(vmx->fail)) {
5857 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5858 vcpu->run->fail_entry.hardware_entry_failure_reason
5859 = vmcs_read32(VM_INSTRUCTION_ERROR);
5865 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5866 * delivery event since it indicates guest is accessing MMIO.
5867 * The vm-exit can be triggered again after return to guest that
5868 * will cause infinite loop.
5870 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5871 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5872 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5873 exit_reason != EXIT_REASON_PML_FULL &&
5874 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5875 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5876 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5877 vcpu->run->internal.ndata = 3;
5878 vcpu->run->internal.data[0] = vectoring_info;
5879 vcpu->run->internal.data[1] = exit_reason;
5880 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5881 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5882 vcpu->run->internal.ndata++;
5883 vcpu->run->internal.data[3] =
5884 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5889 if (unlikely(!enable_vnmi &&
5890 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5891 if (vmx_interrupt_allowed(vcpu)) {
5892 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5893 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5894 vcpu->arch.nmi_pending) {
5896 * This CPU don't support us in finding the end of an
5897 * NMI-blocked window if the guest runs with IRQs
5898 * disabled. So we pull the trigger after 1 s of
5899 * futile waiting, but inform the user about this.
5901 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5902 "state on VCPU %d after 1 s timeout\n",
5903 __func__, vcpu->vcpu_id);
5904 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5908 if (exit_reason < kvm_vmx_max_exit_handlers
5909 && kvm_vmx_exit_handlers[exit_reason])
5910 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5912 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5915 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5916 vcpu->run->internal.suberror =
5917 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5918 vcpu->run->internal.ndata = 1;
5919 vcpu->run->internal.data[0] = exit_reason;
5925 * Software based L1D cache flush which is used when microcode providing
5926 * the cache control MSR is not loaded.
5928 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5929 * flush it is required to read in 64 KiB because the replacement algorithm
5930 * is not exactly LRU. This could be sized at runtime via topology
5931 * information but as all relevant affected CPUs have 32KiB L1D cache size
5932 * there is no point in doing so.
5934 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5936 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5939 * This code is only executed when the the flush mode is 'cond' or
5942 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5946 * Clear the per-vcpu flush bit, it gets set again
5947 * either from vcpu_run() or from one of the unsafe
5950 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5951 vcpu->arch.l1tf_flush_l1d = false;
5954 * Clear the per-cpu flush bit, it gets set again from
5955 * the interrupt handlers.
5957 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5958 kvm_clear_cpu_l1tf_flush_l1d();
5964 vcpu->stat.l1d_flush++;
5966 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5967 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5972 /* First ensure the pages are in the TLB */
5973 "xorl %%eax, %%eax\n"
5974 ".Lpopulate_tlb:\n\t"
5975 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5976 "addl $4096, %%eax\n\t"
5977 "cmpl %%eax, %[size]\n\t"
5978 "jne .Lpopulate_tlb\n\t"
5979 "xorl %%eax, %%eax\n\t"
5981 /* Now fill the cache */
5982 "xorl %%eax, %%eax\n"
5984 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5985 "addl $64, %%eax\n\t"
5986 "cmpl %%eax, %[size]\n\t"
5987 "jne .Lfill_cache\n\t"
5989 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5991 : "eax", "ebx", "ecx", "edx");
5994 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5996 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5998 if (is_guest_mode(vcpu) &&
5999 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6002 if (irr == -1 || tpr < irr) {
6003 vmcs_write32(TPR_THRESHOLD, 0);
6007 vmcs_write32(TPR_THRESHOLD, irr);
6010 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6012 struct vcpu_vmx *vmx = to_vmx(vcpu);
6013 u32 sec_exec_control;
6015 if (!lapic_in_kernel(vcpu))
6018 if (!flexpriority_enabled &&
6019 !cpu_has_vmx_virtualize_x2apic_mode())
6022 /* Postpone execution until vmcs01 is the current VMCS. */
6023 if (is_guest_mode(vcpu)) {
6024 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6028 sec_exec_control = secondary_exec_controls_get(vmx);
6029 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6030 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6032 switch (kvm_get_apic_mode(vcpu)) {
6033 case LAPIC_MODE_INVALID:
6034 WARN_ONCE(true, "Invalid local APIC state");
6035 case LAPIC_MODE_DISABLED:
6037 case LAPIC_MODE_XAPIC:
6038 if (flexpriority_enabled) {
6040 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6041 vmx_flush_tlb(vcpu, true);
6044 case LAPIC_MODE_X2APIC:
6045 if (cpu_has_vmx_virtualize_x2apic_mode())
6047 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6050 secondary_exec_controls_set(vmx, sec_exec_control);
6052 vmx_update_msr_bitmap(vcpu);
6055 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6057 if (!is_guest_mode(vcpu)) {
6058 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6059 vmx_flush_tlb(vcpu, true);
6063 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6071 status = vmcs_read16(GUEST_INTR_STATUS);
6073 if (max_isr != old) {
6075 status |= max_isr << 8;
6076 vmcs_write16(GUEST_INTR_STATUS, status);
6080 static void vmx_set_rvi(int vector)
6088 status = vmcs_read16(GUEST_INTR_STATUS);
6089 old = (u8)status & 0xff;
6090 if ((u8)vector != old) {
6092 status |= (u8)vector;
6093 vmcs_write16(GUEST_INTR_STATUS, status);
6097 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6100 * When running L2, updating RVI is only relevant when
6101 * vmcs12 virtual-interrupt-delivery enabled.
6102 * However, it can be enabled only when L1 also
6103 * intercepts external-interrupts and in that case
6104 * we should not update vmcs02 RVI but instead intercept
6105 * interrupt. Therefore, do nothing when running L2.
6107 if (!is_guest_mode(vcpu))
6108 vmx_set_rvi(max_irr);
6111 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6113 struct vcpu_vmx *vmx = to_vmx(vcpu);
6115 bool max_irr_updated;
6117 WARN_ON(!vcpu->arch.apicv_active);
6118 if (pi_test_on(&vmx->pi_desc)) {
6119 pi_clear_on(&vmx->pi_desc);
6121 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6122 * But on x86 this is just a compiler barrier anyway.
6124 smp_mb__after_atomic();
6126 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6129 * If we are running L2 and L1 has a new pending interrupt
6130 * which can be injected, we should re-evaluate
6131 * what should be done with this new L1 interrupt.
6132 * If L1 intercepts external-interrupts, we should
6133 * exit from L2 to L1. Otherwise, interrupt should be
6134 * delivered directly to L2.
6136 if (is_guest_mode(vcpu) && max_irr_updated) {
6137 if (nested_exit_on_intr(vcpu))
6138 kvm_vcpu_exiting_guest_mode(vcpu);
6140 kvm_make_request(KVM_REQ_EVENT, vcpu);
6143 max_irr = kvm_lapic_find_highest_irr(vcpu);
6145 vmx_hwapic_irr_update(vcpu, max_irr);
6149 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6151 return pi_test_on(vcpu_to_pi_desc(vcpu));
6154 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6156 if (!kvm_vcpu_apicv_active(vcpu))
6159 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6160 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6161 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6162 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6165 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6167 struct vcpu_vmx *vmx = to_vmx(vcpu);
6169 pi_clear_on(&vmx->pi_desc);
6170 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6173 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6175 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6177 /* if exit due to PF check for async PF */
6178 if (is_page_fault(vmx->exit_intr_info))
6179 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6181 /* Handle machine checks before interrupts are enabled */
6182 if (is_machine_check(vmx->exit_intr_info))
6183 kvm_machine_check();
6185 /* We need to handle NMIs before interrupts are enabled */
6186 if (is_nmi(vmx->exit_intr_info)) {
6187 kvm_before_interrupt(&vmx->vcpu);
6189 kvm_after_interrupt(&vmx->vcpu);
6193 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6195 unsigned int vector;
6196 unsigned long entry;
6197 #ifdef CONFIG_X86_64
6203 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6204 if (WARN_ONCE(!is_external_intr(intr_info),
6205 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6208 vector = intr_info & INTR_INFO_VECTOR_MASK;
6209 desc = (gate_desc *)host_idt_base + vector;
6210 entry = gate_offset(desc);
6212 kvm_before_interrupt(vcpu);
6215 #ifdef CONFIG_X86_64
6216 "mov %%" _ASM_SP ", %[sp]\n\t"
6217 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6222 __ASM_SIZE(push) " $%c[cs]\n\t"
6225 #ifdef CONFIG_X86_64
6230 THUNK_TARGET(entry),
6231 [ss]"i"(__KERNEL_DS),
6232 [cs]"i"(__KERNEL_CS)
6235 kvm_after_interrupt(vcpu);
6237 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6239 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6241 struct vcpu_vmx *vmx = to_vmx(vcpu);
6243 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6244 handle_external_interrupt_irqoff(vcpu);
6245 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6246 handle_exception_nmi_irqoff(vmx);
6249 static bool vmx_has_emulated_msr(int index)
6252 case MSR_IA32_SMBASE:
6254 * We cannot do SMM unless we can run the guest in big
6257 return enable_unrestricted_guest || emulate_invalid_guest_state;
6258 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6260 case MSR_AMD64_VIRT_SPEC_CTRL:
6261 /* This is AMD only. */
6268 static bool vmx_pt_supported(void)
6270 return pt_mode == PT_MODE_HOST_GUEST;
6273 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6278 bool idtv_info_valid;
6280 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6283 if (vmx->loaded_vmcs->nmi_known_unmasked)
6286 * Can't use vmx->exit_intr_info since we're not sure what
6287 * the exit reason is.
6289 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6290 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6291 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6293 * SDM 3: 27.7.1.2 (September 2008)
6294 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6295 * a guest IRET fault.
6296 * SDM 3: 23.2.2 (September 2008)
6297 * Bit 12 is undefined in any of the following cases:
6298 * If the VM exit sets the valid bit in the IDT-vectoring
6299 * information field.
6300 * If the VM exit is due to a double fault.
6302 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6303 vector != DF_VECTOR && !idtv_info_valid)
6304 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6305 GUEST_INTR_STATE_NMI);
6307 vmx->loaded_vmcs->nmi_known_unmasked =
6308 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6309 & GUEST_INTR_STATE_NMI);
6310 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6311 vmx->loaded_vmcs->vnmi_blocked_time +=
6312 ktime_to_ns(ktime_sub(ktime_get(),
6313 vmx->loaded_vmcs->entry_time));
6316 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6317 u32 idt_vectoring_info,
6318 int instr_len_field,
6319 int error_code_field)
6323 bool idtv_info_valid;
6325 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6327 vcpu->arch.nmi_injected = false;
6328 kvm_clear_exception_queue(vcpu);
6329 kvm_clear_interrupt_queue(vcpu);
6331 if (!idtv_info_valid)
6334 kvm_make_request(KVM_REQ_EVENT, vcpu);
6336 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6337 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6340 case INTR_TYPE_NMI_INTR:
6341 vcpu->arch.nmi_injected = true;
6343 * SDM 3: 27.7.1.2 (September 2008)
6344 * Clear bit "block by NMI" before VM entry if a NMI
6347 vmx_set_nmi_mask(vcpu, false);
6349 case INTR_TYPE_SOFT_EXCEPTION:
6350 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6352 case INTR_TYPE_HARD_EXCEPTION:
6353 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6354 u32 err = vmcs_read32(error_code_field);
6355 kvm_requeue_exception_e(vcpu, vector, err);
6357 kvm_requeue_exception(vcpu, vector);
6359 case INTR_TYPE_SOFT_INTR:
6360 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6362 case INTR_TYPE_EXT_INTR:
6363 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6370 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6372 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6373 VM_EXIT_INSTRUCTION_LEN,
6374 IDT_VECTORING_ERROR_CODE);
6377 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6379 __vmx_complete_interrupts(vcpu,
6380 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6381 VM_ENTRY_INSTRUCTION_LEN,
6382 VM_ENTRY_EXCEPTION_ERROR_CODE);
6384 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6387 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6390 struct perf_guest_switch_msr *msrs;
6392 msrs = perf_guest_get_msrs(&nr_msrs);
6397 for (i = 0; i < nr_msrs; i++)
6398 if (msrs[i].host == msrs[i].guest)
6399 clear_atomic_switch_msr(vmx, msrs[i].msr);
6401 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6402 msrs[i].host, false);
6405 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx)
6407 u32 host_umwait_control;
6409 if (!vmx_has_waitpkg(vmx))
6412 host_umwait_control = get_umwait_control_msr();
6414 if (vmx->msr_ia32_umwait_control != host_umwait_control)
6415 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
6416 vmx->msr_ia32_umwait_control,
6417 host_umwait_control, false);
6419 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
6422 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6424 struct vcpu_vmx *vmx = to_vmx(vcpu);
6428 if (vmx->req_immediate_exit) {
6429 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6430 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6431 } else if (vmx->hv_deadline_tsc != -1) {
6433 if (vmx->hv_deadline_tsc > tscl)
6434 /* set_hv_timer ensures the delta fits in 32-bits */
6435 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6436 cpu_preemption_timer_multi);
6440 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6441 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6442 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6443 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6444 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6448 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6450 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6451 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6452 vmcs_writel(HOST_RSP, host_rsp);
6456 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6458 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6460 struct vcpu_vmx *vmx = to_vmx(vcpu);
6461 unsigned long cr3, cr4;
6463 /* Record the guest's net vcpu time for enforced NMI injections. */
6464 if (unlikely(!enable_vnmi &&
6465 vmx->loaded_vmcs->soft_vnmi_blocked))
6466 vmx->loaded_vmcs->entry_time = ktime_get();
6468 /* Don't enter VMX if guest state is invalid, let the exit handler
6469 start emulation until we arrive back to a valid state */
6470 if (vmx->emulation_required)
6473 if (vmx->ple_window_dirty) {
6474 vmx->ple_window_dirty = false;
6475 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6478 if (vmx->nested.need_vmcs12_to_shadow_sync)
6479 nested_sync_vmcs12_to_shadow(vcpu);
6481 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6482 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6483 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6484 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6486 cr3 = __get_current_cr3_fast();
6487 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6488 vmcs_writel(HOST_CR3, cr3);
6489 vmx->loaded_vmcs->host_state.cr3 = cr3;
6492 cr4 = cr4_read_shadow();
6493 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6494 vmcs_writel(HOST_CR4, cr4);
6495 vmx->loaded_vmcs->host_state.cr4 = cr4;
6498 /* When single-stepping over STI and MOV SS, we must clear the
6499 * corresponding interruptibility bits in the guest state. Otherwise
6500 * vmentry fails as it then expects bit 14 (BS) in pending debug
6501 * exceptions being set, but that's not correct for the guest debugging
6503 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6504 vmx_set_interrupt_shadow(vcpu, 0);
6506 kvm_load_guest_xcr0(vcpu);
6508 if (static_cpu_has(X86_FEATURE_PKU) &&
6509 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6510 vcpu->arch.pkru != vmx->host_pkru)
6511 __write_pkru(vcpu->arch.pkru);
6513 pt_guest_enter(vmx);
6515 atomic_switch_perf_msrs(vmx);
6516 atomic_switch_umwait_control_msr(vmx);
6518 if (enable_preemption_timer)
6519 vmx_update_hv_timer(vcpu);
6521 if (lapic_in_kernel(vcpu) &&
6522 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6523 kvm_wait_lapic_expire(vcpu);
6526 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6527 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6528 * is no need to worry about the conditional branch over the wrmsr
6529 * being speculatively taken.
6531 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6533 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6534 if (static_branch_unlikely(&vmx_l1d_should_flush))
6535 vmx_l1d_flush(vcpu);
6536 else if (static_branch_unlikely(&mds_user_clear))
6537 mds_clear_cpu_buffers();
6539 if (vcpu->arch.cr2 != read_cr2())
6540 write_cr2(vcpu->arch.cr2);
6542 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6543 vmx->loaded_vmcs->launched);
6545 vcpu->arch.cr2 = read_cr2();
6548 * We do not use IBRS in the kernel. If this vCPU has used the
6549 * SPEC_CTRL MSR it may have left it on; save the value and
6550 * turn it off. This is much more efficient than blindly adding
6551 * it to the atomic save/restore list. Especially as the former
6552 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6554 * For non-nested case:
6555 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6559 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6562 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6563 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6565 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6567 /* All fields are clean at this point */
6568 if (static_branch_unlikely(&enable_evmcs))
6569 current_evmcs->hv_clean_fields |=
6570 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6572 if (static_branch_unlikely(&enable_evmcs))
6573 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6575 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6576 if (vmx->host_debugctlmsr)
6577 update_debugctlmsr(vmx->host_debugctlmsr);
6579 #ifndef CONFIG_X86_64
6581 * The sysexit path does not restore ds/es, so we must set them to
6582 * a reasonable value ourselves.
6584 * We can't defer this to vmx_prepare_switch_to_host() since that
6585 * function may be executed in interrupt context, which saves and
6586 * restore segments around it, nullifying its effect.
6588 loadsegment(ds, __USER_DS);
6589 loadsegment(es, __USER_DS);
6592 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6593 | (1 << VCPU_EXREG_RFLAGS)
6594 | (1 << VCPU_EXREG_PDPTR)
6595 | (1 << VCPU_EXREG_SEGMENTS)
6596 | (1 << VCPU_EXREG_CR3));
6597 vcpu->arch.regs_dirty = 0;
6602 * eager fpu is enabled if PKEY is supported and CR4 is switched
6603 * back on host, so it is safe to read guest PKRU from current
6606 if (static_cpu_has(X86_FEATURE_PKU) &&
6607 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6608 vcpu->arch.pkru = rdpkru();
6609 if (vcpu->arch.pkru != vmx->host_pkru)
6610 __write_pkru(vmx->host_pkru);
6613 kvm_put_guest_xcr0(vcpu);
6615 vmx->nested.nested_run_pending = 0;
6616 vmx->idt_vectoring_info = 0;
6618 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6619 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6620 kvm_machine_check();
6622 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6625 vmx->loaded_vmcs->launched = 1;
6626 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6628 vmx_recover_nmi_blocking(vmx);
6629 vmx_complete_interrupts(vmx);
6632 static struct kvm *vmx_vm_alloc(void)
6634 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6635 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6637 return &kvm_vmx->kvm;
6640 static void vmx_vm_free(struct kvm *kvm)
6642 kfree(kvm->arch.hyperv.hv_pa_pg);
6643 vfree(to_kvm_vmx(kvm));
6646 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6648 struct vcpu_vmx *vmx = to_vmx(vcpu);
6651 vmx_destroy_pml_buffer(vmx);
6652 free_vpid(vmx->vpid);
6653 nested_vmx_free_vcpu(vcpu);
6654 free_loaded_vmcs(vmx->loaded_vmcs);
6655 kfree(vmx->guest_msrs);
6656 kvm_vcpu_uninit(vcpu);
6657 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6658 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6659 kmem_cache_free(kvm_vcpu_cache, vmx);
6662 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6665 struct vcpu_vmx *vmx;
6666 unsigned long *msr_bitmap;
6669 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6670 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6672 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6674 return ERR_PTR(-ENOMEM);
6676 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6677 GFP_KERNEL_ACCOUNT);
6678 if (!vmx->vcpu.arch.user_fpu) {
6679 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6681 goto free_partial_vcpu;
6684 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6685 GFP_KERNEL_ACCOUNT);
6686 if (!vmx->vcpu.arch.guest_fpu) {
6687 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6692 vmx->vpid = allocate_vpid();
6694 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6701 * If PML is turned on, failure on enabling PML just results in failure
6702 * of creating the vcpu, therefore we can simplify PML logic (by
6703 * avoiding dealing with cases, such as enabling PML partially on vcpus
6704 * for the guest, etc.
6707 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6712 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6713 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6716 if (!vmx->guest_msrs)
6719 err = alloc_loaded_vmcs(&vmx->vmcs01);
6723 msr_bitmap = vmx->vmcs01.msr_bitmap;
6724 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6725 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6726 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6727 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6728 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6729 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6730 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6731 if (kvm_cstate_in_guest(kvm)) {
6732 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6733 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6734 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6735 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6737 vmx->msr_bitmap_mode = 0;
6739 vmx->loaded_vmcs = &vmx->vmcs01;
6741 vmx_vcpu_load(&vmx->vcpu, cpu);
6742 vmx->vcpu.cpu = cpu;
6743 vmx_vcpu_setup(vmx);
6744 vmx_vcpu_put(&vmx->vcpu);
6746 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6747 err = alloc_apic_access_page(kvm);
6752 if (enable_ept && !enable_unrestricted_guest) {
6753 err = init_rmode_identity_map(kvm);
6759 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6761 kvm_vcpu_apicv_active(&vmx->vcpu));
6763 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6765 vmx->nested.posted_intr_nv = -1;
6766 vmx->nested.current_vmptr = -1ull;
6768 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6771 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6772 * or POSTED_INTR_WAKEUP_VECTOR.
6774 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6775 vmx->pi_desc.sn = 1;
6777 vmx->ept_pointer = INVALID_PAGE;
6782 free_loaded_vmcs(vmx->loaded_vmcs);
6784 kfree(vmx->guest_msrs);
6786 vmx_destroy_pml_buffer(vmx);
6788 kvm_vcpu_uninit(&vmx->vcpu);
6790 free_vpid(vmx->vpid);
6791 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6793 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6795 kmem_cache_free(kvm_vcpu_cache, vmx);
6796 return ERR_PTR(err);
6799 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6800 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6802 static int vmx_vm_init(struct kvm *kvm)
6804 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6807 kvm->arch.pause_in_guest = true;
6809 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6810 switch (l1tf_mitigation) {
6811 case L1TF_MITIGATION_OFF:
6812 case L1TF_MITIGATION_FLUSH_NOWARN:
6813 /* 'I explicitly don't care' is set */
6815 case L1TF_MITIGATION_FLUSH:
6816 case L1TF_MITIGATION_FLUSH_NOSMT:
6817 case L1TF_MITIGATION_FULL:
6819 * Warn upon starting the first VM in a potentially
6820 * insecure environment.
6822 if (sched_smt_active())
6823 pr_warn_once(L1TF_MSG_SMT);
6824 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6825 pr_warn_once(L1TF_MSG_L1D);
6827 case L1TF_MITIGATION_FULL_FORCE:
6828 /* Flush is enforced */
6835 static int __init vmx_check_processor_compat(void)
6837 struct vmcs_config vmcs_conf;
6838 struct vmx_capability vmx_cap;
6840 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6843 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6845 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6846 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6847 smp_processor_id());
6853 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6858 /* For VT-d and EPT combination
6859 * 1. MMIO: always map as UC
6861 * a. VT-d without snooping control feature: can't guarantee the
6862 * result, try to trust guest.
6863 * b. VT-d with snooping control feature: snooping control feature of
6864 * VT-d engine can guarantee the cache correctness. Just set it
6865 * to WB to keep consistent with host. So the same as item 3.
6866 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6867 * consistent with host MTRR
6870 cache = MTRR_TYPE_UNCACHABLE;
6874 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6875 ipat = VMX_EPT_IPAT_BIT;
6876 cache = MTRR_TYPE_WRBACK;
6880 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6881 ipat = VMX_EPT_IPAT_BIT;
6882 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6883 cache = MTRR_TYPE_WRBACK;
6885 cache = MTRR_TYPE_UNCACHABLE;
6889 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6892 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6895 static int vmx_get_lpage_level(void)
6897 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6898 return PT_DIRECTORY_LEVEL;
6900 /* For shadow and EPT supported 1GB page */
6901 return PT_PDPE_LEVEL;
6904 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6907 * These bits in the secondary execution controls field
6908 * are dynamic, the others are mostly based on the hypervisor
6909 * architecture and the guest's CPUID. Do not touch the
6913 SECONDARY_EXEC_SHADOW_VMCS |
6914 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6915 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6916 SECONDARY_EXEC_DESC;
6918 u32 new_ctl = vmx->secondary_exec_control;
6919 u32 cur_ctl = secondary_exec_controls_get(vmx);
6921 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6925 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6926 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6928 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6930 struct vcpu_vmx *vmx = to_vmx(vcpu);
6931 struct kvm_cpuid_entry2 *entry;
6933 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6934 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6936 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6937 if (entry && (entry->_reg & (_cpuid_mask))) \
6938 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6941 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6942 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6943 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6944 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6945 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6946 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6947 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6948 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6949 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6950 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6951 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6952 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6953 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6954 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6955 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6957 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6958 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6959 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6960 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6961 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6962 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
6964 #undef cr4_fixed1_update
6967 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6969 struct vcpu_vmx *vmx = to_vmx(vcpu);
6971 if (kvm_mpx_supported()) {
6972 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6975 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6976 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6978 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6979 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6984 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6986 struct vcpu_vmx *vmx = to_vmx(vcpu);
6987 struct kvm_cpuid_entry2 *best = NULL;
6990 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6991 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6994 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6995 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6996 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6997 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7000 /* Get the number of configurable Address Ranges for filtering */
7001 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7002 PT_CAP_num_address_ranges);
7004 /* Initialize and clear the no dependency bits */
7005 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7006 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7009 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7010 * will inject an #GP
7012 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7013 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7016 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7017 * PSBFreq can be set
7019 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7020 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7021 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7024 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7025 * MTCFreq can be set
7027 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7028 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7029 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7031 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7032 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7033 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7036 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7037 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7038 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7040 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7041 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7042 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7044 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7045 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7046 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7048 /* unmask address range configure area */
7049 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7050 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7053 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7055 struct vcpu_vmx *vmx = to_vmx(vcpu);
7057 if (cpu_has_secondary_exec_ctrls()) {
7058 vmx_compute_secondary_exec_control(vmx);
7059 vmcs_set_secondary_exec_control(vmx);
7062 if (nested_vmx_allowed(vcpu))
7063 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7064 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7066 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7067 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7069 if (nested_vmx_allowed(vcpu)) {
7070 nested_vmx_cr_fixed1_bits_update(vcpu);
7071 nested_vmx_entry_exit_ctls_update(vcpu);
7074 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7075 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7076 update_intel_pt_cfg(vcpu);
7079 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7081 if (func == 1 && nested)
7082 entry->ecx |= bit(X86_FEATURE_VMX);
7085 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7087 to_vmx(vcpu)->req_immediate_exit = true;
7090 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7091 struct x86_instruction_info *info,
7092 enum x86_intercept_stage stage)
7094 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7095 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7098 * RDPID causes #UD if disabled through secondary execution controls.
7099 * Because it is marked as EmulateOnUD, we need to intercept it here.
7101 if (info->intercept == x86_intercept_rdtscp &&
7102 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7103 ctxt->exception.vector = UD_VECTOR;
7104 ctxt->exception.error_code_valid = false;
7105 return X86EMUL_PROPAGATE_FAULT;
7108 /* TODO: check more intercepts... */
7109 return X86EMUL_CONTINUE;
7112 #ifdef CONFIG_X86_64
7113 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7114 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7115 u64 divisor, u64 *result)
7117 u64 low = a << shift, high = a >> (64 - shift);
7119 /* To avoid the overflow on divq */
7120 if (high >= divisor)
7123 /* Low hold the result, high hold rem which is discarded */
7124 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7125 "rm" (divisor), "0" (low), "1" (high));
7131 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7134 struct vcpu_vmx *vmx;
7135 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7136 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7138 if (kvm_mwait_in_guest(vcpu->kvm) ||
7139 kvm_can_post_timer_interrupt(vcpu))
7144 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7145 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7146 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7147 ktimer->timer_advance_ns);
7149 if (delta_tsc > lapic_timer_advance_cycles)
7150 delta_tsc -= lapic_timer_advance_cycles;
7154 /* Convert to host delta tsc if tsc scaling is enabled */
7155 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7156 delta_tsc && u64_shl_div_u64(delta_tsc,
7157 kvm_tsc_scaling_ratio_frac_bits,
7158 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7162 * If the delta tsc can't fit in the 32 bit after the multi shift,
7163 * we can't use the preemption timer.
7164 * It's possible that it fits on later vmentries, but checking
7165 * on every vmentry is costly so we just use an hrtimer.
7167 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7170 vmx->hv_deadline_tsc = tscl + delta_tsc;
7171 *expired = !delta_tsc;
7175 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7177 to_vmx(vcpu)->hv_deadline_tsc = -1;
7181 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7183 if (!kvm_pause_in_guest(vcpu->kvm))
7184 shrink_ple_window(vcpu);
7187 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7188 struct kvm_memory_slot *slot)
7190 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7191 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7194 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7195 struct kvm_memory_slot *slot)
7197 kvm_mmu_slot_set_dirty(kvm, slot);
7200 static void vmx_flush_log_dirty(struct kvm *kvm)
7202 kvm_flush_pml_buffers(kvm);
7205 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7207 struct vmcs12 *vmcs12;
7208 struct vcpu_vmx *vmx = to_vmx(vcpu);
7211 if (is_guest_mode(vcpu)) {
7212 WARN_ON_ONCE(vmx->nested.pml_full);
7215 * Check if PML is enabled for the nested guest.
7216 * Whether eptp bit 6 is set is already checked
7217 * as part of A/D emulation.
7219 vmcs12 = get_vmcs12(vcpu);
7220 if (!nested_cpu_has_pml(vmcs12))
7223 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7224 vmx->nested.pml_full = true;
7228 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7229 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7231 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7232 offset_in_page(dst), sizeof(gpa)))
7235 vmcs12->guest_pml_index--;
7241 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7242 struct kvm_memory_slot *memslot,
7243 gfn_t offset, unsigned long mask)
7245 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7248 static void __pi_post_block(struct kvm_vcpu *vcpu)
7250 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7251 struct pi_desc old, new;
7255 old.control = new.control = pi_desc->control;
7256 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7257 "Wakeup handler not enabled while the VCPU is blocked\n");
7259 dest = cpu_physical_id(vcpu->cpu);
7261 if (x2apic_enabled())
7264 new.ndst = (dest << 8) & 0xFF00;
7266 /* set 'NV' to 'notification vector' */
7267 new.nv = POSTED_INTR_VECTOR;
7268 } while (cmpxchg64(&pi_desc->control, old.control,
7269 new.control) != old.control);
7271 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7272 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7273 list_del(&vcpu->blocked_vcpu_list);
7274 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7275 vcpu->pre_pcpu = -1;
7280 * This routine does the following things for vCPU which is going
7281 * to be blocked if VT-d PI is enabled.
7282 * - Store the vCPU to the wakeup list, so when interrupts happen
7283 * we can find the right vCPU to wake up.
7284 * - Change the Posted-interrupt descriptor as below:
7285 * 'NDST' <-- vcpu->pre_pcpu
7286 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7287 * - If 'ON' is set during this process, which means at least one
7288 * interrupt is posted for this vCPU, we cannot block it, in
7289 * this case, return 1, otherwise, return 0.
7292 static int pi_pre_block(struct kvm_vcpu *vcpu)
7295 struct pi_desc old, new;
7296 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7298 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7299 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7300 !kvm_vcpu_apicv_active(vcpu))
7303 WARN_ON(irqs_disabled());
7304 local_irq_disable();
7305 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7306 vcpu->pre_pcpu = vcpu->cpu;
7307 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7308 list_add_tail(&vcpu->blocked_vcpu_list,
7309 &per_cpu(blocked_vcpu_on_cpu,
7311 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7315 old.control = new.control = pi_desc->control;
7317 WARN((pi_desc->sn == 1),
7318 "Warning: SN field of posted-interrupts "
7319 "is set before blocking\n");
7322 * Since vCPU can be preempted during this process,
7323 * vcpu->cpu could be different with pre_pcpu, we
7324 * need to set pre_pcpu as the destination of wakeup
7325 * notification event, then we can find the right vCPU
7326 * to wakeup in wakeup handler if interrupts happen
7327 * when the vCPU is in blocked state.
7329 dest = cpu_physical_id(vcpu->pre_pcpu);
7331 if (x2apic_enabled())
7334 new.ndst = (dest << 8) & 0xFF00;
7336 /* set 'NV' to 'wakeup vector' */
7337 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7338 } while (cmpxchg64(&pi_desc->control, old.control,
7339 new.control) != old.control);
7341 /* We should not block the vCPU if an interrupt is posted for it. */
7342 if (pi_test_on(pi_desc) == 1)
7343 __pi_post_block(vcpu);
7346 return (vcpu->pre_pcpu == -1);
7349 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7351 if (pi_pre_block(vcpu))
7354 if (kvm_lapic_hv_timer_in_use(vcpu))
7355 kvm_lapic_switch_to_sw_timer(vcpu);
7360 static void pi_post_block(struct kvm_vcpu *vcpu)
7362 if (vcpu->pre_pcpu == -1)
7365 WARN_ON(irqs_disabled());
7366 local_irq_disable();
7367 __pi_post_block(vcpu);
7371 static void vmx_post_block(struct kvm_vcpu *vcpu)
7373 if (kvm_x86_ops->set_hv_timer)
7374 kvm_lapic_switch_to_hv_timer(vcpu);
7376 pi_post_block(vcpu);
7380 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7383 * @host_irq: host irq of the interrupt
7384 * @guest_irq: gsi of the interrupt
7385 * @set: set or unset PI
7386 * returns 0 on success, < 0 on failure
7388 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7389 uint32_t guest_irq, bool set)
7391 struct kvm_kernel_irq_routing_entry *e;
7392 struct kvm_irq_routing_table *irq_rt;
7393 struct kvm_lapic_irq irq;
7394 struct kvm_vcpu *vcpu;
7395 struct vcpu_data vcpu_info;
7398 if (!kvm_arch_has_assigned_device(kvm) ||
7399 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7400 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7403 idx = srcu_read_lock(&kvm->irq_srcu);
7404 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7405 if (guest_irq >= irq_rt->nr_rt_entries ||
7406 hlist_empty(&irq_rt->map[guest_irq])) {
7407 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7408 guest_irq, irq_rt->nr_rt_entries);
7412 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7413 if (e->type != KVM_IRQ_ROUTING_MSI)
7416 * VT-d PI cannot support posting multicast/broadcast
7417 * interrupts to a vCPU, we still use interrupt remapping
7418 * for these kind of interrupts.
7420 * For lowest-priority interrupts, we only support
7421 * those with single CPU as the destination, e.g. user
7422 * configures the interrupts via /proc/irq or uses
7423 * irqbalance to make the interrupts single-CPU.
7425 * We will support full lowest-priority interrupt later.
7427 * In addition, we can only inject generic interrupts using
7428 * the PI mechanism, refuse to route others through it.
7431 kvm_set_msi_irq(kvm, e, &irq);
7432 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7433 !kvm_irq_is_postable(&irq)) {
7435 * Make sure the IRTE is in remapped mode if
7436 * we don't handle it in posted mode.
7438 ret = irq_set_vcpu_affinity(host_irq, NULL);
7441 "failed to back to remapped mode, irq: %u\n",
7449 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7450 vcpu_info.vector = irq.vector;
7452 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7453 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7456 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7458 ret = irq_set_vcpu_affinity(host_irq, NULL);
7461 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7469 srcu_read_unlock(&kvm->irq_srcu, idx);
7473 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7475 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7476 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7477 FEATURE_CONTROL_LMCE;
7479 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7480 ~FEATURE_CONTROL_LMCE;
7483 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7485 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7486 if (to_vmx(vcpu)->nested.nested_run_pending)
7491 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7493 struct vcpu_vmx *vmx = to_vmx(vcpu);
7495 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7496 if (vmx->nested.smm.guest_mode)
7497 nested_vmx_vmexit(vcpu, -1, 0, 0);
7499 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7500 vmx->nested.vmxon = false;
7501 vmx_clear_hlt(vcpu);
7505 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7507 struct vcpu_vmx *vmx = to_vmx(vcpu);
7510 if (vmx->nested.smm.vmxon) {
7511 vmx->nested.vmxon = true;
7512 vmx->nested.smm.vmxon = false;
7515 if (vmx->nested.smm.guest_mode) {
7516 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7520 vmx->nested.smm.guest_mode = false;
7525 static int enable_smi_window(struct kvm_vcpu *vcpu)
7530 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7535 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7537 return to_vmx(vcpu)->nested.vmxon;
7540 static __init int hardware_setup(void)
7542 unsigned long host_bndcfgs;
7546 rdmsrl_safe(MSR_EFER, &host_efer);
7549 host_idt_base = dt.address;
7551 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7552 kvm_define_shared_msr(i, vmx_msr_index[i]);
7554 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7557 if (boot_cpu_has(X86_FEATURE_NX))
7558 kvm_enable_efer_bits(EFER_NX);
7560 if (boot_cpu_has(X86_FEATURE_MPX)) {
7561 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7562 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7565 if (boot_cpu_has(X86_FEATURE_XSAVES))
7566 rdmsrl(MSR_IA32_XSS, host_xss);
7568 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7569 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7572 if (!cpu_has_vmx_ept() ||
7573 !cpu_has_vmx_ept_4levels() ||
7574 !cpu_has_vmx_ept_mt_wb() ||
7575 !cpu_has_vmx_invept_global())
7578 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7579 enable_ept_ad_bits = 0;
7581 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7582 enable_unrestricted_guest = 0;
7584 if (!cpu_has_vmx_flexpriority())
7585 flexpriority_enabled = 0;
7587 if (!cpu_has_virtual_nmis())
7591 * set_apic_access_page_addr() is used to reload apic access
7592 * page upon invalidation. No need to do anything if not
7593 * using the APIC_ACCESS_ADDR VMCS field.
7595 if (!flexpriority_enabled)
7596 kvm_x86_ops->set_apic_access_page_addr = NULL;
7598 if (!cpu_has_vmx_tpr_shadow())
7599 kvm_x86_ops->update_cr8_intercept = NULL;
7601 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7602 kvm_disable_largepages();
7604 #if IS_ENABLED(CONFIG_HYPERV)
7605 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7607 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7608 kvm_x86_ops->tlb_remote_flush_with_range =
7609 hv_remote_flush_tlb_with_range;
7613 if (!cpu_has_vmx_ple()) {
7616 ple_window_grow = 0;
7618 ple_window_shrink = 0;
7621 if (!cpu_has_vmx_apicv()) {
7623 kvm_x86_ops->sync_pir_to_irr = NULL;
7626 if (cpu_has_vmx_tsc_scaling()) {
7627 kvm_has_tsc_control = true;
7628 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7629 kvm_tsc_scaling_ratio_frac_bits = 48;
7632 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7640 * Only enable PML when hardware supports PML feature, and both EPT
7641 * and EPT A/D bit features are enabled -- PML depends on them to work.
7643 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7647 kvm_x86_ops->slot_enable_log_dirty = NULL;
7648 kvm_x86_ops->slot_disable_log_dirty = NULL;
7649 kvm_x86_ops->flush_log_dirty = NULL;
7650 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7653 if (!cpu_has_vmx_preemption_timer())
7654 enable_preemption_timer = false;
7656 if (enable_preemption_timer) {
7657 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7660 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7661 cpu_preemption_timer_multi =
7662 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7665 use_timer_freq = (u64)tsc_khz * 1000;
7666 use_timer_freq >>= cpu_preemption_timer_multi;
7669 * KVM "disables" the preemption timer by setting it to its max
7670 * value. Don't use the timer if it might cause spurious exits
7671 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7673 if (use_timer_freq > 0xffffffffu / 10)
7674 enable_preemption_timer = false;
7677 if (!enable_preemption_timer) {
7678 kvm_x86_ops->set_hv_timer = NULL;
7679 kvm_x86_ops->cancel_hv_timer = NULL;
7680 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7683 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7685 kvm_mce_cap_supported |= MCG_LMCE_P;
7687 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7689 if (!enable_ept || !cpu_has_vmx_intel_pt())
7690 pt_mode = PT_MODE_SYSTEM;
7693 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7694 vmx_capability.ept, enable_apicv);
7696 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7701 r = alloc_kvm_area();
7703 nested_vmx_hardware_unsetup();
7707 static __exit void hardware_unsetup(void)
7710 nested_vmx_hardware_unsetup();
7715 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7716 .cpu_has_kvm_support = cpu_has_kvm_support,
7717 .disabled_by_bios = vmx_disabled_by_bios,
7718 .hardware_setup = hardware_setup,
7719 .hardware_unsetup = hardware_unsetup,
7720 .check_processor_compatibility = vmx_check_processor_compat,
7721 .hardware_enable = hardware_enable,
7722 .hardware_disable = hardware_disable,
7723 .cpu_has_accelerated_tpr = report_flexpriority,
7724 .has_emulated_msr = vmx_has_emulated_msr,
7726 .vm_init = vmx_vm_init,
7727 .vm_alloc = vmx_vm_alloc,
7728 .vm_free = vmx_vm_free,
7730 .vcpu_create = vmx_create_vcpu,
7731 .vcpu_free = vmx_free_vcpu,
7732 .vcpu_reset = vmx_vcpu_reset,
7734 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7735 .vcpu_load = vmx_vcpu_load,
7736 .vcpu_put = vmx_vcpu_put,
7738 .update_bp_intercept = update_exception_bitmap,
7739 .get_msr_feature = vmx_get_msr_feature,
7740 .get_msr = vmx_get_msr,
7741 .set_msr = vmx_set_msr,
7742 .get_segment_base = vmx_get_segment_base,
7743 .get_segment = vmx_get_segment,
7744 .set_segment = vmx_set_segment,
7745 .get_cpl = vmx_get_cpl,
7746 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7747 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7748 .decache_cr3 = vmx_decache_cr3,
7749 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7750 .set_cr0 = vmx_set_cr0,
7751 .set_cr3 = vmx_set_cr3,
7752 .set_cr4 = vmx_set_cr4,
7753 .set_efer = vmx_set_efer,
7754 .get_idt = vmx_get_idt,
7755 .set_idt = vmx_set_idt,
7756 .get_gdt = vmx_get_gdt,
7757 .set_gdt = vmx_set_gdt,
7758 .get_dr6 = vmx_get_dr6,
7759 .set_dr6 = vmx_set_dr6,
7760 .set_dr7 = vmx_set_dr7,
7761 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7762 .cache_reg = vmx_cache_reg,
7763 .get_rflags = vmx_get_rflags,
7764 .set_rflags = vmx_set_rflags,
7766 .tlb_flush = vmx_flush_tlb,
7767 .tlb_flush_gva = vmx_flush_tlb_gva,
7769 .run = vmx_vcpu_run,
7770 .handle_exit = vmx_handle_exit,
7771 .skip_emulated_instruction = skip_emulated_instruction,
7772 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7773 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7774 .patch_hypercall = vmx_patch_hypercall,
7775 .set_irq = vmx_inject_irq,
7776 .set_nmi = vmx_inject_nmi,
7777 .queue_exception = vmx_queue_exception,
7778 .cancel_injection = vmx_cancel_injection,
7779 .interrupt_allowed = vmx_interrupt_allowed,
7780 .nmi_allowed = vmx_nmi_allowed,
7781 .get_nmi_mask = vmx_get_nmi_mask,
7782 .set_nmi_mask = vmx_set_nmi_mask,
7783 .enable_nmi_window = enable_nmi_window,
7784 .enable_irq_window = enable_irq_window,
7785 .update_cr8_intercept = update_cr8_intercept,
7786 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7787 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7788 .get_enable_apicv = vmx_get_enable_apicv,
7789 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7790 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7791 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7792 .hwapic_irr_update = vmx_hwapic_irr_update,
7793 .hwapic_isr_update = vmx_hwapic_isr_update,
7794 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7795 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7796 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7797 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7799 .set_tss_addr = vmx_set_tss_addr,
7800 .set_identity_map_addr = vmx_set_identity_map_addr,
7801 .get_tdp_level = get_ept_level,
7802 .get_mt_mask = vmx_get_mt_mask,
7804 .get_exit_info = vmx_get_exit_info,
7806 .get_lpage_level = vmx_get_lpage_level,
7808 .cpuid_update = vmx_cpuid_update,
7810 .rdtscp_supported = vmx_rdtscp_supported,
7811 .invpcid_supported = vmx_invpcid_supported,
7813 .set_supported_cpuid = vmx_set_supported_cpuid,
7815 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7817 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7818 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7820 .set_tdp_cr3 = vmx_set_cr3,
7822 .check_intercept = vmx_check_intercept,
7823 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7824 .mpx_supported = vmx_mpx_supported,
7825 .xsaves_supported = vmx_xsaves_supported,
7826 .umip_emulated = vmx_umip_emulated,
7827 .pt_supported = vmx_pt_supported,
7829 .request_immediate_exit = vmx_request_immediate_exit,
7831 .sched_in = vmx_sched_in,
7833 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7834 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7835 .flush_log_dirty = vmx_flush_log_dirty,
7836 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7837 .write_log_dirty = vmx_write_pml_buffer,
7839 .pre_block = vmx_pre_block,
7840 .post_block = vmx_post_block,
7842 .pmu_ops = &intel_pmu_ops,
7844 .update_pi_irte = vmx_update_pi_irte,
7846 #ifdef CONFIG_X86_64
7847 .set_hv_timer = vmx_set_hv_timer,
7848 .cancel_hv_timer = vmx_cancel_hv_timer,
7851 .setup_mce = vmx_setup_mce,
7853 .smi_allowed = vmx_smi_allowed,
7854 .pre_enter_smm = vmx_pre_enter_smm,
7855 .pre_leave_smm = vmx_pre_leave_smm,
7856 .enable_smi_window = enable_smi_window,
7858 .check_nested_events = NULL,
7859 .get_nested_state = NULL,
7860 .set_nested_state = NULL,
7861 .get_vmcs12_pages = NULL,
7862 .nested_enable_evmcs = NULL,
7863 .nested_get_evmcs_version = NULL,
7864 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7865 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7868 static void vmx_cleanup_l1d_flush(void)
7870 if (vmx_l1d_flush_pages) {
7871 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7872 vmx_l1d_flush_pages = NULL;
7874 /* Restore state so sysfs ignores VMX */
7875 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7878 static void vmx_exit(void)
7880 #ifdef CONFIG_KEXEC_CORE
7881 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7887 #if IS_ENABLED(CONFIG_HYPERV)
7888 if (static_branch_unlikely(&enable_evmcs)) {
7890 struct hv_vp_assist_page *vp_ap;
7892 * Reset everything to support using non-enlightened VMCS
7893 * access later (e.g. when we reload the module with
7894 * enlightened_vmcs=0)
7896 for_each_online_cpu(cpu) {
7897 vp_ap = hv_get_vp_assist_page(cpu);
7902 vp_ap->nested_control.features.directhypercall = 0;
7903 vp_ap->current_nested_vmcs = 0;
7904 vp_ap->enlighten_vmentry = 0;
7907 static_branch_disable(&enable_evmcs);
7910 vmx_cleanup_l1d_flush();
7912 module_exit(vmx_exit);
7914 static int __init vmx_init(void)
7918 #if IS_ENABLED(CONFIG_HYPERV)
7920 * Enlightened VMCS usage should be recommended and the host needs
7921 * to support eVMCS v1 or above. We can also disable eVMCS support
7922 * with module parameter.
7924 if (enlightened_vmcs &&
7925 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7926 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7927 KVM_EVMCS_VERSION) {
7930 /* Check that we have assist pages on all online CPUs */
7931 for_each_online_cpu(cpu) {
7932 if (!hv_get_vp_assist_page(cpu)) {
7933 enlightened_vmcs = false;
7938 if (enlightened_vmcs) {
7939 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7940 static_branch_enable(&enable_evmcs);
7943 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7944 vmx_x86_ops.enable_direct_tlbflush
7945 = hv_enable_direct_tlbflush;
7948 enlightened_vmcs = false;
7952 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7953 __alignof__(struct vcpu_vmx), THIS_MODULE);
7958 * Must be called after kvm_init() so enable_ept is properly set
7959 * up. Hand the parameter mitigation value in which was stored in
7960 * the pre module init parser. If no parameter was given, it will
7961 * contain 'auto' which will be turned into the default 'cond'
7964 if (boot_cpu_has(X86_BUG_L1TF)) {
7965 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7972 #ifdef CONFIG_KEXEC_CORE
7973 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7974 crash_vmclear_local_loaded_vmcss);
7976 vmx_check_vmcs12_offsets();
7980 module_init(vmx_init);