arch/x86/kvm/vmx/vmx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * Copyright (C) 2006 Qumranet, Inc.
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  */
  15
  16 #include <linux/frame.h>
  17 #include <linux/highmem.h>
  18 #include <linux/hrtimer.h>
  19 #include <linux/kernel.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/mod_devicetable.h>
  24 #include <linux/mm.h>
  25 #include <linux/sched.h>
  26 #include <linux/sched/smt.h>
  27 #include <linux/slab.h>
  28 #include <linux/tboot.h>
  29 #include <linux/trace_events.h>
  30
  31 #include <asm/apic.h>
  32 #include <asm/asm.h>
  33 #include <asm/cpu.h>
  34 #include <asm/debugreg.h>
  35 #include <asm/desc.h>
  36 #include <asm/fpu/internal.h>
  37 #include <asm/io.h>
  38 #include <asm/irq_remapping.h>
  39 #include <asm/kexec.h>
  40 #include <asm/perf_event.h>
  41 #include <asm/mce.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/mshyperv.h>
  44 #include <asm/spec-ctrl.h>
  45 #include <asm/virtext.h>
  46 #include <asm/vmx.h>
  47
  48 #include "capabilities.h"
  49 #include "cpuid.h"
  50 #include "evmcs.h"
  51 #include "irq.h"
  52 #include "kvm_cache_regs.h"
  53 #include "lapic.h"
  54 #include "mmu.h"
  55 #include "nested.h"
  56 #include "ops.h"
  57 #include "pmu.h"
  58 #include "trace.h"
  59 #include "vmcs.h"
  60 #include "vmcs12.h"
  61 #include "vmx.h"
  62 #include "x86.h"
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 static const struct x86_cpu_id vmx_cpu_id[] = {
  68         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  69         {}
  70 };
  71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  72
  73 bool __read_mostly enable_vpid = 1;
  74 module_param_named(vpid, enable_vpid, bool, 0444);
  75
  76 static bool __read_mostly enable_vnmi = 1;
  77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  78
  79 bool __read_mostly flexpriority_enabled = 1;
  80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  81
  82 bool __read_mostly enable_ept = 1;
  83 module_param_named(ept, enable_ept, bool, S_IRUGO);
  84
  85 bool __read_mostly enable_unrestricted_guest = 1;
  86 module_param_named(unrestricted_guest,
  87                         enable_unrestricted_guest, bool, S_IRUGO);
  88
  89 bool __read_mostly enable_ept_ad_bits = 1;
  90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  91
  92 static bool __read_mostly emulate_invalid_guest_state = true;
  93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  94
  95 static bool __read_mostly fasteoi = 1;
  96 module_param(fasteoi, bool, S_IRUGO);
  97
  98 static bool __read_mostly enable_apicv = 1;
  99 module_param(enable_apicv, bool, S_IRUGO);
 100
 101 /*
 102  * If nested=1, nested virtualization is supported, i.e., guests may use
 103  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 104  * use VMX instructions.
 105  */
 106 static bool __read_mostly nested = 1;
 107 module_param(nested, bool, S_IRUGO);
 108
 109 static u64 __read_mostly host_xss;
 110
 111 bool __read_mostly enable_pml = 1;
 112 module_param_named(pml, enable_pml, bool, S_IRUGO);
 113
 114 static bool __read_mostly dump_invalid_vmcs = 0;
 115 module_param(dump_invalid_vmcs, bool, 0644);
 116
 117 #define MSR_BITMAP_MODE_X2APIC          1
 118 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 119
 120 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 121
 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 123 static int __read_mostly cpu_preemption_timer_multi;
 124 static bool __read_mostly enable_preemption_timer = 1;
 125 #ifdef CONFIG_X86_64
 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 127 #endif
 128
 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 131 #define KVM_VM_CR0_ALWAYS_ON                            \
 132         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 133          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 134 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 135         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 136          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 137
 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 141
 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 143
 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
 145         RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
 146         RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
 147         RTIT_STATUS_BYTECNT))
 148
 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
 150         (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
 151
 152 /*
 153  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 154  * ple_gap:    upper bound on the amount of time between two successive
 155  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 156  *             According to test, this time is usually smaller than 128 cycles.
 157  * ple_window: upper bound on the amount of time a guest is allowed to execute
 158  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 159  *             less than 2^12 cycles
 160  * Time is measured based on a counter that runs at the same rate as the TSC,
 161  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 162  */
 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, uint, 0444);
 165
 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, uint, 0444);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, uint, 0444);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, uint, 0444);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, uint, 0444);
 180
 181 /* Default is SYSTEM mode, 1 for host-guest mode */
 182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
 183 module_param(pt_mode, int, S_IRUGO);
 184
 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 188
 189 /* Storage for pre module init parameter parsing */
 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 191
 192 static const struct {
 193         const char *option;
 194         bool for_parse;
 195 } vmentry_l1d_param[] = {
 196         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 197         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 198         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 199         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 200         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 201         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 202 };
 203
 204 #define L1D_CACHE_ORDER 4
 205 static void *vmx_l1d_flush_pages;
 206
 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 208 {
 209         struct page *page;
 210         unsigned int i;
 211
 212         if (!enable_ept) {
 213                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 214                 return 0;
 215         }
 216
 217         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 218                 u64 msr;
 219
 220                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 221                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 222                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 223                         return 0;
 224                 }
 225         }
 226
 227         /* If set to auto use the default l1tf mitigation method */
 228         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 229                 switch (l1tf_mitigation) {
 230                 case L1TF_MITIGATION_OFF:
 231                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 232                         break;
 233                 case L1TF_MITIGATION_FLUSH_NOWARN:
 234                 case L1TF_MITIGATION_FLUSH:
 235                 case L1TF_MITIGATION_FLUSH_NOSMT:
 236                         l1tf = VMENTER_L1D_FLUSH_COND;
 237                         break;
 238                 case L1TF_MITIGATION_FULL:
 239                 case L1TF_MITIGATION_FULL_FORCE:
 240                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 241                         break;
 242                 }
 243         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 244                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 245         }
 246
 247         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 248             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 249                 /*
 250                  * This allocation for vmx_l1d_flush_pages is not tied to a VM
 251                  * lifetime and so should not be charged to a memcg.
 252                  */
 253                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 254                 if (!page)
 255                         return -ENOMEM;
 256                 vmx_l1d_flush_pages = page_address(page);
 257
 258                 /*
 259                  * Initialize each page with a different pattern in
 260                  * order to protect against KSM in the nested
 261                  * virtualization case.
 262                  */
 263                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 264                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 265                                PAGE_SIZE);
 266                 }
 267         }
 268
 269         l1tf_vmx_mitigation = l1tf;
 270
 271         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 272                 static_branch_enable(&vmx_l1d_should_flush);
 273         else
 274                 static_branch_disable(&vmx_l1d_should_flush);
 275
 276         if (l1tf == VMENTER_L1D_FLUSH_COND)
 277                 static_branch_enable(&vmx_l1d_flush_cond);
 278         else
 279                 static_branch_disable(&vmx_l1d_flush_cond);
 280         return 0;
 281 }
 282
 283 static int vmentry_l1d_flush_parse(const char *s)
 284 {
 285         unsigned int i;
 286
 287         if (s) {
 288                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 289                         if (vmentry_l1d_param[i].for_parse &&
 290                             sysfs_streq(s, vmentry_l1d_param[i].option))
 291                                 return i;
 292                 }
 293         }
 294         return -EINVAL;
 295 }
 296
 297 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 298 {
 299         int l1tf, ret;
 300
 301         l1tf = vmentry_l1d_flush_parse(s);
 302         if (l1tf < 0)
 303                 return l1tf;
 304
 305         if (!boot_cpu_has(X86_BUG_L1TF))
 306                 return 0;
 307
 308         /*
 309          * Has vmx_init() run already? If not then this is the pre init
 310          * parameter parsing. In that case just store the value and let
 311          * vmx_init() do the proper setup after enable_ept has been
 312          * established.
 313          */
 314         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 315                 vmentry_l1d_flush_param = l1tf;
 316                 return 0;
 317         }
 318
 319         mutex_lock(&vmx_l1d_flush_mutex);
 320         ret = vmx_setup_l1d_flush(l1tf);
 321         mutex_unlock(&vmx_l1d_flush_mutex);
 322         return ret;
 323 }
 324
 325 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 326 {
 327         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 328                 return sprintf(s, "???\n");
 329
 330         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 331 }
 332
 333 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 334         .set = vmentry_l1d_flush_set,
 335         .get = vmentry_l1d_flush_get,
 336 };
 337 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 338
 339 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 340 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 341 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 342                                                           u32 msr, int type);
 343
 344 void vmx_vmexit(void);
 345
 346 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 347 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 348 /*
 349  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 350  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 351  */
 352 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 353
 354 /*
 355  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 356  * can find which vCPU should be waken up.
 357  */
 358 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 359 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 360
 361 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 362 static DEFINE_SPINLOCK(vmx_vpid_lock);
 363
 364 struct vmcs_config vmcs_config;
 365 struct vmx_capability vmx_capability;
 366
 367 #define VMX_SEGMENT_FIELD(seg)                                  \
 368         [VCPU_SREG_##seg] = {                                   \
 369                 .selector = GUEST_##seg##_SELECTOR,             \
 370                 .base = GUEST_##seg##_BASE,                     \
 371                 .limit = GUEST_##seg##_LIMIT,                   \
 372                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 373         }
 374
 375 static const struct kvm_vmx_segment_field {
 376         unsigned selector;
 377         unsigned base;
 378         unsigned limit;
 379         unsigned ar_bytes;
 380 } kvm_vmx_segment_fields[] = {
 381         VMX_SEGMENT_FIELD(CS),
 382         VMX_SEGMENT_FIELD(DS),
 383         VMX_SEGMENT_FIELD(ES),
 384         VMX_SEGMENT_FIELD(FS),
 385         VMX_SEGMENT_FIELD(GS),
 386         VMX_SEGMENT_FIELD(SS),
 387         VMX_SEGMENT_FIELD(TR),
 388         VMX_SEGMENT_FIELD(LDTR),
 389 };
 390
 391 u64 host_efer;
 392 static unsigned long host_idt_base;
 393
 394 /*
 395  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
 396  * will emulate SYSCALL in legacy mode if the vendor string in guest
 397  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
 398  * support this emulation, IA32_STAR must always be included in
 399  * vmx_msr_index[], even in i386 builds.
 400  */
 401 const u32 vmx_msr_index[] = {
 402 #ifdef CONFIG_X86_64
 403         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 404 #endif
 405         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 406 };
 407
 408 #if IS_ENABLED(CONFIG_HYPERV)
 409 static bool __read_mostly enlightened_vmcs = true;
 410 module_param(enlightened_vmcs, bool, 0444);
 411
 412 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
 413 static void check_ept_pointer_match(struct kvm *kvm)
 414 {
 415         struct kvm_vcpu *vcpu;
 416         u64 tmp_eptp = INVALID_PAGE;
 417         int i;
 418
 419         kvm_for_each_vcpu(i, vcpu, kvm) {
 420                 if (!VALID_PAGE(tmp_eptp)) {
 421                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
 422                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
 423                         to_kvm_vmx(kvm)->ept_pointers_match
 424                                 = EPT_POINTERS_MISMATCH;
 425                         return;
 426                 }
 427         }
 428
 429         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
 430 }
 431
 432 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
 433                 void *data)
 434 {
 435         struct kvm_tlb_range *range = data;
 436
 437         return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
 438                         range->pages);
 439 }
 440
 441 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
 442                 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
 443 {
 444         u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
 445
 446         /*
 447          * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
 448          * of the base of EPT PML4 table, strip off EPT configuration
 449          * information.
 450          */
 451         if (range)
 452                 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
 453                                 kvm_fill_hv_flush_list_func, (void *)range);
 454         else
 455                 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
 456 }
 457
 458 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
 459                 struct kvm_tlb_range *range)
 460 {
 461         struct kvm_vcpu *vcpu;
 462         int ret = 0, i;
 463
 464         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 465
 466         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
 467                 check_ept_pointer_match(kvm);
 468
 469         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
 470                 kvm_for_each_vcpu(i, vcpu, kvm) {
 471                         /* If ept_pointer is invalid pointer, bypass flush request. */
 472                         if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
 473                                 ret |= __hv_remote_flush_tlb_with_range(
 474                                         kvm, vcpu, range);
 475                 }
 476         } else {
 477                 ret = __hv_remote_flush_tlb_with_range(kvm,
 478                                 kvm_get_vcpu(kvm, 0), range);
 479         }
 480
 481         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
 482         return ret;
 483 }
 484 static int hv_remote_flush_tlb(struct kvm *kvm)
 485 {
 486         return hv_remote_flush_tlb_with_range(kvm, NULL);
 487 }
 488
 489 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
 490 {
 491         struct hv_enlightened_vmcs *evmcs;
 492         struct hv_partition_assist_pg **p_hv_pa_pg =
 493                         &vcpu->kvm->arch.hyperv.hv_pa_pg;
 494         /*
 495          * Synthetic VM-Exit is not enabled in current code and so All
 496          * evmcs in singe VM shares same assist page.
 497          */
 498         if (!*p_hv_pa_pg) {
 499                 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
 500                 if (!*p_hv_pa_pg)
 501                         return -ENOMEM;
 502                 pr_debug("KVM: Hyper-V: allocated PA_PG for %llx\n",
 503                        (u64)&vcpu->kvm);
 504         }
 505
 506         evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
 507
 508         evmcs->partition_assist_page =
 509                 __pa(*p_hv_pa_pg);
 510         evmcs->hv_vm_id = (u64)vcpu->kvm;
 511         evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
 512
 513         pr_debug("KVM: Hyper-V: enabled DIRECT flush for %llx\n",
 514                  (u64)vcpu->kvm);
 515         return 0;
 516 }
 517
 518 #endif /* IS_ENABLED(CONFIG_HYPERV) */
 519
 520 /*
 521  * Comment's format: document - errata name - stepping - processor name.
 522  * Refer from
 523  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
 524  */
 525 static u32 vmx_preemption_cpu_tfms[] = {
 526 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
 527 0x000206E6,
 528 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
 529 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
 530 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
 531 0x00020652,
 532 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
 533 0x00020655,
 534 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
 535 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
 536 /*
 537  * 320767.pdf - AAP86  - B1 -
 538  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
 539  */
 540 0x000106E5,
 541 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
 542 0x000106A0,
 543 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
 544 0x000106A1,
 545 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
 546 0x000106A4,
 547  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
 548  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
 549  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
 550 0x000106A5,
 551  /* Xeon E3-1220 V2 */
 552 0x000306A8,
 553 };
 554
 555 static inline bool cpu_has_broken_vmx_preemption_timer(void)
 556 {
 557         u32 eax = cpuid_eax(0x00000001), i;
 558
 559         /* Clear the reserved bits */
 560         eax &= ~(0x3U << 14 | 0xfU << 28);
 561         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
 562                 if (eax == vmx_preemption_cpu_tfms[i])
 563                         return true;
 564
 565         return false;
 566 }
 567
 568 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
 569 {
 570         return flexpriority_enabled && lapic_in_kernel(vcpu);
 571 }
 572
 573 static inline bool report_flexpriority(void)
 574 {
 575         return flexpriority_enabled;
 576 }
 577
 578 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 579 {
 580         int i;
 581
 582         for (i = 0; i < vmx->nmsrs; ++i)
 583                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 584                         return i;
 585         return -1;
 586 }
 587
 588 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 589 {
 590         int i;
 591
 592         i = __find_msr_index(vmx, msr);
 593         if (i >= 0)
 594                 return &vmx->guest_msrs[i];
 595         return NULL;
 596 }
 597
 598 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 599 {
 600         vmcs_clear(loaded_vmcs->vmcs);
 601         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
 602                 vmcs_clear(loaded_vmcs->shadow_vmcs);
 603         loaded_vmcs->cpu = -1;
 604         loaded_vmcs->launched = 0;
 605 }
 606
 607 #ifdef CONFIG_KEXEC_CORE
 608 /*
 609  * This bitmap is used to indicate whether the vmclear
 610  * operation is enabled on all cpus. All disabled by
 611  * default.
 612  */
 613 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
 614
 615 static inline void crash_enable_local_vmclear(int cpu)
 616 {
 617         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
 618 }
 619
 620 static inline void crash_disable_local_vmclear(int cpu)
 621 {
 622         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
 623 }
 624
 625 static inline int crash_local_vmclear_enabled(int cpu)
 626 {
 627         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
 628 }
 629
 630 static void crash_vmclear_local_loaded_vmcss(void)
 631 {
 632         int cpu = raw_smp_processor_id();
 633         struct loaded_vmcs *v;
 634
 635         if (!crash_local_vmclear_enabled(cpu))
 636                 return;
 637
 638         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
 639                             loaded_vmcss_on_cpu_link)
 640                 vmcs_clear(v->vmcs);
 641 }
 642 #else
 643 static inline void crash_enable_local_vmclear(int cpu) { }
 644 static inline void crash_disable_local_vmclear(int cpu) { }
 645 #endif /* CONFIG_KEXEC_CORE */
 646
 647 static void __loaded_vmcs_clear(void *arg)
 648 {
 649         struct loaded_vmcs *loaded_vmcs = arg;
 650         int cpu = raw_smp_processor_id();
 651
 652         if (loaded_vmcs->cpu != cpu)
 653                 return; /* vcpu migration can race with cpu offline */
 654         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 655                 per_cpu(current_vmcs, cpu) = NULL;
 656         crash_disable_local_vmclear(cpu);
 657         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 658
 659         /*
 660          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
 661          * is before setting loaded_vmcs->vcpu to -1 which is done in
 662          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
 663          * then adds the vmcs into percpu list before it is deleted.
 664          */
 665         smp_wmb();
 666
 667         loaded_vmcs_init(loaded_vmcs);
 668         crash_enable_local_vmclear(cpu);
 669 }
 670
 671 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 672 {
 673         int cpu = loaded_vmcs->cpu;
 674
 675         if (cpu != -1)
 676                 smp_call_function_single(cpu,
 677                          __loaded_vmcs_clear, loaded_vmcs, 1);
 678 }
 679
 680 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 681                                        unsigned field)
 682 {
 683         bool ret;
 684         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 685
 686         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
 687                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
 688                 vmx->segment_cache.bitmask = 0;
 689         }
 690         ret = vmx->segment_cache.bitmask & mask;
 691         vmx->segment_cache.bitmask |= mask;
 692         return ret;
 693 }
 694
 695 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 696 {
 697         u16 *p = &vmx->segment_cache.seg[seg].selector;
 698
 699         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 700                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 701         return *p;
 702 }
 703
 704 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 705 {
 706         ulong *p = &vmx->segment_cache.seg[seg].base;
 707
 708         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 709                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 710         return *p;
 711 }
 712
 713 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 714 {
 715         u32 *p = &vmx->segment_cache.seg[seg].limit;
 716
 717         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 718                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 719         return *p;
 720 }
 721
 722 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 723 {
 724         u32 *p = &vmx->segment_cache.seg[seg].ar;
 725
 726         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 727                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 728         return *p;
 729 }
 730
 731 void update_exception_bitmap(struct kvm_vcpu *vcpu)
 732 {
 733         u32 eb;
 734
 735         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 736              (1u << DB_VECTOR) | (1u << AC_VECTOR);
 737         /*
 738          * Guest access to VMware backdoor ports could legitimately
 739          * trigger #GP because of TSS I/O permission bitmap.
 740          * We intercept those #GP and allow access to them anyway
 741          * as VMware does.
 742          */
 743         if (enable_vmware_backdoor)
 744                 eb |= (1u << GP_VECTOR);
 745         if ((vcpu->guest_debug &
 746              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 747             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 748                 eb |= 1u << BP_VECTOR;
 749         if (to_vmx(vcpu)->rmode.vm86_active)
 750                 eb = ~0;
 751         if (enable_ept)
 752                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 753
 754         /* When we are running a nested L2 guest and L1 specified for it a
 755          * certain exception bitmap, we must trap the same exceptions and pass
 756          * them to L1. When running L2, we will only handle the exceptions
 757          * specified above if L1 did not want them.
 758          */
 759         if (is_guest_mode(vcpu))
 760                 eb |= get_vmcs12(vcpu)->exception_bitmap;
 761
 762         vmcs_write32(EXCEPTION_BITMAP, eb);
 763 }
 764
 765 /*
 766  * Check if MSR is intercepted for currently loaded MSR bitmap.
 767  */
 768 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 769 {
 770         unsigned long *msr_bitmap;
 771         int f = sizeof(unsigned long);
 772
 773         if (!cpu_has_vmx_msr_bitmap())
 774                 return true;
 775
 776         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
 777
 778         if (msr <= 0x1fff) {
 779                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
 780         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
 781                 msr &= 0x1fff;
 782                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
 783         }
 784
 785         return true;
 786 }
 787
 788 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 789                 unsigned long entry, unsigned long exit)
 790 {
 791         vm_entry_controls_clearbit(vmx, entry);
 792         vm_exit_controls_clearbit(vmx, exit);
 793 }
 794
 795 static int find_msr(struct vmx_msrs *m, unsigned int msr)
 796 {
 797         unsigned int i;
 798
 799         for (i = 0; i < m->nr; ++i) {
 800                 if (m->val[i].index == msr)
 801                         return i;
 802         }
 803         return -ENOENT;
 804 }
 805
 806 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 807 {
 808         int i;
 809         struct msr_autoload *m = &vmx->msr_autoload;
 810
 811         switch (msr) {
 812         case MSR_EFER:
 813                 if (cpu_has_load_ia32_efer()) {
 814                         clear_atomic_switch_msr_special(vmx,
 815                                         VM_ENTRY_LOAD_IA32_EFER,
 816                                         VM_EXIT_LOAD_IA32_EFER);
 817                         return;
 818                 }
 819                 break;
 820         case MSR_CORE_PERF_GLOBAL_CTRL:
 821                 if (cpu_has_load_perf_global_ctrl()) {
 822                         clear_atomic_switch_msr_special(vmx,
 823                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 824                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 825                         return;
 826                 }
 827                 break;
 828         }
 829         i = find_msr(&m->guest, msr);
 830         if (i < 0)
 831                 goto skip_guest;
 832         --m->guest.nr;
 833         m->guest.val[i] = m->guest.val[m->guest.nr];
 834         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 835
 836 skip_guest:
 837         i = find_msr(&m->host, msr);
 838         if (i < 0)
 839                 return;
 840
 841         --m->host.nr;
 842         m->host.val[i] = m->host.val[m->host.nr];
 843         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 844 }
 845
 846 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
 847                 unsigned long entry, unsigned long exit,
 848                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
 849                 u64 guest_val, u64 host_val)
 850 {
 851         vmcs_write64(guest_val_vmcs, guest_val);
 852         if (host_val_vmcs != HOST_IA32_EFER)
 853                 vmcs_write64(host_val_vmcs, host_val);
 854         vm_entry_controls_setbit(vmx, entry);
 855         vm_exit_controls_setbit(vmx, exit);
 856 }
 857
 858 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 859                                   u64 guest_val, u64 host_val, bool entry_only)
 860 {
 861         int i, j = 0;
 862         struct msr_autoload *m = &vmx->msr_autoload;
 863
 864         switch (msr) {
 865         case MSR_EFER:
 866                 if (cpu_has_load_ia32_efer()) {
 867                         add_atomic_switch_msr_special(vmx,
 868                                         VM_ENTRY_LOAD_IA32_EFER,
 869                                         VM_EXIT_LOAD_IA32_EFER,
 870                                         GUEST_IA32_EFER,
 871                                         HOST_IA32_EFER,
 872                                         guest_val, host_val);
 873                         return;
 874                 }
 875                 break;
 876         case MSR_CORE_PERF_GLOBAL_CTRL:
 877                 if (cpu_has_load_perf_global_ctrl()) {
 878                         add_atomic_switch_msr_special(vmx,
 879                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
 880                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
 881                                         GUEST_IA32_PERF_GLOBAL_CTRL,
 882                                         HOST_IA32_PERF_GLOBAL_CTRL,
 883                                         guest_val, host_val);
 884                         return;
 885                 }
 886                 break;
 887         case MSR_IA32_PEBS_ENABLE:
 888                 /* PEBS needs a quiescent period after being disabled (to write
 889                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
 890                  * provide that period, so a CPU could write host's record into
 891                  * guest's memory.
 892                  */
 893                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 894         }
 895
 896         i = find_msr(&m->guest, msr);
 897         if (!entry_only)
 898                 j = find_msr(&m->host, msr);
 899
 900         if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
 901                 (j < 0 &&  m->host.nr == NR_AUTOLOAD_MSRS)) {
 902                 printk_once(KERN_WARNING "Not enough msr switch entries. "
 903                                 "Can't add msr %x\n", msr);
 904                 return;
 905         }
 906         if (i < 0) {
 907                 i = m->guest.nr++;
 908                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
 909         }
 910         m->guest.val[i].index = msr;
 911         m->guest.val[i].value = guest_val;
 912
 913         if (entry_only)
 914                 return;
 915
 916         if (j < 0) {
 917                 j = m->host.nr++;
 918                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
 919         }
 920         m->host.val[j].index = msr;
 921         m->host.val[j].value = host_val;
 922 }
 923
 924 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 925 {
 926         u64 guest_efer = vmx->vcpu.arch.efer;
 927         u64 ignore_bits = 0;
 928
 929         if (!enable_ept) {
 930                 /*
 931                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
 932                  * host CPUID is more efficient than testing guest CPUID
 933                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
 934                  */
 935                 if (boot_cpu_has(X86_FEATURE_SMEP))
 936                         guest_efer |= EFER_NX;
 937                 else if (!(guest_efer & EFER_NX))
 938                         ignore_bits |= EFER_NX;
 939         }
 940
 941         /*
 942          * LMA and LME handled by hardware; SCE meaningless outside long mode.
 943          */
 944         ignore_bits |= EFER_SCE;
 945 #ifdef CONFIG_X86_64
 946         ignore_bits |= EFER_LMA | EFER_LME;
 947         /* SCE is meaningful only in long mode on Intel */
 948         if (guest_efer & EFER_LMA)
 949                 ignore_bits &= ~(u64)EFER_SCE;
 950 #endif
 951
 952         /*
 953          * On EPT, we can't emulate NX, so we must switch EFER atomically.
 954          * On CPUs that support "load IA32_EFER", always switch EFER
 955          * atomically, since it's faster than switching it manually.
 956          */
 957         if (cpu_has_load_ia32_efer() ||
 958             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
 959                 if (!(guest_efer & EFER_LMA))
 960                         guest_efer &= ~EFER_LME;
 961                 if (guest_efer != host_efer)
 962                         add_atomic_switch_msr(vmx, MSR_EFER,
 963                                               guest_efer, host_efer, false);
 964                 else
 965                         clear_atomic_switch_msr(vmx, MSR_EFER);
 966                 return false;
 967         } else {
 968                 clear_atomic_switch_msr(vmx, MSR_EFER);
 969
 970                 guest_efer &= ~ignore_bits;
 971                 guest_efer |= host_efer & ignore_bits;
 972
 973                 vmx->guest_msrs[efer_offset].data = guest_efer;
 974                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 975
 976                 return true;
 977         }
 978 }
 979
 980 #ifdef CONFIG_X86_32
 981 /*
 982  * On 32-bit kernels, VM exits still load the FS and GS bases from the
 983  * VMCS rather than the segment table.  KVM uses this helper to figure
 984  * out the current bases to poke them into the VMCS before entry.
 985  */
 986 static unsigned long segment_base(u16 selector)
 987 {
 988         struct desc_struct *table;
 989         unsigned long v;
 990
 991         if (!(selector & ~SEGMENT_RPL_MASK))
 992                 return 0;
 993
 994         table = get_current_gdt_ro();
 995
 996         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
 997                 u16 ldt_selector = kvm_read_ldt();
 998
 999                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1000                         return 0;
1001
1002                 table = (struct desc_struct *)segment_base(ldt_selector);
1003         }
1004         v = get_desc_base(&table[selector >> 3]);
1005         return v;
1006 }
1007 #endif
1008
1009 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1010 {
1011         u32 i;
1012
1013         wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1014         wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1015         wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1016         wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1017         for (i = 0; i < addr_range; i++) {
1018                 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1019                 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1020         }
1021 }
1022
1023 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1024 {
1025         u32 i;
1026
1027         rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1028         rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1029         rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1030         rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1031         for (i = 0; i < addr_range; i++) {
1032                 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1033                 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1034         }
1035 }
1036
1037 static void pt_guest_enter(struct vcpu_vmx *vmx)
1038 {
1039         if (pt_mode == PT_MODE_SYSTEM)
1040                 return;
1041
1042         /*
1043          * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1044          * Save host state before VM entry.
1045          */
1046         rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1047         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1048                 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1049                 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1050                 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1051         }
1052 }
1053
1054 static void pt_guest_exit(struct vcpu_vmx *vmx)
1055 {
1056         if (pt_mode == PT_MODE_SYSTEM)
1057                 return;
1058
1059         if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1060                 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1061                 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1062         }
1063
1064         /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1065         wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1066 }
1067
1068 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1069                         unsigned long fs_base, unsigned long gs_base)
1070 {
1071         if (unlikely(fs_sel != host->fs_sel)) {
1072                 if (!(fs_sel & 7))
1073                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1074                 else
1075                         vmcs_write16(HOST_FS_SELECTOR, 0);
1076                 host->fs_sel = fs_sel;
1077         }
1078         if (unlikely(gs_sel != host->gs_sel)) {
1079                 if (!(gs_sel & 7))
1080                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1081                 else
1082                         vmcs_write16(HOST_GS_SELECTOR, 0);
1083                 host->gs_sel = gs_sel;
1084         }
1085         if (unlikely(fs_base != host->fs_base)) {
1086                 vmcs_writel(HOST_FS_BASE, fs_base);
1087                 host->fs_base = fs_base;
1088         }
1089         if (unlikely(gs_base != host->gs_base)) {
1090                 vmcs_writel(HOST_GS_BASE, gs_base);
1091                 host->gs_base = gs_base;
1092         }
1093 }
1094
1095 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1096 {
1097         struct vcpu_vmx *vmx = to_vmx(vcpu);
1098         struct vmcs_host_state *host_state;
1099 #ifdef CONFIG_X86_64
1100         int cpu = raw_smp_processor_id();
1101 #endif
1102         unsigned long fs_base, gs_base;
1103         u16 fs_sel, gs_sel;
1104         int i;
1105
1106         vmx->req_immediate_exit = false;
1107
1108         /*
1109          * Note that guest MSRs to be saved/restored can also be changed
1110          * when guest state is loaded. This happens when guest transitions
1111          * to/from long-mode by setting MSR_EFER.LMA.
1112          */
1113         if (!vmx->guest_msrs_ready) {
1114                 vmx->guest_msrs_ready = true;
1115                 for (i = 0; i < vmx->save_nmsrs; ++i)
1116                         kvm_set_shared_msr(vmx->guest_msrs[i].index,
1117                                            vmx->guest_msrs[i].data,
1118                                            vmx->guest_msrs[i].mask);
1119
1120         }
1121         if (vmx->guest_state_loaded)
1122                 return;
1123
1124         host_state = &vmx->loaded_vmcs->host_state;
1125
1126         /*
1127          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1128          * allow segment selectors with cpl > 0 or ti == 1.
1129          */
1130         host_state->ldt_sel = kvm_read_ldt();
1131
1132 #ifdef CONFIG_X86_64
1133         savesegment(ds, host_state->ds_sel);
1134         savesegment(es, host_state->es_sel);
1135
1136         gs_base = cpu_kernelmode_gs_base(cpu);
1137         if (likely(is_64bit_mm(current->mm))) {
1138                 save_fsgs_for_kvm();
1139                 fs_sel = current->thread.fsindex;
1140                 gs_sel = current->thread.gsindex;
1141                 fs_base = current->thread.fsbase;
1142                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1143         } else {
1144                 savesegment(fs, fs_sel);
1145                 savesegment(gs, gs_sel);
1146                 fs_base = read_msr(MSR_FS_BASE);
1147                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1148         }
1149
1150         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1151 #else
1152         savesegment(fs, fs_sel);
1153         savesegment(gs, gs_sel);
1154         fs_base = segment_base(fs_sel);
1155         gs_base = segment_base(gs_sel);
1156 #endif
1157
1158         vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1159         vmx->guest_state_loaded = true;
1160 }
1161
1162 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1163 {
1164         struct vmcs_host_state *host_state;
1165
1166         if (!vmx->guest_state_loaded)
1167                 return;
1168
1169         host_state = &vmx->loaded_vmcs->host_state;
1170
1171         ++vmx->vcpu.stat.host_state_reload;
1172
1173 #ifdef CONFIG_X86_64
1174         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1175 #endif
1176         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1177                 kvm_load_ldt(host_state->ldt_sel);
1178 #ifdef CONFIG_X86_64
1179                 load_gs_index(host_state->gs_sel);
1180 #else
1181                 loadsegment(gs, host_state->gs_sel);
1182 #endif
1183         }
1184         if (host_state->fs_sel & 7)
1185                 loadsegment(fs, host_state->fs_sel);
1186 #ifdef CONFIG_X86_64
1187         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1188                 loadsegment(ds, host_state->ds_sel);
1189                 loadsegment(es, host_state->es_sel);
1190         }
1191 #endif
1192         invalidate_tss_limit();
1193 #ifdef CONFIG_X86_64
1194         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1195 #endif
1196         load_fixmap_gdt(raw_smp_processor_id());
1197         vmx->guest_state_loaded = false;
1198         vmx->guest_msrs_ready = false;
1199 }
1200
1201 #ifdef CONFIG_X86_64
1202 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1203 {
1204         preempt_disable();
1205         if (vmx->guest_state_loaded)
1206                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1207         preempt_enable();
1208         return vmx->msr_guest_kernel_gs_base;
1209 }
1210
1211 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1212 {
1213         preempt_disable();
1214         if (vmx->guest_state_loaded)
1215                 wrmsrl(MSR_KERNEL_GS_BASE, data);
1216         preempt_enable();
1217         vmx->msr_guest_kernel_gs_base = data;
1218 }
1219 #endif
1220
1221 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1222 {
1223         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1224         struct pi_desc old, new;
1225         unsigned int dest;
1226
1227         /*
1228          * In case of hot-plug or hot-unplug, we may have to undo
1229          * vmx_vcpu_pi_put even if there is no assigned device.  And we
1230          * always keep PI.NDST up to date for simplicity: it makes the
1231          * code easier, and CPU migration is not a fast path.
1232          */
1233         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1234                 return;
1235
1236         /* The full case.  */
1237         do {
1238                 old.control = new.control = pi_desc->control;
1239
1240                 dest = cpu_physical_id(cpu);
1241
1242                 if (x2apic_enabled())
1243                         new.ndst = dest;
1244                 else
1245                         new.ndst = (dest << 8) & 0xFF00;
1246
1247                 new.sn = 0;
1248         } while (cmpxchg64(&pi_desc->control, old.control,
1249                            new.control) != old.control);
1250
1251         /*
1252          * Clear SN before reading the bitmap.  The VT-d firmware
1253          * writes the bitmap and reads SN atomically (5.2.3 in the
1254          * spec), so it doesn't really have a memory barrier that
1255          * pairs with this, but we cannot do that and we need one.
1256          */
1257         smp_mb__after_atomic();
1258
1259         if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1260                 pi_set_on(pi_desc);
1261 }
1262
1263 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1264 {
1265         struct vcpu_vmx *vmx = to_vmx(vcpu);
1266         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1267
1268         if (!already_loaded) {
1269                 loaded_vmcs_clear(vmx->loaded_vmcs);
1270                 local_irq_disable();
1271                 crash_disable_local_vmclear(cpu);
1272
1273                 /*
1274                  * Read loaded_vmcs->cpu should be before fetching
1275                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1276                  * See the comments in __loaded_vmcs_clear().
1277                  */
1278                 smp_rmb();
1279
1280                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1281                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1282                 crash_enable_local_vmclear(cpu);
1283                 local_irq_enable();
1284         }
1285
1286         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1287                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1288                 vmcs_load(vmx->loaded_vmcs->vmcs);
1289                 indirect_branch_prediction_barrier();
1290         }
1291
1292         if (!already_loaded) {
1293                 void *gdt = get_current_gdt_ro();
1294                 unsigned long sysenter_esp;
1295
1296                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1297
1298                 /*
1299                  * Linux uses per-cpu TSS and GDT, so set these when switching
1300                  * processors.  See 22.2.4.
1301                  */
1302                 vmcs_writel(HOST_TR_BASE,
1303                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1304                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1305
1306                 /*
1307                  * VM exits change the host TR limit to 0x67 after a VM
1308                  * exit.  This is okay, since 0x67 covers everything except
1309                  * the IO bitmap and have have code to handle the IO bitmap
1310                  * being lost after a VM exit.
1311                  */
1312                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1313
1314                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1315                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1316
1317                 vmx->loaded_vmcs->cpu = cpu;
1318         }
1319
1320         /* Setup TSC multiplier */
1321         if (kvm_has_tsc_control &&
1322             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1323                 decache_tsc_multiplier(vmx);
1324 }
1325
1326 /*
1327  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1328  * vcpu mutex is already taken.
1329  */
1330 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1331 {
1332         struct vcpu_vmx *vmx = to_vmx(vcpu);
1333
1334         vmx_vcpu_load_vmcs(vcpu, cpu);
1335
1336         vmx_vcpu_pi_load(vcpu, cpu);
1337
1338         vmx->host_pkru = read_pkru();
1339         vmx->host_debugctlmsr = get_debugctlmsr();
1340 }
1341
1342 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1343 {
1344         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1345
1346         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1347                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
1348                 !kvm_vcpu_apicv_active(vcpu))
1349                 return;
1350
1351         /* Set SN when the vCPU is preempted */
1352         if (vcpu->preempted)
1353                 pi_set_sn(pi_desc);
1354 }
1355
1356 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1357 {
1358         vmx_vcpu_pi_put(vcpu);
1359
1360         vmx_prepare_switch_to_host(to_vmx(vcpu));
1361 }
1362
1363 static bool emulation_required(struct kvm_vcpu *vcpu)
1364 {
1365         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1366 }
1367
1368 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1369
1370 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1371 {
1372         unsigned long rflags, save_rflags;
1373
1374         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1375                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1376                 rflags = vmcs_readl(GUEST_RFLAGS);
1377                 if (to_vmx(vcpu)->rmode.vm86_active) {
1378                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1379                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1380                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1381                 }
1382                 to_vmx(vcpu)->rflags = rflags;
1383         }
1384         return to_vmx(vcpu)->rflags;
1385 }
1386
1387 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1388 {
1389         unsigned long old_rflags = vmx_get_rflags(vcpu);
1390
1391         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1392         to_vmx(vcpu)->rflags = rflags;
1393         if (to_vmx(vcpu)->rmode.vm86_active) {
1394                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1395                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1396         }
1397         vmcs_writel(GUEST_RFLAGS, rflags);
1398
1399         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1400                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1401 }
1402
1403 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1404 {
1405         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1406         int ret = 0;
1407
1408         if (interruptibility & GUEST_INTR_STATE_STI)
1409                 ret |= KVM_X86_SHADOW_INT_STI;
1410         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1411                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1412
1413         return ret;
1414 }
1415
1416 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1417 {
1418         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1419         u32 interruptibility = interruptibility_old;
1420
1421         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1422
1423         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1424                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1425         else if (mask & KVM_X86_SHADOW_INT_STI)
1426                 interruptibility |= GUEST_INTR_STATE_STI;
1427
1428         if ((interruptibility != interruptibility_old))
1429                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1430 }
1431
1432 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1433 {
1434         struct vcpu_vmx *vmx = to_vmx(vcpu);
1435         unsigned long value;
1436
1437         /*
1438          * Any MSR write that attempts to change bits marked reserved will
1439          * case a #GP fault.
1440          */
1441         if (data & vmx->pt_desc.ctl_bitmask)
1442                 return 1;
1443
1444         /*
1445          * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1446          * result in a #GP unless the same write also clears TraceEn.
1447          */
1448         if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1449                 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1450                 return 1;
1451
1452         /*
1453          * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1454          * and FabricEn would cause #GP, if
1455          * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1456          */
1457         if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1458                 !(data & RTIT_CTL_FABRIC_EN) &&
1459                 !intel_pt_validate_cap(vmx->pt_desc.caps,
1460                                         PT_CAP_single_range_output))
1461                 return 1;
1462
1463         /*
1464          * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1465          * utilize encodings marked reserved will casue a #GP fault.
1466          */
1467         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1468         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1469                         !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1470                         RTIT_CTL_MTC_RANGE_OFFSET, &value))
1471                 return 1;
1472         value = intel_pt_validate_cap(vmx->pt_desc.caps,
1473                                                 PT_CAP_cycle_thresholds);
1474         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1475                         !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1476                         RTIT_CTL_CYC_THRESH_OFFSET, &value))
1477                 return 1;
1478         value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1479         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1480                         !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1481                         RTIT_CTL_PSB_FREQ_OFFSET, &value))
1482                 return 1;
1483
1484         /*
1485          * If ADDRx_CFG is reserved or the encodings is >2 will
1486          * cause a #GP fault.
1487          */
1488         value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1489         if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1490                 return 1;
1491         value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1492         if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1493                 return 1;
1494         value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1495         if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1496                 return 1;
1497         value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1498         if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1499                 return 1;
1500
1501         return 0;
1502 }
1503
1504 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1505 {
1506         unsigned long rip;
1507
1508         /*
1509          * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1510          * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1511          * set when EPT misconfig occurs.  In practice, real hardware updates
1512          * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1513          * (namely Hyper-V) don't set it due to it being undefined behavior,
1514          * i.e. we end up advancing IP with some random value.
1515          */
1516         if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1517             to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1518                 rip = kvm_rip_read(vcpu);
1519                 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1520                 kvm_rip_write(vcpu, rip);
1521         } else {
1522                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1523                         return 0;
1524         }
1525
1526         /* skipping an emulated instruction also counts */
1527         vmx_set_interrupt_shadow(vcpu, 0);
1528
1529         return 1;
1530 }
1531
1532 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1533 {
1534         /*
1535          * Ensure that we clear the HLT state in the VMCS.  We don't need to
1536          * explicitly skip the instruction because if the HLT state is set,
1537          * then the instruction is already executing and RIP has already been
1538          * advanced.
1539          */
1540         if (kvm_hlt_in_guest(vcpu->kvm) &&
1541                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1542                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1543 }
1544
1545 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1546 {
1547         struct vcpu_vmx *vmx = to_vmx(vcpu);
1548         unsigned nr = vcpu->arch.exception.nr;
1549         bool has_error_code = vcpu->arch.exception.has_error_code;
1550         u32 error_code = vcpu->arch.exception.error_code;
1551         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1552
1553         kvm_deliver_exception_payload(vcpu);
1554
1555         if (has_error_code) {
1556                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1557                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1558         }
1559
1560         if (vmx->rmode.vm86_active) {
1561                 int inc_eip = 0;
1562                 if (kvm_exception_is_soft(nr))
1563                         inc_eip = vcpu->arch.event_exit_inst_len;
1564                 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1565                 return;
1566         }
1567
1568         WARN_ON_ONCE(vmx->emulation_required);
1569
1570         if (kvm_exception_is_soft(nr)) {
1571                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1572                              vmx->vcpu.arch.event_exit_inst_len);
1573                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1574         } else
1575                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1576
1577         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1578
1579         vmx_clear_hlt(vcpu);
1580 }
1581
1582 static bool vmx_rdtscp_supported(void)
1583 {
1584         return cpu_has_vmx_rdtscp();
1585 }
1586
1587 static bool vmx_invpcid_supported(void)
1588 {
1589         return cpu_has_vmx_invpcid();
1590 }
1591
1592 /*
1593  * Swap MSR entry in host/guest MSR entry array.
1594  */
1595 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1596 {
1597         struct shared_msr_entry tmp;
1598
1599         tmp = vmx->guest_msrs[to];
1600         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1601         vmx->guest_msrs[from] = tmp;
1602 }
1603
1604 /*
1605  * Set up the vmcs to automatically save and restore system
1606  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1607  * mode, as fiddling with msrs is very expensive.
1608  */
1609 static void setup_msrs(struct vcpu_vmx *vmx)
1610 {
1611         int save_nmsrs, index;
1612
1613         save_nmsrs = 0;
1614 #ifdef CONFIG_X86_64
1615         /*
1616          * The SYSCALL MSRs are only needed on long mode guests, and only
1617          * when EFER.SCE is set.
1618          */
1619         if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1620                 index = __find_msr_index(vmx, MSR_STAR);
1621                 if (index >= 0)
1622                         move_msr_up(vmx, index, save_nmsrs++);
1623                 index = __find_msr_index(vmx, MSR_LSTAR);
1624                 if (index >= 0)
1625                         move_msr_up(vmx, index, save_nmsrs++);
1626                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1627                 if (index >= 0)
1628                         move_msr_up(vmx, index, save_nmsrs++);
1629         }
1630 #endif
1631         index = __find_msr_index(vmx, MSR_EFER);
1632         if (index >= 0 && update_transition_efer(vmx, index))
1633                 move_msr_up(vmx, index, save_nmsrs++);
1634         index = __find_msr_index(vmx, MSR_TSC_AUX);
1635         if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1636                 move_msr_up(vmx, index, save_nmsrs++);
1637
1638         vmx->save_nmsrs = save_nmsrs;
1639         vmx->guest_msrs_ready = false;
1640
1641         if (cpu_has_vmx_msr_bitmap())
1642                 vmx_update_msr_bitmap(&vmx->vcpu);
1643 }
1644
1645 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1646 {
1647         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1648
1649         if (is_guest_mode(vcpu) &&
1650             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1651                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1652
1653         return vcpu->arch.tsc_offset;
1654 }
1655
1656 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1657 {
1658         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1659         u64 g_tsc_offset = 0;
1660
1661         /*
1662          * We're here if L1 chose not to trap WRMSR to TSC. According
1663          * to the spec, this should set L1's TSC; The offset that L1
1664          * set for L2 remains unchanged, and still needs to be added
1665          * to the newly set TSC to get L2's TSC.
1666          */
1667         if (is_guest_mode(vcpu) &&
1668             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1669                 g_tsc_offset = vmcs12->tsc_offset;
1670
1671         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1672                                    vcpu->arch.tsc_offset - g_tsc_offset,
1673                                    offset);
1674         vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1675         return offset + g_tsc_offset;
1676 }
1677
1678 /*
1679  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1680  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1681  * all guests if the "nested" module option is off, and can also be disabled
1682  * for a single guest by disabling its VMX cpuid bit.
1683  */
1684 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1685 {
1686         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1687 }
1688
1689 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1690                                                  uint64_t val)
1691 {
1692         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1693
1694         return !(val & ~valid_bits);
1695 }
1696
1697 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1698 {
1699         switch (msr->index) {
1700         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1701                 if (!nested)
1702                         return 1;
1703                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1704         default:
1705                 return 1;
1706         }
1707
1708         return 0;
1709 }
1710
1711 /*
1712  * Reads an msr value (of 'msr_index') into 'pdata'.
1713  * Returns 0 on success, non-0 otherwise.
1714  * Assumes vcpu_load() was already called.
1715  */
1716 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1717 {
1718         struct vcpu_vmx *vmx = to_vmx(vcpu);
1719         struct shared_msr_entry *msr;
1720         u32 index;
1721
1722         switch (msr_info->index) {
1723 #ifdef CONFIG_X86_64
1724         case MSR_FS_BASE:
1725                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1726                 break;
1727         case MSR_GS_BASE:
1728                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1729                 break;
1730         case MSR_KERNEL_GS_BASE:
1731                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1732                 break;
1733 #endif
1734         case MSR_EFER:
1735                 return kvm_get_msr_common(vcpu, msr_info);
1736         case MSR_IA32_SPEC_CTRL:
1737                 if (!msr_info->host_initiated &&
1738                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1739                         return 1;
1740
1741                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1742                 break;
1743         case MSR_IA32_SYSENTER_CS:
1744                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1745                 break;
1746         case MSR_IA32_SYSENTER_EIP:
1747                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1748                 break;
1749         case MSR_IA32_SYSENTER_ESP:
1750                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1751                 break;
1752         case MSR_IA32_BNDCFGS:
1753                 if (!kvm_mpx_supported() ||
1754                     (!msr_info->host_initiated &&
1755                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1756                         return 1;
1757                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1758                 break;
1759         case MSR_IA32_MCG_EXT_CTL:
1760                 if (!msr_info->host_initiated &&
1761                     !(vmx->msr_ia32_feature_control &
1762                       FEATURE_CONTROL_LMCE))
1763                         return 1;
1764                 msr_info->data = vcpu->arch.mcg_ext_ctl;
1765                 break;
1766         case MSR_IA32_FEATURE_CONTROL:
1767                 msr_info->data = vmx->msr_ia32_feature_control;
1768                 break;
1769         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1770                 if (!nested_vmx_allowed(vcpu))
1771                         return 1;
1772                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1773                                        &msr_info->data);
1774         case MSR_IA32_XSS:
1775                 if (!vmx_xsaves_supported() ||
1776                     (!msr_info->host_initiated &&
1777                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1778                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1779                         return 1;
1780                 msr_info->data = vcpu->arch.ia32_xss;
1781                 break;
1782         case MSR_IA32_RTIT_CTL:
1783                 if (pt_mode != PT_MODE_HOST_GUEST)
1784                         return 1;
1785                 msr_info->data = vmx->pt_desc.guest.ctl;
1786                 break;
1787         case MSR_IA32_RTIT_STATUS:
1788                 if (pt_mode != PT_MODE_HOST_GUEST)
1789                         return 1;
1790                 msr_info->data = vmx->pt_desc.guest.status;
1791                 break;
1792         case MSR_IA32_RTIT_CR3_MATCH:
1793                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1794                         !intel_pt_validate_cap(vmx->pt_desc.caps,
1795                                                 PT_CAP_cr3_filtering))
1796                         return 1;
1797                 msr_info->data = vmx->pt_desc.guest.cr3_match;
1798                 break;
1799         case MSR_IA32_RTIT_OUTPUT_BASE:
1800                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1801                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1802                                         PT_CAP_topa_output) &&
1803                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1804                                         PT_CAP_single_range_output)))
1805                         return 1;
1806                 msr_info->data = vmx->pt_desc.guest.output_base;
1807                 break;
1808         case MSR_IA32_RTIT_OUTPUT_MASK:
1809                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1810                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
1811                                         PT_CAP_topa_output) &&
1812                          !intel_pt_validate_cap(vmx->pt_desc.caps,
1813                                         PT_CAP_single_range_output)))
1814                         return 1;
1815                 msr_info->data = vmx->pt_desc.guest.output_mask;
1816                 break;
1817         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1818                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1819                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1820                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1821                                         PT_CAP_num_address_ranges)))
1822                         return 1;
1823                 if (index % 2)
1824                         msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1825                 else
1826                         msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1827                 break;
1828         case MSR_TSC_AUX:
1829                 if (!msr_info->host_initiated &&
1830                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1831                         return 1;
1832                 /* Else, falls through */
1833         default:
1834                 msr = find_msr_entry(vmx, msr_info->index);
1835                 if (msr) {
1836                         msr_info->data = msr->data;
1837                         break;
1838                 }
1839                 return kvm_get_msr_common(vcpu, msr_info);
1840         }
1841
1842         return 0;
1843 }
1844
1845 /*
1846  * Writes msr value into into the appropriate "register".
1847  * Returns 0 on success, non-0 otherwise.
1848  * Assumes vcpu_load() was already called.
1849  */
1850 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1851 {
1852         struct vcpu_vmx *vmx = to_vmx(vcpu);
1853         struct shared_msr_entry *msr;
1854         int ret = 0;
1855         u32 msr_index = msr_info->index;
1856         u64 data = msr_info->data;
1857         u32 index;
1858
1859         switch (msr_index) {
1860         case MSR_EFER:
1861                 ret = kvm_set_msr_common(vcpu, msr_info);
1862                 break;
1863 #ifdef CONFIG_X86_64
1864         case MSR_FS_BASE:
1865                 vmx_segment_cache_clear(vmx);
1866                 vmcs_writel(GUEST_FS_BASE, data);
1867                 break;
1868         case MSR_GS_BASE:
1869                 vmx_segment_cache_clear(vmx);
1870                 vmcs_writel(GUEST_GS_BASE, data);
1871                 break;
1872         case MSR_KERNEL_GS_BASE:
1873                 vmx_write_guest_kernel_gs_base(vmx, data);
1874                 break;
1875 #endif
1876         case MSR_IA32_SYSENTER_CS:
1877                 if (is_guest_mode(vcpu))
1878                         get_vmcs12(vcpu)->guest_sysenter_cs = data;
1879                 vmcs_write32(GUEST_SYSENTER_CS, data);
1880                 break;
1881         case MSR_IA32_SYSENTER_EIP:
1882                 if (is_guest_mode(vcpu))
1883                         get_vmcs12(vcpu)->guest_sysenter_eip = data;
1884                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1885                 break;
1886         case MSR_IA32_SYSENTER_ESP:
1887                 if (is_guest_mode(vcpu))
1888                         get_vmcs12(vcpu)->guest_sysenter_esp = data;
1889                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1890                 break;
1891         case MSR_IA32_DEBUGCTLMSR:
1892                 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1893                                                 VM_EXIT_SAVE_DEBUG_CONTROLS)
1894                         get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1895
1896                 ret = kvm_set_msr_common(vcpu, msr_info);
1897                 break;
1898
1899         case MSR_IA32_BNDCFGS:
1900                 if (!kvm_mpx_supported() ||
1901                     (!msr_info->host_initiated &&
1902                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1903                         return 1;
1904                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1905                     (data & MSR_IA32_BNDCFGS_RSVD))
1906                         return 1;
1907                 vmcs_write64(GUEST_BNDCFGS, data);
1908                 break;
1909         case MSR_IA32_SPEC_CTRL:
1910                 if (!msr_info->host_initiated &&
1911                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1912                         return 1;
1913
1914                 /* The STIBP bit doesn't fault even if it's not advertised */
1915                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1916                         return 1;
1917
1918                 vmx->spec_ctrl = data;
1919
1920                 if (!data)
1921                         break;
1922
1923                 /*
1924                  * For non-nested:
1925                  * When it's written (to non-zero) for the first time, pass
1926                  * it through.
1927                  *
1928                  * For nested:
1929                  * The handling of the MSR bitmap for L2 guests is done in
1930                  * nested_vmx_merge_msr_bitmap. We should not touch the
1931                  * vmcs02.msr_bitmap here since it gets completely overwritten
1932                  * in the merging. We update the vmcs01 here for L1 as well
1933                  * since it will end up touching the MSR anyway now.
1934                  */
1935                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1936                                               MSR_IA32_SPEC_CTRL,
1937                                               MSR_TYPE_RW);
1938                 break;
1939         case MSR_IA32_PRED_CMD:
1940                 if (!msr_info->host_initiated &&
1941                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1942                         return 1;
1943
1944                 if (data & ~PRED_CMD_IBPB)
1945                         return 1;
1946
1947                 if (!data)
1948                         break;
1949
1950                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1951
1952                 /*
1953                  * For non-nested:
1954                  * When it's written (to non-zero) for the first time, pass
1955                  * it through.
1956                  *
1957                  * For nested:
1958                  * The handling of the MSR bitmap for L2 guests is done in
1959                  * nested_vmx_merge_msr_bitmap. We should not touch the
1960                  * vmcs02.msr_bitmap here since it gets completely overwritten
1961                  * in the merging.
1962                  */
1963                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1964                                               MSR_TYPE_W);
1965                 break;
1966         case MSR_IA32_CR_PAT:
1967                 if (!kvm_pat_valid(data))
1968                         return 1;
1969
1970                 if (is_guest_mode(vcpu) &&
1971                     get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
1972                         get_vmcs12(vcpu)->guest_ia32_pat = data;
1973
1974                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1975                         vmcs_write64(GUEST_IA32_PAT, data);
1976                         vcpu->arch.pat = data;
1977                         break;
1978                 }
1979                 ret = kvm_set_msr_common(vcpu, msr_info);
1980                 break;
1981         case MSR_IA32_TSC_ADJUST:
1982                 ret = kvm_set_msr_common(vcpu, msr_info);
1983                 break;
1984         case MSR_IA32_MCG_EXT_CTL:
1985                 if ((!msr_info->host_initiated &&
1986                      !(to_vmx(vcpu)->msr_ia32_feature_control &
1987                        FEATURE_CONTROL_LMCE)) ||
1988                     (data & ~MCG_EXT_CTL_LMCE_EN))
1989                         return 1;
1990                 vcpu->arch.mcg_ext_ctl = data;
1991                 break;
1992         case MSR_IA32_FEATURE_CONTROL:
1993                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
1994                     (to_vmx(vcpu)->msr_ia32_feature_control &
1995                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1996                         return 1;
1997                 vmx->msr_ia32_feature_control = data;
1998                 if (msr_info->host_initiated && data == 0)
1999                         vmx_leave_nested(vcpu);
2000                 break;
2001         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2002                 if (!msr_info->host_initiated)
2003                         return 1; /* they are read-only */
2004                 if (!nested_vmx_allowed(vcpu))
2005                         return 1;
2006                 return vmx_set_vmx_msr(vcpu, msr_index, data);
2007         case MSR_IA32_XSS:
2008                 if (!vmx_xsaves_supported() ||
2009                     (!msr_info->host_initiated &&
2010                      !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2011                        guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
2012                         return 1;
2013                 /*
2014                  * The only supported bit as of Skylake is bit 8, but
2015                  * it is not supported on KVM.
2016                  */
2017                 if (data != 0)
2018                         return 1;
2019                 vcpu->arch.ia32_xss = data;
2020                 if (vcpu->arch.ia32_xss != host_xss)
2021                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2022                                 vcpu->arch.ia32_xss, host_xss, false);
2023                 else
2024                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2025                 break;
2026         case MSR_IA32_RTIT_CTL:
2027                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2028                         vmx_rtit_ctl_check(vcpu, data) ||
2029                         vmx->nested.vmxon)
2030                         return 1;
2031                 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2032                 vmx->pt_desc.guest.ctl = data;
2033                 pt_update_intercept_for_msr(vmx);
2034                 break;
2035         case MSR_IA32_RTIT_STATUS:
2036                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2037                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2038                         (data & MSR_IA32_RTIT_STATUS_MASK))
2039                         return 1;
2040                 vmx->pt_desc.guest.status = data;
2041                 break;
2042         case MSR_IA32_RTIT_CR3_MATCH:
2043                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2044                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2045                         !intel_pt_validate_cap(vmx->pt_desc.caps,
2046                                                 PT_CAP_cr3_filtering))
2047                         return 1;
2048                 vmx->pt_desc.guest.cr3_match = data;
2049                 break;
2050         case MSR_IA32_RTIT_OUTPUT_BASE:
2051                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2052                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2053                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2054                                         PT_CAP_topa_output) &&
2055                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2056                                         PT_CAP_single_range_output)) ||
2057                         (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2058                         return 1;
2059                 vmx->pt_desc.guest.output_base = data;
2060                 break;
2061         case MSR_IA32_RTIT_OUTPUT_MASK:
2062                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2063                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2064                         (!intel_pt_validate_cap(vmx->pt_desc.caps,
2065                                         PT_CAP_topa_output) &&
2066                          !intel_pt_validate_cap(vmx->pt_desc.caps,
2067                                         PT_CAP_single_range_output)))
2068                         return 1;
2069                 vmx->pt_desc.guest.output_mask = data;
2070                 break;
2071         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2072                 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2073                 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2074                         (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2075                         (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2076                                         PT_CAP_num_address_ranges)))
2077                         return 1;
2078                 if (index % 2)
2079                         vmx->pt_desc.guest.addr_b[index / 2] = data;
2080                 else
2081                         vmx->pt_desc.guest.addr_a[index / 2] = data;
2082                 break;
2083         case MSR_TSC_AUX:
2084                 if (!msr_info->host_initiated &&
2085                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2086                         return 1;
2087                 /* Check reserved bit, higher 32 bits should be zero */
2088                 if ((data >> 32) != 0)
2089                         return 1;
2090                 /* Else, falls through */
2091         default:
2092                 msr = find_msr_entry(vmx, msr_index);
2093                 if (msr) {
2094                         u64 old_msr_data = msr->data;
2095                         msr->data = data;
2096                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2097                                 preempt_disable();
2098                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2099                                                          msr->mask);
2100                                 preempt_enable();
2101                                 if (ret)
2102                                         msr->data = old_msr_data;
2103                         }
2104                         break;
2105                 }
2106                 ret = kvm_set_msr_common(vcpu, msr_info);
2107         }
2108
2109         return ret;
2110 }
2111
2112 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2113 {
2114         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2115         switch (reg) {
2116         case VCPU_REGS_RSP:
2117                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2118                 break;
2119         case VCPU_REGS_RIP:
2120                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2121                 break;
2122         case VCPU_EXREG_PDPTR:
2123                 if (enable_ept)
2124                         ept_save_pdptrs(vcpu);
2125                 break;
2126         default:
2127                 break;
2128         }
2129 }
2130
2131 static __init int cpu_has_kvm_support(void)
2132 {
2133         return cpu_has_vmx();
2134 }
2135
2136 static __init int vmx_disabled_by_bios(void)
2137 {
2138         u64 msr;
2139
2140         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2141         if (msr & FEATURE_CONTROL_LOCKED) {
2142                 /* launched w/ TXT and VMX disabled */
2143                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2144                         && tboot_enabled())
2145                         return 1;
2146                 /* launched w/o TXT and VMX only enabled w/ TXT */
2147                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2148                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2149                         && !tboot_enabled()) {
2150                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2151                                 "activate TXT before enabling KVM\n");
2152                         return 1;
2153                 }
2154                 /* launched w/o TXT and VMX disabled */
2155                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2156                         && !tboot_enabled())
2157                         return 1;
2158         }
2159
2160         return 0;
2161 }
2162
2163 static void kvm_cpu_vmxon(u64 addr)
2164 {
2165         cr4_set_bits(X86_CR4_VMXE);
2166         intel_pt_handle_vmx(1);
2167
2168         asm volatile ("vmxon %0" : : "m"(addr));
2169 }
2170
2171 static int hardware_enable(void)
2172 {
2173         int cpu = raw_smp_processor_id();
2174         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2175         u64 old, test_bits;
2176
2177         if (cr4_read_shadow() & X86_CR4_VMXE)
2178                 return -EBUSY;
2179
2180         /*
2181          * This can happen if we hot-added a CPU but failed to allocate
2182          * VP assist page for it.
2183          */
2184         if (static_branch_unlikely(&enable_evmcs) &&
2185             !hv_get_vp_assist_page(cpu))
2186                 return -EFAULT;
2187
2188         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2189         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2190         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2191
2192         /*
2193          * Now we can enable the vmclear operation in kdump
2194          * since the loaded_vmcss_on_cpu list on this cpu
2195          * has been initialized.
2196          *
2197          * Though the cpu is not in VMX operation now, there
2198          * is no problem to enable the vmclear operation
2199          * for the loaded_vmcss_on_cpu list is empty!
2200          */
2201         crash_enable_local_vmclear(cpu);
2202
2203         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2204
2205         test_bits = FEATURE_CONTROL_LOCKED;
2206         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2207         if (tboot_enabled())
2208                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2209
2210         if ((old & test_bits) != test_bits) {
2211                 /* enable and lock */
2212                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2213         }
2214         kvm_cpu_vmxon(phys_addr);
2215         if (enable_ept)
2216                 ept_sync_global();
2217
2218         return 0;
2219 }
2220
2221 static void vmclear_local_loaded_vmcss(void)
2222 {
2223         int cpu = raw_smp_processor_id();
2224         struct loaded_vmcs *v, *n;
2225
2226         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2227                                  loaded_vmcss_on_cpu_link)
2228                 __loaded_vmcs_clear(v);
2229 }
2230
2231
2232 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2233  * tricks.
2234  */
2235 static void kvm_cpu_vmxoff(void)
2236 {
2237         asm volatile (__ex("vmxoff"));
2238
2239         intel_pt_handle_vmx(0);
2240         cr4_clear_bits(X86_CR4_VMXE);
2241 }
2242
2243 static void hardware_disable(void)
2244 {
2245         vmclear_local_loaded_vmcss();
2246         kvm_cpu_vmxoff();
2247 }
2248
2249 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2250                                       u32 msr, u32 *result)
2251 {
2252         u32 vmx_msr_low, vmx_msr_high;
2253         u32 ctl = ctl_min | ctl_opt;
2254
2255         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2256
2257         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2258         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2259
2260         /* Ensure minimum (required) set of control bits are supported. */
2261         if (ctl_min & ~ctl)
2262                 return -EIO;
2263
2264         *result = ctl;
2265         return 0;
2266 }
2267
2268 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2269                                     struct vmx_capability *vmx_cap)
2270 {
2271         u32 vmx_msr_low, vmx_msr_high;
2272         u32 min, opt, min2, opt2;
2273         u32 _pin_based_exec_control = 0;
2274         u32 _cpu_based_exec_control = 0;
2275         u32 _cpu_based_2nd_exec_control = 0;
2276         u32 _vmexit_control = 0;
2277         u32 _vmentry_control = 0;
2278
2279         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2280         min = CPU_BASED_HLT_EXITING |
2281 #ifdef CONFIG_X86_64
2282               CPU_BASED_CR8_LOAD_EXITING |
2283               CPU_BASED_CR8_STORE_EXITING |
2284 #endif
2285               CPU_BASED_CR3_LOAD_EXITING |
2286               CPU_BASED_CR3_STORE_EXITING |
2287               CPU_BASED_UNCOND_IO_EXITING |
2288               CPU_BASED_MOV_DR_EXITING |
2289               CPU_BASED_USE_TSC_OFFSETING |
2290               CPU_BASED_MWAIT_EXITING |
2291               CPU_BASED_MONITOR_EXITING |
2292               CPU_BASED_INVLPG_EXITING |
2293               CPU_BASED_RDPMC_EXITING;
2294
2295         opt = CPU_BASED_TPR_SHADOW |
2296               CPU_BASED_USE_MSR_BITMAPS |
2297               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2298         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2299                                 &_cpu_based_exec_control) < 0)
2300                 return -EIO;
2301 #ifdef CONFIG_X86_64
2302         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2303                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2304                                            ~CPU_BASED_CR8_STORE_EXITING;
2305 #endif
2306         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2307                 min2 = 0;
2308                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2309                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2310                         SECONDARY_EXEC_WBINVD_EXITING |
2311                         SECONDARY_EXEC_ENABLE_VPID |
2312                         SECONDARY_EXEC_ENABLE_EPT |
2313                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2314                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2315                         SECONDARY_EXEC_DESC |
2316                         SECONDARY_EXEC_RDTSCP |
2317                         SECONDARY_EXEC_ENABLE_INVPCID |
2318                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2319                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2320                         SECONDARY_EXEC_SHADOW_VMCS |
2321                         SECONDARY_EXEC_XSAVES |
2322                         SECONDARY_EXEC_RDSEED_EXITING |
2323                         SECONDARY_EXEC_RDRAND_EXITING |
2324                         SECONDARY_EXEC_ENABLE_PML |
2325                         SECONDARY_EXEC_TSC_SCALING |
2326                         SECONDARY_EXEC_PT_USE_GPA |
2327                         SECONDARY_EXEC_PT_CONCEAL_VMX |
2328                         SECONDARY_EXEC_ENABLE_VMFUNC |
2329                         SECONDARY_EXEC_ENCLS_EXITING;
2330                 if (adjust_vmx_controls(min2, opt2,
2331                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2332                                         &_cpu_based_2nd_exec_control) < 0)
2333                         return -EIO;
2334         }
2335 #ifndef CONFIG_X86_64
2336         if (!(_cpu_based_2nd_exec_control &
2337                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2338                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2339 #endif
2340
2341         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2342                 _cpu_based_2nd_exec_control &= ~(
2343                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2344                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2345                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2346
2347         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2348                 &vmx_cap->ept, &vmx_cap->vpid);
2349
2350         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2351                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2352                    enabled */
2353                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2354                                              CPU_BASED_CR3_STORE_EXITING |
2355                                              CPU_BASED_INVLPG_EXITING);
2356         } else if (vmx_cap->ept) {
2357                 vmx_cap->ept = 0;
2358                 pr_warn_once("EPT CAP should not exist if not support "
2359                                 "1-setting enable EPT VM-execution control\n");
2360         }
2361         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2362                 vmx_cap->vpid) {
2363                 vmx_cap->vpid = 0;
2364                 pr_warn_once("VPID CAP should not exist if not support "
2365                                 "1-setting enable VPID VM-execution control\n");
2366         }
2367
2368         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2369 #ifdef CONFIG_X86_64
2370         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2371 #endif
2372         opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2373               VM_EXIT_LOAD_IA32_PAT |
2374               VM_EXIT_LOAD_IA32_EFER |
2375               VM_EXIT_CLEAR_BNDCFGS |
2376               VM_EXIT_PT_CONCEAL_PIP |
2377               VM_EXIT_CLEAR_IA32_RTIT_CTL;
2378         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2379                                 &_vmexit_control) < 0)
2380                 return -EIO;
2381
2382         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2383         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2384                  PIN_BASED_VMX_PREEMPTION_TIMER;
2385         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2386                                 &_pin_based_exec_control) < 0)
2387                 return -EIO;
2388
2389         if (cpu_has_broken_vmx_preemption_timer())
2390                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2391         if (!(_cpu_based_2nd_exec_control &
2392                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2393                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2394
2395         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2396         opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2397               VM_ENTRY_LOAD_IA32_PAT |
2398               VM_ENTRY_LOAD_IA32_EFER |
2399               VM_ENTRY_LOAD_BNDCFGS |
2400               VM_ENTRY_PT_CONCEAL_PIP |
2401               VM_ENTRY_LOAD_IA32_RTIT_CTL;
2402         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2403                                 &_vmentry_control) < 0)
2404                 return -EIO;
2405
2406         /*
2407          * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2408          * can't be used due to an errata where VM Exit may incorrectly clear
2409          * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2410          * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2411          */
2412         if (boot_cpu_data.x86 == 0x6) {
2413                 switch (boot_cpu_data.x86_model) {
2414                 case 26: /* AAK155 */
2415                 case 30: /* AAP115 */
2416                 case 37: /* AAT100 */
2417                 case 44: /* BC86,AAY89,BD102 */
2418                 case 46: /* BA97 */
2419                         _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2420                         _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2421                         pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2422                                         "does not work properly. Using workaround\n");
2423                         break;
2424                 default:
2425                         break;
2426                 }
2427         }
2428
2429
2430         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2431
2432         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2433         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2434                 return -EIO;
2435
2436 #ifdef CONFIG_X86_64
2437         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2438         if (vmx_msr_high & (1u<<16))
2439                 return -EIO;
2440 #endif
2441
2442         /* Require Write-Back (WB) memory type for VMCS accesses. */
2443         if (((vmx_msr_high >> 18) & 15) != 6)
2444                 return -EIO;
2445
2446         vmcs_conf->size = vmx_msr_high & 0x1fff;
2447         vmcs_conf->order = get_order(vmcs_conf->size);
2448         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2449
2450         vmcs_conf->revision_id = vmx_msr_low;
2451
2452         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2453         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2454         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2455         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2456         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2457
2458         if (static_branch_unlikely(&enable_evmcs))
2459                 evmcs_sanitize_exec_ctrls(vmcs_conf);
2460
2461         return 0;
2462 }
2463
2464 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2465 {
2466         int node = cpu_to_node(cpu);
2467         struct page *pages;
2468         struct vmcs *vmcs;
2469
2470         pages = __alloc_pages_node(node, flags, vmcs_config.order);
2471         if (!pages)
2472                 return NULL;
2473         vmcs = page_address(pages);
2474         memset(vmcs, 0, vmcs_config.size);
2475
2476         /* KVM supports Enlightened VMCS v1 only */
2477         if (static_branch_unlikely(&enable_evmcs))
2478                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2479         else
2480                 vmcs->hdr.revision_id = vmcs_config.revision_id;
2481
2482         if (shadow)
2483                 vmcs->hdr.shadow_vmcs = 1;
2484         return vmcs;
2485 }
2486
2487 void free_vmcs(struct vmcs *vmcs)
2488 {
2489         free_pages((unsigned long)vmcs, vmcs_config.order);
2490 }
2491
2492 /*
2493  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2494  */
2495 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2496 {
2497         if (!loaded_vmcs->vmcs)
2498                 return;
2499         loaded_vmcs_clear(loaded_vmcs);
2500         free_vmcs(loaded_vmcs->vmcs);
2501         loaded_vmcs->vmcs = NULL;
2502         if (loaded_vmcs->msr_bitmap)
2503                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2504         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2505 }
2506
2507 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2508 {
2509         loaded_vmcs->vmcs = alloc_vmcs(false);
2510         if (!loaded_vmcs->vmcs)
2511                 return -ENOMEM;
2512
2513         loaded_vmcs->shadow_vmcs = NULL;
2514         loaded_vmcs->hv_timer_soft_disabled = false;
2515         loaded_vmcs_init(loaded_vmcs);
2516
2517         if (cpu_has_vmx_msr_bitmap()) {
2518                 loaded_vmcs->msr_bitmap = (unsigned long *)
2519                                 __get_free_page(GFP_KERNEL_ACCOUNT);
2520                 if (!loaded_vmcs->msr_bitmap)
2521                         goto out_vmcs;
2522                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2523
2524                 if (IS_ENABLED(CONFIG_HYPERV) &&
2525                     static_branch_unlikely(&enable_evmcs) &&
2526                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2527                         struct hv_enlightened_vmcs *evmcs =
2528                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2529
2530                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
2531                 }
2532         }
2533
2534         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2535         memset(&loaded_vmcs->controls_shadow, 0,
2536                 sizeof(struct vmcs_controls_shadow));
2537
2538         return 0;
2539
2540 out_vmcs:
2541         free_loaded_vmcs(loaded_vmcs);
2542         return -ENOMEM;
2543 }
2544
2545 static void free_kvm_area(void)
2546 {
2547         int cpu;
2548
2549         for_each_possible_cpu(cpu) {
2550                 free_vmcs(per_cpu(vmxarea, cpu));
2551                 per_cpu(vmxarea, cpu) = NULL;
2552         }
2553 }
2554
2555 static __init int alloc_kvm_area(void)
2556 {
2557         int cpu;
2558
2559         for_each_possible_cpu(cpu) {
2560                 struct vmcs *vmcs;
2561
2562                 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2563                 if (!vmcs) {
2564                         free_kvm_area();
2565                         return -ENOMEM;
2566                 }
2567
2568                 /*
2569                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
2570                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2571                  * revision_id reported by MSR_IA32_VMX_BASIC.
2572                  *
2573                  * However, even though not explicitly documented by
2574                  * TLFS, VMXArea passed as VMXON argument should
2575                  * still be marked with revision_id reported by
2576                  * physical CPU.
2577                  */
2578                 if (static_branch_unlikely(&enable_evmcs))
2579                         vmcs->hdr.revision_id = vmcs_config.revision_id;
2580
2581                 per_cpu(vmxarea, cpu) = vmcs;
2582         }
2583         return 0;
2584 }
2585
2586 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2587                 struct kvm_segment *save)
2588 {
2589         if (!emulate_invalid_guest_state) {
2590                 /*
2591                  * CS and SS RPL should be equal during guest entry according
2592                  * to VMX spec, but in reality it is not always so. Since vcpu
2593                  * is in the middle of the transition from real mode to
2594                  * protected mode it is safe to assume that RPL 0 is a good
2595                  * default value.
2596                  */
2597                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2598                         save->selector &= ~SEGMENT_RPL_MASK;
2599                 save->dpl = save->selector & SEGMENT_RPL_MASK;
2600                 save->s = 1;
2601         }
2602         vmx_set_segment(vcpu, save, seg);
2603 }
2604
2605 static void enter_pmode(struct kvm_vcpu *vcpu)
2606 {
2607         unsigned long flags;
2608         struct vcpu_vmx *vmx = to_vmx(vcpu);
2609
2610         /*
2611          * Update real mode segment cache. It may be not up-to-date if sement
2612          * register was written while vcpu was in a guest mode.
2613          */
2614         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2615         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2616         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2617         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2618         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2619         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2620
2621         vmx->rmode.vm86_active = 0;
2622
2623         vmx_segment_cache_clear(vmx);
2624
2625         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2626
2627         flags = vmcs_readl(GUEST_RFLAGS);
2628         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2629         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2630         vmcs_writel(GUEST_RFLAGS, flags);
2631
2632         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2633                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2634
2635         update_exception_bitmap(vcpu);
2636
2637         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2638         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2639         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2640         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2641         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2642         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2643 }
2644
2645 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2646 {
2647         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2648         struct kvm_segment var = *save;
2649
2650         var.dpl = 0x3;
2651         if (seg == VCPU_SREG_CS)
2652                 var.type = 0x3;
2653
2654         if (!emulate_invalid_guest_state) {
2655                 var.selector = var.base >> 4;
2656                 var.base = var.base & 0xffff0;
2657                 var.limit = 0xffff;
2658                 var.g = 0;
2659                 var.db = 0;
2660                 var.present = 1;
2661                 var.s = 1;
2662                 var.l = 0;
2663                 var.unusable = 0;
2664                 var.type = 0x3;
2665                 var.avl = 0;
2666                 if (save->base & 0xf)
2667                         printk_once(KERN_WARNING "kvm: segment base is not "
2668                                         "paragraph aligned when entering "
2669                                         "protected mode (seg=%d)", seg);
2670         }
2671
2672         vmcs_write16(sf->selector, var.selector);
2673         vmcs_writel(sf->base, var.base);
2674         vmcs_write32(sf->limit, var.limit);
2675         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2676 }
2677
2678 static void enter_rmode(struct kvm_vcpu *vcpu)
2679 {
2680         unsigned long flags;
2681         struct vcpu_vmx *vmx = to_vmx(vcpu);
2682         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2683
2684         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2685         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2686         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2687         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2688         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2689         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2690         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2691
2692         vmx->rmode.vm86_active = 1;
2693
2694         /*
2695          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2696          * vcpu. Warn the user that an update is overdue.
2697          */
2698         if (!kvm_vmx->tss_addr)
2699                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2700                              "called before entering vcpu\n");
2701
2702         vmx_segment_cache_clear(vmx);
2703
2704         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2705         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2706         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2707
2708         flags = vmcs_readl(GUEST_RFLAGS);
2709         vmx->rmode.save_rflags = flags;
2710
2711         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2712
2713         vmcs_writel(GUEST_RFLAGS, flags);
2714         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2715         update_exception_bitmap(vcpu);
2716
2717         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2718         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2719         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2720         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2721         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2722         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2723
2724         kvm_mmu_reset_context(vcpu);
2725 }
2726
2727 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2728 {
2729         struct vcpu_vmx *vmx = to_vmx(vcpu);
2730         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2731
2732         if (!msr)
2733                 return;
2734
2735         vcpu->arch.efer = efer;
2736         if (efer & EFER_LMA) {
2737                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2738                 msr->data = efer;
2739         } else {
2740                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2741
2742                 msr->data = efer & ~EFER_LME;
2743         }
2744         setup_msrs(vmx);
2745 }
2746
2747 #ifdef CONFIG_X86_64
2748
2749 static void enter_lmode(struct kvm_vcpu *vcpu)
2750 {
2751         u32 guest_tr_ar;
2752
2753         vmx_segment_cache_clear(to_vmx(vcpu));
2754
2755         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2756         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2757                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2758                                      __func__);
2759                 vmcs_write32(GUEST_TR_AR_BYTES,
2760                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2761                              | VMX_AR_TYPE_BUSY_64_TSS);
2762         }
2763         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2764 }
2765
2766 static void exit_lmode(struct kvm_vcpu *vcpu)
2767 {
2768         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2769         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2770 }
2771
2772 #endif
2773
2774 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2775 {
2776         int vpid = to_vmx(vcpu)->vpid;
2777
2778         if (!vpid_sync_vcpu_addr(vpid, addr))
2779                 vpid_sync_context(vpid);
2780
2781         /*
2782          * If VPIDs are not supported or enabled, then the above is a no-op.
2783          * But we don't really need a TLB flush in that case anyway, because
2784          * each VM entry/exit includes an implicit flush when VPID is 0.
2785          */
2786 }
2787
2788 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2789 {
2790         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2791
2792         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2793         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2794 }
2795
2796 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2797 {
2798         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2799                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2800         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2801 }
2802
2803 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2804 {
2805         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2806
2807         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2808         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2809 }
2810
2811 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2812 {
2813         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2814
2815         if (!test_bit(VCPU_EXREG_PDPTR,
2816                       (unsigned long *)&vcpu->arch.regs_dirty))
2817                 return;
2818
2819         if (is_pae_paging(vcpu)) {
2820                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2821                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2822                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2823                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2824         }
2825 }
2826
2827 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2828 {
2829         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2830
2831         if (is_pae_paging(vcpu)) {
2832                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2833                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2834                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2835                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2836         }
2837
2838         __set_bit(VCPU_EXREG_PDPTR,
2839                   (unsigned long *)&vcpu->arch.regs_avail);
2840         __set_bit(VCPU_EXREG_PDPTR,
2841                   (unsigned long *)&vcpu->arch.regs_dirty);
2842 }
2843
2844 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2845                                         unsigned long cr0,
2846                                         struct kvm_vcpu *vcpu)
2847 {
2848         struct vcpu_vmx *vmx = to_vmx(vcpu);
2849
2850         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2851                 vmx_decache_cr3(vcpu);
2852         if (!(cr0 & X86_CR0_PG)) {
2853                 /* From paging/starting to nonpaging */
2854                 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2855                                           CPU_BASED_CR3_STORE_EXITING);
2856                 vcpu->arch.cr0 = cr0;
2857                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2858         } else if (!is_paging(vcpu)) {
2859                 /* From nonpaging to paging */
2860                 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2861                                             CPU_BASED_CR3_STORE_EXITING);
2862                 vcpu->arch.cr0 = cr0;
2863                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2864         }
2865
2866         if (!(cr0 & X86_CR0_WP))
2867                 *hw_cr0 &= ~X86_CR0_WP;
2868 }
2869
2870 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2871 {
2872         struct vcpu_vmx *vmx = to_vmx(vcpu);
2873         unsigned long hw_cr0;
2874
2875         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2876         if (enable_unrestricted_guest)
2877                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2878         else {
2879                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2880
2881                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2882                         enter_pmode(vcpu);
2883
2884                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2885                         enter_rmode(vcpu);
2886         }
2887
2888 #ifdef CONFIG_X86_64
2889         if (vcpu->arch.efer & EFER_LME) {
2890                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2891                         enter_lmode(vcpu);
2892                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2893                         exit_lmode(vcpu);
2894         }
2895 #endif
2896
2897         if (enable_ept && !enable_unrestricted_guest)
2898                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2899
2900         vmcs_writel(CR0_READ_SHADOW, cr0);
2901         vmcs_writel(GUEST_CR0, hw_cr0);
2902         vcpu->arch.cr0 = cr0;
2903
2904         /* depends on vcpu->arch.cr0 to be set to a new value */
2905         vmx->emulation_required = emulation_required(vcpu);
2906 }
2907
2908 static int get_ept_level(struct kvm_vcpu *vcpu)
2909 {
2910         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2911                 return 5;
2912         return 4;
2913 }
2914
2915 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2916 {
2917         u64 eptp = VMX_EPTP_MT_WB;
2918
2919         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2920
2921         if (enable_ept_ad_bits &&
2922             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2923                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2924         eptp |= (root_hpa & PAGE_MASK);
2925
2926         return eptp;
2927 }
2928
2929 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2930 {
2931         struct kvm *kvm = vcpu->kvm;
2932         unsigned long guest_cr3;
2933         u64 eptp;
2934
2935         guest_cr3 = cr3;
2936         if (enable_ept) {
2937                 eptp = construct_eptp(vcpu, cr3);
2938                 vmcs_write64(EPT_POINTER, eptp);
2939
2940                 if (kvm_x86_ops->tlb_remote_flush) {
2941                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2942                         to_vmx(vcpu)->ept_pointer = eptp;
2943                         to_kvm_vmx(kvm)->ept_pointers_match
2944                                 = EPT_POINTERS_CHECK;
2945                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2946                 }
2947
2948                 if (enable_unrestricted_guest || is_paging(vcpu) ||
2949                     is_guest_mode(vcpu))
2950                         guest_cr3 = kvm_read_cr3(vcpu);
2951                 else
2952                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
2953                 ept_load_pdptrs(vcpu);
2954         }
2955
2956         vmcs_writel(GUEST_CR3, guest_cr3);
2957 }
2958
2959 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2960 {
2961         struct vcpu_vmx *vmx = to_vmx(vcpu);
2962         /*
2963          * Pass through host's Machine Check Enable value to hw_cr4, which
2964          * is in force while we are in guest mode.  Do not let guests control
2965          * this bit, even if host CR4.MCE == 0.
2966          */
2967         unsigned long hw_cr4;
2968
2969         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2970         if (enable_unrestricted_guest)
2971                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2972         else if (vmx->rmode.vm86_active)
2973                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2974         else
2975                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
2976
2977         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2978                 if (cr4 & X86_CR4_UMIP) {
2979                         secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
2980                         hw_cr4 &= ~X86_CR4_UMIP;
2981                 } else if (!is_guest_mode(vcpu) ||
2982                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
2983                         secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
2984                 }
2985         }
2986
2987         if (cr4 & X86_CR4_VMXE) {
2988                 /*
2989                  * To use VMXON (and later other VMX instructions), a guest
2990                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2991                  * So basically the check on whether to allow nested VMX
2992                  * is here.  We operate under the default treatment of SMM,
2993                  * so VMX cannot be enabled under SMM.
2994                  */
2995                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
2996                         return 1;
2997         }
2998
2999         if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3000                 return 1;
3001
3002         vcpu->arch.cr4 = cr4;
3003
3004         if (!enable_unrestricted_guest) {
3005                 if (enable_ept) {
3006                         if (!is_paging(vcpu)) {
3007                                 hw_cr4 &= ~X86_CR4_PAE;
3008                                 hw_cr4 |= X86_CR4_PSE;
3009                         } else if (!(cr4 & X86_CR4_PAE)) {
3010                                 hw_cr4 &= ~X86_CR4_PAE;
3011                         }
3012                 }
3013
3014                 /*
3015                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3016                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3017                  * to be manually disabled when guest switches to non-paging
3018                  * mode.
3019                  *
3020                  * If !enable_unrestricted_guest, the CPU is always running
3021                  * with CR0.PG=1 and CR4 needs to be modified.
3022                  * If enable_unrestricted_guest, the CPU automatically
3023                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3024                  */
3025                 if (!is_paging(vcpu))
3026                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3027         }
3028
3029         vmcs_writel(CR4_READ_SHADOW, cr4);
3030         vmcs_writel(GUEST_CR4, hw_cr4);
3031         return 0;
3032 }
3033
3034 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3035 {
3036         struct vcpu_vmx *vmx = to_vmx(vcpu);
3037         u32 ar;
3038
3039         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3040                 *var = vmx->rmode.segs[seg];
3041                 if (seg == VCPU_SREG_TR
3042                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3043                         return;
3044                 var->base = vmx_read_guest_seg_base(vmx, seg);
3045                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3046                 return;
3047         }
3048         var->base = vmx_read_guest_seg_base(vmx, seg);
3049         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3050         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3051         ar = vmx_read_guest_seg_ar(vmx, seg);
3052         var->unusable = (ar >> 16) & 1;
3053         var->type = ar & 15;
3054         var->s = (ar >> 4) & 1;
3055         var->dpl = (ar >> 5) & 3;
3056         /*
3057          * Some userspaces do not preserve unusable property. Since usable
3058          * segment has to be present according to VMX spec we can use present
3059          * property to amend userspace bug by making unusable segment always
3060          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3061          * segment as unusable.
3062          */
3063         var->present = !var->unusable;
3064         var->avl = (ar >> 12) & 1;
3065         var->l = (ar >> 13) & 1;
3066         var->db = (ar >> 14) & 1;
3067         var->g = (ar >> 15) & 1;
3068 }
3069
3070 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3071 {
3072         struct kvm_segment s;
3073
3074         if (to_vmx(vcpu)->rmode.vm86_active) {
3075                 vmx_get_segment(vcpu, &s, seg);
3076                 return s.base;
3077         }
3078         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3079 }
3080
3081 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3082 {
3083         struct vcpu_vmx *vmx = to_vmx(vcpu);
3084
3085         if (unlikely(vmx->rmode.vm86_active))
3086                 return 0;
3087         else {
3088                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3089                 return VMX_AR_DPL(ar);
3090         }
3091 }
3092
3093 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3094 {
3095         u32 ar;
3096
3097         if (var->unusable || !var->present)
3098                 ar = 1 << 16;
3099         else {
3100                 ar = var->type & 15;
3101                 ar |= (var->s & 1) << 4;
3102                 ar |= (var->dpl & 3) << 5;
3103                 ar |= (var->present & 1) << 7;
3104                 ar |= (var->avl & 1) << 12;
3105                 ar |= (var->l & 1) << 13;
3106                 ar |= (var->db & 1) << 14;
3107                 ar |= (var->g & 1) << 15;
3108         }
3109
3110         return ar;
3111 }
3112
3113 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3114 {
3115         struct vcpu_vmx *vmx = to_vmx(vcpu);
3116         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3117
3118         vmx_segment_cache_clear(vmx);
3119
3120         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3121                 vmx->rmode.segs[seg] = *var;
3122                 if (seg == VCPU_SREG_TR)
3123                         vmcs_write16(sf->selector, var->selector);
3124                 else if (var->s)
3125                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3126                 goto out;
3127         }
3128
3129         vmcs_writel(sf->base, var->base);
3130         vmcs_write32(sf->limit, var->limit);
3131         vmcs_write16(sf->selector, var->selector);
3132
3133         /*
3134          *   Fix the "Accessed" bit in AR field of segment registers for older
3135          * qemu binaries.
3136          *   IA32 arch specifies that at the time of processor reset the
3137          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3138          * is setting it to 0 in the userland code. This causes invalid guest
3139          * state vmexit when "unrestricted guest" mode is turned on.
3140          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3141          * tree. Newer qemu binaries with that qemu fix would not need this
3142          * kvm hack.
3143          */
3144         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3145                 var->type |= 0x1; /* Accessed */
3146
3147         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3148
3149 out:
3150         vmx->emulation_required = emulation_required(vcpu);
3151 }
3152
3153 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3154 {
3155         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3156
3157         *db = (ar >> 14) & 1;
3158         *l = (ar >> 13) & 1;
3159 }
3160
3161 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3162 {
3163         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3164         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3165 }
3166
3167 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3168 {
3169         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3170         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3171 }
3172
3173 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3174 {
3175         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3176         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3177 }
3178
3179 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3180 {
3181         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3182         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3183 }
3184
3185 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3186 {
3187         struct kvm_segment var;
3188         u32 ar;
3189
3190         vmx_get_segment(vcpu, &var, seg);
3191         var.dpl = 0x3;
3192         if (seg == VCPU_SREG_CS)
3193                 var.type = 0x3;
3194         ar = vmx_segment_access_rights(&var);
3195
3196         if (var.base != (var.selector << 4))
3197                 return false;
3198         if (var.limit != 0xffff)
3199                 return false;
3200         if (ar != 0xf3)
3201                 return false;
3202
3203         return true;
3204 }
3205
3206 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3207 {
3208         struct kvm_segment cs;
3209         unsigned int cs_rpl;
3210
3211         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3212         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3213
3214         if (cs.unusable)
3215                 return false;
3216         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3217                 return false;
3218         if (!cs.s)
3219                 return false;
3220         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3221                 if (cs.dpl > cs_rpl)
3222                         return false;
3223         } else {
3224                 if (cs.dpl != cs_rpl)
3225                         return false;
3226         }
3227         if (!cs.present)
3228                 return false;
3229
3230         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3231         return true;
3232 }
3233
3234 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3235 {
3236         struct kvm_segment ss;
3237         unsigned int ss_rpl;
3238
3239         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3240         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3241
3242         if (ss.unusable)
3243                 return true;
3244         if (ss.type != 3 && ss.type != 7)
3245                 return false;
3246         if (!ss.s)
3247                 return false;
3248         if (ss.dpl != ss_rpl) /* DPL != RPL */
3249                 return false;
3250         if (!ss.present)
3251                 return false;
3252
3253         return true;
3254 }
3255
3256 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3257 {
3258         struct kvm_segment var;
3259         unsigned int rpl;
3260
3261         vmx_get_segment(vcpu, &var, seg);
3262         rpl = var.selector & SEGMENT_RPL_MASK;
3263
3264         if (var.unusable)
3265                 return true;
3266         if (!var.s)
3267                 return false;
3268         if (!var.present)
3269                 return false;
3270         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3271                 if (var.dpl < rpl) /* DPL < RPL */
3272                         return false;
3273         }
3274
3275         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3276          * rights flags
3277          */
3278         return true;
3279 }
3280
3281 static bool tr_valid(struct kvm_vcpu *vcpu)
3282 {
3283         struct kvm_segment tr;
3284
3285         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3286
3287         if (tr.unusable)
3288                 return false;
3289         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3290                 return false;
3291         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3292                 return false;
3293         if (!tr.present)
3294                 return false;
3295
3296         return true;
3297 }
3298
3299 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3300 {
3301         struct kvm_segment ldtr;
3302
3303         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3304
3305         if (ldtr.unusable)
3306                 return true;
3307         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3308                 return false;
3309         if (ldtr.type != 2)
3310                 return false;
3311         if (!ldtr.present)
3312                 return false;
3313
3314         return true;
3315 }
3316
3317 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3318 {
3319         struct kvm_segment cs, ss;
3320
3321         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3322         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3323
3324         return ((cs.selector & SEGMENT_RPL_MASK) ==
3325                  (ss.selector & SEGMENT_RPL_MASK));
3326 }
3327
3328 /*
3329  * Check if guest state is valid. Returns true if valid, false if
3330  * not.
3331  * We assume that registers are always usable
3332  */
3333 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3334 {
3335         if (enable_unrestricted_guest)
3336                 return true;
3337
3338         /* real mode guest state checks */
3339         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3340                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3341                         return false;
3342                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3343                         return false;
3344                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3345                         return false;
3346                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3347                         return false;
3348                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3349                         return false;
3350                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3351                         return false;
3352         } else {
3353         /* protected mode guest state checks */
3354                 if (!cs_ss_rpl_check(vcpu))
3355                         return false;
3356                 if (!code_segment_valid(vcpu))
3357                         return false;
3358                 if (!stack_segment_valid(vcpu))
3359                         return false;
3360                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3361                         return false;
3362                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3363                         return false;
3364                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3365                         return false;
3366                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3367                         return false;
3368                 if (!tr_valid(vcpu))
3369                         return false;
3370                 if (!ldtr_valid(vcpu))
3371                         return false;
3372         }
3373         /* TODO:
3374          * - Add checks on RIP
3375          * - Add checks on RFLAGS
3376          */
3377
3378         return true;
3379 }
3380
3381 static int init_rmode_tss(struct kvm *kvm)
3382 {
3383         gfn_t fn;
3384         u16 data = 0;
3385         int idx, r;
3386
3387         idx = srcu_read_lock(&kvm->srcu);
3388         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3389         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3390         if (r < 0)
3391                 goto out;
3392         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3393         r = kvm_write_guest_page(kvm, fn++, &data,
3394                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3395         if (r < 0)
3396                 goto out;
3397         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3398         if (r < 0)
3399                 goto out;
3400         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3401         if (r < 0)
3402                 goto out;
3403         data = ~0;
3404         r = kvm_write_guest_page(kvm, fn, &data,
3405                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3406                                  sizeof(u8));
3407 out:
3408         srcu_read_unlock(&kvm->srcu, idx);
3409         return r;
3410 }
3411
3412 static int init_rmode_identity_map(struct kvm *kvm)
3413 {
3414         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3415         int i, idx, r = 0;
3416         kvm_pfn_t identity_map_pfn;
3417         u32 tmp;
3418
3419         /* Protect kvm_vmx->ept_identity_pagetable_done. */
3420         mutex_lock(&kvm->slots_lock);
3421
3422         if (likely(kvm_vmx->ept_identity_pagetable_done))
3423                 goto out2;
3424
3425         if (!kvm_vmx->ept_identity_map_addr)
3426                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3427         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3428
3429         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3430                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3431         if (r < 0)
3432                 goto out2;
3433
3434         idx = srcu_read_lock(&kvm->srcu);
3435         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3436         if (r < 0)
3437                 goto out;
3438         /* Set up identity-mapping pagetable for EPT in real mode */
3439         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3440                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3441                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3442                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3443                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3444                 if (r < 0)
3445                         goto out;
3446         }
3447         kvm_vmx->ept_identity_pagetable_done = true;
3448
3449 out:
3450         srcu_read_unlock(&kvm->srcu, idx);
3451
3452 out2:
3453         mutex_unlock(&kvm->slots_lock);
3454         return r;
3455 }
3456
3457 static void seg_setup(int seg)
3458 {
3459         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3460         unsigned int ar;
3461
3462         vmcs_write16(sf->selector, 0);
3463         vmcs_writel(sf->base, 0);
3464         vmcs_write32(sf->limit, 0xffff);
3465         ar = 0x93;
3466         if (seg == VCPU_SREG_CS)
3467                 ar |= 0x08; /* code segment */
3468
3469         vmcs_write32(sf->ar_bytes, ar);
3470 }
3471
3472 static int alloc_apic_access_page(struct kvm *kvm)
3473 {
3474         struct page *page;
3475         int r = 0;
3476
3477         mutex_lock(&kvm->slots_lock);
3478         if (kvm->arch.apic_access_page_done)
3479                 goto out;
3480         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3481                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3482         if (r)
3483                 goto out;
3484
3485         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3486         if (is_error_page(page)) {
3487                 r = -EFAULT;
3488                 goto out;
3489         }
3490
3491         /*
3492          * Do not pin the page in memory, so that memory hot-unplug
3493          * is able to migrate it.
3494          */
3495         put_page(page);
3496         kvm->arch.apic_access_page_done = true;
3497 out:
3498         mutex_unlock(&kvm->slots_lock);
3499         return r;
3500 }
3501
3502 int allocate_vpid(void)
3503 {
3504         int vpid;
3505
3506         if (!enable_vpid)
3507                 return 0;
3508         spin_lock(&vmx_vpid_lock);
3509         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3510         if (vpid < VMX_NR_VPIDS)
3511                 __set_bit(vpid, vmx_vpid_bitmap);
3512         else
3513                 vpid = 0;
3514         spin_unlock(&vmx_vpid_lock);
3515         return vpid;
3516 }
3517
3518 void free_vpid(int vpid)
3519 {
3520         if (!enable_vpid || vpid == 0)
3521                 return;
3522         spin_lock(&vmx_vpid_lock);
3523         __clear_bit(vpid, vmx_vpid_bitmap);
3524         spin_unlock(&vmx_vpid_lock);
3525 }
3526
3527 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3528                                                           u32 msr, int type)
3529 {
3530         int f = sizeof(unsigned long);
3531
3532         if (!cpu_has_vmx_msr_bitmap())
3533                 return;
3534
3535         if (static_branch_unlikely(&enable_evmcs))
3536                 evmcs_touch_msr_bitmap();
3537
3538         /*
3539          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3540          * have the write-low and read-high bitmap offsets the wrong way round.
3541          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3542          */
3543         if (msr <= 0x1fff) {
3544                 if (type & MSR_TYPE_R)
3545                         /* read-low */
3546                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3547
3548                 if (type & MSR_TYPE_W)
3549                         /* write-low */
3550                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3551
3552         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3553                 msr &= 0x1fff;
3554                 if (type & MSR_TYPE_R)
3555                         /* read-high */
3556                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3557
3558                 if (type & MSR_TYPE_W)
3559                         /* write-high */
3560                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3561
3562         }
3563 }
3564
3565 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3566                                                          u32 msr, int type)
3567 {
3568         int f = sizeof(unsigned long);
3569
3570         if (!cpu_has_vmx_msr_bitmap())
3571                 return;
3572
3573         if (static_branch_unlikely(&enable_evmcs))
3574                 evmcs_touch_msr_bitmap();
3575
3576         /*
3577          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3578          * have the write-low and read-high bitmap offsets the wrong way round.
3579          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3580          */
3581         if (msr <= 0x1fff) {
3582                 if (type & MSR_TYPE_R)
3583                         /* read-low */
3584                         __set_bit(msr, msr_bitmap + 0x000 / f);
3585
3586                 if (type & MSR_TYPE_W)
3587                         /* write-low */
3588                         __set_bit(msr, msr_bitmap + 0x800 / f);
3589
3590         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3591                 msr &= 0x1fff;
3592                 if (type & MSR_TYPE_R)
3593                         /* read-high */
3594                         __set_bit(msr, msr_bitmap + 0x400 / f);
3595
3596                 if (type & MSR_TYPE_W)
3597                         /* write-high */
3598                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3599
3600         }
3601 }
3602
3603 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3604                                                       u32 msr, int type, bool value)
3605 {
3606         if (value)
3607                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3608         else
3609                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3610 }
3611
3612 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3613 {
3614         u8 mode = 0;
3615
3616         if (cpu_has_secondary_exec_ctrls() &&
3617             (secondary_exec_controls_get(to_vmx(vcpu)) &
3618              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3619                 mode |= MSR_BITMAP_MODE_X2APIC;
3620                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3621                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3622         }
3623
3624         return mode;
3625 }
3626
3627 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3628                                          u8 mode)
3629 {
3630         int msr;
3631
3632         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3633                 unsigned word = msr / BITS_PER_LONG;
3634                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3635                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3636         }
3637
3638         if (mode & MSR_BITMAP_MODE_X2APIC) {
3639                 /*
3640                  * TPR reads and writes can be virtualized even if virtual interrupt
3641                  * delivery is not in use.
3642                  */
3643                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3644                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3645                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3646                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3647                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3648                 }
3649         }
3650 }
3651
3652 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3653 {
3654         struct vcpu_vmx *vmx = to_vmx(vcpu);
3655         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3656         u8 mode = vmx_msr_bitmap_mode(vcpu);
3657         u8 changed = mode ^ vmx->msr_bitmap_mode;
3658
3659         if (!changed)
3660                 return;
3661
3662         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3663                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3664
3665         vmx->msr_bitmap_mode = mode;
3666 }
3667
3668 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3669 {
3670         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3671         bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3672         u32 i;
3673
3674         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3675                                                         MSR_TYPE_RW, flag);
3676         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3677                                                         MSR_TYPE_RW, flag);
3678         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3679                                                         MSR_TYPE_RW, flag);
3680         vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3681                                                         MSR_TYPE_RW, flag);
3682         for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3683                 vmx_set_intercept_for_msr(msr_bitmap,
3684                         MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3685                 vmx_set_intercept_for_msr(msr_bitmap,
3686                         MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3687         }
3688 }
3689
3690 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3691 {
3692         return enable_apicv;
3693 }
3694
3695 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3696 {
3697         struct vcpu_vmx *vmx = to_vmx(vcpu);
3698         void *vapic_page;
3699         u32 vppr;
3700         int rvi;
3701
3702         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3703                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3704                 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3705                 return false;
3706
3707         rvi = vmx_get_rvi();
3708
3709         vapic_page = vmx->nested.virtual_apic_map.hva;
3710         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3711
3712         return ((rvi & 0xf0) > (vppr & 0xf0));
3713 }
3714
3715 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3716                                                      bool nested)
3717 {
3718 #ifdef CONFIG_SMP
3719         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3720
3721         if (vcpu->mode == IN_GUEST_MODE) {
3722                 /*
3723                  * The vector of interrupt to be delivered to vcpu had
3724                  * been set in PIR before this function.
3725                  *
3726                  * Following cases will be reached in this block, and
3727                  * we always send a notification event in all cases as
3728                  * explained below.
3729                  *
3730                  * Case 1: vcpu keeps in non-root mode. Sending a
3731                  * notification event posts the interrupt to vcpu.
3732                  *
3733                  * Case 2: vcpu exits to root mode and is still
3734                  * runnable. PIR will be synced to vIRR before the
3735                  * next vcpu entry. Sending a notification event in
3736                  * this case has no effect, as vcpu is not in root
3737                  * mode.
3738                  *
3739                  * Case 3: vcpu exits to root mode and is blocked.
3740                  * vcpu_block() has already synced PIR to vIRR and
3741                  * never blocks vcpu if vIRR is not cleared. Therefore,
3742                  * a blocked vcpu here does not wait for any requested
3743                  * interrupts in PIR, and sending a notification event
3744                  * which has no effect is safe here.
3745                  */
3746
3747                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3748                 return true;
3749         }
3750 #endif
3751         return false;
3752 }
3753
3754 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3755                                                 int vector)
3756 {
3757         struct vcpu_vmx *vmx = to_vmx(vcpu);
3758
3759         if (is_guest_mode(vcpu) &&
3760             vector == vmx->nested.posted_intr_nv) {
3761                 /*
3762                  * If a posted intr is not recognized by hardware,
3763                  * we will accomplish it in the next vmentry.
3764                  */
3765                 vmx->nested.pi_pending = true;
3766                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3767                 /* the PIR and ON have been set by L1. */
3768                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3769                         kvm_vcpu_kick(vcpu);
3770                 return 0;
3771         }
3772         return -1;
3773 }
3774 /*
3775  * Send interrupt to vcpu via posted interrupt way.
3776  * 1. If target vcpu is running(non-root mode), send posted interrupt
3777  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3778  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3779  * interrupt from PIR in next vmentry.
3780  */
3781 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3782 {
3783         struct vcpu_vmx *vmx = to_vmx(vcpu);
3784         int r;
3785
3786         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3787         if (!r)
3788                 return;
3789
3790         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3791                 return;
3792
3793         /* If a previous notification has sent the IPI, nothing to do.  */
3794         if (pi_test_and_set_on(&vmx->pi_desc))
3795                 return;
3796
3797         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3798                 kvm_vcpu_kick(vcpu);
3799 }
3800
3801 /*
3802  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3803  * will not change in the lifetime of the guest.
3804  * Note that host-state that does change is set elsewhere. E.g., host-state
3805  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3806  */
3807 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3808 {
3809         u32 low32, high32;
3810         unsigned long tmpl;
3811         unsigned long cr0, cr3, cr4;
3812
3813         cr0 = read_cr0();
3814         WARN_ON(cr0 & X86_CR0_TS);
3815         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
3816
3817         /*
3818          * Save the most likely value for this task's CR3 in the VMCS.
3819          * We can't use __get_current_cr3_fast() because we're not atomic.
3820          */
3821         cr3 = __read_cr3();
3822         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
3823         vmx->loaded_vmcs->host_state.cr3 = cr3;
3824
3825         /* Save the most likely value for this task's CR4 in the VMCS. */
3826         cr4 = cr4_read_shadow();
3827         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
3828         vmx->loaded_vmcs->host_state.cr4 = cr4;
3829
3830         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3831 #ifdef CONFIG_X86_64
3832         /*
3833          * Load null selectors, so we can avoid reloading them in
3834          * vmx_prepare_switch_to_host(), in case userspace uses
3835          * the null selectors too (the expected case).
3836          */
3837         vmcs_write16(HOST_DS_SELECTOR, 0);
3838         vmcs_write16(HOST_ES_SELECTOR, 0);
3839 #else
3840         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3841         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3842 #endif
3843         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3844         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3845
3846         vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
3847
3848         vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3849
3850         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3851         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3852         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3853         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3854
3855         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3856                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3857                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3858         }
3859
3860         if (cpu_has_load_ia32_efer())
3861                 vmcs_write64(HOST_IA32_EFER, host_efer);
3862 }
3863
3864 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3865 {
3866         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3867         if (enable_ept)
3868                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3869         if (is_guest_mode(&vmx->vcpu))
3870                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3871                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3872         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3873 }
3874
3875 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3876 {
3877         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3878
3879         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3880                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3881
3882         if (!enable_vnmi)
3883                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3884
3885         if (!enable_preemption_timer)
3886                 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3887
3888         return pin_based_exec_ctrl;
3889 }
3890
3891 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3892 {
3893         struct vcpu_vmx *vmx = to_vmx(vcpu);
3894
3895         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3896         if (cpu_has_secondary_exec_ctrls()) {
3897                 if (kvm_vcpu_apicv_active(vcpu))
3898                         secondary_exec_controls_setbit(vmx,
3899                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
3900                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3901                 else
3902                         secondary_exec_controls_clearbit(vmx,
3903                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3904                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3905         }
3906
3907         if (cpu_has_vmx_msr_bitmap())
3908                 vmx_update_msr_bitmap(vcpu);
3909 }
3910
3911 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3912 {
3913         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3914
3915         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3916                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3917
3918         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3919                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3920 #ifdef CONFIG_X86_64
3921                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3922                                 CPU_BASED_CR8_LOAD_EXITING;
3923 #endif
3924         }
3925         if (!enable_ept)
3926                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3927                                 CPU_BASED_CR3_LOAD_EXITING  |
3928                                 CPU_BASED_INVLPG_EXITING;
3929         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3930                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3931                                 CPU_BASED_MONITOR_EXITING);
3932         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3933                 exec_control &= ~CPU_BASED_HLT_EXITING;
3934         return exec_control;
3935 }
3936
3937
3938 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3939 {
3940         struct kvm_vcpu *vcpu = &vmx->vcpu;
3941
3942         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3943
3944         if (pt_mode == PT_MODE_SYSTEM)
3945                 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3946         if (!cpu_need_virtualize_apic_accesses(vcpu))
3947                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3948         if (vmx->vpid == 0)
3949                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3950         if (!enable_ept) {
3951                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3952                 enable_unrestricted_guest = 0;
3953         }
3954         if (!enable_unrestricted_guest)
3955                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3956         if (kvm_pause_in_guest(vmx->vcpu.kvm))
3957                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3958         if (!kvm_vcpu_apicv_active(vcpu))
3959                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3960                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3961         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3962
3963         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3964          * in vmx_set_cr4.  */
3965         exec_control &= ~SECONDARY_EXEC_DESC;
3966
3967         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3968            (handle_vmptrld).
3969            We can NOT enable shadow_vmcs here because we don't have yet
3970            a current VMCS12
3971         */
3972         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
3973
3974         if (!enable_pml)
3975                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
3976
3977         if (vmx_xsaves_supported()) {
3978                 /* Exposing XSAVES only when XSAVE is exposed */
3979                 bool xsaves_enabled =
3980                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3981                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3982
3983                 if (!xsaves_enabled)
3984                         exec_control &= ~SECONDARY_EXEC_XSAVES;
3985
3986                 if (nested) {
3987                         if (xsaves_enabled)
3988                                 vmx->nested.msrs.secondary_ctls_high |=
3989                                         SECONDARY_EXEC_XSAVES;
3990                         else
3991                                 vmx->nested.msrs.secondary_ctls_high &=
3992                                         ~SECONDARY_EXEC_XSAVES;
3993                 }
3994         }
3995
3996         if (vmx_rdtscp_supported()) {
3997                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3998                 if (!rdtscp_enabled)
3999                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
4000
4001                 if (nested) {
4002                         if (rdtscp_enabled)
4003                                 vmx->nested.msrs.secondary_ctls_high |=
4004                                         SECONDARY_EXEC_RDTSCP;
4005                         else
4006                                 vmx->nested.msrs.secondary_ctls_high &=
4007                                         ~SECONDARY_EXEC_RDTSCP;
4008                 }
4009         }
4010
4011         if (vmx_invpcid_supported()) {
4012                 /* Exposing INVPCID only when PCID is exposed */
4013                 bool invpcid_enabled =
4014                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4015                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4016
4017                 if (!invpcid_enabled) {
4018                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4019                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4020                 }
4021
4022                 if (nested) {
4023                         if (invpcid_enabled)
4024                                 vmx->nested.msrs.secondary_ctls_high |=
4025                                         SECONDARY_EXEC_ENABLE_INVPCID;
4026                         else
4027                                 vmx->nested.msrs.secondary_ctls_high &=
4028                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
4029                 }
4030         }
4031
4032         if (vmx_rdrand_supported()) {
4033                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4034                 if (rdrand_enabled)
4035                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4036
4037                 if (nested) {
4038                         if (rdrand_enabled)
4039                                 vmx->nested.msrs.secondary_ctls_high |=
4040                                         SECONDARY_EXEC_RDRAND_EXITING;
4041                         else
4042                                 vmx->nested.msrs.secondary_ctls_high &=
4043                                         ~SECONDARY_EXEC_RDRAND_EXITING;
4044                 }
4045         }
4046
4047         if (vmx_rdseed_supported()) {
4048                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4049                 if (rdseed_enabled)
4050                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4051
4052                 if (nested) {
4053                         if (rdseed_enabled)
4054                                 vmx->nested.msrs.secondary_ctls_high |=
4055                                         SECONDARY_EXEC_RDSEED_EXITING;
4056                         else
4057                                 vmx->nested.msrs.secondary_ctls_high &=
4058                                         ~SECONDARY_EXEC_RDSEED_EXITING;
4059                 }
4060         }
4061
4062         vmx->secondary_exec_control = exec_control;
4063 }
4064
4065 static void ept_set_mmio_spte_mask(void)
4066 {
4067         /*
4068          * EPT Misconfigurations can be generated if the value of bits 2:0
4069          * of an EPT paging-structure entry is 110b (write/execute).
4070          */
4071         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4072                                    VMX_EPT_MISCONFIG_WX_VALUE, 0);
4073 }
4074
4075 #define VMX_XSS_EXIT_BITMAP 0
4076
4077 /*
4078  * Sets up the vmcs for emulated real mode.
4079  */
4080 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4081 {
4082         int i;
4083
4084         if (nested)
4085                 nested_vmx_vcpu_setup();
4086
4087         if (cpu_has_vmx_msr_bitmap())
4088                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4089
4090         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4091
4092         /* Control */
4093         pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4094         vmx->hv_deadline_tsc = -1;
4095
4096         exec_controls_set(vmx, vmx_exec_control(vmx));
4097
4098         if (cpu_has_secondary_exec_ctrls()) {
4099                 vmx_compute_secondary_exec_control(vmx);
4100                 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4101         }
4102
4103         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4104                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4105                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4106                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4107                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4108
4109                 vmcs_write16(GUEST_INTR_STATUS, 0);
4110
4111                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4112                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4113         }
4114
4115         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4116                 vmcs_write32(PLE_GAP, ple_gap);
4117                 vmx->ple_window = ple_window;
4118                 vmx->ple_window_dirty = true;
4119         }
4120
4121         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4122         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4123         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4124
4125         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4126         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4127         vmx_set_constant_host_state(vmx);
4128         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4129         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4130
4131         if (cpu_has_vmx_vmfunc())
4132                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4133
4134         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4135         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4136         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4137         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4138         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4139
4140         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4141                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4142
4143         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4144                 u32 index = vmx_msr_index[i];
4145                 u32 data_low, data_high;
4146                 int j = vmx->nmsrs;
4147
4148                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4149                         continue;
4150                 if (wrmsr_safe(index, data_low, data_high) < 0)
4151                         continue;
4152                 vmx->guest_msrs[j].index = i;
4153                 vmx->guest_msrs[j].data = 0;
4154                 vmx->guest_msrs[j].mask = -1ull;
4155                 ++vmx->nmsrs;
4156         }
4157
4158         vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4159
4160         /* 22.2.1, 20.8.1 */
4161         vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4162
4163         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4164         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4165
4166         set_cr4_guest_host_mask(vmx);
4167
4168         if (vmx_xsaves_supported())
4169                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4170
4171         if (enable_pml) {
4172                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4173                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4174         }
4175
4176         if (cpu_has_vmx_encls_vmexit())
4177                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4178
4179         if (pt_mode == PT_MODE_HOST_GUEST) {
4180                 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4181                 /* Bit[6~0] are forced to 1, writes are ignored. */
4182                 vmx->pt_desc.guest.output_mask = 0x7F;
4183                 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4184         }
4185 }
4186
4187 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4188 {
4189         struct vcpu_vmx *vmx = to_vmx(vcpu);
4190         struct msr_data apic_base_msr;
4191         u64 cr0;
4192
4193         vmx->rmode.vm86_active = 0;
4194         vmx->spec_ctrl = 0;
4195
4196         vcpu->arch.microcode_version = 0x100000000ULL;
4197         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4198         vmx->hv_deadline_tsc = -1;
4199         kvm_set_cr8(vcpu, 0);
4200
4201         if (!init_event) {
4202                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4203                                      MSR_IA32_APICBASE_ENABLE;
4204                 if (kvm_vcpu_is_reset_bsp(vcpu))
4205                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4206                 apic_base_msr.host_initiated = true;
4207                 kvm_set_apic_base(vcpu, &apic_base_msr);
4208         }
4209
4210         vmx_segment_cache_clear(vmx);
4211
4212         seg_setup(VCPU_SREG_CS);
4213         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4214         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4215
4216         seg_setup(VCPU_SREG_DS);
4217         seg_setup(VCPU_SREG_ES);
4218         seg_setup(VCPU_SREG_FS);
4219         seg_setup(VCPU_SREG_GS);
4220         seg_setup(VCPU_SREG_SS);
4221
4222         vmcs_write16(GUEST_TR_SELECTOR, 0);
4223         vmcs_writel(GUEST_TR_BASE, 0);
4224         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4225         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4226
4227         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4228         vmcs_writel(GUEST_LDTR_BASE, 0);
4229         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4230         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4231
4232         if (!init_event) {
4233                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4234                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4235                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4236                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4237         }
4238
4239         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4240         kvm_rip_write(vcpu, 0xfff0);
4241
4242         vmcs_writel(GUEST_GDTR_BASE, 0);
4243         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4244
4245         vmcs_writel(GUEST_IDTR_BASE, 0);
4246         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4247
4248         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4249         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4250         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4251         if (kvm_mpx_supported())
4252                 vmcs_write64(GUEST_BNDCFGS, 0);
4253
4254         setup_msrs(vmx);
4255
4256         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4257
4258         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4259                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4260                 if (cpu_need_tpr_shadow(vcpu))
4261                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4262                                      __pa(vcpu->arch.apic->regs));
4263                 vmcs_write32(TPR_THRESHOLD, 0);
4264         }
4265
4266         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4267
4268         if (vmx->vpid != 0)
4269                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4270
4271         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4272         vmx->vcpu.arch.cr0 = cr0;
4273         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4274         vmx_set_cr4(vcpu, 0);
4275         vmx_set_efer(vcpu, 0);
4276
4277         update_exception_bitmap(vcpu);
4278
4279         vpid_sync_context(vmx->vpid);
4280         if (init_event)
4281                 vmx_clear_hlt(vcpu);
4282 }
4283
4284 static void enable_irq_window(struct kvm_vcpu *vcpu)
4285 {
4286         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4287 }
4288
4289 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4290 {
4291         if (!enable_vnmi ||
4292             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4293                 enable_irq_window(vcpu);
4294                 return;
4295         }
4296
4297         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4298 }
4299
4300 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4301 {
4302         struct vcpu_vmx *vmx = to_vmx(vcpu);
4303         uint32_t intr;
4304         int irq = vcpu->arch.interrupt.nr;
4305
4306         trace_kvm_inj_virq(irq);
4307
4308         ++vcpu->stat.irq_injections;
4309         if (vmx->rmode.vm86_active) {
4310                 int inc_eip = 0;
4311                 if (vcpu->arch.interrupt.soft)
4312                         inc_eip = vcpu->arch.event_exit_inst_len;
4313                 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4314                 return;
4315         }
4316         intr = irq | INTR_INFO_VALID_MASK;
4317         if (vcpu->arch.interrupt.soft) {
4318                 intr |= INTR_TYPE_SOFT_INTR;
4319                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4320                              vmx->vcpu.arch.event_exit_inst_len);
4321         } else
4322                 intr |= INTR_TYPE_EXT_INTR;
4323         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4324
4325         vmx_clear_hlt(vcpu);
4326 }
4327
4328 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4329 {
4330         struct vcpu_vmx *vmx = to_vmx(vcpu);
4331
4332         if (!enable_vnmi) {
4333                 /*
4334                  * Tracking the NMI-blocked state in software is built upon
4335                  * finding the next open IRQ window. This, in turn, depends on
4336                  * well-behaving guests: They have to keep IRQs disabled at
4337                  * least as long as the NMI handler runs. Otherwise we may
4338                  * cause NMI nesting, maybe breaking the guest. But as this is
4339                  * highly unlikely, we can live with the residual risk.
4340                  */
4341                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4342                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4343         }
4344
4345         ++vcpu->stat.nmi_injections;
4346         vmx->loaded_vmcs->nmi_known_unmasked = false;
4347
4348         if (vmx->rmode.vm86_active) {
4349                 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4350                 return;
4351         }
4352
4353         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4354                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4355
4356         vmx_clear_hlt(vcpu);
4357 }
4358
4359 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4360 {
4361         struct vcpu_vmx *vmx = to_vmx(vcpu);
4362         bool masked;
4363
4364         if (!enable_vnmi)
4365                 return vmx->loaded_vmcs->soft_vnmi_blocked;
4366         if (vmx->loaded_vmcs->nmi_known_unmasked)
4367                 return false;
4368         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4369         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4370         return masked;
4371 }
4372
4373 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4374 {
4375         struct vcpu_vmx *vmx = to_vmx(vcpu);
4376
4377         if (!enable_vnmi) {
4378                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4379                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4380                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
4381                 }
4382         } else {
4383                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4384                 if (masked)
4385                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4386                                       GUEST_INTR_STATE_NMI);
4387                 else
4388                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4389                                         GUEST_INTR_STATE_NMI);
4390         }
4391 }
4392
4393 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4394 {
4395         if (to_vmx(vcpu)->nested.nested_run_pending)
4396                 return 0;
4397
4398         if (!enable_vnmi &&
4399             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4400                 return 0;
4401
4402         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4403                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4404                    | GUEST_INTR_STATE_NMI));
4405 }
4406
4407 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4408 {
4409         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4410                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4411                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4412                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4413 }
4414
4415 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4416 {
4417         int ret;
4418
4419         if (enable_unrestricted_guest)
4420                 return 0;
4421
4422         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4423                                     PAGE_SIZE * 3);
4424         if (ret)
4425                 return ret;
4426         to_kvm_vmx(kvm)->tss_addr = addr;
4427         return init_rmode_tss(kvm);
4428 }
4429
4430 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4431 {
4432         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4433         return 0;
4434 }
4435
4436 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4437 {
4438         switch (vec) {
4439         case BP_VECTOR:
4440                 /*
4441                  * Update instruction length as we may reinject the exception
4442                  * from user space while in guest debugging mode.
4443                  */
4444                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4445                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4446                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4447                         return false;
4448                 /* fall through */
4449         case DB_VECTOR:
4450                 if (vcpu->guest_debug &
4451                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4452                         return false;
4453                 /* fall through */
4454         case DE_VECTOR:
4455         case OF_VECTOR:
4456         case BR_VECTOR:
4457         case UD_VECTOR:
4458         case DF_VECTOR:
4459         case SS_VECTOR:
4460         case GP_VECTOR:
4461         case MF_VECTOR:
4462                 return true;
4463         break;
4464         }
4465         return false;
4466 }
4467
4468 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4469                                   int vec, u32 err_code)
4470 {
4471         /*
4472          * Instruction with address size override prefix opcode 0x67
4473          * Cause the #SS fault with 0 error code in VM86 mode.
4474          */
4475         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4476                 if (kvm_emulate_instruction(vcpu, 0)) {
4477                         if (vcpu->arch.halt_request) {
4478                                 vcpu->arch.halt_request = 0;
4479                                 return kvm_vcpu_halt(vcpu);
4480                         }
4481                         return 1;
4482                 }
4483                 return 0;
4484         }
4485
4486         /*
4487          * Forward all other exceptions that are valid in real mode.
4488          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4489          *        the required debugging infrastructure rework.
4490          */
4491         kvm_queue_exception(vcpu, vec);
4492         return 1;
4493 }
4494
4495 /*
4496  * Trigger machine check on the host. We assume all the MSRs are already set up
4497  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4498  * We pass a fake environment to the machine check handler because we want
4499  * the guest to be always treated like user space, no matter what context
4500  * it used internally.
4501  */
4502 static void kvm_machine_check(void)
4503 {
4504 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4505         struct pt_regs regs = {
4506                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4507                 .flags = X86_EFLAGS_IF,
4508         };
4509
4510         do_machine_check(&regs, 0);
4511 #endif
4512 }
4513
4514 static int handle_machine_check(struct kvm_vcpu *vcpu)
4515 {
4516         /* handled by vmx_vcpu_run() */
4517         return 1;
4518 }
4519
4520 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4521 {
4522         struct vcpu_vmx *vmx = to_vmx(vcpu);
4523         struct kvm_run *kvm_run = vcpu->run;
4524         u32 intr_info, ex_no, error_code;
4525         unsigned long cr2, rip, dr6;
4526         u32 vect_info;
4527
4528         vect_info = vmx->idt_vectoring_info;
4529         intr_info = vmx->exit_intr_info;
4530
4531         if (is_machine_check(intr_info) || is_nmi(intr_info))
4532                 return 1; /* handled by handle_exception_nmi_irqoff() */
4533
4534         if (is_invalid_opcode(intr_info))
4535                 return handle_ud(vcpu);
4536
4537         error_code = 0;
4538         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4539                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4540
4541         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4542                 WARN_ON_ONCE(!enable_vmware_backdoor);
4543
4544                 /*
4545                  * VMware backdoor emulation on #GP interception only handles
4546                  * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4547                  * error code on #GP.
4548                  */
4549                 if (error_code) {
4550                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4551                         return 1;
4552                 }
4553                 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4554         }
4555
4556         /*
4557          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4558          * MMIO, it is better to report an internal error.
4559          * See the comments in vmx_handle_exit.
4560          */
4561         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4562             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4563                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4564                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4565                 vcpu->run->internal.ndata = 3;
4566                 vcpu->run->internal.data[0] = vect_info;
4567                 vcpu->run->internal.data[1] = intr_info;
4568                 vcpu->run->internal.data[2] = error_code;
4569                 return 0;
4570         }
4571
4572         if (is_page_fault(intr_info)) {
4573                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4574                 /* EPT won't cause page fault directly */
4575                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4576                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4577         }
4578
4579         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4580
4581         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4582                 return handle_rmode_exception(vcpu, ex_no, error_code);
4583
4584         switch (ex_no) {
4585         case AC_VECTOR:
4586                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4587                 return 1;
4588         case DB_VECTOR:
4589                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4590                 if (!(vcpu->guest_debug &
4591                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4592                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4593                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4594                         if (is_icebp(intr_info))
4595                                 WARN_ON(!skip_emulated_instruction(vcpu));
4596
4597                         kvm_queue_exception(vcpu, DB_VECTOR);
4598                         return 1;
4599                 }
4600                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4601                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4602                 /* fall through */
4603         case BP_VECTOR:
4604                 /*
4605                  * Update instruction length as we may reinject #BP from
4606                  * user space while in guest debugging mode. Reading it for
4607                  * #DB as well causes no harm, it is not used in that case.
4608                  */
4609                 vmx->vcpu.arch.event_exit_inst_len =
4610                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4611                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4612                 rip = kvm_rip_read(vcpu);
4613                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4614                 kvm_run->debug.arch.exception = ex_no;
4615                 break;
4616         default:
4617                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4618                 kvm_run->ex.exception = ex_no;
4619                 kvm_run->ex.error_code = error_code;
4620                 break;
4621         }
4622         return 0;
4623 }
4624
4625 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4626 {
4627         ++vcpu->stat.irq_exits;
4628         return 1;
4629 }
4630
4631 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4632 {
4633         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4634         vcpu->mmio_needed = 0;
4635         return 0;
4636 }
4637
4638 static int handle_io(struct kvm_vcpu *vcpu)
4639 {
4640         unsigned long exit_qualification;
4641         int size, in, string;
4642         unsigned port;
4643
4644         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4645         string = (exit_qualification & 16) != 0;
4646
4647         ++vcpu->stat.io_exits;
4648
4649         if (string)
4650                 return kvm_emulate_instruction(vcpu, 0);
4651
4652         port = exit_qualification >> 16;
4653         size = (exit_qualification & 7) + 1;
4654         in = (exit_qualification & 8) != 0;
4655
4656         return kvm_fast_pio(vcpu, size, port, in);
4657 }
4658
4659 static void
4660 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4661 {
4662         /*
4663          * Patch in the VMCALL instruction:
4664          */
4665         hypercall[0] = 0x0f;
4666         hypercall[1] = 0x01;
4667         hypercall[2] = 0xc1;
4668 }
4669
4670 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4671 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4672 {
4673         if (is_guest_mode(vcpu)) {
4674                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4675                 unsigned long orig_val = val;
4676
4677                 /*
4678                  * We get here when L2 changed cr0 in a way that did not change
4679                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4680                  * but did change L0 shadowed bits. So we first calculate the
4681                  * effective cr0 value that L1 would like to write into the
4682                  * hardware. It consists of the L2-owned bits from the new
4683                  * value combined with the L1-owned bits from L1's guest_cr0.
4684                  */
4685                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4686                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4687
4688                 if (!nested_guest_cr0_valid(vcpu, val))
4689                         return 1;
4690
4691                 if (kvm_set_cr0(vcpu, val))
4692                         return 1;
4693                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4694                 return 0;
4695         } else {
4696                 if (to_vmx(vcpu)->nested.vmxon &&
4697                     !nested_host_cr0_valid(vcpu, val))
4698                         return 1;
4699
4700                 return kvm_set_cr0(vcpu, val);
4701         }
4702 }
4703
4704 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4705 {
4706         if (is_guest_mode(vcpu)) {
4707                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4708                 unsigned long orig_val = val;
4709
4710                 /* analogously to handle_set_cr0 */
4711                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4712                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4713                 if (kvm_set_cr4(vcpu, val))
4714                         return 1;
4715                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4716                 return 0;
4717         } else
4718                 return kvm_set_cr4(vcpu, val);
4719 }
4720
4721 static int handle_desc(struct kvm_vcpu *vcpu)
4722 {
4723         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4724         return kvm_emulate_instruction(vcpu, 0);
4725 }
4726
4727 static int handle_cr(struct kvm_vcpu *vcpu)
4728 {
4729         unsigned long exit_qualification, val;
4730         int cr;
4731         int reg;
4732         int err;
4733         int ret;
4734
4735         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4736         cr = exit_qualification & 15;
4737         reg = (exit_qualification >> 8) & 15;
4738         switch ((exit_qualification >> 4) & 3) {
4739         case 0: /* mov to cr */
4740                 val = kvm_register_readl(vcpu, reg);
4741                 trace_kvm_cr_write(cr, val);
4742                 switch (cr) {
4743                 case 0:
4744                         err = handle_set_cr0(vcpu, val);
4745                         return kvm_complete_insn_gp(vcpu, err);
4746                 case 3:
4747                         WARN_ON_ONCE(enable_unrestricted_guest);
4748                         err = kvm_set_cr3(vcpu, val);
4749                         return kvm_complete_insn_gp(vcpu, err);
4750                 case 4:
4751                         err = handle_set_cr4(vcpu, val);
4752                         return kvm_complete_insn_gp(vcpu, err);
4753                 case 8: {
4754                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4755                                 u8 cr8 = (u8)val;
4756                                 err = kvm_set_cr8(vcpu, cr8);
4757                                 ret = kvm_complete_insn_gp(vcpu, err);
4758                                 if (lapic_in_kernel(vcpu))
4759                                         return ret;
4760                                 if (cr8_prev <= cr8)
4761                                         return ret;
4762                                 /*
4763                                  * TODO: we might be squashing a
4764                                  * KVM_GUESTDBG_SINGLESTEP-triggered
4765                                  * KVM_EXIT_DEBUG here.
4766                                  */
4767                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4768                                 return 0;
4769                         }
4770                 }
4771                 break;
4772         case 2: /* clts */
4773                 WARN_ONCE(1, "Guest should always own CR0.TS");
4774                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4775                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4776                 return kvm_skip_emulated_instruction(vcpu);
4777         case 1: /*mov from cr*/
4778                 switch (cr) {
4779                 case 3:
4780                         WARN_ON_ONCE(enable_unrestricted_guest);
4781                         val = kvm_read_cr3(vcpu);
4782                         kvm_register_write(vcpu, reg, val);
4783                         trace_kvm_cr_read(cr, val);
4784                         return kvm_skip_emulated_instruction(vcpu);
4785                 case 8:
4786                         val = kvm_get_cr8(vcpu);
4787                         kvm_register_write(vcpu, reg, val);
4788                         trace_kvm_cr_read(cr, val);
4789                         return kvm_skip_emulated_instruction(vcpu);
4790                 }
4791                 break;
4792         case 3: /* lmsw */
4793                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4794                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4795                 kvm_lmsw(vcpu, val);
4796
4797                 return kvm_skip_emulated_instruction(vcpu);
4798         default:
4799                 break;
4800         }
4801         vcpu->run->exit_reason = 0;
4802         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4803                (int)(exit_qualification >> 4) & 3, cr);
4804         return 0;
4805 }
4806
4807 static int handle_dr(struct kvm_vcpu *vcpu)
4808 {
4809         unsigned long exit_qualification;
4810         int dr, dr7, reg;
4811
4812         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4813         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4814
4815         /* First, if DR does not exist, trigger UD */
4816         if (!kvm_require_dr(vcpu, dr))
4817                 return 1;
4818
4819         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4820         if (!kvm_require_cpl(vcpu, 0))
4821                 return 1;
4822         dr7 = vmcs_readl(GUEST_DR7);
4823         if (dr7 & DR7_GD) {
4824                 /*
4825                  * As the vm-exit takes precedence over the debug trap, we
4826                  * need to emulate the latter, either for the host or the
4827                  * guest debugging itself.
4828                  */
4829                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4830                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4831                         vcpu->run->debug.arch.dr7 = dr7;
4832                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4833                         vcpu->run->debug.arch.exception = DB_VECTOR;
4834                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4835                         return 0;
4836                 } else {
4837                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4838                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4839                         kvm_queue_exception(vcpu, DB_VECTOR);
4840                         return 1;
4841                 }
4842         }
4843
4844         if (vcpu->guest_debug == 0) {
4845                 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4846
4847                 /*
4848                  * No more DR vmexits; force a reload of the debug registers
4849                  * and reenter on this instruction.  The next vmexit will
4850                  * retrieve the full state of the debug registers.
4851                  */
4852                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4853                 return 1;
4854         }
4855
4856         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4857         if (exit_qualification & TYPE_MOV_FROM_DR) {
4858                 unsigned long val;
4859
4860                 if (kvm_get_dr(vcpu, dr, &val))
4861                         return 1;
4862                 kvm_register_write(vcpu, reg, val);
4863         } else
4864                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4865                         return 1;
4866
4867         return kvm_skip_emulated_instruction(vcpu);
4868 }
4869
4870 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4871 {
4872         return vcpu->arch.dr6;
4873 }
4874
4875 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4876 {
4877 }
4878
4879 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4880 {
4881         get_debugreg(vcpu->arch.db[0], 0);
4882         get_debugreg(vcpu->arch.db[1], 1);
4883         get_debugreg(vcpu->arch.db[2], 2);
4884         get_debugreg(vcpu->arch.db[3], 3);
4885         get_debugreg(vcpu->arch.dr6, 6);
4886         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4887
4888         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4889         exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4890 }
4891
4892 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4893 {
4894         vmcs_writel(GUEST_DR7, val);
4895 }
4896
4897 static int handle_cpuid(struct kvm_vcpu *vcpu)
4898 {
4899         return kvm_emulate_cpuid(vcpu);
4900 }
4901
4902 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4903 {
4904         return kvm_emulate_rdmsr(vcpu);
4905 }
4906
4907 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4908 {
4909         return kvm_emulate_wrmsr(vcpu);
4910 }
4911
4912 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4913 {
4914         kvm_apic_update_ppr(vcpu);
4915         return 1;
4916 }
4917
4918 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4919 {
4920         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4921
4922         kvm_make_request(KVM_REQ_EVENT, vcpu);
4923
4924         ++vcpu->stat.irq_window_exits;
4925         return 1;
4926 }
4927
4928 static int handle_halt(struct kvm_vcpu *vcpu)
4929 {
4930         return kvm_emulate_halt(vcpu);
4931 }
4932
4933 static int handle_vmcall(struct kvm_vcpu *vcpu)
4934 {
4935         return kvm_emulate_hypercall(vcpu);
4936 }
4937
4938 static int handle_invd(struct kvm_vcpu *vcpu)
4939 {
4940         return kvm_emulate_instruction(vcpu, 0);
4941 }
4942
4943 static int handle_invlpg(struct kvm_vcpu *vcpu)
4944 {
4945         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4946
4947         kvm_mmu_invlpg(vcpu, exit_qualification);
4948         return kvm_skip_emulated_instruction(vcpu);
4949 }
4950
4951 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4952 {
4953         int err;
4954
4955         err = kvm_rdpmc(vcpu);
4956         return kvm_complete_insn_gp(vcpu, err);
4957 }
4958
4959 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4960 {
4961         return kvm_emulate_wbinvd(vcpu);
4962 }
4963
4964 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4965 {
4966         u64 new_bv = kvm_read_edx_eax(vcpu);
4967         u32 index = kvm_rcx_read(vcpu);
4968
4969         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4970                 return kvm_skip_emulated_instruction(vcpu);
4971         return 1;
4972 }
4973
4974 static int handle_xsaves(struct kvm_vcpu *vcpu)
4975 {
4976         kvm_skip_emulated_instruction(vcpu);
4977         WARN(1, "this should never happen\n");
4978         return 1;
4979 }
4980
4981 static int handle_xrstors(struct kvm_vcpu *vcpu)
4982 {
4983         kvm_skip_emulated_instruction(vcpu);
4984         WARN(1, "this should never happen\n");
4985         return 1;
4986 }
4987
4988 static int handle_apic_access(struct kvm_vcpu *vcpu)
4989 {
4990         if (likely(fasteoi)) {
4991                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4992                 int access_type, offset;
4993
4994                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4995                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4996                 /*
4997                  * Sane guest uses MOV to write EOI, with written value
4998                  * not cared. So make a short-circuit here by avoiding
4999                  * heavy instruction emulation.
5000                  */
5001                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5002                     (offset == APIC_EOI)) {
5003                         kvm_lapic_set_eoi(vcpu);
5004                         return kvm_skip_emulated_instruction(vcpu);
5005                 }
5006         }
5007         return kvm_emulate_instruction(vcpu, 0);
5008 }
5009
5010 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5011 {
5012         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5013         int vector = exit_qualification & 0xff;
5014
5015         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5016         kvm_apic_set_eoi_accelerated(vcpu, vector);
5017         return 1;
5018 }
5019
5020 static int handle_apic_write(struct kvm_vcpu *vcpu)
5021 {
5022         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5023         u32 offset = exit_qualification & 0xfff;
5024
5025         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5026         kvm_apic_write_nodecode(vcpu, offset);
5027         return 1;
5028 }
5029
5030 static int handle_task_switch(struct kvm_vcpu *vcpu)
5031 {
5032         struct vcpu_vmx *vmx = to_vmx(vcpu);
5033         unsigned long exit_qualification;
5034         bool has_error_code = false;
5035         u32 error_code = 0;
5036         u16 tss_selector;
5037         int reason, type, idt_v, idt_index;
5038
5039         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5040         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5041         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5042
5043         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5044
5045         reason = (u32)exit_qualification >> 30;
5046         if (reason == TASK_SWITCH_GATE && idt_v) {
5047                 switch (type) {
5048                 case INTR_TYPE_NMI_INTR:
5049                         vcpu->arch.nmi_injected = false;
5050                         vmx_set_nmi_mask(vcpu, true);
5051                         break;
5052                 case INTR_TYPE_EXT_INTR:
5053                 case INTR_TYPE_SOFT_INTR:
5054                         kvm_clear_interrupt_queue(vcpu);
5055                         break;
5056                 case INTR_TYPE_HARD_EXCEPTION:
5057                         if (vmx->idt_vectoring_info &
5058                             VECTORING_INFO_DELIVER_CODE_MASK) {
5059                                 has_error_code = true;
5060                                 error_code =
5061                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5062                         }
5063                         /* fall through */
5064                 case INTR_TYPE_SOFT_EXCEPTION:
5065                         kvm_clear_exception_queue(vcpu);
5066                         break;
5067                 default:
5068                         break;
5069                 }
5070         }
5071         tss_selector = exit_qualification;
5072
5073         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5074                        type != INTR_TYPE_EXT_INTR &&
5075                        type != INTR_TYPE_NMI_INTR))
5076                 WARN_ON(!skip_emulated_instruction(vcpu));
5077
5078         /*
5079          * TODO: What about debug traps on tss switch?
5080          *       Are we supposed to inject them and update dr6?
5081          */
5082         return kvm_task_switch(vcpu, tss_selector,
5083                                type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5084                                reason, has_error_code, error_code);
5085 }
5086
5087 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5088 {
5089         unsigned long exit_qualification;
5090         gpa_t gpa;
5091         u64 error_code;
5092
5093         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5094
5095         /*
5096          * EPT violation happened while executing iret from NMI,
5097          * "blocked by NMI" bit has to be set before next VM entry.
5098          * There are errata that may cause this bit to not be set:
5099          * AAK134, BY25.
5100          */
5101         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5102                         enable_vnmi &&
5103                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5104                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5105
5106         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5107         trace_kvm_page_fault(gpa, exit_qualification);
5108
5109         /* Is it a read fault? */
5110         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5111                      ? PFERR_USER_MASK : 0;
5112         /* Is it a write fault? */
5113         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5114                       ? PFERR_WRITE_MASK : 0;
5115         /* Is it a fetch fault? */
5116         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5117                       ? PFERR_FETCH_MASK : 0;
5118         /* ept page table entry is present? */
5119         error_code |= (exit_qualification &
5120                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5121                         EPT_VIOLATION_EXECUTABLE))
5122                       ? PFERR_PRESENT_MASK : 0;
5123
5124         error_code |= (exit_qualification & 0x100) != 0 ?
5125                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5126
5127         vcpu->arch.exit_qualification = exit_qualification;
5128         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5129 }
5130
5131 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5132 {
5133         gpa_t gpa;
5134
5135         /*
5136          * A nested guest cannot optimize MMIO vmexits, because we have an
5137          * nGPA here instead of the required GPA.
5138          */
5139         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5140         if (!is_guest_mode(vcpu) &&
5141             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5142                 trace_kvm_fast_mmio(gpa);
5143                 return kvm_skip_emulated_instruction(vcpu);
5144         }
5145
5146         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5147 }
5148
5149 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5150 {
5151         WARN_ON_ONCE(!enable_vnmi);
5152         exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5153         ++vcpu->stat.nmi_window_exits;
5154         kvm_make_request(KVM_REQ_EVENT, vcpu);
5155
5156         return 1;
5157 }
5158
5159 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5160 {
5161         struct vcpu_vmx *vmx = to_vmx(vcpu);
5162         bool intr_window_requested;
5163         unsigned count = 130;
5164
5165         /*
5166          * We should never reach the point where we are emulating L2
5167          * due to invalid guest state as that means we incorrectly
5168          * allowed a nested VMEntry with an invalid vmcs12.
5169          */
5170         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5171
5172         intr_window_requested = exec_controls_get(vmx) &
5173                                 CPU_BASED_VIRTUAL_INTR_PENDING;
5174
5175         while (vmx->emulation_required && count-- != 0) {
5176                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5177                         return handle_interrupt_window(&vmx->vcpu);
5178
5179                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5180                         return 1;
5181
5182                 if (!kvm_emulate_instruction(vcpu, 0))
5183                         return 0;
5184
5185                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5186                     vcpu->arch.exception.pending) {
5187                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5188                         vcpu->run->internal.suberror =
5189                                                 KVM_INTERNAL_ERROR_EMULATION;
5190                         vcpu->run->internal.ndata = 0;
5191                         return 0;
5192                 }
5193
5194                 if (vcpu->arch.halt_request) {
5195                         vcpu->arch.halt_request = 0;
5196                         return kvm_vcpu_halt(vcpu);
5197                 }
5198
5199                 /*
5200                  * Note, return 1 and not 0, vcpu_run() is responsible for
5201                  * morphing the pending signal into the proper return code.
5202                  */
5203                 if (signal_pending(current))
5204                         return 1;
5205
5206                 if (need_resched())
5207                         schedule();
5208         }
5209
5210         return 1;
5211 }
5212
5213 static void grow_ple_window(struct kvm_vcpu *vcpu)
5214 {
5215         struct vcpu_vmx *vmx = to_vmx(vcpu);
5216         unsigned int old = vmx->ple_window;
5217
5218         vmx->ple_window = __grow_ple_window(old, ple_window,
5219                                             ple_window_grow,
5220                                             ple_window_max);
5221
5222         if (vmx->ple_window != old) {
5223                 vmx->ple_window_dirty = true;
5224                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5225                                             vmx->ple_window, old);
5226         }
5227 }
5228
5229 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5230 {
5231         struct vcpu_vmx *vmx = to_vmx(vcpu);
5232         unsigned int old = vmx->ple_window;
5233
5234         vmx->ple_window = __shrink_ple_window(old, ple_window,
5235                                               ple_window_shrink,
5236                                               ple_window);
5237
5238         if (vmx->ple_window != old) {
5239                 vmx->ple_window_dirty = true;
5240                 trace_kvm_ple_window_update(vcpu->vcpu_id,
5241                                             vmx->ple_window, old);
5242         }
5243 }
5244
5245 /*
5246  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5247  */
5248 static void wakeup_handler(void)
5249 {
5250         struct kvm_vcpu *vcpu;
5251         int cpu = smp_processor_id();
5252
5253         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5254         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5255                         blocked_vcpu_list) {
5256                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5257
5258                 if (pi_test_on(pi_desc) == 1)
5259                         kvm_vcpu_kick(vcpu);
5260         }
5261         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5262 }
5263
5264 static void vmx_enable_tdp(void)
5265 {
5266         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5267                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5268                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5269                 0ull, VMX_EPT_EXECUTABLE_MASK,
5270                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5271                 VMX_EPT_RWX_MASK, 0ull);
5272
5273         ept_set_mmio_spte_mask();
5274         kvm_enable_tdp();
5275 }
5276
5277 /*
5278  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5279  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5280  */
5281 static int handle_pause(struct kvm_vcpu *vcpu)
5282 {
5283         if (!kvm_pause_in_guest(vcpu->kvm))
5284                 grow_ple_window(vcpu);
5285
5286         /*
5287          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5288          * VM-execution control is ignored if CPL > 0. OTOH, KVM
5289          * never set PAUSE_EXITING and just set PLE if supported,
5290          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5291          */
5292         kvm_vcpu_on_spin(vcpu, true);
5293         return kvm_skip_emulated_instruction(vcpu);
5294 }
5295
5296 static int handle_nop(struct kvm_vcpu *vcpu)
5297 {
5298         return kvm_skip_emulated_instruction(vcpu);
5299 }
5300
5301 static int handle_mwait(struct kvm_vcpu *vcpu)
5302 {
5303         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5304         return handle_nop(vcpu);
5305 }
5306
5307 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5308 {
5309         kvm_queue_exception(vcpu, UD_VECTOR);
5310         return 1;
5311 }
5312
5313 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5314 {
5315         return 1;
5316 }
5317
5318 static int handle_monitor(struct kvm_vcpu *vcpu)
5319 {
5320         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5321         return handle_nop(vcpu);
5322 }
5323
5324 static int handle_invpcid(struct kvm_vcpu *vcpu)
5325 {
5326         u32 vmx_instruction_info;
5327         unsigned long type;
5328         bool pcid_enabled;
5329         gva_t gva;
5330         struct x86_exception e;
5331         unsigned i;
5332         unsigned long roots_to_free = 0;
5333         struct {
5334                 u64 pcid;
5335                 u64 gla;
5336         } operand;
5337
5338         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5339                 kvm_queue_exception(vcpu, UD_VECTOR);
5340                 return 1;
5341         }
5342
5343         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5344         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5345
5346         if (type > 3) {
5347                 kvm_inject_gp(vcpu, 0);
5348                 return 1;
5349         }
5350
5351         /* According to the Intel instruction reference, the memory operand
5352          * is read even if it isn't needed (e.g., for type==all)
5353          */
5354         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5355                                 vmx_instruction_info, false,
5356                                 sizeof(operand), &gva))
5357                 return 1;
5358
5359         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5360                 kvm_inject_page_fault(vcpu, &e);
5361                 return 1;
5362         }
5363
5364         if (operand.pcid >> 12 != 0) {
5365                 kvm_inject_gp(vcpu, 0);
5366                 return 1;
5367         }
5368
5369         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5370
5371         switch (type) {
5372         case INVPCID_TYPE_INDIV_ADDR:
5373                 if ((!pcid_enabled && (operand.pcid != 0)) ||
5374                     is_noncanonical_address(operand.gla, vcpu)) {
5375                         kvm_inject_gp(vcpu, 0);
5376                         return 1;
5377                 }
5378                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5379                 return kvm_skip_emulated_instruction(vcpu);
5380
5381         case INVPCID_TYPE_SINGLE_CTXT:
5382                 if (!pcid_enabled && (operand.pcid != 0)) {
5383                         kvm_inject_gp(vcpu, 0);
5384                         return 1;
5385                 }
5386
5387                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5388                         kvm_mmu_sync_roots(vcpu);
5389                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5390                 }
5391
5392                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5393                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5394                             == operand.pcid)
5395                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5396
5397                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5398                 /*
5399                  * If neither the current cr3 nor any of the prev_roots use the
5400                  * given PCID, then nothing needs to be done here because a
5401                  * resync will happen anyway before switching to any other CR3.
5402                  */
5403
5404                 return kvm_skip_emulated_instruction(vcpu);
5405
5406         case INVPCID_TYPE_ALL_NON_GLOBAL:
5407                 /*
5408                  * Currently, KVM doesn't mark global entries in the shadow
5409                  * page tables, so a non-global flush just degenerates to a
5410                  * global flush. If needed, we could optimize this later by
5411                  * keeping track of global entries in shadow page tables.
5412                  */
5413
5414                 /* fall-through */
5415         case INVPCID_TYPE_ALL_INCL_GLOBAL:
5416                 kvm_mmu_unload(vcpu);
5417                 return kvm_skip_emulated_instruction(vcpu);
5418
5419         default:
5420                 BUG(); /* We have already checked above that type <= 3 */
5421         }
5422 }
5423
5424 static int handle_pml_full(struct kvm_vcpu *vcpu)
5425 {
5426         unsigned long exit_qualification;
5427
5428         trace_kvm_pml_full(vcpu->vcpu_id);
5429
5430         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5431
5432         /*
5433          * PML buffer FULL happened while executing iret from NMI,
5434          * "blocked by NMI" bit has to be set before next VM entry.
5435          */
5436         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5437                         enable_vnmi &&
5438                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5439                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5440                                 GUEST_INTR_STATE_NMI);
5441
5442         /*
5443          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5444          * here.., and there's no userspace involvement needed for PML.
5445          */
5446         return 1;
5447 }
5448
5449 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5450 {
5451         struct vcpu_vmx *vmx = to_vmx(vcpu);
5452
5453         if (!vmx->req_immediate_exit &&
5454             !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5455                 kvm_lapic_expired_hv_timer(vcpu);
5456
5457         return 1;
5458 }
5459
5460 /*
5461  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5462  * are overwritten by nested_vmx_setup() when nested=1.
5463  */
5464 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5465 {
5466         kvm_queue_exception(vcpu, UD_VECTOR);
5467         return 1;
5468 }
5469
5470 static int handle_encls(struct kvm_vcpu *vcpu)
5471 {
5472         /*
5473          * SGX virtualization is not yet supported.  There is no software
5474          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5475          * to prevent the guest from executing ENCLS.
5476          */
5477         kvm_queue_exception(vcpu, UD_VECTOR);
5478         return 1;
5479 }
5480
5481 /*
5482  * The exit handlers return 1 if the exit was handled fully and guest execution
5483  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5484  * to be done to userspace and return 0.
5485  */
5486 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5487         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5488         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5489         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5490         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5491         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5492         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5493         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5494         [EXIT_REASON_CPUID]                   = handle_cpuid,
5495         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5496         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5497         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5498         [EXIT_REASON_HLT]                     = handle_halt,
5499         [EXIT_REASON_INVD]                    = handle_invd,
5500         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5501         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5502         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5503         [EXIT_REASON_VMCLEAR]                 = handle_vmx_instruction,
5504         [EXIT_REASON_VMLAUNCH]                = handle_vmx_instruction,
5505         [EXIT_REASON_VMPTRLD]                 = handle_vmx_instruction,
5506         [EXIT_REASON_VMPTRST]                 = handle_vmx_instruction,
5507         [EXIT_REASON_VMREAD]                  = handle_vmx_instruction,
5508         [EXIT_REASON_VMRESUME]                = handle_vmx_instruction,
5509         [EXIT_REASON_VMWRITE]                 = handle_vmx_instruction,
5510         [EXIT_REASON_VMOFF]                   = handle_vmx_instruction,
5511         [EXIT_REASON_VMON]                    = handle_vmx_instruction,
5512         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5513         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5514         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5515         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5516         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5517         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5518         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5519         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5520         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
5521         [EXIT_REASON_LDTR_TR]                 = handle_desc,
5522         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5523         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5524         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5525         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
5526         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5527         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5528         [EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5529         [EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5530         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
5531         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
5532         [EXIT_REASON_XSAVES]                  = handle_xsaves,
5533         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
5534         [EXIT_REASON_PML_FULL]                = handle_pml_full,
5535         [EXIT_REASON_INVPCID]                 = handle_invpcid,
5536         [EXIT_REASON_VMFUNC]                  = handle_vmx_instruction,
5537         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
5538         [EXIT_REASON_ENCLS]                   = handle_encls,
5539 };
5540
5541 static const int kvm_vmx_max_exit_handlers =
5542         ARRAY_SIZE(kvm_vmx_exit_handlers);
5543
5544 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5545 {
5546         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5547         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5548 }
5549
5550 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5551 {
5552         if (vmx->pml_pg) {
5553                 __free_page(vmx->pml_pg);
5554                 vmx->pml_pg = NULL;
5555         }
5556 }
5557
5558 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5559 {
5560         struct vcpu_vmx *vmx = to_vmx(vcpu);
5561         u64 *pml_buf;
5562         u16 pml_idx;
5563
5564         pml_idx = vmcs_read16(GUEST_PML_INDEX);
5565
5566         /* Do nothing if PML buffer is empty */
5567         if (pml_idx == (PML_ENTITY_NUM - 1))
5568                 return;
5569
5570         /* PML index always points to next available PML buffer entity */
5571         if (pml_idx >= PML_ENTITY_NUM)
5572                 pml_idx = 0;
5573         else
5574                 pml_idx++;
5575
5576         pml_buf = page_address(vmx->pml_pg);
5577         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5578                 u64 gpa;
5579
5580                 gpa = pml_buf[pml_idx];
5581                 WARN_ON(gpa & (PAGE_SIZE - 1));
5582                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5583         }
5584
5585         /* reset PML index */
5586         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5587 }
5588
5589 /*
5590  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5591  * Called before reporting dirty_bitmap to userspace.
5592  */
5593 static void kvm_flush_pml_buffers(struct kvm *kvm)
5594 {
5595         int i;
5596         struct kvm_vcpu *vcpu;
5597         /*
5598          * We only need to kick vcpu out of guest mode here, as PML buffer
5599          * is flushed at beginning of all VMEXITs, and it's obvious that only
5600          * vcpus running in guest are possible to have unflushed GPAs in PML
5601          * buffer.
5602          */
5603         kvm_for_each_vcpu(i, vcpu, kvm)
5604                 kvm_vcpu_kick(vcpu);
5605 }
5606
5607 static void vmx_dump_sel(char *name, uint32_t sel)
5608 {
5609         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5610                name, vmcs_read16(sel),
5611                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5612                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5613                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5614 }
5615
5616 static void vmx_dump_dtsel(char *name, uint32_t limit)
5617 {
5618         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5619                name, vmcs_read32(limit),
5620                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5621 }
5622
5623 void dump_vmcs(void)
5624 {
5625         u32 vmentry_ctl, vmexit_ctl;
5626         u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5627         unsigned long cr4;
5628         u64 efer;
5629         int i, n;
5630
5631         if (!dump_invalid_vmcs) {
5632                 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5633                 return;
5634         }
5635
5636         vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5637         vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5638         cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5639         pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5640         cr4 = vmcs_readl(GUEST_CR4);
5641         efer = vmcs_read64(GUEST_IA32_EFER);
5642         secondary_exec_control = 0;
5643         if (cpu_has_secondary_exec_ctrls())
5644                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5645
5646         pr_err("*** Guest State ***\n");
5647         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5648                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5649                vmcs_readl(CR0_GUEST_HOST_MASK));
5650         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5651                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5652         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5653         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5654             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5655         {
5656                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5657                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5658                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5659                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5660         }
5661         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5662                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5663         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5664                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5665         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5666                vmcs_readl(GUEST_SYSENTER_ESP),
5667                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5668         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5669         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5670         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5671         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5672         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5673         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5674         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5675         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5676         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5677         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5678         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5679             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5680                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5681                        efer, vmcs_read64(GUEST_IA32_PAT));
5682         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5683                vmcs_read64(GUEST_IA32_DEBUGCTL),
5684                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5685         if (cpu_has_load_perf_global_ctrl() &&
5686             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5687                 pr_err("PerfGlobCtl = 0x%016llx\n",
5688                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5689         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5690                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5691         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5692                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5693                vmcs_read32(GUEST_ACTIVITY_STATE));
5694         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5695                 pr_err("InterruptStatus = %04x\n",
5696                        vmcs_read16(GUEST_INTR_STATUS));
5697
5698         pr_err("*** Host State ***\n");
5699         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5700                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5701         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5702                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5703                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5704                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5705                vmcs_read16(HOST_TR_SELECTOR));
5706         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5707                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5708                vmcs_readl(HOST_TR_BASE));
5709         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5710                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5711         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5712                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5713                vmcs_readl(HOST_CR4));
5714         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5715                vmcs_readl(HOST_IA32_SYSENTER_ESP),
5716                vmcs_read32(HOST_IA32_SYSENTER_CS),
5717                vmcs_readl(HOST_IA32_SYSENTER_EIP));
5718         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5719                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5720                        vmcs_read64(HOST_IA32_EFER),
5721                        vmcs_read64(HOST_IA32_PAT));
5722         if (cpu_has_load_perf_global_ctrl() &&
5723             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5724                 pr_err("PerfGlobCtl = 0x%016llx\n",
5725                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5726
5727         pr_err("*** Control State ***\n");
5728         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5729                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5730         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5731         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5732                vmcs_read32(EXCEPTION_BITMAP),
5733                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5734                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5735         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5736                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5737                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5738                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5739         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5740                vmcs_read32(VM_EXIT_INTR_INFO),
5741                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5742                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5743         pr_err("        reason=%08x qualification=%016lx\n",
5744                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5745         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5746                vmcs_read32(IDT_VECTORING_INFO_FIELD),
5747                vmcs_read32(IDT_VECTORING_ERROR_CODE));
5748         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5749         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5750                 pr_err("TSC Multiplier = 0x%016llx\n",
5751                        vmcs_read64(TSC_MULTIPLIER));
5752         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5753                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5754                         u16 status = vmcs_read16(GUEST_INTR_STATUS);
5755                         pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5756                 }
5757                 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5758                 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5759                         pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5760                 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5761         }
5762         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5763                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5764         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5765                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5766         n = vmcs_read32(CR3_TARGET_COUNT);
5767         for (i = 0; i + 1 < n; i += 4)
5768                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5769                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5770                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5771         if (i < n)
5772                 pr_err("CR3 target%u=%016lx\n",
5773                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5774         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5775                 pr_err("PLE Gap=%08x Window=%08x\n",
5776                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5777         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5778                 pr_err("Virtual processor ID = 0x%04x\n",
5779                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
5780 }
5781
5782 /*
5783  * The guest has exited.  See if we can fix it or if we need userspace
5784  * assistance.
5785  */
5786 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5787 {
5788         struct vcpu_vmx *vmx = to_vmx(vcpu);
5789         u32 exit_reason = vmx->exit_reason;
5790         u32 vectoring_info = vmx->idt_vectoring_info;
5791
5792         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5793
5794         /*
5795          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5796          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5797          * querying dirty_bitmap, we only need to kick all vcpus out of guest
5798          * mode as if vcpus is in root mode, the PML buffer must has been
5799          * flushed already.
5800          */
5801         if (enable_pml)
5802                 vmx_flush_pml_buffer(vcpu);
5803
5804         /* If guest state is invalid, start emulating */
5805         if (vmx->emulation_required)
5806                 return handle_invalid_guest_state(vcpu);
5807
5808         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5809                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5810
5811         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5812                 dump_vmcs();
5813                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5814                 vcpu->run->fail_entry.hardware_entry_failure_reason
5815                         = exit_reason;
5816                 return 0;
5817         }
5818
5819         if (unlikely(vmx->fail)) {
5820                 dump_vmcs();
5821                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5822                 vcpu->run->fail_entry.hardware_entry_failure_reason
5823                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5824                 return 0;
5825         }
5826
5827         /*
5828          * Note:
5829          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5830          * delivery event since it indicates guest is accessing MMIO.
5831          * The vm-exit can be triggered again after return to guest that
5832          * will cause infinite loop.
5833          */
5834         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5835                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5836                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5837                         exit_reason != EXIT_REASON_PML_FULL &&
5838                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
5839                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5840                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5841                 vcpu->run->internal.ndata = 3;
5842                 vcpu->run->internal.data[0] = vectoring_info;
5843                 vcpu->run->internal.data[1] = exit_reason;
5844                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5845                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5846                         vcpu->run->internal.ndata++;
5847                         vcpu->run->internal.data[3] =
5848                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5849                 }
5850                 return 0;
5851         }
5852
5853         if (unlikely(!enable_vnmi &&
5854                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
5855                 if (vmx_interrupt_allowed(vcpu)) {
5856                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5857                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5858                            vcpu->arch.nmi_pending) {
5859                         /*
5860                          * This CPU don't support us in finding the end of an
5861                          * NMI-blocked window if the guest runs with IRQs
5862                          * disabled. So we pull the trigger after 1 s of
5863                          * futile waiting, but inform the user about this.
5864                          */
5865                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5866                                "state on VCPU %d after 1 s timeout\n",
5867                                __func__, vcpu->vcpu_id);
5868                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5869                 }
5870         }
5871
5872         if (exit_reason < kvm_vmx_max_exit_handlers
5873             && kvm_vmx_exit_handlers[exit_reason])
5874                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5875         else {
5876                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5877                                 exit_reason);
5878                 dump_vmcs();
5879                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5880                 vcpu->run->internal.suberror =
5881                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5882                 vcpu->run->internal.ndata = 1;
5883                 vcpu->run->internal.data[0] = exit_reason;
5884                 return 0;
5885         }
5886 }
5887
5888 /*
5889  * Software based L1D cache flush which is used when microcode providing
5890  * the cache control MSR is not loaded.
5891  *
5892  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5893  * flush it is required to read in 64 KiB because the replacement algorithm
5894  * is not exactly LRU. This could be sized at runtime via topology
5895  * information but as all relevant affected CPUs have 32KiB L1D cache size
5896  * there is no point in doing so.
5897  */
5898 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5899 {
5900         int size = PAGE_SIZE << L1D_CACHE_ORDER;
5901
5902         /*
5903          * This code is only executed when the the flush mode is 'cond' or
5904          * 'always'
5905          */
5906         if (static_branch_likely(&vmx_l1d_flush_cond)) {
5907                 bool flush_l1d;
5908
5909                 /*
5910                  * Clear the per-vcpu flush bit, it gets set again
5911                  * either from vcpu_run() or from one of the unsafe
5912                  * VMEXIT handlers.
5913                  */
5914                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5915                 vcpu->arch.l1tf_flush_l1d = false;
5916
5917                 /*
5918                  * Clear the per-cpu flush bit, it gets set again from
5919                  * the interrupt handlers.
5920                  */
5921                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5922                 kvm_clear_cpu_l1tf_flush_l1d();
5923
5924                 if (!flush_l1d)
5925                         return;
5926         }
5927
5928         vcpu->stat.l1d_flush++;
5929
5930         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5931                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5932                 return;
5933         }
5934
5935         asm volatile(
5936                 /* First ensure the pages are in the TLB */
5937                 "xorl   %%eax, %%eax\n"
5938                 ".Lpopulate_tlb:\n\t"
5939                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5940                 "addl   $4096, %%eax\n\t"
5941                 "cmpl   %%eax, %[size]\n\t"
5942                 "jne    .Lpopulate_tlb\n\t"
5943                 "xorl   %%eax, %%eax\n\t"
5944                 "cpuid\n\t"
5945                 /* Now fill the cache */
5946                 "xorl   %%eax, %%eax\n"
5947                 ".Lfill_cache:\n"
5948                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5949                 "addl   $64, %%eax\n\t"
5950                 "cmpl   %%eax, %[size]\n\t"
5951                 "jne    .Lfill_cache\n\t"
5952                 "lfence\n"
5953                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5954                     [size] "r" (size)
5955                 : "eax", "ebx", "ecx", "edx");
5956 }
5957
5958 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5959 {
5960         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5961
5962         if (is_guest_mode(vcpu) &&
5963                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5964                 return;
5965
5966         if (irr == -1 || tpr < irr) {
5967                 vmcs_write32(TPR_THRESHOLD, 0);
5968                 return;
5969         }
5970
5971         vmcs_write32(TPR_THRESHOLD, irr);
5972 }
5973
5974 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5975 {
5976         struct vcpu_vmx *vmx = to_vmx(vcpu);
5977         u32 sec_exec_control;
5978
5979         if (!lapic_in_kernel(vcpu))
5980                 return;
5981
5982         if (!flexpriority_enabled &&
5983             !cpu_has_vmx_virtualize_x2apic_mode())
5984                 return;
5985
5986         /* Postpone execution until vmcs01 is the current VMCS. */
5987         if (is_guest_mode(vcpu)) {
5988                 vmx->nested.change_vmcs01_virtual_apic_mode = true;
5989                 return;
5990         }
5991
5992         sec_exec_control = secondary_exec_controls_get(vmx);
5993         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
5994                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
5995
5996         switch (kvm_get_apic_mode(vcpu)) {
5997         case LAPIC_MODE_INVALID:
5998                 WARN_ONCE(true, "Invalid local APIC state");
5999         case LAPIC_MODE_DISABLED:
6000                 break;
6001         case LAPIC_MODE_XAPIC:
6002                 if (flexpriority_enabled) {
6003                         sec_exec_control |=
6004                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6005                         vmx_flush_tlb(vcpu, true);
6006                 }
6007                 break;
6008         case LAPIC_MODE_X2APIC:
6009                 if (cpu_has_vmx_virtualize_x2apic_mode())
6010                         sec_exec_control |=
6011                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6012                 break;
6013         }
6014         secondary_exec_controls_set(vmx, sec_exec_control);
6015
6016         vmx_update_msr_bitmap(vcpu);
6017 }
6018
6019 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6020 {
6021         if (!is_guest_mode(vcpu)) {
6022                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6023                 vmx_flush_tlb(vcpu, true);
6024         }
6025 }
6026
6027 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6028 {
6029         u16 status;
6030         u8 old;
6031
6032         if (max_isr == -1)
6033                 max_isr = 0;
6034
6035         status = vmcs_read16(GUEST_INTR_STATUS);
6036         old = status >> 8;
6037         if (max_isr != old) {
6038                 status &= 0xff;
6039                 status |= max_isr << 8;
6040                 vmcs_write16(GUEST_INTR_STATUS, status);
6041         }
6042 }
6043
6044 static void vmx_set_rvi(int vector)
6045 {
6046         u16 status;
6047         u8 old;
6048
6049         if (vector == -1)
6050                 vector = 0;
6051
6052         status = vmcs_read16(GUEST_INTR_STATUS);
6053         old = (u8)status & 0xff;
6054         if ((u8)vector != old) {
6055                 status &= ~0xff;
6056                 status |= (u8)vector;
6057                 vmcs_write16(GUEST_INTR_STATUS, status);
6058         }
6059 }
6060
6061 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6062 {
6063         /*
6064          * When running L2, updating RVI is only relevant when
6065          * vmcs12 virtual-interrupt-delivery enabled.
6066          * However, it can be enabled only when L1 also
6067          * intercepts external-interrupts and in that case
6068          * we should not update vmcs02 RVI but instead intercept
6069          * interrupt. Therefore, do nothing when running L2.
6070          */
6071         if (!is_guest_mode(vcpu))
6072                 vmx_set_rvi(max_irr);
6073 }
6074
6075 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6076 {
6077         struct vcpu_vmx *vmx = to_vmx(vcpu);
6078         int max_irr;
6079         bool max_irr_updated;
6080
6081         WARN_ON(!vcpu->arch.apicv_active);
6082         if (pi_test_on(&vmx->pi_desc)) {
6083                 pi_clear_on(&vmx->pi_desc);
6084                 /*
6085                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6086                  * But on x86 this is just a compiler barrier anyway.
6087                  */
6088                 smp_mb__after_atomic();
6089                 max_irr_updated =
6090                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6091
6092                 /*
6093                  * If we are running L2 and L1 has a new pending interrupt
6094                  * which can be injected, we should re-evaluate
6095                  * what should be done with this new L1 interrupt.
6096                  * If L1 intercepts external-interrupts, we should
6097                  * exit from L2 to L1. Otherwise, interrupt should be
6098                  * delivered directly to L2.
6099                  */
6100                 if (is_guest_mode(vcpu) && max_irr_updated) {
6101                         if (nested_exit_on_intr(vcpu))
6102                                 kvm_vcpu_exiting_guest_mode(vcpu);
6103                         else
6104                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6105                 }
6106         } else {
6107                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6108         }
6109         vmx_hwapic_irr_update(vcpu, max_irr);
6110         return max_irr;
6111 }
6112
6113 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6114 {
6115         return pi_test_on(vcpu_to_pi_desc(vcpu));
6116 }
6117
6118 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6119 {
6120         if (!kvm_vcpu_apicv_active(vcpu))
6121                 return;
6122
6123         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6124         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6125         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6126         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6127 }
6128
6129 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6130 {
6131         struct vcpu_vmx *vmx = to_vmx(vcpu);
6132
6133         pi_clear_on(&vmx->pi_desc);
6134         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6135 }
6136
6137 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6138 {
6139         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6140
6141         /* if exit due to PF check for async PF */
6142         if (is_page_fault(vmx->exit_intr_info))
6143                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6144
6145         /* Handle machine checks before interrupts are enabled */
6146         if (is_machine_check(vmx->exit_intr_info))
6147                 kvm_machine_check();
6148
6149         /* We need to handle NMIs before interrupts are enabled */
6150         if (is_nmi(vmx->exit_intr_info)) {
6151                 kvm_before_interrupt(&vmx->vcpu);
6152                 asm("int $2");
6153                 kvm_after_interrupt(&vmx->vcpu);
6154         }
6155 }
6156
6157 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6158 {
6159         unsigned int vector;
6160         unsigned long entry;
6161 #ifdef CONFIG_X86_64
6162         unsigned long tmp;
6163 #endif
6164         gate_desc *desc;
6165         u32 intr_info;
6166
6167         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6168         if (WARN_ONCE(!is_external_intr(intr_info),
6169             "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6170                 return;
6171
6172         vector = intr_info & INTR_INFO_VECTOR_MASK;
6173         desc = (gate_desc *)host_idt_base + vector;
6174         entry = gate_offset(desc);
6175
6176         kvm_before_interrupt(vcpu);
6177
6178         asm volatile(
6179 #ifdef CONFIG_X86_64
6180                 "mov %%" _ASM_SP ", %[sp]\n\t"
6181                 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6182                 "push $%c[ss]\n\t"
6183                 "push %[sp]\n\t"
6184 #endif
6185                 "pushf\n\t"
6186                 __ASM_SIZE(push) " $%c[cs]\n\t"
6187                 CALL_NOSPEC
6188                 :
6189 #ifdef CONFIG_X86_64
6190                 [sp]"=&r"(tmp),
6191 #endif
6192                 ASM_CALL_CONSTRAINT
6193                 :
6194                 THUNK_TARGET(entry),
6195                 [ss]"i"(__KERNEL_DS),
6196                 [cs]"i"(__KERNEL_CS)
6197         );
6198
6199         kvm_after_interrupt(vcpu);
6200 }
6201 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6202
6203 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6204 {
6205         struct vcpu_vmx *vmx = to_vmx(vcpu);
6206
6207         if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6208                 handle_external_interrupt_irqoff(vcpu);
6209         else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6210                 handle_exception_nmi_irqoff(vmx);
6211 }
6212
6213 static bool vmx_has_emulated_msr(int index)
6214 {
6215         switch (index) {
6216         case MSR_IA32_SMBASE:
6217                 /*
6218                  * We cannot do SMM unless we can run the guest in big
6219                  * real mode.
6220                  */
6221                 return enable_unrestricted_guest || emulate_invalid_guest_state;
6222         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6223                 return nested;
6224         case MSR_AMD64_VIRT_SPEC_CTRL:
6225                 /* This is AMD only.  */
6226                 return false;
6227         default:
6228                 return true;
6229         }
6230 }
6231
6232 static bool vmx_pt_supported(void)
6233 {
6234         return pt_mode == PT_MODE_HOST_GUEST;
6235 }
6236
6237 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6238 {
6239         u32 exit_intr_info;
6240         bool unblock_nmi;
6241         u8 vector;
6242         bool idtv_info_valid;
6243
6244         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6245
6246         if (enable_vnmi) {
6247                 if (vmx->loaded_vmcs->nmi_known_unmasked)
6248                         return;
6249                 /*
6250                  * Can't use vmx->exit_intr_info since we're not sure what
6251                  * the exit reason is.
6252                  */
6253                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6254                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6255                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6256                 /*
6257                  * SDM 3: 27.7.1.2 (September 2008)
6258                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6259                  * a guest IRET fault.
6260                  * SDM 3: 23.2.2 (September 2008)
6261                  * Bit 12 is undefined in any of the following cases:
6262                  *  If the VM exit sets the valid bit in the IDT-vectoring
6263                  *   information field.
6264                  *  If the VM exit is due to a double fault.
6265                  */
6266                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6267                     vector != DF_VECTOR && !idtv_info_valid)
6268                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6269                                       GUEST_INTR_STATE_NMI);
6270                 else
6271                         vmx->loaded_vmcs->nmi_known_unmasked =
6272                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6273                                   & GUEST_INTR_STATE_NMI);
6274         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6275                 vmx->loaded_vmcs->vnmi_blocked_time +=
6276                         ktime_to_ns(ktime_sub(ktime_get(),
6277                                               vmx->loaded_vmcs->entry_time));
6278 }
6279
6280 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6281                                       u32 idt_vectoring_info,
6282                                       int instr_len_field,
6283                                       int error_code_field)
6284 {
6285         u8 vector;
6286         int type;
6287         bool idtv_info_valid;
6288
6289         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6290
6291         vcpu->arch.nmi_injected = false;
6292         kvm_clear_exception_queue(vcpu);
6293         kvm_clear_interrupt_queue(vcpu);
6294
6295         if (!idtv_info_valid)
6296                 return;
6297
6298         kvm_make_request(KVM_REQ_EVENT, vcpu);
6299
6300         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6301         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6302
6303         switch (type) {
6304         case INTR_TYPE_NMI_INTR:
6305                 vcpu->arch.nmi_injected = true;
6306                 /*
6307                  * SDM 3: 27.7.1.2 (September 2008)
6308                  * Clear bit "block by NMI" before VM entry if a NMI
6309                  * delivery faulted.
6310                  */
6311                 vmx_set_nmi_mask(vcpu, false);
6312                 break;
6313         case INTR_TYPE_SOFT_EXCEPTION:
6314                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6315                 /* fall through */
6316         case INTR_TYPE_HARD_EXCEPTION:
6317                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6318                         u32 err = vmcs_read32(error_code_field);
6319                         kvm_requeue_exception_e(vcpu, vector, err);
6320                 } else
6321                         kvm_requeue_exception(vcpu, vector);
6322                 break;
6323         case INTR_TYPE_SOFT_INTR:
6324                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6325                 /* fall through */
6326         case INTR_TYPE_EXT_INTR:
6327                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6328                 break;
6329         default:
6330                 break;
6331         }
6332 }
6333
6334 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6335 {
6336         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6337                                   VM_EXIT_INSTRUCTION_LEN,
6338                                   IDT_VECTORING_ERROR_CODE);
6339 }
6340
6341 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6342 {
6343         __vmx_complete_interrupts(vcpu,
6344                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6345                                   VM_ENTRY_INSTRUCTION_LEN,
6346                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6347
6348         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6349 }
6350
6351 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6352 {
6353         int i, nr_msrs;
6354         struct perf_guest_switch_msr *msrs;
6355
6356         msrs = perf_guest_get_msrs(&nr_msrs);
6357
6358         if (!msrs)
6359                 return;
6360
6361         for (i = 0; i < nr_msrs; i++)
6362                 if (msrs[i].host == msrs[i].guest)
6363                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6364                 else
6365                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6366                                         msrs[i].host, false);
6367 }
6368
6369 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6370 {
6371         struct vcpu_vmx *vmx = to_vmx(vcpu);
6372         u64 tscl;
6373         u32 delta_tsc;
6374
6375         if (vmx->req_immediate_exit) {
6376                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6377                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6378         } else if (vmx->hv_deadline_tsc != -1) {
6379                 tscl = rdtsc();
6380                 if (vmx->hv_deadline_tsc > tscl)
6381                         /* set_hv_timer ensures the delta fits in 32-bits */
6382                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6383                                 cpu_preemption_timer_multi);
6384                 else
6385                         delta_tsc = 0;
6386
6387                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6388                 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6389         } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6390                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6391                 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6392         }
6393 }
6394
6395 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6396 {
6397         if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6398                 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6399                 vmcs_writel(HOST_RSP, host_rsp);
6400         }
6401 }
6402
6403 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6404
6405 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6406 {
6407         struct vcpu_vmx *vmx = to_vmx(vcpu);
6408         unsigned long cr3, cr4;
6409
6410         /* Record the guest's net vcpu time for enforced NMI injections. */
6411         if (unlikely(!enable_vnmi &&
6412                      vmx->loaded_vmcs->soft_vnmi_blocked))
6413                 vmx->loaded_vmcs->entry_time = ktime_get();
6414
6415         /* Don't enter VMX if guest state is invalid, let the exit handler
6416            start emulation until we arrive back to a valid state */
6417         if (vmx->emulation_required)
6418                 return;
6419
6420         if (vmx->ple_window_dirty) {
6421                 vmx->ple_window_dirty = false;
6422                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6423         }
6424
6425         if (vmx->nested.need_vmcs12_to_shadow_sync)
6426                 nested_sync_vmcs12_to_shadow(vcpu);
6427
6428         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6429                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6430         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6431                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6432
6433         cr3 = __get_current_cr3_fast();
6434         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6435                 vmcs_writel(HOST_CR3, cr3);
6436                 vmx->loaded_vmcs->host_state.cr3 = cr3;
6437         }
6438
6439         cr4 = cr4_read_shadow();
6440         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6441                 vmcs_writel(HOST_CR4, cr4);
6442                 vmx->loaded_vmcs->host_state.cr4 = cr4;
6443         }
6444
6445         /* When single-stepping over STI and MOV SS, we must clear the
6446          * corresponding interruptibility bits in the guest state. Otherwise
6447          * vmentry fails as it then expects bit 14 (BS) in pending debug
6448          * exceptions being set, but that's not correct for the guest debugging
6449          * case. */
6450         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6451                 vmx_set_interrupt_shadow(vcpu, 0);
6452
6453         kvm_load_guest_xcr0(vcpu);
6454
6455         if (static_cpu_has(X86_FEATURE_PKU) &&
6456             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6457             vcpu->arch.pkru != vmx->host_pkru)
6458                 __write_pkru(vcpu->arch.pkru);
6459
6460         pt_guest_enter(vmx);
6461
6462         atomic_switch_perf_msrs(vmx);
6463
6464         if (enable_preemption_timer)
6465                 vmx_update_hv_timer(vcpu);
6466
6467         if (lapic_in_kernel(vcpu) &&
6468                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6469                 kvm_wait_lapic_expire(vcpu);
6470
6471         /*
6472          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6473          * it's non-zero. Since vmentry is serialising on affected CPUs, there
6474          * is no need to worry about the conditional branch over the wrmsr
6475          * being speculatively taken.
6476          */
6477         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6478
6479         /* L1D Flush includes CPU buffer clear to mitigate MDS */
6480         if (static_branch_unlikely(&vmx_l1d_should_flush))
6481                 vmx_l1d_flush(vcpu);
6482         else if (static_branch_unlikely(&mds_user_clear))
6483                 mds_clear_cpu_buffers();
6484
6485         if (vcpu->arch.cr2 != read_cr2())
6486                 write_cr2(vcpu->arch.cr2);
6487
6488         vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6489                                    vmx->loaded_vmcs->launched);
6490
6491         vcpu->arch.cr2 = read_cr2();
6492
6493         /*
6494          * We do not use IBRS in the kernel. If this vCPU has used the
6495          * SPEC_CTRL MSR it may have left it on; save the value and
6496          * turn it off. This is much more efficient than blindly adding
6497          * it to the atomic save/restore list. Especially as the former
6498          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6499          *
6500          * For non-nested case:
6501          * If the L01 MSR bitmap does not intercept the MSR, then we need to
6502          * save it.
6503          *
6504          * For nested case:
6505          * If the L02 MSR bitmap does not intercept the MSR, then we need to
6506          * save it.
6507          */
6508         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6509                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6510
6511         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6512
6513         /* All fields are clean at this point */
6514         if (static_branch_unlikely(&enable_evmcs))
6515                 current_evmcs->hv_clean_fields |=
6516                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6517
6518         if (static_branch_unlikely(&enable_evmcs))
6519                 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6520
6521         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6522         if (vmx->host_debugctlmsr)
6523                 update_debugctlmsr(vmx->host_debugctlmsr);
6524
6525 #ifndef CONFIG_X86_64
6526         /*
6527          * The sysexit path does not restore ds/es, so we must set them to
6528          * a reasonable value ourselves.
6529          *
6530          * We can't defer this to vmx_prepare_switch_to_host() since that
6531          * function may be executed in interrupt context, which saves and
6532          * restore segments around it, nullifying its effect.
6533          */
6534         loadsegment(ds, __USER_DS);
6535         loadsegment(es, __USER_DS);
6536 #endif
6537
6538         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6539                                   | (1 << VCPU_EXREG_RFLAGS)
6540                                   | (1 << VCPU_EXREG_PDPTR)
6541                                   | (1 << VCPU_EXREG_SEGMENTS)
6542                                   | (1 << VCPU_EXREG_CR3));
6543         vcpu->arch.regs_dirty = 0;
6544
6545         pt_guest_exit(vmx);
6546
6547         /*
6548          * eager fpu is enabled if PKEY is supported and CR4 is switched
6549          * back on host, so it is safe to read guest PKRU from current
6550          * XSAVE.
6551          */
6552         if (static_cpu_has(X86_FEATURE_PKU) &&
6553             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6554                 vcpu->arch.pkru = rdpkru();
6555                 if (vcpu->arch.pkru != vmx->host_pkru)
6556                         __write_pkru(vmx->host_pkru);
6557         }
6558
6559         kvm_put_guest_xcr0(vcpu);
6560
6561         vmx->nested.nested_run_pending = 0;
6562         vmx->idt_vectoring_info = 0;
6563
6564         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6565         if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6566                 kvm_machine_check();
6567
6568         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6569                 return;
6570
6571         vmx->loaded_vmcs->launched = 1;
6572         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6573
6574         vmx_recover_nmi_blocking(vmx);
6575         vmx_complete_interrupts(vmx);
6576 }
6577
6578 static struct kvm *vmx_vm_alloc(void)
6579 {
6580         struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6581                                             GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6582                                             PAGE_KERNEL);
6583         return &kvm_vmx->kvm;
6584 }
6585
6586 static void vmx_vm_free(struct kvm *kvm)
6587 {
6588         kfree(kvm->arch.hyperv.hv_pa_pg);
6589         vfree(to_kvm_vmx(kvm));
6590 }
6591
6592 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6593 {
6594         struct vcpu_vmx *vmx = to_vmx(vcpu);
6595
6596         if (enable_pml)
6597                 vmx_destroy_pml_buffer(vmx);
6598         free_vpid(vmx->vpid);
6599         nested_vmx_free_vcpu(vcpu);
6600         free_loaded_vmcs(vmx->loaded_vmcs);
6601         kfree(vmx->guest_msrs);
6602         kvm_vcpu_uninit(vcpu);
6603         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6604         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6605         kmem_cache_free(kvm_vcpu_cache, vmx);
6606 }
6607
6608 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6609 {
6610         int err;
6611         struct vcpu_vmx *vmx;
6612         unsigned long *msr_bitmap;
6613         int cpu;
6614
6615         BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6616                 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6617
6618         vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6619         if (!vmx)
6620                 return ERR_PTR(-ENOMEM);
6621
6622         vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6623                         GFP_KERNEL_ACCOUNT);
6624         if (!vmx->vcpu.arch.user_fpu) {
6625                 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6626                 err = -ENOMEM;
6627                 goto free_partial_vcpu;
6628         }
6629
6630         vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6631                         GFP_KERNEL_ACCOUNT);
6632         if (!vmx->vcpu.arch.guest_fpu) {
6633                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6634                 err = -ENOMEM;
6635                 goto free_user_fpu;
6636         }
6637
6638         vmx->vpid = allocate_vpid();
6639
6640         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6641         if (err)
6642                 goto free_vcpu;
6643
6644         err = -ENOMEM;
6645
6646         /*
6647          * If PML is turned on, failure on enabling PML just results in failure
6648          * of creating the vcpu, therefore we can simplify PML logic (by
6649          * avoiding dealing with cases, such as enabling PML partially on vcpus
6650          * for the guest, etc.
6651          */
6652         if (enable_pml) {
6653                 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6654                 if (!vmx->pml_pg)
6655                         goto uninit_vcpu;
6656         }
6657
6658         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6659         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6660                      > PAGE_SIZE);
6661
6662         if (!vmx->guest_msrs)
6663                 goto free_pml;
6664
6665         err = alloc_loaded_vmcs(&vmx->vmcs01);
6666         if (err < 0)
6667                 goto free_msrs;
6668
6669         msr_bitmap = vmx->vmcs01.msr_bitmap;
6670         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6671         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6672         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6673         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6674         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6675         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6676         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6677         if (kvm_cstate_in_guest(kvm)) {
6678                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6679                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6680                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6681                 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6682         }
6683         vmx->msr_bitmap_mode = 0;
6684
6685         vmx->loaded_vmcs = &vmx->vmcs01;
6686         cpu = get_cpu();
6687         vmx_vcpu_load(&vmx->vcpu, cpu);
6688         vmx->vcpu.cpu = cpu;
6689         vmx_vcpu_setup(vmx);
6690         vmx_vcpu_put(&vmx->vcpu);
6691         put_cpu();
6692         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6693                 err = alloc_apic_access_page(kvm);
6694                 if (err)
6695                         goto free_vmcs;
6696         }
6697
6698         if (enable_ept && !enable_unrestricted_guest) {
6699                 err = init_rmode_identity_map(kvm);
6700                 if (err)
6701                         goto free_vmcs;
6702         }
6703
6704         if (nested)
6705                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6706                                            vmx_capability.ept,
6707                                            kvm_vcpu_apicv_active(&vmx->vcpu));
6708         else
6709                 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6710
6711         vmx->nested.posted_intr_nv = -1;
6712         vmx->nested.current_vmptr = -1ull;
6713
6714         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6715
6716         /*
6717          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6718          * or POSTED_INTR_WAKEUP_VECTOR.
6719          */
6720         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6721         vmx->pi_desc.sn = 1;
6722
6723         vmx->ept_pointer = INVALID_PAGE;
6724
6725         return &vmx->vcpu;
6726
6727 free_vmcs:
6728         free_loaded_vmcs(vmx->loaded_vmcs);
6729 free_msrs:
6730         kfree(vmx->guest_msrs);
6731 free_pml:
6732         vmx_destroy_pml_buffer(vmx);
6733 uninit_vcpu:
6734         kvm_vcpu_uninit(&vmx->vcpu);
6735 free_vcpu:
6736         free_vpid(vmx->vpid);
6737         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6738 free_user_fpu:
6739         kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6740 free_partial_vcpu:
6741         kmem_cache_free(kvm_vcpu_cache, vmx);
6742         return ERR_PTR(err);
6743 }
6744
6745 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6746 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6747
6748 static int vmx_vm_init(struct kvm *kvm)
6749 {
6750         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6751
6752         if (!ple_gap)
6753                 kvm->arch.pause_in_guest = true;
6754
6755         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6756                 switch (l1tf_mitigation) {
6757                 case L1TF_MITIGATION_OFF:
6758                 case L1TF_MITIGATION_FLUSH_NOWARN:
6759                         /* 'I explicitly don't care' is set */
6760                         break;
6761                 case L1TF_MITIGATION_FLUSH:
6762                 case L1TF_MITIGATION_FLUSH_NOSMT:
6763                 case L1TF_MITIGATION_FULL:
6764                         /*
6765                          * Warn upon starting the first VM in a potentially
6766                          * insecure environment.
6767                          */
6768                         if (sched_smt_active())
6769                                 pr_warn_once(L1TF_MSG_SMT);
6770                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6771                                 pr_warn_once(L1TF_MSG_L1D);
6772                         break;
6773                 case L1TF_MITIGATION_FULL_FORCE:
6774                         /* Flush is enforced */
6775                         break;
6776                 }
6777         }
6778         return 0;
6779 }
6780
6781 static int __init vmx_check_processor_compat(void)
6782 {
6783         struct vmcs_config vmcs_conf;
6784         struct vmx_capability vmx_cap;
6785
6786         if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6787                 return -EIO;
6788         if (nested)
6789                 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6790                                            enable_apicv);
6791         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6792                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6793                                 smp_processor_id());
6794                 return -EIO;
6795         }
6796         return 0;
6797 }
6798
6799 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6800 {
6801         u8 cache;
6802         u64 ipat = 0;
6803
6804         /* For VT-d and EPT combination
6805          * 1. MMIO: always map as UC
6806          * 2. EPT with VT-d:
6807          *   a. VT-d without snooping control feature: can't guarantee the
6808          *      result, try to trust guest.
6809          *   b. VT-d with snooping control feature: snooping control feature of
6810          *      VT-d engine can guarantee the cache correctness. Just set it
6811          *      to WB to keep consistent with host. So the same as item 3.
6812          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6813          *    consistent with host MTRR
6814          */
6815         if (is_mmio) {
6816                 cache = MTRR_TYPE_UNCACHABLE;
6817                 goto exit;
6818         }
6819
6820         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6821                 ipat = VMX_EPT_IPAT_BIT;
6822                 cache = MTRR_TYPE_WRBACK;
6823                 goto exit;
6824         }
6825
6826         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6827                 ipat = VMX_EPT_IPAT_BIT;
6828                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6829                         cache = MTRR_TYPE_WRBACK;
6830                 else
6831                         cache = MTRR_TYPE_UNCACHABLE;
6832                 goto exit;
6833         }
6834
6835         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6836
6837 exit:
6838         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6839 }
6840
6841 static int vmx_get_lpage_level(void)
6842 {
6843         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6844                 return PT_DIRECTORY_LEVEL;
6845         else
6846                 /* For shadow and EPT supported 1GB page */
6847                 return PT_PDPE_LEVEL;
6848 }
6849
6850 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6851 {
6852         /*
6853          * These bits in the secondary execution controls field
6854          * are dynamic, the others are mostly based on the hypervisor
6855          * architecture and the guest's CPUID.  Do not touch the
6856          * dynamic bits.
6857          */
6858         u32 mask =
6859                 SECONDARY_EXEC_SHADOW_VMCS |
6860                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6861                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6862                 SECONDARY_EXEC_DESC;
6863
6864         u32 new_ctl = vmx->secondary_exec_control;
6865         u32 cur_ctl = secondary_exec_controls_get(vmx);
6866
6867         secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6868 }
6869
6870 /*
6871  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6872  * (indicating "allowed-1") if they are supported in the guest's CPUID.
6873  */
6874 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6875 {
6876         struct vcpu_vmx *vmx = to_vmx(vcpu);
6877         struct kvm_cpuid_entry2 *entry;
6878
6879         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6880         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6881
6882 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
6883         if (entry && (entry->_reg & (_cpuid_mask)))                     \
6884                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
6885 } while (0)
6886
6887         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6888         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
6889         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
6890         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
6891         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
6892         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
6893         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
6894         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
6895         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
6896         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
6897         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6898         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
6899         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
6900         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
6901         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
6902
6903         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6904         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
6905         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
6906         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
6907         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
6908         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
6909
6910 #undef cr4_fixed1_update
6911 }
6912
6913 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6914 {
6915         struct vcpu_vmx *vmx = to_vmx(vcpu);
6916
6917         if (kvm_mpx_supported()) {
6918                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6919
6920                 if (mpx_enabled) {
6921                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6922                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6923                 } else {
6924                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6925                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6926                 }
6927         }
6928 }
6929
6930 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6931 {
6932         struct vcpu_vmx *vmx = to_vmx(vcpu);
6933         struct kvm_cpuid_entry2 *best = NULL;
6934         int i;
6935
6936         for (i = 0; i < PT_CPUID_LEAVES; i++) {
6937                 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6938                 if (!best)
6939                         return;
6940                 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6941                 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6942                 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6943                 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6944         }
6945
6946         /* Get the number of configurable Address Ranges for filtering */
6947         vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6948                                                 PT_CAP_num_address_ranges);
6949
6950         /* Initialize and clear the no dependency bits */
6951         vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6952                         RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6953
6954         /*
6955          * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6956          * will inject an #GP
6957          */
6958         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6959                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6960
6961         /*
6962          * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6963          * PSBFreq can be set
6964          */
6965         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6966                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6967                                 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6968
6969         /*
6970          * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6971          * MTCFreq can be set
6972          */
6973         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6974                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6975                                 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6976
6977         /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6978         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6979                 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6980                                                         RTIT_CTL_PTW_EN);
6981
6982         /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
6983         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
6984                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
6985
6986         /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
6987         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
6988                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
6989
6990         /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
6991         if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
6992                 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
6993
6994         /* unmask address range configure area */
6995         for (i = 0; i < vmx->pt_desc.addr_range; i++)
6996                 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6997 }
6998
6999 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7000 {
7001         struct vcpu_vmx *vmx = to_vmx(vcpu);
7002
7003         if (cpu_has_secondary_exec_ctrls()) {
7004                 vmx_compute_secondary_exec_control(vmx);
7005                 vmcs_set_secondary_exec_control(vmx);
7006         }
7007
7008         if (nested_vmx_allowed(vcpu))
7009                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7010                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7011         else
7012                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7013                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7014
7015         if (nested_vmx_allowed(vcpu)) {
7016                 nested_vmx_cr_fixed1_bits_update(vcpu);
7017                 nested_vmx_entry_exit_ctls_update(vcpu);
7018         }
7019
7020         if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7021                         guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7022                 update_intel_pt_cfg(vcpu);
7023 }
7024
7025 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7026 {
7027         if (func == 1 && nested)
7028                 entry->ecx |= bit(X86_FEATURE_VMX);
7029 }
7030
7031 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7032 {
7033         to_vmx(vcpu)->req_immediate_exit = true;
7034 }
7035
7036 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7037                                struct x86_instruction_info *info,
7038                                enum x86_intercept_stage stage)
7039 {
7040         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7041         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7042
7043         /*
7044          * RDPID causes #UD if disabled through secondary execution controls.
7045          * Because it is marked as EmulateOnUD, we need to intercept it here.
7046          */
7047         if (info->intercept == x86_intercept_rdtscp &&
7048             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7049                 ctxt->exception.vector = UD_VECTOR;
7050                 ctxt->exception.error_code_valid = false;
7051                 return X86EMUL_PROPAGATE_FAULT;
7052         }
7053
7054         /* TODO: check more intercepts... */
7055         return X86EMUL_CONTINUE;
7056 }
7057
7058 #ifdef CONFIG_X86_64
7059 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7060 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7061                                   u64 divisor, u64 *result)
7062 {
7063         u64 low = a << shift, high = a >> (64 - shift);
7064
7065         /* To avoid the overflow on divq */
7066         if (high >= divisor)
7067                 return 1;
7068
7069         /* Low hold the result, high hold rem which is discarded */
7070         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7071             "rm" (divisor), "0" (low), "1" (high));
7072         *result = low;
7073
7074         return 0;
7075 }
7076
7077 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7078                             bool *expired)
7079 {
7080         struct vcpu_vmx *vmx;
7081         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7082         struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7083
7084         if (kvm_mwait_in_guest(vcpu->kvm) ||
7085                 kvm_can_post_timer_interrupt(vcpu))
7086                 return -EOPNOTSUPP;
7087
7088         vmx = to_vmx(vcpu);
7089         tscl = rdtsc();
7090         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7091         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7092         lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7093                                                     ktimer->timer_advance_ns);
7094
7095         if (delta_tsc > lapic_timer_advance_cycles)
7096                 delta_tsc -= lapic_timer_advance_cycles;
7097         else
7098                 delta_tsc = 0;
7099
7100         /* Convert to host delta tsc if tsc scaling is enabled */
7101         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7102             delta_tsc && u64_shl_div_u64(delta_tsc,
7103                                 kvm_tsc_scaling_ratio_frac_bits,
7104                                 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7105                 return -ERANGE;
7106
7107         /*
7108          * If the delta tsc can't fit in the 32 bit after the multi shift,
7109          * we can't use the preemption timer.
7110          * It's possible that it fits on later vmentries, but checking
7111          * on every vmentry is costly so we just use an hrtimer.
7112          */
7113         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7114                 return -ERANGE;
7115
7116         vmx->hv_deadline_tsc = tscl + delta_tsc;
7117         *expired = !delta_tsc;
7118         return 0;
7119 }
7120
7121 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7122 {
7123         to_vmx(vcpu)->hv_deadline_tsc = -1;
7124 }
7125 #endif
7126
7127 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7128 {
7129         if (!kvm_pause_in_guest(vcpu->kvm))
7130                 shrink_ple_window(vcpu);
7131 }
7132
7133 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7134                                      struct kvm_memory_slot *slot)
7135 {
7136         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7137         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7138 }
7139
7140 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7141                                        struct kvm_memory_slot *slot)
7142 {
7143         kvm_mmu_slot_set_dirty(kvm, slot);
7144 }
7145
7146 static void vmx_flush_log_dirty(struct kvm *kvm)
7147 {
7148         kvm_flush_pml_buffers(kvm);
7149 }
7150
7151 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7152 {
7153         struct vmcs12 *vmcs12;
7154         struct vcpu_vmx *vmx = to_vmx(vcpu);
7155         gpa_t gpa, dst;
7156
7157         if (is_guest_mode(vcpu)) {
7158                 WARN_ON_ONCE(vmx->nested.pml_full);
7159
7160                 /*
7161                  * Check if PML is enabled for the nested guest.
7162                  * Whether eptp bit 6 is set is already checked
7163                  * as part of A/D emulation.
7164                  */
7165                 vmcs12 = get_vmcs12(vcpu);
7166                 if (!nested_cpu_has_pml(vmcs12))
7167                         return 0;
7168
7169                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7170                         vmx->nested.pml_full = true;
7171                         return 1;
7172                 }
7173
7174                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7175                 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7176
7177                 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7178                                          offset_in_page(dst), sizeof(gpa)))
7179                         return 0;
7180
7181                 vmcs12->guest_pml_index--;
7182         }
7183
7184         return 0;
7185 }
7186
7187 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7188                                            struct kvm_memory_slot *memslot,
7189                                            gfn_t offset, unsigned long mask)
7190 {
7191         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7192 }
7193
7194 static void __pi_post_block(struct kvm_vcpu *vcpu)
7195 {
7196         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7197         struct pi_desc old, new;
7198         unsigned int dest;
7199
7200         do {
7201                 old.control = new.control = pi_desc->control;
7202                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7203                      "Wakeup handler not enabled while the VCPU is blocked\n");
7204
7205                 dest = cpu_physical_id(vcpu->cpu);
7206
7207                 if (x2apic_enabled())
7208                         new.ndst = dest;
7209                 else
7210                         new.ndst = (dest << 8) & 0xFF00;
7211
7212                 /* set 'NV' to 'notification vector' */
7213                 new.nv = POSTED_INTR_VECTOR;
7214         } while (cmpxchg64(&pi_desc->control, old.control,
7215                            new.control) != old.control);
7216
7217         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7218                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7219                 list_del(&vcpu->blocked_vcpu_list);
7220                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7221                 vcpu->pre_pcpu = -1;
7222         }
7223 }
7224
7225 /*
7226  * This routine does the following things for vCPU which is going
7227  * to be blocked if VT-d PI is enabled.
7228  * - Store the vCPU to the wakeup list, so when interrupts happen
7229  *   we can find the right vCPU to wake up.
7230  * - Change the Posted-interrupt descriptor as below:
7231  *      'NDST' <-- vcpu->pre_pcpu
7232  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7233  * - If 'ON' is set during this process, which means at least one
7234  *   interrupt is posted for this vCPU, we cannot block it, in
7235  *   this case, return 1, otherwise, return 0.
7236  *
7237  */
7238 static int pi_pre_block(struct kvm_vcpu *vcpu)
7239 {
7240         unsigned int dest;
7241         struct pi_desc old, new;
7242         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7243
7244         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7245                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
7246                 !kvm_vcpu_apicv_active(vcpu))
7247                 return 0;
7248
7249         WARN_ON(irqs_disabled());
7250         local_irq_disable();
7251         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7252                 vcpu->pre_pcpu = vcpu->cpu;
7253                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7254                 list_add_tail(&vcpu->blocked_vcpu_list,
7255                               &per_cpu(blocked_vcpu_on_cpu,
7256                                        vcpu->pre_pcpu));
7257                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7258         }
7259
7260         do {
7261                 old.control = new.control = pi_desc->control;
7262
7263                 WARN((pi_desc->sn == 1),
7264                      "Warning: SN field of posted-interrupts "
7265                      "is set before blocking\n");
7266
7267                 /*
7268                  * Since vCPU can be preempted during this process,
7269                  * vcpu->cpu could be different with pre_pcpu, we
7270                  * need to set pre_pcpu as the destination of wakeup
7271                  * notification event, then we can find the right vCPU
7272                  * to wakeup in wakeup handler if interrupts happen
7273                  * when the vCPU is in blocked state.
7274                  */
7275                 dest = cpu_physical_id(vcpu->pre_pcpu);
7276
7277                 if (x2apic_enabled())
7278                         new.ndst = dest;
7279                 else
7280                         new.ndst = (dest << 8) & 0xFF00;
7281
7282                 /* set 'NV' to 'wakeup vector' */
7283                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7284         } while (cmpxchg64(&pi_desc->control, old.control,
7285                            new.control) != old.control);
7286
7287         /* We should not block the vCPU if an interrupt is posted for it.  */
7288         if (pi_test_on(pi_desc) == 1)
7289                 __pi_post_block(vcpu);
7290
7291         local_irq_enable();
7292         return (vcpu->pre_pcpu == -1);
7293 }
7294
7295 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7296 {
7297         if (pi_pre_block(vcpu))
7298                 return 1;
7299
7300         if (kvm_lapic_hv_timer_in_use(vcpu))
7301                 kvm_lapic_switch_to_sw_timer(vcpu);
7302
7303         return 0;
7304 }
7305
7306 static void pi_post_block(struct kvm_vcpu *vcpu)
7307 {
7308         if (vcpu->pre_pcpu == -1)
7309                 return;
7310
7311         WARN_ON(irqs_disabled());
7312         local_irq_disable();
7313         __pi_post_block(vcpu);
7314         local_irq_enable();
7315 }
7316
7317 static void vmx_post_block(struct kvm_vcpu *vcpu)
7318 {
7319         if (kvm_x86_ops->set_hv_timer)
7320                 kvm_lapic_switch_to_hv_timer(vcpu);
7321
7322         pi_post_block(vcpu);
7323 }
7324
7325 /*
7326  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7327  *
7328  * @kvm: kvm
7329  * @host_irq: host irq of the interrupt
7330  * @guest_irq: gsi of the interrupt
7331  * @set: set or unset PI
7332  * returns 0 on success, < 0 on failure
7333  */
7334 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7335                               uint32_t guest_irq, bool set)
7336 {
7337         struct kvm_kernel_irq_routing_entry *e;
7338         struct kvm_irq_routing_table *irq_rt;
7339         struct kvm_lapic_irq irq;
7340         struct kvm_vcpu *vcpu;
7341         struct vcpu_data vcpu_info;
7342         int idx, ret = 0;
7343
7344         if (!kvm_arch_has_assigned_device(kvm) ||
7345                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7346                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7347                 return 0;
7348
7349         idx = srcu_read_lock(&kvm->irq_srcu);
7350         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7351         if (guest_irq >= irq_rt->nr_rt_entries ||
7352             hlist_empty(&irq_rt->map[guest_irq])) {
7353                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7354                              guest_irq, irq_rt->nr_rt_entries);
7355                 goto out;
7356         }
7357
7358         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7359                 if (e->type != KVM_IRQ_ROUTING_MSI)
7360                         continue;
7361                 /*
7362                  * VT-d PI cannot support posting multicast/broadcast
7363                  * interrupts to a vCPU, we still use interrupt remapping
7364                  * for these kind of interrupts.
7365                  *
7366                  * For lowest-priority interrupts, we only support
7367                  * those with single CPU as the destination, e.g. user
7368                  * configures the interrupts via /proc/irq or uses
7369                  * irqbalance to make the interrupts single-CPU.
7370                  *
7371                  * We will support full lowest-priority interrupt later.
7372                  *
7373                  * In addition, we can only inject generic interrupts using
7374                  * the PI mechanism, refuse to route others through it.
7375                  */
7376
7377                 kvm_set_msi_irq(kvm, e, &irq);
7378                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7379                     !kvm_irq_is_postable(&irq)) {
7380                         /*
7381                          * Make sure the IRTE is in remapped mode if
7382                          * we don't handle it in posted mode.
7383                          */
7384                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7385                         if (ret < 0) {
7386                                 printk(KERN_INFO
7387                                    "failed to back to remapped mode, irq: %u\n",
7388                                    host_irq);
7389                                 goto out;
7390                         }
7391
7392                         continue;
7393                 }
7394
7395                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7396                 vcpu_info.vector = irq.vector;
7397
7398                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7399                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7400
7401                 if (set)
7402                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7403                 else
7404                         ret = irq_set_vcpu_affinity(host_irq, NULL);
7405
7406                 if (ret < 0) {
7407                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
7408                                         __func__);
7409                         goto out;
7410                 }
7411         }
7412
7413         ret = 0;
7414 out:
7415         srcu_read_unlock(&kvm->irq_srcu, idx);
7416         return ret;
7417 }
7418
7419 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7420 {
7421         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7422                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7423                         FEATURE_CONTROL_LMCE;
7424         else
7425                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7426                         ~FEATURE_CONTROL_LMCE;
7427 }
7428
7429 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7430 {
7431         /* we need a nested vmexit to enter SMM, postpone if run is pending */
7432         if (to_vmx(vcpu)->nested.nested_run_pending)
7433                 return 0;
7434         return 1;
7435 }
7436
7437 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7438 {
7439         struct vcpu_vmx *vmx = to_vmx(vcpu);
7440
7441         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7442         if (vmx->nested.smm.guest_mode)
7443                 nested_vmx_vmexit(vcpu, -1, 0, 0);
7444
7445         vmx->nested.smm.vmxon = vmx->nested.vmxon;
7446         vmx->nested.vmxon = false;
7447         vmx_clear_hlt(vcpu);
7448         return 0;
7449 }
7450
7451 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7452 {
7453         struct vcpu_vmx *vmx = to_vmx(vcpu);
7454         int ret;
7455
7456         if (vmx->nested.smm.vmxon) {
7457                 vmx->nested.vmxon = true;
7458                 vmx->nested.smm.vmxon = false;
7459         }
7460
7461         if (vmx->nested.smm.guest_mode) {
7462                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7463                 if (ret)
7464                         return ret;
7465
7466                 vmx->nested.smm.guest_mode = false;
7467         }
7468         return 0;
7469 }
7470
7471 static int enable_smi_window(struct kvm_vcpu *vcpu)
7472 {
7473         return 0;
7474 }
7475
7476 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7477 {
7478         return false;
7479 }
7480
7481 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7482 {
7483         return to_vmx(vcpu)->nested.vmxon;
7484 }
7485
7486 static __init int hardware_setup(void)
7487 {
7488         unsigned long host_bndcfgs;
7489         struct desc_ptr dt;
7490         int r, i;
7491
7492         rdmsrl_safe(MSR_EFER, &host_efer);
7493
7494         store_idt(&dt);
7495         host_idt_base = dt.address;
7496
7497         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7498                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7499
7500         if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7501                 return -EIO;
7502
7503         if (boot_cpu_has(X86_FEATURE_NX))
7504                 kvm_enable_efer_bits(EFER_NX);
7505
7506         if (boot_cpu_has(X86_FEATURE_MPX)) {
7507                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7508                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7509         }
7510
7511         if (boot_cpu_has(X86_FEATURE_XSAVES))
7512                 rdmsrl(MSR_IA32_XSS, host_xss);
7513
7514         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7515             !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7516                 enable_vpid = 0;
7517
7518         if (!cpu_has_vmx_ept() ||
7519             !cpu_has_vmx_ept_4levels() ||
7520             !cpu_has_vmx_ept_mt_wb() ||
7521             !cpu_has_vmx_invept_global())
7522                 enable_ept = 0;
7523
7524         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7525                 enable_ept_ad_bits = 0;
7526
7527         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7528                 enable_unrestricted_guest = 0;
7529
7530         if (!cpu_has_vmx_flexpriority())
7531                 flexpriority_enabled = 0;
7532
7533         if (!cpu_has_virtual_nmis())
7534                 enable_vnmi = 0;
7535
7536         /*
7537          * set_apic_access_page_addr() is used to reload apic access
7538          * page upon invalidation.  No need to do anything if not
7539          * using the APIC_ACCESS_ADDR VMCS field.
7540          */
7541         if (!flexpriority_enabled)
7542                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7543
7544         if (!cpu_has_vmx_tpr_shadow())
7545                 kvm_x86_ops->update_cr8_intercept = NULL;
7546
7547         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7548                 kvm_disable_largepages();
7549
7550 #if IS_ENABLED(CONFIG_HYPERV)
7551         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7552             && enable_ept) {
7553                 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7554                 kvm_x86_ops->tlb_remote_flush_with_range =
7555                                 hv_remote_flush_tlb_with_range;
7556         }
7557 #endif
7558
7559         if (!cpu_has_vmx_ple()) {
7560                 ple_gap = 0;
7561                 ple_window = 0;
7562                 ple_window_grow = 0;
7563                 ple_window_max = 0;
7564                 ple_window_shrink = 0;
7565         }
7566
7567         if (!cpu_has_vmx_apicv()) {
7568                 enable_apicv = 0;
7569                 kvm_x86_ops->sync_pir_to_irr = NULL;
7570         }
7571
7572         if (cpu_has_vmx_tsc_scaling()) {
7573                 kvm_has_tsc_control = true;
7574                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7575                 kvm_tsc_scaling_ratio_frac_bits = 48;
7576         }
7577
7578         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7579
7580         if (enable_ept)
7581                 vmx_enable_tdp();
7582         else
7583                 kvm_disable_tdp();
7584
7585         /*
7586          * Only enable PML when hardware supports PML feature, and both EPT
7587          * and EPT A/D bit features are enabled -- PML depends on them to work.
7588          */
7589         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7590                 enable_pml = 0;
7591
7592         if (!enable_pml) {
7593                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7594                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7595                 kvm_x86_ops->flush_log_dirty = NULL;
7596                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7597         }
7598
7599         if (!cpu_has_vmx_preemption_timer())
7600                 enable_preemption_timer = false;
7601
7602         if (enable_preemption_timer) {
7603                 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7604                 u64 vmx_msr;
7605
7606                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7607                 cpu_preemption_timer_multi =
7608                         vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7609
7610                 if (tsc_khz)
7611                         use_timer_freq = (u64)tsc_khz * 1000;
7612                 use_timer_freq >>= cpu_preemption_timer_multi;
7613
7614                 /*
7615                  * KVM "disables" the preemption timer by setting it to its max
7616                  * value.  Don't use the timer if it might cause spurious exits
7617                  * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7618                  */
7619                 if (use_timer_freq > 0xffffffffu / 10)
7620                         enable_preemption_timer = false;
7621         }
7622
7623         if (!enable_preemption_timer) {
7624                 kvm_x86_ops->set_hv_timer = NULL;
7625                 kvm_x86_ops->cancel_hv_timer = NULL;
7626                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7627         }
7628
7629         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7630
7631         kvm_mce_cap_supported |= MCG_LMCE_P;
7632
7633         if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7634                 return -EINVAL;
7635         if (!enable_ept || !cpu_has_vmx_intel_pt())
7636                 pt_mode = PT_MODE_SYSTEM;
7637
7638         if (nested) {
7639                 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7640                                            vmx_capability.ept, enable_apicv);
7641
7642                 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7643                 if (r)
7644                         return r;
7645         }
7646
7647         r = alloc_kvm_area();
7648         if (r)
7649                 nested_vmx_hardware_unsetup();
7650         return r;
7651 }
7652
7653 static __exit void hardware_unsetup(void)
7654 {
7655         if (nested)
7656                 nested_vmx_hardware_unsetup();
7657
7658         free_kvm_area();
7659 }
7660
7661 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7662         .cpu_has_kvm_support = cpu_has_kvm_support,
7663         .disabled_by_bios = vmx_disabled_by_bios,
7664         .hardware_setup = hardware_setup,
7665         .hardware_unsetup = hardware_unsetup,
7666         .check_processor_compatibility = vmx_check_processor_compat,
7667         .hardware_enable = hardware_enable,
7668         .hardware_disable = hardware_disable,
7669         .cpu_has_accelerated_tpr = report_flexpriority,
7670         .has_emulated_msr = vmx_has_emulated_msr,
7671
7672         .vm_init = vmx_vm_init,
7673         .vm_alloc = vmx_vm_alloc,
7674         .vm_free = vmx_vm_free,
7675
7676         .vcpu_create = vmx_create_vcpu,
7677         .vcpu_free = vmx_free_vcpu,
7678         .vcpu_reset = vmx_vcpu_reset,
7679
7680         .prepare_guest_switch = vmx_prepare_switch_to_guest,
7681         .vcpu_load = vmx_vcpu_load,
7682         .vcpu_put = vmx_vcpu_put,
7683
7684         .update_bp_intercept = update_exception_bitmap,
7685         .get_msr_feature = vmx_get_msr_feature,
7686         .get_msr = vmx_get_msr,
7687         .set_msr = vmx_set_msr,
7688         .get_segment_base = vmx_get_segment_base,
7689         .get_segment = vmx_get_segment,
7690         .set_segment = vmx_set_segment,
7691         .get_cpl = vmx_get_cpl,
7692         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7693         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7694         .decache_cr3 = vmx_decache_cr3,
7695         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7696         .set_cr0 = vmx_set_cr0,
7697         .set_cr3 = vmx_set_cr3,
7698         .set_cr4 = vmx_set_cr4,
7699         .set_efer = vmx_set_efer,
7700         .get_idt = vmx_get_idt,
7701         .set_idt = vmx_set_idt,
7702         .get_gdt = vmx_get_gdt,
7703         .set_gdt = vmx_set_gdt,
7704         .get_dr6 = vmx_get_dr6,
7705         .set_dr6 = vmx_set_dr6,
7706         .set_dr7 = vmx_set_dr7,
7707         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7708         .cache_reg = vmx_cache_reg,
7709         .get_rflags = vmx_get_rflags,
7710         .set_rflags = vmx_set_rflags,
7711
7712         .tlb_flush = vmx_flush_tlb,
7713         .tlb_flush_gva = vmx_flush_tlb_gva,
7714
7715         .run = vmx_vcpu_run,
7716         .handle_exit = vmx_handle_exit,
7717         .skip_emulated_instruction = skip_emulated_instruction,
7718         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7719         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7720         .patch_hypercall = vmx_patch_hypercall,
7721         .set_irq = vmx_inject_irq,
7722         .set_nmi = vmx_inject_nmi,
7723         .queue_exception = vmx_queue_exception,
7724         .cancel_injection = vmx_cancel_injection,
7725         .interrupt_allowed = vmx_interrupt_allowed,
7726         .nmi_allowed = vmx_nmi_allowed,
7727         .get_nmi_mask = vmx_get_nmi_mask,
7728         .set_nmi_mask = vmx_set_nmi_mask,
7729         .enable_nmi_window = enable_nmi_window,
7730         .enable_irq_window = enable_irq_window,
7731         .update_cr8_intercept = update_cr8_intercept,
7732         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7733         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7734         .get_enable_apicv = vmx_get_enable_apicv,
7735         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7736         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7737         .apicv_post_state_restore = vmx_apicv_post_state_restore,
7738         .hwapic_irr_update = vmx_hwapic_irr_update,
7739         .hwapic_isr_update = vmx_hwapic_isr_update,
7740         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7741         .sync_pir_to_irr = vmx_sync_pir_to_irr,
7742         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7743         .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7744
7745         .set_tss_addr = vmx_set_tss_addr,
7746         .set_identity_map_addr = vmx_set_identity_map_addr,
7747         .get_tdp_level = get_ept_level,
7748         .get_mt_mask = vmx_get_mt_mask,
7749
7750         .get_exit_info = vmx_get_exit_info,
7751
7752         .get_lpage_level = vmx_get_lpage_level,
7753
7754         .cpuid_update = vmx_cpuid_update,
7755
7756         .rdtscp_supported = vmx_rdtscp_supported,
7757         .invpcid_supported = vmx_invpcid_supported,
7758
7759         .set_supported_cpuid = vmx_set_supported_cpuid,
7760
7761         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7762
7763         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7764         .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7765
7766         .set_tdp_cr3 = vmx_set_cr3,
7767
7768         .check_intercept = vmx_check_intercept,
7769         .handle_exit_irqoff = vmx_handle_exit_irqoff,
7770         .mpx_supported = vmx_mpx_supported,
7771         .xsaves_supported = vmx_xsaves_supported,
7772         .umip_emulated = vmx_umip_emulated,
7773         .pt_supported = vmx_pt_supported,
7774
7775         .request_immediate_exit = vmx_request_immediate_exit,
7776
7777         .sched_in = vmx_sched_in,
7778
7779         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7780         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7781         .flush_log_dirty = vmx_flush_log_dirty,
7782         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7783         .write_log_dirty = vmx_write_pml_buffer,
7784
7785         .pre_block = vmx_pre_block,
7786         .post_block = vmx_post_block,
7787
7788         .pmu_ops = &intel_pmu_ops,
7789
7790         .update_pi_irte = vmx_update_pi_irte,
7791
7792 #ifdef CONFIG_X86_64
7793         .set_hv_timer = vmx_set_hv_timer,
7794         .cancel_hv_timer = vmx_cancel_hv_timer,
7795 #endif
7796
7797         .setup_mce = vmx_setup_mce,
7798
7799         .smi_allowed = vmx_smi_allowed,
7800         .pre_enter_smm = vmx_pre_enter_smm,
7801         .pre_leave_smm = vmx_pre_leave_smm,
7802         .enable_smi_window = enable_smi_window,
7803
7804         .check_nested_events = NULL,
7805         .get_nested_state = NULL,
7806         .set_nested_state = NULL,
7807         .get_vmcs12_pages = NULL,
7808         .nested_enable_evmcs = NULL,
7809         .nested_get_evmcs_version = NULL,
7810         .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7811         .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7812 };
7813
7814 static void vmx_cleanup_l1d_flush(void)
7815 {
7816         if (vmx_l1d_flush_pages) {
7817                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7818                 vmx_l1d_flush_pages = NULL;
7819         }
7820         /* Restore state so sysfs ignores VMX */
7821         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7822 }
7823
7824 static void vmx_exit(void)
7825 {
7826 #ifdef CONFIG_KEXEC_CORE
7827         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7828         synchronize_rcu();
7829 #endif
7830
7831         kvm_exit();
7832
7833 #if IS_ENABLED(CONFIG_HYPERV)
7834         if (static_branch_unlikely(&enable_evmcs)) {
7835                 int cpu;
7836                 struct hv_vp_assist_page *vp_ap;
7837                 /*
7838                  * Reset everything to support using non-enlightened VMCS
7839                  * access later (e.g. when we reload the module with
7840                  * enlightened_vmcs=0)
7841                  */
7842                 for_each_online_cpu(cpu) {
7843                         vp_ap = hv_get_vp_assist_page(cpu);
7844
7845                         if (!vp_ap)
7846                                 continue;
7847
7848                         vp_ap->nested_control.features.directhypercall = 0;
7849                         vp_ap->current_nested_vmcs = 0;
7850                         vp_ap->enlighten_vmentry = 0;
7851                 }
7852
7853                 static_branch_disable(&enable_evmcs);
7854         }
7855 #endif
7856         vmx_cleanup_l1d_flush();
7857 }
7858 module_exit(vmx_exit);
7859
7860 static int __init vmx_init(void)
7861 {
7862         int r;
7863
7864 #if IS_ENABLED(CONFIG_HYPERV)
7865         /*
7866          * Enlightened VMCS usage should be recommended and the host needs
7867          * to support eVMCS v1 or above. We can also disable eVMCS support
7868          * with module parameter.
7869          */
7870         if (enlightened_vmcs &&
7871             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7872             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7873             KVM_EVMCS_VERSION) {
7874                 int cpu;
7875
7876                 /* Check that we have assist pages on all online CPUs */
7877                 for_each_online_cpu(cpu) {
7878                         if (!hv_get_vp_assist_page(cpu)) {
7879                                 enlightened_vmcs = false;
7880                                 break;
7881                         }
7882                 }
7883
7884                 if (enlightened_vmcs) {
7885                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7886                         static_branch_enable(&enable_evmcs);
7887                 }
7888
7889                 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7890                         vmx_x86_ops.enable_direct_tlbflush
7891                                 = hv_enable_direct_tlbflush;
7892
7893         } else {
7894                 enlightened_vmcs = false;
7895         }
7896 #endif
7897
7898         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7899                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7900         if (r)
7901                 return r;
7902
7903         /*
7904          * Must be called after kvm_init() so enable_ept is properly set
7905          * up. Hand the parameter mitigation value in which was stored in
7906          * the pre module init parser. If no parameter was given, it will
7907          * contain 'auto' which will be turned into the default 'cond'
7908          * mitigation mode.
7909          */
7910         if (boot_cpu_has(X86_BUG_L1TF)) {
7911                 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7912                 if (r) {
7913                         vmx_exit();
7914                         return r;
7915                 }
7916         }
7917
7918 #ifdef CONFIG_KEXEC_CORE
7919         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7920                            crash_vmclear_local_loaded_vmcss);
7921 #endif
7922         vmx_check_vmcs12_offsets();
7923
7924         return 0;
7925 }
7926 module_init(vmx_init);