1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 static u64 __read_mostly host_xss;
111 bool __read_mostly enable_pml = 1;
112 module_param_named(pml, enable_pml, bool, S_IRUGO);
114 static bool __read_mostly dump_invalid_vmcs = 0;
115 module_param(dump_invalid_vmcs, bool, 0644);
117 #define MSR_BITMAP_MODE_X2APIC 1
118 #define MSR_BITMAP_MODE_X2APIC_APICV 2
120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123 static int __read_mostly cpu_preemption_timer_multi;
124 static bool __read_mostly enable_preemption_timer = 1;
126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131 #define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
134 #define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
227 /* If set to auto use the default l1tf mitigation method */
228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
229 switch (l1tf_mitigation) {
230 case L1TF_MITIGATION_OFF:
231 l1tf = VMENTER_L1D_FLUSH_NEVER;
233 case L1TF_MITIGATION_FLUSH_NOWARN:
234 case L1TF_MITIGATION_FLUSH:
235 case L1TF_MITIGATION_FLUSH_NOSMT:
236 l1tf = VMENTER_L1D_FLUSH_COND;
238 case L1TF_MITIGATION_FULL:
239 case L1TF_MITIGATION_FULL_FORCE:
240 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
244 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
250 * This allocation for vmx_l1d_flush_pages is not tied to a VM
251 * lifetime and so should not be charged to a memcg.
253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
256 vmx_l1d_flush_pages = page_address(page);
259 * Initialize each page with a different pattern in
260 * order to protect against KSM in the nested
261 * virtualization case.
263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
269 l1tf_vmx_mitigation = l1tf;
271 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
272 static_branch_enable(&vmx_l1d_should_flush);
274 static_branch_disable(&vmx_l1d_should_flush);
276 if (l1tf == VMENTER_L1D_FLUSH_COND)
277 static_branch_enable(&vmx_l1d_flush_cond);
279 static_branch_disable(&vmx_l1d_flush_cond);
283 static int vmentry_l1d_flush_parse(const char *s)
288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
289 if (vmentry_l1d_param[i].for_parse &&
290 sysfs_streq(s, vmentry_l1d_param[i].option))
297 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301 l1tf = vmentry_l1d_flush_parse(s);
305 if (!boot_cpu_has(X86_BUG_L1TF))
309 * Has vmx_init() run already? If not then this is the pre init
310 * parameter parsing. In that case just store the value and let
311 * vmx_init() do the proper setup after enable_ept has been
314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
315 vmentry_l1d_flush_param = l1tf;
319 mutex_lock(&vmx_l1d_flush_mutex);
320 ret = vmx_setup_l1d_flush(l1tf);
321 mutex_unlock(&vmx_l1d_flush_mutex);
325 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
328 return sprintf(s, "???\n");
330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
333 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
334 .set = vmentry_l1d_flush_set,
335 .get = vmentry_l1d_flush_get,
337 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
339 static bool guest_state_valid(struct kvm_vcpu *vcpu);
340 static u32 vmx_segment_access_rights(struct kvm_segment *var);
341 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
344 void vmx_vmexit(void);
346 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
347 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
352 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
356 * can find which vCPU should be waken up.
358 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
359 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
361 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
362 static DEFINE_SPINLOCK(vmx_vpid_lock);
364 struct vmcs_config vmcs_config;
365 struct vmx_capability vmx_capability;
367 #define VMX_SEGMENT_FIELD(seg) \
368 [VCPU_SREG_##seg] = { \
369 .selector = GUEST_##seg##_SELECTOR, \
370 .base = GUEST_##seg##_BASE, \
371 .limit = GUEST_##seg##_LIMIT, \
372 .ar_bytes = GUEST_##seg##_AR_BYTES, \
375 static const struct kvm_vmx_segment_field {
380 } kvm_vmx_segment_fields[] = {
381 VMX_SEGMENT_FIELD(CS),
382 VMX_SEGMENT_FIELD(DS),
383 VMX_SEGMENT_FIELD(ES),
384 VMX_SEGMENT_FIELD(FS),
385 VMX_SEGMENT_FIELD(GS),
386 VMX_SEGMENT_FIELD(SS),
387 VMX_SEGMENT_FIELD(TR),
388 VMX_SEGMENT_FIELD(LDTR),
392 static unsigned long host_idt_base;
395 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
396 * will emulate SYSCALL in legacy mode if the vendor string in guest
397 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
398 * support this emulation, IA32_STAR must always be included in
399 * vmx_msr_index[], even in i386 builds.
401 const u32 vmx_msr_index[] = {
403 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
405 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
408 #if IS_ENABLED(CONFIG_HYPERV)
409 static bool __read_mostly enlightened_vmcs = true;
410 module_param(enlightened_vmcs, bool, 0444);
412 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
413 static void check_ept_pointer_match(struct kvm *kvm)
415 struct kvm_vcpu *vcpu;
416 u64 tmp_eptp = INVALID_PAGE;
419 kvm_for_each_vcpu(i, vcpu, kvm) {
420 if (!VALID_PAGE(tmp_eptp)) {
421 tmp_eptp = to_vmx(vcpu)->ept_pointer;
422 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
423 to_kvm_vmx(kvm)->ept_pointers_match
424 = EPT_POINTERS_MISMATCH;
429 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
432 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
435 struct kvm_tlb_range *range = data;
437 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
441 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
442 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
444 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
447 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
448 * of the base of EPT PML4 table, strip off EPT configuration
452 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
453 kvm_fill_hv_flush_list_func, (void *)range);
455 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
458 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
459 struct kvm_tlb_range *range)
461 struct kvm_vcpu *vcpu;
464 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
466 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
467 check_ept_pointer_match(kvm);
469 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
470 kvm_for_each_vcpu(i, vcpu, kvm) {
471 /* If ept_pointer is invalid pointer, bypass flush request. */
472 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
473 ret |= __hv_remote_flush_tlb_with_range(
477 ret = __hv_remote_flush_tlb_with_range(kvm,
478 kvm_get_vcpu(kvm, 0), range);
481 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
484 static int hv_remote_flush_tlb(struct kvm *kvm)
486 return hv_remote_flush_tlb_with_range(kvm, NULL);
489 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
491 struct hv_enlightened_vmcs *evmcs;
492 struct hv_partition_assist_pg **p_hv_pa_pg =
493 &vcpu->kvm->arch.hyperv.hv_pa_pg;
495 * Synthetic VM-Exit is not enabled in current code and so All
496 * evmcs in singe VM shares same assist page.
499 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
502 pr_debug("KVM: Hyper-V: allocated PA_PG for %llx\n",
506 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
508 evmcs->partition_assist_page =
510 evmcs->hv_vm_id = (u64)vcpu->kvm;
511 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
513 pr_debug("KVM: Hyper-V: enabled DIRECT flush for %llx\n",
518 #endif /* IS_ENABLED(CONFIG_HYPERV) */
521 * Comment's format: document - errata name - stepping - processor name.
523 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
525 static u32 vmx_preemption_cpu_tfms[] = {
526 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
528 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
529 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
530 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
532 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
534 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
535 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
537 * 320767.pdf - AAP86 - B1 -
538 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
541 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
543 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
545 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
547 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
548 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
549 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
551 /* Xeon E3-1220 V2 */
555 static inline bool cpu_has_broken_vmx_preemption_timer(void)
557 u32 eax = cpuid_eax(0x00000001), i;
559 /* Clear the reserved bits */
560 eax &= ~(0x3U << 14 | 0xfU << 28);
561 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
562 if (eax == vmx_preemption_cpu_tfms[i])
568 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
570 return flexpriority_enabled && lapic_in_kernel(vcpu);
573 static inline bool report_flexpriority(void)
575 return flexpriority_enabled;
578 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
582 for (i = 0; i < vmx->nmsrs; ++i)
583 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
588 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
592 i = __find_msr_index(vmx, msr);
594 return &vmx->guest_msrs[i];
598 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
600 vmcs_clear(loaded_vmcs->vmcs);
601 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
602 vmcs_clear(loaded_vmcs->shadow_vmcs);
603 loaded_vmcs->cpu = -1;
604 loaded_vmcs->launched = 0;
607 #ifdef CONFIG_KEXEC_CORE
609 * This bitmap is used to indicate whether the vmclear
610 * operation is enabled on all cpus. All disabled by
613 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
615 static inline void crash_enable_local_vmclear(int cpu)
617 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
620 static inline void crash_disable_local_vmclear(int cpu)
622 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
625 static inline int crash_local_vmclear_enabled(int cpu)
627 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
630 static void crash_vmclear_local_loaded_vmcss(void)
632 int cpu = raw_smp_processor_id();
633 struct loaded_vmcs *v;
635 if (!crash_local_vmclear_enabled(cpu))
638 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
639 loaded_vmcss_on_cpu_link)
643 static inline void crash_enable_local_vmclear(int cpu) { }
644 static inline void crash_disable_local_vmclear(int cpu) { }
645 #endif /* CONFIG_KEXEC_CORE */
647 static void __loaded_vmcs_clear(void *arg)
649 struct loaded_vmcs *loaded_vmcs = arg;
650 int cpu = raw_smp_processor_id();
652 if (loaded_vmcs->cpu != cpu)
653 return; /* vcpu migration can race with cpu offline */
654 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
655 per_cpu(current_vmcs, cpu) = NULL;
656 crash_disable_local_vmclear(cpu);
657 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
660 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
661 * is before setting loaded_vmcs->vcpu to -1 which is done in
662 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
663 * then adds the vmcs into percpu list before it is deleted.
667 loaded_vmcs_init(loaded_vmcs);
668 crash_enable_local_vmclear(cpu);
671 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
673 int cpu = loaded_vmcs->cpu;
676 smp_call_function_single(cpu,
677 __loaded_vmcs_clear, loaded_vmcs, 1);
680 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
684 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
686 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
687 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
688 vmx->segment_cache.bitmask = 0;
690 ret = vmx->segment_cache.bitmask & mask;
691 vmx->segment_cache.bitmask |= mask;
695 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
697 u16 *p = &vmx->segment_cache.seg[seg].selector;
699 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
700 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
704 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
706 ulong *p = &vmx->segment_cache.seg[seg].base;
708 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
709 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
713 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
715 u32 *p = &vmx->segment_cache.seg[seg].limit;
717 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
718 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
722 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
724 u32 *p = &vmx->segment_cache.seg[seg].ar;
726 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
727 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
731 void update_exception_bitmap(struct kvm_vcpu *vcpu)
735 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
736 (1u << DB_VECTOR) | (1u << AC_VECTOR);
738 * Guest access to VMware backdoor ports could legitimately
739 * trigger #GP because of TSS I/O permission bitmap.
740 * We intercept those #GP and allow access to them anyway
743 if (enable_vmware_backdoor)
744 eb |= (1u << GP_VECTOR);
745 if ((vcpu->guest_debug &
746 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
747 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
748 eb |= 1u << BP_VECTOR;
749 if (to_vmx(vcpu)->rmode.vm86_active)
752 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
754 /* When we are running a nested L2 guest and L1 specified for it a
755 * certain exception bitmap, we must trap the same exceptions and pass
756 * them to L1. When running L2, we will only handle the exceptions
757 * specified above if L1 did not want them.
759 if (is_guest_mode(vcpu))
760 eb |= get_vmcs12(vcpu)->exception_bitmap;
762 vmcs_write32(EXCEPTION_BITMAP, eb);
766 * Check if MSR is intercepted for currently loaded MSR bitmap.
768 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
770 unsigned long *msr_bitmap;
771 int f = sizeof(unsigned long);
773 if (!cpu_has_vmx_msr_bitmap())
776 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
779 return !!test_bit(msr, msr_bitmap + 0x800 / f);
780 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
782 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
788 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
789 unsigned long entry, unsigned long exit)
791 vm_entry_controls_clearbit(vmx, entry);
792 vm_exit_controls_clearbit(vmx, exit);
795 static int find_msr(struct vmx_msrs *m, unsigned int msr)
799 for (i = 0; i < m->nr; ++i) {
800 if (m->val[i].index == msr)
806 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
809 struct msr_autoload *m = &vmx->msr_autoload;
813 if (cpu_has_load_ia32_efer()) {
814 clear_atomic_switch_msr_special(vmx,
815 VM_ENTRY_LOAD_IA32_EFER,
816 VM_EXIT_LOAD_IA32_EFER);
820 case MSR_CORE_PERF_GLOBAL_CTRL:
821 if (cpu_has_load_perf_global_ctrl()) {
822 clear_atomic_switch_msr_special(vmx,
823 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
824 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
829 i = find_msr(&m->guest, msr);
833 m->guest.val[i] = m->guest.val[m->guest.nr];
834 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
837 i = find_msr(&m->host, msr);
842 m->host.val[i] = m->host.val[m->host.nr];
843 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
846 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
847 unsigned long entry, unsigned long exit,
848 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
849 u64 guest_val, u64 host_val)
851 vmcs_write64(guest_val_vmcs, guest_val);
852 if (host_val_vmcs != HOST_IA32_EFER)
853 vmcs_write64(host_val_vmcs, host_val);
854 vm_entry_controls_setbit(vmx, entry);
855 vm_exit_controls_setbit(vmx, exit);
858 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
859 u64 guest_val, u64 host_val, bool entry_only)
862 struct msr_autoload *m = &vmx->msr_autoload;
866 if (cpu_has_load_ia32_efer()) {
867 add_atomic_switch_msr_special(vmx,
868 VM_ENTRY_LOAD_IA32_EFER,
869 VM_EXIT_LOAD_IA32_EFER,
872 guest_val, host_val);
876 case MSR_CORE_PERF_GLOBAL_CTRL:
877 if (cpu_has_load_perf_global_ctrl()) {
878 add_atomic_switch_msr_special(vmx,
879 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
880 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
881 GUEST_IA32_PERF_GLOBAL_CTRL,
882 HOST_IA32_PERF_GLOBAL_CTRL,
883 guest_val, host_val);
887 case MSR_IA32_PEBS_ENABLE:
888 /* PEBS needs a quiescent period after being disabled (to write
889 * a record). Disabling PEBS through VMX MSR swapping doesn't
890 * provide that period, so a CPU could write host's record into
893 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
896 i = find_msr(&m->guest, msr);
898 j = find_msr(&m->host, msr);
900 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
901 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
902 printk_once(KERN_WARNING "Not enough msr switch entries. "
903 "Can't add msr %x\n", msr);
908 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
910 m->guest.val[i].index = msr;
911 m->guest.val[i].value = guest_val;
918 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
920 m->host.val[j].index = msr;
921 m->host.val[j].value = host_val;
924 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
926 u64 guest_efer = vmx->vcpu.arch.efer;
931 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
932 * host CPUID is more efficient than testing guest CPUID
933 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
935 if (boot_cpu_has(X86_FEATURE_SMEP))
936 guest_efer |= EFER_NX;
937 else if (!(guest_efer & EFER_NX))
938 ignore_bits |= EFER_NX;
942 * LMA and LME handled by hardware; SCE meaningless outside long mode.
944 ignore_bits |= EFER_SCE;
946 ignore_bits |= EFER_LMA | EFER_LME;
947 /* SCE is meaningful only in long mode on Intel */
948 if (guest_efer & EFER_LMA)
949 ignore_bits &= ~(u64)EFER_SCE;
953 * On EPT, we can't emulate NX, so we must switch EFER atomically.
954 * On CPUs that support "load IA32_EFER", always switch EFER
955 * atomically, since it's faster than switching it manually.
957 if (cpu_has_load_ia32_efer() ||
958 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
959 if (!(guest_efer & EFER_LMA))
960 guest_efer &= ~EFER_LME;
961 if (guest_efer != host_efer)
962 add_atomic_switch_msr(vmx, MSR_EFER,
963 guest_efer, host_efer, false);
965 clear_atomic_switch_msr(vmx, MSR_EFER);
968 clear_atomic_switch_msr(vmx, MSR_EFER);
970 guest_efer &= ~ignore_bits;
971 guest_efer |= host_efer & ignore_bits;
973 vmx->guest_msrs[efer_offset].data = guest_efer;
974 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
982 * On 32-bit kernels, VM exits still load the FS and GS bases from the
983 * VMCS rather than the segment table. KVM uses this helper to figure
984 * out the current bases to poke them into the VMCS before entry.
986 static unsigned long segment_base(u16 selector)
988 struct desc_struct *table;
991 if (!(selector & ~SEGMENT_RPL_MASK))
994 table = get_current_gdt_ro();
996 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
997 u16 ldt_selector = kvm_read_ldt();
999 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1002 table = (struct desc_struct *)segment_base(ldt_selector);
1004 v = get_desc_base(&table[selector >> 3]);
1009 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1013 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1014 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1015 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1016 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1017 for (i = 0; i < addr_range; i++) {
1018 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1019 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1023 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1027 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1028 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1029 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1030 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1031 for (i = 0; i < addr_range; i++) {
1032 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1033 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1037 static void pt_guest_enter(struct vcpu_vmx *vmx)
1039 if (pt_mode == PT_MODE_SYSTEM)
1043 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1044 * Save host state before VM entry.
1046 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1047 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1048 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1049 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1050 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1054 static void pt_guest_exit(struct vcpu_vmx *vmx)
1056 if (pt_mode == PT_MODE_SYSTEM)
1059 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1060 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1061 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1064 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1065 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1068 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1069 unsigned long fs_base, unsigned long gs_base)
1071 if (unlikely(fs_sel != host->fs_sel)) {
1073 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1075 vmcs_write16(HOST_FS_SELECTOR, 0);
1076 host->fs_sel = fs_sel;
1078 if (unlikely(gs_sel != host->gs_sel)) {
1080 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1082 vmcs_write16(HOST_GS_SELECTOR, 0);
1083 host->gs_sel = gs_sel;
1085 if (unlikely(fs_base != host->fs_base)) {
1086 vmcs_writel(HOST_FS_BASE, fs_base);
1087 host->fs_base = fs_base;
1089 if (unlikely(gs_base != host->gs_base)) {
1090 vmcs_writel(HOST_GS_BASE, gs_base);
1091 host->gs_base = gs_base;
1095 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1097 struct vcpu_vmx *vmx = to_vmx(vcpu);
1098 struct vmcs_host_state *host_state;
1099 #ifdef CONFIG_X86_64
1100 int cpu = raw_smp_processor_id();
1102 unsigned long fs_base, gs_base;
1106 vmx->req_immediate_exit = false;
1109 * Note that guest MSRs to be saved/restored can also be changed
1110 * when guest state is loaded. This happens when guest transitions
1111 * to/from long-mode by setting MSR_EFER.LMA.
1113 if (!vmx->guest_msrs_ready) {
1114 vmx->guest_msrs_ready = true;
1115 for (i = 0; i < vmx->save_nmsrs; ++i)
1116 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1117 vmx->guest_msrs[i].data,
1118 vmx->guest_msrs[i].mask);
1121 if (vmx->guest_state_loaded)
1124 host_state = &vmx->loaded_vmcs->host_state;
1127 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1128 * allow segment selectors with cpl > 0 or ti == 1.
1130 host_state->ldt_sel = kvm_read_ldt();
1132 #ifdef CONFIG_X86_64
1133 savesegment(ds, host_state->ds_sel);
1134 savesegment(es, host_state->es_sel);
1136 gs_base = cpu_kernelmode_gs_base(cpu);
1137 if (likely(is_64bit_mm(current->mm))) {
1138 save_fsgs_for_kvm();
1139 fs_sel = current->thread.fsindex;
1140 gs_sel = current->thread.gsindex;
1141 fs_base = current->thread.fsbase;
1142 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1144 savesegment(fs, fs_sel);
1145 savesegment(gs, gs_sel);
1146 fs_base = read_msr(MSR_FS_BASE);
1147 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1150 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1152 savesegment(fs, fs_sel);
1153 savesegment(gs, gs_sel);
1154 fs_base = segment_base(fs_sel);
1155 gs_base = segment_base(gs_sel);
1158 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1159 vmx->guest_state_loaded = true;
1162 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1164 struct vmcs_host_state *host_state;
1166 if (!vmx->guest_state_loaded)
1169 host_state = &vmx->loaded_vmcs->host_state;
1171 ++vmx->vcpu.stat.host_state_reload;
1173 #ifdef CONFIG_X86_64
1174 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1176 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1177 kvm_load_ldt(host_state->ldt_sel);
1178 #ifdef CONFIG_X86_64
1179 load_gs_index(host_state->gs_sel);
1181 loadsegment(gs, host_state->gs_sel);
1184 if (host_state->fs_sel & 7)
1185 loadsegment(fs, host_state->fs_sel);
1186 #ifdef CONFIG_X86_64
1187 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1188 loadsegment(ds, host_state->ds_sel);
1189 loadsegment(es, host_state->es_sel);
1192 invalidate_tss_limit();
1193 #ifdef CONFIG_X86_64
1194 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1196 load_fixmap_gdt(raw_smp_processor_id());
1197 vmx->guest_state_loaded = false;
1198 vmx->guest_msrs_ready = false;
1201 #ifdef CONFIG_X86_64
1202 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1205 if (vmx->guest_state_loaded)
1206 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1208 return vmx->msr_guest_kernel_gs_base;
1211 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1214 if (vmx->guest_state_loaded)
1215 wrmsrl(MSR_KERNEL_GS_BASE, data);
1217 vmx->msr_guest_kernel_gs_base = data;
1221 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1223 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1224 struct pi_desc old, new;
1228 * In case of hot-plug or hot-unplug, we may have to undo
1229 * vmx_vcpu_pi_put even if there is no assigned device. And we
1230 * always keep PI.NDST up to date for simplicity: it makes the
1231 * code easier, and CPU migration is not a fast path.
1233 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1236 /* The full case. */
1238 old.control = new.control = pi_desc->control;
1240 dest = cpu_physical_id(cpu);
1242 if (x2apic_enabled())
1245 new.ndst = (dest << 8) & 0xFF00;
1248 } while (cmpxchg64(&pi_desc->control, old.control,
1249 new.control) != old.control);
1252 * Clear SN before reading the bitmap. The VT-d firmware
1253 * writes the bitmap and reads SN atomically (5.2.3 in the
1254 * spec), so it doesn't really have a memory barrier that
1255 * pairs with this, but we cannot do that and we need one.
1257 smp_mb__after_atomic();
1259 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1263 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1265 struct vcpu_vmx *vmx = to_vmx(vcpu);
1266 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1268 if (!already_loaded) {
1269 loaded_vmcs_clear(vmx->loaded_vmcs);
1270 local_irq_disable();
1271 crash_disable_local_vmclear(cpu);
1274 * Read loaded_vmcs->cpu should be before fetching
1275 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1276 * See the comments in __loaded_vmcs_clear().
1280 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1281 &per_cpu(loaded_vmcss_on_cpu, cpu));
1282 crash_enable_local_vmclear(cpu);
1286 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1287 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1288 vmcs_load(vmx->loaded_vmcs->vmcs);
1289 indirect_branch_prediction_barrier();
1292 if (!already_loaded) {
1293 void *gdt = get_current_gdt_ro();
1294 unsigned long sysenter_esp;
1296 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1299 * Linux uses per-cpu TSS and GDT, so set these when switching
1300 * processors. See 22.2.4.
1302 vmcs_writel(HOST_TR_BASE,
1303 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1304 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1307 * VM exits change the host TR limit to 0x67 after a VM
1308 * exit. This is okay, since 0x67 covers everything except
1309 * the IO bitmap and have have code to handle the IO bitmap
1310 * being lost after a VM exit.
1312 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1314 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1315 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1317 vmx->loaded_vmcs->cpu = cpu;
1320 /* Setup TSC multiplier */
1321 if (kvm_has_tsc_control &&
1322 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1323 decache_tsc_multiplier(vmx);
1327 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1328 * vcpu mutex is already taken.
1330 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1332 struct vcpu_vmx *vmx = to_vmx(vcpu);
1334 vmx_vcpu_load_vmcs(vcpu, cpu);
1336 vmx_vcpu_pi_load(vcpu, cpu);
1338 vmx->host_pkru = read_pkru();
1339 vmx->host_debugctlmsr = get_debugctlmsr();
1342 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1344 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1346 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1347 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1348 !kvm_vcpu_apicv_active(vcpu))
1351 /* Set SN when the vCPU is preempted */
1352 if (vcpu->preempted)
1356 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1358 vmx_vcpu_pi_put(vcpu);
1360 vmx_prepare_switch_to_host(to_vmx(vcpu));
1363 static bool emulation_required(struct kvm_vcpu *vcpu)
1365 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1368 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1370 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1372 unsigned long rflags, save_rflags;
1374 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1375 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1376 rflags = vmcs_readl(GUEST_RFLAGS);
1377 if (to_vmx(vcpu)->rmode.vm86_active) {
1378 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1379 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1380 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1382 to_vmx(vcpu)->rflags = rflags;
1384 return to_vmx(vcpu)->rflags;
1387 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1389 unsigned long old_rflags = vmx_get_rflags(vcpu);
1391 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1392 to_vmx(vcpu)->rflags = rflags;
1393 if (to_vmx(vcpu)->rmode.vm86_active) {
1394 to_vmx(vcpu)->rmode.save_rflags = rflags;
1395 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1397 vmcs_writel(GUEST_RFLAGS, rflags);
1399 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1400 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1403 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1405 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1408 if (interruptibility & GUEST_INTR_STATE_STI)
1409 ret |= KVM_X86_SHADOW_INT_STI;
1410 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1411 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1416 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1418 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1419 u32 interruptibility = interruptibility_old;
1421 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1423 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1424 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1425 else if (mask & KVM_X86_SHADOW_INT_STI)
1426 interruptibility |= GUEST_INTR_STATE_STI;
1428 if ((interruptibility != interruptibility_old))
1429 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1432 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1434 struct vcpu_vmx *vmx = to_vmx(vcpu);
1435 unsigned long value;
1438 * Any MSR write that attempts to change bits marked reserved will
1441 if (data & vmx->pt_desc.ctl_bitmask)
1445 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1446 * result in a #GP unless the same write also clears TraceEn.
1448 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1449 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1453 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1454 * and FabricEn would cause #GP, if
1455 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1457 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1458 !(data & RTIT_CTL_FABRIC_EN) &&
1459 !intel_pt_validate_cap(vmx->pt_desc.caps,
1460 PT_CAP_single_range_output))
1464 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1465 * utilize encodings marked reserved will casue a #GP fault.
1467 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1468 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1469 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1470 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1472 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1473 PT_CAP_cycle_thresholds);
1474 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1475 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1476 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1478 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1479 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1480 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1481 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1485 * If ADDRx_CFG is reserved or the encodings is >2 will
1486 * cause a #GP fault.
1488 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1489 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1491 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1492 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1494 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1495 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1497 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1498 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1505 * Returns an int to be compatible with SVM implementation (which can fail).
1506 * Do not use directly, use skip_emulated_instruction() instead.
1508 static int __skip_emulated_instruction(struct kvm_vcpu *vcpu)
1512 rip = kvm_rip_read(vcpu);
1513 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1514 kvm_rip_write(vcpu, rip);
1516 /* skipping an emulated instruction also counts */
1517 vmx_set_interrupt_shadow(vcpu, 0);
1519 return EMULATE_DONE;
1522 static inline void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1524 (void)__skip_emulated_instruction(vcpu);
1527 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1530 * Ensure that we clear the HLT state in the VMCS. We don't need to
1531 * explicitly skip the instruction because if the HLT state is set,
1532 * then the instruction is already executing and RIP has already been
1535 if (kvm_hlt_in_guest(vcpu->kvm) &&
1536 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1537 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1540 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1542 struct vcpu_vmx *vmx = to_vmx(vcpu);
1543 unsigned nr = vcpu->arch.exception.nr;
1544 bool has_error_code = vcpu->arch.exception.has_error_code;
1545 u32 error_code = vcpu->arch.exception.error_code;
1546 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1548 kvm_deliver_exception_payload(vcpu);
1550 if (has_error_code) {
1551 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1552 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1555 if (vmx->rmode.vm86_active) {
1557 if (kvm_exception_is_soft(nr))
1558 inc_eip = vcpu->arch.event_exit_inst_len;
1559 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1563 WARN_ON_ONCE(vmx->emulation_required);
1565 if (kvm_exception_is_soft(nr)) {
1566 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1567 vmx->vcpu.arch.event_exit_inst_len);
1568 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1570 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1572 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1574 vmx_clear_hlt(vcpu);
1577 static bool vmx_rdtscp_supported(void)
1579 return cpu_has_vmx_rdtscp();
1582 static bool vmx_invpcid_supported(void)
1584 return cpu_has_vmx_invpcid();
1588 * Swap MSR entry in host/guest MSR entry array.
1590 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1592 struct shared_msr_entry tmp;
1594 tmp = vmx->guest_msrs[to];
1595 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1596 vmx->guest_msrs[from] = tmp;
1600 * Set up the vmcs to automatically save and restore system
1601 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1602 * mode, as fiddling with msrs is very expensive.
1604 static void setup_msrs(struct vcpu_vmx *vmx)
1606 int save_nmsrs, index;
1609 #ifdef CONFIG_X86_64
1611 * The SYSCALL MSRs are only needed on long mode guests, and only
1612 * when EFER.SCE is set.
1614 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1615 index = __find_msr_index(vmx, MSR_STAR);
1617 move_msr_up(vmx, index, save_nmsrs++);
1618 index = __find_msr_index(vmx, MSR_LSTAR);
1620 move_msr_up(vmx, index, save_nmsrs++);
1621 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1623 move_msr_up(vmx, index, save_nmsrs++);
1626 index = __find_msr_index(vmx, MSR_EFER);
1627 if (index >= 0 && update_transition_efer(vmx, index))
1628 move_msr_up(vmx, index, save_nmsrs++);
1629 index = __find_msr_index(vmx, MSR_TSC_AUX);
1630 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1631 move_msr_up(vmx, index, save_nmsrs++);
1633 vmx->save_nmsrs = save_nmsrs;
1634 vmx->guest_msrs_ready = false;
1636 if (cpu_has_vmx_msr_bitmap())
1637 vmx_update_msr_bitmap(&vmx->vcpu);
1640 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1642 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1644 if (is_guest_mode(vcpu) &&
1645 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1646 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1648 return vcpu->arch.tsc_offset;
1651 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1653 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1654 u64 g_tsc_offset = 0;
1657 * We're here if L1 chose not to trap WRMSR to TSC. According
1658 * to the spec, this should set L1's TSC; The offset that L1
1659 * set for L2 remains unchanged, and still needs to be added
1660 * to the newly set TSC to get L2's TSC.
1662 if (is_guest_mode(vcpu) &&
1663 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1664 g_tsc_offset = vmcs12->tsc_offset;
1666 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1667 vcpu->arch.tsc_offset - g_tsc_offset,
1669 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1670 return offset + g_tsc_offset;
1674 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1675 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1676 * all guests if the "nested" module option is off, and can also be disabled
1677 * for a single guest by disabling its VMX cpuid bit.
1679 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1681 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1684 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1687 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1689 return !(val & ~valid_bits);
1692 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1694 switch (msr->index) {
1695 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1698 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1707 * Reads an msr value (of 'msr_index') into 'pdata'.
1708 * Returns 0 on success, non-0 otherwise.
1709 * Assumes vcpu_load() was already called.
1711 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1713 struct vcpu_vmx *vmx = to_vmx(vcpu);
1714 struct shared_msr_entry *msr;
1717 switch (msr_info->index) {
1718 #ifdef CONFIG_X86_64
1720 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1723 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1725 case MSR_KERNEL_GS_BASE:
1726 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1730 return kvm_get_msr_common(vcpu, msr_info);
1731 case MSR_IA32_SPEC_CTRL:
1732 if (!msr_info->host_initiated &&
1733 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1736 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1738 case MSR_IA32_SYSENTER_CS:
1739 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1741 case MSR_IA32_SYSENTER_EIP:
1742 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1744 case MSR_IA32_SYSENTER_ESP:
1745 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1747 case MSR_IA32_BNDCFGS:
1748 if (!kvm_mpx_supported() ||
1749 (!msr_info->host_initiated &&
1750 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1752 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1754 case MSR_IA32_MCG_EXT_CTL:
1755 if (!msr_info->host_initiated &&
1756 !(vmx->msr_ia32_feature_control &
1757 FEATURE_CONTROL_LMCE))
1759 msr_info->data = vcpu->arch.mcg_ext_ctl;
1761 case MSR_IA32_FEATURE_CONTROL:
1762 msr_info->data = vmx->msr_ia32_feature_control;
1764 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1765 if (!nested_vmx_allowed(vcpu))
1767 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1770 if (!vmx_xsaves_supported() ||
1771 (!msr_info->host_initiated &&
1772 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1773 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1775 msr_info->data = vcpu->arch.ia32_xss;
1777 case MSR_IA32_RTIT_CTL:
1778 if (pt_mode != PT_MODE_HOST_GUEST)
1780 msr_info->data = vmx->pt_desc.guest.ctl;
1782 case MSR_IA32_RTIT_STATUS:
1783 if (pt_mode != PT_MODE_HOST_GUEST)
1785 msr_info->data = vmx->pt_desc.guest.status;
1787 case MSR_IA32_RTIT_CR3_MATCH:
1788 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1789 !intel_pt_validate_cap(vmx->pt_desc.caps,
1790 PT_CAP_cr3_filtering))
1792 msr_info->data = vmx->pt_desc.guest.cr3_match;
1794 case MSR_IA32_RTIT_OUTPUT_BASE:
1795 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1796 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1797 PT_CAP_topa_output) &&
1798 !intel_pt_validate_cap(vmx->pt_desc.caps,
1799 PT_CAP_single_range_output)))
1801 msr_info->data = vmx->pt_desc.guest.output_base;
1803 case MSR_IA32_RTIT_OUTPUT_MASK:
1804 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1805 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1806 PT_CAP_topa_output) &&
1807 !intel_pt_validate_cap(vmx->pt_desc.caps,
1808 PT_CAP_single_range_output)))
1810 msr_info->data = vmx->pt_desc.guest.output_mask;
1812 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1813 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1814 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1815 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1816 PT_CAP_num_address_ranges)))
1819 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1821 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1824 if (!msr_info->host_initiated &&
1825 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1827 /* Else, falls through */
1829 msr = find_msr_entry(vmx, msr_info->index);
1831 msr_info->data = msr->data;
1834 return kvm_get_msr_common(vcpu, msr_info);
1841 * Writes msr value into into the appropriate "register".
1842 * Returns 0 on success, non-0 otherwise.
1843 * Assumes vcpu_load() was already called.
1845 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1847 struct vcpu_vmx *vmx = to_vmx(vcpu);
1848 struct shared_msr_entry *msr;
1850 u32 msr_index = msr_info->index;
1851 u64 data = msr_info->data;
1854 switch (msr_index) {
1856 ret = kvm_set_msr_common(vcpu, msr_info);
1858 #ifdef CONFIG_X86_64
1860 vmx_segment_cache_clear(vmx);
1861 vmcs_writel(GUEST_FS_BASE, data);
1864 vmx_segment_cache_clear(vmx);
1865 vmcs_writel(GUEST_GS_BASE, data);
1867 case MSR_KERNEL_GS_BASE:
1868 vmx_write_guest_kernel_gs_base(vmx, data);
1871 case MSR_IA32_SYSENTER_CS:
1872 if (is_guest_mode(vcpu))
1873 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1874 vmcs_write32(GUEST_SYSENTER_CS, data);
1876 case MSR_IA32_SYSENTER_EIP:
1877 if (is_guest_mode(vcpu))
1878 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1879 vmcs_writel(GUEST_SYSENTER_EIP, data);
1881 case MSR_IA32_SYSENTER_ESP:
1882 if (is_guest_mode(vcpu))
1883 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1884 vmcs_writel(GUEST_SYSENTER_ESP, data);
1886 case MSR_IA32_DEBUGCTLMSR:
1887 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1888 VM_EXIT_SAVE_DEBUG_CONTROLS)
1889 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1891 ret = kvm_set_msr_common(vcpu, msr_info);
1894 case MSR_IA32_BNDCFGS:
1895 if (!kvm_mpx_supported() ||
1896 (!msr_info->host_initiated &&
1897 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1899 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1900 (data & MSR_IA32_BNDCFGS_RSVD))
1902 vmcs_write64(GUEST_BNDCFGS, data);
1904 case MSR_IA32_SPEC_CTRL:
1905 if (!msr_info->host_initiated &&
1906 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1909 /* The STIBP bit doesn't fault even if it's not advertised */
1910 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1913 vmx->spec_ctrl = data;
1920 * When it's written (to non-zero) for the first time, pass
1924 * The handling of the MSR bitmap for L2 guests is done in
1925 * nested_vmx_merge_msr_bitmap. We should not touch the
1926 * vmcs02.msr_bitmap here since it gets completely overwritten
1927 * in the merging. We update the vmcs01 here for L1 as well
1928 * since it will end up touching the MSR anyway now.
1930 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1934 case MSR_IA32_PRED_CMD:
1935 if (!msr_info->host_initiated &&
1936 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1939 if (data & ~PRED_CMD_IBPB)
1945 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1949 * When it's written (to non-zero) for the first time, pass
1953 * The handling of the MSR bitmap for L2 guests is done in
1954 * nested_vmx_merge_msr_bitmap. We should not touch the
1955 * vmcs02.msr_bitmap here since it gets completely overwritten
1958 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1961 case MSR_IA32_CR_PAT:
1962 if (!kvm_pat_valid(data))
1965 if (is_guest_mode(vcpu) &&
1966 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
1967 get_vmcs12(vcpu)->guest_ia32_pat = data;
1969 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1970 vmcs_write64(GUEST_IA32_PAT, data);
1971 vcpu->arch.pat = data;
1974 ret = kvm_set_msr_common(vcpu, msr_info);
1976 case MSR_IA32_TSC_ADJUST:
1977 ret = kvm_set_msr_common(vcpu, msr_info);
1979 case MSR_IA32_MCG_EXT_CTL:
1980 if ((!msr_info->host_initiated &&
1981 !(to_vmx(vcpu)->msr_ia32_feature_control &
1982 FEATURE_CONTROL_LMCE)) ||
1983 (data & ~MCG_EXT_CTL_LMCE_EN))
1985 vcpu->arch.mcg_ext_ctl = data;
1987 case MSR_IA32_FEATURE_CONTROL:
1988 if (!vmx_feature_control_msr_valid(vcpu, data) ||
1989 (to_vmx(vcpu)->msr_ia32_feature_control &
1990 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1992 vmx->msr_ia32_feature_control = data;
1993 if (msr_info->host_initiated && data == 0)
1994 vmx_leave_nested(vcpu);
1996 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1997 if (!msr_info->host_initiated)
1998 return 1; /* they are read-only */
1999 if (!nested_vmx_allowed(vcpu))
2001 return vmx_set_vmx_msr(vcpu, msr_index, data);
2003 if (!vmx_xsaves_supported() ||
2004 (!msr_info->host_initiated &&
2005 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
2006 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
2009 * The only supported bit as of Skylake is bit 8, but
2010 * it is not supported on KVM.
2014 vcpu->arch.ia32_xss = data;
2015 if (vcpu->arch.ia32_xss != host_xss)
2016 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2017 vcpu->arch.ia32_xss, host_xss, false);
2019 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2021 case MSR_IA32_RTIT_CTL:
2022 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2023 vmx_rtit_ctl_check(vcpu, data) ||
2026 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2027 vmx->pt_desc.guest.ctl = data;
2028 pt_update_intercept_for_msr(vmx);
2030 case MSR_IA32_RTIT_STATUS:
2031 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2032 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2033 (data & MSR_IA32_RTIT_STATUS_MASK))
2035 vmx->pt_desc.guest.status = data;
2037 case MSR_IA32_RTIT_CR3_MATCH:
2038 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2039 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2040 !intel_pt_validate_cap(vmx->pt_desc.caps,
2041 PT_CAP_cr3_filtering))
2043 vmx->pt_desc.guest.cr3_match = data;
2045 case MSR_IA32_RTIT_OUTPUT_BASE:
2046 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2047 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2048 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2049 PT_CAP_topa_output) &&
2050 !intel_pt_validate_cap(vmx->pt_desc.caps,
2051 PT_CAP_single_range_output)) ||
2052 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2054 vmx->pt_desc.guest.output_base = data;
2056 case MSR_IA32_RTIT_OUTPUT_MASK:
2057 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2058 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2059 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2060 PT_CAP_topa_output) &&
2061 !intel_pt_validate_cap(vmx->pt_desc.caps,
2062 PT_CAP_single_range_output)))
2064 vmx->pt_desc.guest.output_mask = data;
2066 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2067 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2068 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2069 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2070 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2071 PT_CAP_num_address_ranges)))
2074 vmx->pt_desc.guest.addr_b[index / 2] = data;
2076 vmx->pt_desc.guest.addr_a[index / 2] = data;
2079 if (!msr_info->host_initiated &&
2080 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2082 /* Check reserved bit, higher 32 bits should be zero */
2083 if ((data >> 32) != 0)
2085 /* Else, falls through */
2087 msr = find_msr_entry(vmx, msr_index);
2089 u64 old_msr_data = msr->data;
2091 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2093 ret = kvm_set_shared_msr(msr->index, msr->data,
2097 msr->data = old_msr_data;
2101 ret = kvm_set_msr_common(vcpu, msr_info);
2107 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2109 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2112 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2115 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2117 case VCPU_EXREG_PDPTR:
2119 ept_save_pdptrs(vcpu);
2126 static __init int cpu_has_kvm_support(void)
2128 return cpu_has_vmx();
2131 static __init int vmx_disabled_by_bios(void)
2135 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2136 if (msr & FEATURE_CONTROL_LOCKED) {
2137 /* launched w/ TXT and VMX disabled */
2138 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2141 /* launched w/o TXT and VMX only enabled w/ TXT */
2142 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2143 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2144 && !tboot_enabled()) {
2145 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2146 "activate TXT before enabling KVM\n");
2149 /* launched w/o TXT and VMX disabled */
2150 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2151 && !tboot_enabled())
2158 static void kvm_cpu_vmxon(u64 addr)
2160 cr4_set_bits(X86_CR4_VMXE);
2161 intel_pt_handle_vmx(1);
2163 asm volatile ("vmxon %0" : : "m"(addr));
2166 static int hardware_enable(void)
2168 int cpu = raw_smp_processor_id();
2169 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2172 if (cr4_read_shadow() & X86_CR4_VMXE)
2176 * This can happen if we hot-added a CPU but failed to allocate
2177 * VP assist page for it.
2179 if (static_branch_unlikely(&enable_evmcs) &&
2180 !hv_get_vp_assist_page(cpu))
2183 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2184 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2185 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2188 * Now we can enable the vmclear operation in kdump
2189 * since the loaded_vmcss_on_cpu list on this cpu
2190 * has been initialized.
2192 * Though the cpu is not in VMX operation now, there
2193 * is no problem to enable the vmclear operation
2194 * for the loaded_vmcss_on_cpu list is empty!
2196 crash_enable_local_vmclear(cpu);
2198 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2200 test_bits = FEATURE_CONTROL_LOCKED;
2201 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2202 if (tboot_enabled())
2203 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2205 if ((old & test_bits) != test_bits) {
2206 /* enable and lock */
2207 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2209 kvm_cpu_vmxon(phys_addr);
2216 static void vmclear_local_loaded_vmcss(void)
2218 int cpu = raw_smp_processor_id();
2219 struct loaded_vmcs *v, *n;
2221 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2222 loaded_vmcss_on_cpu_link)
2223 __loaded_vmcs_clear(v);
2227 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2230 static void kvm_cpu_vmxoff(void)
2232 asm volatile (__ex("vmxoff"));
2234 intel_pt_handle_vmx(0);
2235 cr4_clear_bits(X86_CR4_VMXE);
2238 static void hardware_disable(void)
2240 vmclear_local_loaded_vmcss();
2244 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2245 u32 msr, u32 *result)
2247 u32 vmx_msr_low, vmx_msr_high;
2248 u32 ctl = ctl_min | ctl_opt;
2250 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2252 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2253 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2255 /* Ensure minimum (required) set of control bits are supported. */
2263 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2264 struct vmx_capability *vmx_cap)
2266 u32 vmx_msr_low, vmx_msr_high;
2267 u32 min, opt, min2, opt2;
2268 u32 _pin_based_exec_control = 0;
2269 u32 _cpu_based_exec_control = 0;
2270 u32 _cpu_based_2nd_exec_control = 0;
2271 u32 _vmexit_control = 0;
2272 u32 _vmentry_control = 0;
2274 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2275 min = CPU_BASED_HLT_EXITING |
2276 #ifdef CONFIG_X86_64
2277 CPU_BASED_CR8_LOAD_EXITING |
2278 CPU_BASED_CR8_STORE_EXITING |
2280 CPU_BASED_CR3_LOAD_EXITING |
2281 CPU_BASED_CR3_STORE_EXITING |
2282 CPU_BASED_UNCOND_IO_EXITING |
2283 CPU_BASED_MOV_DR_EXITING |
2284 CPU_BASED_USE_TSC_OFFSETING |
2285 CPU_BASED_MWAIT_EXITING |
2286 CPU_BASED_MONITOR_EXITING |
2287 CPU_BASED_INVLPG_EXITING |
2288 CPU_BASED_RDPMC_EXITING;
2290 opt = CPU_BASED_TPR_SHADOW |
2291 CPU_BASED_USE_MSR_BITMAPS |
2292 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2293 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2294 &_cpu_based_exec_control) < 0)
2296 #ifdef CONFIG_X86_64
2297 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2298 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2299 ~CPU_BASED_CR8_STORE_EXITING;
2301 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2303 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2304 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2305 SECONDARY_EXEC_WBINVD_EXITING |
2306 SECONDARY_EXEC_ENABLE_VPID |
2307 SECONDARY_EXEC_ENABLE_EPT |
2308 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2309 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2310 SECONDARY_EXEC_DESC |
2311 SECONDARY_EXEC_RDTSCP |
2312 SECONDARY_EXEC_ENABLE_INVPCID |
2313 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2314 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2315 SECONDARY_EXEC_SHADOW_VMCS |
2316 SECONDARY_EXEC_XSAVES |
2317 SECONDARY_EXEC_RDSEED_EXITING |
2318 SECONDARY_EXEC_RDRAND_EXITING |
2319 SECONDARY_EXEC_ENABLE_PML |
2320 SECONDARY_EXEC_TSC_SCALING |
2321 SECONDARY_EXEC_PT_USE_GPA |
2322 SECONDARY_EXEC_PT_CONCEAL_VMX |
2323 SECONDARY_EXEC_ENABLE_VMFUNC |
2324 SECONDARY_EXEC_ENCLS_EXITING;
2325 if (adjust_vmx_controls(min2, opt2,
2326 MSR_IA32_VMX_PROCBASED_CTLS2,
2327 &_cpu_based_2nd_exec_control) < 0)
2330 #ifndef CONFIG_X86_64
2331 if (!(_cpu_based_2nd_exec_control &
2332 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2333 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2336 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2337 _cpu_based_2nd_exec_control &= ~(
2338 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2339 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2340 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2342 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2343 &vmx_cap->ept, &vmx_cap->vpid);
2345 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2346 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2348 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2349 CPU_BASED_CR3_STORE_EXITING |
2350 CPU_BASED_INVLPG_EXITING);
2351 } else if (vmx_cap->ept) {
2353 pr_warn_once("EPT CAP should not exist if not support "
2354 "1-setting enable EPT VM-execution control\n");
2356 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2359 pr_warn_once("VPID CAP should not exist if not support "
2360 "1-setting enable VPID VM-execution control\n");
2363 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2364 #ifdef CONFIG_X86_64
2365 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2367 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2368 VM_EXIT_LOAD_IA32_PAT |
2369 VM_EXIT_LOAD_IA32_EFER |
2370 VM_EXIT_CLEAR_BNDCFGS |
2371 VM_EXIT_PT_CONCEAL_PIP |
2372 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2373 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2374 &_vmexit_control) < 0)
2377 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2378 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2379 PIN_BASED_VMX_PREEMPTION_TIMER;
2380 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2381 &_pin_based_exec_control) < 0)
2384 if (cpu_has_broken_vmx_preemption_timer())
2385 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2386 if (!(_cpu_based_2nd_exec_control &
2387 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2388 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2390 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2391 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2392 VM_ENTRY_LOAD_IA32_PAT |
2393 VM_ENTRY_LOAD_IA32_EFER |
2394 VM_ENTRY_LOAD_BNDCFGS |
2395 VM_ENTRY_PT_CONCEAL_PIP |
2396 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2397 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2398 &_vmentry_control) < 0)
2402 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2403 * can't be used due to an errata where VM Exit may incorrectly clear
2404 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2405 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2407 if (boot_cpu_data.x86 == 0x6) {
2408 switch (boot_cpu_data.x86_model) {
2409 case 26: /* AAK155 */
2410 case 30: /* AAP115 */
2411 case 37: /* AAT100 */
2412 case 44: /* BC86,AAY89,BD102 */
2414 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2415 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2416 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2417 "does not work properly. Using workaround\n");
2425 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2427 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2428 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2431 #ifdef CONFIG_X86_64
2432 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2433 if (vmx_msr_high & (1u<<16))
2437 /* Require Write-Back (WB) memory type for VMCS accesses. */
2438 if (((vmx_msr_high >> 18) & 15) != 6)
2441 vmcs_conf->size = vmx_msr_high & 0x1fff;
2442 vmcs_conf->order = get_order(vmcs_conf->size);
2443 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2445 vmcs_conf->revision_id = vmx_msr_low;
2447 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2448 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2449 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2450 vmcs_conf->vmexit_ctrl = _vmexit_control;
2451 vmcs_conf->vmentry_ctrl = _vmentry_control;
2453 if (static_branch_unlikely(&enable_evmcs))
2454 evmcs_sanitize_exec_ctrls(vmcs_conf);
2459 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2461 int node = cpu_to_node(cpu);
2465 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2468 vmcs = page_address(pages);
2469 memset(vmcs, 0, vmcs_config.size);
2471 /* KVM supports Enlightened VMCS v1 only */
2472 if (static_branch_unlikely(&enable_evmcs))
2473 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2475 vmcs->hdr.revision_id = vmcs_config.revision_id;
2478 vmcs->hdr.shadow_vmcs = 1;
2482 void free_vmcs(struct vmcs *vmcs)
2484 free_pages((unsigned long)vmcs, vmcs_config.order);
2488 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2490 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2492 if (!loaded_vmcs->vmcs)
2494 loaded_vmcs_clear(loaded_vmcs);
2495 free_vmcs(loaded_vmcs->vmcs);
2496 loaded_vmcs->vmcs = NULL;
2497 if (loaded_vmcs->msr_bitmap)
2498 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2499 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2502 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2504 loaded_vmcs->vmcs = alloc_vmcs(false);
2505 if (!loaded_vmcs->vmcs)
2508 loaded_vmcs->shadow_vmcs = NULL;
2509 loaded_vmcs->hv_timer_soft_disabled = false;
2510 loaded_vmcs_init(loaded_vmcs);
2512 if (cpu_has_vmx_msr_bitmap()) {
2513 loaded_vmcs->msr_bitmap = (unsigned long *)
2514 __get_free_page(GFP_KERNEL_ACCOUNT);
2515 if (!loaded_vmcs->msr_bitmap)
2517 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2519 if (IS_ENABLED(CONFIG_HYPERV) &&
2520 static_branch_unlikely(&enable_evmcs) &&
2521 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2522 struct hv_enlightened_vmcs *evmcs =
2523 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2525 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2529 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2530 memset(&loaded_vmcs->controls_shadow, 0,
2531 sizeof(struct vmcs_controls_shadow));
2536 free_loaded_vmcs(loaded_vmcs);
2540 static void free_kvm_area(void)
2544 for_each_possible_cpu(cpu) {
2545 free_vmcs(per_cpu(vmxarea, cpu));
2546 per_cpu(vmxarea, cpu) = NULL;
2550 static __init int alloc_kvm_area(void)
2554 for_each_possible_cpu(cpu) {
2557 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2564 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2565 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2566 * revision_id reported by MSR_IA32_VMX_BASIC.
2568 * However, even though not explicitly documented by
2569 * TLFS, VMXArea passed as VMXON argument should
2570 * still be marked with revision_id reported by
2573 if (static_branch_unlikely(&enable_evmcs))
2574 vmcs->hdr.revision_id = vmcs_config.revision_id;
2576 per_cpu(vmxarea, cpu) = vmcs;
2581 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2582 struct kvm_segment *save)
2584 if (!emulate_invalid_guest_state) {
2586 * CS and SS RPL should be equal during guest entry according
2587 * to VMX spec, but in reality it is not always so. Since vcpu
2588 * is in the middle of the transition from real mode to
2589 * protected mode it is safe to assume that RPL 0 is a good
2592 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2593 save->selector &= ~SEGMENT_RPL_MASK;
2594 save->dpl = save->selector & SEGMENT_RPL_MASK;
2597 vmx_set_segment(vcpu, save, seg);
2600 static void enter_pmode(struct kvm_vcpu *vcpu)
2602 unsigned long flags;
2603 struct vcpu_vmx *vmx = to_vmx(vcpu);
2606 * Update real mode segment cache. It may be not up-to-date if sement
2607 * register was written while vcpu was in a guest mode.
2609 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2610 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2611 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2612 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2613 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2614 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2616 vmx->rmode.vm86_active = 0;
2618 vmx_segment_cache_clear(vmx);
2620 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2622 flags = vmcs_readl(GUEST_RFLAGS);
2623 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2624 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2625 vmcs_writel(GUEST_RFLAGS, flags);
2627 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2628 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2630 update_exception_bitmap(vcpu);
2632 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2633 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2634 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2635 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2636 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2637 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2640 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2642 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2643 struct kvm_segment var = *save;
2646 if (seg == VCPU_SREG_CS)
2649 if (!emulate_invalid_guest_state) {
2650 var.selector = var.base >> 4;
2651 var.base = var.base & 0xffff0;
2661 if (save->base & 0xf)
2662 printk_once(KERN_WARNING "kvm: segment base is not "
2663 "paragraph aligned when entering "
2664 "protected mode (seg=%d)", seg);
2667 vmcs_write16(sf->selector, var.selector);
2668 vmcs_writel(sf->base, var.base);
2669 vmcs_write32(sf->limit, var.limit);
2670 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2673 static void enter_rmode(struct kvm_vcpu *vcpu)
2675 unsigned long flags;
2676 struct vcpu_vmx *vmx = to_vmx(vcpu);
2677 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2679 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2680 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2681 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2682 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2683 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2687 vmx->rmode.vm86_active = 1;
2690 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2691 * vcpu. Warn the user that an update is overdue.
2693 if (!kvm_vmx->tss_addr)
2694 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2695 "called before entering vcpu\n");
2697 vmx_segment_cache_clear(vmx);
2699 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2700 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2701 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2703 flags = vmcs_readl(GUEST_RFLAGS);
2704 vmx->rmode.save_rflags = flags;
2706 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2708 vmcs_writel(GUEST_RFLAGS, flags);
2709 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2710 update_exception_bitmap(vcpu);
2712 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2713 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2714 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2715 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2716 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2717 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2719 kvm_mmu_reset_context(vcpu);
2722 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2724 struct vcpu_vmx *vmx = to_vmx(vcpu);
2725 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2730 vcpu->arch.efer = efer;
2731 if (efer & EFER_LMA) {
2732 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2735 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2737 msr->data = efer & ~EFER_LME;
2742 #ifdef CONFIG_X86_64
2744 static void enter_lmode(struct kvm_vcpu *vcpu)
2748 vmx_segment_cache_clear(to_vmx(vcpu));
2750 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2751 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2752 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2754 vmcs_write32(GUEST_TR_AR_BYTES,
2755 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2756 | VMX_AR_TYPE_BUSY_64_TSS);
2758 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2761 static void exit_lmode(struct kvm_vcpu *vcpu)
2763 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2764 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2769 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2771 int vpid = to_vmx(vcpu)->vpid;
2773 if (!vpid_sync_vcpu_addr(vpid, addr))
2774 vpid_sync_context(vpid);
2777 * If VPIDs are not supported or enabled, then the above is a no-op.
2778 * But we don't really need a TLB flush in that case anyway, because
2779 * each VM entry/exit includes an implicit flush when VPID is 0.
2783 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2785 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2787 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2788 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2791 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2793 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2794 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2795 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2798 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2800 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2802 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2803 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2806 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2808 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2810 if (!test_bit(VCPU_EXREG_PDPTR,
2811 (unsigned long *)&vcpu->arch.regs_dirty))
2814 if (is_pae_paging(vcpu)) {
2815 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2816 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2817 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2818 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2822 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2824 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2826 if (is_pae_paging(vcpu)) {
2827 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2828 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2829 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2830 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2833 __set_bit(VCPU_EXREG_PDPTR,
2834 (unsigned long *)&vcpu->arch.regs_avail);
2835 __set_bit(VCPU_EXREG_PDPTR,
2836 (unsigned long *)&vcpu->arch.regs_dirty);
2839 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2841 struct kvm_vcpu *vcpu)
2843 struct vcpu_vmx *vmx = to_vmx(vcpu);
2845 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2846 vmx_decache_cr3(vcpu);
2847 if (!(cr0 & X86_CR0_PG)) {
2848 /* From paging/starting to nonpaging */
2849 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2850 CPU_BASED_CR3_STORE_EXITING);
2851 vcpu->arch.cr0 = cr0;
2852 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2853 } else if (!is_paging(vcpu)) {
2854 /* From nonpaging to paging */
2855 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2856 CPU_BASED_CR3_STORE_EXITING);
2857 vcpu->arch.cr0 = cr0;
2858 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2861 if (!(cr0 & X86_CR0_WP))
2862 *hw_cr0 &= ~X86_CR0_WP;
2865 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2867 struct vcpu_vmx *vmx = to_vmx(vcpu);
2868 unsigned long hw_cr0;
2870 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2871 if (enable_unrestricted_guest)
2872 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2874 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2876 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2879 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2883 #ifdef CONFIG_X86_64
2884 if (vcpu->arch.efer & EFER_LME) {
2885 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2887 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2892 if (enable_ept && !enable_unrestricted_guest)
2893 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2895 vmcs_writel(CR0_READ_SHADOW, cr0);
2896 vmcs_writel(GUEST_CR0, hw_cr0);
2897 vcpu->arch.cr0 = cr0;
2899 /* depends on vcpu->arch.cr0 to be set to a new value */
2900 vmx->emulation_required = emulation_required(vcpu);
2903 static int get_ept_level(struct kvm_vcpu *vcpu)
2905 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2910 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2912 u64 eptp = VMX_EPTP_MT_WB;
2914 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2916 if (enable_ept_ad_bits &&
2917 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2918 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2919 eptp |= (root_hpa & PAGE_MASK);
2924 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2926 struct kvm *kvm = vcpu->kvm;
2927 unsigned long guest_cr3;
2932 eptp = construct_eptp(vcpu, cr3);
2933 vmcs_write64(EPT_POINTER, eptp);
2935 if (kvm_x86_ops->tlb_remote_flush) {
2936 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2937 to_vmx(vcpu)->ept_pointer = eptp;
2938 to_kvm_vmx(kvm)->ept_pointers_match
2939 = EPT_POINTERS_CHECK;
2940 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2943 if (enable_unrestricted_guest || is_paging(vcpu) ||
2944 is_guest_mode(vcpu))
2945 guest_cr3 = kvm_read_cr3(vcpu);
2947 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
2948 ept_load_pdptrs(vcpu);
2951 vmcs_writel(GUEST_CR3, guest_cr3);
2954 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2956 struct vcpu_vmx *vmx = to_vmx(vcpu);
2958 * Pass through host's Machine Check Enable value to hw_cr4, which
2959 * is in force while we are in guest mode. Do not let guests control
2960 * this bit, even if host CR4.MCE == 0.
2962 unsigned long hw_cr4;
2964 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2965 if (enable_unrestricted_guest)
2966 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2967 else if (vmx->rmode.vm86_active)
2968 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2970 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
2972 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2973 if (cr4 & X86_CR4_UMIP) {
2974 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
2975 hw_cr4 &= ~X86_CR4_UMIP;
2976 } else if (!is_guest_mode(vcpu) ||
2977 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
2978 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
2982 if (cr4 & X86_CR4_VMXE) {
2984 * To use VMXON (and later other VMX instructions), a guest
2985 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2986 * So basically the check on whether to allow nested VMX
2987 * is here. We operate under the default treatment of SMM,
2988 * so VMX cannot be enabled under SMM.
2990 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
2994 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
2997 vcpu->arch.cr4 = cr4;
2999 if (!enable_unrestricted_guest) {
3001 if (!is_paging(vcpu)) {
3002 hw_cr4 &= ~X86_CR4_PAE;
3003 hw_cr4 |= X86_CR4_PSE;
3004 } else if (!(cr4 & X86_CR4_PAE)) {
3005 hw_cr4 &= ~X86_CR4_PAE;
3010 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3011 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3012 * to be manually disabled when guest switches to non-paging
3015 * If !enable_unrestricted_guest, the CPU is always running
3016 * with CR0.PG=1 and CR4 needs to be modified.
3017 * If enable_unrestricted_guest, the CPU automatically
3018 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3020 if (!is_paging(vcpu))
3021 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3024 vmcs_writel(CR4_READ_SHADOW, cr4);
3025 vmcs_writel(GUEST_CR4, hw_cr4);
3029 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3031 struct vcpu_vmx *vmx = to_vmx(vcpu);
3034 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3035 *var = vmx->rmode.segs[seg];
3036 if (seg == VCPU_SREG_TR
3037 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3039 var->base = vmx_read_guest_seg_base(vmx, seg);
3040 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3043 var->base = vmx_read_guest_seg_base(vmx, seg);
3044 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3045 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3046 ar = vmx_read_guest_seg_ar(vmx, seg);
3047 var->unusable = (ar >> 16) & 1;
3048 var->type = ar & 15;
3049 var->s = (ar >> 4) & 1;
3050 var->dpl = (ar >> 5) & 3;
3052 * Some userspaces do not preserve unusable property. Since usable
3053 * segment has to be present according to VMX spec we can use present
3054 * property to amend userspace bug by making unusable segment always
3055 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3056 * segment as unusable.
3058 var->present = !var->unusable;
3059 var->avl = (ar >> 12) & 1;
3060 var->l = (ar >> 13) & 1;
3061 var->db = (ar >> 14) & 1;
3062 var->g = (ar >> 15) & 1;
3065 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3067 struct kvm_segment s;
3069 if (to_vmx(vcpu)->rmode.vm86_active) {
3070 vmx_get_segment(vcpu, &s, seg);
3073 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3076 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3078 struct vcpu_vmx *vmx = to_vmx(vcpu);
3080 if (unlikely(vmx->rmode.vm86_active))
3083 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3084 return VMX_AR_DPL(ar);
3088 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3092 if (var->unusable || !var->present)
3095 ar = var->type & 15;
3096 ar |= (var->s & 1) << 4;
3097 ar |= (var->dpl & 3) << 5;
3098 ar |= (var->present & 1) << 7;
3099 ar |= (var->avl & 1) << 12;
3100 ar |= (var->l & 1) << 13;
3101 ar |= (var->db & 1) << 14;
3102 ar |= (var->g & 1) << 15;
3108 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3110 struct vcpu_vmx *vmx = to_vmx(vcpu);
3111 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3113 vmx_segment_cache_clear(vmx);
3115 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3116 vmx->rmode.segs[seg] = *var;
3117 if (seg == VCPU_SREG_TR)
3118 vmcs_write16(sf->selector, var->selector);
3120 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3124 vmcs_writel(sf->base, var->base);
3125 vmcs_write32(sf->limit, var->limit);
3126 vmcs_write16(sf->selector, var->selector);
3129 * Fix the "Accessed" bit in AR field of segment registers for older
3131 * IA32 arch specifies that at the time of processor reset the
3132 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3133 * is setting it to 0 in the userland code. This causes invalid guest
3134 * state vmexit when "unrestricted guest" mode is turned on.
3135 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3136 * tree. Newer qemu binaries with that qemu fix would not need this
3139 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3140 var->type |= 0x1; /* Accessed */
3142 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3145 vmx->emulation_required = emulation_required(vcpu);
3148 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3150 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3152 *db = (ar >> 14) & 1;
3153 *l = (ar >> 13) & 1;
3156 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3158 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3159 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3162 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3164 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3165 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3168 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3170 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3171 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3174 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3176 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3177 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3180 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3182 struct kvm_segment var;
3185 vmx_get_segment(vcpu, &var, seg);
3187 if (seg == VCPU_SREG_CS)
3189 ar = vmx_segment_access_rights(&var);
3191 if (var.base != (var.selector << 4))
3193 if (var.limit != 0xffff)
3201 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3203 struct kvm_segment cs;
3204 unsigned int cs_rpl;
3206 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3207 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3211 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3215 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3216 if (cs.dpl > cs_rpl)
3219 if (cs.dpl != cs_rpl)
3225 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3229 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3231 struct kvm_segment ss;
3232 unsigned int ss_rpl;
3234 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3235 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3239 if (ss.type != 3 && ss.type != 7)
3243 if (ss.dpl != ss_rpl) /* DPL != RPL */
3251 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3253 struct kvm_segment var;
3256 vmx_get_segment(vcpu, &var, seg);
3257 rpl = var.selector & SEGMENT_RPL_MASK;
3265 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3266 if (var.dpl < rpl) /* DPL < RPL */
3270 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3276 static bool tr_valid(struct kvm_vcpu *vcpu)
3278 struct kvm_segment tr;
3280 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3284 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3286 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3294 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3296 struct kvm_segment ldtr;
3298 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3302 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3312 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3314 struct kvm_segment cs, ss;
3316 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3317 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3319 return ((cs.selector & SEGMENT_RPL_MASK) ==
3320 (ss.selector & SEGMENT_RPL_MASK));
3324 * Check if guest state is valid. Returns true if valid, false if
3326 * We assume that registers are always usable
3328 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3330 if (enable_unrestricted_guest)
3333 /* real mode guest state checks */
3334 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3335 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3337 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3339 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3341 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3343 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3345 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3348 /* protected mode guest state checks */
3349 if (!cs_ss_rpl_check(vcpu))
3351 if (!code_segment_valid(vcpu))
3353 if (!stack_segment_valid(vcpu))
3355 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3357 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3359 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3361 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3363 if (!tr_valid(vcpu))
3365 if (!ldtr_valid(vcpu))
3369 * - Add checks on RIP
3370 * - Add checks on RFLAGS
3376 static int init_rmode_tss(struct kvm *kvm)
3382 idx = srcu_read_lock(&kvm->srcu);
3383 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3384 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3387 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3388 r = kvm_write_guest_page(kvm, fn++, &data,
3389 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3392 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3395 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3399 r = kvm_write_guest_page(kvm, fn, &data,
3400 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3403 srcu_read_unlock(&kvm->srcu, idx);
3407 static int init_rmode_identity_map(struct kvm *kvm)
3409 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3411 kvm_pfn_t identity_map_pfn;
3414 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3415 mutex_lock(&kvm->slots_lock);
3417 if (likely(kvm_vmx->ept_identity_pagetable_done))
3420 if (!kvm_vmx->ept_identity_map_addr)
3421 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3422 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3424 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3425 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3429 idx = srcu_read_lock(&kvm->srcu);
3430 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3433 /* Set up identity-mapping pagetable for EPT in real mode */
3434 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3435 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3436 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3437 r = kvm_write_guest_page(kvm, identity_map_pfn,
3438 &tmp, i * sizeof(tmp), sizeof(tmp));
3442 kvm_vmx->ept_identity_pagetable_done = true;
3445 srcu_read_unlock(&kvm->srcu, idx);
3448 mutex_unlock(&kvm->slots_lock);
3452 static void seg_setup(int seg)
3454 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3457 vmcs_write16(sf->selector, 0);
3458 vmcs_writel(sf->base, 0);
3459 vmcs_write32(sf->limit, 0xffff);
3461 if (seg == VCPU_SREG_CS)
3462 ar |= 0x08; /* code segment */
3464 vmcs_write32(sf->ar_bytes, ar);
3467 static int alloc_apic_access_page(struct kvm *kvm)
3472 mutex_lock(&kvm->slots_lock);
3473 if (kvm->arch.apic_access_page_done)
3475 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3476 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3480 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3481 if (is_error_page(page)) {
3487 * Do not pin the page in memory, so that memory hot-unplug
3488 * is able to migrate it.
3491 kvm->arch.apic_access_page_done = true;
3493 mutex_unlock(&kvm->slots_lock);
3497 int allocate_vpid(void)
3503 spin_lock(&vmx_vpid_lock);
3504 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3505 if (vpid < VMX_NR_VPIDS)
3506 __set_bit(vpid, vmx_vpid_bitmap);
3509 spin_unlock(&vmx_vpid_lock);
3513 void free_vpid(int vpid)
3515 if (!enable_vpid || vpid == 0)
3517 spin_lock(&vmx_vpid_lock);
3518 __clear_bit(vpid, vmx_vpid_bitmap);
3519 spin_unlock(&vmx_vpid_lock);
3522 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3525 int f = sizeof(unsigned long);
3527 if (!cpu_has_vmx_msr_bitmap())
3530 if (static_branch_unlikely(&enable_evmcs))
3531 evmcs_touch_msr_bitmap();
3534 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3535 * have the write-low and read-high bitmap offsets the wrong way round.
3536 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3538 if (msr <= 0x1fff) {
3539 if (type & MSR_TYPE_R)
3541 __clear_bit(msr, msr_bitmap + 0x000 / f);
3543 if (type & MSR_TYPE_W)
3545 __clear_bit(msr, msr_bitmap + 0x800 / f);
3547 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3549 if (type & MSR_TYPE_R)
3551 __clear_bit(msr, msr_bitmap + 0x400 / f);
3553 if (type & MSR_TYPE_W)
3555 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3560 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3563 int f = sizeof(unsigned long);
3565 if (!cpu_has_vmx_msr_bitmap())
3568 if (static_branch_unlikely(&enable_evmcs))
3569 evmcs_touch_msr_bitmap();
3572 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3573 * have the write-low and read-high bitmap offsets the wrong way round.
3574 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3576 if (msr <= 0x1fff) {
3577 if (type & MSR_TYPE_R)
3579 __set_bit(msr, msr_bitmap + 0x000 / f);
3581 if (type & MSR_TYPE_W)
3583 __set_bit(msr, msr_bitmap + 0x800 / f);
3585 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3587 if (type & MSR_TYPE_R)
3589 __set_bit(msr, msr_bitmap + 0x400 / f);
3591 if (type & MSR_TYPE_W)
3593 __set_bit(msr, msr_bitmap + 0xc00 / f);
3598 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3599 u32 msr, int type, bool value)
3602 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3604 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3607 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3611 if (cpu_has_secondary_exec_ctrls() &&
3612 (secondary_exec_controls_get(to_vmx(vcpu)) &
3613 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3614 mode |= MSR_BITMAP_MODE_X2APIC;
3615 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3616 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3622 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3627 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3628 unsigned word = msr / BITS_PER_LONG;
3629 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3630 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3633 if (mode & MSR_BITMAP_MODE_X2APIC) {
3635 * TPR reads and writes can be virtualized even if virtual interrupt
3636 * delivery is not in use.
3638 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3639 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3640 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3641 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3642 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3647 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3649 struct vcpu_vmx *vmx = to_vmx(vcpu);
3650 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3651 u8 mode = vmx_msr_bitmap_mode(vcpu);
3652 u8 changed = mode ^ vmx->msr_bitmap_mode;
3657 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3658 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3660 vmx->msr_bitmap_mode = mode;
3663 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3665 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3666 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3669 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3671 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3673 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3675 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3677 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3678 vmx_set_intercept_for_msr(msr_bitmap,
3679 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3680 vmx_set_intercept_for_msr(msr_bitmap,
3681 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3685 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3687 return enable_apicv;
3690 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3692 struct vcpu_vmx *vmx = to_vmx(vcpu);
3697 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3698 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3699 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3702 rvi = vmx_get_rvi();
3704 vapic_page = vmx->nested.virtual_apic_map.hva;
3705 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3707 return ((rvi & 0xf0) > (vppr & 0xf0));
3710 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3714 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3716 if (vcpu->mode == IN_GUEST_MODE) {
3718 * The vector of interrupt to be delivered to vcpu had
3719 * been set in PIR before this function.
3721 * Following cases will be reached in this block, and
3722 * we always send a notification event in all cases as
3725 * Case 1: vcpu keeps in non-root mode. Sending a
3726 * notification event posts the interrupt to vcpu.
3728 * Case 2: vcpu exits to root mode and is still
3729 * runnable. PIR will be synced to vIRR before the
3730 * next vcpu entry. Sending a notification event in
3731 * this case has no effect, as vcpu is not in root
3734 * Case 3: vcpu exits to root mode and is blocked.
3735 * vcpu_block() has already synced PIR to vIRR and
3736 * never blocks vcpu if vIRR is not cleared. Therefore,
3737 * a blocked vcpu here does not wait for any requested
3738 * interrupts in PIR, and sending a notification event
3739 * which has no effect is safe here.
3742 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3749 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3752 struct vcpu_vmx *vmx = to_vmx(vcpu);
3754 if (is_guest_mode(vcpu) &&
3755 vector == vmx->nested.posted_intr_nv) {
3757 * If a posted intr is not recognized by hardware,
3758 * we will accomplish it in the next vmentry.
3760 vmx->nested.pi_pending = true;
3761 kvm_make_request(KVM_REQ_EVENT, vcpu);
3762 /* the PIR and ON have been set by L1. */
3763 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3764 kvm_vcpu_kick(vcpu);
3770 * Send interrupt to vcpu via posted interrupt way.
3771 * 1. If target vcpu is running(non-root mode), send posted interrupt
3772 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3773 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3774 * interrupt from PIR in next vmentry.
3776 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3778 struct vcpu_vmx *vmx = to_vmx(vcpu);
3781 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3785 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3788 /* If a previous notification has sent the IPI, nothing to do. */
3789 if (pi_test_and_set_on(&vmx->pi_desc))
3792 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3793 kvm_vcpu_kick(vcpu);
3797 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3798 * will not change in the lifetime of the guest.
3799 * Note that host-state that does change is set elsewhere. E.g., host-state
3800 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3802 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3806 unsigned long cr0, cr3, cr4;
3809 WARN_ON(cr0 & X86_CR0_TS);
3810 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3813 * Save the most likely value for this task's CR3 in the VMCS.
3814 * We can't use __get_current_cr3_fast() because we're not atomic.
3817 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3818 vmx->loaded_vmcs->host_state.cr3 = cr3;
3820 /* Save the most likely value for this task's CR4 in the VMCS. */
3821 cr4 = cr4_read_shadow();
3822 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3823 vmx->loaded_vmcs->host_state.cr4 = cr4;
3825 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3826 #ifdef CONFIG_X86_64
3828 * Load null selectors, so we can avoid reloading them in
3829 * vmx_prepare_switch_to_host(), in case userspace uses
3830 * the null selectors too (the expected case).
3832 vmcs_write16(HOST_DS_SELECTOR, 0);
3833 vmcs_write16(HOST_ES_SELECTOR, 0);
3835 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3836 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3838 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3839 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3841 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3843 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3845 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3846 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3847 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3848 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3850 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3851 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3852 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3855 if (cpu_has_load_ia32_efer())
3856 vmcs_write64(HOST_IA32_EFER, host_efer);
3859 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3861 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3863 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3864 if (is_guest_mode(&vmx->vcpu))
3865 vmx->vcpu.arch.cr4_guest_owned_bits &=
3866 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3867 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3870 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3872 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3874 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3875 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3878 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3880 if (!enable_preemption_timer)
3881 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3883 return pin_based_exec_ctrl;
3886 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3888 struct vcpu_vmx *vmx = to_vmx(vcpu);
3890 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3891 if (cpu_has_secondary_exec_ctrls()) {
3892 if (kvm_vcpu_apicv_active(vcpu))
3893 secondary_exec_controls_setbit(vmx,
3894 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3895 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3897 secondary_exec_controls_clearbit(vmx,
3898 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3899 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3902 if (cpu_has_vmx_msr_bitmap())
3903 vmx_update_msr_bitmap(vcpu);
3906 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3908 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3910 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3911 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3913 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3914 exec_control &= ~CPU_BASED_TPR_SHADOW;
3915 #ifdef CONFIG_X86_64
3916 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3917 CPU_BASED_CR8_LOAD_EXITING;
3921 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3922 CPU_BASED_CR3_LOAD_EXITING |
3923 CPU_BASED_INVLPG_EXITING;
3924 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3925 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3926 CPU_BASED_MONITOR_EXITING);
3927 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3928 exec_control &= ~CPU_BASED_HLT_EXITING;
3929 return exec_control;
3933 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3935 struct kvm_vcpu *vcpu = &vmx->vcpu;
3937 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3939 if (pt_mode == PT_MODE_SYSTEM)
3940 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3941 if (!cpu_need_virtualize_apic_accesses(vcpu))
3942 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3944 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3946 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3947 enable_unrestricted_guest = 0;
3949 if (!enable_unrestricted_guest)
3950 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3951 if (kvm_pause_in_guest(vmx->vcpu.kvm))
3952 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3953 if (!kvm_vcpu_apicv_active(vcpu))
3954 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3955 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3956 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3958 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3959 * in vmx_set_cr4. */
3960 exec_control &= ~SECONDARY_EXEC_DESC;
3962 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3964 We can NOT enable shadow_vmcs here because we don't have yet
3967 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
3970 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
3972 if (vmx_xsaves_supported()) {
3973 /* Exposing XSAVES only when XSAVE is exposed */
3974 bool xsaves_enabled =
3975 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3976 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3978 if (!xsaves_enabled)
3979 exec_control &= ~SECONDARY_EXEC_XSAVES;
3983 vmx->nested.msrs.secondary_ctls_high |=
3984 SECONDARY_EXEC_XSAVES;
3986 vmx->nested.msrs.secondary_ctls_high &=
3987 ~SECONDARY_EXEC_XSAVES;
3991 if (vmx_rdtscp_supported()) {
3992 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3993 if (!rdtscp_enabled)
3994 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3998 vmx->nested.msrs.secondary_ctls_high |=
3999 SECONDARY_EXEC_RDTSCP;
4001 vmx->nested.msrs.secondary_ctls_high &=
4002 ~SECONDARY_EXEC_RDTSCP;
4006 if (vmx_invpcid_supported()) {
4007 /* Exposing INVPCID only when PCID is exposed */
4008 bool invpcid_enabled =
4009 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
4010 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
4012 if (!invpcid_enabled) {
4013 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4014 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4018 if (invpcid_enabled)
4019 vmx->nested.msrs.secondary_ctls_high |=
4020 SECONDARY_EXEC_ENABLE_INVPCID;
4022 vmx->nested.msrs.secondary_ctls_high &=
4023 ~SECONDARY_EXEC_ENABLE_INVPCID;
4027 if (vmx_rdrand_supported()) {
4028 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
4030 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
4034 vmx->nested.msrs.secondary_ctls_high |=
4035 SECONDARY_EXEC_RDRAND_EXITING;
4037 vmx->nested.msrs.secondary_ctls_high &=
4038 ~SECONDARY_EXEC_RDRAND_EXITING;
4042 if (vmx_rdseed_supported()) {
4043 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4045 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4049 vmx->nested.msrs.secondary_ctls_high |=
4050 SECONDARY_EXEC_RDSEED_EXITING;
4052 vmx->nested.msrs.secondary_ctls_high &=
4053 ~SECONDARY_EXEC_RDSEED_EXITING;
4057 vmx->secondary_exec_control = exec_control;
4060 static void ept_set_mmio_spte_mask(void)
4063 * EPT Misconfigurations can be generated if the value of bits 2:0
4064 * of an EPT paging-structure entry is 110b (write/execute).
4066 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4067 VMX_EPT_MISCONFIG_WX_VALUE, 0);
4070 #define VMX_XSS_EXIT_BITMAP 0
4073 * Sets up the vmcs for emulated real mode.
4075 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4080 nested_vmx_vcpu_setup();
4082 if (cpu_has_vmx_msr_bitmap())
4083 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4085 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4088 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4089 vmx->hv_deadline_tsc = -1;
4091 exec_controls_set(vmx, vmx_exec_control(vmx));
4093 if (cpu_has_secondary_exec_ctrls()) {
4094 vmx_compute_secondary_exec_control(vmx);
4095 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4098 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4099 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4100 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4101 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4102 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4104 vmcs_write16(GUEST_INTR_STATUS, 0);
4106 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4107 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4110 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4111 vmcs_write32(PLE_GAP, ple_gap);
4112 vmx->ple_window = ple_window;
4113 vmx->ple_window_dirty = true;
4116 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4117 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4118 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4120 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4121 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4122 vmx_set_constant_host_state(vmx);
4123 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4124 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4126 if (cpu_has_vmx_vmfunc())
4127 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4129 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4130 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4131 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4132 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4133 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4135 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4136 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4138 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4139 u32 index = vmx_msr_index[i];
4140 u32 data_low, data_high;
4143 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4145 if (wrmsr_safe(index, data_low, data_high) < 0)
4147 vmx->guest_msrs[j].index = i;
4148 vmx->guest_msrs[j].data = 0;
4149 vmx->guest_msrs[j].mask = -1ull;
4153 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4155 /* 22.2.1, 20.8.1 */
4156 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4158 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4159 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4161 set_cr4_guest_host_mask(vmx);
4163 if (vmx_xsaves_supported())
4164 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4167 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4168 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4171 if (cpu_has_vmx_encls_vmexit())
4172 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4174 if (pt_mode == PT_MODE_HOST_GUEST) {
4175 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4176 /* Bit[6~0] are forced to 1, writes are ignored. */
4177 vmx->pt_desc.guest.output_mask = 0x7F;
4178 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4182 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4184 struct vcpu_vmx *vmx = to_vmx(vcpu);
4185 struct msr_data apic_base_msr;
4188 vmx->rmode.vm86_active = 0;
4191 vcpu->arch.microcode_version = 0x100000000ULL;
4192 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4193 vmx->hv_deadline_tsc = -1;
4194 kvm_set_cr8(vcpu, 0);
4197 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4198 MSR_IA32_APICBASE_ENABLE;
4199 if (kvm_vcpu_is_reset_bsp(vcpu))
4200 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4201 apic_base_msr.host_initiated = true;
4202 kvm_set_apic_base(vcpu, &apic_base_msr);
4205 vmx_segment_cache_clear(vmx);
4207 seg_setup(VCPU_SREG_CS);
4208 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4209 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4211 seg_setup(VCPU_SREG_DS);
4212 seg_setup(VCPU_SREG_ES);
4213 seg_setup(VCPU_SREG_FS);
4214 seg_setup(VCPU_SREG_GS);
4215 seg_setup(VCPU_SREG_SS);
4217 vmcs_write16(GUEST_TR_SELECTOR, 0);
4218 vmcs_writel(GUEST_TR_BASE, 0);
4219 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4220 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4222 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4223 vmcs_writel(GUEST_LDTR_BASE, 0);
4224 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4225 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4228 vmcs_write32(GUEST_SYSENTER_CS, 0);
4229 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4230 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4231 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4234 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4235 kvm_rip_write(vcpu, 0xfff0);
4237 vmcs_writel(GUEST_GDTR_BASE, 0);
4238 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4240 vmcs_writel(GUEST_IDTR_BASE, 0);
4241 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4243 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4244 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4245 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4246 if (kvm_mpx_supported())
4247 vmcs_write64(GUEST_BNDCFGS, 0);
4251 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4253 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4254 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4255 if (cpu_need_tpr_shadow(vcpu))
4256 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4257 __pa(vcpu->arch.apic->regs));
4258 vmcs_write32(TPR_THRESHOLD, 0);
4261 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4264 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4266 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4267 vmx->vcpu.arch.cr0 = cr0;
4268 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4269 vmx_set_cr4(vcpu, 0);
4270 vmx_set_efer(vcpu, 0);
4272 update_exception_bitmap(vcpu);
4274 vpid_sync_context(vmx->vpid);
4276 vmx_clear_hlt(vcpu);
4279 static void enable_irq_window(struct kvm_vcpu *vcpu)
4281 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4284 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4287 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4288 enable_irq_window(vcpu);
4292 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4295 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4297 struct vcpu_vmx *vmx = to_vmx(vcpu);
4299 int irq = vcpu->arch.interrupt.nr;
4301 trace_kvm_inj_virq(irq);
4303 ++vcpu->stat.irq_injections;
4304 if (vmx->rmode.vm86_active) {
4306 if (vcpu->arch.interrupt.soft)
4307 inc_eip = vcpu->arch.event_exit_inst_len;
4308 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4311 intr = irq | INTR_INFO_VALID_MASK;
4312 if (vcpu->arch.interrupt.soft) {
4313 intr |= INTR_TYPE_SOFT_INTR;
4314 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4315 vmx->vcpu.arch.event_exit_inst_len);
4317 intr |= INTR_TYPE_EXT_INTR;
4318 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4320 vmx_clear_hlt(vcpu);
4323 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4325 struct vcpu_vmx *vmx = to_vmx(vcpu);
4329 * Tracking the NMI-blocked state in software is built upon
4330 * finding the next open IRQ window. This, in turn, depends on
4331 * well-behaving guests: They have to keep IRQs disabled at
4332 * least as long as the NMI handler runs. Otherwise we may
4333 * cause NMI nesting, maybe breaking the guest. But as this is
4334 * highly unlikely, we can live with the residual risk.
4336 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4337 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4340 ++vcpu->stat.nmi_injections;
4341 vmx->loaded_vmcs->nmi_known_unmasked = false;
4343 if (vmx->rmode.vm86_active) {
4344 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4348 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4349 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4351 vmx_clear_hlt(vcpu);
4354 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4356 struct vcpu_vmx *vmx = to_vmx(vcpu);
4360 return vmx->loaded_vmcs->soft_vnmi_blocked;
4361 if (vmx->loaded_vmcs->nmi_known_unmasked)
4363 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4364 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4368 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4370 struct vcpu_vmx *vmx = to_vmx(vcpu);
4373 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4374 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4375 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4378 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4380 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4381 GUEST_INTR_STATE_NMI);
4383 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4384 GUEST_INTR_STATE_NMI);
4388 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4390 if (to_vmx(vcpu)->nested.nested_run_pending)
4394 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4397 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4398 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4399 | GUEST_INTR_STATE_NMI));
4402 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4404 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4405 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4406 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4407 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4410 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4414 if (enable_unrestricted_guest)
4417 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4421 to_kvm_vmx(kvm)->tss_addr = addr;
4422 return init_rmode_tss(kvm);
4425 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4427 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4431 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4436 * Update instruction length as we may reinject the exception
4437 * from user space while in guest debugging mode.
4439 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4440 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4441 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4445 if (vcpu->guest_debug &
4446 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4463 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4464 int vec, u32 err_code)
4467 * Instruction with address size override prefix opcode 0x67
4468 * Cause the #SS fault with 0 error code in VM86 mode.
4470 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4471 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4472 if (vcpu->arch.halt_request) {
4473 vcpu->arch.halt_request = 0;
4474 return kvm_vcpu_halt(vcpu);
4482 * Forward all other exceptions that are valid in real mode.
4483 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4484 * the required debugging infrastructure rework.
4486 kvm_queue_exception(vcpu, vec);
4491 * Trigger machine check on the host. We assume all the MSRs are already set up
4492 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4493 * We pass a fake environment to the machine check handler because we want
4494 * the guest to be always treated like user space, no matter what context
4495 * it used internally.
4497 static void kvm_machine_check(void)
4499 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4500 struct pt_regs regs = {
4501 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4502 .flags = X86_EFLAGS_IF,
4505 do_machine_check(®s, 0);
4509 static int handle_machine_check(struct kvm_vcpu *vcpu)
4511 /* handled by vmx_vcpu_run() */
4515 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4517 struct vcpu_vmx *vmx = to_vmx(vcpu);
4518 struct kvm_run *kvm_run = vcpu->run;
4519 u32 intr_info, ex_no, error_code;
4520 unsigned long cr2, rip, dr6;
4523 vect_info = vmx->idt_vectoring_info;
4524 intr_info = vmx->exit_intr_info;
4526 if (is_machine_check(intr_info) || is_nmi(intr_info))
4527 return 1; /* handled by handle_exception_nmi_irqoff() */
4529 if (is_invalid_opcode(intr_info))
4530 return handle_ud(vcpu);
4533 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4534 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4536 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4537 WARN_ON_ONCE(!enable_vmware_backdoor);
4540 * VMware backdoor emulation on #GP interception only handles
4541 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4542 * error code on #GP.
4545 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4548 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP) !=
4553 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4554 * MMIO, it is better to report an internal error.
4555 * See the comments in vmx_handle_exit.
4557 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4558 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4559 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4560 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4561 vcpu->run->internal.ndata = 3;
4562 vcpu->run->internal.data[0] = vect_info;
4563 vcpu->run->internal.data[1] = intr_info;
4564 vcpu->run->internal.data[2] = error_code;
4568 if (is_page_fault(intr_info)) {
4569 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4570 /* EPT won't cause page fault directly */
4571 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4572 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4575 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4577 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4578 return handle_rmode_exception(vcpu, ex_no, error_code);
4582 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4585 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4586 if (!(vcpu->guest_debug &
4587 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4588 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4589 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4590 if (is_icebp(intr_info))
4591 skip_emulated_instruction(vcpu);
4593 kvm_queue_exception(vcpu, DB_VECTOR);
4596 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4597 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4601 * Update instruction length as we may reinject #BP from
4602 * user space while in guest debugging mode. Reading it for
4603 * #DB as well causes no harm, it is not used in that case.
4605 vmx->vcpu.arch.event_exit_inst_len =
4606 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4607 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4608 rip = kvm_rip_read(vcpu);
4609 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4610 kvm_run->debug.arch.exception = ex_no;
4613 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4614 kvm_run->ex.exception = ex_no;
4615 kvm_run->ex.error_code = error_code;
4621 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4623 ++vcpu->stat.irq_exits;
4627 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4629 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4630 vcpu->mmio_needed = 0;
4634 static int handle_io(struct kvm_vcpu *vcpu)
4636 unsigned long exit_qualification;
4637 int size, in, string;
4640 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4641 string = (exit_qualification & 16) != 0;
4643 ++vcpu->stat.io_exits;
4646 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4648 port = exit_qualification >> 16;
4649 size = (exit_qualification & 7) + 1;
4650 in = (exit_qualification & 8) != 0;
4652 return kvm_fast_pio(vcpu, size, port, in);
4656 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4659 * Patch in the VMCALL instruction:
4661 hypercall[0] = 0x0f;
4662 hypercall[1] = 0x01;
4663 hypercall[2] = 0xc1;
4666 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4667 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4669 if (is_guest_mode(vcpu)) {
4670 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4671 unsigned long orig_val = val;
4674 * We get here when L2 changed cr0 in a way that did not change
4675 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4676 * but did change L0 shadowed bits. So we first calculate the
4677 * effective cr0 value that L1 would like to write into the
4678 * hardware. It consists of the L2-owned bits from the new
4679 * value combined with the L1-owned bits from L1's guest_cr0.
4681 val = (val & ~vmcs12->cr0_guest_host_mask) |
4682 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4684 if (!nested_guest_cr0_valid(vcpu, val))
4687 if (kvm_set_cr0(vcpu, val))
4689 vmcs_writel(CR0_READ_SHADOW, orig_val);
4692 if (to_vmx(vcpu)->nested.vmxon &&
4693 !nested_host_cr0_valid(vcpu, val))
4696 return kvm_set_cr0(vcpu, val);
4700 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4702 if (is_guest_mode(vcpu)) {
4703 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4704 unsigned long orig_val = val;
4706 /* analogously to handle_set_cr0 */
4707 val = (val & ~vmcs12->cr4_guest_host_mask) |
4708 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4709 if (kvm_set_cr4(vcpu, val))
4711 vmcs_writel(CR4_READ_SHADOW, orig_val);
4714 return kvm_set_cr4(vcpu, val);
4717 static int handle_desc(struct kvm_vcpu *vcpu)
4719 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4720 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4723 static int handle_cr(struct kvm_vcpu *vcpu)
4725 unsigned long exit_qualification, val;
4731 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4732 cr = exit_qualification & 15;
4733 reg = (exit_qualification >> 8) & 15;
4734 switch ((exit_qualification >> 4) & 3) {
4735 case 0: /* mov to cr */
4736 val = kvm_register_readl(vcpu, reg);
4737 trace_kvm_cr_write(cr, val);
4740 err = handle_set_cr0(vcpu, val);
4741 return kvm_complete_insn_gp(vcpu, err);
4743 WARN_ON_ONCE(enable_unrestricted_guest);
4744 err = kvm_set_cr3(vcpu, val);
4745 return kvm_complete_insn_gp(vcpu, err);
4747 err = handle_set_cr4(vcpu, val);
4748 return kvm_complete_insn_gp(vcpu, err);
4750 u8 cr8_prev = kvm_get_cr8(vcpu);
4752 err = kvm_set_cr8(vcpu, cr8);
4753 ret = kvm_complete_insn_gp(vcpu, err);
4754 if (lapic_in_kernel(vcpu))
4756 if (cr8_prev <= cr8)
4759 * TODO: we might be squashing a
4760 * KVM_GUESTDBG_SINGLESTEP-triggered
4761 * KVM_EXIT_DEBUG here.
4763 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4769 WARN_ONCE(1, "Guest should always own CR0.TS");
4770 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4771 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4772 return kvm_skip_emulated_instruction(vcpu);
4773 case 1: /*mov from cr*/
4776 WARN_ON_ONCE(enable_unrestricted_guest);
4777 val = kvm_read_cr3(vcpu);
4778 kvm_register_write(vcpu, reg, val);
4779 trace_kvm_cr_read(cr, val);
4780 return kvm_skip_emulated_instruction(vcpu);
4782 val = kvm_get_cr8(vcpu);
4783 kvm_register_write(vcpu, reg, val);
4784 trace_kvm_cr_read(cr, val);
4785 return kvm_skip_emulated_instruction(vcpu);
4789 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4790 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4791 kvm_lmsw(vcpu, val);
4793 return kvm_skip_emulated_instruction(vcpu);
4797 vcpu->run->exit_reason = 0;
4798 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4799 (int)(exit_qualification >> 4) & 3, cr);
4803 static int handle_dr(struct kvm_vcpu *vcpu)
4805 unsigned long exit_qualification;
4808 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4809 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4811 /* First, if DR does not exist, trigger UD */
4812 if (!kvm_require_dr(vcpu, dr))
4815 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4816 if (!kvm_require_cpl(vcpu, 0))
4818 dr7 = vmcs_readl(GUEST_DR7);
4821 * As the vm-exit takes precedence over the debug trap, we
4822 * need to emulate the latter, either for the host or the
4823 * guest debugging itself.
4825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4826 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4827 vcpu->run->debug.arch.dr7 = dr7;
4828 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4829 vcpu->run->debug.arch.exception = DB_VECTOR;
4830 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4833 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4834 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4835 kvm_queue_exception(vcpu, DB_VECTOR);
4840 if (vcpu->guest_debug == 0) {
4841 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4844 * No more DR vmexits; force a reload of the debug registers
4845 * and reenter on this instruction. The next vmexit will
4846 * retrieve the full state of the debug registers.
4848 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4852 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4853 if (exit_qualification & TYPE_MOV_FROM_DR) {
4856 if (kvm_get_dr(vcpu, dr, &val))
4858 kvm_register_write(vcpu, reg, val);
4860 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4863 return kvm_skip_emulated_instruction(vcpu);
4866 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4868 return vcpu->arch.dr6;
4871 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4875 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4877 get_debugreg(vcpu->arch.db[0], 0);
4878 get_debugreg(vcpu->arch.db[1], 1);
4879 get_debugreg(vcpu->arch.db[2], 2);
4880 get_debugreg(vcpu->arch.db[3], 3);
4881 get_debugreg(vcpu->arch.dr6, 6);
4882 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4884 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4885 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4888 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4890 vmcs_writel(GUEST_DR7, val);
4893 static int handle_cpuid(struct kvm_vcpu *vcpu)
4895 return kvm_emulate_cpuid(vcpu);
4898 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4900 return kvm_emulate_rdmsr(vcpu);
4903 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4905 return kvm_emulate_wrmsr(vcpu);
4908 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4910 kvm_apic_update_ppr(vcpu);
4914 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4916 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4918 kvm_make_request(KVM_REQ_EVENT, vcpu);
4920 ++vcpu->stat.irq_window_exits;
4924 static int handle_halt(struct kvm_vcpu *vcpu)
4926 return kvm_emulate_halt(vcpu);
4929 static int handle_vmcall(struct kvm_vcpu *vcpu)
4931 return kvm_emulate_hypercall(vcpu);
4934 static int handle_invd(struct kvm_vcpu *vcpu)
4936 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4939 static int handle_invlpg(struct kvm_vcpu *vcpu)
4941 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4943 kvm_mmu_invlpg(vcpu, exit_qualification);
4944 return kvm_skip_emulated_instruction(vcpu);
4947 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4951 err = kvm_rdpmc(vcpu);
4952 return kvm_complete_insn_gp(vcpu, err);
4955 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4957 return kvm_emulate_wbinvd(vcpu);
4960 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4962 u64 new_bv = kvm_read_edx_eax(vcpu);
4963 u32 index = kvm_rcx_read(vcpu);
4965 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4966 return kvm_skip_emulated_instruction(vcpu);
4970 static int handle_xsaves(struct kvm_vcpu *vcpu)
4972 kvm_skip_emulated_instruction(vcpu);
4973 WARN(1, "this should never happen\n");
4977 static int handle_xrstors(struct kvm_vcpu *vcpu)
4979 kvm_skip_emulated_instruction(vcpu);
4980 WARN(1, "this should never happen\n");
4984 static int handle_apic_access(struct kvm_vcpu *vcpu)
4986 if (likely(fasteoi)) {
4987 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4988 int access_type, offset;
4990 access_type = exit_qualification & APIC_ACCESS_TYPE;
4991 offset = exit_qualification & APIC_ACCESS_OFFSET;
4993 * Sane guest uses MOV to write EOI, with written value
4994 * not cared. So make a short-circuit here by avoiding
4995 * heavy instruction emulation.
4997 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4998 (offset == APIC_EOI)) {
4999 kvm_lapic_set_eoi(vcpu);
5000 return kvm_skip_emulated_instruction(vcpu);
5003 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
5006 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5008 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5009 int vector = exit_qualification & 0xff;
5011 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5012 kvm_apic_set_eoi_accelerated(vcpu, vector);
5016 static int handle_apic_write(struct kvm_vcpu *vcpu)
5018 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5019 u32 offset = exit_qualification & 0xfff;
5021 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5022 kvm_apic_write_nodecode(vcpu, offset);
5026 static int handle_task_switch(struct kvm_vcpu *vcpu)
5028 struct vcpu_vmx *vmx = to_vmx(vcpu);
5029 unsigned long exit_qualification;
5030 bool has_error_code = false;
5033 int reason, type, idt_v, idt_index;
5035 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5036 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5037 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5039 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5041 reason = (u32)exit_qualification >> 30;
5042 if (reason == TASK_SWITCH_GATE && idt_v) {
5044 case INTR_TYPE_NMI_INTR:
5045 vcpu->arch.nmi_injected = false;
5046 vmx_set_nmi_mask(vcpu, true);
5048 case INTR_TYPE_EXT_INTR:
5049 case INTR_TYPE_SOFT_INTR:
5050 kvm_clear_interrupt_queue(vcpu);
5052 case INTR_TYPE_HARD_EXCEPTION:
5053 if (vmx->idt_vectoring_info &
5054 VECTORING_INFO_DELIVER_CODE_MASK) {
5055 has_error_code = true;
5057 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5060 case INTR_TYPE_SOFT_EXCEPTION:
5061 kvm_clear_exception_queue(vcpu);
5067 tss_selector = exit_qualification;
5069 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5070 type != INTR_TYPE_EXT_INTR &&
5071 type != INTR_TYPE_NMI_INTR))
5072 skip_emulated_instruction(vcpu);
5075 * TODO: What about debug traps on tss switch?
5076 * Are we supposed to inject them and update dr6?
5078 return kvm_task_switch(vcpu, tss_selector,
5079 type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5080 reason, has_error_code, error_code) != EMULATE_USER_EXIT;
5083 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5085 unsigned long exit_qualification;
5089 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5092 * EPT violation happened while executing iret from NMI,
5093 * "blocked by NMI" bit has to be set before next VM entry.
5094 * There are errata that may cause this bit to not be set:
5097 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5099 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5100 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5102 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5103 trace_kvm_page_fault(gpa, exit_qualification);
5105 /* Is it a read fault? */
5106 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5107 ? PFERR_USER_MASK : 0;
5108 /* Is it a write fault? */
5109 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5110 ? PFERR_WRITE_MASK : 0;
5111 /* Is it a fetch fault? */
5112 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5113 ? PFERR_FETCH_MASK : 0;
5114 /* ept page table entry is present? */
5115 error_code |= (exit_qualification &
5116 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5117 EPT_VIOLATION_EXECUTABLE))
5118 ? PFERR_PRESENT_MASK : 0;
5120 error_code |= (exit_qualification & 0x100) != 0 ?
5121 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5123 vcpu->arch.exit_qualification = exit_qualification;
5124 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5127 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5132 * A nested guest cannot optimize MMIO vmexits, because we have an
5133 * nGPA here instead of the required GPA.
5135 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5136 if (!is_guest_mode(vcpu) &&
5137 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5138 trace_kvm_fast_mmio(gpa);
5140 * Doing kvm_skip_emulated_instruction() depends on undefined
5141 * behavior: Intel's manual doesn't mandate
5142 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5143 * occurs and while on real hardware it was observed to be set,
5144 * other hypervisors (namely Hyper-V) don't set it, we end up
5145 * advancing IP with some random value. Disable fast mmio when
5146 * running nested and keep it for real hardware in hope that
5147 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5149 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5150 return kvm_skip_emulated_instruction(vcpu);
5152 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
5156 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5159 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5161 WARN_ON_ONCE(!enable_vnmi);
5162 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5163 ++vcpu->stat.nmi_window_exits;
5164 kvm_make_request(KVM_REQ_EVENT, vcpu);
5169 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5171 struct vcpu_vmx *vmx = to_vmx(vcpu);
5172 enum emulation_result err = EMULATE_DONE;
5174 bool intr_window_requested;
5175 unsigned count = 130;
5178 * We should never reach the point where we are emulating L2
5179 * due to invalid guest state as that means we incorrectly
5180 * allowed a nested VMEntry with an invalid vmcs12.
5182 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5184 intr_window_requested = exec_controls_get(vmx) &
5185 CPU_BASED_VIRTUAL_INTR_PENDING;
5187 while (vmx->emulation_required && count-- != 0) {
5188 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5189 return handle_interrupt_window(&vmx->vcpu);
5191 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5194 err = kvm_emulate_instruction(vcpu, 0);
5196 if (err == EMULATE_USER_EXIT) {
5201 if (err != EMULATE_DONE)
5202 goto emulation_error;
5204 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5205 vcpu->arch.exception.pending)
5206 goto emulation_error;
5208 if (vcpu->arch.halt_request) {
5209 vcpu->arch.halt_request = 0;
5210 ret = kvm_vcpu_halt(vcpu);
5214 if (signal_pending(current))
5224 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5225 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5226 vcpu->run->internal.ndata = 0;
5230 static void grow_ple_window(struct kvm_vcpu *vcpu)
5232 struct vcpu_vmx *vmx = to_vmx(vcpu);
5233 unsigned int old = vmx->ple_window;
5235 vmx->ple_window = __grow_ple_window(old, ple_window,
5239 if (vmx->ple_window != old) {
5240 vmx->ple_window_dirty = true;
5241 trace_kvm_ple_window_update(vcpu->vcpu_id,
5242 vmx->ple_window, old);
5246 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5248 struct vcpu_vmx *vmx = to_vmx(vcpu);
5249 unsigned int old = vmx->ple_window;
5251 vmx->ple_window = __shrink_ple_window(old, ple_window,
5255 if (vmx->ple_window != old) {
5256 vmx->ple_window_dirty = true;
5257 trace_kvm_ple_window_update(vcpu->vcpu_id,
5258 vmx->ple_window, old);
5263 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5265 static void wakeup_handler(void)
5267 struct kvm_vcpu *vcpu;
5268 int cpu = smp_processor_id();
5270 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5271 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5272 blocked_vcpu_list) {
5273 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5275 if (pi_test_on(pi_desc) == 1)
5276 kvm_vcpu_kick(vcpu);
5278 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5281 static void vmx_enable_tdp(void)
5283 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5284 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5285 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5286 0ull, VMX_EPT_EXECUTABLE_MASK,
5287 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5288 VMX_EPT_RWX_MASK, 0ull);
5290 ept_set_mmio_spte_mask();
5295 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5296 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5298 static int handle_pause(struct kvm_vcpu *vcpu)
5300 if (!kvm_pause_in_guest(vcpu->kvm))
5301 grow_ple_window(vcpu);
5304 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5305 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5306 * never set PAUSE_EXITING and just set PLE if supported,
5307 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5309 kvm_vcpu_on_spin(vcpu, true);
5310 return kvm_skip_emulated_instruction(vcpu);
5313 static int handle_nop(struct kvm_vcpu *vcpu)
5315 return kvm_skip_emulated_instruction(vcpu);
5318 static int handle_mwait(struct kvm_vcpu *vcpu)
5320 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5321 return handle_nop(vcpu);
5324 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5326 kvm_queue_exception(vcpu, UD_VECTOR);
5330 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5335 static int handle_monitor(struct kvm_vcpu *vcpu)
5337 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5338 return handle_nop(vcpu);
5341 static int handle_invpcid(struct kvm_vcpu *vcpu)
5343 u32 vmx_instruction_info;
5347 struct x86_exception e;
5349 unsigned long roots_to_free = 0;
5355 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5356 kvm_queue_exception(vcpu, UD_VECTOR);
5360 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5361 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5364 kvm_inject_gp(vcpu, 0);
5368 /* According to the Intel instruction reference, the memory operand
5369 * is read even if it isn't needed (e.g., for type==all)
5371 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5372 vmx_instruction_info, false,
5373 sizeof(operand), &gva))
5376 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5377 kvm_inject_page_fault(vcpu, &e);
5381 if (operand.pcid >> 12 != 0) {
5382 kvm_inject_gp(vcpu, 0);
5386 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5389 case INVPCID_TYPE_INDIV_ADDR:
5390 if ((!pcid_enabled && (operand.pcid != 0)) ||
5391 is_noncanonical_address(operand.gla, vcpu)) {
5392 kvm_inject_gp(vcpu, 0);
5395 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5396 return kvm_skip_emulated_instruction(vcpu);
5398 case INVPCID_TYPE_SINGLE_CTXT:
5399 if (!pcid_enabled && (operand.pcid != 0)) {
5400 kvm_inject_gp(vcpu, 0);
5404 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5405 kvm_mmu_sync_roots(vcpu);
5406 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5409 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5410 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5412 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5414 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5416 * If neither the current cr3 nor any of the prev_roots use the
5417 * given PCID, then nothing needs to be done here because a
5418 * resync will happen anyway before switching to any other CR3.
5421 return kvm_skip_emulated_instruction(vcpu);
5423 case INVPCID_TYPE_ALL_NON_GLOBAL:
5425 * Currently, KVM doesn't mark global entries in the shadow
5426 * page tables, so a non-global flush just degenerates to a
5427 * global flush. If needed, we could optimize this later by
5428 * keeping track of global entries in shadow page tables.
5432 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5433 kvm_mmu_unload(vcpu);
5434 return kvm_skip_emulated_instruction(vcpu);
5437 BUG(); /* We have already checked above that type <= 3 */
5441 static int handle_pml_full(struct kvm_vcpu *vcpu)
5443 unsigned long exit_qualification;
5445 trace_kvm_pml_full(vcpu->vcpu_id);
5447 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5450 * PML buffer FULL happened while executing iret from NMI,
5451 * "blocked by NMI" bit has to be set before next VM entry.
5453 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5455 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5456 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5457 GUEST_INTR_STATE_NMI);
5460 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5461 * here.., and there's no userspace involvement needed for PML.
5466 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5468 struct vcpu_vmx *vmx = to_vmx(vcpu);
5470 if (!vmx->req_immediate_exit &&
5471 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5472 kvm_lapic_expired_hv_timer(vcpu);
5478 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5479 * are overwritten by nested_vmx_setup() when nested=1.
5481 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5483 kvm_queue_exception(vcpu, UD_VECTOR);
5487 static int handle_encls(struct kvm_vcpu *vcpu)
5490 * SGX virtualization is not yet supported. There is no software
5491 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5492 * to prevent the guest from executing ENCLS.
5494 kvm_queue_exception(vcpu, UD_VECTOR);
5499 * The exit handlers return 1 if the exit was handled fully and guest execution
5500 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5501 * to be done to userspace and return 0.
5503 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5504 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5505 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5506 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5507 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5508 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5509 [EXIT_REASON_CR_ACCESS] = handle_cr,
5510 [EXIT_REASON_DR_ACCESS] = handle_dr,
5511 [EXIT_REASON_CPUID] = handle_cpuid,
5512 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5513 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5514 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5515 [EXIT_REASON_HLT] = handle_halt,
5516 [EXIT_REASON_INVD] = handle_invd,
5517 [EXIT_REASON_INVLPG] = handle_invlpg,
5518 [EXIT_REASON_RDPMC] = handle_rdpmc,
5519 [EXIT_REASON_VMCALL] = handle_vmcall,
5520 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5521 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5522 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5523 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5524 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5525 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5526 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5527 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5528 [EXIT_REASON_VMON] = handle_vmx_instruction,
5529 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5530 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5531 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5532 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5533 [EXIT_REASON_WBINVD] = handle_wbinvd,
5534 [EXIT_REASON_XSETBV] = handle_xsetbv,
5535 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5536 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5537 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5538 [EXIT_REASON_LDTR_TR] = handle_desc,
5539 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5540 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5541 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5542 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5543 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5544 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5545 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5546 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5547 [EXIT_REASON_RDRAND] = handle_invalid_op,
5548 [EXIT_REASON_RDSEED] = handle_invalid_op,
5549 [EXIT_REASON_XSAVES] = handle_xsaves,
5550 [EXIT_REASON_XRSTORS] = handle_xrstors,
5551 [EXIT_REASON_PML_FULL] = handle_pml_full,
5552 [EXIT_REASON_INVPCID] = handle_invpcid,
5553 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5554 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5555 [EXIT_REASON_ENCLS] = handle_encls,
5558 static const int kvm_vmx_max_exit_handlers =
5559 ARRAY_SIZE(kvm_vmx_exit_handlers);
5561 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5563 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5564 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5567 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5570 __free_page(vmx->pml_pg);
5575 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5577 struct vcpu_vmx *vmx = to_vmx(vcpu);
5581 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5583 /* Do nothing if PML buffer is empty */
5584 if (pml_idx == (PML_ENTITY_NUM - 1))
5587 /* PML index always points to next available PML buffer entity */
5588 if (pml_idx >= PML_ENTITY_NUM)
5593 pml_buf = page_address(vmx->pml_pg);
5594 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5597 gpa = pml_buf[pml_idx];
5598 WARN_ON(gpa & (PAGE_SIZE - 1));
5599 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5602 /* reset PML index */
5603 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5607 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5608 * Called before reporting dirty_bitmap to userspace.
5610 static void kvm_flush_pml_buffers(struct kvm *kvm)
5613 struct kvm_vcpu *vcpu;
5615 * We only need to kick vcpu out of guest mode here, as PML buffer
5616 * is flushed at beginning of all VMEXITs, and it's obvious that only
5617 * vcpus running in guest are possible to have unflushed GPAs in PML
5620 kvm_for_each_vcpu(i, vcpu, kvm)
5621 kvm_vcpu_kick(vcpu);
5624 static void vmx_dump_sel(char *name, uint32_t sel)
5626 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5627 name, vmcs_read16(sel),
5628 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5629 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5630 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5633 static void vmx_dump_dtsel(char *name, uint32_t limit)
5635 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5636 name, vmcs_read32(limit),
5637 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5640 void dump_vmcs(void)
5642 u32 vmentry_ctl, vmexit_ctl;
5643 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5648 if (!dump_invalid_vmcs) {
5649 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5653 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5654 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5655 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5656 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5657 cr4 = vmcs_readl(GUEST_CR4);
5658 efer = vmcs_read64(GUEST_IA32_EFER);
5659 secondary_exec_control = 0;
5660 if (cpu_has_secondary_exec_ctrls())
5661 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5663 pr_err("*** Guest State ***\n");
5664 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5665 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5666 vmcs_readl(CR0_GUEST_HOST_MASK));
5667 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5668 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5669 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5670 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5671 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5673 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5674 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5675 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5676 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5678 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5679 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5680 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5681 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5682 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5683 vmcs_readl(GUEST_SYSENTER_ESP),
5684 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5685 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5686 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5687 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5688 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5689 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5690 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5691 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5692 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5693 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5694 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5695 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5696 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5697 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5698 efer, vmcs_read64(GUEST_IA32_PAT));
5699 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5700 vmcs_read64(GUEST_IA32_DEBUGCTL),
5701 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5702 if (cpu_has_load_perf_global_ctrl() &&
5703 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5704 pr_err("PerfGlobCtl = 0x%016llx\n",
5705 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5706 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5707 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5708 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5709 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5710 vmcs_read32(GUEST_ACTIVITY_STATE));
5711 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5712 pr_err("InterruptStatus = %04x\n",
5713 vmcs_read16(GUEST_INTR_STATUS));
5715 pr_err("*** Host State ***\n");
5716 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5717 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5718 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5719 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5720 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5721 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5722 vmcs_read16(HOST_TR_SELECTOR));
5723 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5724 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5725 vmcs_readl(HOST_TR_BASE));
5726 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5727 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5728 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5729 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5730 vmcs_readl(HOST_CR4));
5731 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5732 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5733 vmcs_read32(HOST_IA32_SYSENTER_CS),
5734 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5735 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5736 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5737 vmcs_read64(HOST_IA32_EFER),
5738 vmcs_read64(HOST_IA32_PAT));
5739 if (cpu_has_load_perf_global_ctrl() &&
5740 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5741 pr_err("PerfGlobCtl = 0x%016llx\n",
5742 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5744 pr_err("*** Control State ***\n");
5745 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5746 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5747 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5748 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5749 vmcs_read32(EXCEPTION_BITMAP),
5750 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5751 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5752 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5753 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5754 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5755 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5756 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5757 vmcs_read32(VM_EXIT_INTR_INFO),
5758 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5759 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5760 pr_err(" reason=%08x qualification=%016lx\n",
5761 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5762 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5763 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5764 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5765 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5766 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5767 pr_err("TSC Multiplier = 0x%016llx\n",
5768 vmcs_read64(TSC_MULTIPLIER));
5769 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5770 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5771 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5772 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5774 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5775 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5776 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5777 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5779 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5780 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5781 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5782 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5783 n = vmcs_read32(CR3_TARGET_COUNT);
5784 for (i = 0; i + 1 < n; i += 4)
5785 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5786 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5787 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5789 pr_err("CR3 target%u=%016lx\n",
5790 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5791 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5792 pr_err("PLE Gap=%08x Window=%08x\n",
5793 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5794 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5795 pr_err("Virtual processor ID = 0x%04x\n",
5796 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5800 * The guest has exited. See if we can fix it or if we need userspace
5803 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5805 struct vcpu_vmx *vmx = to_vmx(vcpu);
5806 u32 exit_reason = vmx->exit_reason;
5807 u32 vectoring_info = vmx->idt_vectoring_info;
5809 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5812 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5813 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5814 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5815 * mode as if vcpus is in root mode, the PML buffer must has been
5819 vmx_flush_pml_buffer(vcpu);
5821 /* If guest state is invalid, start emulating */
5822 if (vmx->emulation_required)
5823 return handle_invalid_guest_state(vcpu);
5825 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5826 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5828 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5830 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5831 vcpu->run->fail_entry.hardware_entry_failure_reason
5836 if (unlikely(vmx->fail)) {
5838 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5839 vcpu->run->fail_entry.hardware_entry_failure_reason
5840 = vmcs_read32(VM_INSTRUCTION_ERROR);
5846 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5847 * delivery event since it indicates guest is accessing MMIO.
5848 * The vm-exit can be triggered again after return to guest that
5849 * will cause infinite loop.
5851 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5852 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5853 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5854 exit_reason != EXIT_REASON_PML_FULL &&
5855 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5856 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5857 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5858 vcpu->run->internal.ndata = 3;
5859 vcpu->run->internal.data[0] = vectoring_info;
5860 vcpu->run->internal.data[1] = exit_reason;
5861 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5862 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5863 vcpu->run->internal.ndata++;
5864 vcpu->run->internal.data[3] =
5865 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5870 if (unlikely(!enable_vnmi &&
5871 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5872 if (vmx_interrupt_allowed(vcpu)) {
5873 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5874 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5875 vcpu->arch.nmi_pending) {
5877 * This CPU don't support us in finding the end of an
5878 * NMI-blocked window if the guest runs with IRQs
5879 * disabled. So we pull the trigger after 1 s of
5880 * futile waiting, but inform the user about this.
5882 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5883 "state on VCPU %d after 1 s timeout\n",
5884 __func__, vcpu->vcpu_id);
5885 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5889 if (exit_reason < kvm_vmx_max_exit_handlers
5890 && kvm_vmx_exit_handlers[exit_reason])
5891 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5893 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5896 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5897 vcpu->run->internal.suberror =
5898 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
5899 vcpu->run->internal.ndata = 1;
5900 vcpu->run->internal.data[0] = exit_reason;
5906 * Software based L1D cache flush which is used when microcode providing
5907 * the cache control MSR is not loaded.
5909 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5910 * flush it is required to read in 64 KiB because the replacement algorithm
5911 * is not exactly LRU. This could be sized at runtime via topology
5912 * information but as all relevant affected CPUs have 32KiB L1D cache size
5913 * there is no point in doing so.
5915 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5917 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5920 * This code is only executed when the the flush mode is 'cond' or
5923 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5927 * Clear the per-vcpu flush bit, it gets set again
5928 * either from vcpu_run() or from one of the unsafe
5931 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5932 vcpu->arch.l1tf_flush_l1d = false;
5935 * Clear the per-cpu flush bit, it gets set again from
5936 * the interrupt handlers.
5938 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5939 kvm_clear_cpu_l1tf_flush_l1d();
5945 vcpu->stat.l1d_flush++;
5947 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5948 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5953 /* First ensure the pages are in the TLB */
5954 "xorl %%eax, %%eax\n"
5955 ".Lpopulate_tlb:\n\t"
5956 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5957 "addl $4096, %%eax\n\t"
5958 "cmpl %%eax, %[size]\n\t"
5959 "jne .Lpopulate_tlb\n\t"
5960 "xorl %%eax, %%eax\n\t"
5962 /* Now fill the cache */
5963 "xorl %%eax, %%eax\n"
5965 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5966 "addl $64, %%eax\n\t"
5967 "cmpl %%eax, %[size]\n\t"
5968 "jne .Lfill_cache\n\t"
5970 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5972 : "eax", "ebx", "ecx", "edx");
5975 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5977 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5979 if (is_guest_mode(vcpu) &&
5980 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5983 if (irr == -1 || tpr < irr) {
5984 vmcs_write32(TPR_THRESHOLD, 0);
5988 vmcs_write32(TPR_THRESHOLD, irr);
5991 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5993 struct vcpu_vmx *vmx = to_vmx(vcpu);
5994 u32 sec_exec_control;
5996 if (!lapic_in_kernel(vcpu))
5999 if (!flexpriority_enabled &&
6000 !cpu_has_vmx_virtualize_x2apic_mode())
6003 /* Postpone execution until vmcs01 is the current VMCS. */
6004 if (is_guest_mode(vcpu)) {
6005 vmx->nested.change_vmcs01_virtual_apic_mode = true;
6009 sec_exec_control = secondary_exec_controls_get(vmx);
6010 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6011 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6013 switch (kvm_get_apic_mode(vcpu)) {
6014 case LAPIC_MODE_INVALID:
6015 WARN_ONCE(true, "Invalid local APIC state");
6016 case LAPIC_MODE_DISABLED:
6018 case LAPIC_MODE_XAPIC:
6019 if (flexpriority_enabled) {
6021 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6022 vmx_flush_tlb(vcpu, true);
6025 case LAPIC_MODE_X2APIC:
6026 if (cpu_has_vmx_virtualize_x2apic_mode())
6028 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6031 secondary_exec_controls_set(vmx, sec_exec_control);
6033 vmx_update_msr_bitmap(vcpu);
6036 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6038 if (!is_guest_mode(vcpu)) {
6039 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6040 vmx_flush_tlb(vcpu, true);
6044 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6052 status = vmcs_read16(GUEST_INTR_STATUS);
6054 if (max_isr != old) {
6056 status |= max_isr << 8;
6057 vmcs_write16(GUEST_INTR_STATUS, status);
6061 static void vmx_set_rvi(int vector)
6069 status = vmcs_read16(GUEST_INTR_STATUS);
6070 old = (u8)status & 0xff;
6071 if ((u8)vector != old) {
6073 status |= (u8)vector;
6074 vmcs_write16(GUEST_INTR_STATUS, status);
6078 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6081 * When running L2, updating RVI is only relevant when
6082 * vmcs12 virtual-interrupt-delivery enabled.
6083 * However, it can be enabled only when L1 also
6084 * intercepts external-interrupts and in that case
6085 * we should not update vmcs02 RVI but instead intercept
6086 * interrupt. Therefore, do nothing when running L2.
6088 if (!is_guest_mode(vcpu))
6089 vmx_set_rvi(max_irr);
6092 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6094 struct vcpu_vmx *vmx = to_vmx(vcpu);
6096 bool max_irr_updated;
6098 WARN_ON(!vcpu->arch.apicv_active);
6099 if (pi_test_on(&vmx->pi_desc)) {
6100 pi_clear_on(&vmx->pi_desc);
6102 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6103 * But on x86 this is just a compiler barrier anyway.
6105 smp_mb__after_atomic();
6107 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6110 * If we are running L2 and L1 has a new pending interrupt
6111 * which can be injected, we should re-evaluate
6112 * what should be done with this new L1 interrupt.
6113 * If L1 intercepts external-interrupts, we should
6114 * exit from L2 to L1. Otherwise, interrupt should be
6115 * delivered directly to L2.
6117 if (is_guest_mode(vcpu) && max_irr_updated) {
6118 if (nested_exit_on_intr(vcpu))
6119 kvm_vcpu_exiting_guest_mode(vcpu);
6121 kvm_make_request(KVM_REQ_EVENT, vcpu);
6124 max_irr = kvm_lapic_find_highest_irr(vcpu);
6126 vmx_hwapic_irr_update(vcpu, max_irr);
6130 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6132 return pi_test_on(vcpu_to_pi_desc(vcpu));
6135 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6137 if (!kvm_vcpu_apicv_active(vcpu))
6140 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6141 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6142 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6143 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6146 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6148 struct vcpu_vmx *vmx = to_vmx(vcpu);
6150 pi_clear_on(&vmx->pi_desc);
6151 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6154 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6156 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6158 /* if exit due to PF check for async PF */
6159 if (is_page_fault(vmx->exit_intr_info))
6160 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6162 /* Handle machine checks before interrupts are enabled */
6163 if (is_machine_check(vmx->exit_intr_info))
6164 kvm_machine_check();
6166 /* We need to handle NMIs before interrupts are enabled */
6167 if (is_nmi(vmx->exit_intr_info)) {
6168 kvm_before_interrupt(&vmx->vcpu);
6170 kvm_after_interrupt(&vmx->vcpu);
6174 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6176 unsigned int vector;
6177 unsigned long entry;
6178 #ifdef CONFIG_X86_64
6184 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6185 if (WARN_ONCE(!is_external_intr(intr_info),
6186 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6189 vector = intr_info & INTR_INFO_VECTOR_MASK;
6190 desc = (gate_desc *)host_idt_base + vector;
6191 entry = gate_offset(desc);
6193 kvm_before_interrupt(vcpu);
6196 #ifdef CONFIG_X86_64
6197 "mov %%" _ASM_SP ", %[sp]\n\t"
6198 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6203 __ASM_SIZE(push) " $%c[cs]\n\t"
6206 #ifdef CONFIG_X86_64
6211 THUNK_TARGET(entry),
6212 [ss]"i"(__KERNEL_DS),
6213 [cs]"i"(__KERNEL_CS)
6216 kvm_after_interrupt(vcpu);
6218 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6220 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6222 struct vcpu_vmx *vmx = to_vmx(vcpu);
6224 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6225 handle_external_interrupt_irqoff(vcpu);
6226 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6227 handle_exception_nmi_irqoff(vmx);
6230 static bool vmx_has_emulated_msr(int index)
6233 case MSR_IA32_SMBASE:
6235 * We cannot do SMM unless we can run the guest in big
6238 return enable_unrestricted_guest || emulate_invalid_guest_state;
6239 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6241 case MSR_AMD64_VIRT_SPEC_CTRL:
6242 /* This is AMD only. */
6249 static bool vmx_pt_supported(void)
6251 return pt_mode == PT_MODE_HOST_GUEST;
6254 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6259 bool idtv_info_valid;
6261 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6264 if (vmx->loaded_vmcs->nmi_known_unmasked)
6267 * Can't use vmx->exit_intr_info since we're not sure what
6268 * the exit reason is.
6270 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6271 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6272 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6274 * SDM 3: 27.7.1.2 (September 2008)
6275 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6276 * a guest IRET fault.
6277 * SDM 3: 23.2.2 (September 2008)
6278 * Bit 12 is undefined in any of the following cases:
6279 * If the VM exit sets the valid bit in the IDT-vectoring
6280 * information field.
6281 * If the VM exit is due to a double fault.
6283 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6284 vector != DF_VECTOR && !idtv_info_valid)
6285 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6286 GUEST_INTR_STATE_NMI);
6288 vmx->loaded_vmcs->nmi_known_unmasked =
6289 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6290 & GUEST_INTR_STATE_NMI);
6291 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6292 vmx->loaded_vmcs->vnmi_blocked_time +=
6293 ktime_to_ns(ktime_sub(ktime_get(),
6294 vmx->loaded_vmcs->entry_time));
6297 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6298 u32 idt_vectoring_info,
6299 int instr_len_field,
6300 int error_code_field)
6304 bool idtv_info_valid;
6306 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6308 vcpu->arch.nmi_injected = false;
6309 kvm_clear_exception_queue(vcpu);
6310 kvm_clear_interrupt_queue(vcpu);
6312 if (!idtv_info_valid)
6315 kvm_make_request(KVM_REQ_EVENT, vcpu);
6317 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6318 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6321 case INTR_TYPE_NMI_INTR:
6322 vcpu->arch.nmi_injected = true;
6324 * SDM 3: 27.7.1.2 (September 2008)
6325 * Clear bit "block by NMI" before VM entry if a NMI
6328 vmx_set_nmi_mask(vcpu, false);
6330 case INTR_TYPE_SOFT_EXCEPTION:
6331 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6333 case INTR_TYPE_HARD_EXCEPTION:
6334 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6335 u32 err = vmcs_read32(error_code_field);
6336 kvm_requeue_exception_e(vcpu, vector, err);
6338 kvm_requeue_exception(vcpu, vector);
6340 case INTR_TYPE_SOFT_INTR:
6341 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6343 case INTR_TYPE_EXT_INTR:
6344 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6351 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6353 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6354 VM_EXIT_INSTRUCTION_LEN,
6355 IDT_VECTORING_ERROR_CODE);
6358 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6360 __vmx_complete_interrupts(vcpu,
6361 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6362 VM_ENTRY_INSTRUCTION_LEN,
6363 VM_ENTRY_EXCEPTION_ERROR_CODE);
6365 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6368 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6371 struct perf_guest_switch_msr *msrs;
6373 msrs = perf_guest_get_msrs(&nr_msrs);
6378 for (i = 0; i < nr_msrs; i++)
6379 if (msrs[i].host == msrs[i].guest)
6380 clear_atomic_switch_msr(vmx, msrs[i].msr);
6382 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6383 msrs[i].host, false);
6386 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6388 struct vcpu_vmx *vmx = to_vmx(vcpu);
6392 if (vmx->req_immediate_exit) {
6393 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6394 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6395 } else if (vmx->hv_deadline_tsc != -1) {
6397 if (vmx->hv_deadline_tsc > tscl)
6398 /* set_hv_timer ensures the delta fits in 32-bits */
6399 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6400 cpu_preemption_timer_multi);
6404 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6405 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6406 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6407 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6408 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6412 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6414 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6415 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6416 vmcs_writel(HOST_RSP, host_rsp);
6420 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6422 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6424 struct vcpu_vmx *vmx = to_vmx(vcpu);
6425 unsigned long cr3, cr4;
6427 /* Record the guest's net vcpu time for enforced NMI injections. */
6428 if (unlikely(!enable_vnmi &&
6429 vmx->loaded_vmcs->soft_vnmi_blocked))
6430 vmx->loaded_vmcs->entry_time = ktime_get();
6432 /* Don't enter VMX if guest state is invalid, let the exit handler
6433 start emulation until we arrive back to a valid state */
6434 if (vmx->emulation_required)
6437 if (vmx->ple_window_dirty) {
6438 vmx->ple_window_dirty = false;
6439 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6442 if (vmx->nested.need_vmcs12_to_shadow_sync)
6443 nested_sync_vmcs12_to_shadow(vcpu);
6445 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6446 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6447 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6448 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6450 cr3 = __get_current_cr3_fast();
6451 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6452 vmcs_writel(HOST_CR3, cr3);
6453 vmx->loaded_vmcs->host_state.cr3 = cr3;
6456 cr4 = cr4_read_shadow();
6457 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6458 vmcs_writel(HOST_CR4, cr4);
6459 vmx->loaded_vmcs->host_state.cr4 = cr4;
6462 /* When single-stepping over STI and MOV SS, we must clear the
6463 * corresponding interruptibility bits in the guest state. Otherwise
6464 * vmentry fails as it then expects bit 14 (BS) in pending debug
6465 * exceptions being set, but that's not correct for the guest debugging
6467 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6468 vmx_set_interrupt_shadow(vcpu, 0);
6470 kvm_load_guest_xcr0(vcpu);
6472 if (static_cpu_has(X86_FEATURE_PKU) &&
6473 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6474 vcpu->arch.pkru != vmx->host_pkru)
6475 __write_pkru(vcpu->arch.pkru);
6477 pt_guest_enter(vmx);
6479 atomic_switch_perf_msrs(vmx);
6481 if (enable_preemption_timer)
6482 vmx_update_hv_timer(vcpu);
6484 if (lapic_in_kernel(vcpu) &&
6485 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6486 kvm_wait_lapic_expire(vcpu);
6489 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6490 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6491 * is no need to worry about the conditional branch over the wrmsr
6492 * being speculatively taken.
6494 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6496 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6497 if (static_branch_unlikely(&vmx_l1d_should_flush))
6498 vmx_l1d_flush(vcpu);
6499 else if (static_branch_unlikely(&mds_user_clear))
6500 mds_clear_cpu_buffers();
6502 if (vcpu->arch.cr2 != read_cr2())
6503 write_cr2(vcpu->arch.cr2);
6505 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6506 vmx->loaded_vmcs->launched);
6508 vcpu->arch.cr2 = read_cr2();
6511 * We do not use IBRS in the kernel. If this vCPU has used the
6512 * SPEC_CTRL MSR it may have left it on; save the value and
6513 * turn it off. This is much more efficient than blindly adding
6514 * it to the atomic save/restore list. Especially as the former
6515 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6517 * For non-nested case:
6518 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6522 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6525 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6526 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6528 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6530 /* All fields are clean at this point */
6531 if (static_branch_unlikely(&enable_evmcs))
6532 current_evmcs->hv_clean_fields |=
6533 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6535 if (static_branch_unlikely(&enable_evmcs))
6536 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6538 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6539 if (vmx->host_debugctlmsr)
6540 update_debugctlmsr(vmx->host_debugctlmsr);
6542 #ifndef CONFIG_X86_64
6544 * The sysexit path does not restore ds/es, so we must set them to
6545 * a reasonable value ourselves.
6547 * We can't defer this to vmx_prepare_switch_to_host() since that
6548 * function may be executed in interrupt context, which saves and
6549 * restore segments around it, nullifying its effect.
6551 loadsegment(ds, __USER_DS);
6552 loadsegment(es, __USER_DS);
6555 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6556 | (1 << VCPU_EXREG_RFLAGS)
6557 | (1 << VCPU_EXREG_PDPTR)
6558 | (1 << VCPU_EXREG_SEGMENTS)
6559 | (1 << VCPU_EXREG_CR3));
6560 vcpu->arch.regs_dirty = 0;
6565 * eager fpu is enabled if PKEY is supported and CR4 is switched
6566 * back on host, so it is safe to read guest PKRU from current
6569 if (static_cpu_has(X86_FEATURE_PKU) &&
6570 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6571 vcpu->arch.pkru = rdpkru();
6572 if (vcpu->arch.pkru != vmx->host_pkru)
6573 __write_pkru(vmx->host_pkru);
6576 kvm_put_guest_xcr0(vcpu);
6578 vmx->nested.nested_run_pending = 0;
6579 vmx->idt_vectoring_info = 0;
6581 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6582 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6583 kvm_machine_check();
6585 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6588 vmx->loaded_vmcs->launched = 1;
6589 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6591 vmx_recover_nmi_blocking(vmx);
6592 vmx_complete_interrupts(vmx);
6595 static struct kvm *vmx_vm_alloc(void)
6597 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6598 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6600 return &kvm_vmx->kvm;
6603 static void vmx_vm_free(struct kvm *kvm)
6605 kfree(kvm->arch.hyperv.hv_pa_pg);
6606 vfree(to_kvm_vmx(kvm));
6609 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6611 struct vcpu_vmx *vmx = to_vmx(vcpu);
6614 vmx_destroy_pml_buffer(vmx);
6615 free_vpid(vmx->vpid);
6616 nested_vmx_free_vcpu(vcpu);
6617 free_loaded_vmcs(vmx->loaded_vmcs);
6618 kfree(vmx->guest_msrs);
6619 kvm_vcpu_uninit(vcpu);
6620 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6621 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6622 kmem_cache_free(kvm_vcpu_cache, vmx);
6625 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6628 struct vcpu_vmx *vmx;
6629 unsigned long *msr_bitmap;
6632 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0,
6633 "struct kvm_vcpu must be at offset 0 for arch usercopy region");
6635 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6637 return ERR_PTR(-ENOMEM);
6639 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6640 GFP_KERNEL_ACCOUNT);
6641 if (!vmx->vcpu.arch.user_fpu) {
6642 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6644 goto free_partial_vcpu;
6647 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6648 GFP_KERNEL_ACCOUNT);
6649 if (!vmx->vcpu.arch.guest_fpu) {
6650 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6655 vmx->vpid = allocate_vpid();
6657 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6664 * If PML is turned on, failure on enabling PML just results in failure
6665 * of creating the vcpu, therefore we can simplify PML logic (by
6666 * avoiding dealing with cases, such as enabling PML partially on vcpus
6667 * for the guest, etc.
6670 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6675 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6676 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6679 if (!vmx->guest_msrs)
6682 err = alloc_loaded_vmcs(&vmx->vmcs01);
6686 msr_bitmap = vmx->vmcs01.msr_bitmap;
6687 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6688 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6689 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6690 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6691 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6692 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6693 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6694 if (kvm_cstate_in_guest(kvm)) {
6695 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6696 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6697 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6698 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6700 vmx->msr_bitmap_mode = 0;
6702 vmx->loaded_vmcs = &vmx->vmcs01;
6704 vmx_vcpu_load(&vmx->vcpu, cpu);
6705 vmx->vcpu.cpu = cpu;
6706 vmx_vcpu_setup(vmx);
6707 vmx_vcpu_put(&vmx->vcpu);
6709 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6710 err = alloc_apic_access_page(kvm);
6715 if (enable_ept && !enable_unrestricted_guest) {
6716 err = init_rmode_identity_map(kvm);
6722 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6724 kvm_vcpu_apicv_active(&vmx->vcpu));
6726 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6728 vmx->nested.posted_intr_nv = -1;
6729 vmx->nested.current_vmptr = -1ull;
6731 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6734 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6735 * or POSTED_INTR_WAKEUP_VECTOR.
6737 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6738 vmx->pi_desc.sn = 1;
6740 vmx->ept_pointer = INVALID_PAGE;
6745 free_loaded_vmcs(vmx->loaded_vmcs);
6747 kfree(vmx->guest_msrs);
6749 vmx_destroy_pml_buffer(vmx);
6751 kvm_vcpu_uninit(&vmx->vcpu);
6753 free_vpid(vmx->vpid);
6754 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6756 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6758 kmem_cache_free(kvm_vcpu_cache, vmx);
6759 return ERR_PTR(err);
6762 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6763 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6765 static int vmx_vm_init(struct kvm *kvm)
6767 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6770 kvm->arch.pause_in_guest = true;
6772 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6773 switch (l1tf_mitigation) {
6774 case L1TF_MITIGATION_OFF:
6775 case L1TF_MITIGATION_FLUSH_NOWARN:
6776 /* 'I explicitly don't care' is set */
6778 case L1TF_MITIGATION_FLUSH:
6779 case L1TF_MITIGATION_FLUSH_NOSMT:
6780 case L1TF_MITIGATION_FULL:
6782 * Warn upon starting the first VM in a potentially
6783 * insecure environment.
6785 if (sched_smt_active())
6786 pr_warn_once(L1TF_MSG_SMT);
6787 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6788 pr_warn_once(L1TF_MSG_L1D);
6790 case L1TF_MITIGATION_FULL_FORCE:
6791 /* Flush is enforced */
6798 static int __init vmx_check_processor_compat(void)
6800 struct vmcs_config vmcs_conf;
6801 struct vmx_capability vmx_cap;
6803 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6806 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6808 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6809 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6810 smp_processor_id());
6816 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6821 /* For VT-d and EPT combination
6822 * 1. MMIO: always map as UC
6824 * a. VT-d without snooping control feature: can't guarantee the
6825 * result, try to trust guest.
6826 * b. VT-d with snooping control feature: snooping control feature of
6827 * VT-d engine can guarantee the cache correctness. Just set it
6828 * to WB to keep consistent with host. So the same as item 3.
6829 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6830 * consistent with host MTRR
6833 cache = MTRR_TYPE_UNCACHABLE;
6837 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6838 ipat = VMX_EPT_IPAT_BIT;
6839 cache = MTRR_TYPE_WRBACK;
6843 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6844 ipat = VMX_EPT_IPAT_BIT;
6845 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6846 cache = MTRR_TYPE_WRBACK;
6848 cache = MTRR_TYPE_UNCACHABLE;
6852 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6855 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6858 static int vmx_get_lpage_level(void)
6860 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6861 return PT_DIRECTORY_LEVEL;
6863 /* For shadow and EPT supported 1GB page */
6864 return PT_PDPE_LEVEL;
6867 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6870 * These bits in the secondary execution controls field
6871 * are dynamic, the others are mostly based on the hypervisor
6872 * architecture and the guest's CPUID. Do not touch the
6876 SECONDARY_EXEC_SHADOW_VMCS |
6877 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6878 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6879 SECONDARY_EXEC_DESC;
6881 u32 new_ctl = vmx->secondary_exec_control;
6882 u32 cur_ctl = secondary_exec_controls_get(vmx);
6884 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6888 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6889 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6891 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6893 struct vcpu_vmx *vmx = to_vmx(vcpu);
6894 struct kvm_cpuid_entry2 *entry;
6896 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6897 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6899 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6900 if (entry && (entry->_reg & (_cpuid_mask))) \
6901 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6904 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6905 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6906 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6907 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6908 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6909 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6910 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6911 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6912 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6913 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6914 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6915 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6916 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6917 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6918 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6920 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6921 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6922 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6923 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6924 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6925 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
6927 #undef cr4_fixed1_update
6930 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6932 struct vcpu_vmx *vmx = to_vmx(vcpu);
6934 if (kvm_mpx_supported()) {
6935 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6938 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6939 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6941 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6942 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6947 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6949 struct vcpu_vmx *vmx = to_vmx(vcpu);
6950 struct kvm_cpuid_entry2 *best = NULL;
6953 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6954 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6957 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6958 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6959 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6960 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6963 /* Get the number of configurable Address Ranges for filtering */
6964 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6965 PT_CAP_num_address_ranges);
6967 /* Initialize and clear the no dependency bits */
6968 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6969 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6972 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6973 * will inject an #GP
6975 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6976 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6979 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6980 * PSBFreq can be set
6982 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6983 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6984 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6987 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6988 * MTCFreq can be set
6990 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6991 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6992 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6994 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6995 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6996 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6999 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7000 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7001 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7003 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7004 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7005 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7007 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7008 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7009 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7011 /* unmask address range configure area */
7012 for (i = 0; i < vmx->pt_desc.addr_range; i++)
7013 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7016 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7018 struct vcpu_vmx *vmx = to_vmx(vcpu);
7020 if (cpu_has_secondary_exec_ctrls()) {
7021 vmx_compute_secondary_exec_control(vmx);
7022 vmcs_set_secondary_exec_control(vmx);
7025 if (nested_vmx_allowed(vcpu))
7026 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7027 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7029 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7030 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7032 if (nested_vmx_allowed(vcpu)) {
7033 nested_vmx_cr_fixed1_bits_update(vcpu);
7034 nested_vmx_entry_exit_ctls_update(vcpu);
7037 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7038 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7039 update_intel_pt_cfg(vcpu);
7042 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7044 if (func == 1 && nested)
7045 entry->ecx |= bit(X86_FEATURE_VMX);
7048 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7050 to_vmx(vcpu)->req_immediate_exit = true;
7053 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7054 struct x86_instruction_info *info,
7055 enum x86_intercept_stage stage)
7057 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7058 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7061 * RDPID causes #UD if disabled through secondary execution controls.
7062 * Because it is marked as EmulateOnUD, we need to intercept it here.
7064 if (info->intercept == x86_intercept_rdtscp &&
7065 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7066 ctxt->exception.vector = UD_VECTOR;
7067 ctxt->exception.error_code_valid = false;
7068 return X86EMUL_PROPAGATE_FAULT;
7071 /* TODO: check more intercepts... */
7072 return X86EMUL_CONTINUE;
7075 #ifdef CONFIG_X86_64
7076 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7077 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7078 u64 divisor, u64 *result)
7080 u64 low = a << shift, high = a >> (64 - shift);
7082 /* To avoid the overflow on divq */
7083 if (high >= divisor)
7086 /* Low hold the result, high hold rem which is discarded */
7087 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7088 "rm" (divisor), "0" (low), "1" (high));
7094 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7097 struct vcpu_vmx *vmx;
7098 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7099 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7101 if (kvm_mwait_in_guest(vcpu->kvm) ||
7102 kvm_can_post_timer_interrupt(vcpu))
7107 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7108 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7109 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7110 ktimer->timer_advance_ns);
7112 if (delta_tsc > lapic_timer_advance_cycles)
7113 delta_tsc -= lapic_timer_advance_cycles;
7117 /* Convert to host delta tsc if tsc scaling is enabled */
7118 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7119 delta_tsc && u64_shl_div_u64(delta_tsc,
7120 kvm_tsc_scaling_ratio_frac_bits,
7121 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7125 * If the delta tsc can't fit in the 32 bit after the multi shift,
7126 * we can't use the preemption timer.
7127 * It's possible that it fits on later vmentries, but checking
7128 * on every vmentry is costly so we just use an hrtimer.
7130 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7133 vmx->hv_deadline_tsc = tscl + delta_tsc;
7134 *expired = !delta_tsc;
7138 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7140 to_vmx(vcpu)->hv_deadline_tsc = -1;
7144 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7146 if (!kvm_pause_in_guest(vcpu->kvm))
7147 shrink_ple_window(vcpu);
7150 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7151 struct kvm_memory_slot *slot)
7153 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7154 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7157 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7158 struct kvm_memory_slot *slot)
7160 kvm_mmu_slot_set_dirty(kvm, slot);
7163 static void vmx_flush_log_dirty(struct kvm *kvm)
7165 kvm_flush_pml_buffers(kvm);
7168 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7170 struct vmcs12 *vmcs12;
7171 struct vcpu_vmx *vmx = to_vmx(vcpu);
7174 if (is_guest_mode(vcpu)) {
7175 WARN_ON_ONCE(vmx->nested.pml_full);
7178 * Check if PML is enabled for the nested guest.
7179 * Whether eptp bit 6 is set is already checked
7180 * as part of A/D emulation.
7182 vmcs12 = get_vmcs12(vcpu);
7183 if (!nested_cpu_has_pml(vmcs12))
7186 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7187 vmx->nested.pml_full = true;
7191 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7192 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7194 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7195 offset_in_page(dst), sizeof(gpa)))
7198 vmcs12->guest_pml_index--;
7204 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7205 struct kvm_memory_slot *memslot,
7206 gfn_t offset, unsigned long mask)
7208 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7211 static void __pi_post_block(struct kvm_vcpu *vcpu)
7213 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7214 struct pi_desc old, new;
7218 old.control = new.control = pi_desc->control;
7219 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7220 "Wakeup handler not enabled while the VCPU is blocked\n");
7222 dest = cpu_physical_id(vcpu->cpu);
7224 if (x2apic_enabled())
7227 new.ndst = (dest << 8) & 0xFF00;
7229 /* set 'NV' to 'notification vector' */
7230 new.nv = POSTED_INTR_VECTOR;
7231 } while (cmpxchg64(&pi_desc->control, old.control,
7232 new.control) != old.control);
7234 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7235 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7236 list_del(&vcpu->blocked_vcpu_list);
7237 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7238 vcpu->pre_pcpu = -1;
7243 * This routine does the following things for vCPU which is going
7244 * to be blocked if VT-d PI is enabled.
7245 * - Store the vCPU to the wakeup list, so when interrupts happen
7246 * we can find the right vCPU to wake up.
7247 * - Change the Posted-interrupt descriptor as below:
7248 * 'NDST' <-- vcpu->pre_pcpu
7249 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7250 * - If 'ON' is set during this process, which means at least one
7251 * interrupt is posted for this vCPU, we cannot block it, in
7252 * this case, return 1, otherwise, return 0.
7255 static int pi_pre_block(struct kvm_vcpu *vcpu)
7258 struct pi_desc old, new;
7259 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7261 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7262 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7263 !kvm_vcpu_apicv_active(vcpu))
7266 WARN_ON(irqs_disabled());
7267 local_irq_disable();
7268 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7269 vcpu->pre_pcpu = vcpu->cpu;
7270 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7271 list_add_tail(&vcpu->blocked_vcpu_list,
7272 &per_cpu(blocked_vcpu_on_cpu,
7274 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7278 old.control = new.control = pi_desc->control;
7280 WARN((pi_desc->sn == 1),
7281 "Warning: SN field of posted-interrupts "
7282 "is set before blocking\n");
7285 * Since vCPU can be preempted during this process,
7286 * vcpu->cpu could be different with pre_pcpu, we
7287 * need to set pre_pcpu as the destination of wakeup
7288 * notification event, then we can find the right vCPU
7289 * to wakeup in wakeup handler if interrupts happen
7290 * when the vCPU is in blocked state.
7292 dest = cpu_physical_id(vcpu->pre_pcpu);
7294 if (x2apic_enabled())
7297 new.ndst = (dest << 8) & 0xFF00;
7299 /* set 'NV' to 'wakeup vector' */
7300 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7301 } while (cmpxchg64(&pi_desc->control, old.control,
7302 new.control) != old.control);
7304 /* We should not block the vCPU if an interrupt is posted for it. */
7305 if (pi_test_on(pi_desc) == 1)
7306 __pi_post_block(vcpu);
7309 return (vcpu->pre_pcpu == -1);
7312 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7314 if (pi_pre_block(vcpu))
7317 if (kvm_lapic_hv_timer_in_use(vcpu))
7318 kvm_lapic_switch_to_sw_timer(vcpu);
7323 static void pi_post_block(struct kvm_vcpu *vcpu)
7325 if (vcpu->pre_pcpu == -1)
7328 WARN_ON(irqs_disabled());
7329 local_irq_disable();
7330 __pi_post_block(vcpu);
7334 static void vmx_post_block(struct kvm_vcpu *vcpu)
7336 if (kvm_x86_ops->set_hv_timer)
7337 kvm_lapic_switch_to_hv_timer(vcpu);
7339 pi_post_block(vcpu);
7343 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7346 * @host_irq: host irq of the interrupt
7347 * @guest_irq: gsi of the interrupt
7348 * @set: set or unset PI
7349 * returns 0 on success, < 0 on failure
7351 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7352 uint32_t guest_irq, bool set)
7354 struct kvm_kernel_irq_routing_entry *e;
7355 struct kvm_irq_routing_table *irq_rt;
7356 struct kvm_lapic_irq irq;
7357 struct kvm_vcpu *vcpu;
7358 struct vcpu_data vcpu_info;
7361 if (!kvm_arch_has_assigned_device(kvm) ||
7362 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7363 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7366 idx = srcu_read_lock(&kvm->irq_srcu);
7367 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7368 if (guest_irq >= irq_rt->nr_rt_entries ||
7369 hlist_empty(&irq_rt->map[guest_irq])) {
7370 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7371 guest_irq, irq_rt->nr_rt_entries);
7375 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7376 if (e->type != KVM_IRQ_ROUTING_MSI)
7379 * VT-d PI cannot support posting multicast/broadcast
7380 * interrupts to a vCPU, we still use interrupt remapping
7381 * for these kind of interrupts.
7383 * For lowest-priority interrupts, we only support
7384 * those with single CPU as the destination, e.g. user
7385 * configures the interrupts via /proc/irq or uses
7386 * irqbalance to make the interrupts single-CPU.
7388 * We will support full lowest-priority interrupt later.
7390 * In addition, we can only inject generic interrupts using
7391 * the PI mechanism, refuse to route others through it.
7394 kvm_set_msi_irq(kvm, e, &irq);
7395 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
7396 !kvm_irq_is_postable(&irq)) {
7398 * Make sure the IRTE is in remapped mode if
7399 * we don't handle it in posted mode.
7401 ret = irq_set_vcpu_affinity(host_irq, NULL);
7404 "failed to back to remapped mode, irq: %u\n",
7412 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7413 vcpu_info.vector = irq.vector;
7415 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7416 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7419 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7421 ret = irq_set_vcpu_affinity(host_irq, NULL);
7424 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7432 srcu_read_unlock(&kvm->irq_srcu, idx);
7436 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7438 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7439 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7440 FEATURE_CONTROL_LMCE;
7442 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7443 ~FEATURE_CONTROL_LMCE;
7446 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7448 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7449 if (to_vmx(vcpu)->nested.nested_run_pending)
7454 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7456 struct vcpu_vmx *vmx = to_vmx(vcpu);
7458 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7459 if (vmx->nested.smm.guest_mode)
7460 nested_vmx_vmexit(vcpu, -1, 0, 0);
7462 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7463 vmx->nested.vmxon = false;
7464 vmx_clear_hlt(vcpu);
7468 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7470 struct vcpu_vmx *vmx = to_vmx(vcpu);
7473 if (vmx->nested.smm.vmxon) {
7474 vmx->nested.vmxon = true;
7475 vmx->nested.smm.vmxon = false;
7478 if (vmx->nested.smm.guest_mode) {
7479 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7483 vmx->nested.smm.guest_mode = false;
7488 static int enable_smi_window(struct kvm_vcpu *vcpu)
7493 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7498 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7500 return to_vmx(vcpu)->nested.vmxon;
7503 static __init int hardware_setup(void)
7505 unsigned long host_bndcfgs;
7509 rdmsrl_safe(MSR_EFER, &host_efer);
7512 host_idt_base = dt.address;
7514 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7515 kvm_define_shared_msr(i, vmx_msr_index[i]);
7517 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7520 if (boot_cpu_has(X86_FEATURE_NX))
7521 kvm_enable_efer_bits(EFER_NX);
7523 if (boot_cpu_has(X86_FEATURE_MPX)) {
7524 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7525 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7528 if (boot_cpu_has(X86_FEATURE_XSAVES))
7529 rdmsrl(MSR_IA32_XSS, host_xss);
7531 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7532 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7535 if (!cpu_has_vmx_ept() ||
7536 !cpu_has_vmx_ept_4levels() ||
7537 !cpu_has_vmx_ept_mt_wb() ||
7538 !cpu_has_vmx_invept_global())
7541 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7542 enable_ept_ad_bits = 0;
7544 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7545 enable_unrestricted_guest = 0;
7547 if (!cpu_has_vmx_flexpriority())
7548 flexpriority_enabled = 0;
7550 if (!cpu_has_virtual_nmis())
7554 * set_apic_access_page_addr() is used to reload apic access
7555 * page upon invalidation. No need to do anything if not
7556 * using the APIC_ACCESS_ADDR VMCS field.
7558 if (!flexpriority_enabled)
7559 kvm_x86_ops->set_apic_access_page_addr = NULL;
7561 if (!cpu_has_vmx_tpr_shadow())
7562 kvm_x86_ops->update_cr8_intercept = NULL;
7564 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7565 kvm_disable_largepages();
7567 #if IS_ENABLED(CONFIG_HYPERV)
7568 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7570 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7571 kvm_x86_ops->tlb_remote_flush_with_range =
7572 hv_remote_flush_tlb_with_range;
7576 if (!cpu_has_vmx_ple()) {
7579 ple_window_grow = 0;
7581 ple_window_shrink = 0;
7584 if (!cpu_has_vmx_apicv()) {
7586 kvm_x86_ops->sync_pir_to_irr = NULL;
7589 if (cpu_has_vmx_tsc_scaling()) {
7590 kvm_has_tsc_control = true;
7591 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7592 kvm_tsc_scaling_ratio_frac_bits = 48;
7595 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7603 * Only enable PML when hardware supports PML feature, and both EPT
7604 * and EPT A/D bit features are enabled -- PML depends on them to work.
7606 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7610 kvm_x86_ops->slot_enable_log_dirty = NULL;
7611 kvm_x86_ops->slot_disable_log_dirty = NULL;
7612 kvm_x86_ops->flush_log_dirty = NULL;
7613 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7616 if (!cpu_has_vmx_preemption_timer())
7617 enable_preemption_timer = false;
7619 if (enable_preemption_timer) {
7620 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7623 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7624 cpu_preemption_timer_multi =
7625 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7628 use_timer_freq = (u64)tsc_khz * 1000;
7629 use_timer_freq >>= cpu_preemption_timer_multi;
7632 * KVM "disables" the preemption timer by setting it to its max
7633 * value. Don't use the timer if it might cause spurious exits
7634 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7636 if (use_timer_freq > 0xffffffffu / 10)
7637 enable_preemption_timer = false;
7640 if (!enable_preemption_timer) {
7641 kvm_x86_ops->set_hv_timer = NULL;
7642 kvm_x86_ops->cancel_hv_timer = NULL;
7643 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7646 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7648 kvm_mce_cap_supported |= MCG_LMCE_P;
7650 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7652 if (!enable_ept || !cpu_has_vmx_intel_pt())
7653 pt_mode = PT_MODE_SYSTEM;
7656 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7657 vmx_capability.ept, enable_apicv);
7659 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7664 r = alloc_kvm_area();
7666 nested_vmx_hardware_unsetup();
7670 static __exit void hardware_unsetup(void)
7673 nested_vmx_hardware_unsetup();
7678 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7679 .cpu_has_kvm_support = cpu_has_kvm_support,
7680 .disabled_by_bios = vmx_disabled_by_bios,
7681 .hardware_setup = hardware_setup,
7682 .hardware_unsetup = hardware_unsetup,
7683 .check_processor_compatibility = vmx_check_processor_compat,
7684 .hardware_enable = hardware_enable,
7685 .hardware_disable = hardware_disable,
7686 .cpu_has_accelerated_tpr = report_flexpriority,
7687 .has_emulated_msr = vmx_has_emulated_msr,
7689 .vm_init = vmx_vm_init,
7690 .vm_alloc = vmx_vm_alloc,
7691 .vm_free = vmx_vm_free,
7693 .vcpu_create = vmx_create_vcpu,
7694 .vcpu_free = vmx_free_vcpu,
7695 .vcpu_reset = vmx_vcpu_reset,
7697 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7698 .vcpu_load = vmx_vcpu_load,
7699 .vcpu_put = vmx_vcpu_put,
7701 .update_bp_intercept = update_exception_bitmap,
7702 .get_msr_feature = vmx_get_msr_feature,
7703 .get_msr = vmx_get_msr,
7704 .set_msr = vmx_set_msr,
7705 .get_segment_base = vmx_get_segment_base,
7706 .get_segment = vmx_get_segment,
7707 .set_segment = vmx_set_segment,
7708 .get_cpl = vmx_get_cpl,
7709 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7710 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7711 .decache_cr3 = vmx_decache_cr3,
7712 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7713 .set_cr0 = vmx_set_cr0,
7714 .set_cr3 = vmx_set_cr3,
7715 .set_cr4 = vmx_set_cr4,
7716 .set_efer = vmx_set_efer,
7717 .get_idt = vmx_get_idt,
7718 .set_idt = vmx_set_idt,
7719 .get_gdt = vmx_get_gdt,
7720 .set_gdt = vmx_set_gdt,
7721 .get_dr6 = vmx_get_dr6,
7722 .set_dr6 = vmx_set_dr6,
7723 .set_dr7 = vmx_set_dr7,
7724 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7725 .cache_reg = vmx_cache_reg,
7726 .get_rflags = vmx_get_rflags,
7727 .set_rflags = vmx_set_rflags,
7729 .tlb_flush = vmx_flush_tlb,
7730 .tlb_flush_gva = vmx_flush_tlb_gva,
7732 .run = vmx_vcpu_run,
7733 .handle_exit = vmx_handle_exit,
7734 .skip_emulated_instruction = __skip_emulated_instruction,
7735 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7736 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7737 .patch_hypercall = vmx_patch_hypercall,
7738 .set_irq = vmx_inject_irq,
7739 .set_nmi = vmx_inject_nmi,
7740 .queue_exception = vmx_queue_exception,
7741 .cancel_injection = vmx_cancel_injection,
7742 .interrupt_allowed = vmx_interrupt_allowed,
7743 .nmi_allowed = vmx_nmi_allowed,
7744 .get_nmi_mask = vmx_get_nmi_mask,
7745 .set_nmi_mask = vmx_set_nmi_mask,
7746 .enable_nmi_window = enable_nmi_window,
7747 .enable_irq_window = enable_irq_window,
7748 .update_cr8_intercept = update_cr8_intercept,
7749 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7750 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7751 .get_enable_apicv = vmx_get_enable_apicv,
7752 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7753 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7754 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7755 .hwapic_irr_update = vmx_hwapic_irr_update,
7756 .hwapic_isr_update = vmx_hwapic_isr_update,
7757 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7758 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7759 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7760 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7762 .set_tss_addr = vmx_set_tss_addr,
7763 .set_identity_map_addr = vmx_set_identity_map_addr,
7764 .get_tdp_level = get_ept_level,
7765 .get_mt_mask = vmx_get_mt_mask,
7767 .get_exit_info = vmx_get_exit_info,
7769 .get_lpage_level = vmx_get_lpage_level,
7771 .cpuid_update = vmx_cpuid_update,
7773 .rdtscp_supported = vmx_rdtscp_supported,
7774 .invpcid_supported = vmx_invpcid_supported,
7776 .set_supported_cpuid = vmx_set_supported_cpuid,
7778 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7780 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7781 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7783 .set_tdp_cr3 = vmx_set_cr3,
7785 .check_intercept = vmx_check_intercept,
7786 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7787 .mpx_supported = vmx_mpx_supported,
7788 .xsaves_supported = vmx_xsaves_supported,
7789 .umip_emulated = vmx_umip_emulated,
7790 .pt_supported = vmx_pt_supported,
7792 .request_immediate_exit = vmx_request_immediate_exit,
7794 .sched_in = vmx_sched_in,
7796 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7797 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7798 .flush_log_dirty = vmx_flush_log_dirty,
7799 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7800 .write_log_dirty = vmx_write_pml_buffer,
7802 .pre_block = vmx_pre_block,
7803 .post_block = vmx_post_block,
7805 .pmu_ops = &intel_pmu_ops,
7807 .update_pi_irte = vmx_update_pi_irte,
7809 #ifdef CONFIG_X86_64
7810 .set_hv_timer = vmx_set_hv_timer,
7811 .cancel_hv_timer = vmx_cancel_hv_timer,
7814 .setup_mce = vmx_setup_mce,
7816 .smi_allowed = vmx_smi_allowed,
7817 .pre_enter_smm = vmx_pre_enter_smm,
7818 .pre_leave_smm = vmx_pre_leave_smm,
7819 .enable_smi_window = enable_smi_window,
7821 .check_nested_events = NULL,
7822 .get_nested_state = NULL,
7823 .set_nested_state = NULL,
7824 .get_vmcs12_pages = NULL,
7825 .nested_enable_evmcs = NULL,
7826 .nested_get_evmcs_version = NULL,
7827 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7828 .apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7831 static void vmx_cleanup_l1d_flush(void)
7833 if (vmx_l1d_flush_pages) {
7834 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7835 vmx_l1d_flush_pages = NULL;
7837 /* Restore state so sysfs ignores VMX */
7838 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7841 static void vmx_exit(void)
7843 #ifdef CONFIG_KEXEC_CORE
7844 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7850 #if IS_ENABLED(CONFIG_HYPERV)
7851 if (static_branch_unlikely(&enable_evmcs)) {
7853 struct hv_vp_assist_page *vp_ap;
7855 * Reset everything to support using non-enlightened VMCS
7856 * access later (e.g. when we reload the module with
7857 * enlightened_vmcs=0)
7859 for_each_online_cpu(cpu) {
7860 vp_ap = hv_get_vp_assist_page(cpu);
7865 vp_ap->nested_control.features.directhypercall = 0;
7866 vp_ap->current_nested_vmcs = 0;
7867 vp_ap->enlighten_vmentry = 0;
7870 static_branch_disable(&enable_evmcs);
7873 vmx_cleanup_l1d_flush();
7875 module_exit(vmx_exit);
7877 static int __init vmx_init(void)
7881 #if IS_ENABLED(CONFIG_HYPERV)
7883 * Enlightened VMCS usage should be recommended and the host needs
7884 * to support eVMCS v1 or above. We can also disable eVMCS support
7885 * with module parameter.
7887 if (enlightened_vmcs &&
7888 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7889 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7890 KVM_EVMCS_VERSION) {
7893 /* Check that we have assist pages on all online CPUs */
7894 for_each_online_cpu(cpu) {
7895 if (!hv_get_vp_assist_page(cpu)) {
7896 enlightened_vmcs = false;
7901 if (enlightened_vmcs) {
7902 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7903 static_branch_enable(&enable_evmcs);
7906 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7907 vmx_x86_ops.enable_direct_tlbflush
7908 = hv_enable_direct_tlbflush;
7911 enlightened_vmcs = false;
7915 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7916 __alignof__(struct vcpu_vmx), THIS_MODULE);
7921 * Must be called after kvm_init() so enable_ept is properly set
7922 * up. Hand the parameter mitigation value in which was stored in
7923 * the pre module init parser. If no parameter was given, it will
7924 * contain 'auto' which will be turned into the default 'cond'
7927 if (boot_cpu_has(X86_BUG_L1TF)) {
7928 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7935 #ifdef CONFIG_KEXEC_CORE
7936 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7937 crash_vmclear_local_loaded_vmcss);
7939 vmx_check_vmcs12_offsets();
7943 module_init(vmx_init);