1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/frame.h>
17 #include <linux/highmem.h>
18 #include <linux/hrtimer.h>
19 #include <linux/kernel.h>
20 #include <linux/kvm_host.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/mod_devicetable.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
34 #include <asm/debugreg.h>
36 #include <asm/fpu/internal.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/kexec.h>
40 #include <asm/perf_event.h>
42 #include <asm/mmu_context.h>
43 #include <asm/mshyperv.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/virtext.h>
48 #include "capabilities.h"
52 #include "kvm_cache_regs.h"
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly enable_vnmi = 1;
77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
79 bool __read_mostly flexpriority_enabled = 1;
80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
82 bool __read_mostly enable_ept = 1;
83 module_param_named(ept, enable_ept, bool, S_IRUGO);
85 bool __read_mostly enable_unrestricted_guest = 1;
86 module_param_named(unrestricted_guest,
87 enable_unrestricted_guest, bool, S_IRUGO);
89 bool __read_mostly enable_ept_ad_bits = 1;
90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
92 static bool __read_mostly emulate_invalid_guest_state = true;
93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
95 static bool __read_mostly fasteoi = 1;
96 module_param(fasteoi, bool, S_IRUGO);
98 static bool __read_mostly enable_apicv = 1;
99 module_param(enable_apicv, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 1;
107 module_param(nested, bool, S_IRUGO);
109 static u64 __read_mostly host_xss;
111 bool __read_mostly enable_pml = 1;
112 module_param_named(pml, enable_pml, bool, S_IRUGO);
114 static bool __read_mostly dump_invalid_vmcs = 0;
115 module_param(dump_invalid_vmcs, bool, 0644);
117 #define MSR_BITMAP_MODE_X2APIC 1
118 #define MSR_BITMAP_MODE_X2APIC_APICV 2
120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
123 static int __read_mostly cpu_preemption_timer_multi;
124 static bool __read_mostly enable_preemption_timer = 1;
126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
131 #define KVM_VM_CR0_ALWAYS_ON \
132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
134 #define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
147 RTIT_STATUS_BYTECNT))
149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
153 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
154 * ple_gap: upper bound on the amount of time between two successive
155 * executions of PAUSE in a loop. Also indicate if ple enabled.
156 * According to test, this time is usually smaller than 128 cycles.
157 * ple_window: upper bound on the amount of time a guest is allowed to execute
158 * in a PAUSE loop. Tests indicate that most spinlocks are held for
159 * less than 2^12 cycles
160 * Time is measured based on a counter that runs at the same rate as the TSC,
161 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
164 module_param(ple_gap, uint, 0444);
166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
167 module_param(ple_window, uint, 0444);
169 /* Default doubles per-vcpu window every exit. */
170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
171 module_param(ple_window_grow, uint, 0444);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
175 module_param(ple_window_shrink, uint, 0444);
177 /* Default is to compute the maximum so we can never overflow. */
178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, uint, 0444);
181 /* Default is SYSTEM mode, 1 for host-guest mode */
182 int __read_mostly pt_mode = PT_MODE_SYSTEM;
183 module_param(pt_mode, int, S_IRUGO);
185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
187 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
189 /* Storage for pre module init parameter parsing */
190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
192 static const struct {
195 } vmentry_l1d_param[] = {
196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
198 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
204 #define L1D_CACHE_ORDER 4
205 static void *vmx_l1d_flush_pages;
207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
227 /* If set to auto use the default l1tf mitigation method */
228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
229 switch (l1tf_mitigation) {
230 case L1TF_MITIGATION_OFF:
231 l1tf = VMENTER_L1D_FLUSH_NEVER;
233 case L1TF_MITIGATION_FLUSH_NOWARN:
234 case L1TF_MITIGATION_FLUSH:
235 case L1TF_MITIGATION_FLUSH_NOSMT:
236 l1tf = VMENTER_L1D_FLUSH_COND;
238 case L1TF_MITIGATION_FULL:
239 case L1TF_MITIGATION_FULL_FORCE:
240 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
244 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
250 * This allocation for vmx_l1d_flush_pages is not tied to a VM
251 * lifetime and so should not be charged to a memcg.
253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
256 vmx_l1d_flush_pages = page_address(page);
259 * Initialize each page with a different pattern in
260 * order to protect against KSM in the nested
261 * virtualization case.
263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
269 l1tf_vmx_mitigation = l1tf;
271 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
272 static_branch_enable(&vmx_l1d_should_flush);
274 static_branch_disable(&vmx_l1d_should_flush);
276 if (l1tf == VMENTER_L1D_FLUSH_COND)
277 static_branch_enable(&vmx_l1d_flush_cond);
279 static_branch_disable(&vmx_l1d_flush_cond);
283 static int vmentry_l1d_flush_parse(const char *s)
288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
289 if (vmentry_l1d_param[i].for_parse &&
290 sysfs_streq(s, vmentry_l1d_param[i].option))
297 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301 l1tf = vmentry_l1d_flush_parse(s);
305 if (!boot_cpu_has(X86_BUG_L1TF))
309 * Has vmx_init() run already? If not then this is the pre init
310 * parameter parsing. In that case just store the value and let
311 * vmx_init() do the proper setup after enable_ept has been
314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
315 vmentry_l1d_flush_param = l1tf;
319 mutex_lock(&vmx_l1d_flush_mutex);
320 ret = vmx_setup_l1d_flush(l1tf);
321 mutex_unlock(&vmx_l1d_flush_mutex);
325 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
328 return sprintf(s, "???\n");
330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
333 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
334 .set = vmentry_l1d_flush_set,
335 .get = vmentry_l1d_flush_get,
337 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
339 static bool guest_state_valid(struct kvm_vcpu *vcpu);
340 static u32 vmx_segment_access_rights(struct kvm_segment *var);
341 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
344 void vmx_vmexit(void);
346 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
347 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
352 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
356 * can find which vCPU should be waken up.
358 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
359 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
361 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
362 static DEFINE_SPINLOCK(vmx_vpid_lock);
364 struct vmcs_config vmcs_config;
365 struct vmx_capability vmx_capability;
367 #define VMX_SEGMENT_FIELD(seg) \
368 [VCPU_SREG_##seg] = { \
369 .selector = GUEST_##seg##_SELECTOR, \
370 .base = GUEST_##seg##_BASE, \
371 .limit = GUEST_##seg##_LIMIT, \
372 .ar_bytes = GUEST_##seg##_AR_BYTES, \
375 static const struct kvm_vmx_segment_field {
380 } kvm_vmx_segment_fields[] = {
381 VMX_SEGMENT_FIELD(CS),
382 VMX_SEGMENT_FIELD(DS),
383 VMX_SEGMENT_FIELD(ES),
384 VMX_SEGMENT_FIELD(FS),
385 VMX_SEGMENT_FIELD(GS),
386 VMX_SEGMENT_FIELD(SS),
387 VMX_SEGMENT_FIELD(TR),
388 VMX_SEGMENT_FIELD(LDTR),
392 static unsigned long host_idt_base;
395 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
396 * will emulate SYSCALL in legacy mode if the vendor string in guest
397 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
398 * support this emulation, IA32_STAR must always be included in
399 * vmx_msr_index[], even in i386 builds.
401 const u32 vmx_msr_index[] = {
403 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
405 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
408 #if IS_ENABLED(CONFIG_HYPERV)
409 static bool __read_mostly enlightened_vmcs = true;
410 module_param(enlightened_vmcs, bool, 0444);
412 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
413 static void check_ept_pointer_match(struct kvm *kvm)
415 struct kvm_vcpu *vcpu;
416 u64 tmp_eptp = INVALID_PAGE;
419 kvm_for_each_vcpu(i, vcpu, kvm) {
420 if (!VALID_PAGE(tmp_eptp)) {
421 tmp_eptp = to_vmx(vcpu)->ept_pointer;
422 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
423 to_kvm_vmx(kvm)->ept_pointers_match
424 = EPT_POINTERS_MISMATCH;
429 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
432 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
435 struct kvm_tlb_range *range = data;
437 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
441 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
442 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
444 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
447 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
448 * of the base of EPT PML4 table, strip off EPT configuration
452 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
453 kvm_fill_hv_flush_list_func, (void *)range);
455 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
458 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
459 struct kvm_tlb_range *range)
461 struct kvm_vcpu *vcpu;
464 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
466 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
467 check_ept_pointer_match(kvm);
469 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
470 kvm_for_each_vcpu(i, vcpu, kvm) {
471 /* If ept_pointer is invalid pointer, bypass flush request. */
472 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
473 ret |= __hv_remote_flush_tlb_with_range(
477 ret = __hv_remote_flush_tlb_with_range(kvm,
478 kvm_get_vcpu(kvm, 0), range);
481 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
484 static int hv_remote_flush_tlb(struct kvm *kvm)
486 return hv_remote_flush_tlb_with_range(kvm, NULL);
489 #endif /* IS_ENABLED(CONFIG_HYPERV) */
492 * Comment's format: document - errata name - stepping - processor name.
494 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
496 static u32 vmx_preemption_cpu_tfms[] = {
497 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
499 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
500 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
501 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
503 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
505 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
506 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
508 * 320767.pdf - AAP86 - B1 -
509 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
512 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
514 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
516 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
518 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
519 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
520 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
522 /* Xeon E3-1220 V2 */
526 static inline bool cpu_has_broken_vmx_preemption_timer(void)
528 u32 eax = cpuid_eax(0x00000001), i;
530 /* Clear the reserved bits */
531 eax &= ~(0x3U << 14 | 0xfU << 28);
532 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
533 if (eax == vmx_preemption_cpu_tfms[i])
539 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
541 return flexpriority_enabled && lapic_in_kernel(vcpu);
544 static inline bool report_flexpriority(void)
546 return flexpriority_enabled;
549 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
553 for (i = 0; i < vmx->nmsrs; ++i)
554 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
559 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
563 i = __find_msr_index(vmx, msr);
565 return &vmx->guest_msrs[i];
569 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
571 vmcs_clear(loaded_vmcs->vmcs);
572 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
573 vmcs_clear(loaded_vmcs->shadow_vmcs);
574 loaded_vmcs->cpu = -1;
575 loaded_vmcs->launched = 0;
578 #ifdef CONFIG_KEXEC_CORE
580 * This bitmap is used to indicate whether the vmclear
581 * operation is enabled on all cpus. All disabled by
584 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
586 static inline void crash_enable_local_vmclear(int cpu)
588 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
591 static inline void crash_disable_local_vmclear(int cpu)
593 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
596 static inline int crash_local_vmclear_enabled(int cpu)
598 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
601 static void crash_vmclear_local_loaded_vmcss(void)
603 int cpu = raw_smp_processor_id();
604 struct loaded_vmcs *v;
606 if (!crash_local_vmclear_enabled(cpu))
609 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
610 loaded_vmcss_on_cpu_link)
614 static inline void crash_enable_local_vmclear(int cpu) { }
615 static inline void crash_disable_local_vmclear(int cpu) { }
616 #endif /* CONFIG_KEXEC_CORE */
618 static void __loaded_vmcs_clear(void *arg)
620 struct loaded_vmcs *loaded_vmcs = arg;
621 int cpu = raw_smp_processor_id();
623 if (loaded_vmcs->cpu != cpu)
624 return; /* vcpu migration can race with cpu offline */
625 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
626 per_cpu(current_vmcs, cpu) = NULL;
627 crash_disable_local_vmclear(cpu);
628 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
631 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
632 * is before setting loaded_vmcs->vcpu to -1 which is done in
633 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
634 * then adds the vmcs into percpu list before it is deleted.
638 loaded_vmcs_init(loaded_vmcs);
639 crash_enable_local_vmclear(cpu);
642 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
644 int cpu = loaded_vmcs->cpu;
647 smp_call_function_single(cpu,
648 __loaded_vmcs_clear, loaded_vmcs, 1);
651 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
655 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
657 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
658 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
659 vmx->segment_cache.bitmask = 0;
661 ret = vmx->segment_cache.bitmask & mask;
662 vmx->segment_cache.bitmask |= mask;
666 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
668 u16 *p = &vmx->segment_cache.seg[seg].selector;
670 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
671 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
675 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
677 ulong *p = &vmx->segment_cache.seg[seg].base;
679 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
680 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
684 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
686 u32 *p = &vmx->segment_cache.seg[seg].limit;
688 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
689 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
693 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
695 u32 *p = &vmx->segment_cache.seg[seg].ar;
697 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
698 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
702 void update_exception_bitmap(struct kvm_vcpu *vcpu)
706 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
707 (1u << DB_VECTOR) | (1u << AC_VECTOR);
709 * Guest access to VMware backdoor ports could legitimately
710 * trigger #GP because of TSS I/O permission bitmap.
711 * We intercept those #GP and allow access to them anyway
714 if (enable_vmware_backdoor)
715 eb |= (1u << GP_VECTOR);
716 if ((vcpu->guest_debug &
717 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
718 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
719 eb |= 1u << BP_VECTOR;
720 if (to_vmx(vcpu)->rmode.vm86_active)
723 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
725 /* When we are running a nested L2 guest and L1 specified for it a
726 * certain exception bitmap, we must trap the same exceptions and pass
727 * them to L1. When running L2, we will only handle the exceptions
728 * specified above if L1 did not want them.
730 if (is_guest_mode(vcpu))
731 eb |= get_vmcs12(vcpu)->exception_bitmap;
733 vmcs_write32(EXCEPTION_BITMAP, eb);
737 * Check if MSR is intercepted for currently loaded MSR bitmap.
739 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
741 unsigned long *msr_bitmap;
742 int f = sizeof(unsigned long);
744 if (!cpu_has_vmx_msr_bitmap())
747 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
750 return !!test_bit(msr, msr_bitmap + 0x800 / f);
751 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
753 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
759 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
760 unsigned long entry, unsigned long exit)
762 vm_entry_controls_clearbit(vmx, entry);
763 vm_exit_controls_clearbit(vmx, exit);
766 static int find_msr(struct vmx_msrs *m, unsigned int msr)
770 for (i = 0; i < m->nr; ++i) {
771 if (m->val[i].index == msr)
777 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
780 struct msr_autoload *m = &vmx->msr_autoload;
784 if (cpu_has_load_ia32_efer()) {
785 clear_atomic_switch_msr_special(vmx,
786 VM_ENTRY_LOAD_IA32_EFER,
787 VM_EXIT_LOAD_IA32_EFER);
791 case MSR_CORE_PERF_GLOBAL_CTRL:
792 if (cpu_has_load_perf_global_ctrl()) {
793 clear_atomic_switch_msr_special(vmx,
794 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
795 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
800 i = find_msr(&m->guest, msr);
804 m->guest.val[i] = m->guest.val[m->guest.nr];
805 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
808 i = find_msr(&m->host, msr);
813 m->host.val[i] = m->host.val[m->host.nr];
814 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
817 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
818 unsigned long entry, unsigned long exit,
819 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
820 u64 guest_val, u64 host_val)
822 vmcs_write64(guest_val_vmcs, guest_val);
823 if (host_val_vmcs != HOST_IA32_EFER)
824 vmcs_write64(host_val_vmcs, host_val);
825 vm_entry_controls_setbit(vmx, entry);
826 vm_exit_controls_setbit(vmx, exit);
829 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
830 u64 guest_val, u64 host_val, bool entry_only)
833 struct msr_autoload *m = &vmx->msr_autoload;
837 if (cpu_has_load_ia32_efer()) {
838 add_atomic_switch_msr_special(vmx,
839 VM_ENTRY_LOAD_IA32_EFER,
840 VM_EXIT_LOAD_IA32_EFER,
843 guest_val, host_val);
847 case MSR_CORE_PERF_GLOBAL_CTRL:
848 if (cpu_has_load_perf_global_ctrl()) {
849 add_atomic_switch_msr_special(vmx,
850 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
851 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
852 GUEST_IA32_PERF_GLOBAL_CTRL,
853 HOST_IA32_PERF_GLOBAL_CTRL,
854 guest_val, host_val);
858 case MSR_IA32_PEBS_ENABLE:
859 /* PEBS needs a quiescent period after being disabled (to write
860 * a record). Disabling PEBS through VMX MSR swapping doesn't
861 * provide that period, so a CPU could write host's record into
864 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
867 i = find_msr(&m->guest, msr);
869 j = find_msr(&m->host, msr);
871 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) ||
872 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) {
873 printk_once(KERN_WARNING "Not enough msr switch entries. "
874 "Can't add msr %x\n", msr);
879 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
881 m->guest.val[i].index = msr;
882 m->guest.val[i].value = guest_val;
889 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
891 m->host.val[j].index = msr;
892 m->host.val[j].value = host_val;
895 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
897 u64 guest_efer = vmx->vcpu.arch.efer;
902 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
903 * host CPUID is more efficient than testing guest CPUID
904 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
906 if (boot_cpu_has(X86_FEATURE_SMEP))
907 guest_efer |= EFER_NX;
908 else if (!(guest_efer & EFER_NX))
909 ignore_bits |= EFER_NX;
913 * LMA and LME handled by hardware; SCE meaningless outside long mode.
915 ignore_bits |= EFER_SCE;
917 ignore_bits |= EFER_LMA | EFER_LME;
918 /* SCE is meaningful only in long mode on Intel */
919 if (guest_efer & EFER_LMA)
920 ignore_bits &= ~(u64)EFER_SCE;
924 * On EPT, we can't emulate NX, so we must switch EFER atomically.
925 * On CPUs that support "load IA32_EFER", always switch EFER
926 * atomically, since it's faster than switching it manually.
928 if (cpu_has_load_ia32_efer() ||
929 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
930 if (!(guest_efer & EFER_LMA))
931 guest_efer &= ~EFER_LME;
932 if (guest_efer != host_efer)
933 add_atomic_switch_msr(vmx, MSR_EFER,
934 guest_efer, host_efer, false);
936 clear_atomic_switch_msr(vmx, MSR_EFER);
939 clear_atomic_switch_msr(vmx, MSR_EFER);
941 guest_efer &= ~ignore_bits;
942 guest_efer |= host_efer & ignore_bits;
944 vmx->guest_msrs[efer_offset].data = guest_efer;
945 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
953 * On 32-bit kernels, VM exits still load the FS and GS bases from the
954 * VMCS rather than the segment table. KVM uses this helper to figure
955 * out the current bases to poke them into the VMCS before entry.
957 static unsigned long segment_base(u16 selector)
959 struct desc_struct *table;
962 if (!(selector & ~SEGMENT_RPL_MASK))
965 table = get_current_gdt_ro();
967 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
968 u16 ldt_selector = kvm_read_ldt();
970 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
973 table = (struct desc_struct *)segment_base(ldt_selector);
975 v = get_desc_base(&table[selector >> 3]);
980 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
984 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
985 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
986 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
987 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
988 for (i = 0; i < addr_range; i++) {
989 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
990 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
994 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
998 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
999 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1000 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1001 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1002 for (i = 0; i < addr_range; i++) {
1003 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1004 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1008 static void pt_guest_enter(struct vcpu_vmx *vmx)
1010 if (pt_mode == PT_MODE_SYSTEM)
1014 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1015 * Save host state before VM entry.
1017 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1018 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1019 wrmsrl(MSR_IA32_RTIT_CTL, 0);
1020 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1021 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1025 static void pt_guest_exit(struct vcpu_vmx *vmx)
1027 if (pt_mode == PT_MODE_SYSTEM)
1030 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1031 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1032 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1035 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1036 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1039 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1040 unsigned long fs_base, unsigned long gs_base)
1042 if (unlikely(fs_sel != host->fs_sel)) {
1044 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1046 vmcs_write16(HOST_FS_SELECTOR, 0);
1047 host->fs_sel = fs_sel;
1049 if (unlikely(gs_sel != host->gs_sel)) {
1051 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1053 vmcs_write16(HOST_GS_SELECTOR, 0);
1054 host->gs_sel = gs_sel;
1056 if (unlikely(fs_base != host->fs_base)) {
1057 vmcs_writel(HOST_FS_BASE, fs_base);
1058 host->fs_base = fs_base;
1060 if (unlikely(gs_base != host->gs_base)) {
1061 vmcs_writel(HOST_GS_BASE, gs_base);
1062 host->gs_base = gs_base;
1066 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1068 struct vcpu_vmx *vmx = to_vmx(vcpu);
1069 struct vmcs_host_state *host_state;
1070 #ifdef CONFIG_X86_64
1071 int cpu = raw_smp_processor_id();
1073 unsigned long fs_base, gs_base;
1077 vmx->req_immediate_exit = false;
1080 * Note that guest MSRs to be saved/restored can also be changed
1081 * when guest state is loaded. This happens when guest transitions
1082 * to/from long-mode by setting MSR_EFER.LMA.
1084 if (!vmx->guest_msrs_ready) {
1085 vmx->guest_msrs_ready = true;
1086 for (i = 0; i < vmx->save_nmsrs; ++i)
1087 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1088 vmx->guest_msrs[i].data,
1089 vmx->guest_msrs[i].mask);
1092 if (vmx->guest_state_loaded)
1095 host_state = &vmx->loaded_vmcs->host_state;
1098 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1099 * allow segment selectors with cpl > 0 or ti == 1.
1101 host_state->ldt_sel = kvm_read_ldt();
1103 #ifdef CONFIG_X86_64
1104 savesegment(ds, host_state->ds_sel);
1105 savesegment(es, host_state->es_sel);
1107 gs_base = cpu_kernelmode_gs_base(cpu);
1108 if (likely(is_64bit_mm(current->mm))) {
1109 save_fsgs_for_kvm();
1110 fs_sel = current->thread.fsindex;
1111 gs_sel = current->thread.gsindex;
1112 fs_base = current->thread.fsbase;
1113 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1115 savesegment(fs, fs_sel);
1116 savesegment(gs, gs_sel);
1117 fs_base = read_msr(MSR_FS_BASE);
1118 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1121 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1123 savesegment(fs, fs_sel);
1124 savesegment(gs, gs_sel);
1125 fs_base = segment_base(fs_sel);
1126 gs_base = segment_base(gs_sel);
1129 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1130 vmx->guest_state_loaded = true;
1133 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1135 struct vmcs_host_state *host_state;
1137 if (!vmx->guest_state_loaded)
1140 host_state = &vmx->loaded_vmcs->host_state;
1142 ++vmx->vcpu.stat.host_state_reload;
1144 #ifdef CONFIG_X86_64
1145 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1147 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1148 kvm_load_ldt(host_state->ldt_sel);
1149 #ifdef CONFIG_X86_64
1150 load_gs_index(host_state->gs_sel);
1152 loadsegment(gs, host_state->gs_sel);
1155 if (host_state->fs_sel & 7)
1156 loadsegment(fs, host_state->fs_sel);
1157 #ifdef CONFIG_X86_64
1158 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1159 loadsegment(ds, host_state->ds_sel);
1160 loadsegment(es, host_state->es_sel);
1163 invalidate_tss_limit();
1164 #ifdef CONFIG_X86_64
1165 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1167 load_fixmap_gdt(raw_smp_processor_id());
1168 vmx->guest_state_loaded = false;
1169 vmx->guest_msrs_ready = false;
1172 #ifdef CONFIG_X86_64
1173 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1176 if (vmx->guest_state_loaded)
1177 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1179 return vmx->msr_guest_kernel_gs_base;
1182 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1185 if (vmx->guest_state_loaded)
1186 wrmsrl(MSR_KERNEL_GS_BASE, data);
1188 vmx->msr_guest_kernel_gs_base = data;
1192 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1194 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1195 struct pi_desc old, new;
1199 * In case of hot-plug or hot-unplug, we may have to undo
1200 * vmx_vcpu_pi_put even if there is no assigned device. And we
1201 * always keep PI.NDST up to date for simplicity: it makes the
1202 * code easier, and CPU migration is not a fast path.
1204 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
1207 /* The full case. */
1209 old.control = new.control = pi_desc->control;
1211 dest = cpu_physical_id(cpu);
1213 if (x2apic_enabled())
1216 new.ndst = (dest << 8) & 0xFF00;
1219 } while (cmpxchg64(&pi_desc->control, old.control,
1220 new.control) != old.control);
1223 * Clear SN before reading the bitmap. The VT-d firmware
1224 * writes the bitmap and reads SN atomically (5.2.3 in the
1225 * spec), so it doesn't really have a memory barrier that
1226 * pairs with this, but we cannot do that and we need one.
1228 smp_mb__after_atomic();
1230 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS))
1234 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu)
1236 struct vcpu_vmx *vmx = to_vmx(vcpu);
1237 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1239 if (!already_loaded) {
1240 loaded_vmcs_clear(vmx->loaded_vmcs);
1241 local_irq_disable();
1242 crash_disable_local_vmclear(cpu);
1245 * Read loaded_vmcs->cpu should be before fetching
1246 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1247 * See the comments in __loaded_vmcs_clear().
1251 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1252 &per_cpu(loaded_vmcss_on_cpu, cpu));
1253 crash_enable_local_vmclear(cpu);
1257 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1258 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1259 vmcs_load(vmx->loaded_vmcs->vmcs);
1260 indirect_branch_prediction_barrier();
1263 if (!already_loaded) {
1264 void *gdt = get_current_gdt_ro();
1265 unsigned long sysenter_esp;
1267 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1270 * Linux uses per-cpu TSS and GDT, so set these when switching
1271 * processors. See 22.2.4.
1273 vmcs_writel(HOST_TR_BASE,
1274 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1275 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
1278 * VM exits change the host TR limit to 0x67 after a VM
1279 * exit. This is okay, since 0x67 covers everything except
1280 * the IO bitmap and have have code to handle the IO bitmap
1281 * being lost after a VM exit.
1283 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1285 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1286 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1288 vmx->loaded_vmcs->cpu = cpu;
1291 /* Setup TSC multiplier */
1292 if (kvm_has_tsc_control &&
1293 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1294 decache_tsc_multiplier(vmx);
1298 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1299 * vcpu mutex is already taken.
1301 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1303 struct vcpu_vmx *vmx = to_vmx(vcpu);
1305 vmx_vcpu_load_vmcs(vcpu, cpu);
1307 vmx_vcpu_pi_load(vcpu, cpu);
1309 vmx->host_pkru = read_pkru();
1310 vmx->host_debugctlmsr = get_debugctlmsr();
1313 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1315 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1317 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1318 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1319 !kvm_vcpu_apicv_active(vcpu))
1322 /* Set SN when the vCPU is preempted */
1323 if (vcpu->preempted)
1327 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1329 vmx_vcpu_pi_put(vcpu);
1331 vmx_prepare_switch_to_host(to_vmx(vcpu));
1334 static bool emulation_required(struct kvm_vcpu *vcpu)
1336 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1339 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1341 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1343 unsigned long rflags, save_rflags;
1345 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1346 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1347 rflags = vmcs_readl(GUEST_RFLAGS);
1348 if (to_vmx(vcpu)->rmode.vm86_active) {
1349 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1350 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1351 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1353 to_vmx(vcpu)->rflags = rflags;
1355 return to_vmx(vcpu)->rflags;
1358 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1360 unsigned long old_rflags = vmx_get_rflags(vcpu);
1362 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1363 to_vmx(vcpu)->rflags = rflags;
1364 if (to_vmx(vcpu)->rmode.vm86_active) {
1365 to_vmx(vcpu)->rmode.save_rflags = rflags;
1366 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1368 vmcs_writel(GUEST_RFLAGS, rflags);
1370 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1371 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
1374 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1376 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1379 if (interruptibility & GUEST_INTR_STATE_STI)
1380 ret |= KVM_X86_SHADOW_INT_STI;
1381 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1382 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1387 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1389 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1390 u32 interruptibility = interruptibility_old;
1392 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1394 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1395 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1396 else if (mask & KVM_X86_SHADOW_INT_STI)
1397 interruptibility |= GUEST_INTR_STATE_STI;
1399 if ((interruptibility != interruptibility_old))
1400 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1403 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1405 struct vcpu_vmx *vmx = to_vmx(vcpu);
1406 unsigned long value;
1409 * Any MSR write that attempts to change bits marked reserved will
1412 if (data & vmx->pt_desc.ctl_bitmask)
1416 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1417 * result in a #GP unless the same write also clears TraceEn.
1419 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1420 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1424 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1425 * and FabricEn would cause #GP, if
1426 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1428 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1429 !(data & RTIT_CTL_FABRIC_EN) &&
1430 !intel_pt_validate_cap(vmx->pt_desc.caps,
1431 PT_CAP_single_range_output))
1435 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1436 * utilize encodings marked reserved will casue a #GP fault.
1438 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1439 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1440 !test_bit((data & RTIT_CTL_MTC_RANGE) >>
1441 RTIT_CTL_MTC_RANGE_OFFSET, &value))
1443 value = intel_pt_validate_cap(vmx->pt_desc.caps,
1444 PT_CAP_cycle_thresholds);
1445 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1446 !test_bit((data & RTIT_CTL_CYC_THRESH) >>
1447 RTIT_CTL_CYC_THRESH_OFFSET, &value))
1449 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1450 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1451 !test_bit((data & RTIT_CTL_PSB_FREQ) >>
1452 RTIT_CTL_PSB_FREQ_OFFSET, &value))
1456 * If ADDRx_CFG is reserved or the encodings is >2 will
1457 * cause a #GP fault.
1459 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1460 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1462 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1463 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1465 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1466 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1468 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1469 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1476 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1480 rip = kvm_rip_read(vcpu);
1481 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1482 kvm_rip_write(vcpu, rip);
1484 /* skipping an emulated instruction also counts */
1485 vmx_set_interrupt_shadow(vcpu, 0);
1488 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1491 * Ensure that we clear the HLT state in the VMCS. We don't need to
1492 * explicitly skip the instruction because if the HLT state is set,
1493 * then the instruction is already executing and RIP has already been
1496 if (kvm_hlt_in_guest(vcpu->kvm) &&
1497 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1498 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1501 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1503 struct vcpu_vmx *vmx = to_vmx(vcpu);
1504 unsigned nr = vcpu->arch.exception.nr;
1505 bool has_error_code = vcpu->arch.exception.has_error_code;
1506 u32 error_code = vcpu->arch.exception.error_code;
1507 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1509 kvm_deliver_exception_payload(vcpu);
1511 if (has_error_code) {
1512 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1513 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1516 if (vmx->rmode.vm86_active) {
1518 if (kvm_exception_is_soft(nr))
1519 inc_eip = vcpu->arch.event_exit_inst_len;
1520 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1521 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1525 WARN_ON_ONCE(vmx->emulation_required);
1527 if (kvm_exception_is_soft(nr)) {
1528 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1529 vmx->vcpu.arch.event_exit_inst_len);
1530 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1532 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1534 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1536 vmx_clear_hlt(vcpu);
1539 static bool vmx_rdtscp_supported(void)
1541 return cpu_has_vmx_rdtscp();
1544 static bool vmx_invpcid_supported(void)
1546 return cpu_has_vmx_invpcid();
1550 * Swap MSR entry in host/guest MSR entry array.
1552 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1554 struct shared_msr_entry tmp;
1556 tmp = vmx->guest_msrs[to];
1557 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1558 vmx->guest_msrs[from] = tmp;
1562 * Set up the vmcs to automatically save and restore system
1563 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1564 * mode, as fiddling with msrs is very expensive.
1566 static void setup_msrs(struct vcpu_vmx *vmx)
1568 int save_nmsrs, index;
1571 #ifdef CONFIG_X86_64
1573 * The SYSCALL MSRs are only needed on long mode guests, and only
1574 * when EFER.SCE is set.
1576 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1577 index = __find_msr_index(vmx, MSR_STAR);
1579 move_msr_up(vmx, index, save_nmsrs++);
1580 index = __find_msr_index(vmx, MSR_LSTAR);
1582 move_msr_up(vmx, index, save_nmsrs++);
1583 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1585 move_msr_up(vmx, index, save_nmsrs++);
1588 index = __find_msr_index(vmx, MSR_EFER);
1589 if (index >= 0 && update_transition_efer(vmx, index))
1590 move_msr_up(vmx, index, save_nmsrs++);
1591 index = __find_msr_index(vmx, MSR_TSC_AUX);
1592 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1593 move_msr_up(vmx, index, save_nmsrs++);
1595 vmx->save_nmsrs = save_nmsrs;
1596 vmx->guest_msrs_ready = false;
1598 if (cpu_has_vmx_msr_bitmap())
1599 vmx_update_msr_bitmap(&vmx->vcpu);
1602 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1604 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1606 if (is_guest_mode(vcpu) &&
1607 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1608 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1610 return vcpu->arch.tsc_offset;
1613 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1615 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616 u64 g_tsc_offset = 0;
1619 * We're here if L1 chose not to trap WRMSR to TSC. According
1620 * to the spec, this should set L1's TSC; The offset that L1
1621 * set for L2 remains unchanged, and still needs to be added
1622 * to the newly set TSC to get L2's TSC.
1624 if (is_guest_mode(vcpu) &&
1625 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1626 g_tsc_offset = vmcs12->tsc_offset;
1628 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1629 vcpu->arch.tsc_offset - g_tsc_offset,
1631 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1632 return offset + g_tsc_offset;
1636 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1637 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1638 * all guests if the "nested" module option is off, and can also be disabled
1639 * for a single guest by disabling its VMX cpuid bit.
1641 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1643 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1646 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1649 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1651 return !(val & ~valid_bits);
1654 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1656 switch (msr->index) {
1657 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1660 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1669 * Reads an msr value (of 'msr_index') into 'pdata'.
1670 * Returns 0 on success, non-0 otherwise.
1671 * Assumes vcpu_load() was already called.
1673 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1675 struct vcpu_vmx *vmx = to_vmx(vcpu);
1676 struct shared_msr_entry *msr;
1679 switch (msr_info->index) {
1680 #ifdef CONFIG_X86_64
1682 msr_info->data = vmcs_readl(GUEST_FS_BASE);
1685 msr_info->data = vmcs_readl(GUEST_GS_BASE);
1687 case MSR_KERNEL_GS_BASE:
1688 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1692 return kvm_get_msr_common(vcpu, msr_info);
1693 case MSR_IA32_SPEC_CTRL:
1694 if (!msr_info->host_initiated &&
1695 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1698 msr_info->data = to_vmx(vcpu)->spec_ctrl;
1700 case MSR_IA32_SYSENTER_CS:
1701 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1703 case MSR_IA32_SYSENTER_EIP:
1704 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1706 case MSR_IA32_SYSENTER_ESP:
1707 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1709 case MSR_IA32_BNDCFGS:
1710 if (!kvm_mpx_supported() ||
1711 (!msr_info->host_initiated &&
1712 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1714 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1716 case MSR_IA32_MCG_EXT_CTL:
1717 if (!msr_info->host_initiated &&
1718 !(vmx->msr_ia32_feature_control &
1719 FEATURE_CONTROL_LMCE))
1721 msr_info->data = vcpu->arch.mcg_ext_ctl;
1723 case MSR_IA32_FEATURE_CONTROL:
1724 msr_info->data = vmx->msr_ia32_feature_control;
1726 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1727 if (!nested_vmx_allowed(vcpu))
1729 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1732 if (!vmx_xsaves_supported() ||
1733 (!msr_info->host_initiated &&
1734 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1735 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1737 msr_info->data = vcpu->arch.ia32_xss;
1739 case MSR_IA32_RTIT_CTL:
1740 if (pt_mode != PT_MODE_HOST_GUEST)
1742 msr_info->data = vmx->pt_desc.guest.ctl;
1744 case MSR_IA32_RTIT_STATUS:
1745 if (pt_mode != PT_MODE_HOST_GUEST)
1747 msr_info->data = vmx->pt_desc.guest.status;
1749 case MSR_IA32_RTIT_CR3_MATCH:
1750 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1751 !intel_pt_validate_cap(vmx->pt_desc.caps,
1752 PT_CAP_cr3_filtering))
1754 msr_info->data = vmx->pt_desc.guest.cr3_match;
1756 case MSR_IA32_RTIT_OUTPUT_BASE:
1757 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1758 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1759 PT_CAP_topa_output) &&
1760 !intel_pt_validate_cap(vmx->pt_desc.caps,
1761 PT_CAP_single_range_output)))
1763 msr_info->data = vmx->pt_desc.guest.output_base;
1765 case MSR_IA32_RTIT_OUTPUT_MASK:
1766 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1767 (!intel_pt_validate_cap(vmx->pt_desc.caps,
1768 PT_CAP_topa_output) &&
1769 !intel_pt_validate_cap(vmx->pt_desc.caps,
1770 PT_CAP_single_range_output)))
1772 msr_info->data = vmx->pt_desc.guest.output_mask;
1774 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1775 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1776 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1777 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1778 PT_CAP_num_address_ranges)))
1781 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1783 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1786 if (!msr_info->host_initiated &&
1787 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1789 /* Else, falls through */
1791 msr = find_msr_entry(vmx, msr_info->index);
1793 msr_info->data = msr->data;
1796 return kvm_get_msr_common(vcpu, msr_info);
1803 * Writes msr value into into the appropriate "register".
1804 * Returns 0 on success, non-0 otherwise.
1805 * Assumes vcpu_load() was already called.
1807 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1809 struct vcpu_vmx *vmx = to_vmx(vcpu);
1810 struct shared_msr_entry *msr;
1812 u32 msr_index = msr_info->index;
1813 u64 data = msr_info->data;
1816 switch (msr_index) {
1818 ret = kvm_set_msr_common(vcpu, msr_info);
1820 #ifdef CONFIG_X86_64
1822 vmx_segment_cache_clear(vmx);
1823 vmcs_writel(GUEST_FS_BASE, data);
1826 vmx_segment_cache_clear(vmx);
1827 vmcs_writel(GUEST_GS_BASE, data);
1829 case MSR_KERNEL_GS_BASE:
1830 vmx_write_guest_kernel_gs_base(vmx, data);
1833 case MSR_IA32_SYSENTER_CS:
1834 if (is_guest_mode(vcpu))
1835 get_vmcs12(vcpu)->guest_sysenter_cs = data;
1836 vmcs_write32(GUEST_SYSENTER_CS, data);
1838 case MSR_IA32_SYSENTER_EIP:
1839 if (is_guest_mode(vcpu))
1840 get_vmcs12(vcpu)->guest_sysenter_eip = data;
1841 vmcs_writel(GUEST_SYSENTER_EIP, data);
1843 case MSR_IA32_SYSENTER_ESP:
1844 if (is_guest_mode(vcpu))
1845 get_vmcs12(vcpu)->guest_sysenter_esp = data;
1846 vmcs_writel(GUEST_SYSENTER_ESP, data);
1848 case MSR_IA32_DEBUGCTLMSR:
1849 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
1850 VM_EXIT_SAVE_DEBUG_CONTROLS)
1851 get_vmcs12(vcpu)->guest_ia32_debugctl = data;
1853 ret = kvm_set_msr_common(vcpu, msr_info);
1856 case MSR_IA32_BNDCFGS:
1857 if (!kvm_mpx_supported() ||
1858 (!msr_info->host_initiated &&
1859 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1861 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
1862 (data & MSR_IA32_BNDCFGS_RSVD))
1864 vmcs_write64(GUEST_BNDCFGS, data);
1866 case MSR_IA32_SPEC_CTRL:
1867 if (!msr_info->host_initiated &&
1868 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1871 /* The STIBP bit doesn't fault even if it's not advertised */
1872 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
1875 vmx->spec_ctrl = data;
1882 * When it's written (to non-zero) for the first time, pass
1886 * The handling of the MSR bitmap for L2 guests is done in
1887 * nested_vmx_merge_msr_bitmap. We should not touch the
1888 * vmcs02.msr_bitmap here since it gets completely overwritten
1889 * in the merging. We update the vmcs01 here for L1 as well
1890 * since it will end up touching the MSR anyway now.
1892 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1896 case MSR_IA32_PRED_CMD:
1897 if (!msr_info->host_initiated &&
1898 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1901 if (data & ~PRED_CMD_IBPB)
1907 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1911 * When it's written (to non-zero) for the first time, pass
1915 * The handling of the MSR bitmap for L2 guests is done in
1916 * nested_vmx_merge_msr_bitmap. We should not touch the
1917 * vmcs02.msr_bitmap here since it gets completely overwritten
1920 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1923 case MSR_IA32_CR_PAT:
1924 if (!kvm_pat_valid(data))
1927 if (is_guest_mode(vcpu) &&
1928 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
1929 get_vmcs12(vcpu)->guest_ia32_pat = data;
1931 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1932 vmcs_write64(GUEST_IA32_PAT, data);
1933 vcpu->arch.pat = data;
1936 ret = kvm_set_msr_common(vcpu, msr_info);
1938 case MSR_IA32_TSC_ADJUST:
1939 ret = kvm_set_msr_common(vcpu, msr_info);
1941 case MSR_IA32_MCG_EXT_CTL:
1942 if ((!msr_info->host_initiated &&
1943 !(to_vmx(vcpu)->msr_ia32_feature_control &
1944 FEATURE_CONTROL_LMCE)) ||
1945 (data & ~MCG_EXT_CTL_LMCE_EN))
1947 vcpu->arch.mcg_ext_ctl = data;
1949 case MSR_IA32_FEATURE_CONTROL:
1950 if (!vmx_feature_control_msr_valid(vcpu, data) ||
1951 (to_vmx(vcpu)->msr_ia32_feature_control &
1952 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1954 vmx->msr_ia32_feature_control = data;
1955 if (msr_info->host_initiated && data == 0)
1956 vmx_leave_nested(vcpu);
1958 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1959 if (!msr_info->host_initiated)
1960 return 1; /* they are read-only */
1961 if (!nested_vmx_allowed(vcpu))
1963 return vmx_set_vmx_msr(vcpu, msr_index, data);
1965 if (!vmx_xsaves_supported() ||
1966 (!msr_info->host_initiated &&
1967 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
1968 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
1971 * The only supported bit as of Skylake is bit 8, but
1972 * it is not supported on KVM.
1976 vcpu->arch.ia32_xss = data;
1977 if (vcpu->arch.ia32_xss != host_xss)
1978 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
1979 vcpu->arch.ia32_xss, host_xss, false);
1981 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1983 case MSR_IA32_RTIT_CTL:
1984 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1985 vmx_rtit_ctl_check(vcpu, data) ||
1988 vmcs_write64(GUEST_IA32_RTIT_CTL, data);
1989 vmx->pt_desc.guest.ctl = data;
1990 pt_update_intercept_for_msr(vmx);
1992 case MSR_IA32_RTIT_STATUS:
1993 if ((pt_mode != PT_MODE_HOST_GUEST) ||
1994 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
1995 (data & MSR_IA32_RTIT_STATUS_MASK))
1997 vmx->pt_desc.guest.status = data;
1999 case MSR_IA32_RTIT_CR3_MATCH:
2000 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2001 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2002 !intel_pt_validate_cap(vmx->pt_desc.caps,
2003 PT_CAP_cr3_filtering))
2005 vmx->pt_desc.guest.cr3_match = data;
2007 case MSR_IA32_RTIT_OUTPUT_BASE:
2008 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2009 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2010 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2011 PT_CAP_topa_output) &&
2012 !intel_pt_validate_cap(vmx->pt_desc.caps,
2013 PT_CAP_single_range_output)) ||
2014 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
2016 vmx->pt_desc.guest.output_base = data;
2018 case MSR_IA32_RTIT_OUTPUT_MASK:
2019 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2020 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2021 (!intel_pt_validate_cap(vmx->pt_desc.caps,
2022 PT_CAP_topa_output) &&
2023 !intel_pt_validate_cap(vmx->pt_desc.caps,
2024 PT_CAP_single_range_output)))
2026 vmx->pt_desc.guest.output_mask = data;
2028 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2029 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2030 if ((pt_mode != PT_MODE_HOST_GUEST) ||
2031 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
2032 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2033 PT_CAP_num_address_ranges)))
2036 vmx->pt_desc.guest.addr_b[index / 2] = data;
2038 vmx->pt_desc.guest.addr_a[index / 2] = data;
2041 if (!msr_info->host_initiated &&
2042 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2044 /* Check reserved bit, higher 32 bits should be zero */
2045 if ((data >> 32) != 0)
2047 /* Else, falls through */
2049 msr = find_msr_entry(vmx, msr_index);
2051 u64 old_msr_data = msr->data;
2053 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2055 ret = kvm_set_shared_msr(msr->index, msr->data,
2059 msr->data = old_msr_data;
2063 ret = kvm_set_msr_common(vcpu, msr_info);
2069 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2071 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2074 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2077 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2079 case VCPU_EXREG_PDPTR:
2081 ept_save_pdptrs(vcpu);
2088 static __init int cpu_has_kvm_support(void)
2090 return cpu_has_vmx();
2093 static __init int vmx_disabled_by_bios(void)
2097 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2098 if (msr & FEATURE_CONTROL_LOCKED) {
2099 /* launched w/ TXT and VMX disabled */
2100 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2103 /* launched w/o TXT and VMX only enabled w/ TXT */
2104 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2105 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2106 && !tboot_enabled()) {
2107 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2108 "activate TXT before enabling KVM\n");
2111 /* launched w/o TXT and VMX disabled */
2112 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2113 && !tboot_enabled())
2120 static void kvm_cpu_vmxon(u64 addr)
2122 cr4_set_bits(X86_CR4_VMXE);
2123 intel_pt_handle_vmx(1);
2125 asm volatile ("vmxon %0" : : "m"(addr));
2128 static int hardware_enable(void)
2130 int cpu = raw_smp_processor_id();
2131 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2134 if (cr4_read_shadow() & X86_CR4_VMXE)
2138 * This can happen if we hot-added a CPU but failed to allocate
2139 * VP assist page for it.
2141 if (static_branch_unlikely(&enable_evmcs) &&
2142 !hv_get_vp_assist_page(cpu))
2145 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2146 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
2147 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
2150 * Now we can enable the vmclear operation in kdump
2151 * since the loaded_vmcss_on_cpu list on this cpu
2152 * has been initialized.
2154 * Though the cpu is not in VMX operation now, there
2155 * is no problem to enable the vmclear operation
2156 * for the loaded_vmcss_on_cpu list is empty!
2158 crash_enable_local_vmclear(cpu);
2160 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2162 test_bits = FEATURE_CONTROL_LOCKED;
2163 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2164 if (tboot_enabled())
2165 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2167 if ((old & test_bits) != test_bits) {
2168 /* enable and lock */
2169 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2171 kvm_cpu_vmxon(phys_addr);
2178 static void vmclear_local_loaded_vmcss(void)
2180 int cpu = raw_smp_processor_id();
2181 struct loaded_vmcs *v, *n;
2183 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2184 loaded_vmcss_on_cpu_link)
2185 __loaded_vmcs_clear(v);
2189 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2192 static void kvm_cpu_vmxoff(void)
2194 asm volatile (__ex("vmxoff"));
2196 intel_pt_handle_vmx(0);
2197 cr4_clear_bits(X86_CR4_VMXE);
2200 static void hardware_disable(void)
2202 vmclear_local_loaded_vmcss();
2206 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2207 u32 msr, u32 *result)
2209 u32 vmx_msr_low, vmx_msr_high;
2210 u32 ctl = ctl_min | ctl_opt;
2212 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2214 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2215 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2217 /* Ensure minimum (required) set of control bits are supported. */
2225 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2226 struct vmx_capability *vmx_cap)
2228 u32 vmx_msr_low, vmx_msr_high;
2229 u32 min, opt, min2, opt2;
2230 u32 _pin_based_exec_control = 0;
2231 u32 _cpu_based_exec_control = 0;
2232 u32 _cpu_based_2nd_exec_control = 0;
2233 u32 _vmexit_control = 0;
2234 u32 _vmentry_control = 0;
2236 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2237 min = CPU_BASED_HLT_EXITING |
2238 #ifdef CONFIG_X86_64
2239 CPU_BASED_CR8_LOAD_EXITING |
2240 CPU_BASED_CR8_STORE_EXITING |
2242 CPU_BASED_CR3_LOAD_EXITING |
2243 CPU_BASED_CR3_STORE_EXITING |
2244 CPU_BASED_UNCOND_IO_EXITING |
2245 CPU_BASED_MOV_DR_EXITING |
2246 CPU_BASED_USE_TSC_OFFSETING |
2247 CPU_BASED_MWAIT_EXITING |
2248 CPU_BASED_MONITOR_EXITING |
2249 CPU_BASED_INVLPG_EXITING |
2250 CPU_BASED_RDPMC_EXITING;
2252 opt = CPU_BASED_TPR_SHADOW |
2253 CPU_BASED_USE_MSR_BITMAPS |
2254 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2255 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2256 &_cpu_based_exec_control) < 0)
2258 #ifdef CONFIG_X86_64
2259 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2260 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2261 ~CPU_BASED_CR8_STORE_EXITING;
2263 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2265 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2266 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2267 SECONDARY_EXEC_WBINVD_EXITING |
2268 SECONDARY_EXEC_ENABLE_VPID |
2269 SECONDARY_EXEC_ENABLE_EPT |
2270 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2271 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2272 SECONDARY_EXEC_DESC |
2273 SECONDARY_EXEC_RDTSCP |
2274 SECONDARY_EXEC_ENABLE_INVPCID |
2275 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2276 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2277 SECONDARY_EXEC_SHADOW_VMCS |
2278 SECONDARY_EXEC_XSAVES |
2279 SECONDARY_EXEC_RDSEED_EXITING |
2280 SECONDARY_EXEC_RDRAND_EXITING |
2281 SECONDARY_EXEC_ENABLE_PML |
2282 SECONDARY_EXEC_TSC_SCALING |
2283 SECONDARY_EXEC_PT_USE_GPA |
2284 SECONDARY_EXEC_PT_CONCEAL_VMX |
2285 SECONDARY_EXEC_ENABLE_VMFUNC |
2286 SECONDARY_EXEC_ENCLS_EXITING;
2287 if (adjust_vmx_controls(min2, opt2,
2288 MSR_IA32_VMX_PROCBASED_CTLS2,
2289 &_cpu_based_2nd_exec_control) < 0)
2292 #ifndef CONFIG_X86_64
2293 if (!(_cpu_based_2nd_exec_control &
2294 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2295 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2298 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2299 _cpu_based_2nd_exec_control &= ~(
2300 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2301 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2302 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2304 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2305 &vmx_cap->ept, &vmx_cap->vpid);
2307 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2308 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2310 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2311 CPU_BASED_CR3_STORE_EXITING |
2312 CPU_BASED_INVLPG_EXITING);
2313 } else if (vmx_cap->ept) {
2315 pr_warn_once("EPT CAP should not exist if not support "
2316 "1-setting enable EPT VM-execution control\n");
2318 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2321 pr_warn_once("VPID CAP should not exist if not support "
2322 "1-setting enable VPID VM-execution control\n");
2325 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2326 #ifdef CONFIG_X86_64
2327 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2329 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2330 VM_EXIT_LOAD_IA32_PAT |
2331 VM_EXIT_LOAD_IA32_EFER |
2332 VM_EXIT_CLEAR_BNDCFGS |
2333 VM_EXIT_PT_CONCEAL_PIP |
2334 VM_EXIT_CLEAR_IA32_RTIT_CTL;
2335 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2336 &_vmexit_control) < 0)
2339 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2340 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2341 PIN_BASED_VMX_PREEMPTION_TIMER;
2342 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2343 &_pin_based_exec_control) < 0)
2346 if (cpu_has_broken_vmx_preemption_timer())
2347 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2348 if (!(_cpu_based_2nd_exec_control &
2349 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2350 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2352 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2353 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2354 VM_ENTRY_LOAD_IA32_PAT |
2355 VM_ENTRY_LOAD_IA32_EFER |
2356 VM_ENTRY_LOAD_BNDCFGS |
2357 VM_ENTRY_PT_CONCEAL_PIP |
2358 VM_ENTRY_LOAD_IA32_RTIT_CTL;
2359 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2360 &_vmentry_control) < 0)
2364 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2365 * can't be used due to an errata where VM Exit may incorrectly clear
2366 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2367 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2369 if (boot_cpu_data.x86 == 0x6) {
2370 switch (boot_cpu_data.x86_model) {
2371 case 26: /* AAK155 */
2372 case 30: /* AAP115 */
2373 case 37: /* AAT100 */
2374 case 44: /* BC86,AAY89,BD102 */
2376 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2377 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2378 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2379 "does not work properly. Using workaround\n");
2387 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2389 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2390 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2393 #ifdef CONFIG_X86_64
2394 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2395 if (vmx_msr_high & (1u<<16))
2399 /* Require Write-Back (WB) memory type for VMCS accesses. */
2400 if (((vmx_msr_high >> 18) & 15) != 6)
2403 vmcs_conf->size = vmx_msr_high & 0x1fff;
2404 vmcs_conf->order = get_order(vmcs_conf->size);
2405 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2407 vmcs_conf->revision_id = vmx_msr_low;
2409 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2410 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2411 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2412 vmcs_conf->vmexit_ctrl = _vmexit_control;
2413 vmcs_conf->vmentry_ctrl = _vmentry_control;
2415 if (static_branch_unlikely(&enable_evmcs))
2416 evmcs_sanitize_exec_ctrls(vmcs_conf);
2421 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2423 int node = cpu_to_node(cpu);
2427 pages = __alloc_pages_node(node, flags, vmcs_config.order);
2430 vmcs = page_address(pages);
2431 memset(vmcs, 0, vmcs_config.size);
2433 /* KVM supports Enlightened VMCS v1 only */
2434 if (static_branch_unlikely(&enable_evmcs))
2435 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2437 vmcs->hdr.revision_id = vmcs_config.revision_id;
2440 vmcs->hdr.shadow_vmcs = 1;
2444 void free_vmcs(struct vmcs *vmcs)
2446 free_pages((unsigned long)vmcs, vmcs_config.order);
2450 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2452 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2454 if (!loaded_vmcs->vmcs)
2456 loaded_vmcs_clear(loaded_vmcs);
2457 free_vmcs(loaded_vmcs->vmcs);
2458 loaded_vmcs->vmcs = NULL;
2459 if (loaded_vmcs->msr_bitmap)
2460 free_page((unsigned long)loaded_vmcs->msr_bitmap);
2461 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2464 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2466 loaded_vmcs->vmcs = alloc_vmcs(false);
2467 if (!loaded_vmcs->vmcs)
2470 loaded_vmcs->shadow_vmcs = NULL;
2471 loaded_vmcs->hv_timer_soft_disabled = false;
2472 loaded_vmcs_init(loaded_vmcs);
2474 if (cpu_has_vmx_msr_bitmap()) {
2475 loaded_vmcs->msr_bitmap = (unsigned long *)
2476 __get_free_page(GFP_KERNEL_ACCOUNT);
2477 if (!loaded_vmcs->msr_bitmap)
2479 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2481 if (IS_ENABLED(CONFIG_HYPERV) &&
2482 static_branch_unlikely(&enable_evmcs) &&
2483 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2484 struct hv_enlightened_vmcs *evmcs =
2485 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2487 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2491 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2492 memset(&loaded_vmcs->controls_shadow, 0,
2493 sizeof(struct vmcs_controls_shadow));
2498 free_loaded_vmcs(loaded_vmcs);
2502 static void free_kvm_area(void)
2506 for_each_possible_cpu(cpu) {
2507 free_vmcs(per_cpu(vmxarea, cpu));
2508 per_cpu(vmxarea, cpu) = NULL;
2512 static __init int alloc_kvm_area(void)
2516 for_each_possible_cpu(cpu) {
2519 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2526 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2527 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2528 * revision_id reported by MSR_IA32_VMX_BASIC.
2530 * However, even though not explicitly documented by
2531 * TLFS, VMXArea passed as VMXON argument should
2532 * still be marked with revision_id reported by
2535 if (static_branch_unlikely(&enable_evmcs))
2536 vmcs->hdr.revision_id = vmcs_config.revision_id;
2538 per_cpu(vmxarea, cpu) = vmcs;
2543 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2544 struct kvm_segment *save)
2546 if (!emulate_invalid_guest_state) {
2548 * CS and SS RPL should be equal during guest entry according
2549 * to VMX spec, but in reality it is not always so. Since vcpu
2550 * is in the middle of the transition from real mode to
2551 * protected mode it is safe to assume that RPL 0 is a good
2554 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2555 save->selector &= ~SEGMENT_RPL_MASK;
2556 save->dpl = save->selector & SEGMENT_RPL_MASK;
2559 vmx_set_segment(vcpu, save, seg);
2562 static void enter_pmode(struct kvm_vcpu *vcpu)
2564 unsigned long flags;
2565 struct vcpu_vmx *vmx = to_vmx(vcpu);
2568 * Update real mode segment cache. It may be not up-to-date if sement
2569 * register was written while vcpu was in a guest mode.
2571 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2572 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2573 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2574 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2575 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2576 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2578 vmx->rmode.vm86_active = 0;
2580 vmx_segment_cache_clear(vmx);
2582 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2584 flags = vmcs_readl(GUEST_RFLAGS);
2585 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2586 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2587 vmcs_writel(GUEST_RFLAGS, flags);
2589 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2590 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2592 update_exception_bitmap(vcpu);
2594 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2595 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2596 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2597 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2598 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2599 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2602 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2604 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2605 struct kvm_segment var = *save;
2608 if (seg == VCPU_SREG_CS)
2611 if (!emulate_invalid_guest_state) {
2612 var.selector = var.base >> 4;
2613 var.base = var.base & 0xffff0;
2623 if (save->base & 0xf)
2624 printk_once(KERN_WARNING "kvm: segment base is not "
2625 "paragraph aligned when entering "
2626 "protected mode (seg=%d)", seg);
2629 vmcs_write16(sf->selector, var.selector);
2630 vmcs_writel(sf->base, var.base);
2631 vmcs_write32(sf->limit, var.limit);
2632 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2635 static void enter_rmode(struct kvm_vcpu *vcpu)
2637 unsigned long flags;
2638 struct vcpu_vmx *vmx = to_vmx(vcpu);
2639 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2641 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2642 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2643 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2644 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2645 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2646 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2647 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2649 vmx->rmode.vm86_active = 1;
2652 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2653 * vcpu. Warn the user that an update is overdue.
2655 if (!kvm_vmx->tss_addr)
2656 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2657 "called before entering vcpu\n");
2659 vmx_segment_cache_clear(vmx);
2661 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2662 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2663 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2665 flags = vmcs_readl(GUEST_RFLAGS);
2666 vmx->rmode.save_rflags = flags;
2668 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2670 vmcs_writel(GUEST_RFLAGS, flags);
2671 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2672 update_exception_bitmap(vcpu);
2674 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2675 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2676 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2677 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2678 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2679 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2681 kvm_mmu_reset_context(vcpu);
2684 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2686 struct vcpu_vmx *vmx = to_vmx(vcpu);
2687 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2692 vcpu->arch.efer = efer;
2693 if (efer & EFER_LMA) {
2694 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2697 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2699 msr->data = efer & ~EFER_LME;
2704 #ifdef CONFIG_X86_64
2706 static void enter_lmode(struct kvm_vcpu *vcpu)
2710 vmx_segment_cache_clear(to_vmx(vcpu));
2712 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2713 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2714 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2716 vmcs_write32(GUEST_TR_AR_BYTES,
2717 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2718 | VMX_AR_TYPE_BUSY_64_TSS);
2720 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2723 static void exit_lmode(struct kvm_vcpu *vcpu)
2725 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2726 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2731 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2733 int vpid = to_vmx(vcpu)->vpid;
2735 if (!vpid_sync_vcpu_addr(vpid, addr))
2736 vpid_sync_context(vpid);
2739 * If VPIDs are not supported or enabled, then the above is a no-op.
2740 * But we don't really need a TLB flush in that case anyway, because
2741 * each VM entry/exit includes an implicit flush when VPID is 0.
2745 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2747 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2749 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2750 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2753 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2755 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
2756 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2757 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2760 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2762 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2764 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2765 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2768 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2770 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2772 if (!test_bit(VCPU_EXREG_PDPTR,
2773 (unsigned long *)&vcpu->arch.regs_dirty))
2776 if (is_pae_paging(vcpu)) {
2777 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2778 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2779 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2780 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2784 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2786 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2788 if (is_pae_paging(vcpu)) {
2789 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2790 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2791 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2792 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2795 __set_bit(VCPU_EXREG_PDPTR,
2796 (unsigned long *)&vcpu->arch.regs_avail);
2797 __set_bit(VCPU_EXREG_PDPTR,
2798 (unsigned long *)&vcpu->arch.regs_dirty);
2801 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2803 struct kvm_vcpu *vcpu)
2805 struct vcpu_vmx *vmx = to_vmx(vcpu);
2807 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2808 vmx_decache_cr3(vcpu);
2809 if (!(cr0 & X86_CR0_PG)) {
2810 /* From paging/starting to nonpaging */
2811 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2812 CPU_BASED_CR3_STORE_EXITING);
2813 vcpu->arch.cr0 = cr0;
2814 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2815 } else if (!is_paging(vcpu)) {
2816 /* From nonpaging to paging */
2817 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2818 CPU_BASED_CR3_STORE_EXITING);
2819 vcpu->arch.cr0 = cr0;
2820 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2823 if (!(cr0 & X86_CR0_WP))
2824 *hw_cr0 &= ~X86_CR0_WP;
2827 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2829 struct vcpu_vmx *vmx = to_vmx(vcpu);
2830 unsigned long hw_cr0;
2832 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
2833 if (enable_unrestricted_guest)
2834 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2836 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
2838 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2841 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2845 #ifdef CONFIG_X86_64
2846 if (vcpu->arch.efer & EFER_LME) {
2847 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2849 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2854 if (enable_ept && !enable_unrestricted_guest)
2855 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2857 vmcs_writel(CR0_READ_SHADOW, cr0);
2858 vmcs_writel(GUEST_CR0, hw_cr0);
2859 vcpu->arch.cr0 = cr0;
2861 /* depends on vcpu->arch.cr0 to be set to a new value */
2862 vmx->emulation_required = emulation_required(vcpu);
2865 static int get_ept_level(struct kvm_vcpu *vcpu)
2867 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2872 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
2874 u64 eptp = VMX_EPTP_MT_WB;
2876 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
2878 if (enable_ept_ad_bits &&
2879 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
2880 eptp |= VMX_EPTP_AD_ENABLE_BIT;
2881 eptp |= (root_hpa & PAGE_MASK);
2886 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2888 struct kvm *kvm = vcpu->kvm;
2889 unsigned long guest_cr3;
2894 eptp = construct_eptp(vcpu, cr3);
2895 vmcs_write64(EPT_POINTER, eptp);
2897 if (kvm_x86_ops->tlb_remote_flush) {
2898 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2899 to_vmx(vcpu)->ept_pointer = eptp;
2900 to_kvm_vmx(kvm)->ept_pointers_match
2901 = EPT_POINTERS_CHECK;
2902 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2905 if (enable_unrestricted_guest || is_paging(vcpu) ||
2906 is_guest_mode(vcpu))
2907 guest_cr3 = kvm_read_cr3(vcpu);
2909 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
2910 ept_load_pdptrs(vcpu);
2913 vmcs_writel(GUEST_CR3, guest_cr3);
2916 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2918 struct vcpu_vmx *vmx = to_vmx(vcpu);
2920 * Pass through host's Machine Check Enable value to hw_cr4, which
2921 * is in force while we are in guest mode. Do not let guests control
2922 * this bit, even if host CR4.MCE == 0.
2924 unsigned long hw_cr4;
2926 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2927 if (enable_unrestricted_guest)
2928 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2929 else if (vmx->rmode.vm86_active)
2930 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2932 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
2934 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2935 if (cr4 & X86_CR4_UMIP) {
2936 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
2937 hw_cr4 &= ~X86_CR4_UMIP;
2938 } else if (!is_guest_mode(vcpu) ||
2939 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
2940 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
2944 if (cr4 & X86_CR4_VMXE) {
2946 * To use VMXON (and later other VMX instructions), a guest
2947 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2948 * So basically the check on whether to allow nested VMX
2949 * is here. We operate under the default treatment of SMM,
2950 * so VMX cannot be enabled under SMM.
2952 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
2956 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
2959 vcpu->arch.cr4 = cr4;
2961 if (!enable_unrestricted_guest) {
2963 if (!is_paging(vcpu)) {
2964 hw_cr4 &= ~X86_CR4_PAE;
2965 hw_cr4 |= X86_CR4_PSE;
2966 } else if (!(cr4 & X86_CR4_PAE)) {
2967 hw_cr4 &= ~X86_CR4_PAE;
2972 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2973 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
2974 * to be manually disabled when guest switches to non-paging
2977 * If !enable_unrestricted_guest, the CPU is always running
2978 * with CR0.PG=1 and CR4 needs to be modified.
2979 * If enable_unrestricted_guest, the CPU automatically
2980 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
2982 if (!is_paging(vcpu))
2983 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2986 vmcs_writel(CR4_READ_SHADOW, cr4);
2987 vmcs_writel(GUEST_CR4, hw_cr4);
2991 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
2993 struct vcpu_vmx *vmx = to_vmx(vcpu);
2996 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
2997 *var = vmx->rmode.segs[seg];
2998 if (seg == VCPU_SREG_TR
2999 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3001 var->base = vmx_read_guest_seg_base(vmx, seg);
3002 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3005 var->base = vmx_read_guest_seg_base(vmx, seg);
3006 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3007 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3008 ar = vmx_read_guest_seg_ar(vmx, seg);
3009 var->unusable = (ar >> 16) & 1;
3010 var->type = ar & 15;
3011 var->s = (ar >> 4) & 1;
3012 var->dpl = (ar >> 5) & 3;
3014 * Some userspaces do not preserve unusable property. Since usable
3015 * segment has to be present according to VMX spec we can use present
3016 * property to amend userspace bug by making unusable segment always
3017 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3018 * segment as unusable.
3020 var->present = !var->unusable;
3021 var->avl = (ar >> 12) & 1;
3022 var->l = (ar >> 13) & 1;
3023 var->db = (ar >> 14) & 1;
3024 var->g = (ar >> 15) & 1;
3027 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3029 struct kvm_segment s;
3031 if (to_vmx(vcpu)->rmode.vm86_active) {
3032 vmx_get_segment(vcpu, &s, seg);
3035 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3038 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3040 struct vcpu_vmx *vmx = to_vmx(vcpu);
3042 if (unlikely(vmx->rmode.vm86_active))
3045 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3046 return VMX_AR_DPL(ar);
3050 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3054 if (var->unusable || !var->present)
3057 ar = var->type & 15;
3058 ar |= (var->s & 1) << 4;
3059 ar |= (var->dpl & 3) << 5;
3060 ar |= (var->present & 1) << 7;
3061 ar |= (var->avl & 1) << 12;
3062 ar |= (var->l & 1) << 13;
3063 ar |= (var->db & 1) << 14;
3064 ar |= (var->g & 1) << 15;
3070 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3072 struct vcpu_vmx *vmx = to_vmx(vcpu);
3073 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3075 vmx_segment_cache_clear(vmx);
3077 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3078 vmx->rmode.segs[seg] = *var;
3079 if (seg == VCPU_SREG_TR)
3080 vmcs_write16(sf->selector, var->selector);
3082 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3086 vmcs_writel(sf->base, var->base);
3087 vmcs_write32(sf->limit, var->limit);
3088 vmcs_write16(sf->selector, var->selector);
3091 * Fix the "Accessed" bit in AR field of segment registers for older
3093 * IA32 arch specifies that at the time of processor reset the
3094 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3095 * is setting it to 0 in the userland code. This causes invalid guest
3096 * state vmexit when "unrestricted guest" mode is turned on.
3097 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3098 * tree. Newer qemu binaries with that qemu fix would not need this
3101 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3102 var->type |= 0x1; /* Accessed */
3104 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3107 vmx->emulation_required = emulation_required(vcpu);
3110 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3112 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3114 *db = (ar >> 14) & 1;
3115 *l = (ar >> 13) & 1;
3118 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3120 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3121 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3124 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3126 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3127 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3130 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3132 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3133 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3136 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3138 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3139 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3142 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3144 struct kvm_segment var;
3147 vmx_get_segment(vcpu, &var, seg);
3149 if (seg == VCPU_SREG_CS)
3151 ar = vmx_segment_access_rights(&var);
3153 if (var.base != (var.selector << 4))
3155 if (var.limit != 0xffff)
3163 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3165 struct kvm_segment cs;
3166 unsigned int cs_rpl;
3168 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3169 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3173 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3177 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3178 if (cs.dpl > cs_rpl)
3181 if (cs.dpl != cs_rpl)
3187 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3191 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3193 struct kvm_segment ss;
3194 unsigned int ss_rpl;
3196 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3197 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3201 if (ss.type != 3 && ss.type != 7)
3205 if (ss.dpl != ss_rpl) /* DPL != RPL */
3213 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3215 struct kvm_segment var;
3218 vmx_get_segment(vcpu, &var, seg);
3219 rpl = var.selector & SEGMENT_RPL_MASK;
3227 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3228 if (var.dpl < rpl) /* DPL < RPL */
3232 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3238 static bool tr_valid(struct kvm_vcpu *vcpu)
3240 struct kvm_segment tr;
3242 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3246 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3248 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3256 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3258 struct kvm_segment ldtr;
3260 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3264 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3274 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3276 struct kvm_segment cs, ss;
3278 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3279 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3281 return ((cs.selector & SEGMENT_RPL_MASK) ==
3282 (ss.selector & SEGMENT_RPL_MASK));
3286 * Check if guest state is valid. Returns true if valid, false if
3288 * We assume that registers are always usable
3290 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3292 if (enable_unrestricted_guest)
3295 /* real mode guest state checks */
3296 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3297 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3299 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3301 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3303 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3305 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3307 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3310 /* protected mode guest state checks */
3311 if (!cs_ss_rpl_check(vcpu))
3313 if (!code_segment_valid(vcpu))
3315 if (!stack_segment_valid(vcpu))
3317 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3319 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3321 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3323 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3325 if (!tr_valid(vcpu))
3327 if (!ldtr_valid(vcpu))
3331 * - Add checks on RIP
3332 * - Add checks on RFLAGS
3338 static int init_rmode_tss(struct kvm *kvm)
3344 idx = srcu_read_lock(&kvm->srcu);
3345 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
3346 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3349 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3350 r = kvm_write_guest_page(kvm, fn++, &data,
3351 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3354 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3357 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3361 r = kvm_write_guest_page(kvm, fn, &data,
3362 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3365 srcu_read_unlock(&kvm->srcu, idx);
3369 static int init_rmode_identity_map(struct kvm *kvm)
3371 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3373 kvm_pfn_t identity_map_pfn;
3376 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3377 mutex_lock(&kvm->slots_lock);
3379 if (likely(kvm_vmx->ept_identity_pagetable_done))
3382 if (!kvm_vmx->ept_identity_map_addr)
3383 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3384 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
3386 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3387 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
3391 idx = srcu_read_lock(&kvm->srcu);
3392 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3395 /* Set up identity-mapping pagetable for EPT in real mode */
3396 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3397 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3398 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3399 r = kvm_write_guest_page(kvm, identity_map_pfn,
3400 &tmp, i * sizeof(tmp), sizeof(tmp));
3404 kvm_vmx->ept_identity_pagetable_done = true;
3407 srcu_read_unlock(&kvm->srcu, idx);
3410 mutex_unlock(&kvm->slots_lock);
3414 static void seg_setup(int seg)
3416 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3419 vmcs_write16(sf->selector, 0);
3420 vmcs_writel(sf->base, 0);
3421 vmcs_write32(sf->limit, 0xffff);
3423 if (seg == VCPU_SREG_CS)
3424 ar |= 0x08; /* code segment */
3426 vmcs_write32(sf->ar_bytes, ar);
3429 static int alloc_apic_access_page(struct kvm *kvm)
3434 mutex_lock(&kvm->slots_lock);
3435 if (kvm->arch.apic_access_page_done)
3437 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3438 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3442 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3443 if (is_error_page(page)) {
3449 * Do not pin the page in memory, so that memory hot-unplug
3450 * is able to migrate it.
3453 kvm->arch.apic_access_page_done = true;
3455 mutex_unlock(&kvm->slots_lock);
3459 int allocate_vpid(void)
3465 spin_lock(&vmx_vpid_lock);
3466 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3467 if (vpid < VMX_NR_VPIDS)
3468 __set_bit(vpid, vmx_vpid_bitmap);
3471 spin_unlock(&vmx_vpid_lock);
3475 void free_vpid(int vpid)
3477 if (!enable_vpid || vpid == 0)
3479 spin_lock(&vmx_vpid_lock);
3480 __clear_bit(vpid, vmx_vpid_bitmap);
3481 spin_unlock(&vmx_vpid_lock);
3484 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3487 int f = sizeof(unsigned long);
3489 if (!cpu_has_vmx_msr_bitmap())
3492 if (static_branch_unlikely(&enable_evmcs))
3493 evmcs_touch_msr_bitmap();
3496 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3497 * have the write-low and read-high bitmap offsets the wrong way round.
3498 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3500 if (msr <= 0x1fff) {
3501 if (type & MSR_TYPE_R)
3503 __clear_bit(msr, msr_bitmap + 0x000 / f);
3505 if (type & MSR_TYPE_W)
3507 __clear_bit(msr, msr_bitmap + 0x800 / f);
3509 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3511 if (type & MSR_TYPE_R)
3513 __clear_bit(msr, msr_bitmap + 0x400 / f);
3515 if (type & MSR_TYPE_W)
3517 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3522 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3525 int f = sizeof(unsigned long);
3527 if (!cpu_has_vmx_msr_bitmap())
3530 if (static_branch_unlikely(&enable_evmcs))
3531 evmcs_touch_msr_bitmap();
3534 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3535 * have the write-low and read-high bitmap offsets the wrong way round.
3536 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3538 if (msr <= 0x1fff) {
3539 if (type & MSR_TYPE_R)
3541 __set_bit(msr, msr_bitmap + 0x000 / f);
3543 if (type & MSR_TYPE_W)
3545 __set_bit(msr, msr_bitmap + 0x800 / f);
3547 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3549 if (type & MSR_TYPE_R)
3551 __set_bit(msr, msr_bitmap + 0x400 / f);
3553 if (type & MSR_TYPE_W)
3555 __set_bit(msr, msr_bitmap + 0xc00 / f);
3560 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
3561 u32 msr, int type, bool value)
3564 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3566 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3569 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3573 if (cpu_has_secondary_exec_ctrls() &&
3574 (secondary_exec_controls_get(to_vmx(vcpu)) &
3575 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3576 mode |= MSR_BITMAP_MODE_X2APIC;
3577 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3578 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3584 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3589 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3590 unsigned word = msr / BITS_PER_LONG;
3591 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3592 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3595 if (mode & MSR_BITMAP_MODE_X2APIC) {
3597 * TPR reads and writes can be virtualized even if virtual interrupt
3598 * delivery is not in use.
3600 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3601 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3602 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3603 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3604 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3609 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3611 struct vcpu_vmx *vmx = to_vmx(vcpu);
3612 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3613 u8 mode = vmx_msr_bitmap_mode(vcpu);
3614 u8 changed = mode ^ vmx->msr_bitmap_mode;
3619 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3620 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3622 vmx->msr_bitmap_mode = mode;
3625 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx)
3627 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3628 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3631 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS,
3633 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE,
3635 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK,
3637 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH,
3639 for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3640 vmx_set_intercept_for_msr(msr_bitmap,
3641 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3642 vmx_set_intercept_for_msr(msr_bitmap,
3643 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3647 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
3649 return enable_apicv;
3652 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3654 struct vcpu_vmx *vmx = to_vmx(vcpu);
3659 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3660 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3661 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3664 rvi = vmx_get_rvi();
3666 vapic_page = vmx->nested.virtual_apic_map.hva;
3667 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3669 return ((rvi & 0xf0) > (vppr & 0xf0));
3672 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3676 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3678 if (vcpu->mode == IN_GUEST_MODE) {
3680 * The vector of interrupt to be delivered to vcpu had
3681 * been set in PIR before this function.
3683 * Following cases will be reached in this block, and
3684 * we always send a notification event in all cases as
3687 * Case 1: vcpu keeps in non-root mode. Sending a
3688 * notification event posts the interrupt to vcpu.
3690 * Case 2: vcpu exits to root mode and is still
3691 * runnable. PIR will be synced to vIRR before the
3692 * next vcpu entry. Sending a notification event in
3693 * this case has no effect, as vcpu is not in root
3696 * Case 3: vcpu exits to root mode and is blocked.
3697 * vcpu_block() has already synced PIR to vIRR and
3698 * never blocks vcpu if vIRR is not cleared. Therefore,
3699 * a blocked vcpu here does not wait for any requested
3700 * interrupts in PIR, and sending a notification event
3701 * which has no effect is safe here.
3704 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3711 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3714 struct vcpu_vmx *vmx = to_vmx(vcpu);
3716 if (is_guest_mode(vcpu) &&
3717 vector == vmx->nested.posted_intr_nv) {
3719 * If a posted intr is not recognized by hardware,
3720 * we will accomplish it in the next vmentry.
3722 vmx->nested.pi_pending = true;
3723 kvm_make_request(KVM_REQ_EVENT, vcpu);
3724 /* the PIR and ON have been set by L1. */
3725 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3726 kvm_vcpu_kick(vcpu);
3732 * Send interrupt to vcpu via posted interrupt way.
3733 * 1. If target vcpu is running(non-root mode), send posted interrupt
3734 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3735 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3736 * interrupt from PIR in next vmentry.
3738 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3740 struct vcpu_vmx *vmx = to_vmx(vcpu);
3743 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3747 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3750 /* If a previous notification has sent the IPI, nothing to do. */
3751 if (pi_test_and_set_on(&vmx->pi_desc))
3754 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
3755 kvm_vcpu_kick(vcpu);
3759 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3760 * will not change in the lifetime of the guest.
3761 * Note that host-state that does change is set elsewhere. E.g., host-state
3762 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3764 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
3768 unsigned long cr0, cr3, cr4;
3771 WARN_ON(cr0 & X86_CR0_TS);
3772 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
3775 * Save the most likely value for this task's CR3 in the VMCS.
3776 * We can't use __get_current_cr3_fast() because we're not atomic.
3779 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
3780 vmx->loaded_vmcs->host_state.cr3 = cr3;
3782 /* Save the most likely value for this task's CR4 in the VMCS. */
3783 cr4 = cr4_read_shadow();
3784 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
3785 vmx->loaded_vmcs->host_state.cr4 = cr4;
3787 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3788 #ifdef CONFIG_X86_64
3790 * Load null selectors, so we can avoid reloading them in
3791 * vmx_prepare_switch_to_host(), in case userspace uses
3792 * the null selectors too (the expected case).
3794 vmcs_write16(HOST_DS_SELECTOR, 0);
3795 vmcs_write16(HOST_ES_SELECTOR, 0);
3797 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3798 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3800 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3801 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3803 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */
3805 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
3807 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3808 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3809 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3810 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3812 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3813 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3814 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3817 if (cpu_has_load_ia32_efer())
3818 vmcs_write64(HOST_IA32_EFER, host_efer);
3821 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3823 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3825 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3826 if (is_guest_mode(&vmx->vcpu))
3827 vmx->vcpu.arch.cr4_guest_owned_bits &=
3828 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3829 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3832 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3834 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3836 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
3837 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3840 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3842 if (!enable_preemption_timer)
3843 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3845 return pin_based_exec_ctrl;
3848 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3850 struct vcpu_vmx *vmx = to_vmx(vcpu);
3852 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
3853 if (cpu_has_secondary_exec_ctrls()) {
3854 if (kvm_vcpu_apicv_active(vcpu))
3855 secondary_exec_controls_setbit(vmx,
3856 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3857 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3859 secondary_exec_controls_clearbit(vmx,
3860 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3861 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3864 if (cpu_has_vmx_msr_bitmap())
3865 vmx_update_msr_bitmap(vcpu);
3868 u32 vmx_exec_control(struct vcpu_vmx *vmx)
3870 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3872 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3873 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3875 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3876 exec_control &= ~CPU_BASED_TPR_SHADOW;
3877 #ifdef CONFIG_X86_64
3878 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3879 CPU_BASED_CR8_LOAD_EXITING;
3883 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3884 CPU_BASED_CR3_LOAD_EXITING |
3885 CPU_BASED_INVLPG_EXITING;
3886 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3887 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3888 CPU_BASED_MONITOR_EXITING);
3889 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3890 exec_control &= ~CPU_BASED_HLT_EXITING;
3891 return exec_control;
3895 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
3897 struct kvm_vcpu *vcpu = &vmx->vcpu;
3899 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3901 if (pt_mode == PT_MODE_SYSTEM)
3902 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
3903 if (!cpu_need_virtualize_apic_accesses(vcpu))
3904 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3906 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3908 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3909 enable_unrestricted_guest = 0;
3911 if (!enable_unrestricted_guest)
3912 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3913 if (kvm_pause_in_guest(vmx->vcpu.kvm))
3914 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3915 if (!kvm_vcpu_apicv_active(vcpu))
3916 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3917 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3918 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3920 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3921 * in vmx_set_cr4. */
3922 exec_control &= ~SECONDARY_EXEC_DESC;
3924 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3926 We can NOT enable shadow_vmcs here because we don't have yet
3929 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
3932 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
3934 if (vmx_xsaves_supported()) {
3935 /* Exposing XSAVES only when XSAVE is exposed */
3936 bool xsaves_enabled =
3937 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3938 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3940 if (!xsaves_enabled)
3941 exec_control &= ~SECONDARY_EXEC_XSAVES;
3945 vmx->nested.msrs.secondary_ctls_high |=
3946 SECONDARY_EXEC_XSAVES;
3948 vmx->nested.msrs.secondary_ctls_high &=
3949 ~SECONDARY_EXEC_XSAVES;
3953 if (vmx_rdtscp_supported()) {
3954 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3955 if (!rdtscp_enabled)
3956 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3960 vmx->nested.msrs.secondary_ctls_high |=
3961 SECONDARY_EXEC_RDTSCP;
3963 vmx->nested.msrs.secondary_ctls_high &=
3964 ~SECONDARY_EXEC_RDTSCP;
3968 if (vmx_invpcid_supported()) {
3969 /* Exposing INVPCID only when PCID is exposed */
3970 bool invpcid_enabled =
3971 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3972 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3974 if (!invpcid_enabled) {
3975 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3976 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3980 if (invpcid_enabled)
3981 vmx->nested.msrs.secondary_ctls_high |=
3982 SECONDARY_EXEC_ENABLE_INVPCID;
3984 vmx->nested.msrs.secondary_ctls_high &=
3985 ~SECONDARY_EXEC_ENABLE_INVPCID;
3989 if (vmx_rdrand_supported()) {
3990 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
3992 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
3996 vmx->nested.msrs.secondary_ctls_high |=
3997 SECONDARY_EXEC_RDRAND_EXITING;
3999 vmx->nested.msrs.secondary_ctls_high &=
4000 ~SECONDARY_EXEC_RDRAND_EXITING;
4004 if (vmx_rdseed_supported()) {
4005 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
4007 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
4011 vmx->nested.msrs.secondary_ctls_high |=
4012 SECONDARY_EXEC_RDSEED_EXITING;
4014 vmx->nested.msrs.secondary_ctls_high &=
4015 ~SECONDARY_EXEC_RDSEED_EXITING;
4019 vmx->secondary_exec_control = exec_control;
4022 static void ept_set_mmio_spte_mask(void)
4025 * EPT Misconfigurations can be generated if the value of bits 2:0
4026 * of an EPT paging-structure entry is 110b (write/execute).
4028 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
4029 VMX_EPT_MISCONFIG_WX_VALUE);
4032 #define VMX_XSS_EXIT_BITMAP 0
4035 * Sets up the vmcs for emulated real mode.
4037 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
4042 nested_vmx_vcpu_setup();
4044 if (cpu_has_vmx_msr_bitmap())
4045 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4047 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4050 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4051 vmx->hv_deadline_tsc = -1;
4053 exec_controls_set(vmx, vmx_exec_control(vmx));
4055 if (cpu_has_secondary_exec_ctrls()) {
4056 vmx_compute_secondary_exec_control(vmx);
4057 secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4060 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4061 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4062 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4063 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4064 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4066 vmcs_write16(GUEST_INTR_STATUS, 0);
4068 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4069 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4072 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4073 vmcs_write32(PLE_GAP, ple_gap);
4074 vmx->ple_window = ple_window;
4075 vmx->ple_window_dirty = true;
4078 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4079 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4080 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4082 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4083 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4084 vmx_set_constant_host_state(vmx);
4085 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4086 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4088 if (cpu_has_vmx_vmfunc())
4089 vmcs_write64(VM_FUNCTION_CONTROL, 0);
4091 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4092 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4093 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4094 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4095 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4097 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4098 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4100 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4101 u32 index = vmx_msr_index[i];
4102 u32 data_low, data_high;
4105 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4107 if (wrmsr_safe(index, data_low, data_high) < 0)
4109 vmx->guest_msrs[j].index = i;
4110 vmx->guest_msrs[j].data = 0;
4111 vmx->guest_msrs[j].mask = -1ull;
4115 vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4117 /* 22.2.1, 20.8.1 */
4118 vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4120 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
4121 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
4123 set_cr4_guest_host_mask(vmx);
4125 if (vmx_xsaves_supported())
4126 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4129 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4130 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4133 if (cpu_has_vmx_encls_vmexit())
4134 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4136 if (pt_mode == PT_MODE_HOST_GUEST) {
4137 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4138 /* Bit[6~0] are forced to 1, writes are ignored. */
4139 vmx->pt_desc.guest.output_mask = 0x7F;
4140 vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4144 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4146 struct vcpu_vmx *vmx = to_vmx(vcpu);
4147 struct msr_data apic_base_msr;
4150 vmx->rmode.vm86_active = 0;
4153 vcpu->arch.microcode_version = 0x100000000ULL;
4154 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4155 kvm_set_cr8(vcpu, 0);
4158 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4159 MSR_IA32_APICBASE_ENABLE;
4160 if (kvm_vcpu_is_reset_bsp(vcpu))
4161 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4162 apic_base_msr.host_initiated = true;
4163 kvm_set_apic_base(vcpu, &apic_base_msr);
4166 vmx_segment_cache_clear(vmx);
4168 seg_setup(VCPU_SREG_CS);
4169 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4170 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4172 seg_setup(VCPU_SREG_DS);
4173 seg_setup(VCPU_SREG_ES);
4174 seg_setup(VCPU_SREG_FS);
4175 seg_setup(VCPU_SREG_GS);
4176 seg_setup(VCPU_SREG_SS);
4178 vmcs_write16(GUEST_TR_SELECTOR, 0);
4179 vmcs_writel(GUEST_TR_BASE, 0);
4180 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4181 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4183 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4184 vmcs_writel(GUEST_LDTR_BASE, 0);
4185 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4186 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4189 vmcs_write32(GUEST_SYSENTER_CS, 0);
4190 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4191 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4192 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4195 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4196 kvm_rip_write(vcpu, 0xfff0);
4198 vmcs_writel(GUEST_GDTR_BASE, 0);
4199 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4201 vmcs_writel(GUEST_IDTR_BASE, 0);
4202 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4204 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4205 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4206 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4207 if (kvm_mpx_supported())
4208 vmcs_write64(GUEST_BNDCFGS, 0);
4212 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4214 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4215 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4216 if (cpu_need_tpr_shadow(vcpu))
4217 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4218 __pa(vcpu->arch.apic->regs));
4219 vmcs_write32(TPR_THRESHOLD, 0);
4222 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4225 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4227 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4228 vmx->vcpu.arch.cr0 = cr0;
4229 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4230 vmx_set_cr4(vcpu, 0);
4231 vmx_set_efer(vcpu, 0);
4233 update_exception_bitmap(vcpu);
4235 vpid_sync_context(vmx->vpid);
4237 vmx_clear_hlt(vcpu);
4240 static void enable_irq_window(struct kvm_vcpu *vcpu)
4242 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4245 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4248 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4249 enable_irq_window(vcpu);
4253 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
4256 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4258 struct vcpu_vmx *vmx = to_vmx(vcpu);
4260 int irq = vcpu->arch.interrupt.nr;
4262 trace_kvm_inj_virq(irq);
4264 ++vcpu->stat.irq_injections;
4265 if (vmx->rmode.vm86_active) {
4267 if (vcpu->arch.interrupt.soft)
4268 inc_eip = vcpu->arch.event_exit_inst_len;
4269 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4270 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4273 intr = irq | INTR_INFO_VALID_MASK;
4274 if (vcpu->arch.interrupt.soft) {
4275 intr |= INTR_TYPE_SOFT_INTR;
4276 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4277 vmx->vcpu.arch.event_exit_inst_len);
4279 intr |= INTR_TYPE_EXT_INTR;
4280 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4282 vmx_clear_hlt(vcpu);
4285 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4287 struct vcpu_vmx *vmx = to_vmx(vcpu);
4291 * Tracking the NMI-blocked state in software is built upon
4292 * finding the next open IRQ window. This, in turn, depends on
4293 * well-behaving guests: They have to keep IRQs disabled at
4294 * least as long as the NMI handler runs. Otherwise we may
4295 * cause NMI nesting, maybe breaking the guest. But as this is
4296 * highly unlikely, we can live with the residual risk.
4298 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4299 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4302 ++vcpu->stat.nmi_injections;
4303 vmx->loaded_vmcs->nmi_known_unmasked = false;
4305 if (vmx->rmode.vm86_active) {
4306 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4307 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4311 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4312 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4314 vmx_clear_hlt(vcpu);
4317 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4319 struct vcpu_vmx *vmx = to_vmx(vcpu);
4323 return vmx->loaded_vmcs->soft_vnmi_blocked;
4324 if (vmx->loaded_vmcs->nmi_known_unmasked)
4326 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4327 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4331 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4333 struct vcpu_vmx *vmx = to_vmx(vcpu);
4336 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4337 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4338 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4341 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4343 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4344 GUEST_INTR_STATE_NMI);
4346 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4347 GUEST_INTR_STATE_NMI);
4351 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4353 if (to_vmx(vcpu)->nested.nested_run_pending)
4357 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4360 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4361 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4362 | GUEST_INTR_STATE_NMI));
4365 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4367 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4368 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4369 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4370 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4373 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4377 if (enable_unrestricted_guest)
4380 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4384 to_kvm_vmx(kvm)->tss_addr = addr;
4385 return init_rmode_tss(kvm);
4388 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4390 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4394 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4399 * Update instruction length as we may reinject the exception
4400 * from user space while in guest debugging mode.
4402 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4403 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4404 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4408 if (vcpu->guest_debug &
4409 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4426 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4427 int vec, u32 err_code)
4430 * Instruction with address size override prefix opcode 0x67
4431 * Cause the #SS fault with 0 error code in VM86 mode.
4433 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4434 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4435 if (vcpu->arch.halt_request) {
4436 vcpu->arch.halt_request = 0;
4437 return kvm_vcpu_halt(vcpu);
4445 * Forward all other exceptions that are valid in real mode.
4446 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4447 * the required debugging infrastructure rework.
4449 kvm_queue_exception(vcpu, vec);
4454 * Trigger machine check on the host. We assume all the MSRs are already set up
4455 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4456 * We pass a fake environment to the machine check handler because we want
4457 * the guest to be always treated like user space, no matter what context
4458 * it used internally.
4460 static void kvm_machine_check(void)
4462 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4463 struct pt_regs regs = {
4464 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4465 .flags = X86_EFLAGS_IF,
4468 do_machine_check(®s, 0);
4472 static int handle_machine_check(struct kvm_vcpu *vcpu)
4474 /* handled by vmx_vcpu_run() */
4478 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4480 struct vcpu_vmx *vmx = to_vmx(vcpu);
4481 struct kvm_run *kvm_run = vcpu->run;
4482 u32 intr_info, ex_no, error_code;
4483 unsigned long cr2, rip, dr6;
4485 enum emulation_result er;
4487 vect_info = vmx->idt_vectoring_info;
4488 intr_info = vmx->exit_intr_info;
4490 if (is_machine_check(intr_info) || is_nmi(intr_info))
4491 return 1; /* handled by handle_exception_nmi_irqoff() */
4493 if (is_invalid_opcode(intr_info))
4494 return handle_ud(vcpu);
4497 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4498 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4500 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4501 WARN_ON_ONCE(!enable_vmware_backdoor);
4502 er = kvm_emulate_instruction(vcpu,
4503 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4504 if (er == EMULATE_USER_EXIT)
4506 else if (er != EMULATE_DONE)
4507 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4512 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4513 * MMIO, it is better to report an internal error.
4514 * See the comments in vmx_handle_exit.
4516 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4517 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4518 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4519 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4520 vcpu->run->internal.ndata = 3;
4521 vcpu->run->internal.data[0] = vect_info;
4522 vcpu->run->internal.data[1] = intr_info;
4523 vcpu->run->internal.data[2] = error_code;
4527 if (is_page_fault(intr_info)) {
4528 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4529 /* EPT won't cause page fault directly */
4530 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
4531 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4534 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4536 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4537 return handle_rmode_exception(vcpu, ex_no, error_code);
4541 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4544 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4545 if (!(vcpu->guest_debug &
4546 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4547 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4548 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4549 if (is_icebp(intr_info))
4550 skip_emulated_instruction(vcpu);
4552 kvm_queue_exception(vcpu, DB_VECTOR);
4555 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4556 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4560 * Update instruction length as we may reinject #BP from
4561 * user space while in guest debugging mode. Reading it for
4562 * #DB as well causes no harm, it is not used in that case.
4564 vmx->vcpu.arch.event_exit_inst_len =
4565 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4566 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4567 rip = kvm_rip_read(vcpu);
4568 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4569 kvm_run->debug.arch.exception = ex_no;
4572 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4573 kvm_run->ex.exception = ex_no;
4574 kvm_run->ex.error_code = error_code;
4580 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4582 ++vcpu->stat.irq_exits;
4586 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4588 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4589 vcpu->mmio_needed = 0;
4593 static int handle_io(struct kvm_vcpu *vcpu)
4595 unsigned long exit_qualification;
4596 int size, in, string;
4599 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4600 string = (exit_qualification & 16) != 0;
4602 ++vcpu->stat.io_exits;
4605 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4607 port = exit_qualification >> 16;
4608 size = (exit_qualification & 7) + 1;
4609 in = (exit_qualification & 8) != 0;
4611 return kvm_fast_pio(vcpu, size, port, in);
4615 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4618 * Patch in the VMCALL instruction:
4620 hypercall[0] = 0x0f;
4621 hypercall[1] = 0x01;
4622 hypercall[2] = 0xc1;
4625 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4626 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4628 if (is_guest_mode(vcpu)) {
4629 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4630 unsigned long orig_val = val;
4633 * We get here when L2 changed cr0 in a way that did not change
4634 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4635 * but did change L0 shadowed bits. So we first calculate the
4636 * effective cr0 value that L1 would like to write into the
4637 * hardware. It consists of the L2-owned bits from the new
4638 * value combined with the L1-owned bits from L1's guest_cr0.
4640 val = (val & ~vmcs12->cr0_guest_host_mask) |
4641 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4643 if (!nested_guest_cr0_valid(vcpu, val))
4646 if (kvm_set_cr0(vcpu, val))
4648 vmcs_writel(CR0_READ_SHADOW, orig_val);
4651 if (to_vmx(vcpu)->nested.vmxon &&
4652 !nested_host_cr0_valid(vcpu, val))
4655 return kvm_set_cr0(vcpu, val);
4659 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4661 if (is_guest_mode(vcpu)) {
4662 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4663 unsigned long orig_val = val;
4665 /* analogously to handle_set_cr0 */
4666 val = (val & ~vmcs12->cr4_guest_host_mask) |
4667 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4668 if (kvm_set_cr4(vcpu, val))
4670 vmcs_writel(CR4_READ_SHADOW, orig_val);
4673 return kvm_set_cr4(vcpu, val);
4676 static int handle_desc(struct kvm_vcpu *vcpu)
4678 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4679 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4682 static int handle_cr(struct kvm_vcpu *vcpu)
4684 unsigned long exit_qualification, val;
4690 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4691 cr = exit_qualification & 15;
4692 reg = (exit_qualification >> 8) & 15;
4693 switch ((exit_qualification >> 4) & 3) {
4694 case 0: /* mov to cr */
4695 val = kvm_register_readl(vcpu, reg);
4696 trace_kvm_cr_write(cr, val);
4699 err = handle_set_cr0(vcpu, val);
4700 return kvm_complete_insn_gp(vcpu, err);
4702 WARN_ON_ONCE(enable_unrestricted_guest);
4703 err = kvm_set_cr3(vcpu, val);
4704 return kvm_complete_insn_gp(vcpu, err);
4706 err = handle_set_cr4(vcpu, val);
4707 return kvm_complete_insn_gp(vcpu, err);
4709 u8 cr8_prev = kvm_get_cr8(vcpu);
4711 err = kvm_set_cr8(vcpu, cr8);
4712 ret = kvm_complete_insn_gp(vcpu, err);
4713 if (lapic_in_kernel(vcpu))
4715 if (cr8_prev <= cr8)
4718 * TODO: we might be squashing a
4719 * KVM_GUESTDBG_SINGLESTEP-triggered
4720 * KVM_EXIT_DEBUG here.
4722 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4728 WARN_ONCE(1, "Guest should always own CR0.TS");
4729 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4730 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4731 return kvm_skip_emulated_instruction(vcpu);
4732 case 1: /*mov from cr*/
4735 WARN_ON_ONCE(enable_unrestricted_guest);
4736 val = kvm_read_cr3(vcpu);
4737 kvm_register_write(vcpu, reg, val);
4738 trace_kvm_cr_read(cr, val);
4739 return kvm_skip_emulated_instruction(vcpu);
4741 val = kvm_get_cr8(vcpu);
4742 kvm_register_write(vcpu, reg, val);
4743 trace_kvm_cr_read(cr, val);
4744 return kvm_skip_emulated_instruction(vcpu);
4748 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4749 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4750 kvm_lmsw(vcpu, val);
4752 return kvm_skip_emulated_instruction(vcpu);
4756 vcpu->run->exit_reason = 0;
4757 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4758 (int)(exit_qualification >> 4) & 3, cr);
4762 static int handle_dr(struct kvm_vcpu *vcpu)
4764 unsigned long exit_qualification;
4767 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4768 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4770 /* First, if DR does not exist, trigger UD */
4771 if (!kvm_require_dr(vcpu, dr))
4774 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4775 if (!kvm_require_cpl(vcpu, 0))
4777 dr7 = vmcs_readl(GUEST_DR7);
4780 * As the vm-exit takes precedence over the debug trap, we
4781 * need to emulate the latter, either for the host or the
4782 * guest debugging itself.
4784 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4785 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4786 vcpu->run->debug.arch.dr7 = dr7;
4787 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
4788 vcpu->run->debug.arch.exception = DB_VECTOR;
4789 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4792 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
4793 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
4794 kvm_queue_exception(vcpu, DB_VECTOR);
4799 if (vcpu->guest_debug == 0) {
4800 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4803 * No more DR vmexits; force a reload of the debug registers
4804 * and reenter on this instruction. The next vmexit will
4805 * retrieve the full state of the debug registers.
4807 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4811 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4812 if (exit_qualification & TYPE_MOV_FROM_DR) {
4815 if (kvm_get_dr(vcpu, dr, &val))
4817 kvm_register_write(vcpu, reg, val);
4819 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4822 return kvm_skip_emulated_instruction(vcpu);
4825 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4827 return vcpu->arch.dr6;
4830 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4834 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4836 get_debugreg(vcpu->arch.db[0], 0);
4837 get_debugreg(vcpu->arch.db[1], 1);
4838 get_debugreg(vcpu->arch.db[2], 2);
4839 get_debugreg(vcpu->arch.db[3], 3);
4840 get_debugreg(vcpu->arch.dr6, 6);
4841 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4843 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
4844 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
4847 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4849 vmcs_writel(GUEST_DR7, val);
4852 static int handle_cpuid(struct kvm_vcpu *vcpu)
4854 return kvm_emulate_cpuid(vcpu);
4857 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4859 u32 ecx = kvm_rcx_read(vcpu);
4860 struct msr_data msr_info;
4862 msr_info.index = ecx;
4863 msr_info.host_initiated = false;
4864 if (vmx_get_msr(vcpu, &msr_info)) {
4865 trace_kvm_msr_read_ex(ecx);
4866 kvm_inject_gp(vcpu, 0);
4870 trace_kvm_msr_read(ecx, msr_info.data);
4872 kvm_rax_write(vcpu, msr_info.data & -1u);
4873 kvm_rdx_write(vcpu, (msr_info.data >> 32) & -1u);
4874 return kvm_skip_emulated_instruction(vcpu);
4877 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4879 struct msr_data msr;
4880 u32 ecx = kvm_rcx_read(vcpu);
4881 u64 data = kvm_read_edx_eax(vcpu);
4885 msr.host_initiated = false;
4886 if (kvm_set_msr(vcpu, &msr) != 0) {
4887 trace_kvm_msr_write_ex(ecx, data);
4888 kvm_inject_gp(vcpu, 0);
4892 trace_kvm_msr_write(ecx, data);
4893 return kvm_skip_emulated_instruction(vcpu);
4896 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4898 kvm_apic_update_ppr(vcpu);
4902 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4904 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING);
4906 kvm_make_request(KVM_REQ_EVENT, vcpu);
4908 ++vcpu->stat.irq_window_exits;
4912 static int handle_halt(struct kvm_vcpu *vcpu)
4914 return kvm_emulate_halt(vcpu);
4917 static int handle_vmcall(struct kvm_vcpu *vcpu)
4919 return kvm_emulate_hypercall(vcpu);
4922 static int handle_invd(struct kvm_vcpu *vcpu)
4924 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4927 static int handle_invlpg(struct kvm_vcpu *vcpu)
4929 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4931 kvm_mmu_invlpg(vcpu, exit_qualification);
4932 return kvm_skip_emulated_instruction(vcpu);
4935 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4939 err = kvm_rdpmc(vcpu);
4940 return kvm_complete_insn_gp(vcpu, err);
4943 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4945 return kvm_emulate_wbinvd(vcpu);
4948 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4950 u64 new_bv = kvm_read_edx_eax(vcpu);
4951 u32 index = kvm_rcx_read(vcpu);
4953 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4954 return kvm_skip_emulated_instruction(vcpu);
4958 static int handle_xsaves(struct kvm_vcpu *vcpu)
4960 kvm_skip_emulated_instruction(vcpu);
4961 WARN(1, "this should never happen\n");
4965 static int handle_xrstors(struct kvm_vcpu *vcpu)
4967 kvm_skip_emulated_instruction(vcpu);
4968 WARN(1, "this should never happen\n");
4972 static int handle_apic_access(struct kvm_vcpu *vcpu)
4974 if (likely(fasteoi)) {
4975 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4976 int access_type, offset;
4978 access_type = exit_qualification & APIC_ACCESS_TYPE;
4979 offset = exit_qualification & APIC_ACCESS_OFFSET;
4981 * Sane guest uses MOV to write EOI, with written value
4982 * not cared. So make a short-circuit here by avoiding
4983 * heavy instruction emulation.
4985 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4986 (offset == APIC_EOI)) {
4987 kvm_lapic_set_eoi(vcpu);
4988 return kvm_skip_emulated_instruction(vcpu);
4991 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
4994 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4996 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4997 int vector = exit_qualification & 0xff;
4999 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5000 kvm_apic_set_eoi_accelerated(vcpu, vector);
5004 static int handle_apic_write(struct kvm_vcpu *vcpu)
5006 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5007 u32 offset = exit_qualification & 0xfff;
5009 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5010 kvm_apic_write_nodecode(vcpu, offset);
5014 static int handle_task_switch(struct kvm_vcpu *vcpu)
5016 struct vcpu_vmx *vmx = to_vmx(vcpu);
5017 unsigned long exit_qualification;
5018 bool has_error_code = false;
5021 int reason, type, idt_v, idt_index;
5023 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5024 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5025 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5027 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5029 reason = (u32)exit_qualification >> 30;
5030 if (reason == TASK_SWITCH_GATE && idt_v) {
5032 case INTR_TYPE_NMI_INTR:
5033 vcpu->arch.nmi_injected = false;
5034 vmx_set_nmi_mask(vcpu, true);
5036 case INTR_TYPE_EXT_INTR:
5037 case INTR_TYPE_SOFT_INTR:
5038 kvm_clear_interrupt_queue(vcpu);
5040 case INTR_TYPE_HARD_EXCEPTION:
5041 if (vmx->idt_vectoring_info &
5042 VECTORING_INFO_DELIVER_CODE_MASK) {
5043 has_error_code = true;
5045 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5048 case INTR_TYPE_SOFT_EXCEPTION:
5049 kvm_clear_exception_queue(vcpu);
5055 tss_selector = exit_qualification;
5057 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5058 type != INTR_TYPE_EXT_INTR &&
5059 type != INTR_TYPE_NMI_INTR))
5060 skip_emulated_instruction(vcpu);
5062 if (kvm_task_switch(vcpu, tss_selector,
5063 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5064 has_error_code, error_code) == EMULATE_FAIL) {
5065 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5066 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5067 vcpu->run->internal.ndata = 0;
5072 * TODO: What about debug traps on tss switch?
5073 * Are we supposed to inject them and update dr6?
5079 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5081 unsigned long exit_qualification;
5085 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5088 * EPT violation happened while executing iret from NMI,
5089 * "blocked by NMI" bit has to be set before next VM entry.
5090 * There are errata that may cause this bit to not be set:
5093 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5095 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5096 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5098 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5099 trace_kvm_page_fault(gpa, exit_qualification);
5101 /* Is it a read fault? */
5102 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5103 ? PFERR_USER_MASK : 0;
5104 /* Is it a write fault? */
5105 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5106 ? PFERR_WRITE_MASK : 0;
5107 /* Is it a fetch fault? */
5108 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5109 ? PFERR_FETCH_MASK : 0;
5110 /* ept page table entry is present? */
5111 error_code |= (exit_qualification &
5112 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5113 EPT_VIOLATION_EXECUTABLE))
5114 ? PFERR_PRESENT_MASK : 0;
5116 error_code |= (exit_qualification & 0x100) != 0 ?
5117 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5119 vcpu->arch.exit_qualification = exit_qualification;
5120 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5123 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5128 * A nested guest cannot optimize MMIO vmexits, because we have an
5129 * nGPA here instead of the required GPA.
5131 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5132 if (!is_guest_mode(vcpu) &&
5133 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5134 trace_kvm_fast_mmio(gpa);
5136 * Doing kvm_skip_emulated_instruction() depends on undefined
5137 * behavior: Intel's manual doesn't mandate
5138 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
5139 * occurs and while on real hardware it was observed to be set,
5140 * other hypervisors (namely Hyper-V) don't set it, we end up
5141 * advancing IP with some random value. Disable fast mmio when
5142 * running nested and keep it for real hardware in hope that
5143 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
5145 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
5146 return kvm_skip_emulated_instruction(vcpu);
5148 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
5152 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5155 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5157 WARN_ON_ONCE(!enable_vnmi);
5158 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING);
5159 ++vcpu->stat.nmi_window_exits;
5160 kvm_make_request(KVM_REQ_EVENT, vcpu);
5165 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5167 struct vcpu_vmx *vmx = to_vmx(vcpu);
5168 enum emulation_result err = EMULATE_DONE;
5170 bool intr_window_requested;
5171 unsigned count = 130;
5174 * We should never reach the point where we are emulating L2
5175 * due to invalid guest state as that means we incorrectly
5176 * allowed a nested VMEntry with an invalid vmcs12.
5178 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
5180 intr_window_requested = exec_controls_get(vmx) &
5181 CPU_BASED_VIRTUAL_INTR_PENDING;
5183 while (vmx->emulation_required && count-- != 0) {
5184 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5185 return handle_interrupt_window(&vmx->vcpu);
5187 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5190 err = kvm_emulate_instruction(vcpu, 0);
5192 if (err == EMULATE_USER_EXIT) {
5193 ++vcpu->stat.mmio_exits;
5198 if (err != EMULATE_DONE)
5199 goto emulation_error;
5201 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5202 vcpu->arch.exception.pending)
5203 goto emulation_error;
5205 if (vcpu->arch.halt_request) {
5206 vcpu->arch.halt_request = 0;
5207 ret = kvm_vcpu_halt(vcpu);
5211 if (signal_pending(current))
5221 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5222 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5223 vcpu->run->internal.ndata = 0;
5227 static void grow_ple_window(struct kvm_vcpu *vcpu)
5229 struct vcpu_vmx *vmx = to_vmx(vcpu);
5230 int old = vmx->ple_window;
5232 vmx->ple_window = __grow_ple_window(old, ple_window,
5236 if (vmx->ple_window != old)
5237 vmx->ple_window_dirty = true;
5239 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5242 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5244 struct vcpu_vmx *vmx = to_vmx(vcpu);
5245 int old = vmx->ple_window;
5247 vmx->ple_window = __shrink_ple_window(old, ple_window,
5251 if (vmx->ple_window != old)
5252 vmx->ple_window_dirty = true;
5254 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5258 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
5260 static void wakeup_handler(void)
5262 struct kvm_vcpu *vcpu;
5263 int cpu = smp_processor_id();
5265 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5266 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
5267 blocked_vcpu_list) {
5268 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
5270 if (pi_test_on(pi_desc) == 1)
5271 kvm_vcpu_kick(vcpu);
5273 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
5276 static void vmx_enable_tdp(void)
5278 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5279 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5280 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5281 0ull, VMX_EPT_EXECUTABLE_MASK,
5282 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5283 VMX_EPT_RWX_MASK, 0ull);
5285 ept_set_mmio_spte_mask();
5290 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5291 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5293 static int handle_pause(struct kvm_vcpu *vcpu)
5295 if (!kvm_pause_in_guest(vcpu->kvm))
5296 grow_ple_window(vcpu);
5299 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5300 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5301 * never set PAUSE_EXITING and just set PLE if supported,
5302 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5304 kvm_vcpu_on_spin(vcpu, true);
5305 return kvm_skip_emulated_instruction(vcpu);
5308 static int handle_nop(struct kvm_vcpu *vcpu)
5310 return kvm_skip_emulated_instruction(vcpu);
5313 static int handle_mwait(struct kvm_vcpu *vcpu)
5315 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5316 return handle_nop(vcpu);
5319 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5321 kvm_queue_exception(vcpu, UD_VECTOR);
5325 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5330 static int handle_monitor(struct kvm_vcpu *vcpu)
5332 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5333 return handle_nop(vcpu);
5336 static int handle_invpcid(struct kvm_vcpu *vcpu)
5338 u32 vmx_instruction_info;
5342 struct x86_exception e;
5344 unsigned long roots_to_free = 0;
5350 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5351 kvm_queue_exception(vcpu, UD_VECTOR);
5355 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5356 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5359 kvm_inject_gp(vcpu, 0);
5363 /* According to the Intel instruction reference, the memory operand
5364 * is read even if it isn't needed (e.g., for type==all)
5366 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5367 vmx_instruction_info, false,
5368 sizeof(operand), &gva))
5371 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
5372 kvm_inject_page_fault(vcpu, &e);
5376 if (operand.pcid >> 12 != 0) {
5377 kvm_inject_gp(vcpu, 0);
5381 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
5384 case INVPCID_TYPE_INDIV_ADDR:
5385 if ((!pcid_enabled && (operand.pcid != 0)) ||
5386 is_noncanonical_address(operand.gla, vcpu)) {
5387 kvm_inject_gp(vcpu, 0);
5390 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5391 return kvm_skip_emulated_instruction(vcpu);
5393 case INVPCID_TYPE_SINGLE_CTXT:
5394 if (!pcid_enabled && (operand.pcid != 0)) {
5395 kvm_inject_gp(vcpu, 0);
5399 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5400 kvm_mmu_sync_roots(vcpu);
5401 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5404 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5405 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5407 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
5409 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5411 * If neither the current cr3 nor any of the prev_roots use the
5412 * given PCID, then nothing needs to be done here because a
5413 * resync will happen anyway before switching to any other CR3.
5416 return kvm_skip_emulated_instruction(vcpu);
5418 case INVPCID_TYPE_ALL_NON_GLOBAL:
5420 * Currently, KVM doesn't mark global entries in the shadow
5421 * page tables, so a non-global flush just degenerates to a
5422 * global flush. If needed, we could optimize this later by
5423 * keeping track of global entries in shadow page tables.
5427 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5428 kvm_mmu_unload(vcpu);
5429 return kvm_skip_emulated_instruction(vcpu);
5432 BUG(); /* We have already checked above that type <= 3 */
5436 static int handle_pml_full(struct kvm_vcpu *vcpu)
5438 unsigned long exit_qualification;
5440 trace_kvm_pml_full(vcpu->vcpu_id);
5442 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5445 * PML buffer FULL happened while executing iret from NMI,
5446 * "blocked by NMI" bit has to be set before next VM entry.
5448 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5450 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5451 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5452 GUEST_INTR_STATE_NMI);
5455 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5456 * here.., and there's no userspace involvement needed for PML.
5461 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5463 struct vcpu_vmx *vmx = to_vmx(vcpu);
5465 if (!vmx->req_immediate_exit &&
5466 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled))
5467 kvm_lapic_expired_hv_timer(vcpu);
5473 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5474 * are overwritten by nested_vmx_setup() when nested=1.
5476 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5478 kvm_queue_exception(vcpu, UD_VECTOR);
5482 static int handle_encls(struct kvm_vcpu *vcpu)
5485 * SGX virtualization is not yet supported. There is no software
5486 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5487 * to prevent the guest from executing ENCLS.
5489 kvm_queue_exception(vcpu, UD_VECTOR);
5494 * The exit handlers return 1 if the exit was handled fully and guest execution
5495 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5496 * to be done to userspace and return 0.
5498 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5499 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi,
5500 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5501 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5502 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5503 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5504 [EXIT_REASON_CR_ACCESS] = handle_cr,
5505 [EXIT_REASON_DR_ACCESS] = handle_dr,
5506 [EXIT_REASON_CPUID] = handle_cpuid,
5507 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5508 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5509 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5510 [EXIT_REASON_HLT] = handle_halt,
5511 [EXIT_REASON_INVD] = handle_invd,
5512 [EXIT_REASON_INVLPG] = handle_invlpg,
5513 [EXIT_REASON_RDPMC] = handle_rdpmc,
5514 [EXIT_REASON_VMCALL] = handle_vmcall,
5515 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5516 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5517 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5518 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5519 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5520 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5521 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5522 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5523 [EXIT_REASON_VMON] = handle_vmx_instruction,
5524 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5525 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5526 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5527 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5528 [EXIT_REASON_WBINVD] = handle_wbinvd,
5529 [EXIT_REASON_XSETBV] = handle_xsetbv,
5530 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5531 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5532 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5533 [EXIT_REASON_LDTR_TR] = handle_desc,
5534 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5535 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5536 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5537 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5538 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5539 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5540 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5541 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5542 [EXIT_REASON_RDRAND] = handle_invalid_op,
5543 [EXIT_REASON_RDSEED] = handle_invalid_op,
5544 [EXIT_REASON_XSAVES] = handle_xsaves,
5545 [EXIT_REASON_XRSTORS] = handle_xrstors,
5546 [EXIT_REASON_PML_FULL] = handle_pml_full,
5547 [EXIT_REASON_INVPCID] = handle_invpcid,
5548 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5549 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5550 [EXIT_REASON_ENCLS] = handle_encls,
5553 static const int kvm_vmx_max_exit_handlers =
5554 ARRAY_SIZE(kvm_vmx_exit_handlers);
5556 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5558 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5559 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5562 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5565 __free_page(vmx->pml_pg);
5570 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5572 struct vcpu_vmx *vmx = to_vmx(vcpu);
5576 pml_idx = vmcs_read16(GUEST_PML_INDEX);
5578 /* Do nothing if PML buffer is empty */
5579 if (pml_idx == (PML_ENTITY_NUM - 1))
5582 /* PML index always points to next available PML buffer entity */
5583 if (pml_idx >= PML_ENTITY_NUM)
5588 pml_buf = page_address(vmx->pml_pg);
5589 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5592 gpa = pml_buf[pml_idx];
5593 WARN_ON(gpa & (PAGE_SIZE - 1));
5594 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5597 /* reset PML index */
5598 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5602 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5603 * Called before reporting dirty_bitmap to userspace.
5605 static void kvm_flush_pml_buffers(struct kvm *kvm)
5608 struct kvm_vcpu *vcpu;
5610 * We only need to kick vcpu out of guest mode here, as PML buffer
5611 * is flushed at beginning of all VMEXITs, and it's obvious that only
5612 * vcpus running in guest are possible to have unflushed GPAs in PML
5615 kvm_for_each_vcpu(i, vcpu, kvm)
5616 kvm_vcpu_kick(vcpu);
5619 static void vmx_dump_sel(char *name, uint32_t sel)
5621 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5622 name, vmcs_read16(sel),
5623 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5624 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5625 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5628 static void vmx_dump_dtsel(char *name, uint32_t limit)
5630 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5631 name, vmcs_read32(limit),
5632 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5635 void dump_vmcs(void)
5637 u32 vmentry_ctl, vmexit_ctl;
5638 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5643 if (!dump_invalid_vmcs) {
5644 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5648 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5649 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5650 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5651 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5652 cr4 = vmcs_readl(GUEST_CR4);
5653 efer = vmcs_read64(GUEST_IA32_EFER);
5654 secondary_exec_control = 0;
5655 if (cpu_has_secondary_exec_ctrls())
5656 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5658 pr_err("*** Guest State ***\n");
5659 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5660 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5661 vmcs_readl(CR0_GUEST_HOST_MASK));
5662 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5663 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5664 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5665 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5666 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5668 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5669 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5670 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5671 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5673 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5674 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5675 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5676 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5677 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5678 vmcs_readl(GUEST_SYSENTER_ESP),
5679 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5680 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5681 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5682 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5683 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5684 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5685 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5686 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5687 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5688 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5689 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5690 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5691 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5692 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5693 efer, vmcs_read64(GUEST_IA32_PAT));
5694 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5695 vmcs_read64(GUEST_IA32_DEBUGCTL),
5696 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5697 if (cpu_has_load_perf_global_ctrl() &&
5698 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5699 pr_err("PerfGlobCtl = 0x%016llx\n",
5700 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5701 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5702 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5703 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5704 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5705 vmcs_read32(GUEST_ACTIVITY_STATE));
5706 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5707 pr_err("InterruptStatus = %04x\n",
5708 vmcs_read16(GUEST_INTR_STATUS));
5710 pr_err("*** Host State ***\n");
5711 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5712 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5713 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5714 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5715 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5716 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5717 vmcs_read16(HOST_TR_SELECTOR));
5718 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5719 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5720 vmcs_readl(HOST_TR_BASE));
5721 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5722 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5723 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5724 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5725 vmcs_readl(HOST_CR4));
5726 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5727 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5728 vmcs_read32(HOST_IA32_SYSENTER_CS),
5729 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5730 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5731 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5732 vmcs_read64(HOST_IA32_EFER),
5733 vmcs_read64(HOST_IA32_PAT));
5734 if (cpu_has_load_perf_global_ctrl() &&
5735 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5736 pr_err("PerfGlobCtl = 0x%016llx\n",
5737 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5739 pr_err("*** Control State ***\n");
5740 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5741 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5742 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5743 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5744 vmcs_read32(EXCEPTION_BITMAP),
5745 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5746 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5747 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5748 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5749 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5750 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5751 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5752 vmcs_read32(VM_EXIT_INTR_INFO),
5753 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5754 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5755 pr_err(" reason=%08x qualification=%016lx\n",
5756 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5757 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5758 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5759 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5760 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5761 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5762 pr_err("TSC Multiplier = 0x%016llx\n",
5763 vmcs_read64(TSC_MULTIPLIER));
5764 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5765 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5766 u16 status = vmcs_read16(GUEST_INTR_STATUS);
5767 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5769 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5770 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5771 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5772 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5774 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5775 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5776 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5777 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5778 n = vmcs_read32(CR3_TARGET_COUNT);
5779 for (i = 0; i + 1 < n; i += 4)
5780 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5781 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5782 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5784 pr_err("CR3 target%u=%016lx\n",
5785 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5786 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5787 pr_err("PLE Gap=%08x Window=%08x\n",
5788 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5789 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5790 pr_err("Virtual processor ID = 0x%04x\n",
5791 vmcs_read16(VIRTUAL_PROCESSOR_ID));
5795 * The guest has exited. See if we can fix it or if we need userspace
5798 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5800 struct vcpu_vmx *vmx = to_vmx(vcpu);
5801 u32 exit_reason = vmx->exit_reason;
5802 u32 vectoring_info = vmx->idt_vectoring_info;
5804 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5807 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5808 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5809 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5810 * mode as if vcpus is in root mode, the PML buffer must has been
5814 vmx_flush_pml_buffer(vcpu);
5816 /* If guest state is invalid, start emulating */
5817 if (vmx->emulation_required)
5818 return handle_invalid_guest_state(vcpu);
5820 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5821 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
5823 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5825 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5826 vcpu->run->fail_entry.hardware_entry_failure_reason
5831 if (unlikely(vmx->fail)) {
5833 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5834 vcpu->run->fail_entry.hardware_entry_failure_reason
5835 = vmcs_read32(VM_INSTRUCTION_ERROR);
5841 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5842 * delivery event since it indicates guest is accessing MMIO.
5843 * The vm-exit can be triggered again after return to guest that
5844 * will cause infinite loop.
5846 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5847 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5848 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5849 exit_reason != EXIT_REASON_PML_FULL &&
5850 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5851 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5852 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5853 vcpu->run->internal.ndata = 3;
5854 vcpu->run->internal.data[0] = vectoring_info;
5855 vcpu->run->internal.data[1] = exit_reason;
5856 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5857 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5858 vcpu->run->internal.ndata++;
5859 vcpu->run->internal.data[3] =
5860 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5865 if (unlikely(!enable_vnmi &&
5866 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5867 if (vmx_interrupt_allowed(vcpu)) {
5868 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5869 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5870 vcpu->arch.nmi_pending) {
5872 * This CPU don't support us in finding the end of an
5873 * NMI-blocked window if the guest runs with IRQs
5874 * disabled. So we pull the trigger after 1 s of
5875 * futile waiting, but inform the user about this.
5877 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5878 "state on VCPU %d after 1 s timeout\n",
5879 __func__, vcpu->vcpu_id);
5880 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5884 if (exit_reason < kvm_vmx_max_exit_handlers
5885 && kvm_vmx_exit_handlers[exit_reason])
5886 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5888 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5890 kvm_queue_exception(vcpu, UD_VECTOR);
5896 * Software based L1D cache flush which is used when microcode providing
5897 * the cache control MSR is not loaded.
5899 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5900 * flush it is required to read in 64 KiB because the replacement algorithm
5901 * is not exactly LRU. This could be sized at runtime via topology
5902 * information but as all relevant affected CPUs have 32KiB L1D cache size
5903 * there is no point in doing so.
5905 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
5907 int size = PAGE_SIZE << L1D_CACHE_ORDER;
5910 * This code is only executed when the the flush mode is 'cond' or
5913 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5917 * Clear the per-vcpu flush bit, it gets set again
5918 * either from vcpu_run() or from one of the unsafe
5921 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5922 vcpu->arch.l1tf_flush_l1d = false;
5925 * Clear the per-cpu flush bit, it gets set again from
5926 * the interrupt handlers.
5928 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5929 kvm_clear_cpu_l1tf_flush_l1d();
5935 vcpu->stat.l1d_flush++;
5937 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5938 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5943 /* First ensure the pages are in the TLB */
5944 "xorl %%eax, %%eax\n"
5945 ".Lpopulate_tlb:\n\t"
5946 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5947 "addl $4096, %%eax\n\t"
5948 "cmpl %%eax, %[size]\n\t"
5949 "jne .Lpopulate_tlb\n\t"
5950 "xorl %%eax, %%eax\n\t"
5952 /* Now fill the cache */
5953 "xorl %%eax, %%eax\n"
5955 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5956 "addl $64, %%eax\n\t"
5957 "cmpl %%eax, %[size]\n\t"
5958 "jne .Lfill_cache\n\t"
5960 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5962 : "eax", "ebx", "ecx", "edx");
5965 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5967 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5969 if (is_guest_mode(vcpu) &&
5970 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5973 if (irr == -1 || tpr < irr) {
5974 vmcs_write32(TPR_THRESHOLD, 0);
5978 vmcs_write32(TPR_THRESHOLD, irr);
5981 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5983 struct vcpu_vmx *vmx = to_vmx(vcpu);
5984 u32 sec_exec_control;
5986 if (!lapic_in_kernel(vcpu))
5989 if (!flexpriority_enabled &&
5990 !cpu_has_vmx_virtualize_x2apic_mode())
5993 /* Postpone execution until vmcs01 is the current VMCS. */
5994 if (is_guest_mode(vcpu)) {
5995 vmx->nested.change_vmcs01_virtual_apic_mode = true;
5999 sec_exec_control = secondary_exec_controls_get(vmx);
6000 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6001 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6003 switch (kvm_get_apic_mode(vcpu)) {
6004 case LAPIC_MODE_INVALID:
6005 WARN_ONCE(true, "Invalid local APIC state");
6006 case LAPIC_MODE_DISABLED:
6008 case LAPIC_MODE_XAPIC:
6009 if (flexpriority_enabled) {
6011 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6012 vmx_flush_tlb(vcpu, true);
6015 case LAPIC_MODE_X2APIC:
6016 if (cpu_has_vmx_virtualize_x2apic_mode())
6018 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6021 secondary_exec_controls_set(vmx, sec_exec_control);
6023 vmx_update_msr_bitmap(vcpu);
6026 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
6028 if (!is_guest_mode(vcpu)) {
6029 vmcs_write64(APIC_ACCESS_ADDR, hpa);
6030 vmx_flush_tlb(vcpu, true);
6034 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6042 status = vmcs_read16(GUEST_INTR_STATUS);
6044 if (max_isr != old) {
6046 status |= max_isr << 8;
6047 vmcs_write16(GUEST_INTR_STATUS, status);
6051 static void vmx_set_rvi(int vector)
6059 status = vmcs_read16(GUEST_INTR_STATUS);
6060 old = (u8)status & 0xff;
6061 if ((u8)vector != old) {
6063 status |= (u8)vector;
6064 vmcs_write16(GUEST_INTR_STATUS, status);
6068 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6071 * When running L2, updating RVI is only relevant when
6072 * vmcs12 virtual-interrupt-delivery enabled.
6073 * However, it can be enabled only when L1 also
6074 * intercepts external-interrupts and in that case
6075 * we should not update vmcs02 RVI but instead intercept
6076 * interrupt. Therefore, do nothing when running L2.
6078 if (!is_guest_mode(vcpu))
6079 vmx_set_rvi(max_irr);
6082 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6084 struct vcpu_vmx *vmx = to_vmx(vcpu);
6086 bool max_irr_updated;
6088 WARN_ON(!vcpu->arch.apicv_active);
6089 if (pi_test_on(&vmx->pi_desc)) {
6090 pi_clear_on(&vmx->pi_desc);
6092 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
6093 * But on x86 this is just a compiler barrier anyway.
6095 smp_mb__after_atomic();
6097 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6100 * If we are running L2 and L1 has a new pending interrupt
6101 * which can be injected, we should re-evaluate
6102 * what should be done with this new L1 interrupt.
6103 * If L1 intercepts external-interrupts, we should
6104 * exit from L2 to L1. Otherwise, interrupt should be
6105 * delivered directly to L2.
6107 if (is_guest_mode(vcpu) && max_irr_updated) {
6108 if (nested_exit_on_intr(vcpu))
6109 kvm_vcpu_exiting_guest_mode(vcpu);
6111 kvm_make_request(KVM_REQ_EVENT, vcpu);
6114 max_irr = kvm_lapic_find_highest_irr(vcpu);
6116 vmx_hwapic_irr_update(vcpu, max_irr);
6120 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
6122 return pi_test_on(vcpu_to_pi_desc(vcpu));
6125 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6127 if (!kvm_vcpu_apicv_active(vcpu))
6130 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6131 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6132 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6133 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6136 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6138 struct vcpu_vmx *vmx = to_vmx(vcpu);
6140 pi_clear_on(&vmx->pi_desc);
6141 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6144 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6146 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6148 /* if exit due to PF check for async PF */
6149 if (is_page_fault(vmx->exit_intr_info))
6150 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
6152 /* Handle machine checks before interrupts are enabled */
6153 if (is_machine_check(vmx->exit_intr_info))
6154 kvm_machine_check();
6156 /* We need to handle NMIs before interrupts are enabled */
6157 if (is_nmi(vmx->exit_intr_info)) {
6158 kvm_before_interrupt(&vmx->vcpu);
6160 kvm_after_interrupt(&vmx->vcpu);
6164 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6166 unsigned int vector;
6167 unsigned long entry;
6168 #ifdef CONFIG_X86_64
6174 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6175 if (WARN_ONCE(!is_external_intr(intr_info),
6176 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6179 vector = intr_info & INTR_INFO_VECTOR_MASK;
6180 desc = (gate_desc *)host_idt_base + vector;
6181 entry = gate_offset(desc);
6183 kvm_before_interrupt(vcpu);
6186 #ifdef CONFIG_X86_64
6187 "mov %%" _ASM_SP ", %[sp]\n\t"
6188 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6193 __ASM_SIZE(push) " $%c[cs]\n\t"
6196 #ifdef CONFIG_X86_64
6201 THUNK_TARGET(entry),
6202 [ss]"i"(__KERNEL_DS),
6203 [cs]"i"(__KERNEL_CS)
6206 kvm_after_interrupt(vcpu);
6208 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff);
6210 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6212 struct vcpu_vmx *vmx = to_vmx(vcpu);
6214 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6215 handle_external_interrupt_irqoff(vcpu);
6216 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6217 handle_exception_nmi_irqoff(vmx);
6220 static bool vmx_has_emulated_msr(int index)
6223 case MSR_IA32_SMBASE:
6225 * We cannot do SMM unless we can run the guest in big
6228 return enable_unrestricted_guest || emulate_invalid_guest_state;
6229 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6231 case MSR_AMD64_VIRT_SPEC_CTRL:
6232 /* This is AMD only. */
6239 static bool vmx_pt_supported(void)
6241 return pt_mode == PT_MODE_HOST_GUEST;
6244 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6249 bool idtv_info_valid;
6251 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6254 if (vmx->loaded_vmcs->nmi_known_unmasked)
6257 * Can't use vmx->exit_intr_info since we're not sure what
6258 * the exit reason is.
6260 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6261 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6262 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6264 * SDM 3: 27.7.1.2 (September 2008)
6265 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6266 * a guest IRET fault.
6267 * SDM 3: 23.2.2 (September 2008)
6268 * Bit 12 is undefined in any of the following cases:
6269 * If the VM exit sets the valid bit in the IDT-vectoring
6270 * information field.
6271 * If the VM exit is due to a double fault.
6273 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6274 vector != DF_VECTOR && !idtv_info_valid)
6275 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6276 GUEST_INTR_STATE_NMI);
6278 vmx->loaded_vmcs->nmi_known_unmasked =
6279 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6280 & GUEST_INTR_STATE_NMI);
6281 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6282 vmx->loaded_vmcs->vnmi_blocked_time +=
6283 ktime_to_ns(ktime_sub(ktime_get(),
6284 vmx->loaded_vmcs->entry_time));
6287 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6288 u32 idt_vectoring_info,
6289 int instr_len_field,
6290 int error_code_field)
6294 bool idtv_info_valid;
6296 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6298 vcpu->arch.nmi_injected = false;
6299 kvm_clear_exception_queue(vcpu);
6300 kvm_clear_interrupt_queue(vcpu);
6302 if (!idtv_info_valid)
6305 kvm_make_request(KVM_REQ_EVENT, vcpu);
6307 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6308 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6311 case INTR_TYPE_NMI_INTR:
6312 vcpu->arch.nmi_injected = true;
6314 * SDM 3: 27.7.1.2 (September 2008)
6315 * Clear bit "block by NMI" before VM entry if a NMI
6318 vmx_set_nmi_mask(vcpu, false);
6320 case INTR_TYPE_SOFT_EXCEPTION:
6321 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6323 case INTR_TYPE_HARD_EXCEPTION:
6324 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6325 u32 err = vmcs_read32(error_code_field);
6326 kvm_requeue_exception_e(vcpu, vector, err);
6328 kvm_requeue_exception(vcpu, vector);
6330 case INTR_TYPE_SOFT_INTR:
6331 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6333 case INTR_TYPE_EXT_INTR:
6334 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6341 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6343 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6344 VM_EXIT_INSTRUCTION_LEN,
6345 IDT_VECTORING_ERROR_CODE);
6348 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6350 __vmx_complete_interrupts(vcpu,
6351 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6352 VM_ENTRY_INSTRUCTION_LEN,
6353 VM_ENTRY_EXCEPTION_ERROR_CODE);
6355 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6358 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6361 struct perf_guest_switch_msr *msrs;
6363 msrs = perf_guest_get_msrs(&nr_msrs);
6368 for (i = 0; i < nr_msrs; i++)
6369 if (msrs[i].host == msrs[i].guest)
6370 clear_atomic_switch_msr(vmx, msrs[i].msr);
6372 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6373 msrs[i].host, false);
6376 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6378 struct vcpu_vmx *vmx = to_vmx(vcpu);
6382 if (vmx->req_immediate_exit) {
6383 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6384 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6385 } else if (vmx->hv_deadline_tsc != -1) {
6387 if (vmx->hv_deadline_tsc > tscl)
6388 /* set_hv_timer ensures the delta fits in 32-bits */
6389 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6390 cpu_preemption_timer_multi);
6394 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6395 vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6396 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6397 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6398 vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6402 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6404 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6405 vmx->loaded_vmcs->host_state.rsp = host_rsp;
6406 vmcs_writel(HOST_RSP, host_rsp);
6410 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6412 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6414 struct vcpu_vmx *vmx = to_vmx(vcpu);
6415 unsigned long cr3, cr4;
6417 /* Record the guest's net vcpu time for enforced NMI injections. */
6418 if (unlikely(!enable_vnmi &&
6419 vmx->loaded_vmcs->soft_vnmi_blocked))
6420 vmx->loaded_vmcs->entry_time = ktime_get();
6422 /* Don't enter VMX if guest state is invalid, let the exit handler
6423 start emulation until we arrive back to a valid state */
6424 if (vmx->emulation_required)
6427 if (vmx->ple_window_dirty) {
6428 vmx->ple_window_dirty = false;
6429 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6432 if (vmx->nested.need_vmcs12_to_shadow_sync)
6433 nested_sync_vmcs12_to_shadow(vcpu);
6435 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6436 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6437 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6438 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6440 cr3 = __get_current_cr3_fast();
6441 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6442 vmcs_writel(HOST_CR3, cr3);
6443 vmx->loaded_vmcs->host_state.cr3 = cr3;
6446 cr4 = cr4_read_shadow();
6447 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6448 vmcs_writel(HOST_CR4, cr4);
6449 vmx->loaded_vmcs->host_state.cr4 = cr4;
6452 /* When single-stepping over STI and MOV SS, we must clear the
6453 * corresponding interruptibility bits in the guest state. Otherwise
6454 * vmentry fails as it then expects bit 14 (BS) in pending debug
6455 * exceptions being set, but that's not correct for the guest debugging
6457 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6458 vmx_set_interrupt_shadow(vcpu, 0);
6460 kvm_load_guest_xcr0(vcpu);
6462 if (static_cpu_has(X86_FEATURE_PKU) &&
6463 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6464 vcpu->arch.pkru != vmx->host_pkru)
6465 __write_pkru(vcpu->arch.pkru);
6467 pt_guest_enter(vmx);
6469 atomic_switch_perf_msrs(vmx);
6471 if (enable_preemption_timer)
6472 vmx_update_hv_timer(vcpu);
6474 if (lapic_in_kernel(vcpu) &&
6475 vcpu->arch.apic->lapic_timer.timer_advance_ns)
6476 kvm_wait_lapic_expire(vcpu);
6479 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6480 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6481 * is no need to worry about the conditional branch over the wrmsr
6482 * being speculatively taken.
6484 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6486 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6487 if (static_branch_unlikely(&vmx_l1d_should_flush))
6488 vmx_l1d_flush(vcpu);
6489 else if (static_branch_unlikely(&mds_user_clear))
6490 mds_clear_cpu_buffers();
6492 if (vcpu->arch.cr2 != read_cr2())
6493 write_cr2(vcpu->arch.cr2);
6495 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6496 vmx->loaded_vmcs->launched);
6498 vcpu->arch.cr2 = read_cr2();
6501 * We do not use IBRS in the kernel. If this vCPU has used the
6502 * SPEC_CTRL MSR it may have left it on; save the value and
6503 * turn it off. This is much more efficient than blindly adding
6504 * it to the atomic save/restore list. Especially as the former
6505 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6507 * For non-nested case:
6508 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6512 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6515 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6516 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6518 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6520 /* All fields are clean at this point */
6521 if (static_branch_unlikely(&enable_evmcs))
6522 current_evmcs->hv_clean_fields |=
6523 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6525 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6526 if (vmx->host_debugctlmsr)
6527 update_debugctlmsr(vmx->host_debugctlmsr);
6529 #ifndef CONFIG_X86_64
6531 * The sysexit path does not restore ds/es, so we must set them to
6532 * a reasonable value ourselves.
6534 * We can't defer this to vmx_prepare_switch_to_host() since that
6535 * function may be executed in interrupt context, which saves and
6536 * restore segments around it, nullifying its effect.
6538 loadsegment(ds, __USER_DS);
6539 loadsegment(es, __USER_DS);
6542 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6543 | (1 << VCPU_EXREG_RFLAGS)
6544 | (1 << VCPU_EXREG_PDPTR)
6545 | (1 << VCPU_EXREG_SEGMENTS)
6546 | (1 << VCPU_EXREG_CR3));
6547 vcpu->arch.regs_dirty = 0;
6552 * eager fpu is enabled if PKEY is supported and CR4 is switched
6553 * back on host, so it is safe to read guest PKRU from current
6556 if (static_cpu_has(X86_FEATURE_PKU) &&
6557 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6558 vcpu->arch.pkru = rdpkru();
6559 if (vcpu->arch.pkru != vmx->host_pkru)
6560 __write_pkru(vmx->host_pkru);
6563 kvm_put_guest_xcr0(vcpu);
6565 vmx->nested.nested_run_pending = 0;
6566 vmx->idt_vectoring_info = 0;
6568 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6569 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
6570 kvm_machine_check();
6572 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6575 vmx->loaded_vmcs->launched = 1;
6576 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6578 vmx_recover_nmi_blocking(vmx);
6579 vmx_complete_interrupts(vmx);
6582 static struct kvm *vmx_vm_alloc(void)
6584 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx),
6585 GFP_KERNEL_ACCOUNT | __GFP_ZERO,
6587 return &kvm_vmx->kvm;
6590 static void vmx_vm_free(struct kvm *kvm)
6592 vfree(to_kvm_vmx(kvm));
6595 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6597 struct vcpu_vmx *vmx = to_vmx(vcpu);
6600 vmx_destroy_pml_buffer(vmx);
6601 free_vpid(vmx->vpid);
6602 nested_vmx_free_vcpu(vcpu);
6603 free_loaded_vmcs(vmx->loaded_vmcs);
6604 kfree(vmx->guest_msrs);
6605 kvm_vcpu_uninit(vcpu);
6606 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6607 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6608 kmem_cache_free(kvm_vcpu_cache, vmx);
6611 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6614 struct vcpu_vmx *vmx;
6615 unsigned long *msr_bitmap;
6618 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT);
6620 return ERR_PTR(-ENOMEM);
6622 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
6623 GFP_KERNEL_ACCOUNT);
6624 if (!vmx->vcpu.arch.user_fpu) {
6625 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n");
6627 goto free_partial_vcpu;
6630 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
6631 GFP_KERNEL_ACCOUNT);
6632 if (!vmx->vcpu.arch.guest_fpu) {
6633 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6638 vmx->vpid = allocate_vpid();
6640 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6647 * If PML is turned on, failure on enabling PML just results in failure
6648 * of creating the vcpu, therefore we can simplify PML logic (by
6649 * avoiding dealing with cases, such as enabling PML partially on vcpus
6650 * for the guest, etc.
6653 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6658 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
6659 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6662 if (!vmx->guest_msrs)
6665 err = alloc_loaded_vmcs(&vmx->vmcs01);
6669 msr_bitmap = vmx->vmcs01.msr_bitmap;
6670 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R);
6671 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6672 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6673 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6674 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6675 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6676 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6677 if (kvm_cstate_in_guest(kvm)) {
6678 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R);
6679 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6680 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6681 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6683 vmx->msr_bitmap_mode = 0;
6685 vmx->loaded_vmcs = &vmx->vmcs01;
6687 vmx_vcpu_load(&vmx->vcpu, cpu);
6688 vmx->vcpu.cpu = cpu;
6689 vmx_vcpu_setup(vmx);
6690 vmx_vcpu_put(&vmx->vcpu);
6692 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6693 err = alloc_apic_access_page(kvm);
6698 if (enable_ept && !enable_unrestricted_guest) {
6699 err = init_rmode_identity_map(kvm);
6705 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6707 kvm_vcpu_apicv_active(&vmx->vcpu));
6709 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6711 vmx->nested.posted_intr_nv = -1;
6712 vmx->nested.current_vmptr = -1ull;
6714 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
6717 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6718 * or POSTED_INTR_WAKEUP_VECTOR.
6720 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6721 vmx->pi_desc.sn = 1;
6723 vmx->ept_pointer = INVALID_PAGE;
6728 free_loaded_vmcs(vmx->loaded_vmcs);
6730 kfree(vmx->guest_msrs);
6732 vmx_destroy_pml_buffer(vmx);
6734 kvm_vcpu_uninit(&vmx->vcpu);
6736 free_vpid(vmx->vpid);
6737 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6739 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu);
6741 kmem_cache_free(kvm_vcpu_cache, vmx);
6742 return ERR_PTR(err);
6745 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6746 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6748 static int vmx_vm_init(struct kvm *kvm)
6750 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6753 kvm->arch.pause_in_guest = true;
6755 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6756 switch (l1tf_mitigation) {
6757 case L1TF_MITIGATION_OFF:
6758 case L1TF_MITIGATION_FLUSH_NOWARN:
6759 /* 'I explicitly don't care' is set */
6761 case L1TF_MITIGATION_FLUSH:
6762 case L1TF_MITIGATION_FLUSH_NOSMT:
6763 case L1TF_MITIGATION_FULL:
6765 * Warn upon starting the first VM in a potentially
6766 * insecure environment.
6768 if (sched_smt_active())
6769 pr_warn_once(L1TF_MSG_SMT);
6770 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6771 pr_warn_once(L1TF_MSG_L1D);
6773 case L1TF_MITIGATION_FULL_FORCE:
6774 /* Flush is enforced */
6781 static int __init vmx_check_processor_compat(void)
6783 struct vmcs_config vmcs_conf;
6784 struct vmx_capability vmx_cap;
6786 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6789 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6791 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6792 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6793 smp_processor_id());
6799 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6804 /* For VT-d and EPT combination
6805 * 1. MMIO: always map as UC
6807 * a. VT-d without snooping control feature: can't guarantee the
6808 * result, try to trust guest.
6809 * b. VT-d with snooping control feature: snooping control feature of
6810 * VT-d engine can guarantee the cache correctness. Just set it
6811 * to WB to keep consistent with host. So the same as item 3.
6812 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6813 * consistent with host MTRR
6816 cache = MTRR_TYPE_UNCACHABLE;
6820 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6821 ipat = VMX_EPT_IPAT_BIT;
6822 cache = MTRR_TYPE_WRBACK;
6826 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6827 ipat = VMX_EPT_IPAT_BIT;
6828 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6829 cache = MTRR_TYPE_WRBACK;
6831 cache = MTRR_TYPE_UNCACHABLE;
6835 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
6838 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6841 static int vmx_get_lpage_level(void)
6843 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6844 return PT_DIRECTORY_LEVEL;
6846 /* For shadow and EPT supported 1GB page */
6847 return PT_PDPE_LEVEL;
6850 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
6853 * These bits in the secondary execution controls field
6854 * are dynamic, the others are mostly based on the hypervisor
6855 * architecture and the guest's CPUID. Do not touch the
6859 SECONDARY_EXEC_SHADOW_VMCS |
6860 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6861 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6862 SECONDARY_EXEC_DESC;
6864 u32 new_ctl = vmx->secondary_exec_control;
6865 u32 cur_ctl = secondary_exec_controls_get(vmx);
6867 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
6871 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6872 * (indicating "allowed-1") if they are supported in the guest's CPUID.
6874 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
6876 struct vcpu_vmx *vmx = to_vmx(vcpu);
6877 struct kvm_cpuid_entry2 *entry;
6879 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6880 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
6882 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6883 if (entry && (entry->_reg & (_cpuid_mask))) \
6884 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6887 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6888 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6889 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6890 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6891 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6892 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6893 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6894 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6895 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6896 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6897 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6898 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6899 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6900 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6901 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
6903 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6904 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6905 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6906 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6907 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6908 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
6910 #undef cr4_fixed1_update
6913 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6915 struct vcpu_vmx *vmx = to_vmx(vcpu);
6917 if (kvm_mpx_supported()) {
6918 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
6921 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6922 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6924 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6925 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6930 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
6932 struct vcpu_vmx *vmx = to_vmx(vcpu);
6933 struct kvm_cpuid_entry2 *best = NULL;
6936 for (i = 0; i < PT_CPUID_LEAVES; i++) {
6937 best = kvm_find_cpuid_entry(vcpu, 0x14, i);
6940 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
6941 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
6942 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
6943 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
6946 /* Get the number of configurable Address Ranges for filtering */
6947 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
6948 PT_CAP_num_address_ranges);
6950 /* Initialize and clear the no dependency bits */
6951 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
6952 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
6955 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
6956 * will inject an #GP
6958 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
6959 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
6962 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
6963 * PSBFreq can be set
6965 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
6966 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
6967 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
6970 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
6971 * MTCFreq can be set
6973 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
6974 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
6975 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
6977 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
6978 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
6979 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
6982 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
6983 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
6984 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
6986 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
6987 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
6988 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
6990 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
6991 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
6992 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
6994 /* unmask address range configure area */
6995 for (i = 0; i < vmx->pt_desc.addr_range; i++)
6996 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
6999 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7001 struct vcpu_vmx *vmx = to_vmx(vcpu);
7003 if (cpu_has_secondary_exec_ctrls()) {
7004 vmx_compute_secondary_exec_control(vmx);
7005 vmcs_set_secondary_exec_control(vmx);
7008 if (nested_vmx_allowed(vcpu))
7009 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7010 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7012 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7013 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7015 if (nested_vmx_allowed(vcpu)) {
7016 nested_vmx_cr_fixed1_bits_update(vcpu);
7017 nested_vmx_entry_exit_ctls_update(vcpu);
7020 if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7021 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7022 update_intel_pt_cfg(vcpu);
7025 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7027 if (func == 1 && nested)
7028 entry->ecx |= bit(X86_FEATURE_VMX);
7031 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7033 to_vmx(vcpu)->req_immediate_exit = true;
7036 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7037 struct x86_instruction_info *info,
7038 enum x86_intercept_stage stage)
7040 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7041 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7044 * RDPID causes #UD if disabled through secondary execution controls.
7045 * Because it is marked as EmulateOnUD, we need to intercept it here.
7047 if (info->intercept == x86_intercept_rdtscp &&
7048 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
7049 ctxt->exception.vector = UD_VECTOR;
7050 ctxt->exception.error_code_valid = false;
7051 return X86EMUL_PROPAGATE_FAULT;
7054 /* TODO: check more intercepts... */
7055 return X86EMUL_CONTINUE;
7058 #ifdef CONFIG_X86_64
7059 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7060 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7061 u64 divisor, u64 *result)
7063 u64 low = a << shift, high = a >> (64 - shift);
7065 /* To avoid the overflow on divq */
7066 if (high >= divisor)
7069 /* Low hold the result, high hold rem which is discarded */
7070 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7071 "rm" (divisor), "0" (low), "1" (high));
7077 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7080 struct vcpu_vmx *vmx;
7081 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7082 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7084 if (kvm_mwait_in_guest(vcpu->kvm) ||
7085 kvm_can_post_timer_interrupt(vcpu))
7090 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7091 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7092 lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7093 ktimer->timer_advance_ns);
7095 if (delta_tsc > lapic_timer_advance_cycles)
7096 delta_tsc -= lapic_timer_advance_cycles;
7100 /* Convert to host delta tsc if tsc scaling is enabled */
7101 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7102 delta_tsc && u64_shl_div_u64(delta_tsc,
7103 kvm_tsc_scaling_ratio_frac_bits,
7104 vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7108 * If the delta tsc can't fit in the 32 bit after the multi shift,
7109 * we can't use the preemption timer.
7110 * It's possible that it fits on later vmentries, but checking
7111 * on every vmentry is costly so we just use an hrtimer.
7113 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7116 vmx->hv_deadline_tsc = tscl + delta_tsc;
7117 *expired = !delta_tsc;
7121 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7123 to_vmx(vcpu)->hv_deadline_tsc = -1;
7127 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7129 if (!kvm_pause_in_guest(vcpu->kvm))
7130 shrink_ple_window(vcpu);
7133 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7134 struct kvm_memory_slot *slot)
7136 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7137 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7140 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7141 struct kvm_memory_slot *slot)
7143 kvm_mmu_slot_set_dirty(kvm, slot);
7146 static void vmx_flush_log_dirty(struct kvm *kvm)
7148 kvm_flush_pml_buffers(kvm);
7151 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
7153 struct vmcs12 *vmcs12;
7154 struct vcpu_vmx *vmx = to_vmx(vcpu);
7157 if (is_guest_mode(vcpu)) {
7158 WARN_ON_ONCE(vmx->nested.pml_full);
7161 * Check if PML is enabled for the nested guest.
7162 * Whether eptp bit 6 is set is already checked
7163 * as part of A/D emulation.
7165 vmcs12 = get_vmcs12(vcpu);
7166 if (!nested_cpu_has_pml(vmcs12))
7169 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
7170 vmx->nested.pml_full = true;
7174 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
7175 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index;
7177 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa,
7178 offset_in_page(dst), sizeof(gpa)))
7181 vmcs12->guest_pml_index--;
7187 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7188 struct kvm_memory_slot *memslot,
7189 gfn_t offset, unsigned long mask)
7191 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7194 static void __pi_post_block(struct kvm_vcpu *vcpu)
7196 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7197 struct pi_desc old, new;
7201 old.control = new.control = pi_desc->control;
7202 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
7203 "Wakeup handler not enabled while the VCPU is blocked\n");
7205 dest = cpu_physical_id(vcpu->cpu);
7207 if (x2apic_enabled())
7210 new.ndst = (dest << 8) & 0xFF00;
7212 /* set 'NV' to 'notification vector' */
7213 new.nv = POSTED_INTR_VECTOR;
7214 } while (cmpxchg64(&pi_desc->control, old.control,
7215 new.control) != old.control);
7217 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
7218 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7219 list_del(&vcpu->blocked_vcpu_list);
7220 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7221 vcpu->pre_pcpu = -1;
7226 * This routine does the following things for vCPU which is going
7227 * to be blocked if VT-d PI is enabled.
7228 * - Store the vCPU to the wakeup list, so when interrupts happen
7229 * we can find the right vCPU to wake up.
7230 * - Change the Posted-interrupt descriptor as below:
7231 * 'NDST' <-- vcpu->pre_pcpu
7232 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
7233 * - If 'ON' is set during this process, which means at least one
7234 * interrupt is posted for this vCPU, we cannot block it, in
7235 * this case, return 1, otherwise, return 0.
7238 static int pi_pre_block(struct kvm_vcpu *vcpu)
7241 struct pi_desc old, new;
7242 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7244 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
7245 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7246 !kvm_vcpu_apicv_active(vcpu))
7249 WARN_ON(irqs_disabled());
7250 local_irq_disable();
7251 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
7252 vcpu->pre_pcpu = vcpu->cpu;
7253 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7254 list_add_tail(&vcpu->blocked_vcpu_list,
7255 &per_cpu(blocked_vcpu_on_cpu,
7257 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
7261 old.control = new.control = pi_desc->control;
7263 WARN((pi_desc->sn == 1),
7264 "Warning: SN field of posted-interrupts "
7265 "is set before blocking\n");
7268 * Since vCPU can be preempted during this process,
7269 * vcpu->cpu could be different with pre_pcpu, we
7270 * need to set pre_pcpu as the destination of wakeup
7271 * notification event, then we can find the right vCPU
7272 * to wakeup in wakeup handler if interrupts happen
7273 * when the vCPU is in blocked state.
7275 dest = cpu_physical_id(vcpu->pre_pcpu);
7277 if (x2apic_enabled())
7280 new.ndst = (dest << 8) & 0xFF00;
7282 /* set 'NV' to 'wakeup vector' */
7283 new.nv = POSTED_INTR_WAKEUP_VECTOR;
7284 } while (cmpxchg64(&pi_desc->control, old.control,
7285 new.control) != old.control);
7287 /* We should not block the vCPU if an interrupt is posted for it. */
7288 if (pi_test_on(pi_desc) == 1)
7289 __pi_post_block(vcpu);
7292 return (vcpu->pre_pcpu == -1);
7295 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7297 if (pi_pre_block(vcpu))
7300 if (kvm_lapic_hv_timer_in_use(vcpu))
7301 kvm_lapic_switch_to_sw_timer(vcpu);
7306 static void pi_post_block(struct kvm_vcpu *vcpu)
7308 if (vcpu->pre_pcpu == -1)
7311 WARN_ON(irqs_disabled());
7312 local_irq_disable();
7313 __pi_post_block(vcpu);
7317 static void vmx_post_block(struct kvm_vcpu *vcpu)
7319 if (kvm_x86_ops->set_hv_timer)
7320 kvm_lapic_switch_to_hv_timer(vcpu);
7322 pi_post_block(vcpu);
7326 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
7329 * @host_irq: host irq of the interrupt
7330 * @guest_irq: gsi of the interrupt
7331 * @set: set or unset PI
7332 * returns 0 on success, < 0 on failure
7334 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
7335 uint32_t guest_irq, bool set)
7337 struct kvm_kernel_irq_routing_entry *e;
7338 struct kvm_irq_routing_table *irq_rt;
7339 struct kvm_lapic_irq irq;
7340 struct kvm_vcpu *vcpu;
7341 struct vcpu_data vcpu_info;
7344 if (!kvm_arch_has_assigned_device(kvm) ||
7345 !irq_remapping_cap(IRQ_POSTING_CAP) ||
7346 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
7349 idx = srcu_read_lock(&kvm->irq_srcu);
7350 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
7351 if (guest_irq >= irq_rt->nr_rt_entries ||
7352 hlist_empty(&irq_rt->map[guest_irq])) {
7353 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7354 guest_irq, irq_rt->nr_rt_entries);
7358 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7359 if (e->type != KVM_IRQ_ROUTING_MSI)
7362 * VT-d PI cannot support posting multicast/broadcast
7363 * interrupts to a vCPU, we still use interrupt remapping
7364 * for these kind of interrupts.
7366 * For lowest-priority interrupts, we only support
7367 * those with single CPU as the destination, e.g. user
7368 * configures the interrupts via /proc/irq or uses
7369 * irqbalance to make the interrupts single-CPU.
7371 * We will support full lowest-priority interrupt later.
7374 kvm_set_msi_irq(kvm, e, &irq);
7375 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
7377 * Make sure the IRTE is in remapped mode if
7378 * we don't handle it in posted mode.
7380 ret = irq_set_vcpu_affinity(host_irq, NULL);
7383 "failed to back to remapped mode, irq: %u\n",
7391 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7392 vcpu_info.vector = irq.vector;
7394 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
7395 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7398 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
7400 ret = irq_set_vcpu_affinity(host_irq, NULL);
7403 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7411 srcu_read_unlock(&kvm->irq_srcu, idx);
7415 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7417 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7418 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7419 FEATURE_CONTROL_LMCE;
7421 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7422 ~FEATURE_CONTROL_LMCE;
7425 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7427 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7428 if (to_vmx(vcpu)->nested.nested_run_pending)
7433 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7435 struct vcpu_vmx *vmx = to_vmx(vcpu);
7437 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7438 if (vmx->nested.smm.guest_mode)
7439 nested_vmx_vmexit(vcpu, -1, 0, 0);
7441 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7442 vmx->nested.vmxon = false;
7443 vmx_clear_hlt(vcpu);
7447 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7449 struct vcpu_vmx *vmx = to_vmx(vcpu);
7452 if (vmx->nested.smm.vmxon) {
7453 vmx->nested.vmxon = true;
7454 vmx->nested.smm.vmxon = false;
7457 if (vmx->nested.smm.guest_mode) {
7458 ret = nested_vmx_enter_non_root_mode(vcpu, false);
7462 vmx->nested.smm.guest_mode = false;
7467 static int enable_smi_window(struct kvm_vcpu *vcpu)
7472 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
7477 static __init int hardware_setup(void)
7479 unsigned long host_bndcfgs;
7483 rdmsrl_safe(MSR_EFER, &host_efer);
7486 host_idt_base = dt.address;
7488 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7489 kvm_define_shared_msr(i, vmx_msr_index[i]);
7491 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7494 if (boot_cpu_has(X86_FEATURE_NX))
7495 kvm_enable_efer_bits(EFER_NX);
7497 if (boot_cpu_has(X86_FEATURE_MPX)) {
7498 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7499 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7502 if (boot_cpu_has(X86_FEATURE_XSAVES))
7503 rdmsrl(MSR_IA32_XSS, host_xss);
7505 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7506 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7509 if (!cpu_has_vmx_ept() ||
7510 !cpu_has_vmx_ept_4levels() ||
7511 !cpu_has_vmx_ept_mt_wb() ||
7512 !cpu_has_vmx_invept_global())
7515 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7516 enable_ept_ad_bits = 0;
7518 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7519 enable_unrestricted_guest = 0;
7521 if (!cpu_has_vmx_flexpriority())
7522 flexpriority_enabled = 0;
7524 if (!cpu_has_virtual_nmis())
7528 * set_apic_access_page_addr() is used to reload apic access
7529 * page upon invalidation. No need to do anything if not
7530 * using the APIC_ACCESS_ADDR VMCS field.
7532 if (!flexpriority_enabled)
7533 kvm_x86_ops->set_apic_access_page_addr = NULL;
7535 if (!cpu_has_vmx_tpr_shadow())
7536 kvm_x86_ops->update_cr8_intercept = NULL;
7538 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7539 kvm_disable_largepages();
7541 #if IS_ENABLED(CONFIG_HYPERV)
7542 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7544 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb;
7545 kvm_x86_ops->tlb_remote_flush_with_range =
7546 hv_remote_flush_tlb_with_range;
7550 if (!cpu_has_vmx_ple()) {
7553 ple_window_grow = 0;
7555 ple_window_shrink = 0;
7558 if (!cpu_has_vmx_apicv()) {
7560 kvm_x86_ops->sync_pir_to_irr = NULL;
7563 if (cpu_has_vmx_tsc_scaling()) {
7564 kvm_has_tsc_control = true;
7565 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7566 kvm_tsc_scaling_ratio_frac_bits = 48;
7569 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7577 * Only enable PML when hardware supports PML feature, and both EPT
7578 * and EPT A/D bit features are enabled -- PML depends on them to work.
7580 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7584 kvm_x86_ops->slot_enable_log_dirty = NULL;
7585 kvm_x86_ops->slot_disable_log_dirty = NULL;
7586 kvm_x86_ops->flush_log_dirty = NULL;
7587 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7590 if (!cpu_has_vmx_preemption_timer())
7591 enable_preemption_timer = false;
7593 if (enable_preemption_timer) {
7594 u64 use_timer_freq = 5000ULL * 1000 * 1000;
7597 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7598 cpu_preemption_timer_multi =
7599 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7602 use_timer_freq = (u64)tsc_khz * 1000;
7603 use_timer_freq >>= cpu_preemption_timer_multi;
7606 * KVM "disables" the preemption timer by setting it to its max
7607 * value. Don't use the timer if it might cause spurious exits
7608 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7610 if (use_timer_freq > 0xffffffffu / 10)
7611 enable_preemption_timer = false;
7614 if (!enable_preemption_timer) {
7615 kvm_x86_ops->set_hv_timer = NULL;
7616 kvm_x86_ops->cancel_hv_timer = NULL;
7617 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7620 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7622 kvm_mce_cap_supported |= MCG_LMCE_P;
7624 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7626 if (!enable_ept || !cpu_has_vmx_intel_pt())
7627 pt_mode = PT_MODE_SYSTEM;
7630 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7631 vmx_capability.ept, enable_apicv);
7633 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7638 r = alloc_kvm_area();
7640 nested_vmx_hardware_unsetup();
7644 static __exit void hardware_unsetup(void)
7647 nested_vmx_hardware_unsetup();
7652 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
7653 .cpu_has_kvm_support = cpu_has_kvm_support,
7654 .disabled_by_bios = vmx_disabled_by_bios,
7655 .hardware_setup = hardware_setup,
7656 .hardware_unsetup = hardware_unsetup,
7657 .check_processor_compatibility = vmx_check_processor_compat,
7658 .hardware_enable = hardware_enable,
7659 .hardware_disable = hardware_disable,
7660 .cpu_has_accelerated_tpr = report_flexpriority,
7661 .has_emulated_msr = vmx_has_emulated_msr,
7663 .vm_init = vmx_vm_init,
7664 .vm_alloc = vmx_vm_alloc,
7665 .vm_free = vmx_vm_free,
7667 .vcpu_create = vmx_create_vcpu,
7668 .vcpu_free = vmx_free_vcpu,
7669 .vcpu_reset = vmx_vcpu_reset,
7671 .prepare_guest_switch = vmx_prepare_switch_to_guest,
7672 .vcpu_load = vmx_vcpu_load,
7673 .vcpu_put = vmx_vcpu_put,
7675 .update_bp_intercept = update_exception_bitmap,
7676 .get_msr_feature = vmx_get_msr_feature,
7677 .get_msr = vmx_get_msr,
7678 .set_msr = vmx_set_msr,
7679 .get_segment_base = vmx_get_segment_base,
7680 .get_segment = vmx_get_segment,
7681 .set_segment = vmx_set_segment,
7682 .get_cpl = vmx_get_cpl,
7683 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7684 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7685 .decache_cr3 = vmx_decache_cr3,
7686 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7687 .set_cr0 = vmx_set_cr0,
7688 .set_cr3 = vmx_set_cr3,
7689 .set_cr4 = vmx_set_cr4,
7690 .set_efer = vmx_set_efer,
7691 .get_idt = vmx_get_idt,
7692 .set_idt = vmx_set_idt,
7693 .get_gdt = vmx_get_gdt,
7694 .set_gdt = vmx_set_gdt,
7695 .get_dr6 = vmx_get_dr6,
7696 .set_dr6 = vmx_set_dr6,
7697 .set_dr7 = vmx_set_dr7,
7698 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7699 .cache_reg = vmx_cache_reg,
7700 .get_rflags = vmx_get_rflags,
7701 .set_rflags = vmx_set_rflags,
7703 .tlb_flush = vmx_flush_tlb,
7704 .tlb_flush_gva = vmx_flush_tlb_gva,
7706 .run = vmx_vcpu_run,
7707 .handle_exit = vmx_handle_exit,
7708 .skip_emulated_instruction = skip_emulated_instruction,
7709 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7710 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7711 .patch_hypercall = vmx_patch_hypercall,
7712 .set_irq = vmx_inject_irq,
7713 .set_nmi = vmx_inject_nmi,
7714 .queue_exception = vmx_queue_exception,
7715 .cancel_injection = vmx_cancel_injection,
7716 .interrupt_allowed = vmx_interrupt_allowed,
7717 .nmi_allowed = vmx_nmi_allowed,
7718 .get_nmi_mask = vmx_get_nmi_mask,
7719 .set_nmi_mask = vmx_set_nmi_mask,
7720 .enable_nmi_window = enable_nmi_window,
7721 .enable_irq_window = enable_irq_window,
7722 .update_cr8_intercept = update_cr8_intercept,
7723 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7724 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7725 .get_enable_apicv = vmx_get_enable_apicv,
7726 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7727 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7728 .apicv_post_state_restore = vmx_apicv_post_state_restore,
7729 .hwapic_irr_update = vmx_hwapic_irr_update,
7730 .hwapic_isr_update = vmx_hwapic_isr_update,
7731 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7732 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7733 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7734 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt,
7736 .set_tss_addr = vmx_set_tss_addr,
7737 .set_identity_map_addr = vmx_set_identity_map_addr,
7738 .get_tdp_level = get_ept_level,
7739 .get_mt_mask = vmx_get_mt_mask,
7741 .get_exit_info = vmx_get_exit_info,
7743 .get_lpage_level = vmx_get_lpage_level,
7745 .cpuid_update = vmx_cpuid_update,
7747 .rdtscp_supported = vmx_rdtscp_supported,
7748 .invpcid_supported = vmx_invpcid_supported,
7750 .set_supported_cpuid = vmx_set_supported_cpuid,
7752 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7754 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
7755 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7757 .set_tdp_cr3 = vmx_set_cr3,
7759 .check_intercept = vmx_check_intercept,
7760 .handle_exit_irqoff = vmx_handle_exit_irqoff,
7761 .mpx_supported = vmx_mpx_supported,
7762 .xsaves_supported = vmx_xsaves_supported,
7763 .umip_emulated = vmx_umip_emulated,
7764 .pt_supported = vmx_pt_supported,
7766 .request_immediate_exit = vmx_request_immediate_exit,
7768 .sched_in = vmx_sched_in,
7770 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7771 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7772 .flush_log_dirty = vmx_flush_log_dirty,
7773 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7774 .write_log_dirty = vmx_write_pml_buffer,
7776 .pre_block = vmx_pre_block,
7777 .post_block = vmx_post_block,
7779 .pmu_ops = &intel_pmu_ops,
7781 .update_pi_irte = vmx_update_pi_irte,
7783 #ifdef CONFIG_X86_64
7784 .set_hv_timer = vmx_set_hv_timer,
7785 .cancel_hv_timer = vmx_cancel_hv_timer,
7788 .setup_mce = vmx_setup_mce,
7790 .smi_allowed = vmx_smi_allowed,
7791 .pre_enter_smm = vmx_pre_enter_smm,
7792 .pre_leave_smm = vmx_pre_leave_smm,
7793 .enable_smi_window = enable_smi_window,
7795 .check_nested_events = NULL,
7796 .get_nested_state = NULL,
7797 .set_nested_state = NULL,
7798 .get_vmcs12_pages = NULL,
7799 .nested_enable_evmcs = NULL,
7800 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
7803 static void vmx_cleanup_l1d_flush(void)
7805 if (vmx_l1d_flush_pages) {
7806 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7807 vmx_l1d_flush_pages = NULL;
7809 /* Restore state so sysfs ignores VMX */
7810 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7813 static void vmx_exit(void)
7815 #ifdef CONFIG_KEXEC_CORE
7816 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7822 #if IS_ENABLED(CONFIG_HYPERV)
7823 if (static_branch_unlikely(&enable_evmcs)) {
7825 struct hv_vp_assist_page *vp_ap;
7827 * Reset everything to support using non-enlightened VMCS
7828 * access later (e.g. when we reload the module with
7829 * enlightened_vmcs=0)
7831 for_each_online_cpu(cpu) {
7832 vp_ap = hv_get_vp_assist_page(cpu);
7837 vp_ap->current_nested_vmcs = 0;
7838 vp_ap->enlighten_vmentry = 0;
7841 static_branch_disable(&enable_evmcs);
7844 vmx_cleanup_l1d_flush();
7846 module_exit(vmx_exit);
7848 static int __init vmx_init(void)
7852 #if IS_ENABLED(CONFIG_HYPERV)
7854 * Enlightened VMCS usage should be recommended and the host needs
7855 * to support eVMCS v1 or above. We can also disable eVMCS support
7856 * with module parameter.
7858 if (enlightened_vmcs &&
7859 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7860 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7861 KVM_EVMCS_VERSION) {
7864 /* Check that we have assist pages on all online CPUs */
7865 for_each_online_cpu(cpu) {
7866 if (!hv_get_vp_assist_page(cpu)) {
7867 enlightened_vmcs = false;
7872 if (enlightened_vmcs) {
7873 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7874 static_branch_enable(&enable_evmcs);
7877 enlightened_vmcs = false;
7881 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7882 __alignof__(struct vcpu_vmx), THIS_MODULE);
7887 * Must be called after kvm_init() so enable_ept is properly set
7888 * up. Hand the parameter mitigation value in which was stored in
7889 * the pre module init parser. If no parameter was given, it will
7890 * contain 'auto' which will be turned into the default 'cond'
7893 if (boot_cpu_has(X86_BUG_L1TF)) {
7894 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7901 #ifdef CONFIG_KEXEC_CORE
7902 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7903 crash_vmclear_local_loaded_vmcss);
7905 vmx_check_vmcs12_offsets();
7909 module_init(vmx_init);