1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
5 #include <linux/kvm_host.h>
8 #include <asm/intel_pt.h>
10 #include "capabilities.h"
14 extern const u32 vmx_msr_index[];
17 extern u32 get_umwait_control_msr(void);
23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
25 #define NR_LOADSTORE_MSRS 8
29 struct vmx_msr_entry val[NR_LOADSTORE_MSRS];
32 struct shared_msr_entry {
38 enum segment_cache_field {
47 /* Posted-Interrupt Descriptor */
49 u32 pir[8]; /* Posted interrupt requested */
52 /* bit 256 - Outstanding Notification */
54 /* bit 257 - Suppress Notification */
56 /* bit 271:258 - Reserved */
58 /* bit 279:272 - Notification Vector */
60 /* bit 287:280 - Reserved */
62 /* bit 319:288 - Notification Destination */
70 #define RTIT_ADDR_RANGE 4
78 u64 addr_a[RTIT_ADDR_RANGE];
79 u64 addr_b[RTIT_ADDR_RANGE];
85 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
91 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
92 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
95 /* Has the level1 guest done vmxon? */
100 /* The guest-physical address of the current VMCS L1 keeps for L2 */
103 * Cache of the guest's VMCS, existing outside of guest memory.
104 * Loaded from guest memory during VMPTRLD. Flushed to guest
105 * memory during VMCLEAR and VMPTRLD.
107 struct vmcs12 *cached_vmcs12;
109 * Cache of the guest's shadow VMCS, existing outside of guest
110 * memory. Loaded from guest memory during VM entry. Flushed
111 * to guest memory during VM exit.
113 struct vmcs12 *cached_shadow_vmcs12;
116 * Indicates if the shadow vmcs or enlightened vmcs must be updated
117 * with the data held by struct vmcs12.
119 bool need_vmcs12_to_shadow_sync;
123 * Indicates lazily loaded guest state has not yet been decached from
126 bool need_sync_vmcs02_to_vmcs12_rare;
129 * vmcs02 has been initialized, i.e. state that is constant for
130 * vmcs02 has been written to the backing VMCS. Initialization
131 * is delayed until L1 actually attempts to run a nested VM.
133 bool vmcs02_initialized;
135 bool change_vmcs01_virtual_apic_mode;
138 * Enlightened VMCS has been enabled. It does not mean that L1 has to
139 * use it. However, VMX features available to L1 will be limited based
140 * on what the enlightened VMCS supports.
142 bool enlightened_vmcs_enabled;
144 /* L2 must run next, and mustn't decide to exit to L1. */
145 bool nested_run_pending;
147 struct loaded_vmcs vmcs02;
150 * Guest pages referred to in the vmcs02 with host-physical
151 * pointers, so we must keep them pinned while L2 runs.
153 struct page *apic_access_page;
154 struct kvm_host_map virtual_apic_map;
155 struct kvm_host_map pi_desc_map;
157 struct kvm_host_map msr_bitmap_map;
159 struct pi_desc *pi_desc;
163 struct hrtimer preemption_timer;
164 bool preemption_timer_expired;
166 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
168 u64 vmcs01_guest_bndcfgs;
170 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
171 int l1_tpr_threshold;
176 struct nested_vmx_msrs msrs;
178 /* SMM related state */
180 /* in VMX operation on SMM entry? */
182 /* in guest mode on SMM entry? */
186 gpa_t hv_evmcs_vmptr;
187 struct kvm_host_map hv_evmcs_map;
188 struct hv_enlightened_vmcs *hv_evmcs;
192 struct kvm_vcpu vcpu;
197 * If true, host state has been stored in vmx->loaded_vmcs for
198 * the CPU registers that only need to be switched when transitioning
199 * to/from the kernel, and the registers have been loaded with guest
200 * values. If false, host state is loaded in the CPU registers
201 * and vmx->loaded_vmcs->host_state is invalid.
203 bool guest_state_loaded;
206 u32 idt_vectoring_info;
209 struct shared_msr_entry *guest_msrs;
212 bool guest_msrs_ready;
214 u64 msr_host_kernel_gs_base;
215 u64 msr_guest_kernel_gs_base;
219 u32 msr_ia32_umwait_control;
221 u32 secondary_exec_control;
224 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
225 * non-nested (L1) guest, it always points to vmcs01. For a nested
226 * guest (L2), it points to a different VMCS.
228 struct loaded_vmcs vmcs01;
229 struct loaded_vmcs *loaded_vmcs;
231 struct msr_autoload {
232 struct vmx_msrs guest;
233 struct vmx_msrs host;
236 struct msr_autostore {
237 struct vmx_msrs guest;
243 struct kvm_segment segs[8];
246 u32 bitmask; /* 4 bits per segment (1 bit per field) */
247 struct kvm_save_segment {
255 bool emulation_required;
259 /* Posted interrupt descriptor */
260 struct pi_desc pi_desc;
262 /* Support for a guest hypervisor (nested VMX) */
263 struct nested_vmx nested;
265 /* Dynamic PLE window. */
266 unsigned int ple_window;
267 bool ple_window_dirty;
269 bool req_immediate_exit;
271 /* Support for PML */
272 #define PML_ENTITY_NUM 512
275 /* apic deadline value in host tsc */
278 u64 current_tsc_ratio;
282 unsigned long host_debugctlmsr;
285 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
286 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
287 * in msr_ia32_feature_control_valid_bits.
289 u64 msr_ia32_feature_control;
290 u64 msr_ia32_feature_control_valid_bits;
293 struct pt_desc pt_desc;
296 enum ept_pointers_status {
297 EPT_POINTERS_CHECK = 0,
298 EPT_POINTERS_MATCH = 1,
299 EPT_POINTERS_MISMATCH = 2
305 unsigned int tss_addr;
306 bool ept_identity_pagetable_done;
307 gpa_t ept_identity_map_addr;
309 enum ept_pointers_status ept_pointers_match;
310 spinlock_t ept_pointer_lock;
313 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
314 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
315 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
316 int allocate_vpid(void);
317 void free_vpid(int vpid);
318 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
319 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
320 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
321 unsigned long fs_base, unsigned long gs_base);
322 int vmx_get_cpl(struct kvm_vcpu *vcpu);
323 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
324 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
325 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
326 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
327 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
328 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
329 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
330 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
331 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
332 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
333 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
334 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
335 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
336 void update_exception_bitmap(struct kvm_vcpu *vcpu);
337 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
338 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
339 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
340 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
341 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
342 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
343 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
344 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr);
346 #define POSTED_INTR_ON 0
347 #define POSTED_INTR_SN 1
349 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
351 return test_and_set_bit(POSTED_INTR_ON,
352 (unsigned long *)&pi_desc->control);
355 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
357 return test_and_clear_bit(POSTED_INTR_ON,
358 (unsigned long *)&pi_desc->control);
361 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
363 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
366 static inline void pi_set_sn(struct pi_desc *pi_desc)
368 set_bit(POSTED_INTR_SN,
369 (unsigned long *)&pi_desc->control);
372 static inline void pi_set_on(struct pi_desc *pi_desc)
374 set_bit(POSTED_INTR_ON,
375 (unsigned long *)&pi_desc->control);
378 static inline void pi_clear_on(struct pi_desc *pi_desc)
380 clear_bit(POSTED_INTR_ON,
381 (unsigned long *)&pi_desc->control);
384 static inline int pi_test_on(struct pi_desc *pi_desc)
386 return test_bit(POSTED_INTR_ON,
387 (unsigned long *)&pi_desc->control);
390 static inline int pi_test_sn(struct pi_desc *pi_desc)
392 return test_bit(POSTED_INTR_SN,
393 (unsigned long *)&pi_desc->control);
396 static inline u8 vmx_get_rvi(void)
398 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
401 #define BUILD_CONTROLS_SHADOW(lname, uname) \
402 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
404 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
405 vmcs_write32(uname, val); \
406 vmx->loaded_vmcs->controls_shadow.lname = val; \
409 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
411 return vmx->loaded_vmcs->controls_shadow.lname; \
413 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
415 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
417 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
419 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
421 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
422 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
423 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
424 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
425 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
427 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
429 vmx->segment_cache.bitmask = 0;
432 static inline u32 vmx_vmentry_ctrl(void)
434 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
435 if (pt_mode == PT_MODE_SYSTEM)
436 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
437 VM_ENTRY_LOAD_IA32_RTIT_CTL);
438 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
439 return vmentry_ctrl &
440 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
443 static inline u32 vmx_vmexit_ctrl(void)
445 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
446 if (pt_mode == PT_MODE_SYSTEM)
447 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
448 VM_EXIT_CLEAR_IA32_RTIT_CTL);
449 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
451 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
454 u32 vmx_exec_control(struct vcpu_vmx *vmx);
455 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
457 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
459 return container_of(kvm, struct kvm_vmx, kvm);
462 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
464 return container_of(vcpu, struct vcpu_vmx, vcpu);
467 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
469 return &(to_vmx(vcpu)->pi_desc);
472 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
473 void free_vmcs(struct vmcs *vmcs);
474 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
475 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
476 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
477 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
479 static inline struct vmcs *alloc_vmcs(bool shadow)
481 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
485 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
487 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
490 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
491 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
493 ept_sync_context(construct_eptp(vcpu,
494 vcpu->arch.mmu->root_hpa));
496 vpid_sync_context(vpid);
500 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
502 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
505 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
507 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
508 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
511 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
513 return vmx->secondary_exec_control &
514 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
517 void dump_vmcs(void);
519 #endif /* __KVM_X86_VMX_H */