1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
5 #include <linux/kvm_host.h>
8 #include <asm/intel_pt.h>
10 #include "capabilities.h"
14 extern const u32 vmx_msr_index[];
21 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
23 #define NR_AUTOLOAD_MSRS 8
27 struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
30 struct shared_msr_entry {
36 enum segment_cache_field {
45 /* Posted-Interrupt Descriptor */
47 u32 pir[8]; /* Posted interrupt requested */
50 /* bit 256 - Outstanding Notification */
52 /* bit 257 - Suppress Notification */
54 /* bit 271:258 - Reserved */
56 /* bit 279:272 - Notification Vector */
58 /* bit 287:280 - Reserved */
60 /* bit 319:288 - Notification Destination */
68 #define RTIT_ADDR_RANGE 4
76 u64 addr_a[RTIT_ADDR_RANGE];
77 u64 addr_b[RTIT_ADDR_RANGE];
83 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
89 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
90 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
93 /* Has the level1 guest done vmxon? */
98 /* The guest-physical address of the current VMCS L1 keeps for L2 */
101 * Cache of the guest's VMCS, existing outside of guest memory.
102 * Loaded from guest memory during VMPTRLD. Flushed to guest
103 * memory during VMCLEAR and VMPTRLD.
105 struct vmcs12 *cached_vmcs12;
107 * Cache of the guest's shadow VMCS, existing outside of guest
108 * memory. Loaded from guest memory during VM entry. Flushed
109 * to guest memory during VM exit.
111 struct vmcs12 *cached_shadow_vmcs12;
114 * Indicates if the shadow vmcs or enlightened vmcs must be updated
115 * with the data held by struct vmcs12.
117 bool need_vmcs12_to_shadow_sync;
121 * Indicates lazily loaded guest state has not yet been decached from
124 bool need_sync_vmcs02_to_vmcs12_rare;
127 * vmcs02 has been initialized, i.e. state that is constant for
128 * vmcs02 has been written to the backing VMCS. Initialization
129 * is delayed until L1 actually attempts to run a nested VM.
131 bool vmcs02_initialized;
133 bool change_vmcs01_virtual_apic_mode;
136 * Enlightened VMCS has been enabled. It does not mean that L1 has to
137 * use it. However, VMX features available to L1 will be limited based
138 * on what the enlightened VMCS supports.
140 bool enlightened_vmcs_enabled;
142 /* L2 must run next, and mustn't decide to exit to L1. */
143 bool nested_run_pending;
145 struct loaded_vmcs vmcs02;
148 * Guest pages referred to in the vmcs02 with host-physical
149 * pointers, so we must keep them pinned while L2 runs.
151 struct page *apic_access_page;
152 struct kvm_host_map virtual_apic_map;
153 struct kvm_host_map pi_desc_map;
155 struct kvm_host_map msr_bitmap_map;
157 struct pi_desc *pi_desc;
161 struct hrtimer preemption_timer;
162 bool preemption_timer_expired;
164 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
166 u64 vmcs01_guest_bndcfgs;
171 struct nested_vmx_msrs msrs;
173 /* SMM related state */
175 /* in VMX operation on SMM entry? */
177 /* in guest mode on SMM entry? */
181 gpa_t hv_evmcs_vmptr;
182 struct kvm_host_map hv_evmcs_map;
183 struct hv_enlightened_vmcs *hv_evmcs;
187 struct kvm_vcpu vcpu;
192 * If true, host state has been stored in vmx->loaded_vmcs for
193 * the CPU registers that only need to be switched when transitioning
194 * to/from the kernel, and the registers have been loaded with guest
195 * values. If false, host state is loaded in the CPU registers
196 * and vmx->loaded_vmcs->host_state is invalid.
198 bool guest_state_loaded;
201 u32 idt_vectoring_info;
204 struct shared_msr_entry *guest_msrs;
207 bool guest_msrs_ready;
209 u64 msr_host_kernel_gs_base;
210 u64 msr_guest_kernel_gs_base;
215 u32 secondary_exec_control;
218 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
219 * non-nested (L1) guest, it always points to vmcs01. For a nested
220 * guest (L2), it points to a different VMCS.
222 struct loaded_vmcs vmcs01;
223 struct loaded_vmcs *loaded_vmcs;
225 struct msr_autoload {
226 struct vmx_msrs guest;
227 struct vmx_msrs host;
233 struct kvm_segment segs[8];
236 u32 bitmask; /* 4 bits per segment (1 bit per field) */
237 struct kvm_save_segment {
245 bool emulation_required;
249 /* Posted interrupt descriptor */
250 struct pi_desc pi_desc;
252 /* Support for a guest hypervisor (nested VMX) */
253 struct nested_vmx nested;
255 /* Dynamic PLE window. */
256 unsigned int ple_window;
257 bool ple_window_dirty;
259 bool req_immediate_exit;
261 /* Support for PML */
262 #define PML_ENTITY_NUM 512
265 /* apic deadline value in host tsc */
268 u64 current_tsc_ratio;
272 unsigned long host_debugctlmsr;
275 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
276 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
277 * in msr_ia32_feature_control_valid_bits.
279 u64 msr_ia32_feature_control;
280 u64 msr_ia32_feature_control_valid_bits;
283 struct pt_desc pt_desc;
286 enum ept_pointers_status {
287 EPT_POINTERS_CHECK = 0,
288 EPT_POINTERS_MATCH = 1,
289 EPT_POINTERS_MISMATCH = 2
295 unsigned int tss_addr;
296 bool ept_identity_pagetable_done;
297 gpa_t ept_identity_map_addr;
299 enum ept_pointers_status ept_pointers_match;
300 spinlock_t ept_pointer_lock;
303 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
304 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
305 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
306 int allocate_vpid(void);
307 void free_vpid(int vpid);
308 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
309 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
310 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
311 unsigned long fs_base, unsigned long gs_base);
312 int vmx_get_cpl(struct kvm_vcpu *vcpu);
313 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
314 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
315 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
316 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
317 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
318 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
319 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
320 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
321 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
322 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
323 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
324 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
325 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
326 void update_exception_bitmap(struct kvm_vcpu *vcpu);
327 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
328 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
329 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
330 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
331 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
332 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
333 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
335 #define POSTED_INTR_ON 0
336 #define POSTED_INTR_SN 1
338 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
340 return test_and_set_bit(POSTED_INTR_ON,
341 (unsigned long *)&pi_desc->control);
344 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
346 return test_and_clear_bit(POSTED_INTR_ON,
347 (unsigned long *)&pi_desc->control);
350 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
352 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
355 static inline void pi_set_sn(struct pi_desc *pi_desc)
357 set_bit(POSTED_INTR_SN,
358 (unsigned long *)&pi_desc->control);
361 static inline void pi_set_on(struct pi_desc *pi_desc)
363 set_bit(POSTED_INTR_ON,
364 (unsigned long *)&pi_desc->control);
367 static inline void pi_clear_on(struct pi_desc *pi_desc)
369 clear_bit(POSTED_INTR_ON,
370 (unsigned long *)&pi_desc->control);
373 static inline int pi_test_on(struct pi_desc *pi_desc)
375 return test_bit(POSTED_INTR_ON,
376 (unsigned long *)&pi_desc->control);
379 static inline int pi_test_sn(struct pi_desc *pi_desc)
381 return test_bit(POSTED_INTR_SN,
382 (unsigned long *)&pi_desc->control);
385 static inline u8 vmx_get_rvi(void)
387 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
390 #define BUILD_CONTROLS_SHADOW(lname, uname) \
391 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
393 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
394 vmcs_write32(uname, val); \
395 vmx->loaded_vmcs->controls_shadow.lname = val; \
398 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
400 return vmx->loaded_vmcs->controls_shadow.lname; \
402 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
404 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
406 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
408 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
410 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
411 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
412 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
413 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
414 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
416 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
418 vmx->segment_cache.bitmask = 0;
421 static inline u32 vmx_vmentry_ctrl(void)
423 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
424 if (pt_mode == PT_MODE_SYSTEM)
425 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
426 VM_ENTRY_LOAD_IA32_RTIT_CTL);
427 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
428 return vmentry_ctrl &
429 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
432 static inline u32 vmx_vmexit_ctrl(void)
434 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
435 if (pt_mode == PT_MODE_SYSTEM)
436 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
437 VM_EXIT_CLEAR_IA32_RTIT_CTL);
438 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
440 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
443 u32 vmx_exec_control(struct vcpu_vmx *vmx);
444 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
446 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
448 return container_of(kvm, struct kvm_vmx, kvm);
451 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
453 return container_of(vcpu, struct vcpu_vmx, vcpu);
456 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
458 return &(to_vmx(vcpu)->pi_desc);
461 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
462 void free_vmcs(struct vmcs *vmcs);
463 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
464 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
465 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
466 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
468 static inline struct vmcs *alloc_vmcs(bool shadow)
470 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
474 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
476 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
479 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
480 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
482 ept_sync_context(construct_eptp(vcpu,
483 vcpu->arch.mmu->root_hpa));
485 vpid_sync_context(vpid);
489 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
491 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
494 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
496 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
497 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
500 void dump_vmcs(void);
502 #endif /* __KVM_X86_VMX_H */