arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/cpu.h>
  42 #include <asm/io.h>
  43 #include <asm/desc.h>
  44 #include <asm/vmx.h>
  45 #include <asm/virtext.h>
  46 #include <asm/mce.h>
  47 #include <asm/fpu/internal.h>
  48 #include <asm/perf_event.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kexec.h>
  51 #include <asm/apic.h>
  52 #include <asm/irq_remapping.h>
  53 #include <asm/mmu_context.h>
  54 #include <asm/microcode.h>
  55 #include <asm/nospec-branch.h>
  56
  57 #include "trace.h"
  58 #include "pmu.h"
  59
  60 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  61 #define __ex_clear(x, reg) \
  62         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 static const struct x86_cpu_id vmx_cpu_id[] = {
  68         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  69         {}
  70 };
  71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  72
  73 static bool __read_mostly enable_vpid = 1;
  74 module_param_named(vpid, enable_vpid, bool, 0444);
  75
  76 static bool __read_mostly enable_vnmi = 1;
  77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  78
  79 static bool __read_mostly flexpriority_enabled = 1;
  80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  81
  82 static bool __read_mostly enable_ept = 1;
  83 module_param_named(ept, enable_ept, bool, S_IRUGO);
  84
  85 static bool __read_mostly enable_unrestricted_guest = 1;
  86 module_param_named(unrestricted_guest,
  87                         enable_unrestricted_guest, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_ept_ad_bits = 1;
  90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  91
  92 static bool __read_mostly emulate_invalid_guest_state = true;
  93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  94
  95 static bool __read_mostly fasteoi = 1;
  96 module_param(fasteoi, bool, S_IRUGO);
  97
  98 static bool __read_mostly enable_apicv = 1;
  99 module_param(enable_apicv, bool, S_IRUGO);
 100
 101 static bool __read_mostly enable_shadow_vmcs = 1;
 102 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 103 /*
 104  * If nested=1, nested virtualization is supported, i.e., guests may use
 105  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 106  * use VMX instructions.
 107  */
 108 static bool __read_mostly nested = 0;
 109 module_param(nested, bool, S_IRUGO);
 110
 111 static u64 __read_mostly host_xss;
 112
 113 static bool __read_mostly enable_pml = 1;
 114 module_param_named(pml, enable_pml, bool, S_IRUGO);
 115
 116 #define MSR_TYPE_R      1
 117 #define MSR_TYPE_W      2
 118 #define MSR_TYPE_RW     3
 119
 120 #define MSR_BITMAP_MODE_X2APIC          1
 121 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 122 #define MSR_BITMAP_MODE_LM              4
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 134 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 135 #define KVM_VM_CR0_ALWAYS_ON                                            \
 136         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 137 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 138         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 139          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 140
 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 143
 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 145
 146 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 147
 148 /*
 149  * Hyper-V requires all of these, so mark them as supported even though
 150  * they are just treated the same as all-context.
 151  */
 152 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 153         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 154         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 155         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 156         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 157
 158 /*
 159  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 160  * ple_gap:    upper bound on the amount of time between two successive
 161  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 162  *             According to test, this time is usually smaller than 128 cycles.
 163  * ple_window: upper bound on the amount of time a guest is allowed to execute
 164  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 165  *             less than 2^12 cycles
 166  * Time is measured based on a counter that runs at the same rate as the TSC,
 167  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 168  */
 169 #define KVM_VMX_DEFAULT_PLE_GAP           128
 170 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 171 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 172 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 173 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 174                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 175
 176 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 177 module_param(ple_gap, int, S_IRUGO);
 178
 179 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 180 module_param(ple_window, int, S_IRUGO);
 181
 182 /* Default doubles per-vcpu window every exit. */
 183 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 184 module_param(ple_window_grow, int, S_IRUGO);
 185
 186 /* Default resets per-vcpu window every exit to ple_window. */
 187 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 188 module_param(ple_window_shrink, int, S_IRUGO);
 189
 190 /* Default is to compute the maximum so we can never overflow. */
 191 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 192 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 193 module_param(ple_window_max, int, S_IRUGO);
 194
 195 extern const ulong vmx_return;
 196
 197 #define NR_AUTOLOAD_MSRS 8
 198
 199 struct vmcs {
 200         u32 revision_id;
 201         u32 abort;
 202         char data[0];
 203 };
 204
 205 /*
 206  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 207  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 208  * loaded on this CPU (so we can clear them if the CPU goes down).
 209  */
 210 struct loaded_vmcs {
 211         struct vmcs *vmcs;
 212         struct vmcs *shadow_vmcs;
 213         int cpu;
 214         bool launched;
 215         bool nmi_known_unmasked;
 216         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 217         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 218         /* Support for vnmi-less CPUs */
 219         int soft_vnmi_blocked;
 220         ktime_t entry_time;
 221         s64 vnmi_blocked_time;
 222         unsigned long *msr_bitmap;
 223         struct list_head loaded_vmcss_on_cpu_link;
 224 };
 225
 226 struct shared_msr_entry {
 227         unsigned index;
 228         u64 data;
 229         u64 mask;
 230 };
 231
 232 /*
 233  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 234  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 235  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 236  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 237  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 238  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 239  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 240  * underlying hardware which will be used to run L2.
 241  * This structure is packed to ensure that its layout is identical across
 242  * machines (necessary for live migration).
 243  * If there are changes in this struct, VMCS12_REVISION must be changed.
 244  */
 245 typedef u64 natural_width;
 246 struct __packed vmcs12 {
 247         /* According to the Intel spec, a VMCS region must start with the
 248          * following two fields. Then follow implementation-specific data.
 249          */
 250         u32 revision_id;
 251         u32 abort;
 252
 253         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 254         u32 padding[7]; /* room for future expansion */
 255
 256         u64 io_bitmap_a;
 257         u64 io_bitmap_b;
 258         u64 msr_bitmap;
 259         u64 vm_exit_msr_store_addr;
 260         u64 vm_exit_msr_load_addr;
 261         u64 vm_entry_msr_load_addr;
 262         u64 tsc_offset;
 263         u64 virtual_apic_page_addr;
 264         u64 apic_access_addr;
 265         u64 posted_intr_desc_addr;
 266         u64 vm_function_control;
 267         u64 ept_pointer;
 268         u64 eoi_exit_bitmap0;
 269         u64 eoi_exit_bitmap1;
 270         u64 eoi_exit_bitmap2;
 271         u64 eoi_exit_bitmap3;
 272         u64 eptp_list_address;
 273         u64 xss_exit_bitmap;
 274         u64 guest_physical_address;
 275         u64 vmcs_link_pointer;
 276         u64 pml_address;
 277         u64 guest_ia32_debugctl;
 278         u64 guest_ia32_pat;
 279         u64 guest_ia32_efer;
 280         u64 guest_ia32_perf_global_ctrl;
 281         u64 guest_pdptr0;
 282         u64 guest_pdptr1;
 283         u64 guest_pdptr2;
 284         u64 guest_pdptr3;
 285         u64 guest_bndcfgs;
 286         u64 host_ia32_pat;
 287         u64 host_ia32_efer;
 288         u64 host_ia32_perf_global_ctrl;
 289         u64 padding64[8]; /* room for future expansion */
 290         /*
 291          * To allow migration of L1 (complete with its L2 guests) between
 292          * machines of different natural widths (32 or 64 bit), we cannot have
 293          * unsigned long fields with no explict size. We use u64 (aliased
 294          * natural_width) instead. Luckily, x86 is little-endian.
 295          */
 296         natural_width cr0_guest_host_mask;
 297         natural_width cr4_guest_host_mask;
 298         natural_width cr0_read_shadow;
 299         natural_width cr4_read_shadow;
 300         natural_width cr3_target_value0;
 301         natural_width cr3_target_value1;
 302         natural_width cr3_target_value2;
 303         natural_width cr3_target_value3;
 304         natural_width exit_qualification;
 305         natural_width guest_linear_address;
 306         natural_width guest_cr0;
 307         natural_width guest_cr3;
 308         natural_width guest_cr4;
 309         natural_width guest_es_base;
 310         natural_width guest_cs_base;
 311         natural_width guest_ss_base;
 312         natural_width guest_ds_base;
 313         natural_width guest_fs_base;
 314         natural_width guest_gs_base;
 315         natural_width guest_ldtr_base;
 316         natural_width guest_tr_base;
 317         natural_width guest_gdtr_base;
 318         natural_width guest_idtr_base;
 319         natural_width guest_dr7;
 320         natural_width guest_rsp;
 321         natural_width guest_rip;
 322         natural_width guest_rflags;
 323         natural_width guest_pending_dbg_exceptions;
 324         natural_width guest_sysenter_esp;
 325         natural_width guest_sysenter_eip;
 326         natural_width host_cr0;
 327         natural_width host_cr3;
 328         natural_width host_cr4;
 329         natural_width host_fs_base;
 330         natural_width host_gs_base;
 331         natural_width host_tr_base;
 332         natural_width host_gdtr_base;
 333         natural_width host_idtr_base;
 334         natural_width host_ia32_sysenter_esp;
 335         natural_width host_ia32_sysenter_eip;
 336         natural_width host_rsp;
 337         natural_width host_rip;
 338         natural_width paddingl[8]; /* room for future expansion */
 339         u32 pin_based_vm_exec_control;
 340         u32 cpu_based_vm_exec_control;
 341         u32 exception_bitmap;
 342         u32 page_fault_error_code_mask;
 343         u32 page_fault_error_code_match;
 344         u32 cr3_target_count;
 345         u32 vm_exit_controls;
 346         u32 vm_exit_msr_store_count;
 347         u32 vm_exit_msr_load_count;
 348         u32 vm_entry_controls;
 349         u32 vm_entry_msr_load_count;
 350         u32 vm_entry_intr_info_field;
 351         u32 vm_entry_exception_error_code;
 352         u32 vm_entry_instruction_len;
 353         u32 tpr_threshold;
 354         u32 secondary_vm_exec_control;
 355         u32 vm_instruction_error;
 356         u32 vm_exit_reason;
 357         u32 vm_exit_intr_info;
 358         u32 vm_exit_intr_error_code;
 359         u32 idt_vectoring_info_field;
 360         u32 idt_vectoring_error_code;
 361         u32 vm_exit_instruction_len;
 362         u32 vmx_instruction_info;
 363         u32 guest_es_limit;
 364         u32 guest_cs_limit;
 365         u32 guest_ss_limit;
 366         u32 guest_ds_limit;
 367         u32 guest_fs_limit;
 368         u32 guest_gs_limit;
 369         u32 guest_ldtr_limit;
 370         u32 guest_tr_limit;
 371         u32 guest_gdtr_limit;
 372         u32 guest_idtr_limit;
 373         u32 guest_es_ar_bytes;
 374         u32 guest_cs_ar_bytes;
 375         u32 guest_ss_ar_bytes;
 376         u32 guest_ds_ar_bytes;
 377         u32 guest_fs_ar_bytes;
 378         u32 guest_gs_ar_bytes;
 379         u32 guest_ldtr_ar_bytes;
 380         u32 guest_tr_ar_bytes;
 381         u32 guest_interruptibility_info;
 382         u32 guest_activity_state;
 383         u32 guest_sysenter_cs;
 384         u32 host_ia32_sysenter_cs;
 385         u32 vmx_preemption_timer_value;
 386         u32 padding32[7]; /* room for future expansion */
 387         u16 virtual_processor_id;
 388         u16 posted_intr_nv;
 389         u16 guest_es_selector;
 390         u16 guest_cs_selector;
 391         u16 guest_ss_selector;
 392         u16 guest_ds_selector;
 393         u16 guest_fs_selector;
 394         u16 guest_gs_selector;
 395         u16 guest_ldtr_selector;
 396         u16 guest_tr_selector;
 397         u16 guest_intr_status;
 398         u16 guest_pml_index;
 399         u16 host_es_selector;
 400         u16 host_cs_selector;
 401         u16 host_ss_selector;
 402         u16 host_ds_selector;
 403         u16 host_fs_selector;
 404         u16 host_gs_selector;
 405         u16 host_tr_selector;
 406 };
 407
 408 /*
 409  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 410  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 411  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 412  */
 413 #define VMCS12_REVISION 0x11e57ed0
 414
 415 /*
 416  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 417  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 418  * current implementation, 4K are reserved to avoid future complications.
 419  */
 420 #define VMCS12_SIZE 0x1000
 421
 422 /*
 423  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 424  * supported VMCS12 field encoding.
 425  */
 426 #define VMCS12_MAX_FIELD_INDEX 0x17
 427
 428 /*
 429  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 430  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 431  */
 432 struct nested_vmx {
 433         /* Has the level1 guest done vmxon? */
 434         bool vmxon;
 435         gpa_t vmxon_ptr;
 436         bool pml_full;
 437
 438         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 439         gpa_t current_vmptr;
 440         /*
 441          * Cache of the guest's VMCS, existing outside of guest memory.
 442          * Loaded from guest memory during VMPTRLD. Flushed to guest
 443          * memory during VMCLEAR and VMPTRLD.
 444          */
 445         struct vmcs12 *cached_vmcs12;
 446         /*
 447          * Indicates if the shadow vmcs must be updated with the
 448          * data hold by vmcs12
 449          */
 450         bool sync_shadow_vmcs;
 451         bool dirty_vmcs12;
 452
 453         bool change_vmcs01_virtual_x2apic_mode;
 454         /* L2 must run next, and mustn't decide to exit to L1. */
 455         bool nested_run_pending;
 456
 457         struct loaded_vmcs vmcs02;
 458
 459         /*
 460          * Guest pages referred to in the vmcs02 with host-physical
 461          * pointers, so we must keep them pinned while L2 runs.
 462          */
 463         struct page *apic_access_page;
 464         struct page *virtual_apic_page;
 465         struct page *pi_desc_page;
 466         struct pi_desc *pi_desc;
 467         bool pi_pending;
 468         u16 posted_intr_nv;
 469
 470         struct hrtimer preemption_timer;
 471         bool preemption_timer_expired;
 472
 473         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 474         u64 vmcs01_debugctl;
 475
 476         u16 vpid02;
 477         u16 last_vpid;
 478
 479         /*
 480          * We only store the "true" versions of the VMX capability MSRs. We
 481          * generate the "non-true" versions by setting the must-be-1 bits
 482          * according to the SDM.
 483          */
 484         u32 nested_vmx_procbased_ctls_low;
 485         u32 nested_vmx_procbased_ctls_high;
 486         u32 nested_vmx_secondary_ctls_low;
 487         u32 nested_vmx_secondary_ctls_high;
 488         u32 nested_vmx_pinbased_ctls_low;
 489         u32 nested_vmx_pinbased_ctls_high;
 490         u32 nested_vmx_exit_ctls_low;
 491         u32 nested_vmx_exit_ctls_high;
 492         u32 nested_vmx_entry_ctls_low;
 493         u32 nested_vmx_entry_ctls_high;
 494         u32 nested_vmx_misc_low;
 495         u32 nested_vmx_misc_high;
 496         u32 nested_vmx_ept_caps;
 497         u32 nested_vmx_vpid_caps;
 498         u64 nested_vmx_basic;
 499         u64 nested_vmx_cr0_fixed0;
 500         u64 nested_vmx_cr0_fixed1;
 501         u64 nested_vmx_cr4_fixed0;
 502         u64 nested_vmx_cr4_fixed1;
 503         u64 nested_vmx_vmcs_enum;
 504         u64 nested_vmx_vmfunc_controls;
 505
 506         /* SMM related state */
 507         struct {
 508                 /* in VMX operation on SMM entry? */
 509                 bool vmxon;
 510                 /* in guest mode on SMM entry? */
 511                 bool guest_mode;
 512         } smm;
 513 };
 514
 515 #define POSTED_INTR_ON  0
 516 #define POSTED_INTR_SN  1
 517
 518 /* Posted-Interrupt Descriptor */
 519 struct pi_desc {
 520         u32 pir[8];     /* Posted interrupt requested */
 521         union {
 522                 struct {
 523                                 /* bit 256 - Outstanding Notification */
 524                         u16     on      : 1,
 525                                 /* bit 257 - Suppress Notification */
 526                                 sn      : 1,
 527                                 /* bit 271:258 - Reserved */
 528                                 rsvd_1  : 14;
 529                                 /* bit 279:272 - Notification Vector */
 530                         u8      nv;
 531                                 /* bit 287:280 - Reserved */
 532                         u8      rsvd_2;
 533                                 /* bit 319:288 - Notification Destination */
 534                         u32     ndst;
 535                 };
 536                 u64 control;
 537         };
 538         u32 rsvd[6];
 539 } __aligned(64);
 540
 541 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 542 {
 543         return test_and_set_bit(POSTED_INTR_ON,
 544                         (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 548 {
 549         return test_and_clear_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 554 {
 555         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 556 }
 557
 558 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 559 {
 560         return clear_bit(POSTED_INTR_SN,
 561                         (unsigned long *)&pi_desc->control);
 562 }
 563
 564 static inline void pi_set_sn(struct pi_desc *pi_desc)
 565 {
 566         return set_bit(POSTED_INTR_SN,
 567                         (unsigned long *)&pi_desc->control);
 568 }
 569
 570 static inline void pi_clear_on(struct pi_desc *pi_desc)
 571 {
 572         clear_bit(POSTED_INTR_ON,
 573                   (unsigned long *)&pi_desc->control);
 574 }
 575
 576 static inline int pi_test_on(struct pi_desc *pi_desc)
 577 {
 578         return test_bit(POSTED_INTR_ON,
 579                         (unsigned long *)&pi_desc->control);
 580 }
 581
 582 static inline int pi_test_sn(struct pi_desc *pi_desc)
 583 {
 584         return test_bit(POSTED_INTR_SN,
 585                         (unsigned long *)&pi_desc->control);
 586 }
 587
 588 struct vcpu_vmx {
 589         struct kvm_vcpu       vcpu;
 590         unsigned long         host_rsp;
 591         u8                    fail;
 592         u8                    msr_bitmap_mode;
 593         u32                   exit_intr_info;
 594         u32                   idt_vectoring_info;
 595         ulong                 rflags;
 596         struct shared_msr_entry *guest_msrs;
 597         int                   nmsrs;
 598         int                   save_nmsrs;
 599         unsigned long         host_idt_base;
 600 #ifdef CONFIG_X86_64
 601         u64                   msr_host_kernel_gs_base;
 602         u64                   msr_guest_kernel_gs_base;
 603 #endif
 604
 605         u64                   arch_capabilities;
 606         u64                   spec_ctrl;
 607
 608         u32 vm_entry_controls_shadow;
 609         u32 vm_exit_controls_shadow;
 610         u32 secondary_exec_control;
 611
 612         /*
 613          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 614          * non-nested (L1) guest, it always points to vmcs01. For a nested
 615          * guest (L2), it points to a different VMCS.
 616          */
 617         struct loaded_vmcs    vmcs01;
 618         struct loaded_vmcs   *loaded_vmcs;
 619         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 620         struct msr_autoload {
 621                 unsigned nr;
 622                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 623                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 624         } msr_autoload;
 625         struct {
 626                 int           loaded;
 627                 u16           fs_sel, gs_sel, ldt_sel;
 628 #ifdef CONFIG_X86_64
 629                 u16           ds_sel, es_sel;
 630 #endif
 631                 int           gs_ldt_reload_needed;
 632                 int           fs_reload_needed;
 633                 u64           msr_host_bndcfgs;
 634         } host_state;
 635         struct {
 636                 int vm86_active;
 637                 ulong save_rflags;
 638                 struct kvm_segment segs[8];
 639         } rmode;
 640         struct {
 641                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 642                 struct kvm_save_segment {
 643                         u16 selector;
 644                         unsigned long base;
 645                         u32 limit;
 646                         u32 ar;
 647                 } seg[8];
 648         } segment_cache;
 649         int vpid;
 650         bool emulation_required;
 651
 652         u32 exit_reason;
 653
 654         /* Posted interrupt descriptor */
 655         struct pi_desc pi_desc;
 656
 657         /* Support for a guest hypervisor (nested VMX) */
 658         struct nested_vmx nested;
 659
 660         /* Dynamic PLE window. */
 661         int ple_window;
 662         bool ple_window_dirty;
 663
 664         /* Support for PML */
 665 #define PML_ENTITY_NUM          512
 666         struct page *pml_pg;
 667
 668         /* apic deadline value in host tsc */
 669         u64 hv_deadline_tsc;
 670
 671         u64 current_tsc_ratio;
 672
 673         u32 host_pkru;
 674
 675         unsigned long host_debugctlmsr;
 676
 677         /*
 678          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 679          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 680          * in msr_ia32_feature_control_valid_bits.
 681          */
 682         u64 msr_ia32_feature_control;
 683         u64 msr_ia32_feature_control_valid_bits;
 684 };
 685
 686 enum segment_cache_field {
 687         SEG_FIELD_SEL = 0,
 688         SEG_FIELD_BASE = 1,
 689         SEG_FIELD_LIMIT = 2,
 690         SEG_FIELD_AR = 3,
 691
 692         SEG_FIELD_NR = 4
 693 };
 694
 695 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 696 {
 697         return container_of(vcpu, struct vcpu_vmx, vcpu);
 698 }
 699
 700 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 701 {
 702         return &(to_vmx(vcpu)->pi_desc);
 703 }
 704
 705 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
 706 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 707 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
 708 #define FIELD64(number, name)                                           \
 709         FIELD(number, name),                                            \
 710         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
 711
 712
 713 static u16 shadow_read_only_fields[] = {
 714 #define SHADOW_FIELD_RO(x) x,
 715 #include "vmx_shadow_fields.h"
 716 };
 717 static int max_shadow_read_only_fields =
 718         ARRAY_SIZE(shadow_read_only_fields);
 719
 720 static u16 shadow_read_write_fields[] = {
 721 #define SHADOW_FIELD_RW(x) x,
 722 #include "vmx_shadow_fields.h"
 723 };
 724 static int max_shadow_read_write_fields =
 725         ARRAY_SIZE(shadow_read_write_fields);
 726
 727 static const unsigned short vmcs_field_to_offset_table[] = {
 728         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 729         FIELD(POSTED_INTR_NV, posted_intr_nv),
 730         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 731         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 732         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 733         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 734         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 735         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 736         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 737         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 738         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 739         FIELD(GUEST_PML_INDEX, guest_pml_index),
 740         FIELD(HOST_ES_SELECTOR, host_es_selector),
 741         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 742         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 743         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 744         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 745         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 746         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 747         FIELD64(IO_BITMAP_A, io_bitmap_a),
 748         FIELD64(IO_BITMAP_B, io_bitmap_b),
 749         FIELD64(MSR_BITMAP, msr_bitmap),
 750         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 751         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 752         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 753         FIELD64(TSC_OFFSET, tsc_offset),
 754         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 755         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 756         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 757         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 758         FIELD64(EPT_POINTER, ept_pointer),
 759         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 760         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 761         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 762         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 763         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 764         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 765         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 766         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 767         FIELD64(PML_ADDRESS, pml_address),
 768         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 769         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 770         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 771         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 772         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 773         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 774         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 775         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 776         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 777         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 778         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 779         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 780         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 781         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 782         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 783         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 784         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 785         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 786         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 787         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 788         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 789         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 790         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 791         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 792         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 793         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 794         FIELD(TPR_THRESHOLD, tpr_threshold),
 795         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 796         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 797         FIELD(VM_EXIT_REASON, vm_exit_reason),
 798         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 799         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 800         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 801         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 802         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 803         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 804         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 805         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 806         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 807         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 808         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 809         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 810         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 811         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 812         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 813         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 814         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 815         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 816         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 817         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 818         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 819         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 820         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 821         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 822         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 823         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 824         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 825         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 826         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 827         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 828         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 829         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 830         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 831         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 832         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 833         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 834         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 835         FIELD(EXIT_QUALIFICATION, exit_qualification),
 836         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 837         FIELD(GUEST_CR0, guest_cr0),
 838         FIELD(GUEST_CR3, guest_cr3),
 839         FIELD(GUEST_CR4, guest_cr4),
 840         FIELD(GUEST_ES_BASE, guest_es_base),
 841         FIELD(GUEST_CS_BASE, guest_cs_base),
 842         FIELD(GUEST_SS_BASE, guest_ss_base),
 843         FIELD(GUEST_DS_BASE, guest_ds_base),
 844         FIELD(GUEST_FS_BASE, guest_fs_base),
 845         FIELD(GUEST_GS_BASE, guest_gs_base),
 846         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 847         FIELD(GUEST_TR_BASE, guest_tr_base),
 848         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 849         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 850         FIELD(GUEST_DR7, guest_dr7),
 851         FIELD(GUEST_RSP, guest_rsp),
 852         FIELD(GUEST_RIP, guest_rip),
 853         FIELD(GUEST_RFLAGS, guest_rflags),
 854         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 855         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 856         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 857         FIELD(HOST_CR0, host_cr0),
 858         FIELD(HOST_CR3, host_cr3),
 859         FIELD(HOST_CR4, host_cr4),
 860         FIELD(HOST_FS_BASE, host_fs_base),
 861         FIELD(HOST_GS_BASE, host_gs_base),
 862         FIELD(HOST_TR_BASE, host_tr_base),
 863         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 864         FIELD(HOST_IDTR_BASE, host_idtr_base),
 865         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 866         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 867         FIELD(HOST_RSP, host_rsp),
 868         FIELD(HOST_RIP, host_rip),
 869 };
 870
 871 static inline short vmcs_field_to_offset(unsigned long field)
 872 {
 873         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
 874         unsigned short offset;
 875         unsigned index;
 876
 877         if (field >> 15)
 878                 return -ENOENT;
 879
 880         index = ROL16(field, 6);
 881         if (index >= size)
 882                 return -ENOENT;
 883
 884         index = array_index_nospec(index, size);
 885         offset = vmcs_field_to_offset_table[index];
 886         if (offset == 0)
 887                 return -ENOENT;
 888         return offset;
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 897 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 898 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 899 static bool vmx_xsaves_supported(void);
 900 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 901                             struct kvm_segment *var, int seg);
 902 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 903                             struct kvm_segment *var, int seg);
 904 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 905 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 906 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 907 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 908 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 909 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 910                                             u16 error_code);
 911 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 912 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 913                                                           u32 msr, int type);
 914
 915 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 916 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 917 /*
 918  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 919  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 920  */
 921 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 922
 923 /*
 924  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 925  * can find which vCPU should be waken up.
 926  */
 927 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 928 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 929
 930 enum {
 931         VMX_VMREAD_BITMAP,
 932         VMX_VMWRITE_BITMAP,
 933         VMX_BITMAP_NR
 934 };
 935
 936 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 937
 938 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 939 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 940
 941 static bool cpu_has_load_ia32_efer;
 942 static bool cpu_has_load_perf_global_ctrl;
 943
 944 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 945 static DEFINE_SPINLOCK(vmx_vpid_lock);
 946
 947 static struct vmcs_config {
 948         int size;
 949         int order;
 950         u32 basic_cap;
 951         u32 revision_id;
 952         u32 pin_based_exec_ctrl;
 953         u32 cpu_based_exec_ctrl;
 954         u32 cpu_based_2nd_exec_ctrl;
 955         u32 vmexit_ctrl;
 956         u32 vmentry_ctrl;
 957 } vmcs_config;
 958
 959 static struct vmx_capability {
 960         u32 ept;
 961         u32 vpid;
 962 } vmx_capability;
 963
 964 #define VMX_SEGMENT_FIELD(seg)                                  \
 965         [VCPU_SREG_##seg] = {                                   \
 966                 .selector = GUEST_##seg##_SELECTOR,             \
 967                 .base = GUEST_##seg##_BASE,                     \
 968                 .limit = GUEST_##seg##_LIMIT,                   \
 969                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 970         }
 971
 972 static const struct kvm_vmx_segment_field {
 973         unsigned selector;
 974         unsigned base;
 975         unsigned limit;
 976         unsigned ar_bytes;
 977 } kvm_vmx_segment_fields[] = {
 978         VMX_SEGMENT_FIELD(CS),
 979         VMX_SEGMENT_FIELD(DS),
 980         VMX_SEGMENT_FIELD(ES),
 981         VMX_SEGMENT_FIELD(FS),
 982         VMX_SEGMENT_FIELD(GS),
 983         VMX_SEGMENT_FIELD(SS),
 984         VMX_SEGMENT_FIELD(TR),
 985         VMX_SEGMENT_FIELD(LDTR),
 986 };
 987
 988 static u64 host_efer;
 989
 990 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 991
 992 /*
 993  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 994  * away by decrementing the array size.
 995  */
 996 static const u32 vmx_msr_index[] = {
 997 #ifdef CONFIG_X86_64
 998         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 999 #endif
1000         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1001 };
1002
1003 static inline bool is_exception_n(u32 intr_info, u8 vector)
1004 {
1005         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1006                              INTR_INFO_VALID_MASK)) ==
1007                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1008 }
1009
1010 static inline bool is_debug(u32 intr_info)
1011 {
1012         return is_exception_n(intr_info, DB_VECTOR);
1013 }
1014
1015 static inline bool is_breakpoint(u32 intr_info)
1016 {
1017         return is_exception_n(intr_info, BP_VECTOR);
1018 }
1019
1020 static inline bool is_page_fault(u32 intr_info)
1021 {
1022         return is_exception_n(intr_info, PF_VECTOR);
1023 }
1024
1025 static inline bool is_no_device(u32 intr_info)
1026 {
1027         return is_exception_n(intr_info, NM_VECTOR);
1028 }
1029
1030 static inline bool is_invalid_opcode(u32 intr_info)
1031 {
1032         return is_exception_n(intr_info, UD_VECTOR);
1033 }
1034
1035 static inline bool is_external_interrupt(u32 intr_info)
1036 {
1037         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1038                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1039 }
1040
1041 static inline bool is_machine_check(u32 intr_info)
1042 {
1043         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1044                              INTR_INFO_VALID_MASK)) ==
1045                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1046 }
1047
1048 static inline bool cpu_has_vmx_msr_bitmap(void)
1049 {
1050         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1051 }
1052
1053 static inline bool cpu_has_vmx_tpr_shadow(void)
1054 {
1055         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1056 }
1057
1058 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1059 {
1060         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1061 }
1062
1063 static inline bool cpu_has_secondary_exec_ctrls(void)
1064 {
1065         return vmcs_config.cpu_based_exec_ctrl &
1066                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1067 }
1068
1069 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1070 {
1071         return vmcs_config.cpu_based_2nd_exec_ctrl &
1072                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1073 }
1074
1075 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1076 {
1077         return vmcs_config.cpu_based_2nd_exec_ctrl &
1078                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1079 }
1080
1081 static inline bool cpu_has_vmx_apic_register_virt(void)
1082 {
1083         return vmcs_config.cpu_based_2nd_exec_ctrl &
1084                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1085 }
1086
1087 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1088 {
1089         return vmcs_config.cpu_based_2nd_exec_ctrl &
1090                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1091 }
1092
1093 /*
1094  * Comment's format: document - errata name - stepping - processor name.
1095  * Refer from
1096  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1097  */
1098 static u32 vmx_preemption_cpu_tfms[] = {
1099 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1100 0x000206E6,
1101 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1102 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1103 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1104 0x00020652,
1105 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1106 0x00020655,
1107 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1108 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1109 /*
1110  * 320767.pdf - AAP86  - B1 -
1111  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1112  */
1113 0x000106E5,
1114 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1115 0x000106A0,
1116 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1117 0x000106A1,
1118 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1119 0x000106A4,
1120  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1121  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1122  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1123 0x000106A5,
1124 };
1125
1126 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1127 {
1128         u32 eax = cpuid_eax(0x00000001), i;
1129
1130         /* Clear the reserved bits */
1131         eax &= ~(0x3U << 14 | 0xfU << 28);
1132         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1133                 if (eax == vmx_preemption_cpu_tfms[i])
1134                         return true;
1135
1136         return false;
1137 }
1138
1139 static inline bool cpu_has_vmx_preemption_timer(void)
1140 {
1141         return vmcs_config.pin_based_exec_ctrl &
1142                 PIN_BASED_VMX_PREEMPTION_TIMER;
1143 }
1144
1145 static inline bool cpu_has_vmx_posted_intr(void)
1146 {
1147         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1148                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1149 }
1150
1151 static inline bool cpu_has_vmx_apicv(void)
1152 {
1153         return cpu_has_vmx_apic_register_virt() &&
1154                 cpu_has_vmx_virtual_intr_delivery() &&
1155                 cpu_has_vmx_posted_intr();
1156 }
1157
1158 static inline bool cpu_has_vmx_flexpriority(void)
1159 {
1160         return cpu_has_vmx_tpr_shadow() &&
1161                 cpu_has_vmx_virtualize_apic_accesses();
1162 }
1163
1164 static inline bool cpu_has_vmx_ept_execute_only(void)
1165 {
1166         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1167 }
1168
1169 static inline bool cpu_has_vmx_ept_2m_page(void)
1170 {
1171         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1172 }
1173
1174 static inline bool cpu_has_vmx_ept_1g_page(void)
1175 {
1176         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1177 }
1178
1179 static inline bool cpu_has_vmx_ept_4levels(void)
1180 {
1181         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1182 }
1183
1184 static inline bool cpu_has_vmx_ept_mt_wb(void)
1185 {
1186         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1187 }
1188
1189 static inline bool cpu_has_vmx_ept_5levels(void)
1190 {
1191         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1192 }
1193
1194 static inline bool cpu_has_vmx_ept_ad_bits(void)
1195 {
1196         return vmx_capability.ept & VMX_EPT_AD_BIT;
1197 }
1198
1199 static inline bool cpu_has_vmx_invept_context(void)
1200 {
1201         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1202 }
1203
1204 static inline bool cpu_has_vmx_invept_global(void)
1205 {
1206         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1207 }
1208
1209 static inline bool cpu_has_vmx_invvpid_single(void)
1210 {
1211         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1212 }
1213
1214 static inline bool cpu_has_vmx_invvpid_global(void)
1215 {
1216         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1217 }
1218
1219 static inline bool cpu_has_vmx_invvpid(void)
1220 {
1221         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1222 }
1223
1224 static inline bool cpu_has_vmx_ept(void)
1225 {
1226         return vmcs_config.cpu_based_2nd_exec_ctrl &
1227                 SECONDARY_EXEC_ENABLE_EPT;
1228 }
1229
1230 static inline bool cpu_has_vmx_unrestricted_guest(void)
1231 {
1232         return vmcs_config.cpu_based_2nd_exec_ctrl &
1233                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1234 }
1235
1236 static inline bool cpu_has_vmx_ple(void)
1237 {
1238         return vmcs_config.cpu_based_2nd_exec_ctrl &
1239                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1240 }
1241
1242 static inline bool cpu_has_vmx_basic_inout(void)
1243 {
1244         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1245 }
1246
1247 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1248 {
1249         return flexpriority_enabled && lapic_in_kernel(vcpu);
1250 }
1251
1252 static inline bool cpu_has_vmx_vpid(void)
1253 {
1254         return vmcs_config.cpu_based_2nd_exec_ctrl &
1255                 SECONDARY_EXEC_ENABLE_VPID;
1256 }
1257
1258 static inline bool cpu_has_vmx_rdtscp(void)
1259 {
1260         return vmcs_config.cpu_based_2nd_exec_ctrl &
1261                 SECONDARY_EXEC_RDTSCP;
1262 }
1263
1264 static inline bool cpu_has_vmx_invpcid(void)
1265 {
1266         return vmcs_config.cpu_based_2nd_exec_ctrl &
1267                 SECONDARY_EXEC_ENABLE_INVPCID;
1268 }
1269
1270 static inline bool cpu_has_virtual_nmis(void)
1271 {
1272         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1273 }
1274
1275 static inline bool cpu_has_vmx_wbinvd_exit(void)
1276 {
1277         return vmcs_config.cpu_based_2nd_exec_ctrl &
1278                 SECONDARY_EXEC_WBINVD_EXITING;
1279 }
1280
1281 static inline bool cpu_has_vmx_shadow_vmcs(void)
1282 {
1283         u64 vmx_msr;
1284         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1285         /* check if the cpu supports writing r/o exit information fields */
1286         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1287                 return false;
1288
1289         return vmcs_config.cpu_based_2nd_exec_ctrl &
1290                 SECONDARY_EXEC_SHADOW_VMCS;
1291 }
1292
1293 static inline bool cpu_has_vmx_pml(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1296 }
1297
1298 static inline bool cpu_has_vmx_tsc_scaling(void)
1299 {
1300         return vmcs_config.cpu_based_2nd_exec_ctrl &
1301                 SECONDARY_EXEC_TSC_SCALING;
1302 }
1303
1304 static inline bool cpu_has_vmx_vmfunc(void)
1305 {
1306         return vmcs_config.cpu_based_2nd_exec_ctrl &
1307                 SECONDARY_EXEC_ENABLE_VMFUNC;
1308 }
1309
1310 static inline bool report_flexpriority(void)
1311 {
1312         return flexpriority_enabled;
1313 }
1314
1315 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1316 {
1317         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1318 }
1319
1320 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1321 {
1322         return vmcs12->cpu_based_vm_exec_control & bit;
1323 }
1324
1325 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1326 {
1327         return (vmcs12->cpu_based_vm_exec_control &
1328                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1329                 (vmcs12->secondary_vm_exec_control & bit);
1330 }
1331
1332 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1333 {
1334         return vmcs12->pin_based_vm_exec_control &
1335                 PIN_BASED_VMX_PREEMPTION_TIMER;
1336 }
1337
1338 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1339 {
1340         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1341 }
1342
1343 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1344 {
1345         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1346 }
1347
1348 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1349 {
1350         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1351 }
1352
1353 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1354 {
1355         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1356 }
1357
1358 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1359 {
1360         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1361 }
1362
1363 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1364 {
1365         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1366 }
1367
1368 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1369 {
1370         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1371 }
1372
1373 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1374 {
1375         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1376 }
1377
1378 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1379 {
1380         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1381 }
1382
1383 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1384 {
1385         return nested_cpu_has_vmfunc(vmcs12) &&
1386                 (vmcs12->vm_function_control &
1387                  VMX_VMFUNC_EPTP_SWITCHING);
1388 }
1389
1390 static inline bool is_nmi(u32 intr_info)
1391 {
1392         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1393                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1394 }
1395
1396 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1397                               u32 exit_intr_info,
1398                               unsigned long exit_qualification);
1399 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1400                         struct vmcs12 *vmcs12,
1401                         u32 reason, unsigned long qualification);
1402
1403 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1404 {
1405         int i;
1406
1407         for (i = 0; i < vmx->nmsrs; ++i)
1408                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1409                         return i;
1410         return -1;
1411 }
1412
1413 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1414 {
1415     struct {
1416         u64 vpid : 16;
1417         u64 rsvd : 48;
1418         u64 gva;
1419     } operand = { vpid, 0, gva };
1420
1421     asm volatile (__ex(ASM_VMX_INVVPID)
1422                   /* CF==1 or ZF==1 --> rc = -1 */
1423                   "; ja 1f ; ud2 ; 1:"
1424                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1425 }
1426
1427 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1428 {
1429         struct {
1430                 u64 eptp, gpa;
1431         } operand = {eptp, gpa};
1432
1433         asm volatile (__ex(ASM_VMX_INVEPT)
1434                         /* CF==1 or ZF==1 --> rc = -1 */
1435                         "; ja 1f ; ud2 ; 1:\n"
1436                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1437 }
1438
1439 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1440 {
1441         int i;
1442
1443         i = __find_msr_index(vmx, msr);
1444         if (i >= 0)
1445                 return &vmx->guest_msrs[i];
1446         return NULL;
1447 }
1448
1449 static void vmcs_clear(struct vmcs *vmcs)
1450 {
1451         u64 phys_addr = __pa(vmcs);
1452         u8 error;
1453
1454         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1455                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1456                       : "cc", "memory");
1457         if (error)
1458                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1459                        vmcs, phys_addr);
1460 }
1461
1462 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1463 {
1464         vmcs_clear(loaded_vmcs->vmcs);
1465         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1466                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1467         loaded_vmcs->cpu = -1;
1468         loaded_vmcs->launched = 0;
1469 }
1470
1471 static void vmcs_load(struct vmcs *vmcs)
1472 {
1473         u64 phys_addr = __pa(vmcs);
1474         u8 error;
1475
1476         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1477                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1478                         : "cc", "memory");
1479         if (error)
1480                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1481                        vmcs, phys_addr);
1482 }
1483
1484 #ifdef CONFIG_KEXEC_CORE
1485 /*
1486  * This bitmap is used to indicate whether the vmclear
1487  * operation is enabled on all cpus. All disabled by
1488  * default.
1489  */
1490 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1491
1492 static inline void crash_enable_local_vmclear(int cpu)
1493 {
1494         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1495 }
1496
1497 static inline void crash_disable_local_vmclear(int cpu)
1498 {
1499         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500 }
1501
1502 static inline int crash_local_vmclear_enabled(int cpu)
1503 {
1504         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505 }
1506
1507 static void crash_vmclear_local_loaded_vmcss(void)
1508 {
1509         int cpu = raw_smp_processor_id();
1510         struct loaded_vmcs *v;
1511
1512         if (!crash_local_vmclear_enabled(cpu))
1513                 return;
1514
1515         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1516                             loaded_vmcss_on_cpu_link)
1517                 vmcs_clear(v->vmcs);
1518 }
1519 #else
1520 static inline void crash_enable_local_vmclear(int cpu) { }
1521 static inline void crash_disable_local_vmclear(int cpu) { }
1522 #endif /* CONFIG_KEXEC_CORE */
1523
1524 static void __loaded_vmcs_clear(void *arg)
1525 {
1526         struct loaded_vmcs *loaded_vmcs = arg;
1527         int cpu = raw_smp_processor_id();
1528
1529         if (loaded_vmcs->cpu != cpu)
1530                 return; /* vcpu migration can race with cpu offline */
1531         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1532                 per_cpu(current_vmcs, cpu) = NULL;
1533         crash_disable_local_vmclear(cpu);
1534         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1535
1536         /*
1537          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1538          * is before setting loaded_vmcs->vcpu to -1 which is done in
1539          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1540          * then adds the vmcs into percpu list before it is deleted.
1541          */
1542         smp_wmb();
1543
1544         loaded_vmcs_init(loaded_vmcs);
1545         crash_enable_local_vmclear(cpu);
1546 }
1547
1548 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1549 {
1550         int cpu = loaded_vmcs->cpu;
1551
1552         if (cpu != -1)
1553                 smp_call_function_single(cpu,
1554                          __loaded_vmcs_clear, loaded_vmcs, 1);
1555 }
1556
1557 static inline void vpid_sync_vcpu_single(int vpid)
1558 {
1559         if (vpid == 0)
1560                 return;
1561
1562         if (cpu_has_vmx_invvpid_single())
1563                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1564 }
1565
1566 static inline void vpid_sync_vcpu_global(void)
1567 {
1568         if (cpu_has_vmx_invvpid_global())
1569                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1570 }
1571
1572 static inline void vpid_sync_context(int vpid)
1573 {
1574         if (cpu_has_vmx_invvpid_single())
1575                 vpid_sync_vcpu_single(vpid);
1576         else
1577                 vpid_sync_vcpu_global();
1578 }
1579
1580 static inline void ept_sync_global(void)
1581 {
1582         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1583 }
1584
1585 static inline void ept_sync_context(u64 eptp)
1586 {
1587         if (cpu_has_vmx_invept_context())
1588                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1589         else
1590                 ept_sync_global();
1591 }
1592
1593 static __always_inline void vmcs_check16(unsigned long field)
1594 {
1595         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1596                          "16-bit accessor invalid for 64-bit field");
1597         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1598                          "16-bit accessor invalid for 64-bit high field");
1599         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1600                          "16-bit accessor invalid for 32-bit high field");
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1602                          "16-bit accessor invalid for natural width field");
1603 }
1604
1605 static __always_inline void vmcs_check32(unsigned long field)
1606 {
1607         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1608                          "32-bit accessor invalid for 16-bit field");
1609         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610                          "32-bit accessor invalid for natural width field");
1611 }
1612
1613 static __always_inline void vmcs_check64(unsigned long field)
1614 {
1615         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616                          "64-bit accessor invalid for 16-bit field");
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1618                          "64-bit accessor invalid for 64-bit high field");
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1620                          "64-bit accessor invalid for 32-bit field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1622                          "64-bit accessor invalid for natural width field");
1623 }
1624
1625 static __always_inline void vmcs_checkl(unsigned long field)
1626 {
1627         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1628                          "Natural width accessor invalid for 16-bit field");
1629         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1630                          "Natural width accessor invalid for 64-bit field");
1631         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1632                          "Natural width accessor invalid for 64-bit high field");
1633         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1634                          "Natural width accessor invalid for 32-bit field");
1635 }
1636
1637 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1638 {
1639         unsigned long value;
1640
1641         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1642                       : "=a"(value) : "d"(field) : "cc");
1643         return value;
1644 }
1645
1646 static __always_inline u16 vmcs_read16(unsigned long field)
1647 {
1648         vmcs_check16(field);
1649         return __vmcs_readl(field);
1650 }
1651
1652 static __always_inline u32 vmcs_read32(unsigned long field)
1653 {
1654         vmcs_check32(field);
1655         return __vmcs_readl(field);
1656 }
1657
1658 static __always_inline u64 vmcs_read64(unsigned long field)
1659 {
1660         vmcs_check64(field);
1661 #ifdef CONFIG_X86_64
1662         return __vmcs_readl(field);
1663 #else
1664         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1665 #endif
1666 }
1667
1668 static __always_inline unsigned long vmcs_readl(unsigned long field)
1669 {
1670         vmcs_checkl(field);
1671         return __vmcs_readl(field);
1672 }
1673
1674 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1675 {
1676         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1677                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1678         dump_stack();
1679 }
1680
1681 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1682 {
1683         u8 error;
1684
1685         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1686                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1687         if (unlikely(error))
1688                 vmwrite_error(field, value);
1689 }
1690
1691 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1692 {
1693         vmcs_check16(field);
1694         __vmcs_writel(field, value);
1695 }
1696
1697 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1698 {
1699         vmcs_check32(field);
1700         __vmcs_writel(field, value);
1701 }
1702
1703 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1704 {
1705         vmcs_check64(field);
1706         __vmcs_writel(field, value);
1707 #ifndef CONFIG_X86_64
1708         asm volatile ("");
1709         __vmcs_writel(field+1, value >> 32);
1710 #endif
1711 }
1712
1713 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1714 {
1715         vmcs_checkl(field);
1716         __vmcs_writel(field, value);
1717 }
1718
1719 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1720 {
1721         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1722                          "vmcs_clear_bits does not support 64-bit fields");
1723         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1724 }
1725
1726 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1727 {
1728         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1729                          "vmcs_set_bits does not support 64-bit fields");
1730         __vmcs_writel(field, __vmcs_readl(field) | mask);
1731 }
1732
1733 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1734 {
1735         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1736 }
1737
1738 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1739 {
1740         vmcs_write32(VM_ENTRY_CONTROLS, val);
1741         vmx->vm_entry_controls_shadow = val;
1742 }
1743
1744 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1745 {
1746         if (vmx->vm_entry_controls_shadow != val)
1747                 vm_entry_controls_init(vmx, val);
1748 }
1749
1750 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1751 {
1752         return vmx->vm_entry_controls_shadow;
1753 }
1754
1755
1756 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1757 {
1758         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1759 }
1760
1761 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1762 {
1763         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1764 }
1765
1766 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1767 {
1768         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1769 }
1770
1771 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1772 {
1773         vmcs_write32(VM_EXIT_CONTROLS, val);
1774         vmx->vm_exit_controls_shadow = val;
1775 }
1776
1777 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1778 {
1779         if (vmx->vm_exit_controls_shadow != val)
1780                 vm_exit_controls_init(vmx, val);
1781 }
1782
1783 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1784 {
1785         return vmx->vm_exit_controls_shadow;
1786 }
1787
1788
1789 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1790 {
1791         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1792 }
1793
1794 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1795 {
1796         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1797 }
1798
1799 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1800 {
1801         vmx->segment_cache.bitmask = 0;
1802 }
1803
1804 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1805                                        unsigned field)
1806 {
1807         bool ret;
1808         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1809
1810         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1811                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1812                 vmx->segment_cache.bitmask = 0;
1813         }
1814         ret = vmx->segment_cache.bitmask & mask;
1815         vmx->segment_cache.bitmask |= mask;
1816         return ret;
1817 }
1818
1819 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1820 {
1821         u16 *p = &vmx->segment_cache.seg[seg].selector;
1822
1823         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1824                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1825         return *p;
1826 }
1827
1828 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1829 {
1830         ulong *p = &vmx->segment_cache.seg[seg].base;
1831
1832         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1833                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1834         return *p;
1835 }
1836
1837 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1838 {
1839         u32 *p = &vmx->segment_cache.seg[seg].limit;
1840
1841         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1842                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1843         return *p;
1844 }
1845
1846 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1847 {
1848         u32 *p = &vmx->segment_cache.seg[seg].ar;
1849
1850         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1851                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1852         return *p;
1853 }
1854
1855 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1856 {
1857         u32 eb;
1858
1859         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1860              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1861         if ((vcpu->guest_debug &
1862              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1863             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1864                 eb |= 1u << BP_VECTOR;
1865         if (to_vmx(vcpu)->rmode.vm86_active)
1866                 eb = ~0;
1867         if (enable_ept)
1868                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1869
1870         /* When we are running a nested L2 guest and L1 specified for it a
1871          * certain exception bitmap, we must trap the same exceptions and pass
1872          * them to L1. When running L2, we will only handle the exceptions
1873          * specified above if L1 did not want them.
1874          */
1875         if (is_guest_mode(vcpu))
1876                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1877
1878         vmcs_write32(EXCEPTION_BITMAP, eb);
1879 }
1880
1881 /*
1882  * Check if MSR is intercepted for currently loaded MSR bitmap.
1883  */
1884 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
1885 {
1886         unsigned long *msr_bitmap;
1887         int f = sizeof(unsigned long);
1888
1889         if (!cpu_has_vmx_msr_bitmap())
1890                 return true;
1891
1892         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
1893
1894         if (msr <= 0x1fff) {
1895                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1896         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1897                 msr &= 0x1fff;
1898                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1899         }
1900
1901         return true;
1902 }
1903
1904 /*
1905  * Check if MSR is intercepted for L01 MSR bitmap.
1906  */
1907 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
1908 {
1909         unsigned long *msr_bitmap;
1910         int f = sizeof(unsigned long);
1911
1912         if (!cpu_has_vmx_msr_bitmap())
1913                 return true;
1914
1915         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
1916
1917         if (msr <= 0x1fff) {
1918                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1919         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1920                 msr &= 0x1fff;
1921                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1922         }
1923
1924         return true;
1925 }
1926
1927 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1928                 unsigned long entry, unsigned long exit)
1929 {
1930         vm_entry_controls_clearbit(vmx, entry);
1931         vm_exit_controls_clearbit(vmx, exit);
1932 }
1933
1934 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1935 {
1936         unsigned i;
1937         struct msr_autoload *m = &vmx->msr_autoload;
1938
1939         switch (msr) {
1940         case MSR_EFER:
1941                 if (cpu_has_load_ia32_efer) {
1942                         clear_atomic_switch_msr_special(vmx,
1943                                         VM_ENTRY_LOAD_IA32_EFER,
1944                                         VM_EXIT_LOAD_IA32_EFER);
1945                         return;
1946                 }
1947                 break;
1948         case MSR_CORE_PERF_GLOBAL_CTRL:
1949                 if (cpu_has_load_perf_global_ctrl) {
1950                         clear_atomic_switch_msr_special(vmx,
1951                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1952                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1953                         return;
1954                 }
1955                 break;
1956         }
1957
1958         for (i = 0; i < m->nr; ++i)
1959                 if (m->guest[i].index == msr)
1960                         break;
1961
1962         if (i == m->nr)
1963                 return;
1964         --m->nr;
1965         m->guest[i] = m->guest[m->nr];
1966         m->host[i] = m->host[m->nr];
1967         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1968         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1969 }
1970
1971 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1972                 unsigned long entry, unsigned long exit,
1973                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1974                 u64 guest_val, u64 host_val)
1975 {
1976         vmcs_write64(guest_val_vmcs, guest_val);
1977         vmcs_write64(host_val_vmcs, host_val);
1978         vm_entry_controls_setbit(vmx, entry);
1979         vm_exit_controls_setbit(vmx, exit);
1980 }
1981
1982 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1983                                   u64 guest_val, u64 host_val)
1984 {
1985         unsigned i;
1986         struct msr_autoload *m = &vmx->msr_autoload;
1987
1988         switch (msr) {
1989         case MSR_EFER:
1990                 if (cpu_has_load_ia32_efer) {
1991                         add_atomic_switch_msr_special(vmx,
1992                                         VM_ENTRY_LOAD_IA32_EFER,
1993                                         VM_EXIT_LOAD_IA32_EFER,
1994                                         GUEST_IA32_EFER,
1995                                         HOST_IA32_EFER,
1996                                         guest_val, host_val);
1997                         return;
1998                 }
1999                 break;
2000         case MSR_CORE_PERF_GLOBAL_CTRL:
2001                 if (cpu_has_load_perf_global_ctrl) {
2002                         add_atomic_switch_msr_special(vmx,
2003                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2004                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2005                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2006                                         HOST_IA32_PERF_GLOBAL_CTRL,
2007                                         guest_val, host_val);
2008                         return;
2009                 }
2010                 break;
2011         case MSR_IA32_PEBS_ENABLE:
2012                 /* PEBS needs a quiescent period after being disabled (to write
2013                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2014                  * provide that period, so a CPU could write host's record into
2015                  * guest's memory.
2016                  */
2017                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2018         }
2019
2020         for (i = 0; i < m->nr; ++i)
2021                 if (m->guest[i].index == msr)
2022                         break;
2023
2024         if (i == NR_AUTOLOAD_MSRS) {
2025                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2026                                 "Can't add msr %x\n", msr);
2027                 return;
2028         } else if (i == m->nr) {
2029                 ++m->nr;
2030                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2031                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2032         }
2033
2034         m->guest[i].index = msr;
2035         m->guest[i].value = guest_val;
2036         m->host[i].index = msr;
2037         m->host[i].value = host_val;
2038 }
2039
2040 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2041 {
2042         u64 guest_efer = vmx->vcpu.arch.efer;
2043         u64 ignore_bits = 0;
2044
2045         if (!enable_ept) {
2046                 /*
2047                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2048                  * host CPUID is more efficient than testing guest CPUID
2049                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2050                  */
2051                 if (boot_cpu_has(X86_FEATURE_SMEP))
2052                         guest_efer |= EFER_NX;
2053                 else if (!(guest_efer & EFER_NX))
2054                         ignore_bits |= EFER_NX;
2055         }
2056
2057         /*
2058          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2059          */
2060         ignore_bits |= EFER_SCE;
2061 #ifdef CONFIG_X86_64
2062         ignore_bits |= EFER_LMA | EFER_LME;
2063         /* SCE is meaningful only in long mode on Intel */
2064         if (guest_efer & EFER_LMA)
2065                 ignore_bits &= ~(u64)EFER_SCE;
2066 #endif
2067
2068         clear_atomic_switch_msr(vmx, MSR_EFER);
2069
2070         /*
2071          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2072          * On CPUs that support "load IA32_EFER", always switch EFER
2073          * atomically, since it's faster than switching it manually.
2074          */
2075         if (cpu_has_load_ia32_efer ||
2076             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2077                 if (!(guest_efer & EFER_LMA))
2078                         guest_efer &= ~EFER_LME;
2079                 if (guest_efer != host_efer)
2080                         add_atomic_switch_msr(vmx, MSR_EFER,
2081                                               guest_efer, host_efer);
2082                 return false;
2083         } else {
2084                 guest_efer &= ~ignore_bits;
2085                 guest_efer |= host_efer & ignore_bits;
2086
2087                 vmx->guest_msrs[efer_offset].data = guest_efer;
2088                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2089
2090                 return true;
2091         }
2092 }
2093
2094 #ifdef CONFIG_X86_32
2095 /*
2096  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2097  * VMCS rather than the segment table.  KVM uses this helper to figure
2098  * out the current bases to poke them into the VMCS before entry.
2099  */
2100 static unsigned long segment_base(u16 selector)
2101 {
2102         struct desc_struct *table;
2103         unsigned long v;
2104
2105         if (!(selector & ~SEGMENT_RPL_MASK))
2106                 return 0;
2107
2108         table = get_current_gdt_ro();
2109
2110         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2111                 u16 ldt_selector = kvm_read_ldt();
2112
2113                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2114                         return 0;
2115
2116                 table = (struct desc_struct *)segment_base(ldt_selector);
2117         }
2118         v = get_desc_base(&table[selector >> 3]);
2119         return v;
2120 }
2121 #endif
2122
2123 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2124 {
2125         struct vcpu_vmx *vmx = to_vmx(vcpu);
2126         int i;
2127
2128         if (vmx->host_state.loaded)
2129                 return;
2130
2131         vmx->host_state.loaded = 1;
2132         /*
2133          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2134          * allow segment selectors with cpl > 0 or ti == 1.
2135          */
2136         vmx->host_state.ldt_sel = kvm_read_ldt();
2137         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2138         savesegment(fs, vmx->host_state.fs_sel);
2139         if (!(vmx->host_state.fs_sel & 7)) {
2140                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2141                 vmx->host_state.fs_reload_needed = 0;
2142         } else {
2143                 vmcs_write16(HOST_FS_SELECTOR, 0);
2144                 vmx->host_state.fs_reload_needed = 1;
2145         }
2146         savesegment(gs, vmx->host_state.gs_sel);
2147         if (!(vmx->host_state.gs_sel & 7))
2148                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2149         else {
2150                 vmcs_write16(HOST_GS_SELECTOR, 0);
2151                 vmx->host_state.gs_ldt_reload_needed = 1;
2152         }
2153
2154 #ifdef CONFIG_X86_64
2155         savesegment(ds, vmx->host_state.ds_sel);
2156         savesegment(es, vmx->host_state.es_sel);
2157 #endif
2158
2159 #ifdef CONFIG_X86_64
2160         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2161         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2162 #else
2163         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2164         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2165 #endif
2166
2167 #ifdef CONFIG_X86_64
2168         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2169         if (is_long_mode(&vmx->vcpu))
2170                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2171 #endif
2172         if (boot_cpu_has(X86_FEATURE_MPX))
2173                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2174         for (i = 0; i < vmx->save_nmsrs; ++i)
2175                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2176                                    vmx->guest_msrs[i].data,
2177                                    vmx->guest_msrs[i].mask);
2178 }
2179
2180 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2181 {
2182         if (!vmx->host_state.loaded)
2183                 return;
2184
2185         ++vmx->vcpu.stat.host_state_reload;
2186         vmx->host_state.loaded = 0;
2187 #ifdef CONFIG_X86_64
2188         if (is_long_mode(&vmx->vcpu))
2189                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2190 #endif
2191         if (vmx->host_state.gs_ldt_reload_needed) {
2192                 kvm_load_ldt(vmx->host_state.ldt_sel);
2193 #ifdef CONFIG_X86_64
2194                 load_gs_index(vmx->host_state.gs_sel);
2195 #else
2196                 loadsegment(gs, vmx->host_state.gs_sel);
2197 #endif
2198         }
2199         if (vmx->host_state.fs_reload_needed)
2200                 loadsegment(fs, vmx->host_state.fs_sel);
2201 #ifdef CONFIG_X86_64
2202         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2203                 loadsegment(ds, vmx->host_state.ds_sel);
2204                 loadsegment(es, vmx->host_state.es_sel);
2205         }
2206 #endif
2207         invalidate_tss_limit();
2208 #ifdef CONFIG_X86_64
2209         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2210 #endif
2211         if (vmx->host_state.msr_host_bndcfgs)
2212                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2213         load_fixmap_gdt(raw_smp_processor_id());
2214 }
2215
2216 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2217 {
2218         preempt_disable();
2219         __vmx_load_host_state(vmx);
2220         preempt_enable();
2221 }
2222
2223 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2224 {
2225         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2226         struct pi_desc old, new;
2227         unsigned int dest;
2228
2229         /*
2230          * In case of hot-plug or hot-unplug, we may have to undo
2231          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2232          * always keep PI.NDST up to date for simplicity: it makes the
2233          * code easier, and CPU migration is not a fast path.
2234          */
2235         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2236                 return;
2237
2238         /*
2239          * First handle the simple case where no cmpxchg is necessary; just
2240          * allow posting non-urgent interrupts.
2241          *
2242          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2243          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2244          * expects the VCPU to be on the blocked_vcpu_list that matches
2245          * PI.NDST.
2246          */
2247         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2248             vcpu->cpu == cpu) {
2249                 pi_clear_sn(pi_desc);
2250                 return;
2251         }
2252
2253         /* The full case.  */
2254         do {
2255                 old.control = new.control = pi_desc->control;
2256
2257                 dest = cpu_physical_id(cpu);
2258
2259                 if (x2apic_enabled())
2260                         new.ndst = dest;
2261                 else
2262                         new.ndst = (dest << 8) & 0xFF00;
2263
2264                 new.sn = 0;
2265         } while (cmpxchg64(&pi_desc->control, old.control,
2266                            new.control) != old.control);
2267 }
2268
2269 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2270 {
2271         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2272         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2273 }
2274
2275 /*
2276  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2277  * vcpu mutex is already taken.
2278  */
2279 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2280 {
2281         struct vcpu_vmx *vmx = to_vmx(vcpu);
2282         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2283
2284         if (!already_loaded) {
2285                 loaded_vmcs_clear(vmx->loaded_vmcs);
2286                 local_irq_disable();
2287                 crash_disable_local_vmclear(cpu);
2288
2289                 /*
2290                  * Read loaded_vmcs->cpu should be before fetching
2291                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2292                  * See the comments in __loaded_vmcs_clear().
2293                  */
2294                 smp_rmb();
2295
2296                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2297                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2298                 crash_enable_local_vmclear(cpu);
2299                 local_irq_enable();
2300         }
2301
2302         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2303                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2304                 vmcs_load(vmx->loaded_vmcs->vmcs);
2305                 indirect_branch_prediction_barrier();
2306         }
2307
2308         if (!already_loaded) {
2309                 void *gdt = get_current_gdt_ro();
2310                 unsigned long sysenter_esp;
2311
2312                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2313
2314                 /*
2315                  * Linux uses per-cpu TSS and GDT, so set these when switching
2316                  * processors.  See 22.2.4.
2317                  */
2318                 vmcs_writel(HOST_TR_BASE,
2319                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2320                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2321
2322                 /*
2323                  * VM exits change the host TR limit to 0x67 after a VM
2324                  * exit.  This is okay, since 0x67 covers everything except
2325                  * the IO bitmap and have have code to handle the IO bitmap
2326                  * being lost after a VM exit.
2327                  */
2328                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2329
2330                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2331                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2332
2333                 vmx->loaded_vmcs->cpu = cpu;
2334         }
2335
2336         /* Setup TSC multiplier */
2337         if (kvm_has_tsc_control &&
2338             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2339                 decache_tsc_multiplier(vmx);
2340
2341         vmx_vcpu_pi_load(vcpu, cpu);
2342         vmx->host_pkru = read_pkru();
2343         vmx->host_debugctlmsr = get_debugctlmsr();
2344 }
2345
2346 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2347 {
2348         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2349
2350         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2351                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2352                 !kvm_vcpu_apicv_active(vcpu))
2353                 return;
2354
2355         /* Set SN when the vCPU is preempted */
2356         if (vcpu->preempted)
2357                 pi_set_sn(pi_desc);
2358 }
2359
2360 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2361 {
2362         vmx_vcpu_pi_put(vcpu);
2363
2364         __vmx_load_host_state(to_vmx(vcpu));
2365 }
2366
2367 static bool emulation_required(struct kvm_vcpu *vcpu)
2368 {
2369         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2370 }
2371
2372 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2373
2374 /*
2375  * Return the cr0 value that a nested guest would read. This is a combination
2376  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2377  * its hypervisor (cr0_read_shadow).
2378  */
2379 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2380 {
2381         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2382                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2383 }
2384 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2385 {
2386         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2387                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2388 }
2389
2390 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2391 {
2392         unsigned long rflags, save_rflags;
2393
2394         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2395                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2396                 rflags = vmcs_readl(GUEST_RFLAGS);
2397                 if (to_vmx(vcpu)->rmode.vm86_active) {
2398                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2399                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2400                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2401                 }
2402                 to_vmx(vcpu)->rflags = rflags;
2403         }
2404         return to_vmx(vcpu)->rflags;
2405 }
2406
2407 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2408 {
2409         unsigned long old_rflags = vmx_get_rflags(vcpu);
2410
2411         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2412         to_vmx(vcpu)->rflags = rflags;
2413         if (to_vmx(vcpu)->rmode.vm86_active) {
2414                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2415                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2416         }
2417         vmcs_writel(GUEST_RFLAGS, rflags);
2418
2419         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2420                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2421 }
2422
2423 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2424 {
2425         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2426         int ret = 0;
2427
2428         if (interruptibility & GUEST_INTR_STATE_STI)
2429                 ret |= KVM_X86_SHADOW_INT_STI;
2430         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2431                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2432
2433         return ret;
2434 }
2435
2436 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2437 {
2438         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2439         u32 interruptibility = interruptibility_old;
2440
2441         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2442
2443         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2444                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2445         else if (mask & KVM_X86_SHADOW_INT_STI)
2446                 interruptibility |= GUEST_INTR_STATE_STI;
2447
2448         if ((interruptibility != interruptibility_old))
2449                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2450 }
2451
2452 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2453 {
2454         unsigned long rip;
2455
2456         rip = kvm_rip_read(vcpu);
2457         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2458         kvm_rip_write(vcpu, rip);
2459
2460         /* skipping an emulated instruction also counts */
2461         vmx_set_interrupt_shadow(vcpu, 0);
2462 }
2463
2464 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2465                                                unsigned long exit_qual)
2466 {
2467         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2468         unsigned int nr = vcpu->arch.exception.nr;
2469         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2470
2471         if (vcpu->arch.exception.has_error_code) {
2472                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2473                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2474         }
2475
2476         if (kvm_exception_is_soft(nr))
2477                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2478         else
2479                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2480
2481         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2482             vmx_get_nmi_mask(vcpu))
2483                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2484
2485         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2486 }
2487
2488 /*
2489  * KVM wants to inject page-faults which it got to the guest. This function
2490  * checks whether in a nested guest, we need to inject them to L1 or L2.
2491  */
2492 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2493 {
2494         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2495         unsigned int nr = vcpu->arch.exception.nr;
2496
2497         if (nr == PF_VECTOR) {
2498                 if (vcpu->arch.exception.nested_apf) {
2499                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2500                         return 1;
2501                 }
2502                 /*
2503                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2504                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2505                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2506                  * can be written only when inject_pending_event runs.  This should be
2507                  * conditional on a new capability---if the capability is disabled,
2508                  * kvm_multiple_exception would write the ancillary information to
2509                  * CR2 or DR6, for backwards ABI-compatibility.
2510                  */
2511                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2512                                                     vcpu->arch.exception.error_code)) {
2513                         *exit_qual = vcpu->arch.cr2;
2514                         return 1;
2515                 }
2516         } else {
2517                 if (vmcs12->exception_bitmap & (1u << nr)) {
2518                         if (nr == DB_VECTOR)
2519                                 *exit_qual = vcpu->arch.dr6;
2520                         else
2521                                 *exit_qual = 0;
2522                         return 1;
2523                 }
2524         }
2525
2526         return 0;
2527 }
2528
2529 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2530 {
2531         struct vcpu_vmx *vmx = to_vmx(vcpu);
2532         unsigned nr = vcpu->arch.exception.nr;
2533         bool has_error_code = vcpu->arch.exception.has_error_code;
2534         u32 error_code = vcpu->arch.exception.error_code;
2535         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2536
2537         if (has_error_code) {
2538                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2539                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2540         }
2541
2542         if (vmx->rmode.vm86_active) {
2543                 int inc_eip = 0;
2544                 if (kvm_exception_is_soft(nr))
2545                         inc_eip = vcpu->arch.event_exit_inst_len;
2546                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2547                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2548                 return;
2549         }
2550
2551         if (kvm_exception_is_soft(nr)) {
2552                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2553                              vmx->vcpu.arch.event_exit_inst_len);
2554                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2555         } else
2556                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2557
2558         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2559 }
2560
2561 static bool vmx_rdtscp_supported(void)
2562 {
2563         return cpu_has_vmx_rdtscp();
2564 }
2565
2566 static bool vmx_invpcid_supported(void)
2567 {
2568         return cpu_has_vmx_invpcid() && enable_ept;
2569 }
2570
2571 /*
2572  * Swap MSR entry in host/guest MSR entry array.
2573  */
2574 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2575 {
2576         struct shared_msr_entry tmp;
2577
2578         tmp = vmx->guest_msrs[to];
2579         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2580         vmx->guest_msrs[from] = tmp;
2581 }
2582
2583 /*
2584  * Set up the vmcs to automatically save and restore system
2585  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2586  * mode, as fiddling with msrs is very expensive.
2587  */
2588 static void setup_msrs(struct vcpu_vmx *vmx)
2589 {
2590         int save_nmsrs, index;
2591
2592         save_nmsrs = 0;
2593 #ifdef CONFIG_X86_64
2594         if (is_long_mode(&vmx->vcpu)) {
2595                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2596                 if (index >= 0)
2597                         move_msr_up(vmx, index, save_nmsrs++);
2598                 index = __find_msr_index(vmx, MSR_LSTAR);
2599                 if (index >= 0)
2600                         move_msr_up(vmx, index, save_nmsrs++);
2601                 index = __find_msr_index(vmx, MSR_CSTAR);
2602                 if (index >= 0)
2603                         move_msr_up(vmx, index, save_nmsrs++);
2604                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2605                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2606                         move_msr_up(vmx, index, save_nmsrs++);
2607                 /*
2608                  * MSR_STAR is only needed on long mode guests, and only
2609                  * if efer.sce is enabled.
2610                  */
2611                 index = __find_msr_index(vmx, MSR_STAR);
2612                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2613                         move_msr_up(vmx, index, save_nmsrs++);
2614         }
2615 #endif
2616         index = __find_msr_index(vmx, MSR_EFER);
2617         if (index >= 0 && update_transition_efer(vmx, index))
2618                 move_msr_up(vmx, index, save_nmsrs++);
2619
2620         vmx->save_nmsrs = save_nmsrs;
2621
2622         if (cpu_has_vmx_msr_bitmap())
2623                 vmx_update_msr_bitmap(&vmx->vcpu);
2624 }
2625
2626 /*
2627  * reads and returns guest's timestamp counter "register"
2628  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2629  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2630  */
2631 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2632 {
2633         u64 host_tsc, tsc_offset;
2634
2635         host_tsc = rdtsc();
2636         tsc_offset = vmcs_read64(TSC_OFFSET);
2637         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2638 }
2639
2640 /*
2641  * writes 'offset' into guest's timestamp counter offset register
2642  */
2643 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2644 {
2645         if (is_guest_mode(vcpu)) {
2646                 /*
2647                  * We're here if L1 chose not to trap WRMSR to TSC. According
2648                  * to the spec, this should set L1's TSC; The offset that L1
2649                  * set for L2 remains unchanged, and still needs to be added
2650                  * to the newly set TSC to get L2's TSC.
2651                  */
2652                 struct vmcs12 *vmcs12;
2653                 /* recalculate vmcs02.TSC_OFFSET: */
2654                 vmcs12 = get_vmcs12(vcpu);
2655                 vmcs_write64(TSC_OFFSET, offset +
2656                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2657                          vmcs12->tsc_offset : 0));
2658         } else {
2659                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2660                                            vmcs_read64(TSC_OFFSET), offset);
2661                 vmcs_write64(TSC_OFFSET, offset);
2662         }
2663 }
2664
2665 /*
2666  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2667  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2668  * all guests if the "nested" module option is off, and can also be disabled
2669  * for a single guest by disabling its VMX cpuid bit.
2670  */
2671 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2672 {
2673         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2674 }
2675
2676 /*
2677  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2678  * returned for the various VMX controls MSRs when nested VMX is enabled.
2679  * The same values should also be used to verify that vmcs12 control fields are
2680  * valid during nested entry from L1 to L2.
2681  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2682  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2683  * bit in the high half is on if the corresponding bit in the control field
2684  * may be on. See also vmx_control_verify().
2685  */
2686 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2687 {
2688         /*
2689          * Note that as a general rule, the high half of the MSRs (bits in
2690          * the control fields which may be 1) should be initialized by the
2691          * intersection of the underlying hardware's MSR (i.e., features which
2692          * can be supported) and the list of features we want to expose -
2693          * because they are known to be properly supported in our code.
2694          * Also, usually, the low half of the MSRs (bits which must be 1) can
2695          * be set to 0, meaning that L1 may turn off any of these bits. The
2696          * reason is that if one of these bits is necessary, it will appear
2697          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2698          * fields of vmcs01 and vmcs02, will turn these bits off - and
2699          * nested_vmx_exit_reflected() will not pass related exits to L1.
2700          * These rules have exceptions below.
2701          */
2702
2703         /* pin-based controls */
2704         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2705                 vmx->nested.nested_vmx_pinbased_ctls_low,
2706                 vmx->nested.nested_vmx_pinbased_ctls_high);
2707         vmx->nested.nested_vmx_pinbased_ctls_low |=
2708                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2709         vmx->nested.nested_vmx_pinbased_ctls_high &=
2710                 PIN_BASED_EXT_INTR_MASK |
2711                 PIN_BASED_NMI_EXITING |
2712                 PIN_BASED_VIRTUAL_NMIS;
2713         vmx->nested.nested_vmx_pinbased_ctls_high |=
2714                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2715                 PIN_BASED_VMX_PREEMPTION_TIMER;
2716         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2717                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2718                         PIN_BASED_POSTED_INTR;
2719
2720         /* exit controls */
2721         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2722                 vmx->nested.nested_vmx_exit_ctls_low,
2723                 vmx->nested.nested_vmx_exit_ctls_high);
2724         vmx->nested.nested_vmx_exit_ctls_low =
2725                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2726
2727         vmx->nested.nested_vmx_exit_ctls_high &=
2728 #ifdef CONFIG_X86_64
2729                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2730 #endif
2731                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2732         vmx->nested.nested_vmx_exit_ctls_high |=
2733                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2734                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2735                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2736
2737         if (kvm_mpx_supported())
2738                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2739
2740         /* We support free control of debug control saving. */
2741         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2742
2743         /* entry controls */
2744         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2745                 vmx->nested.nested_vmx_entry_ctls_low,
2746                 vmx->nested.nested_vmx_entry_ctls_high);
2747         vmx->nested.nested_vmx_entry_ctls_low =
2748                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2749         vmx->nested.nested_vmx_entry_ctls_high &=
2750 #ifdef CONFIG_X86_64
2751                 VM_ENTRY_IA32E_MODE |
2752 #endif
2753                 VM_ENTRY_LOAD_IA32_PAT;
2754         vmx->nested.nested_vmx_entry_ctls_high |=
2755                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2756         if (kvm_mpx_supported())
2757                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2758
2759         /* We support free control of debug control loading. */
2760         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2761
2762         /* cpu-based controls */
2763         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2764                 vmx->nested.nested_vmx_procbased_ctls_low,
2765                 vmx->nested.nested_vmx_procbased_ctls_high);
2766         vmx->nested.nested_vmx_procbased_ctls_low =
2767                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2768         vmx->nested.nested_vmx_procbased_ctls_high &=
2769                 CPU_BASED_VIRTUAL_INTR_PENDING |
2770                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2771                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2772                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2773                 CPU_BASED_CR3_STORE_EXITING |
2774 #ifdef CONFIG_X86_64
2775                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2776 #endif
2777                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2778                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2779                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2780                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2781                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2782         /*
2783          * We can allow some features even when not supported by the
2784          * hardware. For example, L1 can specify an MSR bitmap - and we
2785          * can use it to avoid exits to L1 - even when L0 runs L2
2786          * without MSR bitmaps.
2787          */
2788         vmx->nested.nested_vmx_procbased_ctls_high |=
2789                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2790                 CPU_BASED_USE_MSR_BITMAPS;
2791
2792         /* We support free control of CR3 access interception. */
2793         vmx->nested.nested_vmx_procbased_ctls_low &=
2794                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2795
2796         /*
2797          * secondary cpu-based controls.  Do not include those that
2798          * depend on CPUID bits, they are added later by vmx_cpuid_update.
2799          */
2800         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2801                 vmx->nested.nested_vmx_secondary_ctls_low,
2802                 vmx->nested.nested_vmx_secondary_ctls_high);
2803         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2804         vmx->nested.nested_vmx_secondary_ctls_high &=
2805                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2806                 SECONDARY_EXEC_DESC |
2807                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2808                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2809                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2810                 SECONDARY_EXEC_WBINVD_EXITING;
2811
2812         if (enable_ept) {
2813                 /* nested EPT: emulate EPT also to L1 */
2814                 vmx->nested.nested_vmx_secondary_ctls_high |=
2815                         SECONDARY_EXEC_ENABLE_EPT;
2816                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2817                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2818                 if (cpu_has_vmx_ept_execute_only())
2819                         vmx->nested.nested_vmx_ept_caps |=
2820                                 VMX_EPT_EXECUTE_ONLY_BIT;
2821                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2822                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2823                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2824                         VMX_EPT_1GB_PAGE_BIT;
2825                 if (enable_ept_ad_bits) {
2826                         vmx->nested.nested_vmx_secondary_ctls_high |=
2827                                 SECONDARY_EXEC_ENABLE_PML;
2828                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2829                 }
2830         }
2831
2832         if (cpu_has_vmx_vmfunc()) {
2833                 vmx->nested.nested_vmx_secondary_ctls_high |=
2834                         SECONDARY_EXEC_ENABLE_VMFUNC;
2835                 /*
2836                  * Advertise EPTP switching unconditionally
2837                  * since we emulate it
2838                  */
2839                 if (enable_ept)
2840                         vmx->nested.nested_vmx_vmfunc_controls =
2841                                 VMX_VMFUNC_EPTP_SWITCHING;
2842         }
2843
2844         /*
2845          * Old versions of KVM use the single-context version without
2846          * checking for support, so declare that it is supported even
2847          * though it is treated as global context.  The alternative is
2848          * not failing the single-context invvpid, and it is worse.
2849          */
2850         if (enable_vpid) {
2851                 vmx->nested.nested_vmx_secondary_ctls_high |=
2852                         SECONDARY_EXEC_ENABLE_VPID;
2853                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2854                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2855         }
2856
2857         if (enable_unrestricted_guest)
2858                 vmx->nested.nested_vmx_secondary_ctls_high |=
2859                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2860
2861         /* miscellaneous data */
2862         rdmsr(MSR_IA32_VMX_MISC,
2863                 vmx->nested.nested_vmx_misc_low,
2864                 vmx->nested.nested_vmx_misc_high);
2865         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2866         vmx->nested.nested_vmx_misc_low |=
2867                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2868                 VMX_MISC_ACTIVITY_HLT;
2869         vmx->nested.nested_vmx_misc_high = 0;
2870
2871         /*
2872          * This MSR reports some information about VMX support. We
2873          * should return information about the VMX we emulate for the
2874          * guest, and the VMCS structure we give it - not about the
2875          * VMX support of the underlying hardware.
2876          */
2877         vmx->nested.nested_vmx_basic =
2878                 VMCS12_REVISION |
2879                 VMX_BASIC_TRUE_CTLS |
2880                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2881                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2882
2883         if (cpu_has_vmx_basic_inout())
2884                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2885
2886         /*
2887          * These MSRs specify bits which the guest must keep fixed on
2888          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2889          * We picked the standard core2 setting.
2890          */
2891 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2892 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2893         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2894         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2895
2896         /* These MSRs specify bits which the guest must keep fixed off. */
2897         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2898         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2899
2900         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2901         vmx->nested.nested_vmx_vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
2902 }
2903
2904 /*
2905  * if fixed0[i] == 1: val[i] must be 1
2906  * if fixed1[i] == 0: val[i] must be 0
2907  */
2908 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2909 {
2910         return ((val & fixed1) | fixed0) == val;
2911 }
2912
2913 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2914 {
2915         return fixed_bits_valid(control, low, high);
2916 }
2917
2918 static inline u64 vmx_control_msr(u32 low, u32 high)
2919 {
2920         return low | ((u64)high << 32);
2921 }
2922
2923 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2924 {
2925         superset &= mask;
2926         subset &= mask;
2927
2928         return (superset | subset) == superset;
2929 }
2930
2931 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2932 {
2933         const u64 feature_and_reserved =
2934                 /* feature (except bit 48; see below) */
2935                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2936                 /* reserved */
2937                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2938         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2939
2940         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2941                 return -EINVAL;
2942
2943         /*
2944          * KVM does not emulate a version of VMX that constrains physical
2945          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2946          */
2947         if (data & BIT_ULL(48))
2948                 return -EINVAL;
2949
2950         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2951             vmx_basic_vmcs_revision_id(data))
2952                 return -EINVAL;
2953
2954         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2955                 return -EINVAL;
2956
2957         vmx->nested.nested_vmx_basic = data;
2958         return 0;
2959 }
2960
2961 static int
2962 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2963 {
2964         u64 supported;
2965         u32 *lowp, *highp;
2966
2967         switch (msr_index) {
2968         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2969                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2970                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2971                 break;
2972         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2973                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2974                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2975                 break;
2976         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2977                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2978                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2979                 break;
2980         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2981                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2982                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2983                 break;
2984         case MSR_IA32_VMX_PROCBASED_CTLS2:
2985                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2986                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2987                 break;
2988         default:
2989                 BUG();
2990         }
2991
2992         supported = vmx_control_msr(*lowp, *highp);
2993
2994         /* Check must-be-1 bits are still 1. */
2995         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2996                 return -EINVAL;
2997
2998         /* Check must-be-0 bits are still 0. */
2999         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3000                 return -EINVAL;
3001
3002         *lowp = data;
3003         *highp = data >> 32;
3004         return 0;
3005 }
3006
3007 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3008 {
3009         const u64 feature_and_reserved_bits =
3010                 /* feature */
3011                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3012                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3013                 /* reserved */
3014                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3015         u64 vmx_misc;
3016
3017         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3018                                    vmx->nested.nested_vmx_misc_high);
3019
3020         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3021                 return -EINVAL;
3022
3023         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3024              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3025             vmx_misc_preemption_timer_rate(data) !=
3026             vmx_misc_preemption_timer_rate(vmx_misc))
3027                 return -EINVAL;
3028
3029         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3030                 return -EINVAL;
3031
3032         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3033                 return -EINVAL;
3034
3035         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3036                 return -EINVAL;
3037
3038         vmx->nested.nested_vmx_misc_low = data;
3039         vmx->nested.nested_vmx_misc_high = data >> 32;
3040         return 0;
3041 }
3042
3043 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3044 {
3045         u64 vmx_ept_vpid_cap;
3046
3047         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3048                                            vmx->nested.nested_vmx_vpid_caps);
3049
3050         /* Every bit is either reserved or a feature bit. */
3051         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3052                 return -EINVAL;
3053
3054         vmx->nested.nested_vmx_ept_caps = data;
3055         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3056         return 0;
3057 }
3058
3059 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3060 {
3061         u64 *msr;
3062
3063         switch (msr_index) {
3064         case MSR_IA32_VMX_CR0_FIXED0:
3065                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3066                 break;
3067         case MSR_IA32_VMX_CR4_FIXED0:
3068                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3069                 break;
3070         default:
3071                 BUG();
3072         }
3073
3074         /*
3075          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3076          * must be 1 in the restored value.
3077          */
3078         if (!is_bitwise_subset(data, *msr, -1ULL))
3079                 return -EINVAL;
3080
3081         *msr = data;
3082         return 0;
3083 }
3084
3085 /*
3086  * Called when userspace is restoring VMX MSRs.
3087  *
3088  * Returns 0 on success, non-0 otherwise.
3089  */
3090 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3091 {
3092         struct vcpu_vmx *vmx = to_vmx(vcpu);
3093
3094         switch (msr_index) {
3095         case MSR_IA32_VMX_BASIC:
3096                 return vmx_restore_vmx_basic(vmx, data);
3097         case MSR_IA32_VMX_PINBASED_CTLS:
3098         case MSR_IA32_VMX_PROCBASED_CTLS:
3099         case MSR_IA32_VMX_EXIT_CTLS:
3100         case MSR_IA32_VMX_ENTRY_CTLS:
3101                 /*
3102                  * The "non-true" VMX capability MSRs are generated from the
3103                  * "true" MSRs, so we do not support restoring them directly.
3104                  *
3105                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3106                  * should restore the "true" MSRs with the must-be-1 bits
3107                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3108                  * DEFAULT SETTINGS".
3109                  */
3110                 return -EINVAL;
3111         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3112         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3113         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3114         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3115         case MSR_IA32_VMX_PROCBASED_CTLS2:
3116                 return vmx_restore_control_msr(vmx, msr_index, data);
3117         case MSR_IA32_VMX_MISC:
3118                 return vmx_restore_vmx_misc(vmx, data);
3119         case MSR_IA32_VMX_CR0_FIXED0:
3120         case MSR_IA32_VMX_CR4_FIXED0:
3121                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3122         case MSR_IA32_VMX_CR0_FIXED1:
3123         case MSR_IA32_VMX_CR4_FIXED1:
3124                 /*
3125                  * These MSRs are generated based on the vCPU's CPUID, so we
3126                  * do not support restoring them directly.
3127                  */
3128                 return -EINVAL;
3129         case MSR_IA32_VMX_EPT_VPID_CAP:
3130                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3131         case MSR_IA32_VMX_VMCS_ENUM:
3132                 vmx->nested.nested_vmx_vmcs_enum = data;
3133                 return 0;
3134         default:
3135                 /*
3136                  * The rest of the VMX capability MSRs do not support restore.
3137                  */
3138                 return -EINVAL;
3139         }
3140 }
3141
3142 /* Returns 0 on success, non-0 otherwise. */
3143 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3144 {
3145         struct vcpu_vmx *vmx = to_vmx(vcpu);
3146
3147         switch (msr_index) {
3148         case MSR_IA32_VMX_BASIC:
3149                 *pdata = vmx->nested.nested_vmx_basic;
3150                 break;
3151         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3152         case MSR_IA32_VMX_PINBASED_CTLS:
3153                 *pdata = vmx_control_msr(
3154                         vmx->nested.nested_vmx_pinbased_ctls_low,
3155                         vmx->nested.nested_vmx_pinbased_ctls_high);
3156                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3157                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3158                 break;
3159         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3160         case MSR_IA32_VMX_PROCBASED_CTLS:
3161                 *pdata = vmx_control_msr(
3162                         vmx->nested.nested_vmx_procbased_ctls_low,
3163                         vmx->nested.nested_vmx_procbased_ctls_high);
3164                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3165                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3166                 break;
3167         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3168         case MSR_IA32_VMX_EXIT_CTLS:
3169                 *pdata = vmx_control_msr(
3170                         vmx->nested.nested_vmx_exit_ctls_low,
3171                         vmx->nested.nested_vmx_exit_ctls_high);
3172                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3173                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3174                 break;
3175         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3176         case MSR_IA32_VMX_ENTRY_CTLS:
3177                 *pdata = vmx_control_msr(
3178                         vmx->nested.nested_vmx_entry_ctls_low,
3179                         vmx->nested.nested_vmx_entry_ctls_high);
3180                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3181                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3182                 break;
3183         case MSR_IA32_VMX_MISC:
3184                 *pdata = vmx_control_msr(
3185                         vmx->nested.nested_vmx_misc_low,
3186                         vmx->nested.nested_vmx_misc_high);
3187                 break;
3188         case MSR_IA32_VMX_CR0_FIXED0:
3189                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3190                 break;
3191         case MSR_IA32_VMX_CR0_FIXED1:
3192                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3193                 break;
3194         case MSR_IA32_VMX_CR4_FIXED0:
3195                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3196                 break;
3197         case MSR_IA32_VMX_CR4_FIXED1:
3198                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3199                 break;
3200         case MSR_IA32_VMX_VMCS_ENUM:
3201                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3202                 break;
3203         case MSR_IA32_VMX_PROCBASED_CTLS2:
3204                 *pdata = vmx_control_msr(
3205                         vmx->nested.nested_vmx_secondary_ctls_low,
3206                         vmx->nested.nested_vmx_secondary_ctls_high);
3207                 break;
3208         case MSR_IA32_VMX_EPT_VPID_CAP:
3209                 *pdata = vmx->nested.nested_vmx_ept_caps |
3210                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3211                 break;
3212         case MSR_IA32_VMX_VMFUNC:
3213                 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3214                 break;
3215         default:
3216                 return 1;
3217         }
3218
3219         return 0;
3220 }
3221
3222 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3223                                                  uint64_t val)
3224 {
3225         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3226
3227         return !(val & ~valid_bits);
3228 }
3229
3230 /*
3231  * Reads an msr value (of 'msr_index') into 'pdata'.
3232  * Returns 0 on success, non-0 otherwise.
3233  * Assumes vcpu_load() was already called.
3234  */
3235 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3236 {
3237         struct vcpu_vmx *vmx = to_vmx(vcpu);
3238         struct shared_msr_entry *msr;
3239
3240         switch (msr_info->index) {
3241 #ifdef CONFIG_X86_64
3242         case MSR_FS_BASE:
3243                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3244                 break;
3245         case MSR_GS_BASE:
3246                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3247                 break;
3248         case MSR_KERNEL_GS_BASE:
3249                 vmx_load_host_state(vmx);
3250                 msr_info->data = vmx->msr_guest_kernel_gs_base;
3251                 break;
3252 #endif
3253         case MSR_EFER:
3254                 return kvm_get_msr_common(vcpu, msr_info);
3255         case MSR_IA32_TSC:
3256                 msr_info->data = guest_read_tsc(vcpu);
3257                 break;
3258         case MSR_IA32_SPEC_CTRL:
3259                 if (!msr_info->host_initiated &&
3260                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3261                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3262                         return 1;
3263
3264                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3265                 break;
3266         case MSR_IA32_ARCH_CAPABILITIES:
3267                 if (!msr_info->host_initiated &&
3268                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3269                         return 1;
3270                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3271                 break;
3272         case MSR_IA32_SYSENTER_CS:
3273                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3274                 break;
3275         case MSR_IA32_SYSENTER_EIP:
3276                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3277                 break;
3278         case MSR_IA32_SYSENTER_ESP:
3279                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3280                 break;
3281         case MSR_IA32_BNDCFGS:
3282                 if (!kvm_mpx_supported() ||
3283                     (!msr_info->host_initiated &&
3284                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3285                         return 1;
3286                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3287                 break;
3288         case MSR_IA32_MCG_EXT_CTL:
3289                 if (!msr_info->host_initiated &&
3290                     !(vmx->msr_ia32_feature_control &
3291                       FEATURE_CONTROL_LMCE))
3292                         return 1;
3293                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3294                 break;
3295         case MSR_IA32_FEATURE_CONTROL:
3296                 msr_info->data = vmx->msr_ia32_feature_control;
3297                 break;
3298         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3299                 if (!nested_vmx_allowed(vcpu))
3300                         return 1;
3301                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3302         case MSR_IA32_XSS:
3303                 if (!vmx_xsaves_supported())
3304                         return 1;
3305                 msr_info->data = vcpu->arch.ia32_xss;
3306                 break;
3307         case MSR_TSC_AUX:
3308                 if (!msr_info->host_initiated &&
3309                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3310                         return 1;
3311                 /* Otherwise falls through */
3312         default:
3313                 msr = find_msr_entry(vmx, msr_info->index);
3314                 if (msr) {
3315                         msr_info->data = msr->data;
3316                         break;
3317                 }
3318                 return kvm_get_msr_common(vcpu, msr_info);
3319         }
3320
3321         return 0;
3322 }
3323
3324 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3325
3326 /*
3327  * Writes msr value into into the appropriate "register".
3328  * Returns 0 on success, non-0 otherwise.
3329  * Assumes vcpu_load() was already called.
3330  */
3331 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3332 {
3333         struct vcpu_vmx *vmx = to_vmx(vcpu);
3334         struct shared_msr_entry *msr;
3335         int ret = 0;
3336         u32 msr_index = msr_info->index;
3337         u64 data = msr_info->data;
3338
3339         switch (msr_index) {
3340         case MSR_EFER:
3341                 ret = kvm_set_msr_common(vcpu, msr_info);
3342                 break;
3343 #ifdef CONFIG_X86_64
3344         case MSR_FS_BASE:
3345                 vmx_segment_cache_clear(vmx);
3346                 vmcs_writel(GUEST_FS_BASE, data);
3347                 break;
3348         case MSR_GS_BASE:
3349                 vmx_segment_cache_clear(vmx);
3350                 vmcs_writel(GUEST_GS_BASE, data);
3351                 break;
3352         case MSR_KERNEL_GS_BASE:
3353                 vmx_load_host_state(vmx);
3354                 vmx->msr_guest_kernel_gs_base = data;
3355                 break;
3356 #endif
3357         case MSR_IA32_SYSENTER_CS:
3358                 vmcs_write32(GUEST_SYSENTER_CS, data);
3359                 break;
3360         case MSR_IA32_SYSENTER_EIP:
3361                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3362                 break;
3363         case MSR_IA32_SYSENTER_ESP:
3364                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3365                 break;
3366         case MSR_IA32_BNDCFGS:
3367                 if (!kvm_mpx_supported() ||
3368                     (!msr_info->host_initiated &&
3369                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3370                         return 1;
3371                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3372                     (data & MSR_IA32_BNDCFGS_RSVD))
3373                         return 1;
3374                 vmcs_write64(GUEST_BNDCFGS, data);
3375                 break;
3376         case MSR_IA32_TSC:
3377                 kvm_write_tsc(vcpu, msr_info);
3378                 break;
3379         case MSR_IA32_SPEC_CTRL:
3380                 if (!msr_info->host_initiated &&
3381                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3382                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3383                         return 1;
3384
3385                 /* The STIBP bit doesn't fault even if it's not advertised */
3386                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
3387                         return 1;
3388
3389                 vmx->spec_ctrl = data;
3390
3391                 if (!data)
3392                         break;
3393
3394                 /*
3395                  * For non-nested:
3396                  * When it's written (to non-zero) for the first time, pass
3397                  * it through.
3398                  *
3399                  * For nested:
3400                  * The handling of the MSR bitmap for L2 guests is done in
3401                  * nested_vmx_merge_msr_bitmap. We should not touch the
3402                  * vmcs02.msr_bitmap here since it gets completely overwritten
3403                  * in the merging. We update the vmcs01 here for L1 as well
3404                  * since it will end up touching the MSR anyway now.
3405                  */
3406                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3407                                               MSR_IA32_SPEC_CTRL,
3408                                               MSR_TYPE_RW);
3409                 break;
3410         case MSR_IA32_PRED_CMD:
3411                 if (!msr_info->host_initiated &&
3412                     !guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&
3413                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3414                         return 1;
3415
3416                 if (data & ~PRED_CMD_IBPB)
3417                         return 1;
3418
3419                 if (!data)
3420                         break;
3421
3422                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3423
3424                 /*
3425                  * For non-nested:
3426                  * When it's written (to non-zero) for the first time, pass
3427                  * it through.
3428                  *
3429                  * For nested:
3430                  * The handling of the MSR bitmap for L2 guests is done in
3431                  * nested_vmx_merge_msr_bitmap. We should not touch the
3432                  * vmcs02.msr_bitmap here since it gets completely overwritten
3433                  * in the merging.
3434                  */
3435                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3436                                               MSR_TYPE_W);
3437                 break;
3438         case MSR_IA32_ARCH_CAPABILITIES:
3439                 if (!msr_info->host_initiated)
3440                         return 1;
3441                 vmx->arch_capabilities = data;
3442                 break;
3443         case MSR_IA32_CR_PAT:
3444                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3445                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3446                                 return 1;
3447                         vmcs_write64(GUEST_IA32_PAT, data);
3448                         vcpu->arch.pat = data;
3449                         break;
3450                 }
3451                 ret = kvm_set_msr_common(vcpu, msr_info);
3452                 break;
3453         case MSR_IA32_TSC_ADJUST:
3454                 ret = kvm_set_msr_common(vcpu, msr_info);
3455                 break;
3456         case MSR_IA32_MCG_EXT_CTL:
3457                 if ((!msr_info->host_initiated &&
3458                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3459                        FEATURE_CONTROL_LMCE)) ||
3460                     (data & ~MCG_EXT_CTL_LMCE_EN))
3461                         return 1;
3462                 vcpu->arch.mcg_ext_ctl = data;
3463                 break;
3464         case MSR_IA32_FEATURE_CONTROL:
3465                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3466                     (to_vmx(vcpu)->msr_ia32_feature_control &
3467                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3468                         return 1;
3469                 vmx->msr_ia32_feature_control = data;
3470                 if (msr_info->host_initiated && data == 0)
3471                         vmx_leave_nested(vcpu);
3472                 break;
3473         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3474                 if (!msr_info->host_initiated)
3475                         return 1; /* they are read-only */
3476                 if (!nested_vmx_allowed(vcpu))
3477                         return 1;
3478                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3479         case MSR_IA32_XSS:
3480                 if (!vmx_xsaves_supported())
3481                         return 1;
3482                 /*
3483                  * The only supported bit as of Skylake is bit 8, but
3484                  * it is not supported on KVM.
3485                  */
3486                 if (data != 0)
3487                         return 1;
3488                 vcpu->arch.ia32_xss = data;
3489                 if (vcpu->arch.ia32_xss != host_xss)
3490                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3491                                 vcpu->arch.ia32_xss, host_xss);
3492                 else
3493                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3494                 break;
3495         case MSR_TSC_AUX:
3496                 if (!msr_info->host_initiated &&
3497                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3498                         return 1;
3499                 /* Check reserved bit, higher 32 bits should be zero */
3500                 if ((data >> 32) != 0)
3501                         return 1;
3502                 /* Otherwise falls through */
3503         default:
3504                 msr = find_msr_entry(vmx, msr_index);
3505                 if (msr) {
3506                         u64 old_msr_data = msr->data;
3507                         msr->data = data;
3508                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3509                                 preempt_disable();
3510                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3511                                                          msr->mask);
3512                                 preempt_enable();
3513                                 if (ret)
3514                                         msr->data = old_msr_data;
3515                         }
3516                         break;
3517                 }
3518                 ret = kvm_set_msr_common(vcpu, msr_info);
3519         }
3520
3521         return ret;
3522 }
3523
3524 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3525 {
3526         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3527         switch (reg) {
3528         case VCPU_REGS_RSP:
3529                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3530                 break;
3531         case VCPU_REGS_RIP:
3532                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3533                 break;
3534         case VCPU_EXREG_PDPTR:
3535                 if (enable_ept)
3536                         ept_save_pdptrs(vcpu);
3537                 break;
3538         default:
3539                 break;
3540         }
3541 }
3542
3543 static __init int cpu_has_kvm_support(void)
3544 {
3545         return cpu_has_vmx();
3546 }
3547
3548 static __init int vmx_disabled_by_bios(void)
3549 {
3550         u64 msr;
3551
3552         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3553         if (msr & FEATURE_CONTROL_LOCKED) {
3554                 /* launched w/ TXT and VMX disabled */
3555                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3556                         && tboot_enabled())
3557                         return 1;
3558                 /* launched w/o TXT and VMX only enabled w/ TXT */
3559                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3560                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3561                         && !tboot_enabled()) {
3562                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3563                                 "activate TXT before enabling KVM\n");
3564                         return 1;
3565                 }
3566                 /* launched w/o TXT and VMX disabled */
3567                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3568                         && !tboot_enabled())
3569                         return 1;
3570         }
3571
3572         return 0;
3573 }
3574
3575 static void kvm_cpu_vmxon(u64 addr)
3576 {
3577         cr4_set_bits(X86_CR4_VMXE);
3578         intel_pt_handle_vmx(1);
3579
3580         asm volatile (ASM_VMX_VMXON_RAX
3581                         : : "a"(&addr), "m"(addr)
3582                         : "memory", "cc");
3583 }
3584
3585 static int hardware_enable(void)
3586 {
3587         int cpu = raw_smp_processor_id();
3588         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3589         u64 old, test_bits;
3590
3591         if (cr4_read_shadow() & X86_CR4_VMXE)
3592                 return -EBUSY;
3593
3594         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3595         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3596         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3597
3598         /*
3599          * Now we can enable the vmclear operation in kdump
3600          * since the loaded_vmcss_on_cpu list on this cpu
3601          * has been initialized.
3602          *
3603          * Though the cpu is not in VMX operation now, there
3604          * is no problem to enable the vmclear operation
3605          * for the loaded_vmcss_on_cpu list is empty!
3606          */
3607         crash_enable_local_vmclear(cpu);
3608
3609         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3610
3611         test_bits = FEATURE_CONTROL_LOCKED;
3612         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3613         if (tboot_enabled())
3614                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3615
3616         if ((old & test_bits) != test_bits) {
3617                 /* enable and lock */
3618                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3619         }
3620         kvm_cpu_vmxon(phys_addr);
3621         if (enable_ept)
3622                 ept_sync_global();
3623
3624         return 0;
3625 }
3626
3627 static void vmclear_local_loaded_vmcss(void)
3628 {
3629         int cpu = raw_smp_processor_id();
3630         struct loaded_vmcs *v, *n;
3631
3632         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3633                                  loaded_vmcss_on_cpu_link)
3634                 __loaded_vmcs_clear(v);
3635 }
3636
3637
3638 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3639  * tricks.
3640  */
3641 static void kvm_cpu_vmxoff(void)
3642 {
3643         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3644
3645         intel_pt_handle_vmx(0);
3646         cr4_clear_bits(X86_CR4_VMXE);
3647 }
3648
3649 static void hardware_disable(void)
3650 {
3651         vmclear_local_loaded_vmcss();
3652         kvm_cpu_vmxoff();
3653 }
3654
3655 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3656                                       u32 msr, u32 *result)
3657 {
3658         u32 vmx_msr_low, vmx_msr_high;
3659         u32 ctl = ctl_min | ctl_opt;
3660
3661         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3662
3663         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3664         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3665
3666         /* Ensure minimum (required) set of control bits are supported. */
3667         if (ctl_min & ~ctl)
3668                 return -EIO;
3669
3670         *result = ctl;
3671         return 0;
3672 }
3673
3674 static __init bool allow_1_setting(u32 msr, u32 ctl)
3675 {
3676         u32 vmx_msr_low, vmx_msr_high;
3677
3678         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3679         return vmx_msr_high & ctl;
3680 }
3681
3682 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3683 {
3684         u32 vmx_msr_low, vmx_msr_high;
3685         u32 min, opt, min2, opt2;
3686         u32 _pin_based_exec_control = 0;
3687         u32 _cpu_based_exec_control = 0;
3688         u32 _cpu_based_2nd_exec_control = 0;
3689         u32 _vmexit_control = 0;
3690         u32 _vmentry_control = 0;
3691
3692         min = CPU_BASED_HLT_EXITING |
3693 #ifdef CONFIG_X86_64
3694               CPU_BASED_CR8_LOAD_EXITING |
3695               CPU_BASED_CR8_STORE_EXITING |
3696 #endif
3697               CPU_BASED_CR3_LOAD_EXITING |
3698               CPU_BASED_CR3_STORE_EXITING |
3699               CPU_BASED_UNCOND_IO_EXITING |
3700               CPU_BASED_MOV_DR_EXITING |
3701               CPU_BASED_USE_TSC_OFFSETING |
3702               CPU_BASED_INVLPG_EXITING |
3703               CPU_BASED_RDPMC_EXITING;
3704
3705         if (!kvm_mwait_in_guest())
3706                 min |= CPU_BASED_MWAIT_EXITING |
3707                         CPU_BASED_MONITOR_EXITING;
3708
3709         opt = CPU_BASED_TPR_SHADOW |
3710               CPU_BASED_USE_MSR_BITMAPS |
3711               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3712         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3713                                 &_cpu_based_exec_control) < 0)
3714                 return -EIO;
3715 #ifdef CONFIG_X86_64
3716         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3717                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3718                                            ~CPU_BASED_CR8_STORE_EXITING;
3719 #endif
3720         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3721                 min2 = 0;
3722                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3723                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3724                         SECONDARY_EXEC_WBINVD_EXITING |
3725                         SECONDARY_EXEC_ENABLE_VPID |
3726                         SECONDARY_EXEC_ENABLE_EPT |
3727                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3728                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3729                         SECONDARY_EXEC_DESC |
3730                         SECONDARY_EXEC_RDTSCP |
3731                         SECONDARY_EXEC_ENABLE_INVPCID |
3732                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3733                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3734                         SECONDARY_EXEC_SHADOW_VMCS |
3735                         SECONDARY_EXEC_XSAVES |
3736                         SECONDARY_EXEC_RDSEED_EXITING |
3737                         SECONDARY_EXEC_RDRAND_EXITING |
3738                         SECONDARY_EXEC_ENABLE_PML |
3739                         SECONDARY_EXEC_TSC_SCALING |
3740                         SECONDARY_EXEC_ENABLE_VMFUNC;
3741                 if (adjust_vmx_controls(min2, opt2,
3742                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3743                                         &_cpu_based_2nd_exec_control) < 0)
3744                         return -EIO;
3745         }
3746 #ifndef CONFIG_X86_64
3747         if (!(_cpu_based_2nd_exec_control &
3748                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3749                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3750 #endif
3751
3752         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3753                 _cpu_based_2nd_exec_control &= ~(
3754                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3755                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3756                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3757
3758         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
3759                 &vmx_capability.ept, &vmx_capability.vpid);
3760
3761         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3762                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3763                    enabled */
3764                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3765                                              CPU_BASED_CR3_STORE_EXITING |
3766                                              CPU_BASED_INVLPG_EXITING);
3767         } else if (vmx_capability.ept) {
3768                 vmx_capability.ept = 0;
3769                 pr_warn_once("EPT CAP should not exist if not support "
3770                                 "1-setting enable EPT VM-execution control\n");
3771         }
3772         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
3773                 vmx_capability.vpid) {
3774                 vmx_capability.vpid = 0;
3775                 pr_warn_once("VPID CAP should not exist if not support "
3776                                 "1-setting enable VPID VM-execution control\n");
3777         }
3778
3779         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3780 #ifdef CONFIG_X86_64
3781         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3782 #endif
3783         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3784                 VM_EXIT_CLEAR_BNDCFGS;
3785         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3786                                 &_vmexit_control) < 0)
3787                 return -EIO;
3788
3789         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3790         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3791                  PIN_BASED_VMX_PREEMPTION_TIMER;
3792         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3793                                 &_pin_based_exec_control) < 0)
3794                 return -EIO;
3795
3796         if (cpu_has_broken_vmx_preemption_timer())
3797                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3798         if (!(_cpu_based_2nd_exec_control &
3799                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3800                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3801
3802         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3803         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3804         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3805                                 &_vmentry_control) < 0)
3806                 return -EIO;
3807
3808         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3809
3810         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3811         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3812                 return -EIO;
3813
3814 #ifdef CONFIG_X86_64
3815         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3816         if (vmx_msr_high & (1u<<16))
3817                 return -EIO;
3818 #endif
3819
3820         /* Require Write-Back (WB) memory type for VMCS accesses. */
3821         if (((vmx_msr_high >> 18) & 15) != 6)
3822                 return -EIO;
3823
3824         vmcs_conf->size = vmx_msr_high & 0x1fff;
3825         vmcs_conf->order = get_order(vmcs_conf->size);
3826         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3827         vmcs_conf->revision_id = vmx_msr_low;
3828
3829         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3830         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3831         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3832         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3833         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3834
3835         cpu_has_load_ia32_efer =
3836                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3837                                 VM_ENTRY_LOAD_IA32_EFER)
3838                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3839                                    VM_EXIT_LOAD_IA32_EFER);
3840
3841         cpu_has_load_perf_global_ctrl =
3842                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3843                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3844                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3845                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3846
3847         /*
3848          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3849          * but due to errata below it can't be used. Workaround is to use
3850          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3851          *
3852          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3853          *
3854          * AAK155             (model 26)
3855          * AAP115             (model 30)
3856          * AAT100             (model 37)
3857          * BC86,AAY89,BD102   (model 44)
3858          * BA97               (model 46)
3859          *
3860          */
3861         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3862                 switch (boot_cpu_data.x86_model) {
3863                 case 26:
3864                 case 30:
3865                 case 37:
3866                 case 44:
3867                 case 46:
3868                         cpu_has_load_perf_global_ctrl = false;
3869                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3870                                         "does not work properly. Using workaround\n");
3871                         break;
3872                 default:
3873                         break;
3874                 }
3875         }
3876
3877         if (boot_cpu_has(X86_FEATURE_XSAVES))
3878                 rdmsrl(MSR_IA32_XSS, host_xss);
3879
3880         return 0;
3881 }
3882
3883 static struct vmcs *alloc_vmcs_cpu(int cpu)
3884 {
3885         int node = cpu_to_node(cpu);
3886         struct page *pages;
3887         struct vmcs *vmcs;
3888
3889         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3890         if (!pages)
3891                 return NULL;
3892         vmcs = page_address(pages);
3893         memset(vmcs, 0, vmcs_config.size);
3894         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3895         return vmcs;
3896 }
3897
3898 static void free_vmcs(struct vmcs *vmcs)
3899 {
3900         free_pages((unsigned long)vmcs, vmcs_config.order);
3901 }
3902
3903 /*
3904  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3905  */
3906 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3907 {
3908         if (!loaded_vmcs->vmcs)
3909                 return;
3910         loaded_vmcs_clear(loaded_vmcs);
3911         free_vmcs(loaded_vmcs->vmcs);
3912         loaded_vmcs->vmcs = NULL;
3913         if (loaded_vmcs->msr_bitmap)
3914                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
3915         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3916 }
3917
3918 static struct vmcs *alloc_vmcs(void)
3919 {
3920         return alloc_vmcs_cpu(raw_smp_processor_id());
3921 }
3922
3923 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3924 {
3925         loaded_vmcs->vmcs = alloc_vmcs();
3926         if (!loaded_vmcs->vmcs)
3927                 return -ENOMEM;
3928
3929         loaded_vmcs->shadow_vmcs = NULL;
3930         loaded_vmcs_init(loaded_vmcs);
3931
3932         if (cpu_has_vmx_msr_bitmap()) {
3933                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
3934                 if (!loaded_vmcs->msr_bitmap)
3935                         goto out_vmcs;
3936                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
3937         }
3938         return 0;
3939
3940 out_vmcs:
3941         free_loaded_vmcs(loaded_vmcs);
3942         return -ENOMEM;
3943 }
3944
3945 static void free_kvm_area(void)
3946 {
3947         int cpu;
3948
3949         for_each_possible_cpu(cpu) {
3950                 free_vmcs(per_cpu(vmxarea, cpu));
3951                 per_cpu(vmxarea, cpu) = NULL;
3952         }
3953 }
3954
3955 enum vmcs_field_width {
3956         VMCS_FIELD_WIDTH_U16 = 0,
3957         VMCS_FIELD_WIDTH_U64 = 1,
3958         VMCS_FIELD_WIDTH_U32 = 2,
3959         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
3960 };
3961
3962 static inline int vmcs_field_width(unsigned long field)
3963 {
3964         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3965                 return VMCS_FIELD_WIDTH_U32;
3966         return (field >> 13) & 0x3 ;
3967 }
3968
3969 static inline int vmcs_field_readonly(unsigned long field)
3970 {
3971         return (((field >> 10) & 0x3) == 1);
3972 }
3973
3974 static void init_vmcs_shadow_fields(void)
3975 {
3976         int i, j;
3977
3978         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
3979                 u16 field = shadow_read_only_fields[i];
3980                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
3981                     (i + 1 == max_shadow_read_only_fields ||
3982                      shadow_read_only_fields[i + 1] != field + 1))
3983                         pr_err("Missing field from shadow_read_only_field %x\n",
3984                                field + 1);
3985
3986                 clear_bit(field, vmx_vmread_bitmap);
3987 #ifdef CONFIG_X86_64
3988                 if (field & 1)
3989                         continue;
3990 #endif
3991                 if (j < i)
3992                         shadow_read_only_fields[j] = field;
3993                 j++;
3994         }
3995         max_shadow_read_only_fields = j;
3996
3997         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3998                 u16 field = shadow_read_write_fields[i];
3999                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4000                     (i + 1 == max_shadow_read_write_fields ||
4001                      shadow_read_write_fields[i + 1] != field + 1))
4002                         pr_err("Missing field from shadow_read_write_field %x\n",
4003                                field + 1);
4004
4005                 /*
4006                  * PML and the preemption timer can be emulated, but the
4007                  * processor cannot vmwrite to fields that don't exist
4008                  * on bare metal.
4009                  */
4010                 switch (field) {
4011                 case GUEST_PML_INDEX:
4012                         if (!cpu_has_vmx_pml())
4013                                 continue;
4014                         break;
4015                 case VMX_PREEMPTION_TIMER_VALUE:
4016                         if (!cpu_has_vmx_preemption_timer())
4017                                 continue;
4018                         break;
4019                 case GUEST_INTR_STATUS:
4020                         if (!cpu_has_vmx_apicv())
4021                                 continue;
4022                         break;
4023                 default:
4024                         break;
4025                 }
4026
4027                 clear_bit(field, vmx_vmwrite_bitmap);
4028                 clear_bit(field, vmx_vmread_bitmap);
4029 #ifdef CONFIG_X86_64
4030                 if (field & 1)
4031                         continue;
4032 #endif
4033                 if (j < i)
4034                         shadow_read_write_fields[j] = field;
4035                 j++;
4036         }
4037         max_shadow_read_write_fields = j;
4038 }
4039
4040 static __init int alloc_kvm_area(void)
4041 {
4042         int cpu;
4043
4044         for_each_possible_cpu(cpu) {
4045                 struct vmcs *vmcs;
4046
4047                 vmcs = alloc_vmcs_cpu(cpu);
4048                 if (!vmcs) {
4049                         free_kvm_area();
4050                         return -ENOMEM;
4051                 }
4052
4053                 per_cpu(vmxarea, cpu) = vmcs;
4054         }
4055         return 0;
4056 }
4057
4058 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4059                 struct kvm_segment *save)
4060 {
4061         if (!emulate_invalid_guest_state) {
4062                 /*
4063                  * CS and SS RPL should be equal during guest entry according
4064                  * to VMX spec, but in reality it is not always so. Since vcpu
4065                  * is in the middle of the transition from real mode to
4066                  * protected mode it is safe to assume that RPL 0 is a good
4067                  * default value.
4068                  */
4069                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4070                         save->selector &= ~SEGMENT_RPL_MASK;
4071                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4072                 save->s = 1;
4073         }
4074         vmx_set_segment(vcpu, save, seg);
4075 }
4076
4077 static void enter_pmode(struct kvm_vcpu *vcpu)
4078 {
4079         unsigned long flags;
4080         struct vcpu_vmx *vmx = to_vmx(vcpu);
4081
4082         /*
4083          * Update real mode segment cache. It may be not up-to-date if sement
4084          * register was written while vcpu was in a guest mode.
4085          */
4086         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4087         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4088         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4089         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4090         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4091         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4092
4093         vmx->rmode.vm86_active = 0;
4094
4095         vmx_segment_cache_clear(vmx);
4096
4097         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4098
4099         flags = vmcs_readl(GUEST_RFLAGS);
4100         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4101         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4102         vmcs_writel(GUEST_RFLAGS, flags);
4103
4104         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4105                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4106
4107         update_exception_bitmap(vcpu);
4108
4109         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4110         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4111         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4112         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4113         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4114         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4115 }
4116
4117 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4118 {
4119         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4120         struct kvm_segment var = *save;
4121
4122         var.dpl = 0x3;
4123         if (seg == VCPU_SREG_CS)
4124                 var.type = 0x3;
4125
4126         if (!emulate_invalid_guest_state) {
4127                 var.selector = var.base >> 4;
4128                 var.base = var.base & 0xffff0;
4129                 var.limit = 0xffff;
4130                 var.g = 0;
4131                 var.db = 0;
4132                 var.present = 1;
4133                 var.s = 1;
4134                 var.l = 0;
4135                 var.unusable = 0;
4136                 var.type = 0x3;
4137                 var.avl = 0;
4138                 if (save->base & 0xf)
4139                         printk_once(KERN_WARNING "kvm: segment base is not "
4140                                         "paragraph aligned when entering "
4141                                         "protected mode (seg=%d)", seg);
4142         }
4143
4144         vmcs_write16(sf->selector, var.selector);
4145         vmcs_writel(sf->base, var.base);
4146         vmcs_write32(sf->limit, var.limit);
4147         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4148 }
4149
4150 static void enter_rmode(struct kvm_vcpu *vcpu)
4151 {
4152         unsigned long flags;
4153         struct vcpu_vmx *vmx = to_vmx(vcpu);
4154
4155         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4156         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4157         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4158         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4159         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4160         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4161         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4162
4163         vmx->rmode.vm86_active = 1;
4164
4165         /*
4166          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4167          * vcpu. Warn the user that an update is overdue.
4168          */
4169         if (!vcpu->kvm->arch.tss_addr)
4170                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4171                              "called before entering vcpu\n");
4172
4173         vmx_segment_cache_clear(vmx);
4174
4175         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4176         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4177         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4178
4179         flags = vmcs_readl(GUEST_RFLAGS);
4180         vmx->rmode.save_rflags = flags;
4181
4182         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4183
4184         vmcs_writel(GUEST_RFLAGS, flags);
4185         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4186         update_exception_bitmap(vcpu);
4187
4188         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4189         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4190         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4191         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4192         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4193         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4194
4195         kvm_mmu_reset_context(vcpu);
4196 }
4197
4198 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4199 {
4200         struct vcpu_vmx *vmx = to_vmx(vcpu);
4201         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4202
4203         if (!msr)
4204                 return;
4205
4206         /*
4207          * Force kernel_gs_base reloading before EFER changes, as control
4208          * of this msr depends on is_long_mode().
4209          */
4210         vmx_load_host_state(to_vmx(vcpu));
4211         vcpu->arch.efer = efer;
4212         if (efer & EFER_LMA) {
4213                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4214                 msr->data = efer;
4215         } else {
4216                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4217
4218                 msr->data = efer & ~EFER_LME;
4219         }
4220         setup_msrs(vmx);
4221 }
4222
4223 #ifdef CONFIG_X86_64
4224
4225 static void enter_lmode(struct kvm_vcpu *vcpu)
4226 {
4227         u32 guest_tr_ar;
4228
4229         vmx_segment_cache_clear(to_vmx(vcpu));
4230
4231         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4232         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4233                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4234                                      __func__);
4235                 vmcs_write32(GUEST_TR_AR_BYTES,
4236                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4237                              | VMX_AR_TYPE_BUSY_64_TSS);
4238         }
4239         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4240 }
4241
4242 static void exit_lmode(struct kvm_vcpu *vcpu)
4243 {
4244         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4245         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4246 }
4247
4248 #endif
4249
4250 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4251                                 bool invalidate_gpa)
4252 {
4253         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4254                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4255                         return;
4256                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4257         } else {
4258                 vpid_sync_context(vpid);
4259         }
4260 }
4261
4262 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4263 {
4264         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4265 }
4266
4267 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4268 {
4269         if (enable_ept)
4270                 vmx_flush_tlb(vcpu, true);
4271 }
4272
4273 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4274 {
4275         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4276
4277         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4278         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4279 }
4280
4281 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4282 {
4283         if (enable_ept && is_paging(vcpu))
4284                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4285         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4286 }
4287
4288 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4289 {
4290         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4291
4292         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4293         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4294 }
4295
4296 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4297 {
4298         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4299
4300         if (!test_bit(VCPU_EXREG_PDPTR,
4301                       (unsigned long *)&vcpu->arch.regs_dirty))
4302                 return;
4303
4304         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4305                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4306                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4307                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4308                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4309         }
4310 }
4311
4312 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4313 {
4314         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4315
4316         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4317                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4318                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4319                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4320                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4321         }
4322
4323         __set_bit(VCPU_EXREG_PDPTR,
4324                   (unsigned long *)&vcpu->arch.regs_avail);
4325         __set_bit(VCPU_EXREG_PDPTR,
4326                   (unsigned long *)&vcpu->arch.regs_dirty);
4327 }
4328
4329 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4330 {
4331         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4332         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4333         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4334
4335         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4336                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4337             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4338                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4339
4340         return fixed_bits_valid(val, fixed0, fixed1);
4341 }
4342
4343 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4344 {
4345         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4346         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4347
4348         return fixed_bits_valid(val, fixed0, fixed1);
4349 }
4350
4351 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4352 {
4353         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4354         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4355
4356         return fixed_bits_valid(val, fixed0, fixed1);
4357 }
4358
4359 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4360 #define nested_guest_cr4_valid  nested_cr4_valid
4361 #define nested_host_cr4_valid   nested_cr4_valid
4362
4363 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4364
4365 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4366                                         unsigned long cr0,
4367                                         struct kvm_vcpu *vcpu)
4368 {
4369         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4370                 vmx_decache_cr3(vcpu);
4371         if (!(cr0 & X86_CR0_PG)) {
4372                 /* From paging/starting to nonpaging */
4373                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4374                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4375                              (CPU_BASED_CR3_LOAD_EXITING |
4376                               CPU_BASED_CR3_STORE_EXITING));
4377                 vcpu->arch.cr0 = cr0;
4378                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4379         } else if (!is_paging(vcpu)) {
4380                 /* From nonpaging to paging */
4381                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4382                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4383                              ~(CPU_BASED_CR3_LOAD_EXITING |
4384                                CPU_BASED_CR3_STORE_EXITING));
4385                 vcpu->arch.cr0 = cr0;
4386                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4387         }
4388
4389         if (!(cr0 & X86_CR0_WP))
4390                 *hw_cr0 &= ~X86_CR0_WP;
4391 }
4392
4393 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4394 {
4395         struct vcpu_vmx *vmx = to_vmx(vcpu);
4396         unsigned long hw_cr0;
4397
4398         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4399         if (enable_unrestricted_guest)
4400                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4401         else {
4402                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4403
4404                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4405                         enter_pmode(vcpu);
4406
4407                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4408                         enter_rmode(vcpu);
4409         }
4410
4411 #ifdef CONFIG_X86_64
4412         if (vcpu->arch.efer & EFER_LME) {
4413                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4414                         enter_lmode(vcpu);
4415                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4416                         exit_lmode(vcpu);
4417         }
4418 #endif
4419
4420         if (enable_ept)
4421                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4422
4423         vmcs_writel(CR0_READ_SHADOW, cr0);
4424         vmcs_writel(GUEST_CR0, hw_cr0);
4425         vcpu->arch.cr0 = cr0;
4426
4427         /* depends on vcpu->arch.cr0 to be set to a new value */
4428         vmx->emulation_required = emulation_required(vcpu);
4429 }
4430
4431 static int get_ept_level(struct kvm_vcpu *vcpu)
4432 {
4433         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4434                 return 5;
4435         return 4;
4436 }
4437
4438 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4439 {
4440         u64 eptp = VMX_EPTP_MT_WB;
4441
4442         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4443
4444         if (enable_ept_ad_bits &&
4445             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4446                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4447         eptp |= (root_hpa & PAGE_MASK);
4448
4449         return eptp;
4450 }
4451
4452 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4453 {
4454         unsigned long guest_cr3;
4455         u64 eptp;
4456
4457         guest_cr3 = cr3;
4458         if (enable_ept) {
4459                 eptp = construct_eptp(vcpu, cr3);
4460                 vmcs_write64(EPT_POINTER, eptp);
4461                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4462                         guest_cr3 = kvm_read_cr3(vcpu);
4463                 else
4464                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4465                 ept_load_pdptrs(vcpu);
4466         }
4467
4468         vmx_flush_tlb(vcpu, true);
4469         vmcs_writel(GUEST_CR3, guest_cr3);
4470 }
4471
4472 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4473 {
4474         /*
4475          * Pass through host's Machine Check Enable value to hw_cr4, which
4476          * is in force while we are in guest mode.  Do not let guests control
4477          * this bit, even if host CR4.MCE == 0.
4478          */
4479         unsigned long hw_cr4 =
4480                 (cr4_read_shadow() & X86_CR4_MCE) |
4481                 (cr4 & ~X86_CR4_MCE) |
4482                 (to_vmx(vcpu)->rmode.vm86_active ?
4483                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4484
4485         if ((cr4 & X86_CR4_UMIP) && !boot_cpu_has(X86_FEATURE_UMIP)) {
4486                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4487                               SECONDARY_EXEC_DESC);
4488                 hw_cr4 &= ~X86_CR4_UMIP;
4489         } else
4490                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4491                                 SECONDARY_EXEC_DESC);
4492
4493         if (cr4 & X86_CR4_VMXE) {
4494                 /*
4495                  * To use VMXON (and later other VMX instructions), a guest
4496                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4497                  * So basically the check on whether to allow nested VMX
4498                  * is here.
4499                  */
4500                 if (!nested_vmx_allowed(vcpu))
4501                         return 1;
4502         }
4503
4504         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4505                 return 1;
4506
4507         vcpu->arch.cr4 = cr4;
4508         if (enable_ept) {
4509                 if (!is_paging(vcpu)) {
4510                         hw_cr4 &= ~X86_CR4_PAE;
4511                         hw_cr4 |= X86_CR4_PSE;
4512                 } else if (!(cr4 & X86_CR4_PAE)) {
4513                         hw_cr4 &= ~X86_CR4_PAE;
4514                 }
4515         }
4516
4517         if (!enable_unrestricted_guest && !is_paging(vcpu))
4518                 /*
4519                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4520                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4521                  * to be manually disabled when guest switches to non-paging
4522                  * mode.
4523                  *
4524                  * If !enable_unrestricted_guest, the CPU is always running
4525                  * with CR0.PG=1 and CR4 needs to be modified.
4526                  * If enable_unrestricted_guest, the CPU automatically
4527                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4528                  */
4529                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4530
4531         vmcs_writel(CR4_READ_SHADOW, cr4);
4532         vmcs_writel(GUEST_CR4, hw_cr4);
4533         return 0;
4534 }
4535
4536 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4537                             struct kvm_segment *var, int seg)
4538 {
4539         struct vcpu_vmx *vmx = to_vmx(vcpu);
4540         u32 ar;
4541
4542         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4543                 *var = vmx->rmode.segs[seg];
4544                 if (seg == VCPU_SREG_TR
4545                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4546                         return;
4547                 var->base = vmx_read_guest_seg_base(vmx, seg);
4548                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4549                 return;
4550         }
4551         var->base = vmx_read_guest_seg_base(vmx, seg);
4552         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4553         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4554         ar = vmx_read_guest_seg_ar(vmx, seg);
4555         var->unusable = (ar >> 16) & 1;
4556         var->type = ar & 15;
4557         var->s = (ar >> 4) & 1;
4558         var->dpl = (ar >> 5) & 3;
4559         /*
4560          * Some userspaces do not preserve unusable property. Since usable
4561          * segment has to be present according to VMX spec we can use present
4562          * property to amend userspace bug by making unusable segment always
4563          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4564          * segment as unusable.
4565          */
4566         var->present = !var->unusable;
4567         var->avl = (ar >> 12) & 1;
4568         var->l = (ar >> 13) & 1;
4569         var->db = (ar >> 14) & 1;
4570         var->g = (ar >> 15) & 1;
4571 }
4572
4573 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4574 {
4575         struct kvm_segment s;
4576
4577         if (to_vmx(vcpu)->rmode.vm86_active) {
4578                 vmx_get_segment(vcpu, &s, seg);
4579                 return s.base;
4580         }
4581         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4582 }
4583
4584 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4585 {
4586         struct vcpu_vmx *vmx = to_vmx(vcpu);
4587
4588         if (unlikely(vmx->rmode.vm86_active))
4589                 return 0;
4590         else {
4591                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4592                 return VMX_AR_DPL(ar);
4593         }
4594 }
4595
4596 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4597 {
4598         u32 ar;
4599
4600         if (var->unusable || !var->present)
4601                 ar = 1 << 16;
4602         else {
4603                 ar = var->type & 15;
4604                 ar |= (var->s & 1) << 4;
4605                 ar |= (var->dpl & 3) << 5;
4606                 ar |= (var->present & 1) << 7;
4607                 ar |= (var->avl & 1) << 12;
4608                 ar |= (var->l & 1) << 13;
4609                 ar |= (var->db & 1) << 14;
4610                 ar |= (var->g & 1) << 15;
4611         }
4612
4613         return ar;
4614 }
4615
4616 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4617                             struct kvm_segment *var, int seg)
4618 {
4619         struct vcpu_vmx *vmx = to_vmx(vcpu);
4620         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4621
4622         vmx_segment_cache_clear(vmx);
4623
4624         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4625                 vmx->rmode.segs[seg] = *var;
4626                 if (seg == VCPU_SREG_TR)
4627                         vmcs_write16(sf->selector, var->selector);
4628                 else if (var->s)
4629                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4630                 goto out;
4631         }
4632
4633         vmcs_writel(sf->base, var->base);
4634         vmcs_write32(sf->limit, var->limit);
4635         vmcs_write16(sf->selector, var->selector);
4636
4637         /*
4638          *   Fix the "Accessed" bit in AR field of segment registers for older
4639          * qemu binaries.
4640          *   IA32 arch specifies that at the time of processor reset the
4641          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4642          * is setting it to 0 in the userland code. This causes invalid guest
4643          * state vmexit when "unrestricted guest" mode is turned on.
4644          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4645          * tree. Newer qemu binaries with that qemu fix would not need this
4646          * kvm hack.
4647          */
4648         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4649                 var->type |= 0x1; /* Accessed */
4650
4651         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4652
4653 out:
4654         vmx->emulation_required = emulation_required(vcpu);
4655 }
4656
4657 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4658 {
4659         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4660
4661         *db = (ar >> 14) & 1;
4662         *l = (ar >> 13) & 1;
4663 }
4664
4665 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4666 {
4667         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4668         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4669 }
4670
4671 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4672 {
4673         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4674         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4675 }
4676
4677 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4678 {
4679         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4680         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4681 }
4682
4683 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4684 {
4685         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4686         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4687 }
4688
4689 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4690 {
4691         struct kvm_segment var;
4692         u32 ar;
4693
4694         vmx_get_segment(vcpu, &var, seg);
4695         var.dpl = 0x3;
4696         if (seg == VCPU_SREG_CS)
4697                 var.type = 0x3;
4698         ar = vmx_segment_access_rights(&var);
4699
4700         if (var.base != (var.selector << 4))
4701                 return false;
4702         if (var.limit != 0xffff)
4703                 return false;
4704         if (ar != 0xf3)
4705                 return false;
4706
4707         return true;
4708 }
4709
4710 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4711 {
4712         struct kvm_segment cs;
4713         unsigned int cs_rpl;
4714
4715         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4716         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4717
4718         if (cs.unusable)
4719                 return false;
4720         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4721                 return false;
4722         if (!cs.s)
4723                 return false;
4724         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4725                 if (cs.dpl > cs_rpl)
4726                         return false;
4727         } else {
4728                 if (cs.dpl != cs_rpl)
4729                         return false;
4730         }
4731         if (!cs.present)
4732                 return false;
4733
4734         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4735         return true;
4736 }
4737
4738 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4739 {
4740         struct kvm_segment ss;
4741         unsigned int ss_rpl;
4742
4743         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4744         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4745
4746         if (ss.unusable)
4747                 return true;
4748         if (ss.type != 3 && ss.type != 7)
4749                 return false;
4750         if (!ss.s)
4751                 return false;
4752         if (ss.dpl != ss_rpl) /* DPL != RPL */
4753                 return false;
4754         if (!ss.present)
4755                 return false;
4756
4757         return true;
4758 }
4759
4760 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4761 {
4762         struct kvm_segment var;
4763         unsigned int rpl;
4764
4765         vmx_get_segment(vcpu, &var, seg);
4766         rpl = var.selector & SEGMENT_RPL_MASK;
4767
4768         if (var.unusable)
4769                 return true;
4770         if (!var.s)
4771                 return false;
4772         if (!var.present)
4773                 return false;
4774         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4775                 if (var.dpl < rpl) /* DPL < RPL */
4776                         return false;
4777         }
4778
4779         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4780          * rights flags
4781          */
4782         return true;
4783 }
4784
4785 static bool tr_valid(struct kvm_vcpu *vcpu)
4786 {
4787         struct kvm_segment tr;
4788
4789         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4790
4791         if (tr.unusable)
4792                 return false;
4793         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4794                 return false;
4795         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4796                 return false;
4797         if (!tr.present)
4798                 return false;
4799
4800         return true;
4801 }
4802
4803 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4804 {
4805         struct kvm_segment ldtr;
4806
4807         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4808
4809         if (ldtr.unusable)
4810                 return true;
4811         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4812                 return false;
4813         if (ldtr.type != 2)
4814                 return false;
4815         if (!ldtr.present)
4816                 return false;
4817
4818         return true;
4819 }
4820
4821 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4822 {
4823         struct kvm_segment cs, ss;
4824
4825         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4826         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4827
4828         return ((cs.selector & SEGMENT_RPL_MASK) ==
4829                  (ss.selector & SEGMENT_RPL_MASK));
4830 }
4831
4832 /*
4833  * Check if guest state is valid. Returns true if valid, false if
4834  * not.
4835  * We assume that registers are always usable
4836  */
4837 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4838 {
4839         if (enable_unrestricted_guest)
4840                 return true;
4841
4842         /* real mode guest state checks */
4843         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4844                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4845                         return false;
4846                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4847                         return false;
4848                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4849                         return false;
4850                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4851                         return false;
4852                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4853                         return false;
4854                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4855                         return false;
4856         } else {
4857         /* protected mode guest state checks */
4858                 if (!cs_ss_rpl_check(vcpu))
4859                         return false;
4860                 if (!code_segment_valid(vcpu))
4861                         return false;
4862                 if (!stack_segment_valid(vcpu))
4863                         return false;
4864                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4865                         return false;
4866                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4867                         return false;
4868                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4869                         return false;
4870                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4871                         return false;
4872                 if (!tr_valid(vcpu))
4873                         return false;
4874                 if (!ldtr_valid(vcpu))
4875                         return false;
4876         }
4877         /* TODO:
4878          * - Add checks on RIP
4879          * - Add checks on RFLAGS
4880          */
4881
4882         return true;
4883 }
4884
4885 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4886 {
4887         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4888 }
4889
4890 static int init_rmode_tss(struct kvm *kvm)
4891 {
4892         gfn_t fn;
4893         u16 data = 0;
4894         int idx, r;
4895
4896         idx = srcu_read_lock(&kvm->srcu);
4897         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4898         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4899         if (r < 0)
4900                 goto out;
4901         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4902         r = kvm_write_guest_page(kvm, fn++, &data,
4903                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4904         if (r < 0)
4905                 goto out;
4906         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4907         if (r < 0)
4908                 goto out;
4909         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4910         if (r < 0)
4911                 goto out;
4912         data = ~0;
4913         r = kvm_write_guest_page(kvm, fn, &data,
4914                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4915                                  sizeof(u8));
4916 out:
4917         srcu_read_unlock(&kvm->srcu, idx);
4918         return r;
4919 }
4920
4921 static int init_rmode_identity_map(struct kvm *kvm)
4922 {
4923         int i, idx, r = 0;
4924         kvm_pfn_t identity_map_pfn;
4925         u32 tmp;
4926
4927         /* Protect kvm->arch.ept_identity_pagetable_done. */
4928         mutex_lock(&kvm->slots_lock);
4929
4930         if (likely(kvm->arch.ept_identity_pagetable_done))
4931                 goto out2;
4932
4933         if (!kvm->arch.ept_identity_map_addr)
4934                 kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4935         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4936
4937         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4938                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4939         if (r < 0)
4940                 goto out2;
4941
4942         idx = srcu_read_lock(&kvm->srcu);
4943         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4944         if (r < 0)
4945                 goto out;
4946         /* Set up identity-mapping pagetable for EPT in real mode */
4947         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4948                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4949                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4950                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4951                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4952                 if (r < 0)
4953                         goto out;
4954         }
4955         kvm->arch.ept_identity_pagetable_done = true;
4956
4957 out:
4958         srcu_read_unlock(&kvm->srcu, idx);
4959
4960 out2:
4961         mutex_unlock(&kvm->slots_lock);
4962         return r;
4963 }
4964
4965 static void seg_setup(int seg)
4966 {
4967         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4968         unsigned int ar;
4969
4970         vmcs_write16(sf->selector, 0);
4971         vmcs_writel(sf->base, 0);
4972         vmcs_write32(sf->limit, 0xffff);
4973         ar = 0x93;
4974         if (seg == VCPU_SREG_CS)
4975                 ar |= 0x08; /* code segment */
4976
4977         vmcs_write32(sf->ar_bytes, ar);
4978 }
4979
4980 static int alloc_apic_access_page(struct kvm *kvm)
4981 {
4982         struct page *page;
4983         int r = 0;
4984
4985         mutex_lock(&kvm->slots_lock);
4986         if (kvm->arch.apic_access_page_done)
4987                 goto out;
4988         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4989                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4990         if (r)
4991                 goto out;
4992
4993         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4994         if (is_error_page(page)) {
4995                 r = -EFAULT;
4996                 goto out;
4997         }
4998
4999         /*
5000          * Do not pin the page in memory, so that memory hot-unplug
5001          * is able to migrate it.
5002          */
5003         put_page(page);
5004         kvm->arch.apic_access_page_done = true;
5005 out:
5006         mutex_unlock(&kvm->slots_lock);
5007         return r;
5008 }
5009
5010 static int allocate_vpid(void)
5011 {
5012         int vpid;
5013
5014         if (!enable_vpid)
5015                 return 0;
5016         spin_lock(&vmx_vpid_lock);
5017         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5018         if (vpid < VMX_NR_VPIDS)
5019                 __set_bit(vpid, vmx_vpid_bitmap);
5020         else
5021                 vpid = 0;
5022         spin_unlock(&vmx_vpid_lock);
5023         return vpid;
5024 }
5025
5026 static void free_vpid(int vpid)
5027 {
5028         if (!enable_vpid || vpid == 0)
5029                 return;
5030         spin_lock(&vmx_vpid_lock);
5031         __clear_bit(vpid, vmx_vpid_bitmap);
5032         spin_unlock(&vmx_vpid_lock);
5033 }
5034
5035 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5036                                                           u32 msr, int type)
5037 {
5038         int f = sizeof(unsigned long);
5039
5040         if (!cpu_has_vmx_msr_bitmap())
5041                 return;
5042
5043         /*
5044          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5045          * have the write-low and read-high bitmap offsets the wrong way round.
5046          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5047          */
5048         if (msr <= 0x1fff) {
5049                 if (type & MSR_TYPE_R)
5050                         /* read-low */
5051                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5052
5053                 if (type & MSR_TYPE_W)
5054                         /* write-low */
5055                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5056
5057         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5058                 msr &= 0x1fff;
5059                 if (type & MSR_TYPE_R)
5060                         /* read-high */
5061                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5062
5063                 if (type & MSR_TYPE_W)
5064                         /* write-high */
5065                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5066
5067         }
5068 }
5069
5070 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5071                                                          u32 msr, int type)
5072 {
5073         int f = sizeof(unsigned long);
5074
5075         if (!cpu_has_vmx_msr_bitmap())
5076                 return;
5077
5078         /*
5079          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5080          * have the write-low and read-high bitmap offsets the wrong way round.
5081          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5082          */
5083         if (msr <= 0x1fff) {
5084                 if (type & MSR_TYPE_R)
5085                         /* read-low */
5086                         __set_bit(msr, msr_bitmap + 0x000 / f);
5087
5088                 if (type & MSR_TYPE_W)
5089                         /* write-low */
5090                         __set_bit(msr, msr_bitmap + 0x800 / f);
5091
5092         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5093                 msr &= 0x1fff;
5094                 if (type & MSR_TYPE_R)
5095                         /* read-high */
5096                         __set_bit(msr, msr_bitmap + 0x400 / f);
5097
5098                 if (type & MSR_TYPE_W)
5099                         /* write-high */
5100                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5101
5102         }
5103 }
5104
5105 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5106                                                       u32 msr, int type, bool value)
5107 {
5108         if (value)
5109                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5110         else
5111                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5112 }
5113
5114 /*
5115  * If a msr is allowed by L0, we should check whether it is allowed by L1.
5116  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5117  */
5118 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5119                                                unsigned long *msr_bitmap_nested,
5120                                                u32 msr, int type)
5121 {
5122         int f = sizeof(unsigned long);
5123
5124         /*
5125          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5126          * have the write-low and read-high bitmap offsets the wrong way round.
5127          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5128          */
5129         if (msr <= 0x1fff) {
5130                 if (type & MSR_TYPE_R &&
5131                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5132                         /* read-low */
5133                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5134
5135                 if (type & MSR_TYPE_W &&
5136                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5137                         /* write-low */
5138                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5139
5140         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5141                 msr &= 0x1fff;
5142                 if (type & MSR_TYPE_R &&
5143                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5144                         /* read-high */
5145                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5146
5147                 if (type & MSR_TYPE_W &&
5148                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5149                         /* write-high */
5150                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5151
5152         }
5153 }
5154
5155 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5156 {
5157         u8 mode = 0;
5158
5159         if (cpu_has_secondary_exec_ctrls() &&
5160             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5161              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5162                 mode |= MSR_BITMAP_MODE_X2APIC;
5163                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5164                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5165         }
5166
5167         if (is_long_mode(vcpu))
5168                 mode |= MSR_BITMAP_MODE_LM;
5169
5170         return mode;
5171 }
5172
5173 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5174
5175 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5176                                          u8 mode)
5177 {
5178         int msr;
5179
5180         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5181                 unsigned word = msr / BITS_PER_LONG;
5182                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5183                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5184         }
5185
5186         if (mode & MSR_BITMAP_MODE_X2APIC) {
5187                 /*
5188                  * TPR reads and writes can be virtualized even if virtual interrupt
5189                  * delivery is not in use.
5190                  */
5191                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5192                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5193                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5194                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5195                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5196                 }
5197         }
5198 }
5199
5200 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5201 {
5202         struct vcpu_vmx *vmx = to_vmx(vcpu);
5203         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5204         u8 mode = vmx_msr_bitmap_mode(vcpu);
5205         u8 changed = mode ^ vmx->msr_bitmap_mode;
5206
5207         if (!changed)
5208                 return;
5209
5210         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5211                                   !(mode & MSR_BITMAP_MODE_LM));
5212
5213         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5214                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5215
5216         vmx->msr_bitmap_mode = mode;
5217 }
5218
5219 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5220 {
5221         return enable_apicv;
5222 }
5223
5224 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5225 {
5226         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5227         gfn_t gfn;
5228
5229         /*
5230          * Don't need to mark the APIC access page dirty; it is never
5231          * written to by the CPU during APIC virtualization.
5232          */
5233
5234         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5235                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5236                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5237         }
5238
5239         if (nested_cpu_has_posted_intr(vmcs12)) {
5240                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5241                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5242         }
5243 }
5244
5245
5246 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5247 {
5248         struct vcpu_vmx *vmx = to_vmx(vcpu);
5249         int max_irr;
5250         void *vapic_page;
5251         u16 status;
5252
5253         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5254                 return;
5255
5256         vmx->nested.pi_pending = false;
5257         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5258                 return;
5259
5260         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5261         if (max_irr != 256) {
5262                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5263                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5264                         vapic_page, &max_irr);
5265                 kunmap(vmx->nested.virtual_apic_page);
5266
5267                 status = vmcs_read16(GUEST_INTR_STATUS);
5268                 if ((u8)max_irr > ((u8)status & 0xff)) {
5269                         status &= ~0xff;
5270                         status |= (u8)max_irr;
5271                         vmcs_write16(GUEST_INTR_STATUS, status);
5272                 }
5273         }
5274
5275         nested_mark_vmcs12_pages_dirty(vcpu);
5276 }
5277
5278 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5279                                                      bool nested)
5280 {
5281 #ifdef CONFIG_SMP
5282         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5283
5284         if (vcpu->mode == IN_GUEST_MODE) {
5285                 /*
5286                  * The vector of interrupt to be delivered to vcpu had
5287                  * been set in PIR before this function.
5288                  *
5289                  * Following cases will be reached in this block, and
5290                  * we always send a notification event in all cases as
5291                  * explained below.
5292                  *
5293                  * Case 1: vcpu keeps in non-root mode. Sending a
5294                  * notification event posts the interrupt to vcpu.
5295                  *
5296                  * Case 2: vcpu exits to root mode and is still
5297                  * runnable. PIR will be synced to vIRR before the
5298                  * next vcpu entry. Sending a notification event in
5299                  * this case has no effect, as vcpu is not in root
5300                  * mode.
5301                  *
5302                  * Case 3: vcpu exits to root mode and is blocked.
5303                  * vcpu_block() has already synced PIR to vIRR and
5304                  * never blocks vcpu if vIRR is not cleared. Therefore,
5305                  * a blocked vcpu here does not wait for any requested
5306                  * interrupts in PIR, and sending a notification event
5307                  * which has no effect is safe here.
5308                  */
5309
5310                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5311                 return true;
5312         }
5313 #endif
5314         return false;
5315 }
5316
5317 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5318                                                 int vector)
5319 {
5320         struct vcpu_vmx *vmx = to_vmx(vcpu);
5321
5322         if (is_guest_mode(vcpu) &&
5323             vector == vmx->nested.posted_intr_nv) {
5324                 /*
5325                  * If a posted intr is not recognized by hardware,
5326                  * we will accomplish it in the next vmentry.
5327                  */
5328                 vmx->nested.pi_pending = true;
5329                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5330                 /* the PIR and ON have been set by L1. */
5331                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5332                         kvm_vcpu_kick(vcpu);
5333                 return 0;
5334         }
5335         return -1;
5336 }
5337 /*
5338  * Send interrupt to vcpu via posted interrupt way.
5339  * 1. If target vcpu is running(non-root mode), send posted interrupt
5340  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5341  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5342  * interrupt from PIR in next vmentry.
5343  */
5344 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5345 {
5346         struct vcpu_vmx *vmx = to_vmx(vcpu);
5347         int r;
5348
5349         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5350         if (!r)
5351                 return;
5352
5353         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5354                 return;
5355
5356         /* If a previous notification has sent the IPI, nothing to do.  */
5357         if (pi_test_and_set_on(&vmx->pi_desc))
5358                 return;
5359
5360         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5361                 kvm_vcpu_kick(vcpu);
5362 }
5363
5364 /*
5365  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5366  * will not change in the lifetime of the guest.
5367  * Note that host-state that does change is set elsewhere. E.g., host-state
5368  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5369  */
5370 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5371 {
5372         u32 low32, high32;
5373         unsigned long tmpl;
5374         struct desc_ptr dt;
5375         unsigned long cr0, cr3, cr4;
5376
5377         cr0 = read_cr0();
5378         WARN_ON(cr0 & X86_CR0_TS);
5379         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5380
5381         /*
5382          * Save the most likely value for this task's CR3 in the VMCS.
5383          * We can't use __get_current_cr3_fast() because we're not atomic.
5384          */
5385         cr3 = __read_cr3();
5386         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5387         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5388
5389         /* Save the most likely value for this task's CR4 in the VMCS. */
5390         cr4 = cr4_read_shadow();
5391         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5392         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5393
5394         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5395 #ifdef CONFIG_X86_64
5396         /*
5397          * Load null selectors, so we can avoid reloading them in
5398          * __vmx_load_host_state(), in case userspace uses the null selectors
5399          * too (the expected case).
5400          */
5401         vmcs_write16(HOST_DS_SELECTOR, 0);
5402         vmcs_write16(HOST_ES_SELECTOR, 0);
5403 #else
5404         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5405         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5406 #endif
5407         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5408         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5409
5410         store_idt(&dt);
5411         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5412         vmx->host_idt_base = dt.address;
5413
5414         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5415
5416         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5417         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5418         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5419         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5420
5421         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5422                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5423                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5424         }
5425 }
5426
5427 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5428 {
5429         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5430         if (enable_ept)
5431                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5432         if (is_guest_mode(&vmx->vcpu))
5433                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5434                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5435         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5436 }
5437
5438 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5439 {
5440         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5441
5442         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5443                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5444
5445         if (!enable_vnmi)
5446                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5447
5448         /* Enable the preemption timer dynamically */
5449         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5450         return pin_based_exec_ctrl;
5451 }
5452
5453 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5454 {
5455         struct vcpu_vmx *vmx = to_vmx(vcpu);
5456
5457         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5458         if (cpu_has_secondary_exec_ctrls()) {
5459                 if (kvm_vcpu_apicv_active(vcpu))
5460                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5461                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5462                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5463                 else
5464                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5465                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5466                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5467         }
5468
5469         if (cpu_has_vmx_msr_bitmap())
5470                 vmx_update_msr_bitmap(vcpu);
5471 }
5472
5473 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5474 {
5475         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5476
5477         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5478                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5479
5480         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5481                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5482 #ifdef CONFIG_X86_64
5483                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5484                                 CPU_BASED_CR8_LOAD_EXITING;
5485 #endif
5486         }
5487         if (!enable_ept)
5488                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5489                                 CPU_BASED_CR3_LOAD_EXITING  |
5490                                 CPU_BASED_INVLPG_EXITING;
5491         return exec_control;
5492 }
5493
5494 static bool vmx_rdrand_supported(void)
5495 {
5496         return vmcs_config.cpu_based_2nd_exec_ctrl &
5497                 SECONDARY_EXEC_RDRAND_EXITING;
5498 }
5499
5500 static bool vmx_rdseed_supported(void)
5501 {
5502         return vmcs_config.cpu_based_2nd_exec_ctrl &
5503                 SECONDARY_EXEC_RDSEED_EXITING;
5504 }
5505
5506 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5507 {
5508         struct kvm_vcpu *vcpu = &vmx->vcpu;
5509
5510         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5511
5512         if (!cpu_need_virtualize_apic_accesses(vcpu))
5513                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5514         if (vmx->vpid == 0)
5515                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5516         if (!enable_ept) {
5517                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5518                 enable_unrestricted_guest = 0;
5519                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5520                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5521         }
5522         if (!enable_unrestricted_guest)
5523                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5524         if (!ple_gap)
5525                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5526         if (!kvm_vcpu_apicv_active(vcpu))
5527                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5528                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5529         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5530
5531         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
5532          * in vmx_set_cr4.  */
5533         exec_control &= ~SECONDARY_EXEC_DESC;
5534
5535         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5536            (handle_vmptrld).
5537            We can NOT enable shadow_vmcs here because we don't have yet
5538            a current VMCS12
5539         */
5540         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5541
5542         if (!enable_pml)
5543                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5544
5545         if (vmx_xsaves_supported()) {
5546                 /* Exposing XSAVES only when XSAVE is exposed */
5547                 bool xsaves_enabled =
5548                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5549                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5550
5551                 if (!xsaves_enabled)
5552                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5553
5554                 if (nested) {
5555                         if (xsaves_enabled)
5556                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5557                                         SECONDARY_EXEC_XSAVES;
5558                         else
5559                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5560                                         ~SECONDARY_EXEC_XSAVES;
5561                 }
5562         }
5563
5564         if (vmx_rdtscp_supported()) {
5565                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5566                 if (!rdtscp_enabled)
5567                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5568
5569                 if (nested) {
5570                         if (rdtscp_enabled)
5571                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5572                                         SECONDARY_EXEC_RDTSCP;
5573                         else
5574                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5575                                         ~SECONDARY_EXEC_RDTSCP;
5576                 }
5577         }
5578
5579         if (vmx_invpcid_supported()) {
5580                 /* Exposing INVPCID only when PCID is exposed */
5581                 bool invpcid_enabled =
5582                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5583                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5584
5585                 if (!invpcid_enabled) {
5586                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5587                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5588                 }
5589
5590                 if (nested) {
5591                         if (invpcid_enabled)
5592                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5593                                         SECONDARY_EXEC_ENABLE_INVPCID;
5594                         else
5595                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5596                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5597                 }
5598         }
5599
5600         if (vmx_rdrand_supported()) {
5601                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5602                 if (rdrand_enabled)
5603                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
5604
5605                 if (nested) {
5606                         if (rdrand_enabled)
5607                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5608                                         SECONDARY_EXEC_RDRAND_EXITING;
5609                         else
5610                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5611                                         ~SECONDARY_EXEC_RDRAND_EXITING;
5612                 }
5613         }
5614
5615         if (vmx_rdseed_supported()) {
5616                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5617                 if (rdseed_enabled)
5618                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
5619
5620                 if (nested) {
5621                         if (rdseed_enabled)
5622                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5623                                         SECONDARY_EXEC_RDSEED_EXITING;
5624                         else
5625                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5626                                         ~SECONDARY_EXEC_RDSEED_EXITING;
5627                 }
5628         }
5629
5630         vmx->secondary_exec_control = exec_control;
5631 }
5632
5633 static void ept_set_mmio_spte_mask(void)
5634 {
5635         /*
5636          * EPT Misconfigurations can be generated if the value of bits 2:0
5637          * of an EPT paging-structure entry is 110b (write/execute).
5638          */
5639         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5640                                    VMX_EPT_MISCONFIG_WX_VALUE);
5641 }
5642
5643 #define VMX_XSS_EXIT_BITMAP 0
5644 /*
5645  * Sets up the vmcs for emulated real mode.
5646  */
5647 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
5648 {
5649 #ifdef CONFIG_X86_64
5650         unsigned long a;
5651 #endif
5652         int i;
5653
5654         if (enable_shadow_vmcs) {
5655                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5656                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5657         }
5658         if (cpu_has_vmx_msr_bitmap())
5659                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
5660
5661         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5662
5663         /* Control */
5664         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5665         vmx->hv_deadline_tsc = -1;
5666
5667         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5668
5669         if (cpu_has_secondary_exec_ctrls()) {
5670                 vmx_compute_secondary_exec_control(vmx);
5671                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5672                              vmx->secondary_exec_control);
5673         }
5674
5675         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5676                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5677                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5678                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5679                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5680
5681                 vmcs_write16(GUEST_INTR_STATUS, 0);
5682
5683                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5684                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5685         }
5686
5687         if (ple_gap) {
5688                 vmcs_write32(PLE_GAP, ple_gap);
5689                 vmx->ple_window = ple_window;
5690                 vmx->ple_window_dirty = true;
5691         }
5692
5693         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5694         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5695         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5696
5697         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5698         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5699         vmx_set_constant_host_state(vmx);
5700 #ifdef CONFIG_X86_64
5701         rdmsrl(MSR_FS_BASE, a);
5702         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5703         rdmsrl(MSR_GS_BASE, a);
5704         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5705 #else
5706         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5707         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5708 #endif
5709
5710         if (cpu_has_vmx_vmfunc())
5711                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5712
5713         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5714         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5715         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5716         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5717         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5718
5719         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5720                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5721
5722         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5723                 u32 index = vmx_msr_index[i];
5724                 u32 data_low, data_high;
5725                 int j = vmx->nmsrs;
5726
5727                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5728                         continue;
5729                 if (wrmsr_safe(index, data_low, data_high) < 0)
5730                         continue;
5731                 vmx->guest_msrs[j].index = i;
5732                 vmx->guest_msrs[j].data = 0;
5733                 vmx->guest_msrs[j].mask = -1ull;
5734                 ++vmx->nmsrs;
5735         }
5736
5737         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
5738                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
5739
5740         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5741
5742         /* 22.2.1, 20.8.1 */
5743         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5744
5745         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5746         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5747
5748         set_cr4_guest_host_mask(vmx);
5749
5750         if (vmx_xsaves_supported())
5751                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5752
5753         if (enable_pml) {
5754                 ASSERT(vmx->pml_pg);
5755                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5756                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5757         }
5758 }
5759
5760 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5761 {
5762         struct vcpu_vmx *vmx = to_vmx(vcpu);
5763         struct msr_data apic_base_msr;
5764         u64 cr0;
5765
5766         vmx->rmode.vm86_active = 0;
5767         vmx->spec_ctrl = 0;
5768
5769         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5770         kvm_set_cr8(vcpu, 0);
5771
5772         if (!init_event) {
5773                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5774                                      MSR_IA32_APICBASE_ENABLE;
5775                 if (kvm_vcpu_is_reset_bsp(vcpu))
5776                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5777                 apic_base_msr.host_initiated = true;
5778                 kvm_set_apic_base(vcpu, &apic_base_msr);
5779         }
5780
5781         vmx_segment_cache_clear(vmx);
5782
5783         seg_setup(VCPU_SREG_CS);
5784         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5785         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5786
5787         seg_setup(VCPU_SREG_DS);
5788         seg_setup(VCPU_SREG_ES);
5789         seg_setup(VCPU_SREG_FS);
5790         seg_setup(VCPU_SREG_GS);
5791         seg_setup(VCPU_SREG_SS);
5792
5793         vmcs_write16(GUEST_TR_SELECTOR, 0);
5794         vmcs_writel(GUEST_TR_BASE, 0);
5795         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5796         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5797
5798         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5799         vmcs_writel(GUEST_LDTR_BASE, 0);
5800         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5801         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5802
5803         if (!init_event) {
5804                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5805                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5806                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5807                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5808         }
5809
5810         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
5811         kvm_rip_write(vcpu, 0xfff0);
5812
5813         vmcs_writel(GUEST_GDTR_BASE, 0);
5814         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5815
5816         vmcs_writel(GUEST_IDTR_BASE, 0);
5817         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5818
5819         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5820         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5821         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5822         if (kvm_mpx_supported())
5823                 vmcs_write64(GUEST_BNDCFGS, 0);
5824
5825         setup_msrs(vmx);
5826
5827         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5828
5829         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5830                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5831                 if (cpu_need_tpr_shadow(vcpu))
5832                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5833                                      __pa(vcpu->arch.apic->regs));
5834                 vmcs_write32(TPR_THRESHOLD, 0);
5835         }
5836
5837         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5838
5839         if (vmx->vpid != 0)
5840                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5841
5842         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5843         vmx->vcpu.arch.cr0 = cr0;
5844         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5845         vmx_set_cr4(vcpu, 0);
5846         vmx_set_efer(vcpu, 0);
5847
5848         update_exception_bitmap(vcpu);
5849
5850         vpid_sync_context(vmx->vpid);
5851 }
5852
5853 /*
5854  * In nested virtualization, check if L1 asked to exit on external interrupts.
5855  * For most existing hypervisors, this will always return true.
5856  */
5857 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5858 {
5859         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5860                 PIN_BASED_EXT_INTR_MASK;
5861 }
5862
5863 /*
5864  * In nested virtualization, check if L1 has set
5865  * VM_EXIT_ACK_INTR_ON_EXIT
5866  */
5867 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5868 {
5869         return get_vmcs12(vcpu)->vm_exit_controls &
5870                 VM_EXIT_ACK_INTR_ON_EXIT;
5871 }
5872
5873 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5874 {
5875         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5876                 PIN_BASED_NMI_EXITING;
5877 }
5878
5879 static void enable_irq_window(struct kvm_vcpu *vcpu)
5880 {
5881         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5882                       CPU_BASED_VIRTUAL_INTR_PENDING);
5883 }
5884
5885 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5886 {
5887         if (!enable_vnmi ||
5888             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5889                 enable_irq_window(vcpu);
5890                 return;
5891         }
5892
5893         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5894                       CPU_BASED_VIRTUAL_NMI_PENDING);
5895 }
5896
5897 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5898 {
5899         struct vcpu_vmx *vmx = to_vmx(vcpu);
5900         uint32_t intr;
5901         int irq = vcpu->arch.interrupt.nr;
5902
5903         trace_kvm_inj_virq(irq);
5904
5905         ++vcpu->stat.irq_injections;
5906         if (vmx->rmode.vm86_active) {
5907                 int inc_eip = 0;
5908                 if (vcpu->arch.interrupt.soft)
5909                         inc_eip = vcpu->arch.event_exit_inst_len;
5910                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5911                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5912                 return;
5913         }
5914         intr = irq | INTR_INFO_VALID_MASK;
5915         if (vcpu->arch.interrupt.soft) {
5916                 intr |= INTR_TYPE_SOFT_INTR;
5917                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5918                              vmx->vcpu.arch.event_exit_inst_len);
5919         } else
5920                 intr |= INTR_TYPE_EXT_INTR;
5921         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5922 }
5923
5924 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5925 {
5926         struct vcpu_vmx *vmx = to_vmx(vcpu);
5927
5928         if (!enable_vnmi) {
5929                 /*
5930                  * Tracking the NMI-blocked state in software is built upon
5931                  * finding the next open IRQ window. This, in turn, depends on
5932                  * well-behaving guests: They have to keep IRQs disabled at
5933                  * least as long as the NMI handler runs. Otherwise we may
5934                  * cause NMI nesting, maybe breaking the guest. But as this is
5935                  * highly unlikely, we can live with the residual risk.
5936                  */
5937                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
5938                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
5939         }
5940
5941         ++vcpu->stat.nmi_injections;
5942         vmx->loaded_vmcs->nmi_known_unmasked = false;
5943
5944         if (vmx->rmode.vm86_active) {
5945                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5946                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5947                 return;
5948         }
5949
5950         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5951                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5952 }
5953
5954 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5955 {
5956         struct vcpu_vmx *vmx = to_vmx(vcpu);
5957         bool masked;
5958
5959         if (!enable_vnmi)
5960                 return vmx->loaded_vmcs->soft_vnmi_blocked;
5961         if (vmx->loaded_vmcs->nmi_known_unmasked)
5962                 return false;
5963         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5964         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5965         return masked;
5966 }
5967
5968 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5969 {
5970         struct vcpu_vmx *vmx = to_vmx(vcpu);
5971
5972         if (!enable_vnmi) {
5973                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
5974                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
5975                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
5976                 }
5977         } else {
5978                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5979                 if (masked)
5980                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5981                                       GUEST_INTR_STATE_NMI);
5982                 else
5983                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5984                                         GUEST_INTR_STATE_NMI);
5985         }
5986 }
5987
5988 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5989 {
5990         if (to_vmx(vcpu)->nested.nested_run_pending)
5991                 return 0;
5992
5993         if (!enable_vnmi &&
5994             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
5995                 return 0;
5996
5997         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5998                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5999                    | GUEST_INTR_STATE_NMI));
6000 }
6001
6002 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6003 {
6004         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6005                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6006                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6007                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6008 }
6009
6010 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6011 {
6012         int ret;
6013
6014         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6015                                     PAGE_SIZE * 3);
6016         if (ret)
6017                 return ret;
6018         kvm->arch.tss_addr = addr;
6019         return init_rmode_tss(kvm);
6020 }
6021
6022 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6023 {
6024         switch (vec) {
6025         case BP_VECTOR:
6026                 /*
6027                  * Update instruction length as we may reinject the exception
6028                  * from user space while in guest debugging mode.
6029                  */
6030                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6031                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6032                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6033                         return false;
6034                 /* fall through */
6035         case DB_VECTOR:
6036                 if (vcpu->guest_debug &
6037                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6038                         return false;
6039                 /* fall through */
6040         case DE_VECTOR:
6041         case OF_VECTOR:
6042         case BR_VECTOR:
6043         case UD_VECTOR:
6044         case DF_VECTOR:
6045         case SS_VECTOR:
6046         case GP_VECTOR:
6047         case MF_VECTOR:
6048                 return true;
6049         break;
6050         }
6051         return false;
6052 }
6053
6054 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6055                                   int vec, u32 err_code)
6056 {
6057         /*
6058          * Instruction with address size override prefix opcode 0x67
6059          * Cause the #SS fault with 0 error code in VM86 mode.
6060          */
6061         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6062                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6063                         if (vcpu->arch.halt_request) {
6064                                 vcpu->arch.halt_request = 0;
6065                                 return kvm_vcpu_halt(vcpu);
6066                         }
6067                         return 1;
6068                 }
6069                 return 0;
6070         }
6071
6072         /*
6073          * Forward all other exceptions that are valid in real mode.
6074          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6075          *        the required debugging infrastructure rework.
6076          */
6077         kvm_queue_exception(vcpu, vec);
6078         return 1;
6079 }
6080
6081 /*
6082  * Trigger machine check on the host. We assume all the MSRs are already set up
6083  * by the CPU and that we still run on the same CPU as the MCE occurred on.
6084  * We pass a fake environment to the machine check handler because we want
6085  * the guest to be always treated like user space, no matter what context
6086  * it used internally.
6087  */
6088 static void kvm_machine_check(void)
6089 {
6090 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6091         struct pt_regs regs = {
6092                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6093                 .flags = X86_EFLAGS_IF,
6094         };
6095
6096         do_machine_check(&regs, 0);
6097 #endif
6098 }
6099
6100 static int handle_machine_check(struct kvm_vcpu *vcpu)
6101 {
6102         /* already handled by vcpu_run */
6103         return 1;
6104 }
6105
6106 static int handle_exception(struct kvm_vcpu *vcpu)
6107 {
6108         struct vcpu_vmx *vmx = to_vmx(vcpu);
6109         struct kvm_run *kvm_run = vcpu->run;
6110         u32 intr_info, ex_no, error_code;
6111         unsigned long cr2, rip, dr6;
6112         u32 vect_info;
6113         enum emulation_result er;
6114
6115         vect_info = vmx->idt_vectoring_info;
6116         intr_info = vmx->exit_intr_info;
6117
6118         if (is_machine_check(intr_info))
6119                 return handle_machine_check(vcpu);
6120
6121         if (is_nmi(intr_info))
6122                 return 1;  /* already handled by vmx_vcpu_run() */
6123
6124         if (is_invalid_opcode(intr_info)) {
6125                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
6126                 if (er == EMULATE_USER_EXIT)
6127                         return 0;
6128                 if (er != EMULATE_DONE)
6129                         kvm_queue_exception(vcpu, UD_VECTOR);
6130                 return 1;
6131         }
6132
6133         error_code = 0;
6134         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6135                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6136
6137         /*
6138          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6139          * MMIO, it is better to report an internal error.
6140          * See the comments in vmx_handle_exit.
6141          */
6142         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6143             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6144                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6145                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6146                 vcpu->run->internal.ndata = 3;
6147                 vcpu->run->internal.data[0] = vect_info;
6148                 vcpu->run->internal.data[1] = intr_info;
6149                 vcpu->run->internal.data[2] = error_code;
6150                 return 0;
6151         }
6152
6153         if (is_page_fault(intr_info)) {
6154                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6155                 /* EPT won't cause page fault directly */
6156                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6157                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6158         }
6159
6160         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6161
6162         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6163                 return handle_rmode_exception(vcpu, ex_no, error_code);
6164
6165         switch (ex_no) {
6166         case AC_VECTOR:
6167                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6168                 return 1;
6169         case DB_VECTOR:
6170                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6171                 if (!(vcpu->guest_debug &
6172                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6173                         vcpu->arch.dr6 &= ~15;
6174                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6175                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
6176                                 skip_emulated_instruction(vcpu);
6177
6178                         kvm_queue_exception(vcpu, DB_VECTOR);
6179                         return 1;
6180                 }
6181                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6182                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6183                 /* fall through */
6184         case BP_VECTOR:
6185                 /*
6186                  * Update instruction length as we may reinject #BP from
6187                  * user space while in guest debugging mode. Reading it for
6188                  * #DB as well causes no harm, it is not used in that case.
6189                  */
6190                 vmx->vcpu.arch.event_exit_inst_len =
6191                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6192                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6193                 rip = kvm_rip_read(vcpu);
6194                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6195                 kvm_run->debug.arch.exception = ex_no;
6196                 break;
6197         default:
6198                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6199                 kvm_run->ex.exception = ex_no;
6200                 kvm_run->ex.error_code = error_code;
6201                 break;
6202         }
6203         return 0;
6204 }
6205
6206 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6207 {
6208         ++vcpu->stat.irq_exits;
6209         return 1;
6210 }
6211
6212 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6213 {
6214         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6215         vcpu->mmio_needed = 0;
6216         return 0;
6217 }
6218
6219 static int handle_io(struct kvm_vcpu *vcpu)
6220 {
6221         unsigned long exit_qualification;
6222         int size, in, string, ret;
6223         unsigned port;
6224
6225         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6226         string = (exit_qualification & 16) != 0;
6227         in = (exit_qualification & 8) != 0;
6228
6229         ++vcpu->stat.io_exits;
6230
6231         if (string || in)
6232                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6233
6234         port = exit_qualification >> 16;
6235         size = (exit_qualification & 7) + 1;
6236
6237         ret = kvm_skip_emulated_instruction(vcpu);
6238
6239         /*
6240          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6241          * KVM_EXIT_DEBUG here.
6242          */
6243         return kvm_fast_pio_out(vcpu, size, port) && ret;
6244 }
6245
6246 static void
6247 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6248 {
6249         /*
6250          * Patch in the VMCALL instruction:
6251          */
6252         hypercall[0] = 0x0f;
6253         hypercall[1] = 0x01;
6254         hypercall[2] = 0xc1;
6255 }
6256
6257 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6258 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6259 {
6260         if (is_guest_mode(vcpu)) {
6261                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6262                 unsigned long orig_val = val;
6263
6264                 /*
6265                  * We get here when L2 changed cr0 in a way that did not change
6266                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6267                  * but did change L0 shadowed bits. So we first calculate the
6268                  * effective cr0 value that L1 would like to write into the
6269                  * hardware. It consists of the L2-owned bits from the new
6270                  * value combined with the L1-owned bits from L1's guest_cr0.
6271                  */
6272                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6273                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6274
6275                 if (!nested_guest_cr0_valid(vcpu, val))
6276                         return 1;
6277
6278                 if (kvm_set_cr0(vcpu, val))
6279                         return 1;
6280                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6281                 return 0;
6282         } else {
6283                 if (to_vmx(vcpu)->nested.vmxon &&
6284                     !nested_host_cr0_valid(vcpu, val))
6285                         return 1;
6286
6287                 return kvm_set_cr0(vcpu, val);
6288         }
6289 }
6290
6291 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6292 {
6293         if (is_guest_mode(vcpu)) {
6294                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6295                 unsigned long orig_val = val;
6296
6297                 /* analogously to handle_set_cr0 */
6298                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6299                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6300                 if (kvm_set_cr4(vcpu, val))
6301                         return 1;
6302                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6303                 return 0;
6304         } else
6305                 return kvm_set_cr4(vcpu, val);
6306 }
6307
6308 static int handle_desc(struct kvm_vcpu *vcpu)
6309 {
6310         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6311         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6312 }
6313
6314 static int handle_cr(struct kvm_vcpu *vcpu)
6315 {
6316         unsigned long exit_qualification, val;
6317         int cr;
6318         int reg;
6319         int err;
6320         int ret;
6321
6322         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6323         cr = exit_qualification & 15;
6324         reg = (exit_qualification >> 8) & 15;
6325         switch ((exit_qualification >> 4) & 3) {
6326         case 0: /* mov to cr */
6327                 val = kvm_register_readl(vcpu, reg);
6328                 trace_kvm_cr_write(cr, val);
6329                 switch (cr) {
6330                 case 0:
6331                         err = handle_set_cr0(vcpu, val);
6332                         return kvm_complete_insn_gp(vcpu, err);
6333                 case 3:
6334                         err = kvm_set_cr3(vcpu, val);
6335                         return kvm_complete_insn_gp(vcpu, err);
6336                 case 4:
6337                         err = handle_set_cr4(vcpu, val);
6338                         return kvm_complete_insn_gp(vcpu, err);
6339                 case 8: {
6340                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6341                                 u8 cr8 = (u8)val;
6342                                 err = kvm_set_cr8(vcpu, cr8);
6343                                 ret = kvm_complete_insn_gp(vcpu, err);
6344                                 if (lapic_in_kernel(vcpu))
6345                                         return ret;
6346                                 if (cr8_prev <= cr8)
6347                                         return ret;
6348                                 /*
6349                                  * TODO: we might be squashing a
6350                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6351                                  * KVM_EXIT_DEBUG here.
6352                                  */
6353                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6354                                 return 0;
6355                         }
6356                 }
6357                 break;
6358         case 2: /* clts */
6359                 WARN_ONCE(1, "Guest should always own CR0.TS");
6360                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6361                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6362                 return kvm_skip_emulated_instruction(vcpu);
6363         case 1: /*mov from cr*/
6364                 switch (cr) {
6365                 case 3:
6366                         val = kvm_read_cr3(vcpu);
6367                         kvm_register_write(vcpu, reg, val);
6368                         trace_kvm_cr_read(cr, val);
6369                         return kvm_skip_emulated_instruction(vcpu);
6370                 case 8:
6371                         val = kvm_get_cr8(vcpu);
6372                         kvm_register_write(vcpu, reg, val);
6373                         trace_kvm_cr_read(cr, val);
6374                         return kvm_skip_emulated_instruction(vcpu);
6375                 }
6376                 break;
6377         case 3: /* lmsw */
6378                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6379                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6380                 kvm_lmsw(vcpu, val);
6381
6382                 return kvm_skip_emulated_instruction(vcpu);
6383         default:
6384                 break;
6385         }
6386         vcpu->run->exit_reason = 0;
6387         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6388                (int)(exit_qualification >> 4) & 3, cr);
6389         return 0;
6390 }
6391
6392 static int handle_dr(struct kvm_vcpu *vcpu)
6393 {
6394         unsigned long exit_qualification;
6395         int dr, dr7, reg;
6396
6397         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6398         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6399
6400         /* First, if DR does not exist, trigger UD */
6401         if (!kvm_require_dr(vcpu, dr))
6402                 return 1;
6403
6404         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6405         if (!kvm_require_cpl(vcpu, 0))
6406                 return 1;
6407         dr7 = vmcs_readl(GUEST_DR7);
6408         if (dr7 & DR7_GD) {
6409                 /*
6410                  * As the vm-exit takes precedence over the debug trap, we
6411                  * need to emulate the latter, either for the host or the
6412                  * guest debugging itself.
6413                  */
6414                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6415                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6416                         vcpu->run->debug.arch.dr7 = dr7;
6417                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6418                         vcpu->run->debug.arch.exception = DB_VECTOR;
6419                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6420                         return 0;
6421                 } else {
6422                         vcpu->arch.dr6 &= ~15;
6423                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6424                         kvm_queue_exception(vcpu, DB_VECTOR);
6425                         return 1;
6426                 }
6427         }
6428
6429         if (vcpu->guest_debug == 0) {
6430                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6431                                 CPU_BASED_MOV_DR_EXITING);
6432
6433                 /*
6434                  * No more DR vmexits; force a reload of the debug registers
6435                  * and reenter on this instruction.  The next vmexit will
6436                  * retrieve the full state of the debug registers.
6437                  */
6438                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6439                 return 1;
6440         }
6441
6442         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6443         if (exit_qualification & TYPE_MOV_FROM_DR) {
6444                 unsigned long val;
6445
6446                 if (kvm_get_dr(vcpu, dr, &val))
6447                         return 1;
6448                 kvm_register_write(vcpu, reg, val);
6449         } else
6450                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6451                         return 1;
6452
6453         return kvm_skip_emulated_instruction(vcpu);
6454 }
6455
6456 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6457 {
6458         return vcpu->arch.dr6;
6459 }
6460
6461 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6462 {
6463 }
6464
6465 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6466 {
6467         get_debugreg(vcpu->arch.db[0], 0);
6468         get_debugreg(vcpu->arch.db[1], 1);
6469         get_debugreg(vcpu->arch.db[2], 2);
6470         get_debugreg(vcpu->arch.db[3], 3);
6471         get_debugreg(vcpu->arch.dr6, 6);
6472         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6473
6474         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6475         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6476 }
6477
6478 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6479 {
6480         vmcs_writel(GUEST_DR7, val);
6481 }
6482
6483 static int handle_cpuid(struct kvm_vcpu *vcpu)
6484 {
6485         return kvm_emulate_cpuid(vcpu);
6486 }
6487
6488 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6489 {
6490         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6491         struct msr_data msr_info;
6492
6493         msr_info.index = ecx;
6494         msr_info.host_initiated = false;
6495         if (vmx_get_msr(vcpu, &msr_info)) {
6496                 trace_kvm_msr_read_ex(ecx);
6497                 kvm_inject_gp(vcpu, 0);
6498                 return 1;
6499         }
6500
6501         trace_kvm_msr_read(ecx, msr_info.data);
6502
6503         /* FIXME: handling of bits 32:63 of rax, rdx */
6504         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6505         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6506         return kvm_skip_emulated_instruction(vcpu);
6507 }
6508
6509 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6510 {
6511         struct msr_data msr;
6512         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6513         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6514                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6515
6516         msr.data = data;
6517         msr.index = ecx;
6518         msr.host_initiated = false;
6519         if (kvm_set_msr(vcpu, &msr) != 0) {
6520                 trace_kvm_msr_write_ex(ecx, data);
6521                 kvm_inject_gp(vcpu, 0);
6522                 return 1;
6523         }
6524
6525         trace_kvm_msr_write(ecx, data);
6526         return kvm_skip_emulated_instruction(vcpu);
6527 }
6528
6529 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6530 {
6531         kvm_apic_update_ppr(vcpu);
6532         return 1;
6533 }
6534
6535 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6536 {
6537         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6538                         CPU_BASED_VIRTUAL_INTR_PENDING);
6539
6540         kvm_make_request(KVM_REQ_EVENT, vcpu);
6541
6542         ++vcpu->stat.irq_window_exits;
6543         return 1;
6544 }
6545
6546 static int handle_halt(struct kvm_vcpu *vcpu)
6547 {
6548         return kvm_emulate_halt(vcpu);
6549 }
6550
6551 static int handle_vmcall(struct kvm_vcpu *vcpu)
6552 {
6553         return kvm_emulate_hypercall(vcpu);
6554 }
6555
6556 static int handle_invd(struct kvm_vcpu *vcpu)
6557 {
6558         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6559 }
6560
6561 static int handle_invlpg(struct kvm_vcpu *vcpu)
6562 {
6563         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6564
6565         kvm_mmu_invlpg(vcpu, exit_qualification);
6566         return kvm_skip_emulated_instruction(vcpu);
6567 }
6568
6569 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6570 {
6571         int err;
6572
6573         err = kvm_rdpmc(vcpu);
6574         return kvm_complete_insn_gp(vcpu, err);
6575 }
6576
6577 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6578 {
6579         return kvm_emulate_wbinvd(vcpu);
6580 }
6581
6582 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6583 {
6584         u64 new_bv = kvm_read_edx_eax(vcpu);
6585         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6586
6587         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6588                 return kvm_skip_emulated_instruction(vcpu);
6589         return 1;
6590 }
6591
6592 static int handle_xsaves(struct kvm_vcpu *vcpu)
6593 {
6594         kvm_skip_emulated_instruction(vcpu);
6595         WARN(1, "this should never happen\n");
6596         return 1;
6597 }
6598
6599 static int handle_xrstors(struct kvm_vcpu *vcpu)
6600 {
6601         kvm_skip_emulated_instruction(vcpu);
6602         WARN(1, "this should never happen\n");
6603         return 1;
6604 }
6605
6606 static int handle_apic_access(struct kvm_vcpu *vcpu)
6607 {
6608         if (likely(fasteoi)) {
6609                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6610                 int access_type, offset;
6611
6612                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6613                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6614                 /*
6615                  * Sane guest uses MOV to write EOI, with written value
6616                  * not cared. So make a short-circuit here by avoiding
6617                  * heavy instruction emulation.
6618                  */
6619                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6620                     (offset == APIC_EOI)) {
6621                         kvm_lapic_set_eoi(vcpu);
6622                         return kvm_skip_emulated_instruction(vcpu);
6623                 }
6624         }
6625         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6626 }
6627
6628 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6629 {
6630         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6631         int vector = exit_qualification & 0xff;
6632
6633         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6634         kvm_apic_set_eoi_accelerated(vcpu, vector);
6635         return 1;
6636 }
6637
6638 static int handle_apic_write(struct kvm_vcpu *vcpu)
6639 {
6640         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6641         u32 offset = exit_qualification & 0xfff;
6642
6643         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6644         kvm_apic_write_nodecode(vcpu, offset);
6645         return 1;
6646 }
6647
6648 static int handle_task_switch(struct kvm_vcpu *vcpu)
6649 {
6650         struct vcpu_vmx *vmx = to_vmx(vcpu);
6651         unsigned long exit_qualification;
6652         bool has_error_code = false;
6653         u32 error_code = 0;
6654         u16 tss_selector;
6655         int reason, type, idt_v, idt_index;
6656
6657         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6658         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6659         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6660
6661         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6662
6663         reason = (u32)exit_qualification >> 30;
6664         if (reason == TASK_SWITCH_GATE && idt_v) {
6665                 switch (type) {
6666                 case INTR_TYPE_NMI_INTR:
6667                         vcpu->arch.nmi_injected = false;
6668                         vmx_set_nmi_mask(vcpu, true);
6669                         break;
6670                 case INTR_TYPE_EXT_INTR:
6671                 case INTR_TYPE_SOFT_INTR:
6672                         kvm_clear_interrupt_queue(vcpu);
6673                         break;
6674                 case INTR_TYPE_HARD_EXCEPTION:
6675                         if (vmx->idt_vectoring_info &
6676                             VECTORING_INFO_DELIVER_CODE_MASK) {
6677                                 has_error_code = true;
6678                                 error_code =
6679                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6680                         }
6681                         /* fall through */
6682                 case INTR_TYPE_SOFT_EXCEPTION:
6683                         kvm_clear_exception_queue(vcpu);
6684                         break;
6685                 default:
6686                         break;
6687                 }
6688         }
6689         tss_selector = exit_qualification;
6690
6691         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6692                        type != INTR_TYPE_EXT_INTR &&
6693                        type != INTR_TYPE_NMI_INTR))
6694                 skip_emulated_instruction(vcpu);
6695
6696         if (kvm_task_switch(vcpu, tss_selector,
6697                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6698                             has_error_code, error_code) == EMULATE_FAIL) {
6699                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6700                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6701                 vcpu->run->internal.ndata = 0;
6702                 return 0;
6703         }
6704
6705         /*
6706          * TODO: What about debug traps on tss switch?
6707          *       Are we supposed to inject them and update dr6?
6708          */
6709
6710         return 1;
6711 }
6712
6713 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6714 {
6715         unsigned long exit_qualification;
6716         gpa_t gpa;
6717         u64 error_code;
6718
6719         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6720
6721         /*
6722          * EPT violation happened while executing iret from NMI,
6723          * "blocked by NMI" bit has to be set before next VM entry.
6724          * There are errata that may cause this bit to not be set:
6725          * AAK134, BY25.
6726          */
6727         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6728                         enable_vnmi &&
6729                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6730                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6731
6732         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6733         trace_kvm_page_fault(gpa, exit_qualification);
6734
6735         /* Is it a read fault? */
6736         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6737                      ? PFERR_USER_MASK : 0;
6738         /* Is it a write fault? */
6739         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6740                       ? PFERR_WRITE_MASK : 0;
6741         /* Is it a fetch fault? */
6742         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6743                       ? PFERR_FETCH_MASK : 0;
6744         /* ept page table entry is present? */
6745         error_code |= (exit_qualification &
6746                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6747                         EPT_VIOLATION_EXECUTABLE))
6748                       ? PFERR_PRESENT_MASK : 0;
6749
6750         error_code |= (exit_qualification & 0x100) != 0 ?
6751                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6752
6753         vcpu->arch.exit_qualification = exit_qualification;
6754         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6755 }
6756
6757 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6758 {
6759         int ret;
6760         gpa_t gpa;
6761
6762         /*
6763          * A nested guest cannot optimize MMIO vmexits, because we have an
6764          * nGPA here instead of the required GPA.
6765          */
6766         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6767         if (!is_guest_mode(vcpu) &&
6768             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6769                 trace_kvm_fast_mmio(gpa);
6770                 /*
6771                  * Doing kvm_skip_emulated_instruction() depends on undefined
6772                  * behavior: Intel's manual doesn't mandate
6773                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
6774                  * occurs and while on real hardware it was observed to be set,
6775                  * other hypervisors (namely Hyper-V) don't set it, we end up
6776                  * advancing IP with some random value. Disable fast mmio when
6777                  * running nested and keep it for real hardware in hope that
6778                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
6779                  */
6780                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
6781                         return kvm_skip_emulated_instruction(vcpu);
6782                 else
6783                         return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
6784                                                        NULL, 0) == EMULATE_DONE;
6785         }
6786
6787         ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6788         if (ret >= 0)
6789                 return ret;
6790
6791         /* It is the real ept misconfig */
6792         WARN_ON(1);
6793
6794         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6795         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6796
6797         return 0;
6798 }
6799
6800 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6801 {
6802         WARN_ON_ONCE(!enable_vnmi);
6803         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6804                         CPU_BASED_VIRTUAL_NMI_PENDING);
6805         ++vcpu->stat.nmi_window_exits;
6806         kvm_make_request(KVM_REQ_EVENT, vcpu);
6807
6808         return 1;
6809 }
6810
6811 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6812 {
6813         struct vcpu_vmx *vmx = to_vmx(vcpu);
6814         enum emulation_result err = EMULATE_DONE;
6815         int ret = 1;
6816         u32 cpu_exec_ctrl;
6817         bool intr_window_requested;
6818         unsigned count = 130;
6819
6820         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6821         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6822
6823         while (vmx->emulation_required && count-- != 0) {
6824                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6825                         return handle_interrupt_window(&vmx->vcpu);
6826
6827                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6828                         return 1;
6829
6830                 err = emulate_instruction(vcpu, 0);
6831
6832                 if (err == EMULATE_USER_EXIT) {
6833                         ++vcpu->stat.mmio_exits;
6834                         ret = 0;
6835                         goto out;
6836                 }
6837
6838                 if (err != EMULATE_DONE) {
6839                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6840                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6841                         vcpu->run->internal.ndata = 0;
6842                         return 0;
6843                 }
6844
6845                 if (vcpu->arch.halt_request) {
6846                         vcpu->arch.halt_request = 0;
6847                         ret = kvm_vcpu_halt(vcpu);
6848                         goto out;
6849                 }
6850
6851                 if (signal_pending(current))
6852                         goto out;
6853                 if (need_resched())
6854                         schedule();
6855         }
6856
6857 out:
6858         return ret;
6859 }
6860
6861 static int __grow_ple_window(int val)
6862 {
6863         if (ple_window_grow < 1)
6864                 return ple_window;
6865
6866         val = min(val, ple_window_actual_max);
6867
6868         if (ple_window_grow < ple_window)
6869                 val *= ple_window_grow;
6870         else
6871                 val += ple_window_grow;
6872
6873         return val;
6874 }
6875
6876 static int __shrink_ple_window(int val, int modifier, int minimum)
6877 {
6878         if (modifier < 1)
6879                 return ple_window;
6880
6881         if (modifier < ple_window)
6882                 val /= modifier;
6883         else
6884                 val -= modifier;
6885
6886         return max(val, minimum);
6887 }
6888
6889 static void grow_ple_window(struct kvm_vcpu *vcpu)
6890 {
6891         struct vcpu_vmx *vmx = to_vmx(vcpu);
6892         int old = vmx->ple_window;
6893
6894         vmx->ple_window = __grow_ple_window(old);
6895
6896         if (vmx->ple_window != old)
6897                 vmx->ple_window_dirty = true;
6898
6899         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6900 }
6901
6902 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6903 {
6904         struct vcpu_vmx *vmx = to_vmx(vcpu);
6905         int old = vmx->ple_window;
6906
6907         vmx->ple_window = __shrink_ple_window(old,
6908                                               ple_window_shrink, ple_window);
6909
6910         if (vmx->ple_window != old)
6911                 vmx->ple_window_dirty = true;
6912
6913         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6914 }
6915
6916 /*
6917  * ple_window_actual_max is computed to be one grow_ple_window() below
6918  * ple_window_max. (See __grow_ple_window for the reason.)
6919  * This prevents overflows, because ple_window_max is int.
6920  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6921  * this process.
6922  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6923  */
6924 static void update_ple_window_actual_max(void)
6925 {
6926         ple_window_actual_max =
6927                         __shrink_ple_window(max(ple_window_max, ple_window),
6928                                             ple_window_grow, INT_MIN);
6929 }
6930
6931 /*
6932  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6933  */
6934 static void wakeup_handler(void)
6935 {
6936         struct kvm_vcpu *vcpu;
6937         int cpu = smp_processor_id();
6938
6939         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6940         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6941                         blocked_vcpu_list) {
6942                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6943
6944                 if (pi_test_on(pi_desc) == 1)
6945                         kvm_vcpu_kick(vcpu);
6946         }
6947         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6948 }
6949
6950 void vmx_enable_tdp(void)
6951 {
6952         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6953                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6954                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6955                 0ull, VMX_EPT_EXECUTABLE_MASK,
6956                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6957                 VMX_EPT_RWX_MASK, 0ull);
6958
6959         ept_set_mmio_spte_mask();
6960         kvm_enable_tdp();
6961 }
6962
6963 static __init int hardware_setup(void)
6964 {
6965         int r = -ENOMEM, i;
6966
6967         rdmsrl_safe(MSR_EFER, &host_efer);
6968
6969         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6970                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6971
6972         for (i = 0; i < VMX_BITMAP_NR; i++) {
6973                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6974                 if (!vmx_bitmap[i])
6975                         goto out;
6976         }
6977
6978         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6979         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6980
6981         if (setup_vmcs_config(&vmcs_config) < 0) {
6982                 r = -EIO;
6983                 goto out;
6984         }
6985
6986         if (boot_cpu_has(X86_FEATURE_NX))
6987                 kvm_enable_efer_bits(EFER_NX);
6988
6989         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6990                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6991                 enable_vpid = 0;
6992
6993         if (!cpu_has_vmx_ept() ||
6994             !cpu_has_vmx_ept_4levels() ||
6995             !cpu_has_vmx_ept_mt_wb() ||
6996             !cpu_has_vmx_invept_global())
6997                 enable_ept = 0;
6998
6999         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7000                 enable_ept_ad_bits = 0;
7001
7002         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7003                 enable_unrestricted_guest = 0;
7004
7005         if (!cpu_has_vmx_flexpriority())
7006                 flexpriority_enabled = 0;
7007
7008         if (!cpu_has_virtual_nmis())
7009                 enable_vnmi = 0;
7010
7011         /*
7012          * set_apic_access_page_addr() is used to reload apic access
7013          * page upon invalidation.  No need to do anything if not
7014          * using the APIC_ACCESS_ADDR VMCS field.
7015          */
7016         if (!flexpriority_enabled)
7017                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7018
7019         if (!cpu_has_vmx_tpr_shadow())
7020                 kvm_x86_ops->update_cr8_intercept = NULL;
7021
7022         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7023                 kvm_disable_largepages();
7024
7025         if (!cpu_has_vmx_ple()) {
7026                 ple_gap = 0;
7027                 ple_window = 0;
7028                 ple_window_grow = 0;
7029                 ple_window_max = 0;
7030                 ple_window_shrink = 0;
7031         }
7032
7033         if (!cpu_has_vmx_apicv()) {
7034                 enable_apicv = 0;
7035                 kvm_x86_ops->sync_pir_to_irr = NULL;
7036         }
7037
7038         if (cpu_has_vmx_tsc_scaling()) {
7039                 kvm_has_tsc_control = true;
7040                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7041                 kvm_tsc_scaling_ratio_frac_bits = 48;
7042         }
7043
7044         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7045
7046         if (enable_ept)
7047                 vmx_enable_tdp();
7048         else
7049                 kvm_disable_tdp();
7050
7051         update_ple_window_actual_max();
7052
7053         /*
7054          * Only enable PML when hardware supports PML feature, and both EPT
7055          * and EPT A/D bit features are enabled -- PML depends on them to work.
7056          */
7057         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7058                 enable_pml = 0;
7059
7060         if (!enable_pml) {
7061                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7062                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7063                 kvm_x86_ops->flush_log_dirty = NULL;
7064                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7065         }
7066
7067         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7068                 u64 vmx_msr;
7069
7070                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7071                 cpu_preemption_timer_multi =
7072                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7073         } else {
7074                 kvm_x86_ops->set_hv_timer = NULL;
7075                 kvm_x86_ops->cancel_hv_timer = NULL;
7076         }
7077
7078         if (!cpu_has_vmx_shadow_vmcs())
7079                 enable_shadow_vmcs = 0;
7080         if (enable_shadow_vmcs)
7081                 init_vmcs_shadow_fields();
7082
7083         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7084
7085         kvm_mce_cap_supported |= MCG_LMCE_P;
7086
7087         return alloc_kvm_area();
7088
7089 out:
7090         for (i = 0; i < VMX_BITMAP_NR; i++)
7091                 free_page((unsigned long)vmx_bitmap[i]);
7092
7093     return r;
7094 }
7095
7096 static __exit void hardware_unsetup(void)
7097 {
7098         int i;
7099
7100         for (i = 0; i < VMX_BITMAP_NR; i++)
7101                 free_page((unsigned long)vmx_bitmap[i]);
7102
7103         free_kvm_area();
7104 }
7105
7106 /*
7107  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7108  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7109  */
7110 static int handle_pause(struct kvm_vcpu *vcpu)
7111 {
7112         if (ple_gap)
7113                 grow_ple_window(vcpu);
7114
7115         /*
7116          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7117          * VM-execution control is ignored if CPL > 0. OTOH, KVM
7118          * never set PAUSE_EXITING and just set PLE if supported,
7119          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7120          */
7121         kvm_vcpu_on_spin(vcpu, true);
7122         return kvm_skip_emulated_instruction(vcpu);
7123 }
7124
7125 static int handle_nop(struct kvm_vcpu *vcpu)
7126 {
7127         return kvm_skip_emulated_instruction(vcpu);
7128 }
7129
7130 static int handle_mwait(struct kvm_vcpu *vcpu)
7131 {
7132         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7133         return handle_nop(vcpu);
7134 }
7135
7136 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7137 {
7138         kvm_queue_exception(vcpu, UD_VECTOR);
7139         return 1;
7140 }
7141
7142 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7143 {
7144         return 1;
7145 }
7146
7147 static int handle_monitor(struct kvm_vcpu *vcpu)
7148 {
7149         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7150         return handle_nop(vcpu);
7151 }
7152
7153 /*
7154  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7155  * set the success or error code of an emulated VMX instruction, as specified
7156  * by Vol 2B, VMX Instruction Reference, "Conventions".
7157  */
7158 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7159 {
7160         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7161                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7162                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7163 }
7164
7165 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7166 {
7167         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7168                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7169                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7170                         | X86_EFLAGS_CF);
7171 }
7172
7173 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7174                                         u32 vm_instruction_error)
7175 {
7176         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7177                 /*
7178                  * failValid writes the error number to the current VMCS, which
7179                  * can't be done there isn't a current VMCS.
7180                  */
7181                 nested_vmx_failInvalid(vcpu);
7182                 return;
7183         }
7184         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7185                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7186                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7187                         | X86_EFLAGS_ZF);
7188         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7189         /*
7190          * We don't need to force a shadow sync because
7191          * VM_INSTRUCTION_ERROR is not shadowed
7192          */
7193 }
7194
7195 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7196 {
7197         /* TODO: not to reset guest simply here. */
7198         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7199         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7200 }
7201
7202 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7203 {
7204         struct vcpu_vmx *vmx =
7205                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7206
7207         vmx->nested.preemption_timer_expired = true;
7208         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7209         kvm_vcpu_kick(&vmx->vcpu);
7210
7211         return HRTIMER_NORESTART;
7212 }
7213
7214 /*
7215  * Decode the memory-address operand of a vmx instruction, as recorded on an
7216  * exit caused by such an instruction (run by a guest hypervisor).
7217  * On success, returns 0. When the operand is invalid, returns 1 and throws
7218  * #UD or #GP.
7219  */
7220 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7221                                  unsigned long exit_qualification,
7222                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7223 {
7224         gva_t off;
7225         bool exn;
7226         struct kvm_segment s;
7227
7228         /*
7229          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7230          * Execution", on an exit, vmx_instruction_info holds most of the
7231          * addressing components of the operand. Only the displacement part
7232          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7233          * For how an actual address is calculated from all these components,
7234          * refer to Vol. 1, "Operand Addressing".
7235          */
7236         int  scaling = vmx_instruction_info & 3;
7237         int  addr_size = (vmx_instruction_info >> 7) & 7;
7238         bool is_reg = vmx_instruction_info & (1u << 10);
7239         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7240         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7241         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7242         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7243         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7244
7245         if (is_reg) {
7246                 kvm_queue_exception(vcpu, UD_VECTOR);
7247                 return 1;
7248         }
7249
7250         /* Addr = segment_base + offset */
7251         /* offset = base + [index * scale] + displacement */
7252         off = exit_qualification; /* holds the displacement */
7253         if (base_is_valid)
7254                 off += kvm_register_read(vcpu, base_reg);
7255         if (index_is_valid)
7256                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7257         vmx_get_segment(vcpu, &s, seg_reg);
7258         *ret = s.base + off;
7259
7260         if (addr_size == 1) /* 32 bit */
7261                 *ret &= 0xffffffff;
7262
7263         /* Checks for #GP/#SS exceptions. */
7264         exn = false;
7265         if (is_long_mode(vcpu)) {
7266                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7267                  * non-canonical form. This is the only check on the memory
7268                  * destination for long mode!
7269                  */
7270                 exn = is_noncanonical_address(*ret, vcpu);
7271         } else if (is_protmode(vcpu)) {
7272                 /* Protected mode: apply checks for segment validity in the
7273                  * following order:
7274                  * - segment type check (#GP(0) may be thrown)
7275                  * - usability check (#GP(0)/#SS(0))
7276                  * - limit check (#GP(0)/#SS(0))
7277                  */
7278                 if (wr)
7279                         /* #GP(0) if the destination operand is located in a
7280                          * read-only data segment or any code segment.
7281                          */
7282                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7283                 else
7284                         /* #GP(0) if the source operand is located in an
7285                          * execute-only code segment
7286                          */
7287                         exn = ((s.type & 0xa) == 8);
7288                 if (exn) {
7289                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7290                         return 1;
7291                 }
7292                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7293                  */
7294                 exn = (s.unusable != 0);
7295                 /* Protected mode: #GP(0)/#SS(0) if the memory
7296                  * operand is outside the segment limit.
7297                  */
7298                 exn = exn || (off + sizeof(u64) > s.limit);
7299         }
7300         if (exn) {
7301                 kvm_queue_exception_e(vcpu,
7302                                       seg_reg == VCPU_SREG_SS ?
7303                                                 SS_VECTOR : GP_VECTOR,
7304                                       0);
7305                 return 1;
7306         }
7307
7308         return 0;
7309 }
7310
7311 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7312 {
7313         gva_t gva;
7314         struct x86_exception e;
7315
7316         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7317                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7318                 return 1;
7319
7320         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7321                                 sizeof(*vmpointer), &e)) {
7322                 kvm_inject_page_fault(vcpu, &e);
7323                 return 1;
7324         }
7325
7326         return 0;
7327 }
7328
7329 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7330 {
7331         struct vcpu_vmx *vmx = to_vmx(vcpu);
7332         struct vmcs *shadow_vmcs;
7333         int r;
7334
7335         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7336         if (r < 0)
7337                 goto out_vmcs02;
7338
7339         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7340         if (!vmx->nested.cached_vmcs12)
7341                 goto out_cached_vmcs12;
7342
7343         if (enable_shadow_vmcs) {
7344                 shadow_vmcs = alloc_vmcs();
7345                 if (!shadow_vmcs)
7346                         goto out_shadow_vmcs;
7347                 /* mark vmcs as shadow */
7348                 shadow_vmcs->revision_id |= (1u << 31);
7349                 /* init shadow vmcs */
7350                 vmcs_clear(shadow_vmcs);
7351                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7352         }
7353
7354         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7355                      HRTIMER_MODE_REL_PINNED);
7356         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7357
7358         vmx->nested.vmxon = true;
7359         return 0;
7360
7361 out_shadow_vmcs:
7362         kfree(vmx->nested.cached_vmcs12);
7363
7364 out_cached_vmcs12:
7365         free_loaded_vmcs(&vmx->nested.vmcs02);
7366
7367 out_vmcs02:
7368         return -ENOMEM;
7369 }
7370
7371 /*
7372  * Emulate the VMXON instruction.
7373  * Currently, we just remember that VMX is active, and do not save or even
7374  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7375  * do not currently need to store anything in that guest-allocated memory
7376  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7377  * argument is different from the VMXON pointer (which the spec says they do).
7378  */
7379 static int handle_vmon(struct kvm_vcpu *vcpu)
7380 {
7381         int ret;
7382         gpa_t vmptr;
7383         struct page *page;
7384         struct vcpu_vmx *vmx = to_vmx(vcpu);
7385         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7386                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7387
7388         /*
7389          * The Intel VMX Instruction Reference lists a bunch of bits that are
7390          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7391          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7392          * Otherwise, we should fail with #UD.  But most faulting conditions
7393          * have already been checked by hardware, prior to the VM-exit for
7394          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7395          * that bit set to 1 in non-root mode.
7396          */
7397         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7398                 kvm_queue_exception(vcpu, UD_VECTOR);
7399                 return 1;
7400         }
7401
7402         if (vmx->nested.vmxon) {
7403                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7404                 return kvm_skip_emulated_instruction(vcpu);
7405         }
7406
7407         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7408                         != VMXON_NEEDED_FEATURES) {
7409                 kvm_inject_gp(vcpu, 0);
7410                 return 1;
7411         }
7412
7413         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7414                 return 1;
7415
7416         /*
7417          * SDM 3: 24.11.5
7418          * The first 4 bytes of VMXON region contain the supported
7419          * VMCS revision identifier
7420          *
7421          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7422          * which replaces physical address width with 32
7423          */
7424         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7425                 nested_vmx_failInvalid(vcpu);
7426                 return kvm_skip_emulated_instruction(vcpu);
7427         }
7428
7429         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7430         if (is_error_page(page)) {
7431                 nested_vmx_failInvalid(vcpu);
7432                 return kvm_skip_emulated_instruction(vcpu);
7433         }
7434         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7435                 kunmap(page);
7436                 kvm_release_page_clean(page);
7437                 nested_vmx_failInvalid(vcpu);
7438                 return kvm_skip_emulated_instruction(vcpu);
7439         }
7440         kunmap(page);
7441         kvm_release_page_clean(page);
7442
7443         vmx->nested.vmxon_ptr = vmptr;
7444         ret = enter_vmx_operation(vcpu);
7445         if (ret)
7446                 return ret;
7447
7448         nested_vmx_succeed(vcpu);
7449         return kvm_skip_emulated_instruction(vcpu);
7450 }
7451
7452 /*
7453  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7454  * for running VMX instructions (except VMXON, whose prerequisites are
7455  * slightly different). It also specifies what exception to inject otherwise.
7456  * Note that many of these exceptions have priority over VM exits, so they
7457  * don't have to be checked again here.
7458  */
7459 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7460 {
7461         if (!to_vmx(vcpu)->nested.vmxon) {
7462                 kvm_queue_exception(vcpu, UD_VECTOR);
7463                 return 0;
7464         }
7465         return 1;
7466 }
7467
7468 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7469 {
7470         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7471         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7472 }
7473
7474 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7475 {
7476         if (vmx->nested.current_vmptr == -1ull)
7477                 return;
7478
7479         if (enable_shadow_vmcs) {
7480                 /* copy to memory all shadowed fields in case
7481                    they were modified */
7482                 copy_shadow_to_vmcs12(vmx);
7483                 vmx->nested.sync_shadow_vmcs = false;
7484                 vmx_disable_shadow_vmcs(vmx);
7485         }
7486         vmx->nested.posted_intr_nv = -1;
7487
7488         /* Flush VMCS12 to guest memory */
7489         kvm_vcpu_write_guest_page(&vmx->vcpu,
7490                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7491                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7492
7493         vmx->nested.current_vmptr = -1ull;
7494 }
7495
7496 /*
7497  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7498  * just stops using VMX.
7499  */
7500 static void free_nested(struct vcpu_vmx *vmx)
7501 {
7502         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
7503                 return;
7504
7505         vmx->nested.vmxon = false;
7506         vmx->nested.smm.vmxon = false;
7507         free_vpid(vmx->nested.vpid02);
7508         vmx->nested.posted_intr_nv = -1;
7509         vmx->nested.current_vmptr = -1ull;
7510         if (enable_shadow_vmcs) {
7511                 vmx_disable_shadow_vmcs(vmx);
7512                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7513                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7514                 vmx->vmcs01.shadow_vmcs = NULL;
7515         }
7516         kfree(vmx->nested.cached_vmcs12);
7517         /* Unpin physical memory we referred to in the vmcs02 */
7518         if (vmx->nested.apic_access_page) {
7519                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7520                 vmx->nested.apic_access_page = NULL;
7521         }
7522         if (vmx->nested.virtual_apic_page) {
7523                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7524                 vmx->nested.virtual_apic_page = NULL;
7525         }
7526         if (vmx->nested.pi_desc_page) {
7527                 kunmap(vmx->nested.pi_desc_page);
7528                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7529                 vmx->nested.pi_desc_page = NULL;
7530                 vmx->nested.pi_desc = NULL;
7531         }
7532
7533         free_loaded_vmcs(&vmx->nested.vmcs02);
7534 }
7535
7536 /* Emulate the VMXOFF instruction */
7537 static int handle_vmoff(struct kvm_vcpu *vcpu)
7538 {
7539         if (!nested_vmx_check_permission(vcpu))
7540                 return 1;
7541         free_nested(to_vmx(vcpu));
7542         nested_vmx_succeed(vcpu);
7543         return kvm_skip_emulated_instruction(vcpu);
7544 }
7545
7546 /* Emulate the VMCLEAR instruction */
7547 static int handle_vmclear(struct kvm_vcpu *vcpu)
7548 {
7549         struct vcpu_vmx *vmx = to_vmx(vcpu);
7550         u32 zero = 0;
7551         gpa_t vmptr;
7552
7553         if (!nested_vmx_check_permission(vcpu))
7554                 return 1;
7555
7556         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7557                 return 1;
7558
7559         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7560                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7561                 return kvm_skip_emulated_instruction(vcpu);
7562         }
7563
7564         if (vmptr == vmx->nested.vmxon_ptr) {
7565                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7566                 return kvm_skip_emulated_instruction(vcpu);
7567         }
7568
7569         if (vmptr == vmx->nested.current_vmptr)
7570                 nested_release_vmcs12(vmx);
7571
7572         kvm_vcpu_write_guest(vcpu,
7573                         vmptr + offsetof(struct vmcs12, launch_state),
7574                         &zero, sizeof(zero));
7575
7576         nested_vmx_succeed(vcpu);
7577         return kvm_skip_emulated_instruction(vcpu);
7578 }
7579
7580 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7581
7582 /* Emulate the VMLAUNCH instruction */
7583 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7584 {
7585         return nested_vmx_run(vcpu, true);
7586 }
7587
7588 /* Emulate the VMRESUME instruction */
7589 static int handle_vmresume(struct kvm_vcpu *vcpu)
7590 {
7591
7592         return nested_vmx_run(vcpu, false);
7593 }
7594
7595 /*
7596  * Read a vmcs12 field. Since these can have varying lengths and we return
7597  * one type, we chose the biggest type (u64) and zero-extend the return value
7598  * to that size. Note that the caller, handle_vmread, might need to use only
7599  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7600  * 64-bit fields are to be returned).
7601  */
7602 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7603                                   unsigned long field, u64 *ret)
7604 {
7605         short offset = vmcs_field_to_offset(field);
7606         char *p;
7607
7608         if (offset < 0)
7609                 return offset;
7610
7611         p = ((char *)(get_vmcs12(vcpu))) + offset;
7612
7613         switch (vmcs_field_width(field)) {
7614         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7615                 *ret = *((natural_width *)p);
7616                 return 0;
7617         case VMCS_FIELD_WIDTH_U16:
7618                 *ret = *((u16 *)p);
7619                 return 0;
7620         case VMCS_FIELD_WIDTH_U32:
7621                 *ret = *((u32 *)p);
7622                 return 0;
7623         case VMCS_FIELD_WIDTH_U64:
7624                 *ret = *((u64 *)p);
7625                 return 0;
7626         default:
7627                 WARN_ON(1);
7628                 return -ENOENT;
7629         }
7630 }
7631
7632
7633 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7634                                    unsigned long field, u64 field_value){
7635         short offset = vmcs_field_to_offset(field);
7636         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7637         if (offset < 0)
7638                 return offset;
7639
7640         switch (vmcs_field_width(field)) {
7641         case VMCS_FIELD_WIDTH_U16:
7642                 *(u16 *)p = field_value;
7643                 return 0;
7644         case VMCS_FIELD_WIDTH_U32:
7645                 *(u32 *)p = field_value;
7646                 return 0;
7647         case VMCS_FIELD_WIDTH_U64:
7648                 *(u64 *)p = field_value;
7649                 return 0;
7650         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7651                 *(natural_width *)p = field_value;
7652                 return 0;
7653         default:
7654                 WARN_ON(1);
7655                 return -ENOENT;
7656         }
7657
7658 }
7659
7660 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7661 {
7662         int i;
7663         unsigned long field;
7664         u64 field_value;
7665         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7666         const u16 *fields = shadow_read_write_fields;
7667         const int num_fields = max_shadow_read_write_fields;
7668
7669         preempt_disable();
7670
7671         vmcs_load(shadow_vmcs);
7672
7673         for (i = 0; i < num_fields; i++) {
7674                 field = fields[i];
7675                 field_value = __vmcs_readl(field);
7676                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7677         }
7678
7679         vmcs_clear(shadow_vmcs);
7680         vmcs_load(vmx->loaded_vmcs->vmcs);
7681
7682         preempt_enable();
7683 }
7684
7685 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7686 {
7687         const u16 *fields[] = {
7688                 shadow_read_write_fields,
7689                 shadow_read_only_fields
7690         };
7691         const int max_fields[] = {
7692                 max_shadow_read_write_fields,
7693                 max_shadow_read_only_fields
7694         };
7695         int i, q;
7696         unsigned long field;
7697         u64 field_value = 0;
7698         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7699
7700         vmcs_load(shadow_vmcs);
7701
7702         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7703                 for (i = 0; i < max_fields[q]; i++) {
7704                         field = fields[q][i];
7705                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7706                         __vmcs_writel(field, field_value);
7707                 }
7708         }
7709
7710         vmcs_clear(shadow_vmcs);
7711         vmcs_load(vmx->loaded_vmcs->vmcs);
7712 }
7713
7714 /*
7715  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7716  * used before) all generate the same failure when it is missing.
7717  */
7718 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7719 {
7720         struct vcpu_vmx *vmx = to_vmx(vcpu);
7721         if (vmx->nested.current_vmptr == -1ull) {
7722                 nested_vmx_failInvalid(vcpu);
7723                 return 0;
7724         }
7725         return 1;
7726 }
7727
7728 static int handle_vmread(struct kvm_vcpu *vcpu)
7729 {
7730         unsigned long field;
7731         u64 field_value;
7732         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7733         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7734         gva_t gva = 0;
7735
7736         if (!nested_vmx_check_permission(vcpu))
7737                 return 1;
7738
7739         if (!nested_vmx_check_vmcs12(vcpu))
7740                 return kvm_skip_emulated_instruction(vcpu);
7741
7742         /* Decode instruction info and find the field to read */
7743         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7744         /* Read the field, zero-extended to a u64 field_value */
7745         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7746                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7747                 return kvm_skip_emulated_instruction(vcpu);
7748         }
7749         /*
7750          * Now copy part of this value to register or memory, as requested.
7751          * Note that the number of bits actually copied is 32 or 64 depending
7752          * on the guest's mode (32 or 64 bit), not on the given field's length.
7753          */
7754         if (vmx_instruction_info & (1u << 10)) {
7755                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7756                         field_value);
7757         } else {
7758                 if (get_vmx_mem_address(vcpu, exit_qualification,
7759                                 vmx_instruction_info, true, &gva))
7760                         return 1;
7761                 /* _system ok, as hardware has verified cpl=0 */
7762                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7763                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7764         }
7765
7766         nested_vmx_succeed(vcpu);
7767         return kvm_skip_emulated_instruction(vcpu);
7768 }
7769
7770
7771 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7772 {
7773         unsigned long field;
7774         gva_t gva;
7775         struct vcpu_vmx *vmx = to_vmx(vcpu);
7776         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7777         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7778
7779         /* The value to write might be 32 or 64 bits, depending on L1's long
7780          * mode, and eventually we need to write that into a field of several
7781          * possible lengths. The code below first zero-extends the value to 64
7782          * bit (field_value), and then copies only the appropriate number of
7783          * bits into the vmcs12 field.
7784          */
7785         u64 field_value = 0;
7786         struct x86_exception e;
7787
7788         if (!nested_vmx_check_permission(vcpu))
7789                 return 1;
7790
7791         if (!nested_vmx_check_vmcs12(vcpu))
7792                 return kvm_skip_emulated_instruction(vcpu);
7793
7794         if (vmx_instruction_info & (1u << 10))
7795                 field_value = kvm_register_readl(vcpu,
7796                         (((vmx_instruction_info) >> 3) & 0xf));
7797         else {
7798                 if (get_vmx_mem_address(vcpu, exit_qualification,
7799                                 vmx_instruction_info, false, &gva))
7800                         return 1;
7801                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7802                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7803                         kvm_inject_page_fault(vcpu, &e);
7804                         return 1;
7805                 }
7806         }
7807
7808
7809         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7810         if (vmcs_field_readonly(field)) {
7811                 nested_vmx_failValid(vcpu,
7812                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7813                 return kvm_skip_emulated_instruction(vcpu);
7814         }
7815
7816         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7817                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7818                 return kvm_skip_emulated_instruction(vcpu);
7819         }
7820
7821         switch (field) {
7822 #define SHADOW_FIELD_RW(x) case x:
7823 #include "vmx_shadow_fields.h"
7824                 /*
7825                  * The fields that can be updated by L1 without a vmexit are
7826                  * always updated in the vmcs02, the others go down the slow
7827                  * path of prepare_vmcs02.
7828                  */
7829                 break;
7830         default:
7831                 vmx->nested.dirty_vmcs12 = true;
7832                 break;
7833         }
7834
7835         nested_vmx_succeed(vcpu);
7836         return kvm_skip_emulated_instruction(vcpu);
7837 }
7838
7839 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7840 {
7841         vmx->nested.current_vmptr = vmptr;
7842         if (enable_shadow_vmcs) {
7843                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7844                               SECONDARY_EXEC_SHADOW_VMCS);
7845                 vmcs_write64(VMCS_LINK_POINTER,
7846                              __pa(vmx->vmcs01.shadow_vmcs));
7847                 vmx->nested.sync_shadow_vmcs = true;
7848         }
7849         vmx->nested.dirty_vmcs12 = true;
7850 }
7851
7852 /* Emulate the VMPTRLD instruction */
7853 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7854 {
7855         struct vcpu_vmx *vmx = to_vmx(vcpu);
7856         gpa_t vmptr;
7857
7858         if (!nested_vmx_check_permission(vcpu))
7859                 return 1;
7860
7861         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7862                 return 1;
7863
7864         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7865                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7866                 return kvm_skip_emulated_instruction(vcpu);
7867         }
7868
7869         if (vmptr == vmx->nested.vmxon_ptr) {
7870                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7871                 return kvm_skip_emulated_instruction(vcpu);
7872         }
7873
7874         if (vmx->nested.current_vmptr != vmptr) {
7875                 struct vmcs12 *new_vmcs12;
7876                 struct page *page;
7877                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7878                 if (is_error_page(page)) {
7879                         nested_vmx_failInvalid(vcpu);
7880                         return kvm_skip_emulated_instruction(vcpu);
7881                 }
7882                 new_vmcs12 = kmap(page);
7883                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7884                         kunmap(page);
7885                         kvm_release_page_clean(page);
7886                         nested_vmx_failValid(vcpu,
7887                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7888                         return kvm_skip_emulated_instruction(vcpu);
7889                 }
7890
7891                 nested_release_vmcs12(vmx);
7892                 /*
7893                  * Load VMCS12 from guest memory since it is not already
7894                  * cached.
7895                  */
7896                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7897                 kunmap(page);
7898                 kvm_release_page_clean(page);
7899
7900                 set_current_vmptr(vmx, vmptr);
7901         }
7902
7903         nested_vmx_succeed(vcpu);
7904         return kvm_skip_emulated_instruction(vcpu);
7905 }
7906
7907 /* Emulate the VMPTRST instruction */
7908 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7909 {
7910         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7911         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7912         gva_t vmcs_gva;
7913         struct x86_exception e;
7914
7915         if (!nested_vmx_check_permission(vcpu))
7916                 return 1;
7917
7918         if (get_vmx_mem_address(vcpu, exit_qualification,
7919                         vmx_instruction_info, true, &vmcs_gva))
7920                 return 1;
7921         /* ok to use *_system, as hardware has verified cpl=0 */
7922         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7923                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7924                                  sizeof(u64), &e)) {
7925                 kvm_inject_page_fault(vcpu, &e);
7926                 return 1;
7927         }
7928         nested_vmx_succeed(vcpu);
7929         return kvm_skip_emulated_instruction(vcpu);
7930 }
7931
7932 /* Emulate the INVEPT instruction */
7933 static int handle_invept(struct kvm_vcpu *vcpu)
7934 {
7935         struct vcpu_vmx *vmx = to_vmx(vcpu);
7936         u32 vmx_instruction_info, types;
7937         unsigned long type;
7938         gva_t gva;
7939         struct x86_exception e;
7940         struct {
7941                 u64 eptp, gpa;
7942         } operand;
7943
7944         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7945               SECONDARY_EXEC_ENABLE_EPT) ||
7946             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7947                 kvm_queue_exception(vcpu, UD_VECTOR);
7948                 return 1;
7949         }
7950
7951         if (!nested_vmx_check_permission(vcpu))
7952                 return 1;
7953
7954         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7955         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7956
7957         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7958
7959         if (type >= 32 || !(types & (1 << type))) {
7960                 nested_vmx_failValid(vcpu,
7961                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7962                 return kvm_skip_emulated_instruction(vcpu);
7963         }
7964
7965         /* According to the Intel VMX instruction reference, the memory
7966          * operand is read even if it isn't needed (e.g., for type==global)
7967          */
7968         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7969                         vmx_instruction_info, false, &gva))
7970                 return 1;
7971         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7972                                 sizeof(operand), &e)) {
7973                 kvm_inject_page_fault(vcpu, &e);
7974                 return 1;
7975         }
7976
7977         switch (type) {
7978         case VMX_EPT_EXTENT_GLOBAL:
7979         /*
7980          * TODO: track mappings and invalidate
7981          * single context requests appropriately
7982          */
7983         case VMX_EPT_EXTENT_CONTEXT:
7984                 kvm_mmu_sync_roots(vcpu);
7985                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7986                 nested_vmx_succeed(vcpu);
7987                 break;
7988         default:
7989                 BUG_ON(1);
7990                 break;
7991         }
7992
7993         return kvm_skip_emulated_instruction(vcpu);
7994 }
7995
7996 static int handle_invvpid(struct kvm_vcpu *vcpu)
7997 {
7998         struct vcpu_vmx *vmx = to_vmx(vcpu);
7999         u32 vmx_instruction_info;
8000         unsigned long type, types;
8001         gva_t gva;
8002         struct x86_exception e;
8003         struct {
8004                 u64 vpid;
8005                 u64 gla;
8006         } operand;
8007
8008         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
8009               SECONDARY_EXEC_ENABLE_VPID) ||
8010                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
8011                 kvm_queue_exception(vcpu, UD_VECTOR);
8012                 return 1;
8013         }
8014
8015         if (!nested_vmx_check_permission(vcpu))
8016                 return 1;
8017
8018         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8019         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8020
8021         types = (vmx->nested.nested_vmx_vpid_caps &
8022                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8023
8024         if (type >= 32 || !(types & (1 << type))) {
8025                 nested_vmx_failValid(vcpu,
8026                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8027                 return kvm_skip_emulated_instruction(vcpu);
8028         }
8029
8030         /* according to the intel vmx instruction reference, the memory
8031          * operand is read even if it isn't needed (e.g., for type==global)
8032          */
8033         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8034                         vmx_instruction_info, false, &gva))
8035                 return 1;
8036         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8037                                 sizeof(operand), &e)) {
8038                 kvm_inject_page_fault(vcpu, &e);
8039                 return 1;
8040         }
8041         if (operand.vpid >> 16) {
8042                 nested_vmx_failValid(vcpu,
8043                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8044                 return kvm_skip_emulated_instruction(vcpu);
8045         }
8046
8047         switch (type) {
8048         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8049                 if (is_noncanonical_address(operand.gla, vcpu)) {
8050                         nested_vmx_failValid(vcpu,
8051                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8052                         return kvm_skip_emulated_instruction(vcpu);
8053                 }
8054                 /* fall through */
8055         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8056         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8057                 if (!operand.vpid) {
8058                         nested_vmx_failValid(vcpu,
8059                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8060                         return kvm_skip_emulated_instruction(vcpu);
8061                 }
8062                 break;
8063         case VMX_VPID_EXTENT_ALL_CONTEXT:
8064                 break;
8065         default:
8066                 WARN_ON_ONCE(1);
8067                 return kvm_skip_emulated_instruction(vcpu);
8068         }
8069
8070         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8071         nested_vmx_succeed(vcpu);
8072
8073         return kvm_skip_emulated_instruction(vcpu);
8074 }
8075
8076 static int handle_pml_full(struct kvm_vcpu *vcpu)
8077 {
8078         unsigned long exit_qualification;
8079
8080         trace_kvm_pml_full(vcpu->vcpu_id);
8081
8082         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8083
8084         /*
8085          * PML buffer FULL happened while executing iret from NMI,
8086          * "blocked by NMI" bit has to be set before next VM entry.
8087          */
8088         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8089                         enable_vnmi &&
8090                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8091                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8092                                 GUEST_INTR_STATE_NMI);
8093
8094         /*
8095          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8096          * here.., and there's no userspace involvement needed for PML.
8097          */
8098         return 1;
8099 }
8100
8101 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8102 {
8103         kvm_lapic_expired_hv_timer(vcpu);
8104         return 1;
8105 }
8106
8107 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8108 {
8109         struct vcpu_vmx *vmx = to_vmx(vcpu);
8110         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8111
8112         /* Check for memory type validity */
8113         switch (address & VMX_EPTP_MT_MASK) {
8114         case VMX_EPTP_MT_UC:
8115                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8116                         return false;
8117                 break;
8118         case VMX_EPTP_MT_WB:
8119                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8120                         return false;
8121                 break;
8122         default:
8123                 return false;
8124         }
8125
8126         /* only 4 levels page-walk length are valid */
8127         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8128                 return false;
8129
8130         /* Reserved bits should not be set */
8131         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8132                 return false;
8133
8134         /* AD, if set, should be supported */
8135         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8136                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8137                         return false;
8138         }
8139
8140         return true;
8141 }
8142
8143 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8144                                      struct vmcs12 *vmcs12)
8145 {
8146         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8147         u64 address;
8148         bool accessed_dirty;
8149         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8150
8151         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8152             !nested_cpu_has_ept(vmcs12))
8153                 return 1;
8154
8155         if (index >= VMFUNC_EPTP_ENTRIES)
8156                 return 1;
8157
8158
8159         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8160                                      &address, index * 8, 8))
8161                 return 1;
8162
8163         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8164
8165         /*
8166          * If the (L2) guest does a vmfunc to the currently
8167          * active ept pointer, we don't have to do anything else
8168          */
8169         if (vmcs12->ept_pointer != address) {
8170                 if (!valid_ept_address(vcpu, address))
8171                         return 1;
8172
8173                 kvm_mmu_unload(vcpu);
8174                 mmu->ept_ad = accessed_dirty;
8175                 mmu->base_role.ad_disabled = !accessed_dirty;
8176                 vmcs12->ept_pointer = address;
8177                 /*
8178                  * TODO: Check what's the correct approach in case
8179                  * mmu reload fails. Currently, we just let the next
8180                  * reload potentially fail
8181                  */
8182                 kvm_mmu_reload(vcpu);
8183         }
8184
8185         return 0;
8186 }
8187
8188 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8189 {
8190         struct vcpu_vmx *vmx = to_vmx(vcpu);
8191         struct vmcs12 *vmcs12;
8192         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8193
8194         /*
8195          * VMFUNC is only supported for nested guests, but we always enable the
8196          * secondary control for simplicity; for non-nested mode, fake that we
8197          * didn't by injecting #UD.
8198          */
8199         if (!is_guest_mode(vcpu)) {
8200                 kvm_queue_exception(vcpu, UD_VECTOR);
8201                 return 1;
8202         }
8203
8204         vmcs12 = get_vmcs12(vcpu);
8205         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8206                 goto fail;
8207
8208         switch (function) {
8209         case 0:
8210                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8211                         goto fail;
8212                 break;
8213         default:
8214                 goto fail;
8215         }
8216         return kvm_skip_emulated_instruction(vcpu);
8217
8218 fail:
8219         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8220                           vmcs_read32(VM_EXIT_INTR_INFO),
8221                           vmcs_readl(EXIT_QUALIFICATION));
8222         return 1;
8223 }
8224
8225 /*
8226  * The exit handlers return 1 if the exit was handled fully and guest execution
8227  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8228  * to be done to userspace and return 0.
8229  */
8230 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8231         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8232         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8233         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8234         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8235         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8236         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8237         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8238         [EXIT_REASON_CPUID]                   = handle_cpuid,
8239         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8240         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8241         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8242         [EXIT_REASON_HLT]                     = handle_halt,
8243         [EXIT_REASON_INVD]                    = handle_invd,
8244         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8245         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8246         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8247         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8248         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8249         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8250         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8251         [EXIT_REASON_VMREAD]                  = handle_vmread,
8252         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8253         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8254         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8255         [EXIT_REASON_VMON]                    = handle_vmon,
8256         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8257         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8258         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8259         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8260         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8261         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8262         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8263         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8264         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
8265         [EXIT_REASON_LDTR_TR]                 = handle_desc,
8266         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8267         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8268         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8269         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8270         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8271         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8272         [EXIT_REASON_INVEPT]                  = handle_invept,
8273         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8274         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8275         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8276         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8277         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8278         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8279         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8280         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8281 };
8282
8283 static const int kvm_vmx_max_exit_handlers =
8284         ARRAY_SIZE(kvm_vmx_exit_handlers);
8285
8286 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8287                                        struct vmcs12 *vmcs12)
8288 {
8289         unsigned long exit_qualification;
8290         gpa_t bitmap, last_bitmap;
8291         unsigned int port;
8292         int size;
8293         u8 b;
8294
8295         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8296                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8297
8298         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8299
8300         port = exit_qualification >> 16;
8301         size = (exit_qualification & 7) + 1;
8302
8303         last_bitmap = (gpa_t)-1;
8304         b = -1;
8305
8306         while (size > 0) {
8307                 if (port < 0x8000)
8308                         bitmap = vmcs12->io_bitmap_a;
8309                 else if (port < 0x10000)
8310                         bitmap = vmcs12->io_bitmap_b;
8311                 else
8312                         return true;
8313                 bitmap += (port & 0x7fff) / 8;
8314
8315                 if (last_bitmap != bitmap)
8316                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8317                                 return true;
8318                 if (b & (1 << (port & 7)))
8319                         return true;
8320
8321                 port++;
8322                 size--;
8323                 last_bitmap = bitmap;
8324         }
8325
8326         return false;
8327 }
8328
8329 /*
8330  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8331  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8332  * disinterest in the current event (read or write a specific MSR) by using an
8333  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8334  */
8335 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8336         struct vmcs12 *vmcs12, u32 exit_reason)
8337 {
8338         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8339         gpa_t bitmap;
8340
8341         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8342                 return true;
8343
8344         /*
8345          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8346          * for the four combinations of read/write and low/high MSR numbers.
8347          * First we need to figure out which of the four to use:
8348          */
8349         bitmap = vmcs12->msr_bitmap;
8350         if (exit_reason == EXIT_REASON_MSR_WRITE)
8351                 bitmap += 2048;
8352         if (msr_index >= 0xc0000000) {
8353                 msr_index -= 0xc0000000;
8354                 bitmap += 1024;
8355         }
8356
8357         /* Then read the msr_index'th bit from this bitmap: */
8358         if (msr_index < 1024*8) {
8359                 unsigned char b;
8360                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8361                         return true;
8362                 return 1 & (b >> (msr_index & 7));
8363         } else
8364                 return true; /* let L1 handle the wrong parameter */
8365 }
8366
8367 /*
8368  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8369  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8370  * intercept (via guest_host_mask etc.) the current event.
8371  */
8372 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8373         struct vmcs12 *vmcs12)
8374 {
8375         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8376         int cr = exit_qualification & 15;
8377         int reg;
8378         unsigned long val;
8379
8380         switch ((exit_qualification >> 4) & 3) {
8381         case 0: /* mov to cr */
8382                 reg = (exit_qualification >> 8) & 15;
8383                 val = kvm_register_readl(vcpu, reg);
8384                 switch (cr) {
8385                 case 0:
8386                         if (vmcs12->cr0_guest_host_mask &
8387                             (val ^ vmcs12->cr0_read_shadow))
8388                                 return true;
8389                         break;
8390                 case 3:
8391                         if ((vmcs12->cr3_target_count >= 1 &&
8392                                         vmcs12->cr3_target_value0 == val) ||
8393                                 (vmcs12->cr3_target_count >= 2 &&
8394                                         vmcs12->cr3_target_value1 == val) ||
8395                                 (vmcs12->cr3_target_count >= 3 &&
8396                                         vmcs12->cr3_target_value2 == val) ||
8397                                 (vmcs12->cr3_target_count >= 4 &&
8398                                         vmcs12->cr3_target_value3 == val))
8399                                 return false;
8400                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8401                                 return true;
8402                         break;
8403                 case 4:
8404                         if (vmcs12->cr4_guest_host_mask &
8405                             (vmcs12->cr4_read_shadow ^ val))
8406                                 return true;
8407                         break;
8408                 case 8:
8409                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8410                                 return true;
8411                         break;
8412                 }
8413                 break;
8414         case 2: /* clts */
8415                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8416                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8417                         return true;
8418                 break;
8419         case 1: /* mov from cr */
8420                 switch (cr) {
8421                 case 3:
8422                         if (vmcs12->cpu_based_vm_exec_control &
8423                             CPU_BASED_CR3_STORE_EXITING)
8424                                 return true;
8425                         break;
8426                 case 8:
8427                         if (vmcs12->cpu_based_vm_exec_control &
8428                             CPU_BASED_CR8_STORE_EXITING)
8429                                 return true;
8430                         break;
8431                 }
8432                 break;
8433         case 3: /* lmsw */
8434                 /*
8435                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8436                  * cr0. Other attempted changes are ignored, with no exit.
8437                  */
8438                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8439                 if (vmcs12->cr0_guest_host_mask & 0xe &
8440                     (val ^ vmcs12->cr0_read_shadow))
8441                         return true;
8442                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8443                     !(vmcs12->cr0_read_shadow & 0x1) &&
8444                     (val & 0x1))
8445                         return true;
8446                 break;
8447         }
8448         return false;
8449 }
8450
8451 /*
8452  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8453  * should handle it ourselves in L0 (and then continue L2). Only call this
8454  * when in is_guest_mode (L2).
8455  */
8456 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8457 {
8458         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8459         struct vcpu_vmx *vmx = to_vmx(vcpu);
8460         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8461
8462         if (vmx->nested.nested_run_pending)
8463                 return false;
8464
8465         if (unlikely(vmx->fail)) {
8466                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8467                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8468                 return true;
8469         }
8470
8471         /*
8472          * The host physical addresses of some pages of guest memory
8473          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8474          * Page). The CPU may write to these pages via their host
8475          * physical address while L2 is running, bypassing any
8476          * address-translation-based dirty tracking (e.g. EPT write
8477          * protection).
8478          *
8479          * Mark them dirty on every exit from L2 to prevent them from
8480          * getting out of sync with dirty tracking.
8481          */
8482         nested_mark_vmcs12_pages_dirty(vcpu);
8483
8484         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8485                                 vmcs_readl(EXIT_QUALIFICATION),
8486                                 vmx->idt_vectoring_info,
8487                                 intr_info,
8488                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8489                                 KVM_ISA_VMX);
8490
8491         switch (exit_reason) {
8492         case EXIT_REASON_EXCEPTION_NMI:
8493                 if (is_nmi(intr_info))
8494                         return false;
8495                 else if (is_page_fault(intr_info))
8496                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8497                 else if (is_no_device(intr_info) &&
8498                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8499                         return false;
8500                 else if (is_debug(intr_info) &&
8501                          vcpu->guest_debug &
8502                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8503                         return false;
8504                 else if (is_breakpoint(intr_info) &&
8505                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8506                         return false;
8507                 return vmcs12->exception_bitmap &
8508                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8509         case EXIT_REASON_EXTERNAL_INTERRUPT:
8510                 return false;
8511         case EXIT_REASON_TRIPLE_FAULT:
8512                 return true;
8513         case EXIT_REASON_PENDING_INTERRUPT:
8514                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8515         case EXIT_REASON_NMI_WINDOW:
8516                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8517         case EXIT_REASON_TASK_SWITCH:
8518                 return true;
8519         case EXIT_REASON_CPUID:
8520                 return true;
8521         case EXIT_REASON_HLT:
8522                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8523         case EXIT_REASON_INVD:
8524                 return true;
8525         case EXIT_REASON_INVLPG:
8526                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8527         case EXIT_REASON_RDPMC:
8528                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8529         case EXIT_REASON_RDRAND:
8530                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
8531         case EXIT_REASON_RDSEED:
8532                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
8533         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8534                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8535         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8536         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8537         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8538         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8539         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8540         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8541                 /*
8542                  * VMX instructions trap unconditionally. This allows L1 to
8543                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8544                  */
8545                 return true;
8546         case EXIT_REASON_CR_ACCESS:
8547                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8548         case EXIT_REASON_DR_ACCESS:
8549                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8550         case EXIT_REASON_IO_INSTRUCTION:
8551                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8552         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8553                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8554         case EXIT_REASON_MSR_READ:
8555         case EXIT_REASON_MSR_WRITE:
8556                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8557         case EXIT_REASON_INVALID_STATE:
8558                 return true;
8559         case EXIT_REASON_MWAIT_INSTRUCTION:
8560                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8561         case EXIT_REASON_MONITOR_TRAP_FLAG:
8562                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8563         case EXIT_REASON_MONITOR_INSTRUCTION:
8564                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8565         case EXIT_REASON_PAUSE_INSTRUCTION:
8566                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8567                         nested_cpu_has2(vmcs12,
8568                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8569         case EXIT_REASON_MCE_DURING_VMENTRY:
8570                 return false;
8571         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8572                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8573         case EXIT_REASON_APIC_ACCESS:
8574                 return nested_cpu_has2(vmcs12,
8575                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8576         case EXIT_REASON_APIC_WRITE:
8577         case EXIT_REASON_EOI_INDUCED:
8578                 /* apic_write and eoi_induced should exit unconditionally. */
8579                 return true;
8580         case EXIT_REASON_EPT_VIOLATION:
8581                 /*
8582                  * L0 always deals with the EPT violation. If nested EPT is
8583                  * used, and the nested mmu code discovers that the address is
8584                  * missing in the guest EPT table (EPT12), the EPT violation
8585                  * will be injected with nested_ept_inject_page_fault()
8586                  */
8587                 return false;
8588         case EXIT_REASON_EPT_MISCONFIG:
8589                 /*
8590                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8591                  * table (shadow on EPT) or a merged EPT table that L0 built
8592                  * (EPT on EPT). So any problems with the structure of the
8593                  * table is L0's fault.
8594                  */
8595                 return false;
8596         case EXIT_REASON_INVPCID:
8597                 return
8598                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8599                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8600         case EXIT_REASON_WBINVD:
8601                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8602         case EXIT_REASON_XSETBV:
8603                 return true;
8604         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8605                 /*
8606                  * This should never happen, since it is not possible to
8607                  * set XSS to a non-zero value---neither in L1 nor in L2.
8608                  * If if it were, XSS would have to be checked against
8609                  * the XSS exit bitmap in vmcs12.
8610                  */
8611                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8612         case EXIT_REASON_PREEMPTION_TIMER:
8613                 return false;
8614         case EXIT_REASON_PML_FULL:
8615                 /* We emulate PML support to L1. */
8616                 return false;
8617         case EXIT_REASON_VMFUNC:
8618                 /* VM functions are emulated through L2->L0 vmexits. */
8619                 return false;
8620         default:
8621                 return true;
8622         }
8623 }
8624
8625 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8626 {
8627         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8628
8629         /*
8630          * At this point, the exit interruption info in exit_intr_info
8631          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8632          * we need to query the in-kernel LAPIC.
8633          */
8634         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8635         if ((exit_intr_info &
8636              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8637             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8638                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8639                 vmcs12->vm_exit_intr_error_code =
8640                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8641         }
8642
8643         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8644                           vmcs_readl(EXIT_QUALIFICATION));
8645         return 1;
8646 }
8647
8648 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8649 {
8650         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8651         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8652 }
8653
8654 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8655 {
8656         if (vmx->pml_pg) {
8657                 __free_page(vmx->pml_pg);
8658                 vmx->pml_pg = NULL;
8659         }
8660 }
8661
8662 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8663 {
8664         struct vcpu_vmx *vmx = to_vmx(vcpu);
8665         u64 *pml_buf;
8666         u16 pml_idx;
8667
8668         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8669
8670         /* Do nothing if PML buffer is empty */
8671         if (pml_idx == (PML_ENTITY_NUM - 1))
8672                 return;
8673
8674         /* PML index always points to next available PML buffer entity */
8675         if (pml_idx >= PML_ENTITY_NUM)
8676                 pml_idx = 0;
8677         else
8678                 pml_idx++;
8679
8680         pml_buf = page_address(vmx->pml_pg);
8681         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8682                 u64 gpa;
8683
8684                 gpa = pml_buf[pml_idx];
8685                 WARN_ON(gpa & (PAGE_SIZE - 1));
8686                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8687         }
8688
8689         /* reset PML index */
8690         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8691 }
8692
8693 /*
8694  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8695  * Called before reporting dirty_bitmap to userspace.
8696  */
8697 static void kvm_flush_pml_buffers(struct kvm *kvm)
8698 {
8699         int i;
8700         struct kvm_vcpu *vcpu;
8701         /*
8702          * We only need to kick vcpu out of guest mode here, as PML buffer
8703          * is flushed at beginning of all VMEXITs, and it's obvious that only
8704          * vcpus running in guest are possible to have unflushed GPAs in PML
8705          * buffer.
8706          */
8707         kvm_for_each_vcpu(i, vcpu, kvm)
8708                 kvm_vcpu_kick(vcpu);
8709 }
8710
8711 static void vmx_dump_sel(char *name, uint32_t sel)
8712 {
8713         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8714                name, vmcs_read16(sel),
8715                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8716                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8717                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8718 }
8719
8720 static void vmx_dump_dtsel(char *name, uint32_t limit)
8721 {
8722         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8723                name, vmcs_read32(limit),
8724                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8725 }
8726
8727 static void dump_vmcs(void)
8728 {
8729         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8730         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8731         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8732         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8733         u32 secondary_exec_control = 0;
8734         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8735         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8736         int i, n;
8737
8738         if (cpu_has_secondary_exec_ctrls())
8739                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8740
8741         pr_err("*** Guest State ***\n");
8742         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8743                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8744                vmcs_readl(CR0_GUEST_HOST_MASK));
8745         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8746                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8747         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8748         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8749             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8750         {
8751                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8752                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8753                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8754                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8755         }
8756         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8757                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8758         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8759                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8760         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8761                vmcs_readl(GUEST_SYSENTER_ESP),
8762                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8763         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8764         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8765         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8766         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8767         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8768         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8769         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8770         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8771         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8772         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8773         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8774             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8775                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8776                        efer, vmcs_read64(GUEST_IA32_PAT));
8777         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8778                vmcs_read64(GUEST_IA32_DEBUGCTL),
8779                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8780         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8781                 pr_err("PerfGlobCtl = 0x%016llx\n",
8782                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8783         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8784                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8785         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8786                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8787                vmcs_read32(GUEST_ACTIVITY_STATE));
8788         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8789                 pr_err("InterruptStatus = %04x\n",
8790                        vmcs_read16(GUEST_INTR_STATUS));
8791
8792         pr_err("*** Host State ***\n");
8793         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8794                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8795         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8796                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8797                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8798                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8799                vmcs_read16(HOST_TR_SELECTOR));
8800         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8801                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8802                vmcs_readl(HOST_TR_BASE));
8803         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8804                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8805         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8806                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8807                vmcs_readl(HOST_CR4));
8808         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8809                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8810                vmcs_read32(HOST_IA32_SYSENTER_CS),
8811                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8812         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8813                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8814                        vmcs_read64(HOST_IA32_EFER),
8815                        vmcs_read64(HOST_IA32_PAT));
8816         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8817                 pr_err("PerfGlobCtl = 0x%016llx\n",
8818                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8819
8820         pr_err("*** Control State ***\n");
8821         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8822                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8823         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8824         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8825                vmcs_read32(EXCEPTION_BITMAP),
8826                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8827                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8828         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8829                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8830                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8831                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8832         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8833                vmcs_read32(VM_EXIT_INTR_INFO),
8834                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8835                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8836         pr_err("        reason=%08x qualification=%016lx\n",
8837                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8838         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8839                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8840                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8841         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8842         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8843                 pr_err("TSC Multiplier = 0x%016llx\n",
8844                        vmcs_read64(TSC_MULTIPLIER));
8845         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8846                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8847         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8848                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8849         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8850                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8851         n = vmcs_read32(CR3_TARGET_COUNT);
8852         for (i = 0; i + 1 < n; i += 4)
8853                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8854                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8855                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8856         if (i < n)
8857                 pr_err("CR3 target%u=%016lx\n",
8858                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8859         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8860                 pr_err("PLE Gap=%08x Window=%08x\n",
8861                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8862         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8863                 pr_err("Virtual processor ID = 0x%04x\n",
8864                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8865 }
8866
8867 /*
8868  * The guest has exited.  See if we can fix it or if we need userspace
8869  * assistance.
8870  */
8871 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8872 {
8873         struct vcpu_vmx *vmx = to_vmx(vcpu);
8874         u32 exit_reason = vmx->exit_reason;
8875         u32 vectoring_info = vmx->idt_vectoring_info;
8876
8877         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8878
8879         /*
8880          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8881          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8882          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8883          * mode as if vcpus is in root mode, the PML buffer must has been
8884          * flushed already.
8885          */
8886         if (enable_pml)
8887                 vmx_flush_pml_buffer(vcpu);
8888
8889         /* If guest state is invalid, start emulating */
8890         if (vmx->emulation_required)
8891                 return handle_invalid_guest_state(vcpu);
8892
8893         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8894                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8895
8896         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8897                 dump_vmcs();
8898                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8899                 vcpu->run->fail_entry.hardware_entry_failure_reason
8900                         = exit_reason;
8901                 return 0;
8902         }
8903
8904         if (unlikely(vmx->fail)) {
8905                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8906                 vcpu->run->fail_entry.hardware_entry_failure_reason
8907                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8908                 return 0;
8909         }
8910
8911         /*
8912          * Note:
8913          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8914          * delivery event since it indicates guest is accessing MMIO.
8915          * The vm-exit can be triggered again after return to guest that
8916          * will cause infinite loop.
8917          */
8918         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8919                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8920                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8921                         exit_reason != EXIT_REASON_PML_FULL &&
8922                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8923                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8924                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8925                 vcpu->run->internal.ndata = 3;
8926                 vcpu->run->internal.data[0] = vectoring_info;
8927                 vcpu->run->internal.data[1] = exit_reason;
8928                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8929                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8930                         vcpu->run->internal.ndata++;
8931                         vcpu->run->internal.data[3] =
8932                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8933                 }
8934                 return 0;
8935         }
8936
8937         if (unlikely(!enable_vnmi &&
8938                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
8939                 if (vmx_interrupt_allowed(vcpu)) {
8940                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8941                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
8942                            vcpu->arch.nmi_pending) {
8943                         /*
8944                          * This CPU don't support us in finding the end of an
8945                          * NMI-blocked window if the guest runs with IRQs
8946                          * disabled. So we pull the trigger after 1 s of
8947                          * futile waiting, but inform the user about this.
8948                          */
8949                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8950                                "state on VCPU %d after 1 s timeout\n",
8951                                __func__, vcpu->vcpu_id);
8952                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8953                 }
8954         }
8955
8956         if (exit_reason < kvm_vmx_max_exit_handlers
8957             && kvm_vmx_exit_handlers[exit_reason])
8958                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8959         else {
8960                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8961                                 exit_reason);
8962                 kvm_queue_exception(vcpu, UD_VECTOR);
8963                 return 1;
8964         }
8965 }
8966
8967 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8968 {
8969         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8970
8971         if (is_guest_mode(vcpu) &&
8972                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8973                 return;
8974
8975         if (irr == -1 || tpr < irr) {
8976                 vmcs_write32(TPR_THRESHOLD, 0);
8977                 return;
8978         }
8979
8980         vmcs_write32(TPR_THRESHOLD, irr);
8981 }
8982
8983 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8984 {
8985         u32 sec_exec_control;
8986
8987         /* Postpone execution until vmcs01 is the current VMCS. */
8988         if (is_guest_mode(vcpu)) {
8989                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8990                 return;
8991         }
8992
8993         if (!cpu_has_vmx_virtualize_x2apic_mode())
8994                 return;
8995
8996         if (!cpu_need_tpr_shadow(vcpu))
8997                 return;
8998
8999         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9000
9001         if (set) {
9002                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9003                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9004         } else {
9005                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9006                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9007                 vmx_flush_tlb_ept_only(vcpu);
9008         }
9009         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9010
9011         vmx_update_msr_bitmap(vcpu);
9012 }
9013
9014 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9015 {
9016         struct vcpu_vmx *vmx = to_vmx(vcpu);
9017
9018         /*
9019          * Currently we do not handle the nested case where L2 has an
9020          * APIC access page of its own; that page is still pinned.
9021          * Hence, we skip the case where the VCPU is in guest mode _and_
9022          * L1 prepared an APIC access page for L2.
9023          *
9024          * For the case where L1 and L2 share the same APIC access page
9025          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9026          * in the vmcs12), this function will only update either the vmcs01
9027          * or the vmcs02.  If the former, the vmcs02 will be updated by
9028          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
9029          * the next L2->L1 exit.
9030          */
9031         if (!is_guest_mode(vcpu) ||
9032             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9033                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9034                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9035                 vmx_flush_tlb_ept_only(vcpu);
9036         }
9037 }
9038
9039 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9040 {
9041         u16 status;
9042         u8 old;
9043
9044         if (max_isr == -1)
9045                 max_isr = 0;
9046
9047         status = vmcs_read16(GUEST_INTR_STATUS);
9048         old = status >> 8;
9049         if (max_isr != old) {
9050                 status &= 0xff;
9051                 status |= max_isr << 8;
9052                 vmcs_write16(GUEST_INTR_STATUS, status);
9053         }
9054 }
9055
9056 static void vmx_set_rvi(int vector)
9057 {
9058         u16 status;
9059         u8 old;
9060
9061         if (vector == -1)
9062                 vector = 0;
9063
9064         status = vmcs_read16(GUEST_INTR_STATUS);
9065         old = (u8)status & 0xff;
9066         if ((u8)vector != old) {
9067                 status &= ~0xff;
9068                 status |= (u8)vector;
9069                 vmcs_write16(GUEST_INTR_STATUS, status);
9070         }
9071 }
9072
9073 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9074 {
9075         /*
9076          * When running L2, updating RVI is only relevant when
9077          * vmcs12 virtual-interrupt-delivery enabled.
9078          * However, it can be enabled only when L1 also
9079          * intercepts external-interrupts and in that case
9080          * we should not update vmcs02 RVI but instead intercept
9081          * interrupt. Therefore, do nothing when running L2.
9082          */
9083         if (!is_guest_mode(vcpu))
9084                 vmx_set_rvi(max_irr);
9085 }
9086
9087 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9088 {
9089         struct vcpu_vmx *vmx = to_vmx(vcpu);
9090         int max_irr;
9091         bool max_irr_updated;
9092
9093         WARN_ON(!vcpu->arch.apicv_active);
9094         if (pi_test_on(&vmx->pi_desc)) {
9095                 pi_clear_on(&vmx->pi_desc);
9096                 /*
9097                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9098                  * But on x86 this is just a compiler barrier anyway.
9099                  */
9100                 smp_mb__after_atomic();
9101                 max_irr_updated =
9102                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9103
9104                 /*
9105                  * If we are running L2 and L1 has a new pending interrupt
9106                  * which can be injected, we should re-evaluate
9107                  * what should be done with this new L1 interrupt.
9108                  * If L1 intercepts external-interrupts, we should
9109                  * exit from L2 to L1. Otherwise, interrupt should be
9110                  * delivered directly to L2.
9111                  */
9112                 if (is_guest_mode(vcpu) && max_irr_updated) {
9113                         if (nested_exit_on_intr(vcpu))
9114                                 kvm_vcpu_exiting_guest_mode(vcpu);
9115                         else
9116                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9117                 }
9118         } else {
9119                 max_irr = kvm_lapic_find_highest_irr(vcpu);
9120         }
9121         vmx_hwapic_irr_update(vcpu, max_irr);
9122         return max_irr;
9123 }
9124
9125 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9126 {
9127         if (!kvm_vcpu_apicv_active(vcpu))
9128                 return;
9129
9130         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9131         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9132         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9133         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9134 }
9135
9136 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9137 {
9138         struct vcpu_vmx *vmx = to_vmx(vcpu);
9139
9140         pi_clear_on(&vmx->pi_desc);
9141         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9142 }
9143
9144 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9145 {
9146         u32 exit_intr_info = 0;
9147         u16 basic_exit_reason = (u16)vmx->exit_reason;
9148
9149         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9150               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9151                 return;
9152
9153         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9154                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9155         vmx->exit_intr_info = exit_intr_info;
9156
9157         /* if exit due to PF check for async PF */
9158         if (is_page_fault(exit_intr_info))
9159                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9160
9161         /* Handle machine checks before interrupts are enabled */
9162         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9163             is_machine_check(exit_intr_info))
9164                 kvm_machine_check();
9165
9166         /* We need to handle NMIs before interrupts are enabled */
9167         if (is_nmi(exit_intr_info)) {
9168                 kvm_before_handle_nmi(&vmx->vcpu);
9169                 asm("int $2");
9170                 kvm_after_handle_nmi(&vmx->vcpu);
9171         }
9172 }
9173
9174 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9175 {
9176         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9177
9178         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9179                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9180                 unsigned int vector;
9181                 unsigned long entry;
9182                 gate_desc *desc;
9183                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9184 #ifdef CONFIG_X86_64
9185                 unsigned long tmp;
9186 #endif
9187
9188                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9189                 desc = (gate_desc *)vmx->host_idt_base + vector;
9190                 entry = gate_offset(desc);
9191                 asm volatile(
9192 #ifdef CONFIG_X86_64
9193                         "mov %%" _ASM_SP ", %[sp]\n\t"
9194                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9195                         "push $%c[ss]\n\t"
9196                         "push %[sp]\n\t"
9197 #endif
9198                         "pushf\n\t"
9199                         __ASM_SIZE(push) " $%c[cs]\n\t"
9200                         CALL_NOSPEC
9201                         :
9202 #ifdef CONFIG_X86_64
9203                         [sp]"=&r"(tmp),
9204 #endif
9205                         ASM_CALL_CONSTRAINT
9206                         :
9207                         THUNK_TARGET(entry),
9208                         [ss]"i"(__KERNEL_DS),
9209                         [cs]"i"(__KERNEL_CS)
9210                         );
9211         }
9212 }
9213 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9214
9215 static bool vmx_has_high_real_mode_segbase(void)
9216 {
9217         return enable_unrestricted_guest || emulate_invalid_guest_state;
9218 }
9219
9220 static bool vmx_mpx_supported(void)
9221 {
9222         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9223                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9224 }
9225
9226 static bool vmx_xsaves_supported(void)
9227 {
9228         return vmcs_config.cpu_based_2nd_exec_ctrl &
9229                 SECONDARY_EXEC_XSAVES;
9230 }
9231
9232 static bool vmx_umip_emulated(void)
9233 {
9234         return vmcs_config.cpu_based_2nd_exec_ctrl &
9235                 SECONDARY_EXEC_DESC;
9236 }
9237
9238 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9239 {
9240         u32 exit_intr_info;
9241         bool unblock_nmi;
9242         u8 vector;
9243         bool idtv_info_valid;
9244
9245         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9246
9247         if (enable_vnmi) {
9248                 if (vmx->loaded_vmcs->nmi_known_unmasked)
9249                         return;
9250                 /*
9251                  * Can't use vmx->exit_intr_info since we're not sure what
9252                  * the exit reason is.
9253                  */
9254                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9255                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9256                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9257                 /*
9258                  * SDM 3: 27.7.1.2 (September 2008)
9259                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
9260                  * a guest IRET fault.
9261                  * SDM 3: 23.2.2 (September 2008)
9262                  * Bit 12 is undefined in any of the following cases:
9263                  *  If the VM exit sets the valid bit in the IDT-vectoring
9264                  *   information field.
9265                  *  If the VM exit is due to a double fault.
9266                  */
9267                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9268                     vector != DF_VECTOR && !idtv_info_valid)
9269                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9270                                       GUEST_INTR_STATE_NMI);
9271                 else
9272                         vmx->loaded_vmcs->nmi_known_unmasked =
9273                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9274                                   & GUEST_INTR_STATE_NMI);
9275         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9276                 vmx->loaded_vmcs->vnmi_blocked_time +=
9277                         ktime_to_ns(ktime_sub(ktime_get(),
9278                                               vmx->loaded_vmcs->entry_time));
9279 }
9280
9281 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9282                                       u32 idt_vectoring_info,
9283                                       int instr_len_field,
9284                                       int error_code_field)
9285 {
9286         u8 vector;
9287         int type;
9288         bool idtv_info_valid;
9289
9290         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9291
9292         vcpu->arch.nmi_injected = false;
9293         kvm_clear_exception_queue(vcpu);
9294         kvm_clear_interrupt_queue(vcpu);
9295
9296         if (!idtv_info_valid)
9297                 return;
9298
9299         kvm_make_request(KVM_REQ_EVENT, vcpu);
9300
9301         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9302         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9303
9304         switch (type) {
9305         case INTR_TYPE_NMI_INTR:
9306                 vcpu->arch.nmi_injected = true;
9307                 /*
9308                  * SDM 3: 27.7.1.2 (September 2008)
9309                  * Clear bit "block by NMI" before VM entry if a NMI
9310                  * delivery faulted.
9311                  */
9312                 vmx_set_nmi_mask(vcpu, false);
9313                 break;
9314         case INTR_TYPE_SOFT_EXCEPTION:
9315                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9316                 /* fall through */
9317         case INTR_TYPE_HARD_EXCEPTION:
9318                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9319                         u32 err = vmcs_read32(error_code_field);
9320                         kvm_requeue_exception_e(vcpu, vector, err);
9321                 } else
9322                         kvm_requeue_exception(vcpu, vector);
9323                 break;
9324         case INTR_TYPE_SOFT_INTR:
9325                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9326                 /* fall through */
9327         case INTR_TYPE_EXT_INTR:
9328                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9329                 break;
9330         default:
9331                 break;
9332         }
9333 }
9334
9335 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9336 {
9337         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9338                                   VM_EXIT_INSTRUCTION_LEN,
9339                                   IDT_VECTORING_ERROR_CODE);
9340 }
9341
9342 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9343 {
9344         __vmx_complete_interrupts(vcpu,
9345                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9346                                   VM_ENTRY_INSTRUCTION_LEN,
9347                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9348
9349         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9350 }
9351
9352 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9353 {
9354         int i, nr_msrs;
9355         struct perf_guest_switch_msr *msrs;
9356
9357         msrs = perf_guest_get_msrs(&nr_msrs);
9358
9359         if (!msrs)
9360                 return;
9361
9362         for (i = 0; i < nr_msrs; i++)
9363                 if (msrs[i].host == msrs[i].guest)
9364                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9365                 else
9366                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9367                                         msrs[i].host);
9368 }
9369
9370 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9371 {
9372         struct vcpu_vmx *vmx = to_vmx(vcpu);
9373         u64 tscl;
9374         u32 delta_tsc;
9375
9376         if (vmx->hv_deadline_tsc == -1)
9377                 return;
9378
9379         tscl = rdtsc();
9380         if (vmx->hv_deadline_tsc > tscl)
9381                 /* sure to be 32 bit only because checked on set_hv_timer */
9382                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9383                         cpu_preemption_timer_multi);
9384         else
9385                 delta_tsc = 0;
9386
9387         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9388 }
9389
9390 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9391 {
9392         struct vcpu_vmx *vmx = to_vmx(vcpu);
9393         unsigned long cr3, cr4;
9394
9395         /* Record the guest's net vcpu time for enforced NMI injections. */
9396         if (unlikely(!enable_vnmi &&
9397                      vmx->loaded_vmcs->soft_vnmi_blocked))
9398                 vmx->loaded_vmcs->entry_time = ktime_get();
9399
9400         /* Don't enter VMX if guest state is invalid, let the exit handler
9401            start emulation until we arrive back to a valid state */
9402         if (vmx->emulation_required)
9403                 return;
9404
9405         if (vmx->ple_window_dirty) {
9406                 vmx->ple_window_dirty = false;
9407                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9408         }
9409
9410         if (vmx->nested.sync_shadow_vmcs) {
9411                 copy_vmcs12_to_shadow(vmx);
9412                 vmx->nested.sync_shadow_vmcs = false;
9413         }
9414
9415         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9416                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9417         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9418                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9419
9420         cr3 = __get_current_cr3_fast();
9421         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9422                 vmcs_writel(HOST_CR3, cr3);
9423                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9424         }
9425
9426         cr4 = cr4_read_shadow();
9427         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9428                 vmcs_writel(HOST_CR4, cr4);
9429                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9430         }
9431
9432         /* When single-stepping over STI and MOV SS, we must clear the
9433          * corresponding interruptibility bits in the guest state. Otherwise
9434          * vmentry fails as it then expects bit 14 (BS) in pending debug
9435          * exceptions being set, but that's not correct for the guest debugging
9436          * case. */
9437         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9438                 vmx_set_interrupt_shadow(vcpu, 0);
9439
9440         if (static_cpu_has(X86_FEATURE_PKU) &&
9441             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9442             vcpu->arch.pkru != vmx->host_pkru)
9443                 __write_pkru(vcpu->arch.pkru);
9444
9445         atomic_switch_perf_msrs(vmx);
9446
9447         vmx_arm_hv_timer(vcpu);
9448
9449         /*
9450          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9451          * it's non-zero. Since vmentry is serialising on affected CPUs, there
9452          * is no need to worry about the conditional branch over the wrmsr
9453          * being speculatively taken.
9454          */
9455         if (vmx->spec_ctrl)
9456                 native_wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
9457
9458         vmx->__launched = vmx->loaded_vmcs->launched;
9459         asm(
9460                 /* Store host registers */
9461                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9462                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9463                 "push %%" _ASM_CX " \n\t"
9464                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9465                 "je 1f \n\t"
9466                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9467                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9468                 "1: \n\t"
9469                 /* Reload cr2 if changed */
9470                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9471                 "mov %%cr2, %%" _ASM_DX " \n\t"
9472                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9473                 "je 2f \n\t"
9474                 "mov %%" _ASM_AX", %%cr2 \n\t"
9475                 "2: \n\t"
9476                 /* Check if vmlaunch of vmresume is needed */
9477                 "cmpl $0, %c[launched](%0) \n\t"
9478                 /* Load guest registers.  Don't clobber flags. */
9479                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9480                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9481                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9482                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9483                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9484                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9485 #ifdef CONFIG_X86_64
9486                 "mov %c[r8](%0),  %%r8  \n\t"
9487                 "mov %c[r9](%0),  %%r9  \n\t"
9488                 "mov %c[r10](%0), %%r10 \n\t"
9489                 "mov %c[r11](%0), %%r11 \n\t"
9490                 "mov %c[r12](%0), %%r12 \n\t"
9491                 "mov %c[r13](%0), %%r13 \n\t"
9492                 "mov %c[r14](%0), %%r14 \n\t"
9493                 "mov %c[r15](%0), %%r15 \n\t"
9494 #endif
9495                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9496
9497                 /* Enter guest mode */
9498                 "jne 1f \n\t"
9499                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9500                 "jmp 2f \n\t"
9501                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9502                 "2: "
9503                 /* Save guest registers, load host registers, keep flags */
9504                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9505                 "pop %0 \n\t"
9506                 "setbe %c[fail](%0)\n\t"
9507                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9508                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9509                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9510                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9511                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9512                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9513                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9514 #ifdef CONFIG_X86_64
9515                 "mov %%r8,  %c[r8](%0) \n\t"
9516                 "mov %%r9,  %c[r9](%0) \n\t"
9517                 "mov %%r10, %c[r10](%0) \n\t"
9518                 "mov %%r11, %c[r11](%0) \n\t"
9519                 "mov %%r12, %c[r12](%0) \n\t"
9520                 "mov %%r13, %c[r13](%0) \n\t"
9521                 "mov %%r14, %c[r14](%0) \n\t"
9522                 "mov %%r15, %c[r15](%0) \n\t"
9523                 "xor %%r8d,  %%r8d \n\t"
9524                 "xor %%r9d,  %%r9d \n\t"
9525                 "xor %%r10d, %%r10d \n\t"
9526                 "xor %%r11d, %%r11d \n\t"
9527                 "xor %%r12d, %%r12d \n\t"
9528                 "xor %%r13d, %%r13d \n\t"
9529                 "xor %%r14d, %%r14d \n\t"
9530                 "xor %%r15d, %%r15d \n\t"
9531 #endif
9532                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9533                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9534
9535                 "xor %%eax, %%eax \n\t"
9536                 "xor %%ebx, %%ebx \n\t"
9537                 "xor %%esi, %%esi \n\t"
9538                 "xor %%edi, %%edi \n\t"
9539                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9540                 ".pushsection .rodata \n\t"
9541                 ".global vmx_return \n\t"
9542                 "vmx_return: " _ASM_PTR " 2b \n\t"
9543                 ".popsection"
9544               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9545                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9546                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9547                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9548                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9549                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9550                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9551                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9552                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9553                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9554                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9555 #ifdef CONFIG_X86_64
9556                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9557                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9558                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9559                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9560                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9561                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9562                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9563                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9564 #endif
9565                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9566                 [wordsize]"i"(sizeof(ulong))
9567               : "cc", "memory"
9568 #ifdef CONFIG_X86_64
9569                 , "rax", "rbx", "rdi", "rsi"
9570                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9571 #else
9572                 , "eax", "ebx", "edi", "esi"
9573 #endif
9574               );
9575
9576         /*
9577          * We do not use IBRS in the kernel. If this vCPU has used the
9578          * SPEC_CTRL MSR it may have left it on; save the value and
9579          * turn it off. This is much more efficient than blindly adding
9580          * it to the atomic save/restore list. Especially as the former
9581          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9582          *
9583          * For non-nested case:
9584          * If the L01 MSR bitmap does not intercept the MSR, then we need to
9585          * save it.
9586          *
9587          * For nested case:
9588          * If the L02 MSR bitmap does not intercept the MSR, then we need to
9589          * save it.
9590          */
9591         if (!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))
9592                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
9593
9594         if (vmx->spec_ctrl)
9595                 native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
9596
9597         /* Eliminate branch target predictions from guest mode */
9598         vmexit_fill_RSB();
9599
9600         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9601         if (vmx->host_debugctlmsr)
9602                 update_debugctlmsr(vmx->host_debugctlmsr);
9603
9604 #ifndef CONFIG_X86_64
9605         /*
9606          * The sysexit path does not restore ds/es, so we must set them to
9607          * a reasonable value ourselves.
9608          *
9609          * We can't defer this to vmx_load_host_state() since that function
9610          * may be executed in interrupt context, which saves and restore segments
9611          * around it, nullifying its effect.
9612          */
9613         loadsegment(ds, __USER_DS);
9614         loadsegment(es, __USER_DS);
9615 #endif
9616
9617         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9618                                   | (1 << VCPU_EXREG_RFLAGS)
9619                                   | (1 << VCPU_EXREG_PDPTR)
9620                                   | (1 << VCPU_EXREG_SEGMENTS)
9621                                   | (1 << VCPU_EXREG_CR3));
9622         vcpu->arch.regs_dirty = 0;
9623
9624         /*
9625          * eager fpu is enabled if PKEY is supported and CR4 is switched
9626          * back on host, so it is safe to read guest PKRU from current
9627          * XSAVE.
9628          */
9629         if (static_cpu_has(X86_FEATURE_PKU) &&
9630             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9631                 vcpu->arch.pkru = __read_pkru();
9632                 if (vcpu->arch.pkru != vmx->host_pkru)
9633                         __write_pkru(vmx->host_pkru);
9634         }
9635
9636         /*
9637          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9638          * we did not inject a still-pending event to L1 now because of
9639          * nested_run_pending, we need to re-enable this bit.
9640          */
9641         if (vmx->nested.nested_run_pending)
9642                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9643
9644         vmx->nested.nested_run_pending = 0;
9645         vmx->idt_vectoring_info = 0;
9646
9647         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9648         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9649                 return;
9650
9651         vmx->loaded_vmcs->launched = 1;
9652         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9653
9654         vmx_complete_atomic_exit(vmx);
9655         vmx_recover_nmi_blocking(vmx);
9656         vmx_complete_interrupts(vmx);
9657 }
9658 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9659
9660 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9661 {
9662         struct vcpu_vmx *vmx = to_vmx(vcpu);
9663         int cpu;
9664
9665         if (vmx->loaded_vmcs == vmcs)
9666                 return;
9667
9668         cpu = get_cpu();
9669         vmx->loaded_vmcs = vmcs;
9670         vmx_vcpu_put(vcpu);
9671         vmx_vcpu_load(vcpu, cpu);
9672         put_cpu();
9673 }
9674
9675 /*
9676  * Ensure that the current vmcs of the logical processor is the
9677  * vmcs01 of the vcpu before calling free_nested().
9678  */
9679 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9680 {
9681        struct vcpu_vmx *vmx = to_vmx(vcpu);
9682
9683        vcpu_load(vcpu);
9684        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9685        free_nested(vmx);
9686        vcpu_put(vcpu);
9687 }
9688
9689 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9690 {
9691         struct vcpu_vmx *vmx = to_vmx(vcpu);
9692
9693         if (enable_pml)
9694                 vmx_destroy_pml_buffer(vmx);
9695         free_vpid(vmx->vpid);
9696         leave_guest_mode(vcpu);
9697         vmx_free_vcpu_nested(vcpu);
9698         free_loaded_vmcs(vmx->loaded_vmcs);
9699         kfree(vmx->guest_msrs);
9700         kvm_vcpu_uninit(vcpu);
9701         kmem_cache_free(kvm_vcpu_cache, vmx);
9702 }
9703
9704 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9705 {
9706         int err;
9707         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9708         unsigned long *msr_bitmap;
9709         int cpu;
9710
9711         if (!vmx)
9712                 return ERR_PTR(-ENOMEM);
9713
9714         vmx->vpid = allocate_vpid();
9715
9716         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9717         if (err)
9718                 goto free_vcpu;
9719
9720         err = -ENOMEM;
9721
9722         /*
9723          * If PML is turned on, failure on enabling PML just results in failure
9724          * of creating the vcpu, therefore we can simplify PML logic (by
9725          * avoiding dealing with cases, such as enabling PML partially on vcpus
9726          * for the guest, etc.
9727          */
9728         if (enable_pml) {
9729                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9730                 if (!vmx->pml_pg)
9731                         goto uninit_vcpu;
9732         }
9733
9734         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9735         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9736                      > PAGE_SIZE);
9737
9738         if (!vmx->guest_msrs)
9739                 goto free_pml;
9740
9741         err = alloc_loaded_vmcs(&vmx->vmcs01);
9742         if (err < 0)
9743                 goto free_msrs;
9744
9745         msr_bitmap = vmx->vmcs01.msr_bitmap;
9746         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
9747         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
9748         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
9749         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
9750         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
9751         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
9752         vmx->msr_bitmap_mode = 0;
9753
9754         vmx->loaded_vmcs = &vmx->vmcs01;
9755         cpu = get_cpu();
9756         vmx_vcpu_load(&vmx->vcpu, cpu);
9757         vmx->vcpu.cpu = cpu;
9758         vmx_vcpu_setup(vmx);
9759         vmx_vcpu_put(&vmx->vcpu);
9760         put_cpu();
9761         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9762                 err = alloc_apic_access_page(kvm);
9763                 if (err)
9764                         goto free_vmcs;
9765         }
9766
9767         if (enable_ept) {
9768                 err = init_rmode_identity_map(kvm);
9769                 if (err)
9770                         goto free_vmcs;
9771         }
9772
9773         if (nested) {
9774                 nested_vmx_setup_ctls_msrs(vmx);
9775                 vmx->nested.vpid02 = allocate_vpid();
9776         }
9777
9778         vmx->nested.posted_intr_nv = -1;
9779         vmx->nested.current_vmptr = -1ull;
9780
9781         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9782
9783         /*
9784          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9785          * or POSTED_INTR_WAKEUP_VECTOR.
9786          */
9787         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9788         vmx->pi_desc.sn = 1;
9789
9790         return &vmx->vcpu;
9791
9792 free_vmcs:
9793         free_vpid(vmx->nested.vpid02);
9794         free_loaded_vmcs(vmx->loaded_vmcs);
9795 free_msrs:
9796         kfree(vmx->guest_msrs);
9797 free_pml:
9798         vmx_destroy_pml_buffer(vmx);
9799 uninit_vcpu:
9800         kvm_vcpu_uninit(&vmx->vcpu);
9801 free_vcpu:
9802         free_vpid(vmx->vpid);
9803         kmem_cache_free(kvm_vcpu_cache, vmx);
9804         return ERR_PTR(err);
9805 }
9806
9807 static void __init vmx_check_processor_compat(void *rtn)
9808 {
9809         struct vmcs_config vmcs_conf;
9810
9811         *(int *)rtn = 0;
9812         if (setup_vmcs_config(&vmcs_conf) < 0)
9813                 *(int *)rtn = -EIO;
9814         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9815                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9816                                 smp_processor_id());
9817                 *(int *)rtn = -EIO;
9818         }
9819 }
9820
9821 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9822 {
9823         u8 cache;
9824         u64 ipat = 0;
9825
9826         /* For VT-d and EPT combination
9827          * 1. MMIO: always map as UC
9828          * 2. EPT with VT-d:
9829          *   a. VT-d without snooping control feature: can't guarantee the
9830          *      result, try to trust guest.
9831          *   b. VT-d with snooping control feature: snooping control feature of
9832          *      VT-d engine can guarantee the cache correctness. Just set it
9833          *      to WB to keep consistent with host. So the same as item 3.
9834          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9835          *    consistent with host MTRR
9836          */
9837         if (is_mmio) {
9838                 cache = MTRR_TYPE_UNCACHABLE;
9839                 goto exit;
9840         }
9841
9842         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9843                 ipat = VMX_EPT_IPAT_BIT;
9844                 cache = MTRR_TYPE_WRBACK;
9845                 goto exit;
9846         }
9847
9848         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9849                 ipat = VMX_EPT_IPAT_BIT;
9850                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9851                         cache = MTRR_TYPE_WRBACK;
9852                 else
9853                         cache = MTRR_TYPE_UNCACHABLE;
9854                 goto exit;
9855         }
9856
9857         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9858
9859 exit:
9860         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9861 }
9862
9863 static int vmx_get_lpage_level(void)
9864 {
9865         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9866                 return PT_DIRECTORY_LEVEL;
9867         else
9868                 /* For shadow and EPT supported 1GB page */
9869                 return PT_PDPE_LEVEL;
9870 }
9871
9872 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9873 {
9874         /*
9875          * These bits in the secondary execution controls field
9876          * are dynamic, the others are mostly based on the hypervisor
9877          * architecture and the guest's CPUID.  Do not touch the
9878          * dynamic bits.
9879          */
9880         u32 mask =
9881                 SECONDARY_EXEC_SHADOW_VMCS |
9882                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9883                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9884                 SECONDARY_EXEC_DESC;
9885
9886         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9887
9888         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9889                      (new_ctl & ~mask) | (cur_ctl & mask));
9890 }
9891
9892 /*
9893  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9894  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9895  */
9896 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9897 {
9898         struct vcpu_vmx *vmx = to_vmx(vcpu);
9899         struct kvm_cpuid_entry2 *entry;
9900
9901         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9902         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9903
9904 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9905         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9906                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9907 } while (0)
9908
9909         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9910         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9911         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9912         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9913         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9914         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9915         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9916         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9917         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9918         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9919         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9920         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9921         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9922         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9923         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9924
9925         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9926         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9927         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9928         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9929         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9930         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
9931
9932 #undef cr4_fixed1_update
9933 }
9934
9935 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9936 {
9937         struct vcpu_vmx *vmx = to_vmx(vcpu);
9938
9939         if (cpu_has_secondary_exec_ctrls()) {
9940                 vmx_compute_secondary_exec_control(vmx);
9941                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9942         }
9943
9944         if (nested_vmx_allowed(vcpu))
9945                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9946                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9947         else
9948                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9949                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9950
9951         if (nested_vmx_allowed(vcpu))
9952                 nested_vmx_cr_fixed1_bits_update(vcpu);
9953 }
9954
9955 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9956 {
9957         if (func == 1 && nested)
9958                 entry->ecx |= bit(X86_FEATURE_VMX);
9959 }
9960
9961 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9962                 struct x86_exception *fault)
9963 {
9964         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9965         struct vcpu_vmx *vmx = to_vmx(vcpu);
9966         u32 exit_reason;
9967         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9968
9969         if (vmx->nested.pml_full) {
9970                 exit_reason = EXIT_REASON_PML_FULL;
9971                 vmx->nested.pml_full = false;
9972                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9973         } else if (fault->error_code & PFERR_RSVD_MASK)
9974                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9975         else
9976                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9977
9978         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9979         vmcs12->guest_physical_address = fault->address;
9980 }
9981
9982 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9983 {
9984         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9985 }
9986
9987 /* Callbacks for nested_ept_init_mmu_context: */
9988
9989 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9990 {
9991         /* return the page table to be shadowed - in our case, EPT12 */
9992         return get_vmcs12(vcpu)->ept_pointer;
9993 }
9994
9995 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9996 {
9997         WARN_ON(mmu_is_nested(vcpu));
9998         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
9999                 return 1;
10000
10001         kvm_mmu_unload(vcpu);
10002         kvm_init_shadow_ept_mmu(vcpu,
10003                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
10004                         VMX_EPT_EXECUTE_ONLY_BIT,
10005                         nested_ept_ad_enabled(vcpu));
10006         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
10007         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
10008         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10009
10010         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
10011         return 0;
10012 }
10013
10014 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10015 {
10016         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10017 }
10018
10019 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10020                                             u16 error_code)
10021 {
10022         bool inequality, bit;
10023
10024         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10025         inequality =
10026                 (error_code & vmcs12->page_fault_error_code_mask) !=
10027                  vmcs12->page_fault_error_code_match;
10028         return inequality ^ bit;
10029 }
10030
10031 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10032                 struct x86_exception *fault)
10033 {
10034         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10035
10036         WARN_ON(!is_guest_mode(vcpu));
10037
10038         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10039                 !to_vmx(vcpu)->nested.nested_run_pending) {
10040                 vmcs12->vm_exit_intr_error_code = fault->error_code;
10041                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10042                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10043                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10044                                   fault->address);
10045         } else {
10046                 kvm_inject_page_fault(vcpu, fault);
10047         }
10048 }
10049
10050 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10051                                                  struct vmcs12 *vmcs12);
10052
10053 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10054                                         struct vmcs12 *vmcs12)
10055 {
10056         struct vcpu_vmx *vmx = to_vmx(vcpu);
10057         struct page *page;
10058         u64 hpa;
10059
10060         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10061                 /*
10062                  * Translate L1 physical address to host physical
10063                  * address for vmcs02. Keep the page pinned, so this
10064                  * physical address remains valid. We keep a reference
10065                  * to it so we can release it later.
10066                  */
10067                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10068                         kvm_release_page_dirty(vmx->nested.apic_access_page);
10069                         vmx->nested.apic_access_page = NULL;
10070                 }
10071                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10072                 /*
10073                  * If translation failed, no matter: This feature asks
10074                  * to exit when accessing the given address, and if it
10075                  * can never be accessed, this feature won't do
10076                  * anything anyway.
10077                  */
10078                 if (!is_error_page(page)) {
10079                         vmx->nested.apic_access_page = page;
10080                         hpa = page_to_phys(vmx->nested.apic_access_page);
10081                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
10082                 } else {
10083                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10084                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10085                 }
10086         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10087                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10088                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
10089                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10090                 kvm_vcpu_reload_apic_access_page(vcpu);
10091         }
10092
10093         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10094                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10095                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10096                         vmx->nested.virtual_apic_page = NULL;
10097                 }
10098                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10099
10100                 /*
10101                  * If translation failed, VM entry will fail because
10102                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10103                  * Failing the vm entry is _not_ what the processor
10104                  * does but it's basically the only possibility we
10105                  * have.  We could still enter the guest if CR8 load
10106                  * exits are enabled, CR8 store exits are enabled, and
10107                  * virtualize APIC access is disabled; in this case
10108                  * the processor would never use the TPR shadow and we
10109                  * could simply clear the bit from the execution
10110                  * control.  But such a configuration is useless, so
10111                  * let's keep the code simple.
10112                  */
10113                 if (!is_error_page(page)) {
10114                         vmx->nested.virtual_apic_page = page;
10115                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
10116                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10117                 }
10118         }
10119
10120         if (nested_cpu_has_posted_intr(vmcs12)) {
10121                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10122                         kunmap(vmx->nested.pi_desc_page);
10123                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
10124                         vmx->nested.pi_desc_page = NULL;
10125                 }
10126                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10127                 if (is_error_page(page))
10128                         return;
10129                 vmx->nested.pi_desc_page = page;
10130                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10131                 vmx->nested.pi_desc =
10132                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
10133                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10134                         (PAGE_SIZE - 1)));
10135                 vmcs_write64(POSTED_INTR_DESC_ADDR,
10136                         page_to_phys(vmx->nested.pi_desc_page) +
10137                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10138                         (PAGE_SIZE - 1)));
10139         }
10140         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10141                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10142                               CPU_BASED_USE_MSR_BITMAPS);
10143         else
10144                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10145                                 CPU_BASED_USE_MSR_BITMAPS);
10146 }
10147
10148 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10149 {
10150         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10151         struct vcpu_vmx *vmx = to_vmx(vcpu);
10152
10153         if (vcpu->arch.virtual_tsc_khz == 0)
10154                 return;
10155
10156         /* Make sure short timeouts reliably trigger an immediate vmexit.
10157          * hrtimer_start does not guarantee this. */
10158         if (preemption_timeout <= 1) {
10159                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10160                 return;
10161         }
10162
10163         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10164         preemption_timeout *= 1000000;
10165         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10166         hrtimer_start(&vmx->nested.preemption_timer,
10167                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10168 }
10169
10170 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10171                                                struct vmcs12 *vmcs12)
10172 {
10173         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10174                 return 0;
10175
10176         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10177             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10178                 return -EINVAL;
10179
10180         return 0;
10181 }
10182
10183 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10184                                                 struct vmcs12 *vmcs12)
10185 {
10186         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10187                 return 0;
10188
10189         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10190                 return -EINVAL;
10191
10192         return 0;
10193 }
10194
10195 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10196                                                 struct vmcs12 *vmcs12)
10197 {
10198         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10199                 return 0;
10200
10201         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10202                 return -EINVAL;
10203
10204         return 0;
10205 }
10206
10207 /*
10208  * Merge L0's and L1's MSR bitmap, return false to indicate that
10209  * we do not use the hardware.
10210  */
10211 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10212                                                  struct vmcs12 *vmcs12)
10213 {
10214         int msr;
10215         struct page *page;
10216         unsigned long *msr_bitmap_l1;
10217         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10218         /*
10219          * pred_cmd & spec_ctrl are trying to verify two things:
10220          *
10221          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10222          *    ensures that we do not accidentally generate an L02 MSR bitmap
10223          *    from the L12 MSR bitmap that is too permissive.
10224          * 2. That L1 or L2s have actually used the MSR. This avoids
10225          *    unnecessarily merging of the bitmap if the MSR is unused. This
10226          *    works properly because we only update the L01 MSR bitmap lazily.
10227          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10228          *    updated to reflect this when L1 (or its L2s) actually write to
10229          *    the MSR.
10230          */
10231         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10232         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10233
10234         /* Nothing to do if the MSR bitmap is not in use.  */
10235         if (!cpu_has_vmx_msr_bitmap() ||
10236             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10237                 return false;
10238
10239         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10240             !pred_cmd && !spec_ctrl)
10241                 return false;
10242
10243         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10244         if (is_error_page(page))
10245                 return false;
10246
10247         msr_bitmap_l1 = (unsigned long *)kmap(page);
10248         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10249                 /*
10250                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10251                  * just lets the processor take the value from the virtual-APIC page;
10252                  * take those 256 bits directly from the L1 bitmap.
10253                  */
10254                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10255                         unsigned word = msr / BITS_PER_LONG;
10256                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
10257                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10258                 }
10259         } else {
10260                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10261                         unsigned word = msr / BITS_PER_LONG;
10262                         msr_bitmap_l0[word] = ~0;
10263                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10264                 }
10265         }
10266
10267         nested_vmx_disable_intercept_for_msr(
10268                 msr_bitmap_l1, msr_bitmap_l0,
10269                 X2APIC_MSR(APIC_TASKPRI),
10270                 MSR_TYPE_W);
10271
10272         if (nested_cpu_has_vid(vmcs12)) {
10273                 nested_vmx_disable_intercept_for_msr(
10274                         msr_bitmap_l1, msr_bitmap_l0,
10275                         X2APIC_MSR(APIC_EOI),
10276                         MSR_TYPE_W);
10277                 nested_vmx_disable_intercept_for_msr(
10278                         msr_bitmap_l1, msr_bitmap_l0,
10279                         X2APIC_MSR(APIC_SELF_IPI),
10280                         MSR_TYPE_W);
10281         }
10282
10283         if (spec_ctrl)
10284                 nested_vmx_disable_intercept_for_msr(
10285                                         msr_bitmap_l1, msr_bitmap_l0,
10286                                         MSR_IA32_SPEC_CTRL,
10287                                         MSR_TYPE_R | MSR_TYPE_W);
10288
10289         if (pred_cmd)
10290                 nested_vmx_disable_intercept_for_msr(
10291                                         msr_bitmap_l1, msr_bitmap_l0,
10292                                         MSR_IA32_PRED_CMD,
10293                                         MSR_TYPE_W);
10294
10295         kunmap(page);
10296         kvm_release_page_clean(page);
10297
10298         return true;
10299 }
10300
10301 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10302                                            struct vmcs12 *vmcs12)
10303 {
10304         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10305             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10306             !nested_cpu_has_vid(vmcs12) &&
10307             !nested_cpu_has_posted_intr(vmcs12))
10308                 return 0;
10309
10310         /*
10311          * If virtualize x2apic mode is enabled,
10312          * virtualize apic access must be disabled.
10313          */
10314         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10315             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10316                 return -EINVAL;
10317
10318         /*
10319          * If virtual interrupt delivery is enabled,
10320          * we must exit on external interrupts.
10321          */
10322         if (nested_cpu_has_vid(vmcs12) &&
10323            !nested_exit_on_intr(vcpu))
10324                 return -EINVAL;
10325
10326         /*
10327          * bits 15:8 should be zero in posted_intr_nv,
10328          * the descriptor address has been already checked
10329          * in nested_get_vmcs12_pages.
10330          */
10331         if (nested_cpu_has_posted_intr(vmcs12) &&
10332            (!nested_cpu_has_vid(vmcs12) ||
10333             !nested_exit_intr_ack_set(vcpu) ||
10334             vmcs12->posted_intr_nv & 0xff00))
10335                 return -EINVAL;
10336
10337         /* tpr shadow is needed by all apicv features. */
10338         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10339                 return -EINVAL;
10340
10341         return 0;
10342 }
10343
10344 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10345                                        unsigned long count_field,
10346                                        unsigned long addr_field)
10347 {
10348         int maxphyaddr;
10349         u64 count, addr;
10350
10351         if (vmcs12_read_any(vcpu, count_field, &count) ||
10352             vmcs12_read_any(vcpu, addr_field, &addr)) {
10353                 WARN_ON(1);
10354                 return -EINVAL;
10355         }
10356         if (count == 0)
10357                 return 0;
10358         maxphyaddr = cpuid_maxphyaddr(vcpu);
10359         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10360             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10361                 pr_debug_ratelimited(
10362                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10363                         addr_field, maxphyaddr, count, addr);
10364                 return -EINVAL;
10365         }
10366         return 0;
10367 }
10368
10369 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10370                                                 struct vmcs12 *vmcs12)
10371 {
10372         if (vmcs12->vm_exit_msr_load_count == 0 &&
10373             vmcs12->vm_exit_msr_store_count == 0 &&
10374             vmcs12->vm_entry_msr_load_count == 0)
10375                 return 0; /* Fast path */
10376         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10377                                         VM_EXIT_MSR_LOAD_ADDR) ||
10378             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10379                                         VM_EXIT_MSR_STORE_ADDR) ||
10380             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10381                                         VM_ENTRY_MSR_LOAD_ADDR))
10382                 return -EINVAL;
10383         return 0;
10384 }
10385
10386 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10387                                          struct vmcs12 *vmcs12)
10388 {
10389         u64 address = vmcs12->pml_address;
10390         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10391
10392         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10393                 if (!nested_cpu_has_ept(vmcs12) ||
10394                     !IS_ALIGNED(address, 4096)  ||
10395                     address >> maxphyaddr)
10396                         return -EINVAL;
10397         }
10398
10399         return 0;
10400 }
10401
10402 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10403                                        struct vmx_msr_entry *e)
10404 {
10405         /* x2APIC MSR accesses are not allowed */
10406         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10407                 return -EINVAL;
10408         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10409             e->index == MSR_IA32_UCODE_REV)
10410                 return -EINVAL;
10411         if (e->reserved != 0)
10412                 return -EINVAL;
10413         return 0;
10414 }
10415
10416 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10417                                      struct vmx_msr_entry *e)
10418 {
10419         if (e->index == MSR_FS_BASE ||
10420             e->index == MSR_GS_BASE ||
10421             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10422             nested_vmx_msr_check_common(vcpu, e))
10423                 return -EINVAL;
10424         return 0;
10425 }
10426
10427 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10428                                       struct vmx_msr_entry *e)
10429 {
10430         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10431             nested_vmx_msr_check_common(vcpu, e))
10432                 return -EINVAL;
10433         return 0;
10434 }
10435
10436 /*
10437  * Load guest's/host's msr at nested entry/exit.
10438  * return 0 for success, entry index for failure.
10439  */
10440 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10441 {
10442         u32 i;
10443         struct vmx_msr_entry e;
10444         struct msr_data msr;
10445
10446         msr.host_initiated = false;
10447         for (i = 0; i < count; i++) {
10448                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10449                                         &e, sizeof(e))) {
10450                         pr_debug_ratelimited(
10451                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10452                                 __func__, i, gpa + i * sizeof(e));
10453                         goto fail;
10454                 }
10455                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10456                         pr_debug_ratelimited(
10457                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10458                                 __func__, i, e.index, e.reserved);
10459                         goto fail;
10460                 }
10461                 msr.index = e.index;
10462                 msr.data = e.value;
10463                 if (kvm_set_msr(vcpu, &msr)) {
10464                         pr_debug_ratelimited(
10465                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10466                                 __func__, i, e.index, e.value);
10467                         goto fail;
10468                 }
10469         }
10470         return 0;
10471 fail:
10472         return i + 1;
10473 }
10474
10475 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10476 {
10477         u32 i;
10478         struct vmx_msr_entry e;
10479
10480         for (i = 0; i < count; i++) {
10481                 struct msr_data msr_info;
10482                 if (kvm_vcpu_read_guest(vcpu,
10483                                         gpa + i * sizeof(e),
10484                                         &e, 2 * sizeof(u32))) {
10485                         pr_debug_ratelimited(
10486                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10487                                 __func__, i, gpa + i * sizeof(e));
10488                         return -EINVAL;
10489                 }
10490                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10491                         pr_debug_ratelimited(
10492                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10493                                 __func__, i, e.index, e.reserved);
10494                         return -EINVAL;
10495                 }
10496                 msr_info.host_initiated = false;
10497                 msr_info.index = e.index;
10498                 if (kvm_get_msr(vcpu, &msr_info)) {
10499                         pr_debug_ratelimited(
10500                                 "%s cannot read MSR (%u, 0x%x)\n",
10501                                 __func__, i, e.index);
10502                         return -EINVAL;
10503                 }
10504                 if (kvm_vcpu_write_guest(vcpu,
10505                                          gpa + i * sizeof(e) +
10506                                              offsetof(struct vmx_msr_entry, value),
10507                                          &msr_info.data, sizeof(msr_info.data))) {
10508                         pr_debug_ratelimited(
10509                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10510                                 __func__, i, e.index, msr_info.data);
10511                         return -EINVAL;
10512                 }
10513         }
10514         return 0;
10515 }
10516
10517 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10518 {
10519         unsigned long invalid_mask;
10520
10521         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10522         return (val & invalid_mask) == 0;
10523 }
10524
10525 /*
10526  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10527  * emulating VM entry into a guest with EPT enabled.
10528  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10529  * is assigned to entry_failure_code on failure.
10530  */
10531 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10532                                u32 *entry_failure_code)
10533 {
10534         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10535                 if (!nested_cr3_valid(vcpu, cr3)) {
10536                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10537                         return 1;
10538                 }
10539
10540                 /*
10541                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10542                  * must not be dereferenced.
10543                  */
10544                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10545                     !nested_ept) {
10546                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10547                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10548                                 return 1;
10549                         }
10550                 }
10551
10552                 vcpu->arch.cr3 = cr3;
10553                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10554         }
10555
10556         kvm_mmu_reset_context(vcpu);
10557         return 0;
10558 }
10559
10560 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10561                                bool from_vmentry)
10562 {
10563         struct vcpu_vmx *vmx = to_vmx(vcpu);
10564
10565         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10566         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10567         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10568         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10569         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10570         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10571         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10572         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10573         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10574         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10575         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10576         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10577         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10578         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10579         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10580         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10581         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10582         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10583         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10584         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10585         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10586         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10587         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10588         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10589         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10590         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10591         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10592         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10593         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10594         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10595         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10596
10597         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10598         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10599                 vmcs12->guest_pending_dbg_exceptions);
10600         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10601         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10602
10603         if (nested_cpu_has_xsaves(vmcs12))
10604                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10605         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10606
10607         if (cpu_has_vmx_posted_intr())
10608                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10609
10610         /*
10611          * Whether page-faults are trapped is determined by a combination of
10612          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10613          * If enable_ept, L0 doesn't care about page faults and we should
10614          * set all of these to L1's desires. However, if !enable_ept, L0 does
10615          * care about (at least some) page faults, and because it is not easy
10616          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10617          * to exit on each and every L2 page fault. This is done by setting
10618          * MASK=MATCH=0 and (see below) EB.PF=1.
10619          * Note that below we don't need special code to set EB.PF beyond the
10620          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10621          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10622          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10623          */
10624         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10625                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10626         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10627                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10628
10629         /* All VMFUNCs are currently emulated through L0 vmexits.  */
10630         if (cpu_has_vmx_vmfunc())
10631                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
10632
10633         if (cpu_has_vmx_apicv()) {
10634                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
10635                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
10636                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
10637                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
10638         }
10639
10640         /*
10641          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10642          * Some constant fields are set here by vmx_set_constant_host_state().
10643          * Other fields are different per CPU, and will be set later when
10644          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10645          */
10646         vmx_set_constant_host_state(vmx);
10647
10648         /*
10649          * Set the MSR load/store lists to match L0's settings.
10650          */
10651         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10652         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10653         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10654         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10655         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10656
10657         set_cr4_guest_host_mask(vmx);
10658
10659         if (vmx_mpx_supported())
10660                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10661
10662         if (enable_vpid) {
10663                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
10664                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10665                 else
10666                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10667         }
10668
10669         /*
10670          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10671          */
10672         if (enable_ept) {
10673                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10674                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10675                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10676                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10677         }
10678
10679         if (cpu_has_vmx_msr_bitmap())
10680                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
10681 }
10682
10683 /*
10684  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10685  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10686  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10687  * guest in a way that will both be appropriate to L1's requests, and our
10688  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10689  * function also has additional necessary side-effects, like setting various
10690  * vcpu->arch fields.
10691  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10692  * is assigned to entry_failure_code on failure.
10693  */
10694 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10695                           bool from_vmentry, u32 *entry_failure_code)
10696 {
10697         struct vcpu_vmx *vmx = to_vmx(vcpu);
10698         u32 exec_control, vmcs12_exec_ctrl;
10699
10700         /*
10701          * First, the fields that are shadowed.  This must be kept in sync
10702          * with vmx_shadow_fields.h.
10703          */
10704
10705         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10706         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10707         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10708         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10709         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10710
10711         /*
10712          * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
10713          * HOST_FS_BASE, HOST_GS_BASE.
10714          */
10715
10716         if (from_vmentry &&
10717             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10718                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10719                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10720         } else {
10721                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10722                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10723         }
10724         if (from_vmentry) {
10725                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10726                              vmcs12->vm_entry_intr_info_field);
10727                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10728                              vmcs12->vm_entry_exception_error_code);
10729                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10730                              vmcs12->vm_entry_instruction_len);
10731                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10732                              vmcs12->guest_interruptibility_info);
10733                 vmx->loaded_vmcs->nmi_known_unmasked =
10734                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10735         } else {
10736                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10737         }
10738         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10739
10740         exec_control = vmcs12->pin_based_vm_exec_control;
10741
10742         /* Preemption timer setting is only taken from vmcs01.  */
10743         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10744         exec_control |= vmcs_config.pin_based_exec_ctrl;
10745         if (vmx->hv_deadline_tsc == -1)
10746                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10747
10748         /* Posted interrupts setting is only taken from vmcs12.  */
10749         if (nested_cpu_has_posted_intr(vmcs12)) {
10750                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10751                 vmx->nested.pi_pending = false;
10752         } else {
10753                 exec_control &= ~PIN_BASED_POSTED_INTR;
10754         }
10755
10756         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10757
10758         vmx->nested.preemption_timer_expired = false;
10759         if (nested_cpu_has_preemption_timer(vmcs12))
10760                 vmx_start_preemption_timer(vcpu);
10761
10762         if (cpu_has_secondary_exec_ctrls()) {
10763                 exec_control = vmx->secondary_exec_control;
10764
10765                 /* Take the following fields only from vmcs12 */
10766                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10767                                   SECONDARY_EXEC_ENABLE_INVPCID |
10768                                   SECONDARY_EXEC_RDTSCP |
10769                                   SECONDARY_EXEC_XSAVES |
10770                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10771                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
10772                                   SECONDARY_EXEC_ENABLE_VMFUNC);
10773                 if (nested_cpu_has(vmcs12,
10774                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10775                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10776                                 ~SECONDARY_EXEC_ENABLE_PML;
10777                         exec_control |= vmcs12_exec_ctrl;
10778                 }
10779
10780                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
10781                         vmcs_write16(GUEST_INTR_STATUS,
10782                                 vmcs12->guest_intr_status);
10783
10784                 /*
10785                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10786                  * nested_get_vmcs12_pages will either fix it up or
10787                  * remove the VM execution control.
10788                  */
10789                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10790                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10791
10792                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10793         }
10794
10795         /*
10796          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10797          * entry, but only if the current (host) sp changed from the value
10798          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10799          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10800          * here we just force the write to happen on entry.
10801          */
10802         vmx->host_rsp = 0;
10803
10804         exec_control = vmx_exec_control(vmx); /* L0's desires */
10805         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10806         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10807         exec_control &= ~CPU_BASED_TPR_SHADOW;
10808         exec_control |= vmcs12->cpu_based_vm_exec_control;
10809
10810         /*
10811          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10812          * nested_get_vmcs12_pages can't fix it up, the illegal value
10813          * will result in a VM entry failure.
10814          */
10815         if (exec_control & CPU_BASED_TPR_SHADOW) {
10816                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10817                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10818         } else {
10819 #ifdef CONFIG_X86_64
10820                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10821                                 CPU_BASED_CR8_STORE_EXITING;
10822 #endif
10823         }
10824
10825         /*
10826          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
10827          * for I/O port accesses.
10828          */
10829         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10830         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10831
10832         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10833
10834         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10835          * bitwise-or of what L1 wants to trap for L2, and what we want to
10836          * trap. Note that CR0.TS also needs updating - we do this later.
10837          */
10838         update_exception_bitmap(vcpu);
10839         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10840         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10841
10842         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10843          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10844          * bits are further modified by vmx_set_efer() below.
10845          */
10846         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10847
10848         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10849          * emulated by vmx_set_efer(), below.
10850          */
10851         vm_entry_controls_init(vmx,
10852                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10853                         ~VM_ENTRY_IA32E_MODE) |
10854                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10855
10856         if (from_vmentry &&
10857             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10858                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10859                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10860         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10861                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10862         }
10863
10864         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10865                 vmcs_write64(TSC_OFFSET,
10866                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10867         else
10868                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10869         if (kvm_has_tsc_control)
10870                 decache_tsc_multiplier(vmx);
10871
10872         if (enable_vpid) {
10873                 /*
10874                  * There is no direct mapping between vpid02 and vpid12, the
10875                  * vpid02 is per-vCPU for L0 and reused while the value of
10876                  * vpid12 is changed w/ one invvpid during nested vmentry.
10877                  * The vpid12 is allocated by L1 for L2, so it will not
10878                  * influence global bitmap(for vpid01 and vpid02 allocation)
10879                  * even if spawn a lot of nested vCPUs.
10880                  */
10881                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10882                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10883                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10884                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true);
10885                         }
10886                 } else {
10887                         vmx_flush_tlb(vcpu, true);
10888                 }
10889         }
10890
10891         if (enable_pml) {
10892                 /*
10893                  * Conceptually we want to copy the PML address and index from
10894                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10895                  * since we always flush the log on each vmexit, this happens
10896                  * to be equivalent to simply resetting the fields in vmcs02.
10897                  */
10898                 ASSERT(vmx->pml_pg);
10899                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10900                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10901         }
10902
10903         if (nested_cpu_has_ept(vmcs12)) {
10904                 if (nested_ept_init_mmu_context(vcpu)) {
10905                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10906                         return 1;
10907                 }
10908         } else if (nested_cpu_has2(vmcs12,
10909                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10910                 vmx_flush_tlb_ept_only(vcpu);
10911         }
10912
10913         /*
10914          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10915          * bits which we consider mandatory enabled.
10916          * The CR0_READ_SHADOW is what L2 should have expected to read given
10917          * the specifications by L1; It's not enough to take
10918          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10919          * have more bits than L1 expected.
10920          */
10921         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10922         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10923
10924         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10925         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10926
10927         if (from_vmentry &&
10928             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10929                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10930         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10931                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10932         else
10933                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10934         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10935         vmx_set_efer(vcpu, vcpu->arch.efer);
10936
10937         if (vmx->nested.dirty_vmcs12) {
10938                 prepare_vmcs02_full(vcpu, vmcs12, from_vmentry);
10939                 vmx->nested.dirty_vmcs12 = false;
10940         }
10941
10942         /* Shadow page tables on either EPT or shadow page tables. */
10943         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10944                                 entry_failure_code))
10945                 return 1;
10946
10947         if (!enable_ept)
10948                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10949
10950         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10951         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10952         return 0;
10953 }
10954
10955 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10956 {
10957         struct vcpu_vmx *vmx = to_vmx(vcpu);
10958
10959         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10960             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10961                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10962
10963         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10964                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10965
10966         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10967                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10968
10969         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10970                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10971
10972         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10973                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10974
10975         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10976                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10977
10978         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10979                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10980
10981         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10982                                 vmx->nested.nested_vmx_procbased_ctls_low,
10983                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10984             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10985              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10986                                  vmx->nested.nested_vmx_secondary_ctls_low,
10987                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10988             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10989                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10990                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10991             !vmx_control_verify(vmcs12->vm_exit_controls,
10992                                 vmx->nested.nested_vmx_exit_ctls_low,
10993                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10994             !vmx_control_verify(vmcs12->vm_entry_controls,
10995                                 vmx->nested.nested_vmx_entry_ctls_low,
10996                                 vmx->nested.nested_vmx_entry_ctls_high))
10997                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10998
10999         if (nested_cpu_has_vmfunc(vmcs12)) {
11000                 if (vmcs12->vm_function_control &
11001                     ~vmx->nested.nested_vmx_vmfunc_controls)
11002                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11003
11004                 if (nested_cpu_has_eptp_switching(vmcs12)) {
11005                         if (!nested_cpu_has_ept(vmcs12) ||
11006                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
11007                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11008                 }
11009         }
11010
11011         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11012                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11013
11014         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11015             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11016             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11017                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11018
11019         return 0;
11020 }
11021
11022 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11023                                   u32 *exit_qual)
11024 {
11025         bool ia32e;
11026
11027         *exit_qual = ENTRY_FAIL_DEFAULT;
11028
11029         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11030             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11031                 return 1;
11032
11033         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11034             vmcs12->vmcs_link_pointer != -1ull) {
11035                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11036                 return 1;
11037         }
11038
11039         /*
11040          * If the load IA32_EFER VM-entry control is 1, the following checks
11041          * are performed on the field for the IA32_EFER MSR:
11042          * - Bits reserved in the IA32_EFER MSR must be 0.
11043          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11044          *   the IA-32e mode guest VM-exit control. It must also be identical
11045          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11046          *   CR0.PG) is 1.
11047          */
11048         if (to_vmx(vcpu)->nested.nested_run_pending &&
11049             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11050                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11051                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11052                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11053                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11054                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11055                         return 1;
11056         }
11057
11058         /*
11059          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11060          * IA32_EFER MSR must be 0 in the field for that register. In addition,
11061          * the values of the LMA and LME bits in the field must each be that of
11062          * the host address-space size VM-exit control.
11063          */
11064         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11065                 ia32e = (vmcs12->vm_exit_controls &
11066                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11067                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11068                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11069                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11070                         return 1;
11071         }
11072
11073         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11074                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11075                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11076                         return 1;
11077
11078         return 0;
11079 }
11080
11081 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
11082 {
11083         struct vcpu_vmx *vmx = to_vmx(vcpu);
11084         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11085         u32 msr_entry_idx;
11086         u32 exit_qual;
11087
11088         enter_guest_mode(vcpu);
11089
11090         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11091                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11092
11093         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11094         vmx_segment_cache_clear(vmx);
11095
11096         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
11097                 leave_guest_mode(vcpu);
11098                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11099                 nested_vmx_entry_failure(vcpu, vmcs12,
11100                                          EXIT_REASON_INVALID_STATE, exit_qual);
11101                 return 1;
11102         }
11103
11104         nested_get_vmcs12_pages(vcpu, vmcs12);
11105
11106         msr_entry_idx = nested_vmx_load_msr(vcpu,
11107                                             vmcs12->vm_entry_msr_load_addr,
11108                                             vmcs12->vm_entry_msr_load_count);
11109         if (msr_entry_idx) {
11110                 leave_guest_mode(vcpu);
11111                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11112                 nested_vmx_entry_failure(vcpu, vmcs12,
11113                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
11114                 return 1;
11115         }
11116
11117         /*
11118          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11119          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11120          * returned as far as L1 is concerned. It will only return (and set
11121          * the success flag) when L2 exits (see nested_vmx_vmexit()).
11122          */
11123         return 0;
11124 }
11125
11126 /*
11127  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11128  * for running an L2 nested guest.
11129  */
11130 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11131 {
11132         struct vmcs12 *vmcs12;
11133         struct vcpu_vmx *vmx = to_vmx(vcpu);
11134         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11135         u32 exit_qual;
11136         int ret;
11137
11138         if (!nested_vmx_check_permission(vcpu))
11139                 return 1;
11140
11141         if (!nested_vmx_check_vmcs12(vcpu))
11142                 goto out;
11143
11144         vmcs12 = get_vmcs12(vcpu);
11145
11146         if (enable_shadow_vmcs)
11147                 copy_shadow_to_vmcs12(vmx);
11148
11149         /*
11150          * The nested entry process starts with enforcing various prerequisites
11151          * on vmcs12 as required by the Intel SDM, and act appropriately when
11152          * they fail: As the SDM explains, some conditions should cause the
11153          * instruction to fail, while others will cause the instruction to seem
11154          * to succeed, but return an EXIT_REASON_INVALID_STATE.
11155          * To speed up the normal (success) code path, we should avoid checking
11156          * for misconfigurations which will anyway be caught by the processor
11157          * when using the merged vmcs02.
11158          */
11159         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11160                 nested_vmx_failValid(vcpu,
11161                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11162                 goto out;
11163         }
11164
11165         if (vmcs12->launch_state == launch) {
11166                 nested_vmx_failValid(vcpu,
11167                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11168                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11169                 goto out;
11170         }
11171
11172         ret = check_vmentry_prereqs(vcpu, vmcs12);
11173         if (ret) {
11174                 nested_vmx_failValid(vcpu, ret);
11175                 goto out;
11176         }
11177
11178         /*
11179          * After this point, the trap flag no longer triggers a singlestep trap
11180          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11181          * This is not 100% correct; for performance reasons, we delegate most
11182          * of the checks on host state to the processor.  If those fail,
11183          * the singlestep trap is missed.
11184          */
11185         skip_emulated_instruction(vcpu);
11186
11187         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11188         if (ret) {
11189                 nested_vmx_entry_failure(vcpu, vmcs12,
11190                                          EXIT_REASON_INVALID_STATE, exit_qual);
11191                 return 1;
11192         }
11193
11194         /*
11195          * We're finally done with prerequisite checking, and can start with
11196          * the nested entry.
11197          */
11198
11199         ret = enter_vmx_non_root_mode(vcpu, true);
11200         if (ret)
11201                 return ret;
11202
11203         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
11204                 return kvm_vcpu_halt(vcpu);
11205
11206         vmx->nested.nested_run_pending = 1;
11207
11208         return 1;
11209
11210 out:
11211         return kvm_skip_emulated_instruction(vcpu);
11212 }
11213
11214 /*
11215  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11216  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11217  * This function returns the new value we should put in vmcs12.guest_cr0.
11218  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11219  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11220  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11221  *     didn't trap the bit, because if L1 did, so would L0).
11222  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11223  *     been modified by L2, and L1 knows it. So just leave the old value of
11224  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11225  *     isn't relevant, because if L0 traps this bit it can set it to anything.
11226  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11227  *     changed these bits, and therefore they need to be updated, but L0
11228  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11229  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11230  */
11231 static inline unsigned long
11232 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11233 {
11234         return
11235         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11236         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11237         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11238                         vcpu->arch.cr0_guest_owned_bits));
11239 }
11240
11241 static inline unsigned long
11242 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11243 {
11244         return
11245         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11246         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11247         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11248                         vcpu->arch.cr4_guest_owned_bits));
11249 }
11250
11251 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11252                                        struct vmcs12 *vmcs12)
11253 {
11254         u32 idt_vectoring;
11255         unsigned int nr;
11256
11257         if (vcpu->arch.exception.injected) {
11258                 nr = vcpu->arch.exception.nr;
11259                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11260
11261                 if (kvm_exception_is_soft(nr)) {
11262                         vmcs12->vm_exit_instruction_len =
11263                                 vcpu->arch.event_exit_inst_len;
11264                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11265                 } else
11266                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11267
11268                 if (vcpu->arch.exception.has_error_code) {
11269                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11270                         vmcs12->idt_vectoring_error_code =
11271                                 vcpu->arch.exception.error_code;
11272                 }
11273
11274                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11275         } else if (vcpu->arch.nmi_injected) {
11276                 vmcs12->idt_vectoring_info_field =
11277                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11278         } else if (vcpu->arch.interrupt.pending) {
11279                 nr = vcpu->arch.interrupt.nr;
11280                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11281
11282                 if (vcpu->arch.interrupt.soft) {
11283                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11284                         vmcs12->vm_entry_instruction_len =
11285                                 vcpu->arch.event_exit_inst_len;
11286                 } else
11287                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11288
11289                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11290         }
11291 }
11292
11293 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11294 {
11295         struct vcpu_vmx *vmx = to_vmx(vcpu);
11296         unsigned long exit_qual;
11297         bool block_nested_events =
11298             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11299
11300         if (vcpu->arch.exception.pending &&
11301                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11302                 if (block_nested_events)
11303                         return -EBUSY;
11304                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11305                 return 0;
11306         }
11307
11308         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11309             vmx->nested.preemption_timer_expired) {
11310                 if (block_nested_events)
11311                         return -EBUSY;
11312                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11313                 return 0;
11314         }
11315
11316         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11317                 if (block_nested_events)
11318                         return -EBUSY;
11319                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11320                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11321                                   INTR_INFO_VALID_MASK, 0);
11322                 /*
11323                  * The NMI-triggered VM exit counts as injection:
11324                  * clear this one and block further NMIs.
11325                  */
11326                 vcpu->arch.nmi_pending = 0;
11327                 vmx_set_nmi_mask(vcpu, true);
11328                 return 0;
11329         }
11330
11331         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11332             nested_exit_on_intr(vcpu)) {
11333                 if (block_nested_events)
11334                         return -EBUSY;
11335                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11336                 return 0;
11337         }
11338
11339         vmx_complete_nested_posted_interrupt(vcpu);
11340         return 0;
11341 }
11342
11343 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11344 {
11345         ktime_t remaining =
11346                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11347         u64 value;
11348
11349         if (ktime_to_ns(remaining) <= 0)
11350                 return 0;
11351
11352         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11353         do_div(value, 1000000);
11354         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11355 }
11356
11357 /*
11358  * Update the guest state fields of vmcs12 to reflect changes that
11359  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11360  * VM-entry controls is also updated, since this is really a guest
11361  * state bit.)
11362  */
11363 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11364 {
11365         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11366         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11367
11368         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11369         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11370         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11371
11372         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11373         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11374         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11375         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11376         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11377         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11378         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11379         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11380         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11381         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11382         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11383         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11384         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11385         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11386         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11387         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11388         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11389         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11390         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11391         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11392         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11393         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11394         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11395         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11396         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11397         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11398         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11399         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11400         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11401         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11402         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11403         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11404         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11405         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11406         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11407         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11408
11409         vmcs12->guest_interruptibility_info =
11410                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11411         vmcs12->guest_pending_dbg_exceptions =
11412                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11413         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11414                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11415         else
11416                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11417
11418         if (nested_cpu_has_preemption_timer(vmcs12)) {
11419                 if (vmcs12->vm_exit_controls &
11420                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11421                         vmcs12->vmx_preemption_timer_value =
11422                                 vmx_get_preemption_timer_value(vcpu);
11423                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11424         }
11425
11426         /*
11427          * In some cases (usually, nested EPT), L2 is allowed to change its
11428          * own CR3 without exiting. If it has changed it, we must keep it.
11429          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11430          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11431          *
11432          * Additionally, restore L2's PDPTR to vmcs12.
11433          */
11434         if (enable_ept) {
11435                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11436                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11437                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11438                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11439                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11440         }
11441
11442         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11443
11444         if (nested_cpu_has_vid(vmcs12))
11445                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11446
11447         vmcs12->vm_entry_controls =
11448                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11449                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11450
11451         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11452                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11453                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11454         }
11455
11456         /* TODO: These cannot have changed unless we have MSR bitmaps and
11457          * the relevant bit asks not to trap the change */
11458         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11459                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11460         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11461                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11462         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11463         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11464         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11465         if (kvm_mpx_supported())
11466                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11467 }
11468
11469 /*
11470  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11471  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11472  * and this function updates it to reflect the changes to the guest state while
11473  * L2 was running (and perhaps made some exits which were handled directly by L0
11474  * without going back to L1), and to reflect the exit reason.
11475  * Note that we do not have to copy here all VMCS fields, just those that
11476  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11477  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11478  * which already writes to vmcs12 directly.
11479  */
11480 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11481                            u32 exit_reason, u32 exit_intr_info,
11482                            unsigned long exit_qualification)
11483 {
11484         /* update guest state fields: */
11485         sync_vmcs12(vcpu, vmcs12);
11486
11487         /* update exit information fields: */
11488
11489         vmcs12->vm_exit_reason = exit_reason;
11490         vmcs12->exit_qualification = exit_qualification;
11491         vmcs12->vm_exit_intr_info = exit_intr_info;
11492
11493         vmcs12->idt_vectoring_info_field = 0;
11494         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11495         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11496
11497         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11498                 vmcs12->launch_state = 1;
11499
11500                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11501                  * instead of reading the real value. */
11502                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11503
11504                 /*
11505                  * Transfer the event that L0 or L1 may wanted to inject into
11506                  * L2 to IDT_VECTORING_INFO_FIELD.
11507                  */
11508                 vmcs12_save_pending_event(vcpu, vmcs12);
11509         }
11510
11511         /*
11512          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11513          * preserved above and would only end up incorrectly in L1.
11514          */
11515         vcpu->arch.nmi_injected = false;
11516         kvm_clear_exception_queue(vcpu);
11517         kvm_clear_interrupt_queue(vcpu);
11518 }
11519
11520 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
11521                         struct vmcs12 *vmcs12)
11522 {
11523         u32 entry_failure_code;
11524
11525         nested_ept_uninit_mmu_context(vcpu);
11526
11527         /*
11528          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11529          * couldn't have changed.
11530          */
11531         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11532                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11533
11534         if (!enable_ept)
11535                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11536 }
11537
11538 /*
11539  * A part of what we need to when the nested L2 guest exits and we want to
11540  * run its L1 parent, is to reset L1's guest state to the host state specified
11541  * in vmcs12.
11542  * This function is to be called not only on normal nested exit, but also on
11543  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11544  * Failures During or After Loading Guest State").
11545  * This function should be called when the active VMCS is L1's (vmcs01).
11546  */
11547 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11548                                    struct vmcs12 *vmcs12)
11549 {
11550         struct kvm_segment seg;
11551
11552         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11553                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11554         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11555                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11556         else
11557                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11558         vmx_set_efer(vcpu, vcpu->arch.efer);
11559
11560         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11561         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11562         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11563         /*
11564          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11565          * actually changed, because vmx_set_cr0 refers to efer set above.
11566          *
11567          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11568          * (KVM doesn't change it);
11569          */
11570         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11571         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11572
11573         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11574         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11575         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11576
11577         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11578
11579         if (enable_vpid) {
11580                 /*
11581                  * Trivially support vpid by letting L2s share their parent
11582                  * L1's vpid. TODO: move to a more elaborate solution, giving
11583                  * each L2 its own vpid and exposing the vpid feature to L1.
11584                  */
11585                 vmx_flush_tlb(vcpu, true);
11586         }
11587
11588         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11589         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11590         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11591         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11592         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11593         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11594         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
11595
11596         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11597         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11598                 vmcs_write64(GUEST_BNDCFGS, 0);
11599
11600         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11601                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11602                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11603         }
11604         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11605                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11606                         vmcs12->host_ia32_perf_global_ctrl);
11607
11608         /* Set L1 segment info according to Intel SDM
11609             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11610         seg = (struct kvm_segment) {
11611                 .base = 0,
11612                 .limit = 0xFFFFFFFF,
11613                 .selector = vmcs12->host_cs_selector,
11614                 .type = 11,
11615                 .present = 1,
11616                 .s = 1,
11617                 .g = 1
11618         };
11619         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11620                 seg.l = 1;
11621         else
11622                 seg.db = 1;
11623         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11624         seg = (struct kvm_segment) {
11625                 .base = 0,
11626                 .limit = 0xFFFFFFFF,
11627                 .type = 3,
11628                 .present = 1,
11629                 .s = 1,
11630                 .db = 1,
11631                 .g = 1
11632         };
11633         seg.selector = vmcs12->host_ds_selector;
11634         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11635         seg.selector = vmcs12->host_es_selector;
11636         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11637         seg.selector = vmcs12->host_ss_selector;
11638         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11639         seg.selector = vmcs12->host_fs_selector;
11640         seg.base = vmcs12->host_fs_base;
11641         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11642         seg.selector = vmcs12->host_gs_selector;
11643         seg.base = vmcs12->host_gs_base;
11644         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11645         seg = (struct kvm_segment) {
11646                 .base = vmcs12->host_tr_base,
11647                 .limit = 0x67,
11648                 .selector = vmcs12->host_tr_selector,
11649                 .type = 11,
11650                 .present = 1
11651         };
11652         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11653
11654         kvm_set_dr(vcpu, 7, 0x400);
11655         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11656
11657         if (cpu_has_vmx_msr_bitmap())
11658                 vmx_update_msr_bitmap(vcpu);
11659
11660         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11661                                 vmcs12->vm_exit_msr_load_count))
11662                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11663 }
11664
11665 /*
11666  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11667  * and modify vmcs12 to make it see what it would expect to see there if
11668  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11669  */
11670 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11671                               u32 exit_intr_info,
11672                               unsigned long exit_qualification)
11673 {
11674         struct vcpu_vmx *vmx = to_vmx(vcpu);
11675         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11676
11677         /* trying to cancel vmlaunch/vmresume is a bug */
11678         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11679
11680         /*
11681          * The only expected VM-instruction error is "VM entry with
11682          * invalid control field(s)." Anything else indicates a
11683          * problem with L0.
11684          */
11685         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11686                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11687
11688         leave_guest_mode(vcpu);
11689
11690         if (likely(!vmx->fail)) {
11691                 if (exit_reason == -1)
11692                         sync_vmcs12(vcpu, vmcs12);
11693                 else
11694                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11695                                        exit_qualification);
11696
11697                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11698                                          vmcs12->vm_exit_msr_store_count))
11699                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11700         }
11701
11702         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11703         vm_entry_controls_reset_shadow(vmx);
11704         vm_exit_controls_reset_shadow(vmx);
11705         vmx_segment_cache_clear(vmx);
11706
11707         /* Update any VMCS fields that might have changed while L2 ran */
11708         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11709         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11710         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11711         if (vmx->hv_deadline_tsc == -1)
11712                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11713                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11714         else
11715                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11716                               PIN_BASED_VMX_PREEMPTION_TIMER);
11717         if (kvm_has_tsc_control)
11718                 decache_tsc_multiplier(vmx);
11719
11720         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11721                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11722                 vmx_set_virtual_x2apic_mode(vcpu,
11723                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11724         } else if (!nested_cpu_has_ept(vmcs12) &&
11725                    nested_cpu_has2(vmcs12,
11726                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11727                 vmx_flush_tlb_ept_only(vcpu);
11728         }
11729
11730         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11731         vmx->host_rsp = 0;
11732
11733         /* Unpin physical memory we referred to in vmcs02 */
11734         if (vmx->nested.apic_access_page) {
11735                 kvm_release_page_dirty(vmx->nested.apic_access_page);
11736                 vmx->nested.apic_access_page = NULL;
11737         }
11738         if (vmx->nested.virtual_apic_page) {
11739                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11740                 vmx->nested.virtual_apic_page = NULL;
11741         }
11742         if (vmx->nested.pi_desc_page) {
11743                 kunmap(vmx->nested.pi_desc_page);
11744                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11745                 vmx->nested.pi_desc_page = NULL;
11746                 vmx->nested.pi_desc = NULL;
11747         }
11748
11749         /*
11750          * We are now running in L2, mmu_notifier will force to reload the
11751          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11752          */
11753         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11754
11755         if (enable_shadow_vmcs && exit_reason != -1)
11756                 vmx->nested.sync_shadow_vmcs = true;
11757
11758         /* in case we halted in L2 */
11759         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11760
11761         if (likely(!vmx->fail)) {
11762                 /*
11763                  * TODO: SDM says that with acknowledge interrupt on
11764                  * exit, bit 31 of the VM-exit interrupt information
11765                  * (valid interrupt) is always set to 1 on
11766                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11767                  * need kvm_cpu_has_interrupt().  See the commit
11768                  * message for details.
11769                  */
11770                 if (nested_exit_intr_ack_set(vcpu) &&
11771                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11772                     kvm_cpu_has_interrupt(vcpu)) {
11773                         int irq = kvm_cpu_get_interrupt(vcpu);
11774                         WARN_ON(irq < 0);
11775                         vmcs12->vm_exit_intr_info = irq |
11776                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11777                 }
11778
11779                 if (exit_reason != -1)
11780                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11781                                                        vmcs12->exit_qualification,
11782                                                        vmcs12->idt_vectoring_info_field,
11783                                                        vmcs12->vm_exit_intr_info,
11784                                                        vmcs12->vm_exit_intr_error_code,
11785                                                        KVM_ISA_VMX);
11786
11787                 load_vmcs12_host_state(vcpu, vmcs12);
11788
11789                 return;
11790         }
11791
11792         /*
11793          * After an early L2 VM-entry failure, we're now back
11794          * in L1 which thinks it just finished a VMLAUNCH or
11795          * VMRESUME instruction, so we need to set the failure
11796          * flag and the VM-instruction error field of the VMCS
11797          * accordingly.
11798          */
11799         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11800
11801         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11802
11803         /*
11804          * The emulated instruction was already skipped in
11805          * nested_vmx_run, but the updated RIP was never
11806          * written back to the vmcs01.
11807          */
11808         skip_emulated_instruction(vcpu);
11809         vmx->fail = 0;
11810 }
11811
11812 /*
11813  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11814  */
11815 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11816 {
11817         if (is_guest_mode(vcpu)) {
11818                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11819                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11820         }
11821         free_nested(to_vmx(vcpu));
11822 }
11823
11824 /*
11825  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11826  * 23.7 "VM-entry failures during or after loading guest state" (this also
11827  * lists the acceptable exit-reason and exit-qualification parameters).
11828  * It should only be called before L2 actually succeeded to run, and when
11829  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11830  */
11831 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11832                         struct vmcs12 *vmcs12,
11833                         u32 reason, unsigned long qualification)
11834 {
11835         load_vmcs12_host_state(vcpu, vmcs12);
11836         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11837         vmcs12->exit_qualification = qualification;
11838         nested_vmx_succeed(vcpu);
11839         if (enable_shadow_vmcs)
11840                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11841 }
11842
11843 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11844                                struct x86_instruction_info *info,
11845                                enum x86_intercept_stage stage)
11846 {
11847         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11848         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
11849
11850         /*
11851          * RDPID causes #UD if disabled through secondary execution controls.
11852          * Because it is marked as EmulateOnUD, we need to intercept it here.
11853          */
11854         if (info->intercept == x86_intercept_rdtscp &&
11855             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
11856                 ctxt->exception.vector = UD_VECTOR;
11857                 ctxt->exception.error_code_valid = false;
11858                 return X86EMUL_PROPAGATE_FAULT;
11859         }
11860
11861         /* TODO: check more intercepts... */
11862         return X86EMUL_CONTINUE;
11863 }
11864
11865 #ifdef CONFIG_X86_64
11866 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11867 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11868                                   u64 divisor, u64 *result)
11869 {
11870         u64 low = a << shift, high = a >> (64 - shift);
11871
11872         /* To avoid the overflow on divq */
11873         if (high >= divisor)
11874                 return 1;
11875
11876         /* Low hold the result, high hold rem which is discarded */
11877         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11878             "rm" (divisor), "0" (low), "1" (high));
11879         *result = low;
11880
11881         return 0;
11882 }
11883
11884 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11885 {
11886         struct vcpu_vmx *vmx = to_vmx(vcpu);
11887         u64 tscl = rdtsc();
11888         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11889         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11890
11891         /* Convert to host delta tsc if tsc scaling is enabled */
11892         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11893                         u64_shl_div_u64(delta_tsc,
11894                                 kvm_tsc_scaling_ratio_frac_bits,
11895                                 vcpu->arch.tsc_scaling_ratio,
11896                                 &delta_tsc))
11897                 return -ERANGE;
11898
11899         /*
11900          * If the delta tsc can't fit in the 32 bit after the multi shift,
11901          * we can't use the preemption timer.
11902          * It's possible that it fits on later vmentries, but checking
11903          * on every vmentry is costly so we just use an hrtimer.
11904          */
11905         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11906                 return -ERANGE;
11907
11908         vmx->hv_deadline_tsc = tscl + delta_tsc;
11909         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11910                         PIN_BASED_VMX_PREEMPTION_TIMER);
11911
11912         return delta_tsc == 0;
11913 }
11914
11915 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11916 {
11917         struct vcpu_vmx *vmx = to_vmx(vcpu);
11918         vmx->hv_deadline_tsc = -1;
11919         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11920                         PIN_BASED_VMX_PREEMPTION_TIMER);
11921 }
11922 #endif
11923
11924 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11925 {
11926         if (ple_gap)
11927                 shrink_ple_window(vcpu);
11928 }
11929
11930 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11931                                      struct kvm_memory_slot *slot)
11932 {
11933         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11934         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11935 }
11936
11937 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11938                                        struct kvm_memory_slot *slot)
11939 {
11940         kvm_mmu_slot_set_dirty(kvm, slot);
11941 }
11942
11943 static void vmx_flush_log_dirty(struct kvm *kvm)
11944 {
11945         kvm_flush_pml_buffers(kvm);
11946 }
11947
11948 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11949 {
11950         struct vmcs12 *vmcs12;
11951         struct vcpu_vmx *vmx = to_vmx(vcpu);
11952         gpa_t gpa;
11953         struct page *page = NULL;
11954         u64 *pml_address;
11955
11956         if (is_guest_mode(vcpu)) {
11957                 WARN_ON_ONCE(vmx->nested.pml_full);
11958
11959                 /*
11960                  * Check if PML is enabled for the nested guest.
11961                  * Whether eptp bit 6 is set is already checked
11962                  * as part of A/D emulation.
11963                  */
11964                 vmcs12 = get_vmcs12(vcpu);
11965                 if (!nested_cpu_has_pml(vmcs12))
11966                         return 0;
11967
11968                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11969                         vmx->nested.pml_full = true;
11970                         return 1;
11971                 }
11972
11973                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11974
11975                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11976                 if (is_error_page(page))
11977                         return 0;
11978
11979                 pml_address = kmap(page);
11980                 pml_address[vmcs12->guest_pml_index--] = gpa;
11981                 kunmap(page);
11982                 kvm_release_page_clean(page);
11983         }
11984
11985         return 0;
11986 }
11987
11988 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11989                                            struct kvm_memory_slot *memslot,
11990                                            gfn_t offset, unsigned long mask)
11991 {
11992         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11993 }
11994
11995 static void __pi_post_block(struct kvm_vcpu *vcpu)
11996 {
11997         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11998         struct pi_desc old, new;
11999         unsigned int dest;
12000
12001         do {
12002                 old.control = new.control = pi_desc->control;
12003                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12004                      "Wakeup handler not enabled while the VCPU is blocked\n");
12005
12006                 dest = cpu_physical_id(vcpu->cpu);
12007
12008                 if (x2apic_enabled())
12009                         new.ndst = dest;
12010                 else
12011                         new.ndst = (dest << 8) & 0xFF00;
12012
12013                 /* set 'NV' to 'notification vector' */
12014                 new.nv = POSTED_INTR_VECTOR;
12015         } while (cmpxchg64(&pi_desc->control, old.control,
12016                            new.control) != old.control);
12017
12018         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12019                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12020                 list_del(&vcpu->blocked_vcpu_list);
12021                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12022                 vcpu->pre_pcpu = -1;
12023         }
12024 }
12025
12026 /*
12027  * This routine does the following things for vCPU which is going
12028  * to be blocked if VT-d PI is enabled.
12029  * - Store the vCPU to the wakeup list, so when interrupts happen
12030  *   we can find the right vCPU to wake up.
12031  * - Change the Posted-interrupt descriptor as below:
12032  *      'NDST' <-- vcpu->pre_pcpu
12033  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12034  * - If 'ON' is set during this process, which means at least one
12035  *   interrupt is posted for this vCPU, we cannot block it, in
12036  *   this case, return 1, otherwise, return 0.
12037  *
12038  */
12039 static int pi_pre_block(struct kvm_vcpu *vcpu)
12040 {
12041         unsigned int dest;
12042         struct pi_desc old, new;
12043         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12044
12045         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12046                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
12047                 !kvm_vcpu_apicv_active(vcpu))
12048                 return 0;
12049
12050         WARN_ON(irqs_disabled());
12051         local_irq_disable();
12052         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12053                 vcpu->pre_pcpu = vcpu->cpu;
12054                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12055                 list_add_tail(&vcpu->blocked_vcpu_list,
12056                               &per_cpu(blocked_vcpu_on_cpu,
12057                                        vcpu->pre_pcpu));
12058                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12059         }
12060
12061         do {
12062                 old.control = new.control = pi_desc->control;
12063
12064                 WARN((pi_desc->sn == 1),
12065                      "Warning: SN field of posted-interrupts "
12066                      "is set before blocking\n");
12067
12068                 /*
12069                  * Since vCPU can be preempted during this process,
12070                  * vcpu->cpu could be different with pre_pcpu, we
12071                  * need to set pre_pcpu as the destination of wakeup
12072                  * notification event, then we can find the right vCPU
12073                  * to wakeup in wakeup handler if interrupts happen
12074                  * when the vCPU is in blocked state.
12075                  */
12076                 dest = cpu_physical_id(vcpu->pre_pcpu);
12077
12078                 if (x2apic_enabled())
12079                         new.ndst = dest;
12080                 else
12081                         new.ndst = (dest << 8) & 0xFF00;
12082
12083                 /* set 'NV' to 'wakeup vector' */
12084                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12085         } while (cmpxchg64(&pi_desc->control, old.control,
12086                            new.control) != old.control);
12087
12088         /* We should not block the vCPU if an interrupt is posted for it.  */
12089         if (pi_test_on(pi_desc) == 1)
12090                 __pi_post_block(vcpu);
12091
12092         local_irq_enable();
12093         return (vcpu->pre_pcpu == -1);
12094 }
12095
12096 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12097 {
12098         if (pi_pre_block(vcpu))
12099                 return 1;
12100
12101         if (kvm_lapic_hv_timer_in_use(vcpu))
12102                 kvm_lapic_switch_to_sw_timer(vcpu);
12103
12104         return 0;
12105 }
12106
12107 static void pi_post_block(struct kvm_vcpu *vcpu)
12108 {
12109         if (vcpu->pre_pcpu == -1)
12110                 return;
12111
12112         WARN_ON(irqs_disabled());
12113         local_irq_disable();
12114         __pi_post_block(vcpu);
12115         local_irq_enable();
12116 }
12117
12118 static void vmx_post_block(struct kvm_vcpu *vcpu)
12119 {
12120         if (kvm_x86_ops->set_hv_timer)
12121                 kvm_lapic_switch_to_hv_timer(vcpu);
12122
12123         pi_post_block(vcpu);
12124 }
12125
12126 /*
12127  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12128  *
12129  * @kvm: kvm
12130  * @host_irq: host irq of the interrupt
12131  * @guest_irq: gsi of the interrupt
12132  * @set: set or unset PI
12133  * returns 0 on success, < 0 on failure
12134  */
12135 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12136                               uint32_t guest_irq, bool set)
12137 {
12138         struct kvm_kernel_irq_routing_entry *e;
12139         struct kvm_irq_routing_table *irq_rt;
12140         struct kvm_lapic_irq irq;
12141         struct kvm_vcpu *vcpu;
12142         struct vcpu_data vcpu_info;
12143         int idx, ret = 0;
12144
12145         if (!kvm_arch_has_assigned_device(kvm) ||
12146                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12147                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12148                 return 0;
12149
12150         idx = srcu_read_lock(&kvm->irq_srcu);
12151         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12152         if (guest_irq >= irq_rt->nr_rt_entries ||
12153             hlist_empty(&irq_rt->map[guest_irq])) {
12154                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12155                              guest_irq, irq_rt->nr_rt_entries);
12156                 goto out;
12157         }
12158
12159         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12160                 if (e->type != KVM_IRQ_ROUTING_MSI)
12161                         continue;
12162                 /*
12163                  * VT-d PI cannot support posting multicast/broadcast
12164                  * interrupts to a vCPU, we still use interrupt remapping
12165                  * for these kind of interrupts.
12166                  *
12167                  * For lowest-priority interrupts, we only support
12168                  * those with single CPU as the destination, e.g. user
12169                  * configures the interrupts via /proc/irq or uses
12170                  * irqbalance to make the interrupts single-CPU.
12171                  *
12172                  * We will support full lowest-priority interrupt later.
12173                  */
12174
12175                 kvm_set_msi_irq(kvm, e, &irq);
12176                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12177                         /*
12178                          * Make sure the IRTE is in remapped mode if
12179                          * we don't handle it in posted mode.
12180                          */
12181                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12182                         if (ret < 0) {
12183                                 printk(KERN_INFO
12184                                    "failed to back to remapped mode, irq: %u\n",
12185                                    host_irq);
12186                                 goto out;
12187                         }
12188
12189                         continue;
12190                 }
12191
12192                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12193                 vcpu_info.vector = irq.vector;
12194
12195                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
12196                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12197
12198                 if (set)
12199                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12200                 else
12201                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12202
12203                 if (ret < 0) {
12204                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
12205                                         __func__);
12206                         goto out;
12207                 }
12208         }
12209
12210         ret = 0;
12211 out:
12212         srcu_read_unlock(&kvm->irq_srcu, idx);
12213         return ret;
12214 }
12215
12216 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12217 {
12218         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12219                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12220                         FEATURE_CONTROL_LMCE;
12221         else
12222                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12223                         ~FEATURE_CONTROL_LMCE;
12224 }
12225
12226 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12227 {
12228         /* we need a nested vmexit to enter SMM, postpone if run is pending */
12229         if (to_vmx(vcpu)->nested.nested_run_pending)
12230                 return 0;
12231         return 1;
12232 }
12233
12234 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12235 {
12236         struct vcpu_vmx *vmx = to_vmx(vcpu);
12237
12238         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12239         if (vmx->nested.smm.guest_mode)
12240                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12241
12242         vmx->nested.smm.vmxon = vmx->nested.vmxon;
12243         vmx->nested.vmxon = false;
12244         return 0;
12245 }
12246
12247 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12248 {
12249         struct vcpu_vmx *vmx = to_vmx(vcpu);
12250         int ret;
12251
12252         if (vmx->nested.smm.vmxon) {
12253                 vmx->nested.vmxon = true;
12254                 vmx->nested.smm.vmxon = false;
12255         }
12256
12257         if (vmx->nested.smm.guest_mode) {
12258                 vcpu->arch.hflags &= ~HF_SMM_MASK;
12259                 ret = enter_vmx_non_root_mode(vcpu, false);
12260                 vcpu->arch.hflags |= HF_SMM_MASK;
12261                 if (ret)
12262                         return ret;
12263
12264                 vmx->nested.smm.guest_mode = false;
12265         }
12266         return 0;
12267 }
12268
12269 static int enable_smi_window(struct kvm_vcpu *vcpu)
12270 {
12271         return 0;
12272 }
12273
12274 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12275         .cpu_has_kvm_support = cpu_has_kvm_support,
12276         .disabled_by_bios = vmx_disabled_by_bios,
12277         .hardware_setup = hardware_setup,
12278         .hardware_unsetup = hardware_unsetup,
12279         .check_processor_compatibility = vmx_check_processor_compat,
12280         .hardware_enable = hardware_enable,
12281         .hardware_disable = hardware_disable,
12282         .cpu_has_accelerated_tpr = report_flexpriority,
12283         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12284
12285         .vcpu_create = vmx_create_vcpu,
12286         .vcpu_free = vmx_free_vcpu,
12287         .vcpu_reset = vmx_vcpu_reset,
12288
12289         .prepare_guest_switch = vmx_save_host_state,
12290         .vcpu_load = vmx_vcpu_load,
12291         .vcpu_put = vmx_vcpu_put,
12292
12293         .update_bp_intercept = update_exception_bitmap,
12294         .get_msr = vmx_get_msr,
12295         .set_msr = vmx_set_msr,
12296         .get_segment_base = vmx_get_segment_base,
12297         .get_segment = vmx_get_segment,
12298         .set_segment = vmx_set_segment,
12299         .get_cpl = vmx_get_cpl,
12300         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12301         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12302         .decache_cr3 = vmx_decache_cr3,
12303         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12304         .set_cr0 = vmx_set_cr0,
12305         .set_cr3 = vmx_set_cr3,
12306         .set_cr4 = vmx_set_cr4,
12307         .set_efer = vmx_set_efer,
12308         .get_idt = vmx_get_idt,
12309         .set_idt = vmx_set_idt,
12310         .get_gdt = vmx_get_gdt,
12311         .set_gdt = vmx_set_gdt,
12312         .get_dr6 = vmx_get_dr6,
12313         .set_dr6 = vmx_set_dr6,
12314         .set_dr7 = vmx_set_dr7,
12315         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12316         .cache_reg = vmx_cache_reg,
12317         .get_rflags = vmx_get_rflags,
12318         .set_rflags = vmx_set_rflags,
12319
12320         .tlb_flush = vmx_flush_tlb,
12321
12322         .run = vmx_vcpu_run,
12323         .handle_exit = vmx_handle_exit,
12324         .skip_emulated_instruction = skip_emulated_instruction,
12325         .set_interrupt_shadow = vmx_set_interrupt_shadow,
12326         .get_interrupt_shadow = vmx_get_interrupt_shadow,
12327         .patch_hypercall = vmx_patch_hypercall,
12328         .set_irq = vmx_inject_irq,
12329         .set_nmi = vmx_inject_nmi,
12330         .queue_exception = vmx_queue_exception,
12331         .cancel_injection = vmx_cancel_injection,
12332         .interrupt_allowed = vmx_interrupt_allowed,
12333         .nmi_allowed = vmx_nmi_allowed,
12334         .get_nmi_mask = vmx_get_nmi_mask,
12335         .set_nmi_mask = vmx_set_nmi_mask,
12336         .enable_nmi_window = enable_nmi_window,
12337         .enable_irq_window = enable_irq_window,
12338         .update_cr8_intercept = update_cr8_intercept,
12339         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12340         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12341         .get_enable_apicv = vmx_get_enable_apicv,
12342         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12343         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12344         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12345         .hwapic_irr_update = vmx_hwapic_irr_update,
12346         .hwapic_isr_update = vmx_hwapic_isr_update,
12347         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12348         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12349
12350         .set_tss_addr = vmx_set_tss_addr,
12351         .get_tdp_level = get_ept_level,
12352         .get_mt_mask = vmx_get_mt_mask,
12353
12354         .get_exit_info = vmx_get_exit_info,
12355
12356         .get_lpage_level = vmx_get_lpage_level,
12357
12358         .cpuid_update = vmx_cpuid_update,
12359
12360         .rdtscp_supported = vmx_rdtscp_supported,
12361         .invpcid_supported = vmx_invpcid_supported,
12362
12363         .set_supported_cpuid = vmx_set_supported_cpuid,
12364
12365         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12366
12367         .write_tsc_offset = vmx_write_tsc_offset,
12368
12369         .set_tdp_cr3 = vmx_set_cr3,
12370
12371         .check_intercept = vmx_check_intercept,
12372         .handle_external_intr = vmx_handle_external_intr,
12373         .mpx_supported = vmx_mpx_supported,
12374         .xsaves_supported = vmx_xsaves_supported,
12375         .umip_emulated = vmx_umip_emulated,
12376
12377         .check_nested_events = vmx_check_nested_events,
12378
12379         .sched_in = vmx_sched_in,
12380
12381         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12382         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12383         .flush_log_dirty = vmx_flush_log_dirty,
12384         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12385         .write_log_dirty = vmx_write_pml_buffer,
12386
12387         .pre_block = vmx_pre_block,
12388         .post_block = vmx_post_block,
12389
12390         .pmu_ops = &intel_pmu_ops,
12391
12392         .update_pi_irte = vmx_update_pi_irte,
12393
12394 #ifdef CONFIG_X86_64
12395         .set_hv_timer = vmx_set_hv_timer,
12396         .cancel_hv_timer = vmx_cancel_hv_timer,
12397 #endif
12398
12399         .setup_mce = vmx_setup_mce,
12400
12401         .smi_allowed = vmx_smi_allowed,
12402         .pre_enter_smm = vmx_pre_enter_smm,
12403         .pre_leave_smm = vmx_pre_leave_smm,
12404         .enable_smi_window = enable_smi_window,
12405 };
12406
12407 static int __init vmx_init(void)
12408 {
12409         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12410                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12411         if (r)
12412                 return r;
12413
12414 #ifdef CONFIG_KEXEC_CORE
12415         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12416                            crash_vmclear_local_loaded_vmcss);
12417 #endif
12418
12419         return 0;
12420 }
12421
12422 static void __exit vmx_exit(void)
12423 {
12424 #ifdef CONFIG_KEXEC_CORE
12425         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12426         synchronize_rcu();
12427 #endif
12428
12429         kvm_exit();
12430 }
12431
12432 module_init(vmx_init)
12433 module_exit(vmx_exit)