arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/cpu.h>
  42 #include <asm/io.h>
  43 #include <asm/desc.h>
  44 #include <asm/vmx.h>
  45 #include <asm/virtext.h>
  46 #include <asm/mce.h>
  47 #include <asm/fpu/internal.h>
  48 #include <asm/perf_event.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kexec.h>
  51 #include <asm/apic.h>
  52 #include <asm/irq_remapping.h>
  53 #include <asm/mmu_context.h>
  54 #include <asm/spec-ctrl.h>
  55 #include <asm/mshyperv.h>
  56
  57 #include "trace.h"
  58 #include "pmu.h"
  59 #include "vmx_evmcs.h"
  60
  61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  62 #define __ex_clear(x, reg) \
  63         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  64
  65 MODULE_AUTHOR("Qumranet");
  66 MODULE_LICENSE("GPL");
  67
  68 static const struct x86_cpu_id vmx_cpu_id[] = {
  69         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  73
  74 static bool __read_mostly enable_vpid = 1;
  75 module_param_named(vpid, enable_vpid, bool, 0444);
  76
  77 static bool __read_mostly enable_vnmi = 1;
  78 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  79
  80 static bool __read_mostly flexpriority_enabled = 1;
  81 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept = 1;
  84 module_param_named(ept, enable_ept, bool, S_IRUGO);
  85
  86 static bool __read_mostly enable_unrestricted_guest = 1;
  87 module_param_named(unrestricted_guest,
  88                         enable_unrestricted_guest, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_ept_ad_bits = 1;
  91 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  92
  93 static bool __read_mostly emulate_invalid_guest_state = true;
  94 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  95
  96 static bool __read_mostly fasteoi = 1;
  97 module_param(fasteoi, bool, S_IRUGO);
  98
  99 static bool __read_mostly enable_apicv = 1;
 100 module_param(enable_apicv, bool, S_IRUGO);
 101
 102 static bool __read_mostly enable_shadow_vmcs = 1;
 103 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 104 /*
 105  * If nested=1, nested virtualization is supported, i.e., guests may use
 106  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 107  * use VMX instructions.
 108  */
 109 static bool __read_mostly nested = 0;
 110 module_param(nested, bool, S_IRUGO);
 111
 112 static u64 __read_mostly host_xss;
 113
 114 static bool __read_mostly enable_pml = 1;
 115 module_param_named(pml, enable_pml, bool, S_IRUGO);
 116
 117 #define MSR_TYPE_R      1
 118 #define MSR_TYPE_W      2
 119 #define MSR_TYPE_RW     3
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123 #define MSR_BITMAP_MODE_LM              4
 124
 125 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 126
 127 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 128 static int __read_mostly cpu_preemption_timer_multi;
 129 static bool __read_mostly enable_preemption_timer = 1;
 130 #ifdef CONFIG_X86_64
 131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 132 #endif
 133
 134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 136 #define KVM_VM_CR0_ALWAYS_ON                            \
 137         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 138          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 139 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 140         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 141          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 142
 143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 146
 147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 148
 149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 150
 151 /*
 152  * Hyper-V requires all of these, so mark them as supported even though
 153  * they are just treated the same as all-context.
 154  */
 155 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 156         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 157         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 158         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 159         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 160
 161 /*
 162  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 163  * ple_gap:    upper bound on the amount of time between two successive
 164  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 165  *             According to test, this time is usually smaller than 128 cycles.
 166  * ple_window: upper bound on the amount of time a guest is allowed to execute
 167  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 168  *             less than 2^12 cycles
 169  * Time is measured based on a counter that runs at the same rate as the TSC,
 170  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 171  */
 172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 173
 174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 175 module_param(ple_window, uint, 0444);
 176
 177 /* Default doubles per-vcpu window every exit. */
 178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 179 module_param(ple_window_grow, uint, 0444);
 180
 181 /* Default resets per-vcpu window every exit to ple_window. */
 182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 183 module_param(ple_window_shrink, uint, 0444);
 184
 185 /* Default is to compute the maximum so we can never overflow. */
 186 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 187 module_param(ple_window_max, uint, 0444);
 188
 189 extern const ulong vmx_return;
 190
 191 struct kvm_vmx {
 192         struct kvm kvm;
 193
 194         unsigned int tss_addr;
 195         bool ept_identity_pagetable_done;
 196         gpa_t ept_identity_map_addr;
 197 };
 198
 199 #define NR_AUTOLOAD_MSRS 8
 200
 201 struct vmcs {
 202         u32 revision_id;
 203         u32 abort;
 204         char data[0];
 205 };
 206
 207 /*
 208  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 209  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 210  * loaded on this CPU (so we can clear them if the CPU goes down).
 211  */
 212 struct loaded_vmcs {
 213         struct vmcs *vmcs;
 214         struct vmcs *shadow_vmcs;
 215         int cpu;
 216         bool launched;
 217         bool nmi_known_unmasked;
 218         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 219         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 220         /* Support for vnmi-less CPUs */
 221         int soft_vnmi_blocked;
 222         ktime_t entry_time;
 223         s64 vnmi_blocked_time;
 224         unsigned long *msr_bitmap;
 225         struct list_head loaded_vmcss_on_cpu_link;
 226 };
 227
 228 struct shared_msr_entry {
 229         unsigned index;
 230         u64 data;
 231         u64 mask;
 232 };
 233
 234 /*
 235  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 236  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 237  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 238  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 239  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 240  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 241  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 242  * underlying hardware which will be used to run L2.
 243  * This structure is packed to ensure that its layout is identical across
 244  * machines (necessary for live migration).
 245  * If there are changes in this struct, VMCS12_REVISION must be changed.
 246  */
 247 typedef u64 natural_width;
 248 struct __packed vmcs12 {
 249         /* According to the Intel spec, a VMCS region must start with the
 250          * following two fields. Then follow implementation-specific data.
 251          */
 252         u32 revision_id;
 253         u32 abort;
 254
 255         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 256         u32 padding[7]; /* room for future expansion */
 257
 258         u64 io_bitmap_a;
 259         u64 io_bitmap_b;
 260         u64 msr_bitmap;
 261         u64 vm_exit_msr_store_addr;
 262         u64 vm_exit_msr_load_addr;
 263         u64 vm_entry_msr_load_addr;
 264         u64 tsc_offset;
 265         u64 virtual_apic_page_addr;
 266         u64 apic_access_addr;
 267         u64 posted_intr_desc_addr;
 268         u64 vm_function_control;
 269         u64 ept_pointer;
 270         u64 eoi_exit_bitmap0;
 271         u64 eoi_exit_bitmap1;
 272         u64 eoi_exit_bitmap2;
 273         u64 eoi_exit_bitmap3;
 274         u64 eptp_list_address;
 275         u64 xss_exit_bitmap;
 276         u64 guest_physical_address;
 277         u64 vmcs_link_pointer;
 278         u64 pml_address;
 279         u64 guest_ia32_debugctl;
 280         u64 guest_ia32_pat;
 281         u64 guest_ia32_efer;
 282         u64 guest_ia32_perf_global_ctrl;
 283         u64 guest_pdptr0;
 284         u64 guest_pdptr1;
 285         u64 guest_pdptr2;
 286         u64 guest_pdptr3;
 287         u64 guest_bndcfgs;
 288         u64 host_ia32_pat;
 289         u64 host_ia32_efer;
 290         u64 host_ia32_perf_global_ctrl;
 291         u64 padding64[8]; /* room for future expansion */
 292         /*
 293          * To allow migration of L1 (complete with its L2 guests) between
 294          * machines of different natural widths (32 or 64 bit), we cannot have
 295          * unsigned long fields with no explict size. We use u64 (aliased
 296          * natural_width) instead. Luckily, x86 is little-endian.
 297          */
 298         natural_width cr0_guest_host_mask;
 299         natural_width cr4_guest_host_mask;
 300         natural_width cr0_read_shadow;
 301         natural_width cr4_read_shadow;
 302         natural_width cr3_target_value0;
 303         natural_width cr3_target_value1;
 304         natural_width cr3_target_value2;
 305         natural_width cr3_target_value3;
 306         natural_width exit_qualification;
 307         natural_width guest_linear_address;
 308         natural_width guest_cr0;
 309         natural_width guest_cr3;
 310         natural_width guest_cr4;
 311         natural_width guest_es_base;
 312         natural_width guest_cs_base;
 313         natural_width guest_ss_base;
 314         natural_width guest_ds_base;
 315         natural_width guest_fs_base;
 316         natural_width guest_gs_base;
 317         natural_width guest_ldtr_base;
 318         natural_width guest_tr_base;
 319         natural_width guest_gdtr_base;
 320         natural_width guest_idtr_base;
 321         natural_width guest_dr7;
 322         natural_width guest_rsp;
 323         natural_width guest_rip;
 324         natural_width guest_rflags;
 325         natural_width guest_pending_dbg_exceptions;
 326         natural_width guest_sysenter_esp;
 327         natural_width guest_sysenter_eip;
 328         natural_width host_cr0;
 329         natural_width host_cr3;
 330         natural_width host_cr4;
 331         natural_width host_fs_base;
 332         natural_width host_gs_base;
 333         natural_width host_tr_base;
 334         natural_width host_gdtr_base;
 335         natural_width host_idtr_base;
 336         natural_width host_ia32_sysenter_esp;
 337         natural_width host_ia32_sysenter_eip;
 338         natural_width host_rsp;
 339         natural_width host_rip;
 340         natural_width paddingl[8]; /* room for future expansion */
 341         u32 pin_based_vm_exec_control;
 342         u32 cpu_based_vm_exec_control;
 343         u32 exception_bitmap;
 344         u32 page_fault_error_code_mask;
 345         u32 page_fault_error_code_match;
 346         u32 cr3_target_count;
 347         u32 vm_exit_controls;
 348         u32 vm_exit_msr_store_count;
 349         u32 vm_exit_msr_load_count;
 350         u32 vm_entry_controls;
 351         u32 vm_entry_msr_load_count;
 352         u32 vm_entry_intr_info_field;
 353         u32 vm_entry_exception_error_code;
 354         u32 vm_entry_instruction_len;
 355         u32 tpr_threshold;
 356         u32 secondary_vm_exec_control;
 357         u32 vm_instruction_error;
 358         u32 vm_exit_reason;
 359         u32 vm_exit_intr_info;
 360         u32 vm_exit_intr_error_code;
 361         u32 idt_vectoring_info_field;
 362         u32 idt_vectoring_error_code;
 363         u32 vm_exit_instruction_len;
 364         u32 vmx_instruction_info;
 365         u32 guest_es_limit;
 366         u32 guest_cs_limit;
 367         u32 guest_ss_limit;
 368         u32 guest_ds_limit;
 369         u32 guest_fs_limit;
 370         u32 guest_gs_limit;
 371         u32 guest_ldtr_limit;
 372         u32 guest_tr_limit;
 373         u32 guest_gdtr_limit;
 374         u32 guest_idtr_limit;
 375         u32 guest_es_ar_bytes;
 376         u32 guest_cs_ar_bytes;
 377         u32 guest_ss_ar_bytes;
 378         u32 guest_ds_ar_bytes;
 379         u32 guest_fs_ar_bytes;
 380         u32 guest_gs_ar_bytes;
 381         u32 guest_ldtr_ar_bytes;
 382         u32 guest_tr_ar_bytes;
 383         u32 guest_interruptibility_info;
 384         u32 guest_activity_state;
 385         u32 guest_sysenter_cs;
 386         u32 host_ia32_sysenter_cs;
 387         u32 vmx_preemption_timer_value;
 388         u32 padding32[7]; /* room for future expansion */
 389         u16 virtual_processor_id;
 390         u16 posted_intr_nv;
 391         u16 guest_es_selector;
 392         u16 guest_cs_selector;
 393         u16 guest_ss_selector;
 394         u16 guest_ds_selector;
 395         u16 guest_fs_selector;
 396         u16 guest_gs_selector;
 397         u16 guest_ldtr_selector;
 398         u16 guest_tr_selector;
 399         u16 guest_intr_status;
 400         u16 guest_pml_index;
 401         u16 host_es_selector;
 402         u16 host_cs_selector;
 403         u16 host_ss_selector;
 404         u16 host_ds_selector;
 405         u16 host_fs_selector;
 406         u16 host_gs_selector;
 407         u16 host_tr_selector;
 408 };
 409
 410 /*
 411  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 412  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 413  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 414  */
 415 #define VMCS12_REVISION 0x11e57ed0
 416
 417 /*
 418  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 419  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 420  * current implementation, 4K are reserved to avoid future complications.
 421  */
 422 #define VMCS12_SIZE 0x1000
 423
 424 /*
 425  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 426  * supported VMCS12 field encoding.
 427  */
 428 #define VMCS12_MAX_FIELD_INDEX 0x17
 429
 430 struct nested_vmx_msrs {
 431         /*
 432          * We only store the "true" versions of the VMX capability MSRs. We
 433          * generate the "non-true" versions by setting the must-be-1 bits
 434          * according to the SDM.
 435          */
 436         u32 procbased_ctls_low;
 437         u32 procbased_ctls_high;
 438         u32 secondary_ctls_low;
 439         u32 secondary_ctls_high;
 440         u32 pinbased_ctls_low;
 441         u32 pinbased_ctls_high;
 442         u32 exit_ctls_low;
 443         u32 exit_ctls_high;
 444         u32 entry_ctls_low;
 445         u32 entry_ctls_high;
 446         u32 misc_low;
 447         u32 misc_high;
 448         u32 ept_caps;
 449         u32 vpid_caps;
 450         u64 basic;
 451         u64 cr0_fixed0;
 452         u64 cr0_fixed1;
 453         u64 cr4_fixed0;
 454         u64 cr4_fixed1;
 455         u64 vmcs_enum;
 456         u64 vmfunc_controls;
 457 };
 458
 459 /*
 460  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 461  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 462  */
 463 struct nested_vmx {
 464         /* Has the level1 guest done vmxon? */
 465         bool vmxon;
 466         gpa_t vmxon_ptr;
 467         bool pml_full;
 468
 469         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 470         gpa_t current_vmptr;
 471         /*
 472          * Cache of the guest's VMCS, existing outside of guest memory.
 473          * Loaded from guest memory during VMPTRLD. Flushed to guest
 474          * memory during VMCLEAR and VMPTRLD.
 475          */
 476         struct vmcs12 *cached_vmcs12;
 477         /*
 478          * Indicates if the shadow vmcs must be updated with the
 479          * data hold by vmcs12
 480          */
 481         bool sync_shadow_vmcs;
 482         bool dirty_vmcs12;
 483
 484         bool change_vmcs01_virtual_x2apic_mode;
 485         /* L2 must run next, and mustn't decide to exit to L1. */
 486         bool nested_run_pending;
 487
 488         struct loaded_vmcs vmcs02;
 489
 490         /*
 491          * Guest pages referred to in the vmcs02 with host-physical
 492          * pointers, so we must keep them pinned while L2 runs.
 493          */
 494         struct page *apic_access_page;
 495         struct page *virtual_apic_page;
 496         struct page *pi_desc_page;
 497         struct pi_desc *pi_desc;
 498         bool pi_pending;
 499         u16 posted_intr_nv;
 500
 501         struct hrtimer preemption_timer;
 502         bool preemption_timer_expired;
 503
 504         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 505         u64 vmcs01_debugctl;
 506
 507         u16 vpid02;
 508         u16 last_vpid;
 509
 510         struct nested_vmx_msrs msrs;
 511
 512         /* SMM related state */
 513         struct {
 514                 /* in VMX operation on SMM entry? */
 515                 bool vmxon;
 516                 /* in guest mode on SMM entry? */
 517                 bool guest_mode;
 518         } smm;
 519 };
 520
 521 #define POSTED_INTR_ON  0
 522 #define POSTED_INTR_SN  1
 523
 524 /* Posted-Interrupt Descriptor */
 525 struct pi_desc {
 526         u32 pir[8];     /* Posted interrupt requested */
 527         union {
 528                 struct {
 529                                 /* bit 256 - Outstanding Notification */
 530                         u16     on      : 1,
 531                                 /* bit 257 - Suppress Notification */
 532                                 sn      : 1,
 533                                 /* bit 271:258 - Reserved */
 534                                 rsvd_1  : 14;
 535                                 /* bit 279:272 - Notification Vector */
 536                         u8      nv;
 537                                 /* bit 287:280 - Reserved */
 538                         u8      rsvd_2;
 539                                 /* bit 319:288 - Notification Destination */
 540                         u32     ndst;
 541                 };
 542                 u64 control;
 543         };
 544         u32 rsvd[6];
 545 } __aligned(64);
 546
 547 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 548 {
 549         return test_and_set_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 554 {
 555         return test_and_clear_bit(POSTED_INTR_ON,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 560 {
 561         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 562 }
 563
 564 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 565 {
 566         return clear_bit(POSTED_INTR_SN,
 567                         (unsigned long *)&pi_desc->control);
 568 }
 569
 570 static inline void pi_set_sn(struct pi_desc *pi_desc)
 571 {
 572         return set_bit(POSTED_INTR_SN,
 573                         (unsigned long *)&pi_desc->control);
 574 }
 575
 576 static inline void pi_clear_on(struct pi_desc *pi_desc)
 577 {
 578         clear_bit(POSTED_INTR_ON,
 579                   (unsigned long *)&pi_desc->control);
 580 }
 581
 582 static inline int pi_test_on(struct pi_desc *pi_desc)
 583 {
 584         return test_bit(POSTED_INTR_ON,
 585                         (unsigned long *)&pi_desc->control);
 586 }
 587
 588 static inline int pi_test_sn(struct pi_desc *pi_desc)
 589 {
 590         return test_bit(POSTED_INTR_SN,
 591                         (unsigned long *)&pi_desc->control);
 592 }
 593
 594 struct vcpu_vmx {
 595         struct kvm_vcpu       vcpu;
 596         unsigned long         host_rsp;
 597         u8                    fail;
 598         u8                    msr_bitmap_mode;
 599         u32                   exit_intr_info;
 600         u32                   idt_vectoring_info;
 601         ulong                 rflags;
 602         struct shared_msr_entry *guest_msrs;
 603         int                   nmsrs;
 604         int                   save_nmsrs;
 605         unsigned long         host_idt_base;
 606 #ifdef CONFIG_X86_64
 607         u64                   msr_host_kernel_gs_base;
 608         u64                   msr_guest_kernel_gs_base;
 609 #endif
 610
 611         u64                   arch_capabilities;
 612         u64                   spec_ctrl;
 613
 614         u32 vm_entry_controls_shadow;
 615         u32 vm_exit_controls_shadow;
 616         u32 secondary_exec_control;
 617
 618         /*
 619          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 620          * non-nested (L1) guest, it always points to vmcs01. For a nested
 621          * guest (L2), it points to a different VMCS.
 622          */
 623         struct loaded_vmcs    vmcs01;
 624         struct loaded_vmcs   *loaded_vmcs;
 625         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 626         struct msr_autoload {
 627                 unsigned nr;
 628                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 629                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 630         } msr_autoload;
 631         struct {
 632                 int           loaded;
 633                 u16           fs_sel, gs_sel, ldt_sel;
 634 #ifdef CONFIG_X86_64
 635                 u16           ds_sel, es_sel;
 636 #endif
 637                 int           gs_ldt_reload_needed;
 638                 int           fs_reload_needed;
 639                 u64           msr_host_bndcfgs;
 640         } host_state;
 641         struct {
 642                 int vm86_active;
 643                 ulong save_rflags;
 644                 struct kvm_segment segs[8];
 645         } rmode;
 646         struct {
 647                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 648                 struct kvm_save_segment {
 649                         u16 selector;
 650                         unsigned long base;
 651                         u32 limit;
 652                         u32 ar;
 653                 } seg[8];
 654         } segment_cache;
 655         int vpid;
 656         bool emulation_required;
 657
 658         u32 exit_reason;
 659
 660         /* Posted interrupt descriptor */
 661         struct pi_desc pi_desc;
 662
 663         /* Support for a guest hypervisor (nested VMX) */
 664         struct nested_vmx nested;
 665
 666         /* Dynamic PLE window. */
 667         int ple_window;
 668         bool ple_window_dirty;
 669
 670         /* Support for PML */
 671 #define PML_ENTITY_NUM          512
 672         struct page *pml_pg;
 673
 674         /* apic deadline value in host tsc */
 675         u64 hv_deadline_tsc;
 676
 677         u64 current_tsc_ratio;
 678
 679         u32 host_pkru;
 680
 681         unsigned long host_debugctlmsr;
 682
 683         /*
 684          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 685          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 686          * in msr_ia32_feature_control_valid_bits.
 687          */
 688         u64 msr_ia32_feature_control;
 689         u64 msr_ia32_feature_control_valid_bits;
 690 };
 691
 692 enum segment_cache_field {
 693         SEG_FIELD_SEL = 0,
 694         SEG_FIELD_BASE = 1,
 695         SEG_FIELD_LIMIT = 2,
 696         SEG_FIELD_AR = 3,
 697
 698         SEG_FIELD_NR = 4
 699 };
 700
 701 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 702 {
 703         return container_of(kvm, struct kvm_vmx, kvm);
 704 }
 705
 706 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 707 {
 708         return container_of(vcpu, struct vcpu_vmx, vcpu);
 709 }
 710
 711 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 712 {
 713         return &(to_vmx(vcpu)->pi_desc);
 714 }
 715
 716 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
 717 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 718 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
 719 #define FIELD64(number, name)                                           \
 720         FIELD(number, name),                                            \
 721         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
 722
 723
 724 static u16 shadow_read_only_fields[] = {
 725 #define SHADOW_FIELD_RO(x) x,
 726 #include "vmx_shadow_fields.h"
 727 };
 728 static int max_shadow_read_only_fields =
 729         ARRAY_SIZE(shadow_read_only_fields);
 730
 731 static u16 shadow_read_write_fields[] = {
 732 #define SHADOW_FIELD_RW(x) x,
 733 #include "vmx_shadow_fields.h"
 734 };
 735 static int max_shadow_read_write_fields =
 736         ARRAY_SIZE(shadow_read_write_fields);
 737
 738 static const unsigned short vmcs_field_to_offset_table[] = {
 739         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 740         FIELD(POSTED_INTR_NV, posted_intr_nv),
 741         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 742         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 743         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 744         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 745         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 746         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 747         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 748         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 749         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 750         FIELD(GUEST_PML_INDEX, guest_pml_index),
 751         FIELD(HOST_ES_SELECTOR, host_es_selector),
 752         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 753         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 754         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 755         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 756         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 757         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 758         FIELD64(IO_BITMAP_A, io_bitmap_a),
 759         FIELD64(IO_BITMAP_B, io_bitmap_b),
 760         FIELD64(MSR_BITMAP, msr_bitmap),
 761         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 762         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 763         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 764         FIELD64(TSC_OFFSET, tsc_offset),
 765         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 766         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 767         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 768         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 775         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 776         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 777         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 778         FIELD64(PML_ADDRESS, pml_address),
 779         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 780         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 781         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 782         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 783         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 784         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 785         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 786         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 787         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 788         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 789         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 790         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 791         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 792         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 793         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 794         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 795         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 796         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 797         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 798         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 799         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 800         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 801         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 802         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 803         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 804         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 805         FIELD(TPR_THRESHOLD, tpr_threshold),
 806         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 807         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 808         FIELD(VM_EXIT_REASON, vm_exit_reason),
 809         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 810         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 811         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 812         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 813         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 814         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 815         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 816         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 817         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 818         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 819         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 820         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 821         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 822         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 823         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 824         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 825         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 826         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 827         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 828         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 829         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 830         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 831         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 832         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 833         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 834         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 835         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 836         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 837         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 838         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 839         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 840         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 841         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 842         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 843         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 844         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 845         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 846         FIELD(EXIT_QUALIFICATION, exit_qualification),
 847         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 848         FIELD(GUEST_CR0, guest_cr0),
 849         FIELD(GUEST_CR3, guest_cr3),
 850         FIELD(GUEST_CR4, guest_cr4),
 851         FIELD(GUEST_ES_BASE, guest_es_base),
 852         FIELD(GUEST_CS_BASE, guest_cs_base),
 853         FIELD(GUEST_SS_BASE, guest_ss_base),
 854         FIELD(GUEST_DS_BASE, guest_ds_base),
 855         FIELD(GUEST_FS_BASE, guest_fs_base),
 856         FIELD(GUEST_GS_BASE, guest_gs_base),
 857         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 858         FIELD(GUEST_TR_BASE, guest_tr_base),
 859         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 860         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 861         FIELD(GUEST_DR7, guest_dr7),
 862         FIELD(GUEST_RSP, guest_rsp),
 863         FIELD(GUEST_RIP, guest_rip),
 864         FIELD(GUEST_RFLAGS, guest_rflags),
 865         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 866         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 867         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 868         FIELD(HOST_CR0, host_cr0),
 869         FIELD(HOST_CR3, host_cr3),
 870         FIELD(HOST_CR4, host_cr4),
 871         FIELD(HOST_FS_BASE, host_fs_base),
 872         FIELD(HOST_GS_BASE, host_gs_base),
 873         FIELD(HOST_TR_BASE, host_tr_base),
 874         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 875         FIELD(HOST_IDTR_BASE, host_idtr_base),
 876         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 877         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 878         FIELD(HOST_RSP, host_rsp),
 879         FIELD(HOST_RIP, host_rip),
 880 };
 881
 882 static inline short vmcs_field_to_offset(unsigned long field)
 883 {
 884         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
 885         unsigned short offset;
 886         unsigned index;
 887
 888         if (field >> 15)
 889                 return -ENOENT;
 890
 891         index = ROL16(field, 6);
 892         if (index >= size)
 893                 return -ENOENT;
 894
 895         index = array_index_nospec(index, size);
 896         offset = vmcs_field_to_offset_table[index];
 897         if (offset == 0)
 898                 return -ENOENT;
 899         return offset;
 900 }
 901
 902 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 903 {
 904         return to_vmx(vcpu)->nested.cached_vmcs12;
 905 }
 906
 907 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 908 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 909 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 910 static bool vmx_xsaves_supported(void);
 911 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 912                             struct kvm_segment *var, int seg);
 913 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 914                             struct kvm_segment *var, int seg);
 915 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 916 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 917 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 918 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 919 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 920 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 921                                             u16 error_code);
 922 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 923 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 924                                                           u32 msr, int type);
 925
 926 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 927 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 928 /*
 929  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 930  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 931  */
 932 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 933
 934 /*
 935  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 936  * can find which vCPU should be waken up.
 937  */
 938 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 939 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 940
 941 enum {
 942         VMX_VMREAD_BITMAP,
 943         VMX_VMWRITE_BITMAP,
 944         VMX_BITMAP_NR
 945 };
 946
 947 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 948
 949 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 950 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 951
 952 static bool cpu_has_load_ia32_efer;
 953 static bool cpu_has_load_perf_global_ctrl;
 954
 955 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 956 static DEFINE_SPINLOCK(vmx_vpid_lock);
 957
 958 static struct vmcs_config {
 959         int size;
 960         int order;
 961         u32 basic_cap;
 962         u32 revision_id;
 963         u32 pin_based_exec_ctrl;
 964         u32 cpu_based_exec_ctrl;
 965         u32 cpu_based_2nd_exec_ctrl;
 966         u32 vmexit_ctrl;
 967         u32 vmentry_ctrl;
 968         struct nested_vmx_msrs nested;
 969 } vmcs_config;
 970
 971 static struct vmx_capability {
 972         u32 ept;
 973         u32 vpid;
 974 } vmx_capability;
 975
 976 #define VMX_SEGMENT_FIELD(seg)                                  \
 977         [VCPU_SREG_##seg] = {                                   \
 978                 .selector = GUEST_##seg##_SELECTOR,             \
 979                 .base = GUEST_##seg##_BASE,                     \
 980                 .limit = GUEST_##seg##_LIMIT,                   \
 981                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 982         }
 983
 984 static const struct kvm_vmx_segment_field {
 985         unsigned selector;
 986         unsigned base;
 987         unsigned limit;
 988         unsigned ar_bytes;
 989 } kvm_vmx_segment_fields[] = {
 990         VMX_SEGMENT_FIELD(CS),
 991         VMX_SEGMENT_FIELD(DS),
 992         VMX_SEGMENT_FIELD(ES),
 993         VMX_SEGMENT_FIELD(FS),
 994         VMX_SEGMENT_FIELD(GS),
 995         VMX_SEGMENT_FIELD(SS),
 996         VMX_SEGMENT_FIELD(TR),
 997         VMX_SEGMENT_FIELD(LDTR),
 998 };
 999
1000 static u64 host_efer;
1001
1002 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1003
1004 /*
1005  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1006  * away by decrementing the array size.
1007  */
1008 static const u32 vmx_msr_index[] = {
1009 #ifdef CONFIG_X86_64
1010         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1011 #endif
1012         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1013 };
1014
1015 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1016
1017 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1018
1019 #define KVM_EVMCS_VERSION 1
1020
1021 #if IS_ENABLED(CONFIG_HYPERV)
1022 static bool __read_mostly enlightened_vmcs = true;
1023 module_param(enlightened_vmcs, bool, 0444);
1024
1025 static inline void evmcs_write64(unsigned long field, u64 value)
1026 {
1027         u16 clean_field;
1028         int offset = get_evmcs_offset(field, &clean_field);
1029
1030         if (offset < 0)
1031                 return;
1032
1033         *(u64 *)((char *)current_evmcs + offset) = value;
1034
1035         current_evmcs->hv_clean_fields &= ~clean_field;
1036 }
1037
1038 static inline void evmcs_write32(unsigned long field, u32 value)
1039 {
1040         u16 clean_field;
1041         int offset = get_evmcs_offset(field, &clean_field);
1042
1043         if (offset < 0)
1044                 return;
1045
1046         *(u32 *)((char *)current_evmcs + offset) = value;
1047         current_evmcs->hv_clean_fields &= ~clean_field;
1048 }
1049
1050 static inline void evmcs_write16(unsigned long field, u16 value)
1051 {
1052         u16 clean_field;
1053         int offset = get_evmcs_offset(field, &clean_field);
1054
1055         if (offset < 0)
1056                 return;
1057
1058         *(u16 *)((char *)current_evmcs + offset) = value;
1059         current_evmcs->hv_clean_fields &= ~clean_field;
1060 }
1061
1062 static inline u64 evmcs_read64(unsigned long field)
1063 {
1064         int offset = get_evmcs_offset(field, NULL);
1065
1066         if (offset < 0)
1067                 return 0;
1068
1069         return *(u64 *)((char *)current_evmcs + offset);
1070 }
1071
1072 static inline u32 evmcs_read32(unsigned long field)
1073 {
1074         int offset = get_evmcs_offset(field, NULL);
1075
1076         if (offset < 0)
1077                 return 0;
1078
1079         return *(u32 *)((char *)current_evmcs + offset);
1080 }
1081
1082 static inline u16 evmcs_read16(unsigned long field)
1083 {
1084         int offset = get_evmcs_offset(field, NULL);
1085
1086         if (offset < 0)
1087                 return 0;
1088
1089         return *(u16 *)((char *)current_evmcs + offset);
1090 }
1091
1092 static void evmcs_load(u64 phys_addr)
1093 {
1094         struct hv_vp_assist_page *vp_ap =
1095                 hv_get_vp_assist_page(smp_processor_id());
1096
1097         vp_ap->current_nested_vmcs = phys_addr;
1098         vp_ap->enlighten_vmentry = 1;
1099 }
1100
1101 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1102 {
1103         /*
1104          * Enlightened VMCSv1 doesn't support these:
1105          *
1106          *      POSTED_INTR_NV                  = 0x00000002,
1107          *      GUEST_INTR_STATUS               = 0x00000810,
1108          *      APIC_ACCESS_ADDR                = 0x00002014,
1109          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1110          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1111          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1112          *      EOI_EXIT_BITMAP2                = 0x00002020,
1113          *      EOI_EXIT_BITMAP3                = 0x00002022,
1114          */
1115         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1116         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1117                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1118         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1119                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1120         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1121                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1122
1123         /*
1124          *      GUEST_PML_INDEX                 = 0x00000812,
1125          *      PML_ADDRESS                     = 0x0000200e,
1126          */
1127         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1128
1129         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1130         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1131
1132         /*
1133          *      EPTP_LIST_ADDRESS               = 0x00002024,
1134          *      VMREAD_BITMAP                   = 0x00002026,
1135          *      VMWRITE_BITMAP                  = 0x00002028,
1136          */
1137         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1138
1139         /*
1140          *      TSC_MULTIPLIER                  = 0x00002032,
1141          */
1142         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1143
1144         /*
1145          *      PLE_GAP                         = 0x00004020,
1146          *      PLE_WINDOW                      = 0x00004022,
1147          */
1148         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1149
1150         /*
1151          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1152          */
1153         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1154
1155         /*
1156          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1157          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1158          */
1159         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1160         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1161
1162         /*
1163          * Currently unsupported in KVM:
1164          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1165          */
1166 }
1167 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1168 static inline void evmcs_write64(unsigned long field, u64 value) {}
1169 static inline void evmcs_write32(unsigned long field, u32 value) {}
1170 static inline void evmcs_write16(unsigned long field, u16 value) {}
1171 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1172 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1173 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1174 static inline void evmcs_load(u64 phys_addr) {}
1175 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1176 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1177
1178 static inline bool is_exception_n(u32 intr_info, u8 vector)
1179 {
1180         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1181                              INTR_INFO_VALID_MASK)) ==
1182                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1183 }
1184
1185 static inline bool is_debug(u32 intr_info)
1186 {
1187         return is_exception_n(intr_info, DB_VECTOR);
1188 }
1189
1190 static inline bool is_breakpoint(u32 intr_info)
1191 {
1192         return is_exception_n(intr_info, BP_VECTOR);
1193 }
1194
1195 static inline bool is_page_fault(u32 intr_info)
1196 {
1197         return is_exception_n(intr_info, PF_VECTOR);
1198 }
1199
1200 static inline bool is_no_device(u32 intr_info)
1201 {
1202         return is_exception_n(intr_info, NM_VECTOR);
1203 }
1204
1205 static inline bool is_invalid_opcode(u32 intr_info)
1206 {
1207         return is_exception_n(intr_info, UD_VECTOR);
1208 }
1209
1210 static inline bool is_gp_fault(u32 intr_info)
1211 {
1212         return is_exception_n(intr_info, GP_VECTOR);
1213 }
1214
1215 static inline bool is_external_interrupt(u32 intr_info)
1216 {
1217         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1218                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1219 }
1220
1221 static inline bool is_machine_check(u32 intr_info)
1222 {
1223         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1224                              INTR_INFO_VALID_MASK)) ==
1225                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1226 }
1227
1228 /* Undocumented: icebp/int1 */
1229 static inline bool is_icebp(u32 intr_info)
1230 {
1231         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1232                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1233 }
1234
1235 static inline bool cpu_has_vmx_msr_bitmap(void)
1236 {
1237         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1238 }
1239
1240 static inline bool cpu_has_vmx_tpr_shadow(void)
1241 {
1242         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1243 }
1244
1245 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1246 {
1247         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1248 }
1249
1250 static inline bool cpu_has_secondary_exec_ctrls(void)
1251 {
1252         return vmcs_config.cpu_based_exec_ctrl &
1253                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1254 }
1255
1256 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1257 {
1258         return vmcs_config.cpu_based_2nd_exec_ctrl &
1259                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1260 }
1261
1262 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1263 {
1264         return vmcs_config.cpu_based_2nd_exec_ctrl &
1265                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1266 }
1267
1268 static inline bool cpu_has_vmx_apic_register_virt(void)
1269 {
1270         return vmcs_config.cpu_based_2nd_exec_ctrl &
1271                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1272 }
1273
1274 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1275 {
1276         return vmcs_config.cpu_based_2nd_exec_ctrl &
1277                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1278 }
1279
1280 /*
1281  * Comment's format: document - errata name - stepping - processor name.
1282  * Refer from
1283  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1284  */
1285 static u32 vmx_preemption_cpu_tfms[] = {
1286 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1287 0x000206E6,
1288 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1289 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1290 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1291 0x00020652,
1292 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1293 0x00020655,
1294 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1295 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1296 /*
1297  * 320767.pdf - AAP86  - B1 -
1298  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1299  */
1300 0x000106E5,
1301 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1302 0x000106A0,
1303 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1304 0x000106A1,
1305 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1306 0x000106A4,
1307  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1308  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1309  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1310 0x000106A5,
1311 };
1312
1313 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1314 {
1315         u32 eax = cpuid_eax(0x00000001), i;
1316
1317         /* Clear the reserved bits */
1318         eax &= ~(0x3U << 14 | 0xfU << 28);
1319         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1320                 if (eax == vmx_preemption_cpu_tfms[i])
1321                         return true;
1322
1323         return false;
1324 }
1325
1326 static inline bool cpu_has_vmx_preemption_timer(void)
1327 {
1328         return vmcs_config.pin_based_exec_ctrl &
1329                 PIN_BASED_VMX_PREEMPTION_TIMER;
1330 }
1331
1332 static inline bool cpu_has_vmx_posted_intr(void)
1333 {
1334         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1335                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1336 }
1337
1338 static inline bool cpu_has_vmx_apicv(void)
1339 {
1340         return cpu_has_vmx_apic_register_virt() &&
1341                 cpu_has_vmx_virtual_intr_delivery() &&
1342                 cpu_has_vmx_posted_intr();
1343 }
1344
1345 static inline bool cpu_has_vmx_flexpriority(void)
1346 {
1347         return cpu_has_vmx_tpr_shadow() &&
1348                 cpu_has_vmx_virtualize_apic_accesses();
1349 }
1350
1351 static inline bool cpu_has_vmx_ept_execute_only(void)
1352 {
1353         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1354 }
1355
1356 static inline bool cpu_has_vmx_ept_2m_page(void)
1357 {
1358         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1359 }
1360
1361 static inline bool cpu_has_vmx_ept_1g_page(void)
1362 {
1363         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1364 }
1365
1366 static inline bool cpu_has_vmx_ept_4levels(void)
1367 {
1368         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1369 }
1370
1371 static inline bool cpu_has_vmx_ept_mt_wb(void)
1372 {
1373         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1374 }
1375
1376 static inline bool cpu_has_vmx_ept_5levels(void)
1377 {
1378         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1379 }
1380
1381 static inline bool cpu_has_vmx_ept_ad_bits(void)
1382 {
1383         return vmx_capability.ept & VMX_EPT_AD_BIT;
1384 }
1385
1386 static inline bool cpu_has_vmx_invept_context(void)
1387 {
1388         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1389 }
1390
1391 static inline bool cpu_has_vmx_invept_global(void)
1392 {
1393         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1394 }
1395
1396 static inline bool cpu_has_vmx_invvpid_single(void)
1397 {
1398         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1399 }
1400
1401 static inline bool cpu_has_vmx_invvpid_global(void)
1402 {
1403         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1404 }
1405
1406 static inline bool cpu_has_vmx_invvpid(void)
1407 {
1408         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1409 }
1410
1411 static inline bool cpu_has_vmx_ept(void)
1412 {
1413         return vmcs_config.cpu_based_2nd_exec_ctrl &
1414                 SECONDARY_EXEC_ENABLE_EPT;
1415 }
1416
1417 static inline bool cpu_has_vmx_unrestricted_guest(void)
1418 {
1419         return vmcs_config.cpu_based_2nd_exec_ctrl &
1420                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1421 }
1422
1423 static inline bool cpu_has_vmx_ple(void)
1424 {
1425         return vmcs_config.cpu_based_2nd_exec_ctrl &
1426                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1427 }
1428
1429 static inline bool cpu_has_vmx_basic_inout(void)
1430 {
1431         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1432 }
1433
1434 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1435 {
1436         return flexpriority_enabled && lapic_in_kernel(vcpu);
1437 }
1438
1439 static inline bool cpu_has_vmx_vpid(void)
1440 {
1441         return vmcs_config.cpu_based_2nd_exec_ctrl &
1442                 SECONDARY_EXEC_ENABLE_VPID;
1443 }
1444
1445 static inline bool cpu_has_vmx_rdtscp(void)
1446 {
1447         return vmcs_config.cpu_based_2nd_exec_ctrl &
1448                 SECONDARY_EXEC_RDTSCP;
1449 }
1450
1451 static inline bool cpu_has_vmx_invpcid(void)
1452 {
1453         return vmcs_config.cpu_based_2nd_exec_ctrl &
1454                 SECONDARY_EXEC_ENABLE_INVPCID;
1455 }
1456
1457 static inline bool cpu_has_virtual_nmis(void)
1458 {
1459         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1460 }
1461
1462 static inline bool cpu_has_vmx_wbinvd_exit(void)
1463 {
1464         return vmcs_config.cpu_based_2nd_exec_ctrl &
1465                 SECONDARY_EXEC_WBINVD_EXITING;
1466 }
1467
1468 static inline bool cpu_has_vmx_shadow_vmcs(void)
1469 {
1470         u64 vmx_msr;
1471         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1472         /* check if the cpu supports writing r/o exit information fields */
1473         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1474                 return false;
1475
1476         return vmcs_config.cpu_based_2nd_exec_ctrl &
1477                 SECONDARY_EXEC_SHADOW_VMCS;
1478 }
1479
1480 static inline bool cpu_has_vmx_pml(void)
1481 {
1482         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1483 }
1484
1485 static inline bool cpu_has_vmx_tsc_scaling(void)
1486 {
1487         return vmcs_config.cpu_based_2nd_exec_ctrl &
1488                 SECONDARY_EXEC_TSC_SCALING;
1489 }
1490
1491 static inline bool cpu_has_vmx_vmfunc(void)
1492 {
1493         return vmcs_config.cpu_based_2nd_exec_ctrl &
1494                 SECONDARY_EXEC_ENABLE_VMFUNC;
1495 }
1496
1497 static inline bool report_flexpriority(void)
1498 {
1499         return flexpriority_enabled;
1500 }
1501
1502 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1503 {
1504         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1505 }
1506
1507 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1508 {
1509         return vmcs12->cpu_based_vm_exec_control & bit;
1510 }
1511
1512 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1513 {
1514         return (vmcs12->cpu_based_vm_exec_control &
1515                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1516                 (vmcs12->secondary_vm_exec_control & bit);
1517 }
1518
1519 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1520 {
1521         return vmcs12->pin_based_vm_exec_control &
1522                 PIN_BASED_VMX_PREEMPTION_TIMER;
1523 }
1524
1525 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1526 {
1527         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1528 }
1529
1530 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1531 {
1532         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1533 }
1534
1535 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1536 {
1537         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1538 }
1539
1540 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1541 {
1542         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1543 }
1544
1545 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1546 {
1547         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1548 }
1549
1550 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1551 {
1552         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1553 }
1554
1555 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1556 {
1557         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1558 }
1559
1560 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1561 {
1562         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1563 }
1564
1565 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1566 {
1567         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1568 }
1569
1570 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1571 {
1572         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1573 }
1574
1575 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1576 {
1577         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1578 }
1579
1580 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1581 {
1582         return nested_cpu_has_vmfunc(vmcs12) &&
1583                 (vmcs12->vm_function_control &
1584                  VMX_VMFUNC_EPTP_SWITCHING);
1585 }
1586
1587 static inline bool is_nmi(u32 intr_info)
1588 {
1589         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1590                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1591 }
1592
1593 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1594                               u32 exit_intr_info,
1595                               unsigned long exit_qualification);
1596 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1597                         struct vmcs12 *vmcs12,
1598                         u32 reason, unsigned long qualification);
1599
1600 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1601 {
1602         int i;
1603
1604         for (i = 0; i < vmx->nmsrs; ++i)
1605                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1606                         return i;
1607         return -1;
1608 }
1609
1610 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1611 {
1612     struct {
1613         u64 vpid : 16;
1614         u64 rsvd : 48;
1615         u64 gva;
1616     } operand = { vpid, 0, gva };
1617
1618     asm volatile (__ex(ASM_VMX_INVVPID)
1619                   /* CF==1 or ZF==1 --> rc = -1 */
1620                   "; ja 1f ; ud2 ; 1:"
1621                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1622 }
1623
1624 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1625 {
1626         struct {
1627                 u64 eptp, gpa;
1628         } operand = {eptp, gpa};
1629
1630         asm volatile (__ex(ASM_VMX_INVEPT)
1631                         /* CF==1 or ZF==1 --> rc = -1 */
1632                         "; ja 1f ; ud2 ; 1:\n"
1633                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1634 }
1635
1636 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1637 {
1638         int i;
1639
1640         i = __find_msr_index(vmx, msr);
1641         if (i >= 0)
1642                 return &vmx->guest_msrs[i];
1643         return NULL;
1644 }
1645
1646 static void vmcs_clear(struct vmcs *vmcs)
1647 {
1648         u64 phys_addr = __pa(vmcs);
1649         u8 error;
1650
1651         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1652                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1653                       : "cc", "memory");
1654         if (error)
1655                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1656                        vmcs, phys_addr);
1657 }
1658
1659 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1660 {
1661         vmcs_clear(loaded_vmcs->vmcs);
1662         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1663                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1664         loaded_vmcs->cpu = -1;
1665         loaded_vmcs->launched = 0;
1666 }
1667
1668 static void vmcs_load(struct vmcs *vmcs)
1669 {
1670         u64 phys_addr = __pa(vmcs);
1671         u8 error;
1672
1673         if (static_branch_unlikely(&enable_evmcs))
1674                 return evmcs_load(phys_addr);
1675
1676         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1677                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1678                         : "cc", "memory");
1679         if (error)
1680                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1681                        vmcs, phys_addr);
1682 }
1683
1684 #ifdef CONFIG_KEXEC_CORE
1685 /*
1686  * This bitmap is used to indicate whether the vmclear
1687  * operation is enabled on all cpus. All disabled by
1688  * default.
1689  */
1690 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1691
1692 static inline void crash_enable_local_vmclear(int cpu)
1693 {
1694         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1695 }
1696
1697 static inline void crash_disable_local_vmclear(int cpu)
1698 {
1699         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1700 }
1701
1702 static inline int crash_local_vmclear_enabled(int cpu)
1703 {
1704         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1705 }
1706
1707 static void crash_vmclear_local_loaded_vmcss(void)
1708 {
1709         int cpu = raw_smp_processor_id();
1710         struct loaded_vmcs *v;
1711
1712         if (!crash_local_vmclear_enabled(cpu))
1713                 return;
1714
1715         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1716                             loaded_vmcss_on_cpu_link)
1717                 vmcs_clear(v->vmcs);
1718 }
1719 #else
1720 static inline void crash_enable_local_vmclear(int cpu) { }
1721 static inline void crash_disable_local_vmclear(int cpu) { }
1722 #endif /* CONFIG_KEXEC_CORE */
1723
1724 static void __loaded_vmcs_clear(void *arg)
1725 {
1726         struct loaded_vmcs *loaded_vmcs = arg;
1727         int cpu = raw_smp_processor_id();
1728
1729         if (loaded_vmcs->cpu != cpu)
1730                 return; /* vcpu migration can race with cpu offline */
1731         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1732                 per_cpu(current_vmcs, cpu) = NULL;
1733         crash_disable_local_vmclear(cpu);
1734         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1735
1736         /*
1737          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1738          * is before setting loaded_vmcs->vcpu to -1 which is done in
1739          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1740          * then adds the vmcs into percpu list before it is deleted.
1741          */
1742         smp_wmb();
1743
1744         loaded_vmcs_init(loaded_vmcs);
1745         crash_enable_local_vmclear(cpu);
1746 }
1747
1748 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1749 {
1750         int cpu = loaded_vmcs->cpu;
1751
1752         if (cpu != -1)
1753                 smp_call_function_single(cpu,
1754                          __loaded_vmcs_clear, loaded_vmcs, 1);
1755 }
1756
1757 static inline void vpid_sync_vcpu_single(int vpid)
1758 {
1759         if (vpid == 0)
1760                 return;
1761
1762         if (cpu_has_vmx_invvpid_single())
1763                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1764 }
1765
1766 static inline void vpid_sync_vcpu_global(void)
1767 {
1768         if (cpu_has_vmx_invvpid_global())
1769                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1770 }
1771
1772 static inline void vpid_sync_context(int vpid)
1773 {
1774         if (cpu_has_vmx_invvpid_single())
1775                 vpid_sync_vcpu_single(vpid);
1776         else
1777                 vpid_sync_vcpu_global();
1778 }
1779
1780 static inline void ept_sync_global(void)
1781 {
1782         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1783 }
1784
1785 static inline void ept_sync_context(u64 eptp)
1786 {
1787         if (cpu_has_vmx_invept_context())
1788                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1789         else
1790                 ept_sync_global();
1791 }
1792
1793 static __always_inline void vmcs_check16(unsigned long field)
1794 {
1795         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1796                          "16-bit accessor invalid for 64-bit field");
1797         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1798                          "16-bit accessor invalid for 64-bit high field");
1799         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1800                          "16-bit accessor invalid for 32-bit high field");
1801         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1802                          "16-bit accessor invalid for natural width field");
1803 }
1804
1805 static __always_inline void vmcs_check32(unsigned long field)
1806 {
1807         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1808                          "32-bit accessor invalid for 16-bit field");
1809         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1810                          "32-bit accessor invalid for natural width field");
1811 }
1812
1813 static __always_inline void vmcs_check64(unsigned long field)
1814 {
1815         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1816                          "64-bit accessor invalid for 16-bit field");
1817         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1818                          "64-bit accessor invalid for 64-bit high field");
1819         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1820                          "64-bit accessor invalid for 32-bit field");
1821         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1822                          "64-bit accessor invalid for natural width field");
1823 }
1824
1825 static __always_inline void vmcs_checkl(unsigned long field)
1826 {
1827         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1828                          "Natural width accessor invalid for 16-bit field");
1829         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1830                          "Natural width accessor invalid for 64-bit field");
1831         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1832                          "Natural width accessor invalid for 64-bit high field");
1833         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1834                          "Natural width accessor invalid for 32-bit field");
1835 }
1836
1837 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1838 {
1839         unsigned long value;
1840
1841         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1842                       : "=a"(value) : "d"(field) : "cc");
1843         return value;
1844 }
1845
1846 static __always_inline u16 vmcs_read16(unsigned long field)
1847 {
1848         vmcs_check16(field);
1849         if (static_branch_unlikely(&enable_evmcs))
1850                 return evmcs_read16(field);
1851         return __vmcs_readl(field);
1852 }
1853
1854 static __always_inline u32 vmcs_read32(unsigned long field)
1855 {
1856         vmcs_check32(field);
1857         if (static_branch_unlikely(&enable_evmcs))
1858                 return evmcs_read32(field);
1859         return __vmcs_readl(field);
1860 }
1861
1862 static __always_inline u64 vmcs_read64(unsigned long field)
1863 {
1864         vmcs_check64(field);
1865         if (static_branch_unlikely(&enable_evmcs))
1866                 return evmcs_read64(field);
1867 #ifdef CONFIG_X86_64
1868         return __vmcs_readl(field);
1869 #else
1870         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1871 #endif
1872 }
1873
1874 static __always_inline unsigned long vmcs_readl(unsigned long field)
1875 {
1876         vmcs_checkl(field);
1877         if (static_branch_unlikely(&enable_evmcs))
1878                 return evmcs_read64(field);
1879         return __vmcs_readl(field);
1880 }
1881
1882 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1883 {
1884         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1885                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1886         dump_stack();
1887 }
1888
1889 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1890 {
1891         u8 error;
1892
1893         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1894                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1895         if (unlikely(error))
1896                 vmwrite_error(field, value);
1897 }
1898
1899 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1900 {
1901         vmcs_check16(field);
1902         if (static_branch_unlikely(&enable_evmcs))
1903                 return evmcs_write16(field, value);
1904
1905         __vmcs_writel(field, value);
1906 }
1907
1908 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1909 {
1910         vmcs_check32(field);
1911         if (static_branch_unlikely(&enable_evmcs))
1912                 return evmcs_write32(field, value);
1913
1914         __vmcs_writel(field, value);
1915 }
1916
1917 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1918 {
1919         vmcs_check64(field);
1920         if (static_branch_unlikely(&enable_evmcs))
1921                 return evmcs_write64(field, value);
1922
1923         __vmcs_writel(field, value);
1924 #ifndef CONFIG_X86_64
1925         asm volatile ("");
1926         __vmcs_writel(field+1, value >> 32);
1927 #endif
1928 }
1929
1930 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1931 {
1932         vmcs_checkl(field);
1933         if (static_branch_unlikely(&enable_evmcs))
1934                 return evmcs_write64(field, value);
1935
1936         __vmcs_writel(field, value);
1937 }
1938
1939 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1940 {
1941         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1942                          "vmcs_clear_bits does not support 64-bit fields");
1943         if (static_branch_unlikely(&enable_evmcs))
1944                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
1945
1946         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1947 }
1948
1949 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1950 {
1951         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1952                          "vmcs_set_bits does not support 64-bit fields");
1953         if (static_branch_unlikely(&enable_evmcs))
1954                 return evmcs_write32(field, evmcs_read32(field) | mask);
1955
1956         __vmcs_writel(field, __vmcs_readl(field) | mask);
1957 }
1958
1959 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1960 {
1961         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1962 }
1963
1964 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1965 {
1966         vmcs_write32(VM_ENTRY_CONTROLS, val);
1967         vmx->vm_entry_controls_shadow = val;
1968 }
1969
1970 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1971 {
1972         if (vmx->vm_entry_controls_shadow != val)
1973                 vm_entry_controls_init(vmx, val);
1974 }
1975
1976 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1977 {
1978         return vmx->vm_entry_controls_shadow;
1979 }
1980
1981
1982 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1983 {
1984         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1985 }
1986
1987 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1988 {
1989         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1990 }
1991
1992 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1993 {
1994         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1995 }
1996
1997 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1998 {
1999         vmcs_write32(VM_EXIT_CONTROLS, val);
2000         vmx->vm_exit_controls_shadow = val;
2001 }
2002
2003 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2004 {
2005         if (vmx->vm_exit_controls_shadow != val)
2006                 vm_exit_controls_init(vmx, val);
2007 }
2008
2009 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2010 {
2011         return vmx->vm_exit_controls_shadow;
2012 }
2013
2014
2015 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2016 {
2017         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2018 }
2019
2020 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2021 {
2022         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2023 }
2024
2025 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2026 {
2027         vmx->segment_cache.bitmask = 0;
2028 }
2029
2030 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2031                                        unsigned field)
2032 {
2033         bool ret;
2034         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2035
2036         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2037                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2038                 vmx->segment_cache.bitmask = 0;
2039         }
2040         ret = vmx->segment_cache.bitmask & mask;
2041         vmx->segment_cache.bitmask |= mask;
2042         return ret;
2043 }
2044
2045 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2046 {
2047         u16 *p = &vmx->segment_cache.seg[seg].selector;
2048
2049         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2050                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2051         return *p;
2052 }
2053
2054 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2055 {
2056         ulong *p = &vmx->segment_cache.seg[seg].base;
2057
2058         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2059                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2060         return *p;
2061 }
2062
2063 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2064 {
2065         u32 *p = &vmx->segment_cache.seg[seg].limit;
2066
2067         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2068                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2069         return *p;
2070 }
2071
2072 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2073 {
2074         u32 *p = &vmx->segment_cache.seg[seg].ar;
2075
2076         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2077                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2078         return *p;
2079 }
2080
2081 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2082 {
2083         u32 eb;
2084
2085         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2086              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2087         /*
2088          * Guest access to VMware backdoor ports could legitimately
2089          * trigger #GP because of TSS I/O permission bitmap.
2090          * We intercept those #GP and allow access to them anyway
2091          * as VMware does.
2092          */
2093         if (enable_vmware_backdoor)
2094                 eb |= (1u << GP_VECTOR);
2095         if ((vcpu->guest_debug &
2096              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2097             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2098                 eb |= 1u << BP_VECTOR;
2099         if (to_vmx(vcpu)->rmode.vm86_active)
2100                 eb = ~0;
2101         if (enable_ept)
2102                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2103
2104         /* When we are running a nested L2 guest and L1 specified for it a
2105          * certain exception bitmap, we must trap the same exceptions and pass
2106          * them to L1. When running L2, we will only handle the exceptions
2107          * specified above if L1 did not want them.
2108          */
2109         if (is_guest_mode(vcpu))
2110                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2111
2112         vmcs_write32(EXCEPTION_BITMAP, eb);
2113 }
2114
2115 /*
2116  * Check if MSR is intercepted for currently loaded MSR bitmap.
2117  */
2118 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2119 {
2120         unsigned long *msr_bitmap;
2121         int f = sizeof(unsigned long);
2122
2123         if (!cpu_has_vmx_msr_bitmap())
2124                 return true;
2125
2126         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2127
2128         if (msr <= 0x1fff) {
2129                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2130         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2131                 msr &= 0x1fff;
2132                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2133         }
2134
2135         return true;
2136 }
2137
2138 /*
2139  * Check if MSR is intercepted for L01 MSR bitmap.
2140  */
2141 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2142 {
2143         unsigned long *msr_bitmap;
2144         int f = sizeof(unsigned long);
2145
2146         if (!cpu_has_vmx_msr_bitmap())
2147                 return true;
2148
2149         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2150
2151         if (msr <= 0x1fff) {
2152                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2153         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2154                 msr &= 0x1fff;
2155                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2156         }
2157
2158         return true;
2159 }
2160
2161 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2162                 unsigned long entry, unsigned long exit)
2163 {
2164         vm_entry_controls_clearbit(vmx, entry);
2165         vm_exit_controls_clearbit(vmx, exit);
2166 }
2167
2168 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2169 {
2170         unsigned i;
2171         struct msr_autoload *m = &vmx->msr_autoload;
2172
2173         switch (msr) {
2174         case MSR_EFER:
2175                 if (cpu_has_load_ia32_efer) {
2176                         clear_atomic_switch_msr_special(vmx,
2177                                         VM_ENTRY_LOAD_IA32_EFER,
2178                                         VM_EXIT_LOAD_IA32_EFER);
2179                         return;
2180                 }
2181                 break;
2182         case MSR_CORE_PERF_GLOBAL_CTRL:
2183                 if (cpu_has_load_perf_global_ctrl) {
2184                         clear_atomic_switch_msr_special(vmx,
2185                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2186                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2187                         return;
2188                 }
2189                 break;
2190         }
2191
2192         for (i = 0; i < m->nr; ++i)
2193                 if (m->guest[i].index == msr)
2194                         break;
2195
2196         if (i == m->nr)
2197                 return;
2198         --m->nr;
2199         m->guest[i] = m->guest[m->nr];
2200         m->host[i] = m->host[m->nr];
2201         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2202         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2203 }
2204
2205 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2206                 unsigned long entry, unsigned long exit,
2207                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2208                 u64 guest_val, u64 host_val)
2209 {
2210         vmcs_write64(guest_val_vmcs, guest_val);
2211         vmcs_write64(host_val_vmcs, host_val);
2212         vm_entry_controls_setbit(vmx, entry);
2213         vm_exit_controls_setbit(vmx, exit);
2214 }
2215
2216 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2217                                   u64 guest_val, u64 host_val)
2218 {
2219         unsigned i;
2220         struct msr_autoload *m = &vmx->msr_autoload;
2221
2222         switch (msr) {
2223         case MSR_EFER:
2224                 if (cpu_has_load_ia32_efer) {
2225                         add_atomic_switch_msr_special(vmx,
2226                                         VM_ENTRY_LOAD_IA32_EFER,
2227                                         VM_EXIT_LOAD_IA32_EFER,
2228                                         GUEST_IA32_EFER,
2229                                         HOST_IA32_EFER,
2230                                         guest_val, host_val);
2231                         return;
2232                 }
2233                 break;
2234         case MSR_CORE_PERF_GLOBAL_CTRL:
2235                 if (cpu_has_load_perf_global_ctrl) {
2236                         add_atomic_switch_msr_special(vmx,
2237                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2238                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2239                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2240                                         HOST_IA32_PERF_GLOBAL_CTRL,
2241                                         guest_val, host_val);
2242                         return;
2243                 }
2244                 break;
2245         case MSR_IA32_PEBS_ENABLE:
2246                 /* PEBS needs a quiescent period after being disabled (to write
2247                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2248                  * provide that period, so a CPU could write host's record into
2249                  * guest's memory.
2250                  */
2251                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2252         }
2253
2254         for (i = 0; i < m->nr; ++i)
2255                 if (m->guest[i].index == msr)
2256                         break;
2257
2258         if (i == NR_AUTOLOAD_MSRS) {
2259                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2260                                 "Can't add msr %x\n", msr);
2261                 return;
2262         } else if (i == m->nr) {
2263                 ++m->nr;
2264                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2265                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2266         }
2267
2268         m->guest[i].index = msr;
2269         m->guest[i].value = guest_val;
2270         m->host[i].index = msr;
2271         m->host[i].value = host_val;
2272 }
2273
2274 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2275 {
2276         u64 guest_efer = vmx->vcpu.arch.efer;
2277         u64 ignore_bits = 0;
2278
2279         if (!enable_ept) {
2280                 /*
2281                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2282                  * host CPUID is more efficient than testing guest CPUID
2283                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2284                  */
2285                 if (boot_cpu_has(X86_FEATURE_SMEP))
2286                         guest_efer |= EFER_NX;
2287                 else if (!(guest_efer & EFER_NX))
2288                         ignore_bits |= EFER_NX;
2289         }
2290
2291         /*
2292          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2293          */
2294         ignore_bits |= EFER_SCE;
2295 #ifdef CONFIG_X86_64
2296         ignore_bits |= EFER_LMA | EFER_LME;
2297         /* SCE is meaningful only in long mode on Intel */
2298         if (guest_efer & EFER_LMA)
2299                 ignore_bits &= ~(u64)EFER_SCE;
2300 #endif
2301
2302         clear_atomic_switch_msr(vmx, MSR_EFER);
2303
2304         /*
2305          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2306          * On CPUs that support "load IA32_EFER", always switch EFER
2307          * atomically, since it's faster than switching it manually.
2308          */
2309         if (cpu_has_load_ia32_efer ||
2310             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2311                 if (!(guest_efer & EFER_LMA))
2312                         guest_efer &= ~EFER_LME;
2313                 if (guest_efer != host_efer)
2314                         add_atomic_switch_msr(vmx, MSR_EFER,
2315                                               guest_efer, host_efer);
2316                 return false;
2317         } else {
2318                 guest_efer &= ~ignore_bits;
2319                 guest_efer |= host_efer & ignore_bits;
2320
2321                 vmx->guest_msrs[efer_offset].data = guest_efer;
2322                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2323
2324                 return true;
2325         }
2326 }
2327
2328 #ifdef CONFIG_X86_32
2329 /*
2330  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2331  * VMCS rather than the segment table.  KVM uses this helper to figure
2332  * out the current bases to poke them into the VMCS before entry.
2333  */
2334 static unsigned long segment_base(u16 selector)
2335 {
2336         struct desc_struct *table;
2337         unsigned long v;
2338
2339         if (!(selector & ~SEGMENT_RPL_MASK))
2340                 return 0;
2341
2342         table = get_current_gdt_ro();
2343
2344         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2345                 u16 ldt_selector = kvm_read_ldt();
2346
2347                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2348                         return 0;
2349
2350                 table = (struct desc_struct *)segment_base(ldt_selector);
2351         }
2352         v = get_desc_base(&table[selector >> 3]);
2353         return v;
2354 }
2355 #endif
2356
2357 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2358 {
2359         struct vcpu_vmx *vmx = to_vmx(vcpu);
2360 #ifdef CONFIG_X86_64
2361         int cpu = raw_smp_processor_id();
2362 #endif
2363         int i;
2364
2365         if (vmx->host_state.loaded)
2366                 return;
2367
2368         vmx->host_state.loaded = 1;
2369         /*
2370          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2371          * allow segment selectors with cpl > 0 or ti == 1.
2372          */
2373         vmx->host_state.ldt_sel = kvm_read_ldt();
2374         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2375
2376 #ifdef CONFIG_X86_64
2377         save_fsgs_for_kvm();
2378         vmx->host_state.fs_sel = current->thread.fsindex;
2379         vmx->host_state.gs_sel = current->thread.gsindex;
2380 #else
2381         savesegment(fs, vmx->host_state.fs_sel);
2382         savesegment(gs, vmx->host_state.gs_sel);
2383 #endif
2384         if (!(vmx->host_state.fs_sel & 7)) {
2385                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2386                 vmx->host_state.fs_reload_needed = 0;
2387         } else {
2388                 vmcs_write16(HOST_FS_SELECTOR, 0);
2389                 vmx->host_state.fs_reload_needed = 1;
2390         }
2391         if (!(vmx->host_state.gs_sel & 7))
2392                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2393         else {
2394                 vmcs_write16(HOST_GS_SELECTOR, 0);
2395                 vmx->host_state.gs_ldt_reload_needed = 1;
2396         }
2397
2398 #ifdef CONFIG_X86_64
2399         savesegment(ds, vmx->host_state.ds_sel);
2400         savesegment(es, vmx->host_state.es_sel);
2401
2402         vmcs_writel(HOST_FS_BASE, current->thread.fsbase);
2403         vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2404
2405         vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2406         if (is_long_mode(&vmx->vcpu))
2407                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2408 #else
2409         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2410         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2411 #endif
2412         if (boot_cpu_has(X86_FEATURE_MPX))
2413                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2414         for (i = 0; i < vmx->save_nmsrs; ++i)
2415                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2416                                    vmx->guest_msrs[i].data,
2417                                    vmx->guest_msrs[i].mask);
2418 }
2419
2420 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2421 {
2422         if (!vmx->host_state.loaded)
2423                 return;
2424
2425         ++vmx->vcpu.stat.host_state_reload;
2426         vmx->host_state.loaded = 0;
2427 #ifdef CONFIG_X86_64
2428         if (is_long_mode(&vmx->vcpu))
2429                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2430 #endif
2431         if (vmx->host_state.gs_ldt_reload_needed) {
2432                 kvm_load_ldt(vmx->host_state.ldt_sel);
2433 #ifdef CONFIG_X86_64
2434                 load_gs_index(vmx->host_state.gs_sel);
2435 #else
2436                 loadsegment(gs, vmx->host_state.gs_sel);
2437 #endif
2438         }
2439         if (vmx->host_state.fs_reload_needed)
2440                 loadsegment(fs, vmx->host_state.fs_sel);
2441 #ifdef CONFIG_X86_64
2442         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2443                 loadsegment(ds, vmx->host_state.ds_sel);
2444                 loadsegment(es, vmx->host_state.es_sel);
2445         }
2446 #endif
2447         invalidate_tss_limit();
2448 #ifdef CONFIG_X86_64
2449         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2450 #endif
2451         if (vmx->host_state.msr_host_bndcfgs)
2452                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2453         load_fixmap_gdt(raw_smp_processor_id());
2454 }
2455
2456 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2457 {
2458         preempt_disable();
2459         __vmx_load_host_state(vmx);
2460         preempt_enable();
2461 }
2462
2463 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2464 {
2465         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2466         struct pi_desc old, new;
2467         unsigned int dest;
2468
2469         /*
2470          * In case of hot-plug or hot-unplug, we may have to undo
2471          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2472          * always keep PI.NDST up to date for simplicity: it makes the
2473          * code easier, and CPU migration is not a fast path.
2474          */
2475         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2476                 return;
2477
2478         /*
2479          * First handle the simple case where no cmpxchg is necessary; just
2480          * allow posting non-urgent interrupts.
2481          *
2482          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2483          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2484          * expects the VCPU to be on the blocked_vcpu_list that matches
2485          * PI.NDST.
2486          */
2487         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2488             vcpu->cpu == cpu) {
2489                 pi_clear_sn(pi_desc);
2490                 return;
2491         }
2492
2493         /* The full case.  */
2494         do {
2495                 old.control = new.control = pi_desc->control;
2496
2497                 dest = cpu_physical_id(cpu);
2498
2499                 if (x2apic_enabled())
2500                         new.ndst = dest;
2501                 else
2502                         new.ndst = (dest << 8) & 0xFF00;
2503
2504                 new.sn = 0;
2505         } while (cmpxchg64(&pi_desc->control, old.control,
2506                            new.control) != old.control);
2507 }
2508
2509 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2510 {
2511         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2512         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2513 }
2514
2515 /*
2516  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2517  * vcpu mutex is already taken.
2518  */
2519 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2520 {
2521         struct vcpu_vmx *vmx = to_vmx(vcpu);
2522         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2523
2524         if (!already_loaded) {
2525                 loaded_vmcs_clear(vmx->loaded_vmcs);
2526                 local_irq_disable();
2527                 crash_disable_local_vmclear(cpu);
2528
2529                 /*
2530                  * Read loaded_vmcs->cpu should be before fetching
2531                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2532                  * See the comments in __loaded_vmcs_clear().
2533                  */
2534                 smp_rmb();
2535
2536                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2537                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2538                 crash_enable_local_vmclear(cpu);
2539                 local_irq_enable();
2540         }
2541
2542         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2543                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2544                 vmcs_load(vmx->loaded_vmcs->vmcs);
2545                 indirect_branch_prediction_barrier();
2546         }
2547
2548         if (!already_loaded) {
2549                 void *gdt = get_current_gdt_ro();
2550                 unsigned long sysenter_esp;
2551
2552                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2553
2554                 /*
2555                  * Linux uses per-cpu TSS and GDT, so set these when switching
2556                  * processors.  See 22.2.4.
2557                  */
2558                 vmcs_writel(HOST_TR_BASE,
2559                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2560                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2561
2562                 /*
2563                  * VM exits change the host TR limit to 0x67 after a VM
2564                  * exit.  This is okay, since 0x67 covers everything except
2565                  * the IO bitmap and have have code to handle the IO bitmap
2566                  * being lost after a VM exit.
2567                  */
2568                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2569
2570                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2571                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2572
2573                 vmx->loaded_vmcs->cpu = cpu;
2574         }
2575
2576         /* Setup TSC multiplier */
2577         if (kvm_has_tsc_control &&
2578             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2579                 decache_tsc_multiplier(vmx);
2580
2581         vmx_vcpu_pi_load(vcpu, cpu);
2582         vmx->host_pkru = read_pkru();
2583         vmx->host_debugctlmsr = get_debugctlmsr();
2584 }
2585
2586 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2587 {
2588         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2589
2590         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2591                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2592                 !kvm_vcpu_apicv_active(vcpu))
2593                 return;
2594
2595         /* Set SN when the vCPU is preempted */
2596         if (vcpu->preempted)
2597                 pi_set_sn(pi_desc);
2598 }
2599
2600 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2601 {
2602         vmx_vcpu_pi_put(vcpu);
2603
2604         __vmx_load_host_state(to_vmx(vcpu));
2605 }
2606
2607 static bool emulation_required(struct kvm_vcpu *vcpu)
2608 {
2609         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2610 }
2611
2612 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2613
2614 /*
2615  * Return the cr0 value that a nested guest would read. This is a combination
2616  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2617  * its hypervisor (cr0_read_shadow).
2618  */
2619 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2620 {
2621         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2622                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2623 }
2624 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2625 {
2626         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2627                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2628 }
2629
2630 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2631 {
2632         unsigned long rflags, save_rflags;
2633
2634         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2635                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2636                 rflags = vmcs_readl(GUEST_RFLAGS);
2637                 if (to_vmx(vcpu)->rmode.vm86_active) {
2638                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2639                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2640                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2641                 }
2642                 to_vmx(vcpu)->rflags = rflags;
2643         }
2644         return to_vmx(vcpu)->rflags;
2645 }
2646
2647 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2648 {
2649         unsigned long old_rflags = vmx_get_rflags(vcpu);
2650
2651         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2652         to_vmx(vcpu)->rflags = rflags;
2653         if (to_vmx(vcpu)->rmode.vm86_active) {
2654                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2655                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2656         }
2657         vmcs_writel(GUEST_RFLAGS, rflags);
2658
2659         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2660                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2661 }
2662
2663 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2664 {
2665         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2666         int ret = 0;
2667
2668         if (interruptibility & GUEST_INTR_STATE_STI)
2669                 ret |= KVM_X86_SHADOW_INT_STI;
2670         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2671                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2672
2673         return ret;
2674 }
2675
2676 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2677 {
2678         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2679         u32 interruptibility = interruptibility_old;
2680
2681         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2682
2683         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2684                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2685         else if (mask & KVM_X86_SHADOW_INT_STI)
2686                 interruptibility |= GUEST_INTR_STATE_STI;
2687
2688         if ((interruptibility != interruptibility_old))
2689                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2690 }
2691
2692 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2693 {
2694         unsigned long rip;
2695
2696         rip = kvm_rip_read(vcpu);
2697         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2698         kvm_rip_write(vcpu, rip);
2699
2700         /* skipping an emulated instruction also counts */
2701         vmx_set_interrupt_shadow(vcpu, 0);
2702 }
2703
2704 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2705                                                unsigned long exit_qual)
2706 {
2707         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2708         unsigned int nr = vcpu->arch.exception.nr;
2709         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2710
2711         if (vcpu->arch.exception.has_error_code) {
2712                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2713                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2714         }
2715
2716         if (kvm_exception_is_soft(nr))
2717                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2718         else
2719                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2720
2721         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2722             vmx_get_nmi_mask(vcpu))
2723                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2724
2725         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2726 }
2727
2728 /*
2729  * KVM wants to inject page-faults which it got to the guest. This function
2730  * checks whether in a nested guest, we need to inject them to L1 or L2.
2731  */
2732 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2733 {
2734         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2735         unsigned int nr = vcpu->arch.exception.nr;
2736
2737         if (nr == PF_VECTOR) {
2738                 if (vcpu->arch.exception.nested_apf) {
2739                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2740                         return 1;
2741                 }
2742                 /*
2743                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2744                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2745                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2746                  * can be written only when inject_pending_event runs.  This should be
2747                  * conditional on a new capability---if the capability is disabled,
2748                  * kvm_multiple_exception would write the ancillary information to
2749                  * CR2 or DR6, for backwards ABI-compatibility.
2750                  */
2751                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2752                                                     vcpu->arch.exception.error_code)) {
2753                         *exit_qual = vcpu->arch.cr2;
2754                         return 1;
2755                 }
2756         } else {
2757                 if (vmcs12->exception_bitmap & (1u << nr)) {
2758                         if (nr == DB_VECTOR)
2759                                 *exit_qual = vcpu->arch.dr6;
2760                         else
2761                                 *exit_qual = 0;
2762                         return 1;
2763                 }
2764         }
2765
2766         return 0;
2767 }
2768
2769 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2770 {
2771         /*
2772          * Ensure that we clear the HLT state in the VMCS.  We don't need to
2773          * explicitly skip the instruction because if the HLT state is set,
2774          * then the instruction is already executing and RIP has already been
2775          * advanced.
2776          */
2777         if (kvm_hlt_in_guest(vcpu->kvm) &&
2778                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
2779                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2780 }
2781
2782 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2783 {
2784         struct vcpu_vmx *vmx = to_vmx(vcpu);
2785         unsigned nr = vcpu->arch.exception.nr;
2786         bool has_error_code = vcpu->arch.exception.has_error_code;
2787         u32 error_code = vcpu->arch.exception.error_code;
2788         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2789
2790         if (has_error_code) {
2791                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2792                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2793         }
2794
2795         if (vmx->rmode.vm86_active) {
2796                 int inc_eip = 0;
2797                 if (kvm_exception_is_soft(nr))
2798                         inc_eip = vcpu->arch.event_exit_inst_len;
2799                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2800                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2801                 return;
2802         }
2803
2804         WARN_ON_ONCE(vmx->emulation_required);
2805
2806         if (kvm_exception_is_soft(nr)) {
2807                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2808                              vmx->vcpu.arch.event_exit_inst_len);
2809                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2810         } else
2811                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2812
2813         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2814
2815         vmx_clear_hlt(vcpu);
2816 }
2817
2818 static bool vmx_rdtscp_supported(void)
2819 {
2820         return cpu_has_vmx_rdtscp();
2821 }
2822
2823 static bool vmx_invpcid_supported(void)
2824 {
2825         return cpu_has_vmx_invpcid() && enable_ept;
2826 }
2827
2828 /*
2829  * Swap MSR entry in host/guest MSR entry array.
2830  */
2831 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2832 {
2833         struct shared_msr_entry tmp;
2834
2835         tmp = vmx->guest_msrs[to];
2836         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2837         vmx->guest_msrs[from] = tmp;
2838 }
2839
2840 /*
2841  * Set up the vmcs to automatically save and restore system
2842  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2843  * mode, as fiddling with msrs is very expensive.
2844  */
2845 static void setup_msrs(struct vcpu_vmx *vmx)
2846 {
2847         int save_nmsrs, index;
2848
2849         save_nmsrs = 0;
2850 #ifdef CONFIG_X86_64
2851         if (is_long_mode(&vmx->vcpu)) {
2852                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2853                 if (index >= 0)
2854                         move_msr_up(vmx, index, save_nmsrs++);
2855                 index = __find_msr_index(vmx, MSR_LSTAR);
2856                 if (index >= 0)
2857                         move_msr_up(vmx, index, save_nmsrs++);
2858                 index = __find_msr_index(vmx, MSR_CSTAR);
2859                 if (index >= 0)
2860                         move_msr_up(vmx, index, save_nmsrs++);
2861                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2862                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2863                         move_msr_up(vmx, index, save_nmsrs++);
2864                 /*
2865                  * MSR_STAR is only needed on long mode guests, and only
2866                  * if efer.sce is enabled.
2867                  */
2868                 index = __find_msr_index(vmx, MSR_STAR);
2869                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2870                         move_msr_up(vmx, index, save_nmsrs++);
2871         }
2872 #endif
2873         index = __find_msr_index(vmx, MSR_EFER);
2874         if (index >= 0 && update_transition_efer(vmx, index))
2875                 move_msr_up(vmx, index, save_nmsrs++);
2876
2877         vmx->save_nmsrs = save_nmsrs;
2878
2879         if (cpu_has_vmx_msr_bitmap())
2880                 vmx_update_msr_bitmap(&vmx->vcpu);
2881 }
2882
2883 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
2884 {
2885         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2886
2887         if (is_guest_mode(vcpu) &&
2888             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
2889                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
2890
2891         return vcpu->arch.tsc_offset;
2892 }
2893
2894 /*
2895  * writes 'offset' into guest's timestamp counter offset register
2896  */
2897 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2898 {
2899         if (is_guest_mode(vcpu)) {
2900                 /*
2901                  * We're here if L1 chose not to trap WRMSR to TSC. According
2902                  * to the spec, this should set L1's TSC; The offset that L1
2903                  * set for L2 remains unchanged, and still needs to be added
2904                  * to the newly set TSC to get L2's TSC.
2905                  */
2906                 struct vmcs12 *vmcs12;
2907                 /* recalculate vmcs02.TSC_OFFSET: */
2908                 vmcs12 = get_vmcs12(vcpu);
2909                 vmcs_write64(TSC_OFFSET, offset +
2910                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2911                          vmcs12->tsc_offset : 0));
2912         } else {
2913                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2914                                            vmcs_read64(TSC_OFFSET), offset);
2915                 vmcs_write64(TSC_OFFSET, offset);
2916         }
2917 }
2918
2919 /*
2920  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2921  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2922  * all guests if the "nested" module option is off, and can also be disabled
2923  * for a single guest by disabling its VMX cpuid bit.
2924  */
2925 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2926 {
2927         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2928 }
2929
2930 /*
2931  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2932  * returned for the various VMX controls MSRs when nested VMX is enabled.
2933  * The same values should also be used to verify that vmcs12 control fields are
2934  * valid during nested entry from L1 to L2.
2935  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2936  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2937  * bit in the high half is on if the corresponding bit in the control field
2938  * may be on. See also vmx_control_verify().
2939  */
2940 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
2941 {
2942         if (!nested) {
2943                 memset(msrs, 0, sizeof(*msrs));
2944                 return;
2945         }
2946
2947         /*
2948          * Note that as a general rule, the high half of the MSRs (bits in
2949          * the control fields which may be 1) should be initialized by the
2950          * intersection of the underlying hardware's MSR (i.e., features which
2951          * can be supported) and the list of features we want to expose -
2952          * because they are known to be properly supported in our code.
2953          * Also, usually, the low half of the MSRs (bits which must be 1) can
2954          * be set to 0, meaning that L1 may turn off any of these bits. The
2955          * reason is that if one of these bits is necessary, it will appear
2956          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2957          * fields of vmcs01 and vmcs02, will turn these bits off - and
2958          * nested_vmx_exit_reflected() will not pass related exits to L1.
2959          * These rules have exceptions below.
2960          */
2961
2962         /* pin-based controls */
2963         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2964                 msrs->pinbased_ctls_low,
2965                 msrs->pinbased_ctls_high);
2966         msrs->pinbased_ctls_low |=
2967                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2968         msrs->pinbased_ctls_high &=
2969                 PIN_BASED_EXT_INTR_MASK |
2970                 PIN_BASED_NMI_EXITING |
2971                 PIN_BASED_VIRTUAL_NMIS |
2972                 (apicv ? PIN_BASED_POSTED_INTR : 0);
2973         msrs->pinbased_ctls_high |=
2974                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2975                 PIN_BASED_VMX_PREEMPTION_TIMER;
2976
2977         /* exit controls */
2978         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2979                 msrs->exit_ctls_low,
2980                 msrs->exit_ctls_high);
2981         msrs->exit_ctls_low =
2982                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2983
2984         msrs->exit_ctls_high &=
2985 #ifdef CONFIG_X86_64
2986                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2987 #endif
2988                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2989         msrs->exit_ctls_high |=
2990                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2991                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2992                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2993
2994         if (kvm_mpx_supported())
2995                 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2996
2997         /* We support free control of debug control saving. */
2998         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2999
3000         /* entry controls */
3001         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3002                 msrs->entry_ctls_low,
3003                 msrs->entry_ctls_high);
3004         msrs->entry_ctls_low =
3005                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3006         msrs->entry_ctls_high &=
3007 #ifdef CONFIG_X86_64
3008                 VM_ENTRY_IA32E_MODE |
3009 #endif
3010                 VM_ENTRY_LOAD_IA32_PAT;
3011         msrs->entry_ctls_high |=
3012                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3013         if (kvm_mpx_supported())
3014                 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3015
3016         /* We support free control of debug control loading. */
3017         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3018
3019         /* cpu-based controls */
3020         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3021                 msrs->procbased_ctls_low,
3022                 msrs->procbased_ctls_high);
3023         msrs->procbased_ctls_low =
3024                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3025         msrs->procbased_ctls_high &=
3026                 CPU_BASED_VIRTUAL_INTR_PENDING |
3027                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3028                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3029                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3030                 CPU_BASED_CR3_STORE_EXITING |
3031 #ifdef CONFIG_X86_64
3032                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3033 #endif
3034                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3035                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3036                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3037                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3038                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3039         /*
3040          * We can allow some features even when not supported by the
3041          * hardware. For example, L1 can specify an MSR bitmap - and we
3042          * can use it to avoid exits to L1 - even when L0 runs L2
3043          * without MSR bitmaps.
3044          */
3045         msrs->procbased_ctls_high |=
3046                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3047                 CPU_BASED_USE_MSR_BITMAPS;
3048
3049         /* We support free control of CR3 access interception. */
3050         msrs->procbased_ctls_low &=
3051                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3052
3053         /*
3054          * secondary cpu-based controls.  Do not include those that
3055          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3056          */
3057         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3058                 msrs->secondary_ctls_low,
3059                 msrs->secondary_ctls_high);
3060         msrs->secondary_ctls_low = 0;
3061         msrs->secondary_ctls_high &=
3062                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3063                 SECONDARY_EXEC_DESC |
3064                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3065                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3066                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3067                 SECONDARY_EXEC_WBINVD_EXITING;
3068
3069         if (enable_ept) {
3070                 /* nested EPT: emulate EPT also to L1 */
3071                 msrs->secondary_ctls_high |=
3072                         SECONDARY_EXEC_ENABLE_EPT;
3073                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3074                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3075                 if (cpu_has_vmx_ept_execute_only())
3076                         msrs->ept_caps |=
3077                                 VMX_EPT_EXECUTE_ONLY_BIT;
3078                 msrs->ept_caps &= vmx_capability.ept;
3079                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3080                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3081                         VMX_EPT_1GB_PAGE_BIT;
3082                 if (enable_ept_ad_bits) {
3083                         msrs->secondary_ctls_high |=
3084                                 SECONDARY_EXEC_ENABLE_PML;
3085                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3086                 }
3087         }
3088
3089         if (cpu_has_vmx_vmfunc()) {
3090                 msrs->secondary_ctls_high |=
3091                         SECONDARY_EXEC_ENABLE_VMFUNC;
3092                 /*
3093                  * Advertise EPTP switching unconditionally
3094                  * since we emulate it
3095                  */
3096                 if (enable_ept)
3097                         msrs->vmfunc_controls =
3098                                 VMX_VMFUNC_EPTP_SWITCHING;
3099         }
3100
3101         /*
3102          * Old versions of KVM use the single-context version without
3103          * checking for support, so declare that it is supported even
3104          * though it is treated as global context.  The alternative is
3105          * not failing the single-context invvpid, and it is worse.
3106          */
3107         if (enable_vpid) {
3108                 msrs->secondary_ctls_high |=
3109                         SECONDARY_EXEC_ENABLE_VPID;
3110                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3111                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3112         }
3113
3114         if (enable_unrestricted_guest)
3115                 msrs->secondary_ctls_high |=
3116                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3117
3118         /* miscellaneous data */
3119         rdmsr(MSR_IA32_VMX_MISC,
3120                 msrs->misc_low,
3121                 msrs->misc_high);
3122         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3123         msrs->misc_low |=
3124                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3125                 VMX_MISC_ACTIVITY_HLT;
3126         msrs->misc_high = 0;
3127
3128         /*
3129          * This MSR reports some information about VMX support. We
3130          * should return information about the VMX we emulate for the
3131          * guest, and the VMCS structure we give it - not about the
3132          * VMX support of the underlying hardware.
3133          */
3134         msrs->basic =
3135                 VMCS12_REVISION |
3136                 VMX_BASIC_TRUE_CTLS |
3137                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3138                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3139
3140         if (cpu_has_vmx_basic_inout())
3141                 msrs->basic |= VMX_BASIC_INOUT;
3142
3143         /*
3144          * These MSRs specify bits which the guest must keep fixed on
3145          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3146          * We picked the standard core2 setting.
3147          */
3148 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3149 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3150         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3151         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3152
3153         /* These MSRs specify bits which the guest must keep fixed off. */
3154         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3155         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3156
3157         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3158         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3159 }
3160
3161 /*
3162  * if fixed0[i] == 1: val[i] must be 1
3163  * if fixed1[i] == 0: val[i] must be 0
3164  */
3165 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3166 {
3167         return ((val & fixed1) | fixed0) == val;
3168 }
3169
3170 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3171 {
3172         return fixed_bits_valid(control, low, high);
3173 }
3174
3175 static inline u64 vmx_control_msr(u32 low, u32 high)
3176 {
3177         return low | ((u64)high << 32);
3178 }
3179
3180 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3181 {
3182         superset &= mask;
3183         subset &= mask;
3184
3185         return (superset | subset) == superset;
3186 }
3187
3188 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3189 {
3190         const u64 feature_and_reserved =
3191                 /* feature (except bit 48; see below) */
3192                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3193                 /* reserved */
3194                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3195         u64 vmx_basic = vmx->nested.msrs.basic;
3196
3197         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3198                 return -EINVAL;
3199
3200         /*
3201          * KVM does not emulate a version of VMX that constrains physical
3202          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3203          */
3204         if (data & BIT_ULL(48))
3205                 return -EINVAL;
3206
3207         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3208             vmx_basic_vmcs_revision_id(data))
3209                 return -EINVAL;
3210
3211         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3212                 return -EINVAL;
3213
3214         vmx->nested.msrs.basic = data;
3215         return 0;
3216 }
3217
3218 static int
3219 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3220 {
3221         u64 supported;
3222         u32 *lowp, *highp;
3223
3224         switch (msr_index) {
3225         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3226                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3227                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3228                 break;
3229         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3230                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3231                 highp = &vmx->nested.msrs.procbased_ctls_high;
3232                 break;
3233         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3234                 lowp = &vmx->nested.msrs.exit_ctls_low;
3235                 highp = &vmx->nested.msrs.exit_ctls_high;
3236                 break;
3237         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3238                 lowp = &vmx->nested.msrs.entry_ctls_low;
3239                 highp = &vmx->nested.msrs.entry_ctls_high;
3240                 break;
3241         case MSR_IA32_VMX_PROCBASED_CTLS2:
3242                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3243                 highp = &vmx->nested.msrs.secondary_ctls_high;
3244                 break;
3245         default:
3246                 BUG();
3247         }
3248
3249         supported = vmx_control_msr(*lowp, *highp);
3250
3251         /* Check must-be-1 bits are still 1. */
3252         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3253                 return -EINVAL;
3254
3255         /* Check must-be-0 bits are still 0. */
3256         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3257                 return -EINVAL;
3258
3259         *lowp = data;
3260         *highp = data >> 32;
3261         return 0;
3262 }
3263
3264 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3265 {
3266         const u64 feature_and_reserved_bits =
3267                 /* feature */
3268                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3269                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3270                 /* reserved */
3271                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3272         u64 vmx_misc;
3273
3274         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3275                                    vmx->nested.msrs.misc_high);
3276
3277         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3278                 return -EINVAL;
3279
3280         if ((vmx->nested.msrs.pinbased_ctls_high &
3281              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3282             vmx_misc_preemption_timer_rate(data) !=
3283             vmx_misc_preemption_timer_rate(vmx_misc))
3284                 return -EINVAL;
3285
3286         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3287                 return -EINVAL;
3288
3289         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3290                 return -EINVAL;
3291
3292         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3293                 return -EINVAL;
3294
3295         vmx->nested.msrs.misc_low = data;
3296         vmx->nested.msrs.misc_high = data >> 32;
3297         return 0;
3298 }
3299
3300 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3301 {
3302         u64 vmx_ept_vpid_cap;
3303
3304         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3305                                            vmx->nested.msrs.vpid_caps);
3306
3307         /* Every bit is either reserved or a feature bit. */
3308         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3309                 return -EINVAL;
3310
3311         vmx->nested.msrs.ept_caps = data;
3312         vmx->nested.msrs.vpid_caps = data >> 32;
3313         return 0;
3314 }
3315
3316 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3317 {
3318         u64 *msr;
3319
3320         switch (msr_index) {
3321         case MSR_IA32_VMX_CR0_FIXED0:
3322                 msr = &vmx->nested.msrs.cr0_fixed0;
3323                 break;
3324         case MSR_IA32_VMX_CR4_FIXED0:
3325                 msr = &vmx->nested.msrs.cr4_fixed0;
3326                 break;
3327         default:
3328                 BUG();
3329         }
3330
3331         /*
3332          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3333          * must be 1 in the restored value.
3334          */
3335         if (!is_bitwise_subset(data, *msr, -1ULL))
3336                 return -EINVAL;
3337
3338         *msr = data;
3339         return 0;
3340 }
3341
3342 /*
3343  * Called when userspace is restoring VMX MSRs.
3344  *
3345  * Returns 0 on success, non-0 otherwise.
3346  */
3347 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3348 {
3349         struct vcpu_vmx *vmx = to_vmx(vcpu);
3350
3351         switch (msr_index) {
3352         case MSR_IA32_VMX_BASIC:
3353                 return vmx_restore_vmx_basic(vmx, data);
3354         case MSR_IA32_VMX_PINBASED_CTLS:
3355         case MSR_IA32_VMX_PROCBASED_CTLS:
3356         case MSR_IA32_VMX_EXIT_CTLS:
3357         case MSR_IA32_VMX_ENTRY_CTLS:
3358                 /*
3359                  * The "non-true" VMX capability MSRs are generated from the
3360                  * "true" MSRs, so we do not support restoring them directly.
3361                  *
3362                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3363                  * should restore the "true" MSRs with the must-be-1 bits
3364                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3365                  * DEFAULT SETTINGS".
3366                  */
3367                 return -EINVAL;
3368         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3369         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3370         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3371         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3372         case MSR_IA32_VMX_PROCBASED_CTLS2:
3373                 return vmx_restore_control_msr(vmx, msr_index, data);
3374         case MSR_IA32_VMX_MISC:
3375                 return vmx_restore_vmx_misc(vmx, data);
3376         case MSR_IA32_VMX_CR0_FIXED0:
3377         case MSR_IA32_VMX_CR4_FIXED0:
3378                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3379         case MSR_IA32_VMX_CR0_FIXED1:
3380         case MSR_IA32_VMX_CR4_FIXED1:
3381                 /*
3382                  * These MSRs are generated based on the vCPU's CPUID, so we
3383                  * do not support restoring them directly.
3384                  */
3385                 return -EINVAL;
3386         case MSR_IA32_VMX_EPT_VPID_CAP:
3387                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3388         case MSR_IA32_VMX_VMCS_ENUM:
3389                 vmx->nested.msrs.vmcs_enum = data;
3390                 return 0;
3391         default:
3392                 /*
3393                  * The rest of the VMX capability MSRs do not support restore.
3394                  */
3395                 return -EINVAL;
3396         }
3397 }
3398
3399 /* Returns 0 on success, non-0 otherwise. */
3400 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3401 {
3402         switch (msr_index) {
3403         case MSR_IA32_VMX_BASIC:
3404                 *pdata = msrs->basic;
3405                 break;
3406         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3407         case MSR_IA32_VMX_PINBASED_CTLS:
3408                 *pdata = vmx_control_msr(
3409                         msrs->pinbased_ctls_low,
3410                         msrs->pinbased_ctls_high);
3411                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3412                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3413                 break;
3414         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3415         case MSR_IA32_VMX_PROCBASED_CTLS:
3416                 *pdata = vmx_control_msr(
3417                         msrs->procbased_ctls_low,
3418                         msrs->procbased_ctls_high);
3419                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3420                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3421                 break;
3422         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3423         case MSR_IA32_VMX_EXIT_CTLS:
3424                 *pdata = vmx_control_msr(
3425                         msrs->exit_ctls_low,
3426                         msrs->exit_ctls_high);
3427                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3428                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3429                 break;
3430         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3431         case MSR_IA32_VMX_ENTRY_CTLS:
3432                 *pdata = vmx_control_msr(
3433                         msrs->entry_ctls_low,
3434                         msrs->entry_ctls_high);
3435                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3436                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3437                 break;
3438         case MSR_IA32_VMX_MISC:
3439                 *pdata = vmx_control_msr(
3440                         msrs->misc_low,
3441                         msrs->misc_high);
3442                 break;
3443         case MSR_IA32_VMX_CR0_FIXED0:
3444                 *pdata = msrs->cr0_fixed0;
3445                 break;
3446         case MSR_IA32_VMX_CR0_FIXED1:
3447                 *pdata = msrs->cr0_fixed1;
3448                 break;
3449         case MSR_IA32_VMX_CR4_FIXED0:
3450                 *pdata = msrs->cr4_fixed0;
3451                 break;
3452         case MSR_IA32_VMX_CR4_FIXED1:
3453                 *pdata = msrs->cr4_fixed1;
3454                 break;
3455         case MSR_IA32_VMX_VMCS_ENUM:
3456                 *pdata = msrs->vmcs_enum;
3457                 break;
3458         case MSR_IA32_VMX_PROCBASED_CTLS2:
3459                 *pdata = vmx_control_msr(
3460                         msrs->secondary_ctls_low,
3461                         msrs->secondary_ctls_high);
3462                 break;
3463         case MSR_IA32_VMX_EPT_VPID_CAP:
3464                 *pdata = msrs->ept_caps |
3465                         ((u64)msrs->vpid_caps << 32);
3466                 break;
3467         case MSR_IA32_VMX_VMFUNC:
3468                 *pdata = msrs->vmfunc_controls;
3469                 break;
3470         default:
3471                 return 1;
3472         }
3473
3474         return 0;
3475 }
3476
3477 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3478                                                  uint64_t val)
3479 {
3480         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3481
3482         return !(val & ~valid_bits);
3483 }
3484
3485 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3486 {
3487         switch (msr->index) {
3488         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3489                 if (!nested)
3490                         return 1;
3491                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3492         default:
3493                 return 1;
3494         }
3495
3496         return 0;
3497 }
3498
3499 /*
3500  * Reads an msr value (of 'msr_index') into 'pdata'.
3501  * Returns 0 on success, non-0 otherwise.
3502  * Assumes vcpu_load() was already called.
3503  */
3504 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3505 {
3506         struct vcpu_vmx *vmx = to_vmx(vcpu);
3507         struct shared_msr_entry *msr;
3508
3509         switch (msr_info->index) {
3510 #ifdef CONFIG_X86_64
3511         case MSR_FS_BASE:
3512                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3513                 break;
3514         case MSR_GS_BASE:
3515                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3516                 break;
3517         case MSR_KERNEL_GS_BASE:
3518                 vmx_load_host_state(vmx);
3519                 msr_info->data = vmx->msr_guest_kernel_gs_base;
3520                 break;
3521 #endif
3522         case MSR_EFER:
3523                 return kvm_get_msr_common(vcpu, msr_info);
3524         case MSR_IA32_SPEC_CTRL:
3525                 if (!msr_info->host_initiated &&
3526                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3527                         return 1;
3528
3529                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3530                 break;
3531         case MSR_IA32_ARCH_CAPABILITIES:
3532                 if (!msr_info->host_initiated &&
3533                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3534                         return 1;
3535                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3536                 break;
3537         case MSR_IA32_SYSENTER_CS:
3538                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3539                 break;
3540         case MSR_IA32_SYSENTER_EIP:
3541                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3542                 break;
3543         case MSR_IA32_SYSENTER_ESP:
3544                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3545                 break;
3546         case MSR_IA32_BNDCFGS:
3547                 if (!kvm_mpx_supported() ||
3548                     (!msr_info->host_initiated &&
3549                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3550                         return 1;
3551                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3552                 break;
3553         case MSR_IA32_MCG_EXT_CTL:
3554                 if (!msr_info->host_initiated &&
3555                     !(vmx->msr_ia32_feature_control &
3556                       FEATURE_CONTROL_LMCE))
3557                         return 1;
3558                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3559                 break;
3560         case MSR_IA32_FEATURE_CONTROL:
3561                 msr_info->data = vmx->msr_ia32_feature_control;
3562                 break;
3563         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3564                 if (!nested_vmx_allowed(vcpu))
3565                         return 1;
3566                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3567                                        &msr_info->data);
3568         case MSR_IA32_XSS:
3569                 if (!vmx_xsaves_supported())
3570                         return 1;
3571                 msr_info->data = vcpu->arch.ia32_xss;
3572                 break;
3573         case MSR_TSC_AUX:
3574                 if (!msr_info->host_initiated &&
3575                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3576                         return 1;
3577                 /* Otherwise falls through */
3578         default:
3579                 msr = find_msr_entry(vmx, msr_info->index);
3580                 if (msr) {
3581                         msr_info->data = msr->data;
3582                         break;
3583                 }
3584                 return kvm_get_msr_common(vcpu, msr_info);
3585         }
3586
3587         return 0;
3588 }
3589
3590 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3591
3592 /*
3593  * Writes msr value into into the appropriate "register".
3594  * Returns 0 on success, non-0 otherwise.
3595  * Assumes vcpu_load() was already called.
3596  */
3597 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3598 {
3599         struct vcpu_vmx *vmx = to_vmx(vcpu);
3600         struct shared_msr_entry *msr;
3601         int ret = 0;
3602         u32 msr_index = msr_info->index;
3603         u64 data = msr_info->data;
3604
3605         switch (msr_index) {
3606         case MSR_EFER:
3607                 ret = kvm_set_msr_common(vcpu, msr_info);
3608                 break;
3609 #ifdef CONFIG_X86_64
3610         case MSR_FS_BASE:
3611                 vmx_segment_cache_clear(vmx);
3612                 vmcs_writel(GUEST_FS_BASE, data);
3613                 break;
3614         case MSR_GS_BASE:
3615                 vmx_segment_cache_clear(vmx);
3616                 vmcs_writel(GUEST_GS_BASE, data);
3617                 break;
3618         case MSR_KERNEL_GS_BASE:
3619                 vmx_load_host_state(vmx);
3620                 vmx->msr_guest_kernel_gs_base = data;
3621                 break;
3622 #endif
3623         case MSR_IA32_SYSENTER_CS:
3624                 vmcs_write32(GUEST_SYSENTER_CS, data);
3625                 break;
3626         case MSR_IA32_SYSENTER_EIP:
3627                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3628                 break;
3629         case MSR_IA32_SYSENTER_ESP:
3630                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3631                 break;
3632         case MSR_IA32_BNDCFGS:
3633                 if (!kvm_mpx_supported() ||
3634                     (!msr_info->host_initiated &&
3635                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3636                         return 1;
3637                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3638                     (data & MSR_IA32_BNDCFGS_RSVD))
3639                         return 1;
3640                 vmcs_write64(GUEST_BNDCFGS, data);
3641                 break;
3642         case MSR_IA32_SPEC_CTRL:
3643                 if (!msr_info->host_initiated &&
3644                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3645                         return 1;
3646
3647                 /* The STIBP bit doesn't fault even if it's not advertised */
3648                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3649                         return 1;
3650
3651                 vmx->spec_ctrl = data;
3652
3653                 if (!data)
3654                         break;
3655
3656                 /*
3657                  * For non-nested:
3658                  * When it's written (to non-zero) for the first time, pass
3659                  * it through.
3660                  *
3661                  * For nested:
3662                  * The handling of the MSR bitmap for L2 guests is done in
3663                  * nested_vmx_merge_msr_bitmap. We should not touch the
3664                  * vmcs02.msr_bitmap here since it gets completely overwritten
3665                  * in the merging. We update the vmcs01 here for L1 as well
3666                  * since it will end up touching the MSR anyway now.
3667                  */
3668                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3669                                               MSR_IA32_SPEC_CTRL,
3670                                               MSR_TYPE_RW);
3671                 break;
3672         case MSR_IA32_PRED_CMD:
3673                 if (!msr_info->host_initiated &&
3674                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3675                         return 1;
3676
3677                 if (data & ~PRED_CMD_IBPB)
3678                         return 1;
3679
3680                 if (!data)
3681                         break;
3682
3683                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3684
3685                 /*
3686                  * For non-nested:
3687                  * When it's written (to non-zero) for the first time, pass
3688                  * it through.
3689                  *
3690                  * For nested:
3691                  * The handling of the MSR bitmap for L2 guests is done in
3692                  * nested_vmx_merge_msr_bitmap. We should not touch the
3693                  * vmcs02.msr_bitmap here since it gets completely overwritten
3694                  * in the merging.
3695                  */
3696                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3697                                               MSR_TYPE_W);
3698                 break;
3699         case MSR_IA32_ARCH_CAPABILITIES:
3700                 if (!msr_info->host_initiated)
3701                         return 1;
3702                 vmx->arch_capabilities = data;
3703                 break;
3704         case MSR_IA32_CR_PAT:
3705                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3706                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3707                                 return 1;
3708                         vmcs_write64(GUEST_IA32_PAT, data);
3709                         vcpu->arch.pat = data;
3710                         break;
3711                 }
3712                 ret = kvm_set_msr_common(vcpu, msr_info);
3713                 break;
3714         case MSR_IA32_TSC_ADJUST:
3715                 ret = kvm_set_msr_common(vcpu, msr_info);
3716                 break;
3717         case MSR_IA32_MCG_EXT_CTL:
3718                 if ((!msr_info->host_initiated &&
3719                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3720                        FEATURE_CONTROL_LMCE)) ||
3721                     (data & ~MCG_EXT_CTL_LMCE_EN))
3722                         return 1;
3723                 vcpu->arch.mcg_ext_ctl = data;
3724                 break;
3725         case MSR_IA32_FEATURE_CONTROL:
3726                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3727                     (to_vmx(vcpu)->msr_ia32_feature_control &
3728                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3729                         return 1;
3730                 vmx->msr_ia32_feature_control = data;
3731                 if (msr_info->host_initiated && data == 0)
3732                         vmx_leave_nested(vcpu);
3733                 break;
3734         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3735                 if (!msr_info->host_initiated)
3736                         return 1; /* they are read-only */
3737                 if (!nested_vmx_allowed(vcpu))
3738                         return 1;
3739                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3740         case MSR_IA32_XSS:
3741                 if (!vmx_xsaves_supported())
3742                         return 1;
3743                 /*
3744                  * The only supported bit as of Skylake is bit 8, but
3745                  * it is not supported on KVM.
3746                  */
3747                 if (data != 0)
3748                         return 1;
3749                 vcpu->arch.ia32_xss = data;
3750                 if (vcpu->arch.ia32_xss != host_xss)
3751                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3752                                 vcpu->arch.ia32_xss, host_xss);
3753                 else
3754                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3755                 break;
3756         case MSR_TSC_AUX:
3757                 if (!msr_info->host_initiated &&
3758                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3759                         return 1;
3760                 /* Check reserved bit, higher 32 bits should be zero */
3761                 if ((data >> 32) != 0)
3762                         return 1;
3763                 /* Otherwise falls through */
3764         default:
3765                 msr = find_msr_entry(vmx, msr_index);
3766                 if (msr) {
3767                         u64 old_msr_data = msr->data;
3768                         msr->data = data;
3769                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3770                                 preempt_disable();
3771                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3772                                                          msr->mask);
3773                                 preempt_enable();
3774                                 if (ret)
3775                                         msr->data = old_msr_data;
3776                         }
3777                         break;
3778                 }
3779                 ret = kvm_set_msr_common(vcpu, msr_info);
3780         }
3781
3782         return ret;
3783 }
3784
3785 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3786 {
3787         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3788         switch (reg) {
3789         case VCPU_REGS_RSP:
3790                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3791                 break;
3792         case VCPU_REGS_RIP:
3793                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3794                 break;
3795         case VCPU_EXREG_PDPTR:
3796                 if (enable_ept)
3797                         ept_save_pdptrs(vcpu);
3798                 break;
3799         default:
3800                 break;
3801         }
3802 }
3803
3804 static __init int cpu_has_kvm_support(void)
3805 {
3806         return cpu_has_vmx();
3807 }
3808
3809 static __init int vmx_disabled_by_bios(void)
3810 {
3811         u64 msr;
3812
3813         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3814         if (msr & FEATURE_CONTROL_LOCKED) {
3815                 /* launched w/ TXT and VMX disabled */
3816                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3817                         && tboot_enabled())
3818                         return 1;
3819                 /* launched w/o TXT and VMX only enabled w/ TXT */
3820                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3821                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3822                         && !tboot_enabled()) {
3823                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3824                                 "activate TXT before enabling KVM\n");
3825                         return 1;
3826                 }
3827                 /* launched w/o TXT and VMX disabled */
3828                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3829                         && !tboot_enabled())
3830                         return 1;
3831         }
3832
3833         return 0;
3834 }
3835
3836 static void kvm_cpu_vmxon(u64 addr)
3837 {
3838         cr4_set_bits(X86_CR4_VMXE);
3839         intel_pt_handle_vmx(1);
3840
3841         asm volatile (ASM_VMX_VMXON_RAX
3842                         : : "a"(&addr), "m"(addr)
3843                         : "memory", "cc");
3844 }
3845
3846 static int hardware_enable(void)
3847 {
3848         int cpu = raw_smp_processor_id();
3849         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3850         u64 old, test_bits;
3851
3852         if (cr4_read_shadow() & X86_CR4_VMXE)
3853                 return -EBUSY;
3854
3855         /*
3856          * This can happen if we hot-added a CPU but failed to allocate
3857          * VP assist page for it.
3858          */
3859         if (static_branch_unlikely(&enable_evmcs) &&
3860             !hv_get_vp_assist_page(cpu))
3861                 return -EFAULT;
3862
3863         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3864         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3865         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3866
3867         /*
3868          * Now we can enable the vmclear operation in kdump
3869          * since the loaded_vmcss_on_cpu list on this cpu
3870          * has been initialized.
3871          *
3872          * Though the cpu is not in VMX operation now, there
3873          * is no problem to enable the vmclear operation
3874          * for the loaded_vmcss_on_cpu list is empty!
3875          */
3876         crash_enable_local_vmclear(cpu);
3877
3878         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3879
3880         test_bits = FEATURE_CONTROL_LOCKED;
3881         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3882         if (tboot_enabled())
3883                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3884
3885         if ((old & test_bits) != test_bits) {
3886                 /* enable and lock */
3887                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3888         }
3889         kvm_cpu_vmxon(phys_addr);
3890         if (enable_ept)
3891                 ept_sync_global();
3892
3893         return 0;
3894 }
3895
3896 static void vmclear_local_loaded_vmcss(void)
3897 {
3898         int cpu = raw_smp_processor_id();
3899         struct loaded_vmcs *v, *n;
3900
3901         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3902                                  loaded_vmcss_on_cpu_link)
3903                 __loaded_vmcs_clear(v);
3904 }
3905
3906
3907 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3908  * tricks.
3909  */
3910 static void kvm_cpu_vmxoff(void)
3911 {
3912         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3913
3914         intel_pt_handle_vmx(0);
3915         cr4_clear_bits(X86_CR4_VMXE);
3916 }
3917
3918 static void hardware_disable(void)
3919 {
3920         vmclear_local_loaded_vmcss();
3921         kvm_cpu_vmxoff();
3922 }
3923
3924 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3925                                       u32 msr, u32 *result)
3926 {
3927         u32 vmx_msr_low, vmx_msr_high;
3928         u32 ctl = ctl_min | ctl_opt;
3929
3930         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3931
3932         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3933         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3934
3935         /* Ensure minimum (required) set of control bits are supported. */
3936         if (ctl_min & ~ctl)
3937                 return -EIO;
3938
3939         *result = ctl;
3940         return 0;
3941 }
3942
3943 static __init bool allow_1_setting(u32 msr, u32 ctl)
3944 {
3945         u32 vmx_msr_low, vmx_msr_high;
3946
3947         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3948         return vmx_msr_high & ctl;
3949 }
3950
3951 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3952 {
3953         u32 vmx_msr_low, vmx_msr_high;
3954         u32 min, opt, min2, opt2;
3955         u32 _pin_based_exec_control = 0;
3956         u32 _cpu_based_exec_control = 0;
3957         u32 _cpu_based_2nd_exec_control = 0;
3958         u32 _vmexit_control = 0;
3959         u32 _vmentry_control = 0;
3960
3961         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
3962         min = CPU_BASED_HLT_EXITING |
3963 #ifdef CONFIG_X86_64
3964               CPU_BASED_CR8_LOAD_EXITING |
3965               CPU_BASED_CR8_STORE_EXITING |
3966 #endif
3967               CPU_BASED_CR3_LOAD_EXITING |
3968               CPU_BASED_CR3_STORE_EXITING |
3969               CPU_BASED_UNCOND_IO_EXITING |
3970               CPU_BASED_MOV_DR_EXITING |
3971               CPU_BASED_USE_TSC_OFFSETING |
3972               CPU_BASED_MWAIT_EXITING |
3973               CPU_BASED_MONITOR_EXITING |
3974               CPU_BASED_INVLPG_EXITING |
3975               CPU_BASED_RDPMC_EXITING;
3976
3977         opt = CPU_BASED_TPR_SHADOW |
3978               CPU_BASED_USE_MSR_BITMAPS |
3979               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3980         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3981                                 &_cpu_based_exec_control) < 0)
3982                 return -EIO;
3983 #ifdef CONFIG_X86_64
3984         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3985                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3986                                            ~CPU_BASED_CR8_STORE_EXITING;
3987 #endif
3988         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3989                 min2 = 0;
3990                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3991                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3992                         SECONDARY_EXEC_WBINVD_EXITING |
3993                         SECONDARY_EXEC_ENABLE_VPID |
3994                         SECONDARY_EXEC_ENABLE_EPT |
3995                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3996                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3997                         SECONDARY_EXEC_DESC |
3998                         SECONDARY_EXEC_RDTSCP |
3999                         SECONDARY_EXEC_ENABLE_INVPCID |
4000                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4001                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4002                         SECONDARY_EXEC_SHADOW_VMCS |
4003                         SECONDARY_EXEC_XSAVES |
4004                         SECONDARY_EXEC_RDSEED_EXITING |
4005                         SECONDARY_EXEC_RDRAND_EXITING |
4006                         SECONDARY_EXEC_ENABLE_PML |
4007                         SECONDARY_EXEC_TSC_SCALING |
4008                         SECONDARY_EXEC_ENABLE_VMFUNC;
4009                 if (adjust_vmx_controls(min2, opt2,
4010                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4011                                         &_cpu_based_2nd_exec_control) < 0)
4012                         return -EIO;
4013         }
4014 #ifndef CONFIG_X86_64
4015         if (!(_cpu_based_2nd_exec_control &
4016                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4017                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4018 #endif
4019
4020         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4021                 _cpu_based_2nd_exec_control &= ~(
4022                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4023                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4024                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4025
4026         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4027                 &vmx_capability.ept, &vmx_capability.vpid);
4028
4029         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4030                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4031                    enabled */
4032                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4033                                              CPU_BASED_CR3_STORE_EXITING |
4034                                              CPU_BASED_INVLPG_EXITING);
4035         } else if (vmx_capability.ept) {
4036                 vmx_capability.ept = 0;
4037                 pr_warn_once("EPT CAP should not exist if not support "
4038                                 "1-setting enable EPT VM-execution control\n");
4039         }
4040         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4041                 vmx_capability.vpid) {
4042                 vmx_capability.vpid = 0;
4043                 pr_warn_once("VPID CAP should not exist if not support "
4044                                 "1-setting enable VPID VM-execution control\n");
4045         }
4046
4047         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4048 #ifdef CONFIG_X86_64
4049         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4050 #endif
4051         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4052                 VM_EXIT_CLEAR_BNDCFGS;
4053         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4054                                 &_vmexit_control) < 0)
4055                 return -EIO;
4056
4057         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4058         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4059                  PIN_BASED_VMX_PREEMPTION_TIMER;
4060         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4061                                 &_pin_based_exec_control) < 0)
4062                 return -EIO;
4063
4064         if (cpu_has_broken_vmx_preemption_timer())
4065                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4066         if (!(_cpu_based_2nd_exec_control &
4067                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4068                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4069
4070         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4071         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4072         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4073                                 &_vmentry_control) < 0)
4074                 return -EIO;
4075
4076         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4077
4078         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4079         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4080                 return -EIO;
4081
4082 #ifdef CONFIG_X86_64
4083         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4084         if (vmx_msr_high & (1u<<16))
4085                 return -EIO;
4086 #endif
4087
4088         /* Require Write-Back (WB) memory type for VMCS accesses. */
4089         if (((vmx_msr_high >> 18) & 15) != 6)
4090                 return -EIO;
4091
4092         vmcs_conf->size = vmx_msr_high & 0x1fff;
4093         vmcs_conf->order = get_order(vmcs_conf->size);
4094         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4095
4096         /* KVM supports Enlightened VMCS v1 only */
4097         if (static_branch_unlikely(&enable_evmcs))
4098                 vmcs_conf->revision_id = KVM_EVMCS_VERSION;
4099         else
4100                 vmcs_conf->revision_id = vmx_msr_low;
4101
4102         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4103         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4104         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4105         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4106         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4107
4108         if (static_branch_unlikely(&enable_evmcs))
4109                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4110
4111         cpu_has_load_ia32_efer =
4112                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4113                                 VM_ENTRY_LOAD_IA32_EFER)
4114                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4115                                    VM_EXIT_LOAD_IA32_EFER);
4116
4117         cpu_has_load_perf_global_ctrl =
4118                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4119                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4120                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4121                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4122
4123         /*
4124          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4125          * but due to errata below it can't be used. Workaround is to use
4126          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4127          *
4128          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4129          *
4130          * AAK155             (model 26)
4131          * AAP115             (model 30)
4132          * AAT100             (model 37)
4133          * BC86,AAY89,BD102   (model 44)
4134          * BA97               (model 46)
4135          *
4136          */
4137         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4138                 switch (boot_cpu_data.x86_model) {
4139                 case 26:
4140                 case 30:
4141                 case 37:
4142                 case 44:
4143                 case 46:
4144                         cpu_has_load_perf_global_ctrl = false;
4145                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4146                                         "does not work properly. Using workaround\n");
4147                         break;
4148                 default:
4149                         break;
4150                 }
4151         }
4152
4153         if (boot_cpu_has(X86_FEATURE_XSAVES))
4154                 rdmsrl(MSR_IA32_XSS, host_xss);
4155
4156         return 0;
4157 }
4158
4159 static struct vmcs *alloc_vmcs_cpu(int cpu)
4160 {
4161         int node = cpu_to_node(cpu);
4162         struct page *pages;
4163         struct vmcs *vmcs;
4164
4165         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4166         if (!pages)
4167                 return NULL;
4168         vmcs = page_address(pages);
4169         memset(vmcs, 0, vmcs_config.size);
4170         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
4171         return vmcs;
4172 }
4173
4174 static void free_vmcs(struct vmcs *vmcs)
4175 {
4176         free_pages((unsigned long)vmcs, vmcs_config.order);
4177 }
4178
4179 /*
4180  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4181  */
4182 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4183 {
4184         if (!loaded_vmcs->vmcs)
4185                 return;
4186         loaded_vmcs_clear(loaded_vmcs);
4187         free_vmcs(loaded_vmcs->vmcs);
4188         loaded_vmcs->vmcs = NULL;
4189         if (loaded_vmcs->msr_bitmap)
4190                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4191         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4192 }
4193
4194 static struct vmcs *alloc_vmcs(void)
4195 {
4196         return alloc_vmcs_cpu(raw_smp_processor_id());
4197 }
4198
4199 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4200 {
4201         loaded_vmcs->vmcs = alloc_vmcs();
4202         if (!loaded_vmcs->vmcs)
4203                 return -ENOMEM;
4204
4205         loaded_vmcs->shadow_vmcs = NULL;
4206         loaded_vmcs_init(loaded_vmcs);
4207
4208         if (cpu_has_vmx_msr_bitmap()) {
4209                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4210                 if (!loaded_vmcs->msr_bitmap)
4211                         goto out_vmcs;
4212                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4213         }
4214         return 0;
4215
4216 out_vmcs:
4217         free_loaded_vmcs(loaded_vmcs);
4218         return -ENOMEM;
4219 }
4220
4221 static void free_kvm_area(void)
4222 {
4223         int cpu;
4224
4225         for_each_possible_cpu(cpu) {
4226                 free_vmcs(per_cpu(vmxarea, cpu));
4227                 per_cpu(vmxarea, cpu) = NULL;
4228         }
4229 }
4230
4231 enum vmcs_field_width {
4232         VMCS_FIELD_WIDTH_U16 = 0,
4233         VMCS_FIELD_WIDTH_U64 = 1,
4234         VMCS_FIELD_WIDTH_U32 = 2,
4235         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4236 };
4237
4238 static inline int vmcs_field_width(unsigned long field)
4239 {
4240         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4241                 return VMCS_FIELD_WIDTH_U32;
4242         return (field >> 13) & 0x3 ;
4243 }
4244
4245 static inline int vmcs_field_readonly(unsigned long field)
4246 {
4247         return (((field >> 10) & 0x3) == 1);
4248 }
4249
4250 static void init_vmcs_shadow_fields(void)
4251 {
4252         int i, j;
4253
4254         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4255                 u16 field = shadow_read_only_fields[i];
4256                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4257                     (i + 1 == max_shadow_read_only_fields ||
4258                      shadow_read_only_fields[i + 1] != field + 1))
4259                         pr_err("Missing field from shadow_read_only_field %x\n",
4260                                field + 1);
4261
4262                 clear_bit(field, vmx_vmread_bitmap);
4263 #ifdef CONFIG_X86_64
4264                 if (field & 1)
4265                         continue;
4266 #endif
4267                 if (j < i)
4268                         shadow_read_only_fields[j] = field;
4269                 j++;
4270         }
4271         max_shadow_read_only_fields = j;
4272
4273         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4274                 u16 field = shadow_read_write_fields[i];
4275                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4276                     (i + 1 == max_shadow_read_write_fields ||
4277                      shadow_read_write_fields[i + 1] != field + 1))
4278                         pr_err("Missing field from shadow_read_write_field %x\n",
4279                                field + 1);
4280
4281                 /*
4282                  * PML and the preemption timer can be emulated, but the
4283                  * processor cannot vmwrite to fields that don't exist
4284                  * on bare metal.
4285                  */
4286                 switch (field) {
4287                 case GUEST_PML_INDEX:
4288                         if (!cpu_has_vmx_pml())
4289                                 continue;
4290                         break;
4291                 case VMX_PREEMPTION_TIMER_VALUE:
4292                         if (!cpu_has_vmx_preemption_timer())
4293                                 continue;
4294                         break;
4295                 case GUEST_INTR_STATUS:
4296                         if (!cpu_has_vmx_apicv())
4297                                 continue;
4298                         break;
4299                 default:
4300                         break;
4301                 }
4302
4303                 clear_bit(field, vmx_vmwrite_bitmap);
4304                 clear_bit(field, vmx_vmread_bitmap);
4305 #ifdef CONFIG_X86_64
4306                 if (field & 1)
4307                         continue;
4308 #endif
4309                 if (j < i)
4310                         shadow_read_write_fields[j] = field;
4311                 j++;
4312         }
4313         max_shadow_read_write_fields = j;
4314 }
4315
4316 static __init int alloc_kvm_area(void)
4317 {
4318         int cpu;
4319
4320         for_each_possible_cpu(cpu) {
4321                 struct vmcs *vmcs;
4322
4323                 vmcs = alloc_vmcs_cpu(cpu);
4324                 if (!vmcs) {
4325                         free_kvm_area();
4326                         return -ENOMEM;
4327                 }
4328
4329                 per_cpu(vmxarea, cpu) = vmcs;
4330         }
4331         return 0;
4332 }
4333
4334 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4335                 struct kvm_segment *save)
4336 {
4337         if (!emulate_invalid_guest_state) {
4338                 /*
4339                  * CS and SS RPL should be equal during guest entry according
4340                  * to VMX spec, but in reality it is not always so. Since vcpu
4341                  * is in the middle of the transition from real mode to
4342                  * protected mode it is safe to assume that RPL 0 is a good
4343                  * default value.
4344                  */
4345                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4346                         save->selector &= ~SEGMENT_RPL_MASK;
4347                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4348                 save->s = 1;
4349         }
4350         vmx_set_segment(vcpu, save, seg);
4351 }
4352
4353 static void enter_pmode(struct kvm_vcpu *vcpu)
4354 {
4355         unsigned long flags;
4356         struct vcpu_vmx *vmx = to_vmx(vcpu);
4357
4358         /*
4359          * Update real mode segment cache. It may be not up-to-date if sement
4360          * register was written while vcpu was in a guest mode.
4361          */
4362         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4363         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4364         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4365         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4366         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4367         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4368
4369         vmx->rmode.vm86_active = 0;
4370
4371         vmx_segment_cache_clear(vmx);
4372
4373         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4374
4375         flags = vmcs_readl(GUEST_RFLAGS);
4376         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4377         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4378         vmcs_writel(GUEST_RFLAGS, flags);
4379
4380         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4381                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4382
4383         update_exception_bitmap(vcpu);
4384
4385         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4386         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4387         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4388         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4389         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4390         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4391 }
4392
4393 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4394 {
4395         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4396         struct kvm_segment var = *save;
4397
4398         var.dpl = 0x3;
4399         if (seg == VCPU_SREG_CS)
4400                 var.type = 0x3;
4401
4402         if (!emulate_invalid_guest_state) {
4403                 var.selector = var.base >> 4;
4404                 var.base = var.base & 0xffff0;
4405                 var.limit = 0xffff;
4406                 var.g = 0;
4407                 var.db = 0;
4408                 var.present = 1;
4409                 var.s = 1;
4410                 var.l = 0;
4411                 var.unusable = 0;
4412                 var.type = 0x3;
4413                 var.avl = 0;
4414                 if (save->base & 0xf)
4415                         printk_once(KERN_WARNING "kvm: segment base is not "
4416                                         "paragraph aligned when entering "
4417                                         "protected mode (seg=%d)", seg);
4418         }
4419
4420         vmcs_write16(sf->selector, var.selector);
4421         vmcs_writel(sf->base, var.base);
4422         vmcs_write32(sf->limit, var.limit);
4423         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4424 }
4425
4426 static void enter_rmode(struct kvm_vcpu *vcpu)
4427 {
4428         unsigned long flags;
4429         struct vcpu_vmx *vmx = to_vmx(vcpu);
4430         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4431
4432         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4433         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4434         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4435         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4436         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4437         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4438         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4439
4440         vmx->rmode.vm86_active = 1;
4441
4442         /*
4443          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4444          * vcpu. Warn the user that an update is overdue.
4445          */
4446         if (!kvm_vmx->tss_addr)
4447                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4448                              "called before entering vcpu\n");
4449
4450         vmx_segment_cache_clear(vmx);
4451
4452         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4453         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4454         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4455
4456         flags = vmcs_readl(GUEST_RFLAGS);
4457         vmx->rmode.save_rflags = flags;
4458
4459         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4460
4461         vmcs_writel(GUEST_RFLAGS, flags);
4462         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4463         update_exception_bitmap(vcpu);
4464
4465         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4466         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4467         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4468         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4469         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4470         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4471
4472         kvm_mmu_reset_context(vcpu);
4473 }
4474
4475 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4476 {
4477         struct vcpu_vmx *vmx = to_vmx(vcpu);
4478         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4479
4480         if (!msr)
4481                 return;
4482
4483         /*
4484          * Force kernel_gs_base reloading before EFER changes, as control
4485          * of this msr depends on is_long_mode().
4486          */
4487         vmx_load_host_state(to_vmx(vcpu));
4488         vcpu->arch.efer = efer;
4489         if (efer & EFER_LMA) {
4490                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4491                 msr->data = efer;
4492         } else {
4493                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4494
4495                 msr->data = efer & ~EFER_LME;
4496         }
4497         setup_msrs(vmx);
4498 }
4499
4500 #ifdef CONFIG_X86_64
4501
4502 static void enter_lmode(struct kvm_vcpu *vcpu)
4503 {
4504         u32 guest_tr_ar;
4505
4506         vmx_segment_cache_clear(to_vmx(vcpu));
4507
4508         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4509         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4510                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4511                                      __func__);
4512                 vmcs_write32(GUEST_TR_AR_BYTES,
4513                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4514                              | VMX_AR_TYPE_BUSY_64_TSS);
4515         }
4516         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4517 }
4518
4519 static void exit_lmode(struct kvm_vcpu *vcpu)
4520 {
4521         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4522         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4523 }
4524
4525 #endif
4526
4527 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4528                                 bool invalidate_gpa)
4529 {
4530         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4531                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4532                         return;
4533                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4534         } else {
4535                 vpid_sync_context(vpid);
4536         }
4537 }
4538
4539 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4540 {
4541         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4542 }
4543
4544 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4545 {
4546         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4547
4548         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4549         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4550 }
4551
4552 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4553 {
4554         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4555                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4556         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4557 }
4558
4559 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4560 {
4561         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4562
4563         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4564         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4565 }
4566
4567 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4568 {
4569         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4570
4571         if (!test_bit(VCPU_EXREG_PDPTR,
4572                       (unsigned long *)&vcpu->arch.regs_dirty))
4573                 return;
4574
4575         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4576                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4577                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4578                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4579                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4580         }
4581 }
4582
4583 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4584 {
4585         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4586
4587         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4588                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4589                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4590                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4591                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4592         }
4593
4594         __set_bit(VCPU_EXREG_PDPTR,
4595                   (unsigned long *)&vcpu->arch.regs_avail);
4596         __set_bit(VCPU_EXREG_PDPTR,
4597                   (unsigned long *)&vcpu->arch.regs_dirty);
4598 }
4599
4600 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4601 {
4602         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4603         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4604         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4605
4606         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4607                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4608             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4609                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4610
4611         return fixed_bits_valid(val, fixed0, fixed1);
4612 }
4613
4614 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4615 {
4616         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4617         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4618
4619         return fixed_bits_valid(val, fixed0, fixed1);
4620 }
4621
4622 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4623 {
4624         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4625         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4626
4627         return fixed_bits_valid(val, fixed0, fixed1);
4628 }
4629
4630 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4631 #define nested_guest_cr4_valid  nested_cr4_valid
4632 #define nested_host_cr4_valid   nested_cr4_valid
4633
4634 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4635
4636 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4637                                         unsigned long cr0,
4638                                         struct kvm_vcpu *vcpu)
4639 {
4640         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4641                 vmx_decache_cr3(vcpu);
4642         if (!(cr0 & X86_CR0_PG)) {
4643                 /* From paging/starting to nonpaging */
4644                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4645                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4646                              (CPU_BASED_CR3_LOAD_EXITING |
4647                               CPU_BASED_CR3_STORE_EXITING));
4648                 vcpu->arch.cr0 = cr0;
4649                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4650         } else if (!is_paging(vcpu)) {
4651                 /* From nonpaging to paging */
4652                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4653                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4654                              ~(CPU_BASED_CR3_LOAD_EXITING |
4655                                CPU_BASED_CR3_STORE_EXITING));
4656                 vcpu->arch.cr0 = cr0;
4657                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4658         }
4659
4660         if (!(cr0 & X86_CR0_WP))
4661                 *hw_cr0 &= ~X86_CR0_WP;
4662 }
4663
4664 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4665 {
4666         struct vcpu_vmx *vmx = to_vmx(vcpu);
4667         unsigned long hw_cr0;
4668
4669         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4670         if (enable_unrestricted_guest)
4671                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4672         else {
4673                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4674
4675                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4676                         enter_pmode(vcpu);
4677
4678                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4679                         enter_rmode(vcpu);
4680         }
4681
4682 #ifdef CONFIG_X86_64
4683         if (vcpu->arch.efer & EFER_LME) {
4684                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4685                         enter_lmode(vcpu);
4686                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4687                         exit_lmode(vcpu);
4688         }
4689 #endif
4690
4691         if (enable_ept && !enable_unrestricted_guest)
4692                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4693
4694         vmcs_writel(CR0_READ_SHADOW, cr0);
4695         vmcs_writel(GUEST_CR0, hw_cr0);
4696         vcpu->arch.cr0 = cr0;
4697
4698         /* depends on vcpu->arch.cr0 to be set to a new value */
4699         vmx->emulation_required = emulation_required(vcpu);
4700 }
4701
4702 static int get_ept_level(struct kvm_vcpu *vcpu)
4703 {
4704         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4705                 return 5;
4706         return 4;
4707 }
4708
4709 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4710 {
4711         u64 eptp = VMX_EPTP_MT_WB;
4712
4713         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4714
4715         if (enable_ept_ad_bits &&
4716             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4717                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4718         eptp |= (root_hpa & PAGE_MASK);
4719
4720         return eptp;
4721 }
4722
4723 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4724 {
4725         unsigned long guest_cr3;
4726         u64 eptp;
4727
4728         guest_cr3 = cr3;
4729         if (enable_ept) {
4730                 eptp = construct_eptp(vcpu, cr3);
4731                 vmcs_write64(EPT_POINTER, eptp);
4732                 if (enable_unrestricted_guest || is_paging(vcpu) ||
4733                     is_guest_mode(vcpu))
4734                         guest_cr3 = kvm_read_cr3(vcpu);
4735                 else
4736                         guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
4737                 ept_load_pdptrs(vcpu);
4738         }
4739
4740         vmx_flush_tlb(vcpu, true);
4741         vmcs_writel(GUEST_CR3, guest_cr3);
4742 }
4743
4744 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4745 {
4746         /*
4747          * Pass through host's Machine Check Enable value to hw_cr4, which
4748          * is in force while we are in guest mode.  Do not let guests control
4749          * this bit, even if host CR4.MCE == 0.
4750          */
4751         unsigned long hw_cr4;
4752
4753         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
4754         if (enable_unrestricted_guest)
4755                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
4756         else if (to_vmx(vcpu)->rmode.vm86_active)
4757                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
4758         else
4759                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
4760
4761         if ((cr4 & X86_CR4_UMIP) && !boot_cpu_has(X86_FEATURE_UMIP)) {
4762                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4763                               SECONDARY_EXEC_DESC);
4764                 hw_cr4 &= ~X86_CR4_UMIP;
4765         } else if (!is_guest_mode(vcpu) ||
4766                    !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
4767                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4768                                 SECONDARY_EXEC_DESC);
4769
4770         if (cr4 & X86_CR4_VMXE) {
4771                 /*
4772                  * To use VMXON (and later other VMX instructions), a guest
4773                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4774                  * So basically the check on whether to allow nested VMX
4775                  * is here.
4776                  */
4777                 if (!nested_vmx_allowed(vcpu))
4778                         return 1;
4779         }
4780
4781         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4782                 return 1;
4783
4784         vcpu->arch.cr4 = cr4;
4785
4786         if (!enable_unrestricted_guest) {
4787                 if (enable_ept) {
4788                         if (!is_paging(vcpu)) {
4789                                 hw_cr4 &= ~X86_CR4_PAE;
4790                                 hw_cr4 |= X86_CR4_PSE;
4791                         } else if (!(cr4 & X86_CR4_PAE)) {
4792                                 hw_cr4 &= ~X86_CR4_PAE;
4793                         }
4794                 }
4795
4796                 /*
4797                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4798                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4799                  * to be manually disabled when guest switches to non-paging
4800                  * mode.
4801                  *
4802                  * If !enable_unrestricted_guest, the CPU is always running
4803                  * with CR0.PG=1 and CR4 needs to be modified.
4804                  * If enable_unrestricted_guest, the CPU automatically
4805                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4806                  */
4807                 if (!is_paging(vcpu))
4808                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4809         }
4810
4811         vmcs_writel(CR4_READ_SHADOW, cr4);
4812         vmcs_writel(GUEST_CR4, hw_cr4);
4813         return 0;
4814 }
4815
4816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4817                             struct kvm_segment *var, int seg)
4818 {
4819         struct vcpu_vmx *vmx = to_vmx(vcpu);
4820         u32 ar;
4821
4822         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4823                 *var = vmx->rmode.segs[seg];
4824                 if (seg == VCPU_SREG_TR
4825                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4826                         return;
4827                 var->base = vmx_read_guest_seg_base(vmx, seg);
4828                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4829                 return;
4830         }
4831         var->base = vmx_read_guest_seg_base(vmx, seg);
4832         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4833         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4834         ar = vmx_read_guest_seg_ar(vmx, seg);
4835         var->unusable = (ar >> 16) & 1;
4836         var->type = ar & 15;
4837         var->s = (ar >> 4) & 1;
4838         var->dpl = (ar >> 5) & 3;
4839         /*
4840          * Some userspaces do not preserve unusable property. Since usable
4841          * segment has to be present according to VMX spec we can use present
4842          * property to amend userspace bug by making unusable segment always
4843          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4844          * segment as unusable.
4845          */
4846         var->present = !var->unusable;
4847         var->avl = (ar >> 12) & 1;
4848         var->l = (ar >> 13) & 1;
4849         var->db = (ar >> 14) & 1;
4850         var->g = (ar >> 15) & 1;
4851 }
4852
4853 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4854 {
4855         struct kvm_segment s;
4856
4857         if (to_vmx(vcpu)->rmode.vm86_active) {
4858                 vmx_get_segment(vcpu, &s, seg);
4859                 return s.base;
4860         }
4861         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4862 }
4863
4864 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4865 {
4866         struct vcpu_vmx *vmx = to_vmx(vcpu);
4867
4868         if (unlikely(vmx->rmode.vm86_active))
4869                 return 0;
4870         else {
4871                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4872                 return VMX_AR_DPL(ar);
4873         }
4874 }
4875
4876 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4877 {
4878         u32 ar;
4879
4880         if (var->unusable || !var->present)
4881                 ar = 1 << 16;
4882         else {
4883                 ar = var->type & 15;
4884                 ar |= (var->s & 1) << 4;
4885                 ar |= (var->dpl & 3) << 5;
4886                 ar |= (var->present & 1) << 7;
4887                 ar |= (var->avl & 1) << 12;
4888                 ar |= (var->l & 1) << 13;
4889                 ar |= (var->db & 1) << 14;
4890                 ar |= (var->g & 1) << 15;
4891         }
4892
4893         return ar;
4894 }
4895
4896 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4897                             struct kvm_segment *var, int seg)
4898 {
4899         struct vcpu_vmx *vmx = to_vmx(vcpu);
4900         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4901
4902         vmx_segment_cache_clear(vmx);
4903
4904         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4905                 vmx->rmode.segs[seg] = *var;
4906                 if (seg == VCPU_SREG_TR)
4907                         vmcs_write16(sf->selector, var->selector);
4908                 else if (var->s)
4909                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4910                 goto out;
4911         }
4912
4913         vmcs_writel(sf->base, var->base);
4914         vmcs_write32(sf->limit, var->limit);
4915         vmcs_write16(sf->selector, var->selector);
4916
4917         /*
4918          *   Fix the "Accessed" bit in AR field of segment registers for older
4919          * qemu binaries.
4920          *   IA32 arch specifies that at the time of processor reset the
4921          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4922          * is setting it to 0 in the userland code. This causes invalid guest
4923          * state vmexit when "unrestricted guest" mode is turned on.
4924          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4925          * tree. Newer qemu binaries with that qemu fix would not need this
4926          * kvm hack.
4927          */
4928         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4929                 var->type |= 0x1; /* Accessed */
4930
4931         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4932
4933 out:
4934         vmx->emulation_required = emulation_required(vcpu);
4935 }
4936
4937 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4938 {
4939         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4940
4941         *db = (ar >> 14) & 1;
4942         *l = (ar >> 13) & 1;
4943 }
4944
4945 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4946 {
4947         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4948         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4949 }
4950
4951 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4952 {
4953         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4954         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4955 }
4956
4957 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4958 {
4959         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4960         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4961 }
4962
4963 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4964 {
4965         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4966         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4967 }
4968
4969 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4970 {
4971         struct kvm_segment var;
4972         u32 ar;
4973
4974         vmx_get_segment(vcpu, &var, seg);
4975         var.dpl = 0x3;
4976         if (seg == VCPU_SREG_CS)
4977                 var.type = 0x3;
4978         ar = vmx_segment_access_rights(&var);
4979
4980         if (var.base != (var.selector << 4))
4981                 return false;
4982         if (var.limit != 0xffff)
4983                 return false;
4984         if (ar != 0xf3)
4985                 return false;
4986
4987         return true;
4988 }
4989
4990 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4991 {
4992         struct kvm_segment cs;
4993         unsigned int cs_rpl;
4994
4995         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4996         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4997
4998         if (cs.unusable)
4999                 return false;
5000         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5001                 return false;
5002         if (!cs.s)
5003                 return false;
5004         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5005                 if (cs.dpl > cs_rpl)
5006                         return false;
5007         } else {
5008                 if (cs.dpl != cs_rpl)
5009                         return false;
5010         }
5011         if (!cs.present)
5012                 return false;
5013
5014         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5015         return true;
5016 }
5017
5018 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5019 {
5020         struct kvm_segment ss;
5021         unsigned int ss_rpl;
5022
5023         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5024         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5025
5026         if (ss.unusable)
5027                 return true;
5028         if (ss.type != 3 && ss.type != 7)
5029                 return false;
5030         if (!ss.s)
5031                 return false;
5032         if (ss.dpl != ss_rpl) /* DPL != RPL */
5033                 return false;
5034         if (!ss.present)
5035                 return false;
5036
5037         return true;
5038 }
5039
5040 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5041 {
5042         struct kvm_segment var;
5043         unsigned int rpl;
5044
5045         vmx_get_segment(vcpu, &var, seg);
5046         rpl = var.selector & SEGMENT_RPL_MASK;
5047
5048         if (var.unusable)
5049                 return true;
5050         if (!var.s)
5051                 return false;
5052         if (!var.present)
5053                 return false;
5054         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5055                 if (var.dpl < rpl) /* DPL < RPL */
5056                         return false;
5057         }
5058
5059         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5060          * rights flags
5061          */
5062         return true;
5063 }
5064
5065 static bool tr_valid(struct kvm_vcpu *vcpu)
5066 {
5067         struct kvm_segment tr;
5068
5069         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5070
5071         if (tr.unusable)
5072                 return false;
5073         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5074                 return false;
5075         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5076                 return false;
5077         if (!tr.present)
5078                 return false;
5079
5080         return true;
5081 }
5082
5083 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5084 {
5085         struct kvm_segment ldtr;
5086
5087         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5088
5089         if (ldtr.unusable)
5090                 return true;
5091         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5092                 return false;
5093         if (ldtr.type != 2)
5094                 return false;
5095         if (!ldtr.present)
5096                 return false;
5097
5098         return true;
5099 }
5100
5101 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5102 {
5103         struct kvm_segment cs, ss;
5104
5105         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5106         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5107
5108         return ((cs.selector & SEGMENT_RPL_MASK) ==
5109                  (ss.selector & SEGMENT_RPL_MASK));
5110 }
5111
5112 /*
5113  * Check if guest state is valid. Returns true if valid, false if
5114  * not.
5115  * We assume that registers are always usable
5116  */
5117 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5118 {
5119         if (enable_unrestricted_guest)
5120                 return true;
5121
5122         /* real mode guest state checks */
5123         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5124                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5125                         return false;
5126                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5127                         return false;
5128                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5129                         return false;
5130                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5131                         return false;
5132                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5133                         return false;
5134                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5135                         return false;
5136         } else {
5137         /* protected mode guest state checks */
5138                 if (!cs_ss_rpl_check(vcpu))
5139                         return false;
5140                 if (!code_segment_valid(vcpu))
5141                         return false;
5142                 if (!stack_segment_valid(vcpu))
5143                         return false;
5144                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5145                         return false;
5146                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5147                         return false;
5148                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5149                         return false;
5150                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5151                         return false;
5152                 if (!tr_valid(vcpu))
5153                         return false;
5154                 if (!ldtr_valid(vcpu))
5155                         return false;
5156         }
5157         /* TODO:
5158          * - Add checks on RIP
5159          * - Add checks on RFLAGS
5160          */
5161
5162         return true;
5163 }
5164
5165 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5166 {
5167         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5168 }
5169
5170 static int init_rmode_tss(struct kvm *kvm)
5171 {
5172         gfn_t fn;
5173         u16 data = 0;
5174         int idx, r;
5175
5176         idx = srcu_read_lock(&kvm->srcu);
5177         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5178         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5179         if (r < 0)
5180                 goto out;
5181         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5182         r = kvm_write_guest_page(kvm, fn++, &data,
5183                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5184         if (r < 0)
5185                 goto out;
5186         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5187         if (r < 0)
5188                 goto out;
5189         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5190         if (r < 0)
5191                 goto out;
5192         data = ~0;
5193         r = kvm_write_guest_page(kvm, fn, &data,
5194                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5195                                  sizeof(u8));
5196 out:
5197         srcu_read_unlock(&kvm->srcu, idx);
5198         return r;
5199 }
5200
5201 static int init_rmode_identity_map(struct kvm *kvm)
5202 {
5203         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5204         int i, idx, r = 0;
5205         kvm_pfn_t identity_map_pfn;
5206         u32 tmp;
5207
5208         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5209         mutex_lock(&kvm->slots_lock);
5210
5211         if (likely(kvm_vmx->ept_identity_pagetable_done))
5212                 goto out2;
5213
5214         if (!kvm_vmx->ept_identity_map_addr)
5215                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5216         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5217
5218         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5219                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5220         if (r < 0)
5221                 goto out2;
5222
5223         idx = srcu_read_lock(&kvm->srcu);
5224         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5225         if (r < 0)
5226                 goto out;
5227         /* Set up identity-mapping pagetable for EPT in real mode */
5228         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5229                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5230                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5231                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5232                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5233                 if (r < 0)
5234                         goto out;
5235         }
5236         kvm_vmx->ept_identity_pagetable_done = true;
5237
5238 out:
5239         srcu_read_unlock(&kvm->srcu, idx);
5240
5241 out2:
5242         mutex_unlock(&kvm->slots_lock);
5243         return r;
5244 }
5245
5246 static void seg_setup(int seg)
5247 {
5248         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5249         unsigned int ar;
5250
5251         vmcs_write16(sf->selector, 0);
5252         vmcs_writel(sf->base, 0);
5253         vmcs_write32(sf->limit, 0xffff);
5254         ar = 0x93;
5255         if (seg == VCPU_SREG_CS)
5256                 ar |= 0x08; /* code segment */
5257
5258         vmcs_write32(sf->ar_bytes, ar);
5259 }
5260
5261 static int alloc_apic_access_page(struct kvm *kvm)
5262 {
5263         struct page *page;
5264         int r = 0;
5265
5266         mutex_lock(&kvm->slots_lock);
5267         if (kvm->arch.apic_access_page_done)
5268                 goto out;
5269         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5270                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5271         if (r)
5272                 goto out;
5273
5274         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5275         if (is_error_page(page)) {
5276                 r = -EFAULT;
5277                 goto out;
5278         }
5279
5280         /*
5281          * Do not pin the page in memory, so that memory hot-unplug
5282          * is able to migrate it.
5283          */
5284         put_page(page);
5285         kvm->arch.apic_access_page_done = true;
5286 out:
5287         mutex_unlock(&kvm->slots_lock);
5288         return r;
5289 }
5290
5291 static int allocate_vpid(void)
5292 {
5293         int vpid;
5294
5295         if (!enable_vpid)
5296                 return 0;
5297         spin_lock(&vmx_vpid_lock);
5298         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5299         if (vpid < VMX_NR_VPIDS)
5300                 __set_bit(vpid, vmx_vpid_bitmap);
5301         else
5302                 vpid = 0;
5303         spin_unlock(&vmx_vpid_lock);
5304         return vpid;
5305 }
5306
5307 static void free_vpid(int vpid)
5308 {
5309         if (!enable_vpid || vpid == 0)
5310                 return;
5311         spin_lock(&vmx_vpid_lock);
5312         __clear_bit(vpid, vmx_vpid_bitmap);
5313         spin_unlock(&vmx_vpid_lock);
5314 }
5315
5316 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5317                                                           u32 msr, int type)
5318 {
5319         int f = sizeof(unsigned long);
5320
5321         if (!cpu_has_vmx_msr_bitmap())
5322                 return;
5323
5324         /*
5325          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5326          * have the write-low and read-high bitmap offsets the wrong way round.
5327          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5328          */
5329         if (msr <= 0x1fff) {
5330                 if (type & MSR_TYPE_R)
5331                         /* read-low */
5332                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5333
5334                 if (type & MSR_TYPE_W)
5335                         /* write-low */
5336                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5337
5338         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5339                 msr &= 0x1fff;
5340                 if (type & MSR_TYPE_R)
5341                         /* read-high */
5342                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5343
5344                 if (type & MSR_TYPE_W)
5345                         /* write-high */
5346                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5347
5348         }
5349 }
5350
5351 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5352                                                          u32 msr, int type)
5353 {
5354         int f = sizeof(unsigned long);
5355
5356         if (!cpu_has_vmx_msr_bitmap())
5357                 return;
5358
5359         /*
5360          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5361          * have the write-low and read-high bitmap offsets the wrong way round.
5362          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5363          */
5364         if (msr <= 0x1fff) {
5365                 if (type & MSR_TYPE_R)
5366                         /* read-low */
5367                         __set_bit(msr, msr_bitmap + 0x000 / f);
5368
5369                 if (type & MSR_TYPE_W)
5370                         /* write-low */
5371                         __set_bit(msr, msr_bitmap + 0x800 / f);
5372
5373         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5374                 msr &= 0x1fff;
5375                 if (type & MSR_TYPE_R)
5376                         /* read-high */
5377                         __set_bit(msr, msr_bitmap + 0x400 / f);
5378
5379                 if (type & MSR_TYPE_W)
5380                         /* write-high */
5381                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5382
5383         }
5384 }
5385
5386 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5387                                                       u32 msr, int type, bool value)
5388 {
5389         if (value)
5390                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5391         else
5392                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5393 }
5394
5395 /*
5396  * If a msr is allowed by L0, we should check whether it is allowed by L1.
5397  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5398  */
5399 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5400                                                unsigned long *msr_bitmap_nested,
5401                                                u32 msr, int type)
5402 {
5403         int f = sizeof(unsigned long);
5404
5405         /*
5406          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5407          * have the write-low and read-high bitmap offsets the wrong way round.
5408          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5409          */
5410         if (msr <= 0x1fff) {
5411                 if (type & MSR_TYPE_R &&
5412                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5413                         /* read-low */
5414                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5415
5416                 if (type & MSR_TYPE_W &&
5417                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5418                         /* write-low */
5419                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5420
5421         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5422                 msr &= 0x1fff;
5423                 if (type & MSR_TYPE_R &&
5424                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5425                         /* read-high */
5426                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5427
5428                 if (type & MSR_TYPE_W &&
5429                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5430                         /* write-high */
5431                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5432
5433         }
5434 }
5435
5436 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5437 {
5438         u8 mode = 0;
5439
5440         if (cpu_has_secondary_exec_ctrls() &&
5441             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5442              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5443                 mode |= MSR_BITMAP_MODE_X2APIC;
5444                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5445                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5446         }
5447
5448         if (is_long_mode(vcpu))
5449                 mode |= MSR_BITMAP_MODE_LM;
5450
5451         return mode;
5452 }
5453
5454 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5455
5456 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5457                                          u8 mode)
5458 {
5459         int msr;
5460
5461         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5462                 unsigned word = msr / BITS_PER_LONG;
5463                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5464                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5465         }
5466
5467         if (mode & MSR_BITMAP_MODE_X2APIC) {
5468                 /*
5469                  * TPR reads and writes can be virtualized even if virtual interrupt
5470                  * delivery is not in use.
5471                  */
5472                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5473                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5474                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5475                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5476                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5477                 }
5478         }
5479 }
5480
5481 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5482 {
5483         struct vcpu_vmx *vmx = to_vmx(vcpu);
5484         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5485         u8 mode = vmx_msr_bitmap_mode(vcpu);
5486         u8 changed = mode ^ vmx->msr_bitmap_mode;
5487
5488         if (!changed)
5489                 return;
5490
5491         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5492                                   !(mode & MSR_BITMAP_MODE_LM));
5493
5494         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5495                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5496
5497         vmx->msr_bitmap_mode = mode;
5498 }
5499
5500 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5501 {
5502         return enable_apicv;
5503 }
5504
5505 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5506 {
5507         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5508         gfn_t gfn;
5509
5510         /*
5511          * Don't need to mark the APIC access page dirty; it is never
5512          * written to by the CPU during APIC virtualization.
5513          */
5514
5515         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5516                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5517                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5518         }
5519
5520         if (nested_cpu_has_posted_intr(vmcs12)) {
5521                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5522                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5523         }
5524 }
5525
5526
5527 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5528 {
5529         struct vcpu_vmx *vmx = to_vmx(vcpu);
5530         int max_irr;
5531         void *vapic_page;
5532         u16 status;
5533
5534         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5535                 return;
5536
5537         vmx->nested.pi_pending = false;
5538         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5539                 return;
5540
5541         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5542         if (max_irr != 256) {
5543                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5544                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5545                         vapic_page, &max_irr);
5546                 kunmap(vmx->nested.virtual_apic_page);
5547
5548                 status = vmcs_read16(GUEST_INTR_STATUS);
5549                 if ((u8)max_irr > ((u8)status & 0xff)) {
5550                         status &= ~0xff;
5551                         status |= (u8)max_irr;
5552                         vmcs_write16(GUEST_INTR_STATUS, status);
5553                 }
5554         }
5555
5556         nested_mark_vmcs12_pages_dirty(vcpu);
5557 }
5558
5559 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5560                                                      bool nested)
5561 {
5562 #ifdef CONFIG_SMP
5563         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5564
5565         if (vcpu->mode == IN_GUEST_MODE) {
5566                 /*
5567                  * The vector of interrupt to be delivered to vcpu had
5568                  * been set in PIR before this function.
5569                  *
5570                  * Following cases will be reached in this block, and
5571                  * we always send a notification event in all cases as
5572                  * explained below.
5573                  *
5574                  * Case 1: vcpu keeps in non-root mode. Sending a
5575                  * notification event posts the interrupt to vcpu.
5576                  *
5577                  * Case 2: vcpu exits to root mode and is still
5578                  * runnable. PIR will be synced to vIRR before the
5579                  * next vcpu entry. Sending a notification event in
5580                  * this case has no effect, as vcpu is not in root
5581                  * mode.
5582                  *
5583                  * Case 3: vcpu exits to root mode and is blocked.
5584                  * vcpu_block() has already synced PIR to vIRR and
5585                  * never blocks vcpu if vIRR is not cleared. Therefore,
5586                  * a blocked vcpu here does not wait for any requested
5587                  * interrupts in PIR, and sending a notification event
5588                  * which has no effect is safe here.
5589                  */
5590
5591                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5592                 return true;
5593         }
5594 #endif
5595         return false;
5596 }
5597
5598 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5599                                                 int vector)
5600 {
5601         struct vcpu_vmx *vmx = to_vmx(vcpu);
5602
5603         if (is_guest_mode(vcpu) &&
5604             vector == vmx->nested.posted_intr_nv) {
5605                 /*
5606                  * If a posted intr is not recognized by hardware,
5607                  * we will accomplish it in the next vmentry.
5608                  */
5609                 vmx->nested.pi_pending = true;
5610                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5611                 /* the PIR and ON have been set by L1. */
5612                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5613                         kvm_vcpu_kick(vcpu);
5614                 return 0;
5615         }
5616         return -1;
5617 }
5618 /*
5619  * Send interrupt to vcpu via posted interrupt way.
5620  * 1. If target vcpu is running(non-root mode), send posted interrupt
5621  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5622  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5623  * interrupt from PIR in next vmentry.
5624  */
5625 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5626 {
5627         struct vcpu_vmx *vmx = to_vmx(vcpu);
5628         int r;
5629
5630         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5631         if (!r)
5632                 return;
5633
5634         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5635                 return;
5636
5637         /* If a previous notification has sent the IPI, nothing to do.  */
5638         if (pi_test_and_set_on(&vmx->pi_desc))
5639                 return;
5640
5641         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5642                 kvm_vcpu_kick(vcpu);
5643 }
5644
5645 /*
5646  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5647  * will not change in the lifetime of the guest.
5648  * Note that host-state that does change is set elsewhere. E.g., host-state
5649  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5650  */
5651 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5652 {
5653         u32 low32, high32;
5654         unsigned long tmpl;
5655         struct desc_ptr dt;
5656         unsigned long cr0, cr3, cr4;
5657
5658         cr0 = read_cr0();
5659         WARN_ON(cr0 & X86_CR0_TS);
5660         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5661
5662         /*
5663          * Save the most likely value for this task's CR3 in the VMCS.
5664          * We can't use __get_current_cr3_fast() because we're not atomic.
5665          */
5666         cr3 = __read_cr3();
5667         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5668         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5669
5670         /* Save the most likely value for this task's CR4 in the VMCS. */
5671         cr4 = cr4_read_shadow();
5672         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5673         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5674
5675         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5676 #ifdef CONFIG_X86_64
5677         /*
5678          * Load null selectors, so we can avoid reloading them in
5679          * __vmx_load_host_state(), in case userspace uses the null selectors
5680          * too (the expected case).
5681          */
5682         vmcs_write16(HOST_DS_SELECTOR, 0);
5683         vmcs_write16(HOST_ES_SELECTOR, 0);
5684 #else
5685         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5686         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5687 #endif
5688         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5689         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5690
5691         store_idt(&dt);
5692         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5693         vmx->host_idt_base = dt.address;
5694
5695         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5696
5697         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5698         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5699         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5700         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5701
5702         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5703                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5704                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5705         }
5706 }
5707
5708 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5709 {
5710         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5711         if (enable_ept)
5712                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5713         if (is_guest_mode(&vmx->vcpu))
5714                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5715                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5716         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5717 }
5718
5719 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5720 {
5721         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5722
5723         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5724                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5725
5726         if (!enable_vnmi)
5727                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5728
5729         /* Enable the preemption timer dynamically */
5730         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5731         return pin_based_exec_ctrl;
5732 }
5733
5734 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5735 {
5736         struct vcpu_vmx *vmx = to_vmx(vcpu);
5737
5738         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5739         if (cpu_has_secondary_exec_ctrls()) {
5740                 if (kvm_vcpu_apicv_active(vcpu))
5741                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5742                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5743                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5744                 else
5745                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5746                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5747                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5748         }
5749
5750         if (cpu_has_vmx_msr_bitmap())
5751                 vmx_update_msr_bitmap(vcpu);
5752 }
5753
5754 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5755 {
5756         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5757
5758         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5759                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5760
5761         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5762                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5763 #ifdef CONFIG_X86_64
5764                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5765                                 CPU_BASED_CR8_LOAD_EXITING;
5766 #endif
5767         }
5768         if (!enable_ept)
5769                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5770                                 CPU_BASED_CR3_LOAD_EXITING  |
5771                                 CPU_BASED_INVLPG_EXITING;
5772         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
5773                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
5774                                 CPU_BASED_MONITOR_EXITING);
5775         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
5776                 exec_control &= ~CPU_BASED_HLT_EXITING;
5777         return exec_control;
5778 }
5779
5780 static bool vmx_rdrand_supported(void)
5781 {
5782         return vmcs_config.cpu_based_2nd_exec_ctrl &
5783                 SECONDARY_EXEC_RDRAND_EXITING;
5784 }
5785
5786 static bool vmx_rdseed_supported(void)
5787 {
5788         return vmcs_config.cpu_based_2nd_exec_ctrl &
5789                 SECONDARY_EXEC_RDSEED_EXITING;
5790 }
5791
5792 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5793 {
5794         struct kvm_vcpu *vcpu = &vmx->vcpu;
5795
5796         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5797
5798         if (!cpu_need_virtualize_apic_accesses(vcpu))
5799                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5800         if (vmx->vpid == 0)
5801                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5802         if (!enable_ept) {
5803                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5804                 enable_unrestricted_guest = 0;
5805                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5806                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5807         }
5808         if (!enable_unrestricted_guest)
5809                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5810         if (kvm_pause_in_guest(vmx->vcpu.kvm))
5811                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5812         if (!kvm_vcpu_apicv_active(vcpu))
5813                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5814                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5815         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5816
5817         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
5818          * in vmx_set_cr4.  */
5819         exec_control &= ~SECONDARY_EXEC_DESC;
5820
5821         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5822            (handle_vmptrld).
5823            We can NOT enable shadow_vmcs here because we don't have yet
5824            a current VMCS12
5825         */
5826         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5827
5828         if (!enable_pml)
5829                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5830
5831         if (vmx_xsaves_supported()) {
5832                 /* Exposing XSAVES only when XSAVE is exposed */
5833                 bool xsaves_enabled =
5834                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5835                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5836
5837                 if (!xsaves_enabled)
5838                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5839
5840                 if (nested) {
5841                         if (xsaves_enabled)
5842                                 vmx->nested.msrs.secondary_ctls_high |=
5843                                         SECONDARY_EXEC_XSAVES;
5844                         else
5845                                 vmx->nested.msrs.secondary_ctls_high &=
5846                                         ~SECONDARY_EXEC_XSAVES;
5847                 }
5848         }
5849
5850         if (vmx_rdtscp_supported()) {
5851                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5852                 if (!rdtscp_enabled)
5853                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5854
5855                 if (nested) {
5856                         if (rdtscp_enabled)
5857                                 vmx->nested.msrs.secondary_ctls_high |=
5858                                         SECONDARY_EXEC_RDTSCP;
5859                         else
5860                                 vmx->nested.msrs.secondary_ctls_high &=
5861                                         ~SECONDARY_EXEC_RDTSCP;
5862                 }
5863         }
5864
5865         if (vmx_invpcid_supported()) {
5866                 /* Exposing INVPCID only when PCID is exposed */
5867                 bool invpcid_enabled =
5868                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5869                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5870
5871                 if (!invpcid_enabled) {
5872                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5873                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5874                 }
5875
5876                 if (nested) {
5877                         if (invpcid_enabled)
5878                                 vmx->nested.msrs.secondary_ctls_high |=
5879                                         SECONDARY_EXEC_ENABLE_INVPCID;
5880                         else
5881                                 vmx->nested.msrs.secondary_ctls_high &=
5882                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5883                 }
5884         }
5885
5886         if (vmx_rdrand_supported()) {
5887                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5888                 if (rdrand_enabled)
5889                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
5890
5891                 if (nested) {
5892                         if (rdrand_enabled)
5893                                 vmx->nested.msrs.secondary_ctls_high |=
5894                                         SECONDARY_EXEC_RDRAND_EXITING;
5895                         else
5896                                 vmx->nested.msrs.secondary_ctls_high &=
5897                                         ~SECONDARY_EXEC_RDRAND_EXITING;
5898                 }
5899         }
5900
5901         if (vmx_rdseed_supported()) {
5902                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5903                 if (rdseed_enabled)
5904                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
5905
5906                 if (nested) {
5907                         if (rdseed_enabled)
5908                                 vmx->nested.msrs.secondary_ctls_high |=
5909                                         SECONDARY_EXEC_RDSEED_EXITING;
5910                         else
5911                                 vmx->nested.msrs.secondary_ctls_high &=
5912                                         ~SECONDARY_EXEC_RDSEED_EXITING;
5913                 }
5914         }
5915
5916         vmx->secondary_exec_control = exec_control;
5917 }
5918
5919 static void ept_set_mmio_spte_mask(void)
5920 {
5921         /*
5922          * EPT Misconfigurations can be generated if the value of bits 2:0
5923          * of an EPT paging-structure entry is 110b (write/execute).
5924          */
5925         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5926                                    VMX_EPT_MISCONFIG_WX_VALUE);
5927 }
5928
5929 #define VMX_XSS_EXIT_BITMAP 0
5930 /*
5931  * Sets up the vmcs for emulated real mode.
5932  */
5933 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
5934 {
5935 #ifdef CONFIG_X86_64
5936         unsigned long a;
5937 #endif
5938         int i;
5939
5940         if (enable_shadow_vmcs) {
5941                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5942                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5943         }
5944         if (cpu_has_vmx_msr_bitmap())
5945                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
5946
5947         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5948
5949         /* Control */
5950         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5951         vmx->hv_deadline_tsc = -1;
5952
5953         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5954
5955         if (cpu_has_secondary_exec_ctrls()) {
5956                 vmx_compute_secondary_exec_control(vmx);
5957                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5958                              vmx->secondary_exec_control);
5959         }
5960
5961         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5962                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5963                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5964                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5965                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5966
5967                 vmcs_write16(GUEST_INTR_STATUS, 0);
5968
5969                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5970                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5971         }
5972
5973         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
5974                 vmcs_write32(PLE_GAP, ple_gap);
5975                 vmx->ple_window = ple_window;
5976                 vmx->ple_window_dirty = true;
5977         }
5978
5979         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5980         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5981         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5982
5983         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5984         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5985         vmx_set_constant_host_state(vmx);
5986 #ifdef CONFIG_X86_64
5987         rdmsrl(MSR_FS_BASE, a);
5988         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5989         rdmsrl(MSR_GS_BASE, a);
5990         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5991 #else
5992         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5993         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5994 #endif
5995
5996         if (cpu_has_vmx_vmfunc())
5997                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5998
5999         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6000         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6001         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
6002         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6003         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6004
6005         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6006                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6007
6008         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6009                 u32 index = vmx_msr_index[i];
6010                 u32 data_low, data_high;
6011                 int j = vmx->nmsrs;
6012
6013                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6014                         continue;
6015                 if (wrmsr_safe(index, data_low, data_high) < 0)
6016                         continue;
6017                 vmx->guest_msrs[j].index = i;
6018                 vmx->guest_msrs[j].data = 0;
6019                 vmx->guest_msrs[j].mask = -1ull;
6020                 ++vmx->nmsrs;
6021         }
6022
6023         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6024                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6025
6026         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6027
6028         /* 22.2.1, 20.8.1 */
6029         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6030
6031         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6032         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6033
6034         set_cr4_guest_host_mask(vmx);
6035
6036         if (vmx_xsaves_supported())
6037                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6038
6039         if (enable_pml) {
6040                 ASSERT(vmx->pml_pg);
6041                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6042                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6043         }
6044 }
6045
6046 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6047 {
6048         struct vcpu_vmx *vmx = to_vmx(vcpu);
6049         struct msr_data apic_base_msr;
6050         u64 cr0;
6051
6052         vmx->rmode.vm86_active = 0;
6053         vmx->spec_ctrl = 0;
6054
6055         vcpu->arch.microcode_version = 0x100000000ULL;
6056         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6057         kvm_set_cr8(vcpu, 0);
6058
6059         if (!init_event) {
6060                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6061                                      MSR_IA32_APICBASE_ENABLE;
6062                 if (kvm_vcpu_is_reset_bsp(vcpu))
6063                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6064                 apic_base_msr.host_initiated = true;
6065                 kvm_set_apic_base(vcpu, &apic_base_msr);
6066         }
6067
6068         vmx_segment_cache_clear(vmx);
6069
6070         seg_setup(VCPU_SREG_CS);
6071         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6072         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6073
6074         seg_setup(VCPU_SREG_DS);
6075         seg_setup(VCPU_SREG_ES);
6076         seg_setup(VCPU_SREG_FS);
6077         seg_setup(VCPU_SREG_GS);
6078         seg_setup(VCPU_SREG_SS);
6079
6080         vmcs_write16(GUEST_TR_SELECTOR, 0);
6081         vmcs_writel(GUEST_TR_BASE, 0);
6082         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6083         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6084
6085         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6086         vmcs_writel(GUEST_LDTR_BASE, 0);
6087         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6088         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6089
6090         if (!init_event) {
6091                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6092                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6093                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6094                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6095         }
6096
6097         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6098         kvm_rip_write(vcpu, 0xfff0);
6099
6100         vmcs_writel(GUEST_GDTR_BASE, 0);
6101         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6102
6103         vmcs_writel(GUEST_IDTR_BASE, 0);
6104         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6105
6106         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6107         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6108         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6109         if (kvm_mpx_supported())
6110                 vmcs_write64(GUEST_BNDCFGS, 0);
6111
6112         setup_msrs(vmx);
6113
6114         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6115
6116         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6117                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6118                 if (cpu_need_tpr_shadow(vcpu))
6119                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6120                                      __pa(vcpu->arch.apic->regs));
6121                 vmcs_write32(TPR_THRESHOLD, 0);
6122         }
6123
6124         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6125
6126         if (vmx->vpid != 0)
6127                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6128
6129         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6130         vmx->vcpu.arch.cr0 = cr0;
6131         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6132         vmx_set_cr4(vcpu, 0);
6133         vmx_set_efer(vcpu, 0);
6134
6135         update_exception_bitmap(vcpu);
6136
6137         vpid_sync_context(vmx->vpid);
6138         if (init_event)
6139                 vmx_clear_hlt(vcpu);
6140 }
6141
6142 /*
6143  * In nested virtualization, check if L1 asked to exit on external interrupts.
6144  * For most existing hypervisors, this will always return true.
6145  */
6146 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6147 {
6148         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6149                 PIN_BASED_EXT_INTR_MASK;
6150 }
6151
6152 /*
6153  * In nested virtualization, check if L1 has set
6154  * VM_EXIT_ACK_INTR_ON_EXIT
6155  */
6156 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6157 {
6158         return get_vmcs12(vcpu)->vm_exit_controls &
6159                 VM_EXIT_ACK_INTR_ON_EXIT;
6160 }
6161
6162 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6163 {
6164         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6165 }
6166
6167 static void enable_irq_window(struct kvm_vcpu *vcpu)
6168 {
6169         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6170                       CPU_BASED_VIRTUAL_INTR_PENDING);
6171 }
6172
6173 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6174 {
6175         if (!enable_vnmi ||
6176             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6177                 enable_irq_window(vcpu);
6178                 return;
6179         }
6180
6181         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6182                       CPU_BASED_VIRTUAL_NMI_PENDING);
6183 }
6184
6185 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6186 {
6187         struct vcpu_vmx *vmx = to_vmx(vcpu);
6188         uint32_t intr;
6189         int irq = vcpu->arch.interrupt.nr;
6190
6191         trace_kvm_inj_virq(irq);
6192
6193         ++vcpu->stat.irq_injections;
6194         if (vmx->rmode.vm86_active) {
6195                 int inc_eip = 0;
6196                 if (vcpu->arch.interrupt.soft)
6197                         inc_eip = vcpu->arch.event_exit_inst_len;
6198                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6199                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6200                 return;
6201         }
6202         intr = irq | INTR_INFO_VALID_MASK;
6203         if (vcpu->arch.interrupt.soft) {
6204                 intr |= INTR_TYPE_SOFT_INTR;
6205                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6206                              vmx->vcpu.arch.event_exit_inst_len);
6207         } else
6208                 intr |= INTR_TYPE_EXT_INTR;
6209         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6210
6211         vmx_clear_hlt(vcpu);
6212 }
6213
6214 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6215 {
6216         struct vcpu_vmx *vmx = to_vmx(vcpu);
6217
6218         if (!enable_vnmi) {
6219                 /*
6220                  * Tracking the NMI-blocked state in software is built upon
6221                  * finding the next open IRQ window. This, in turn, depends on
6222                  * well-behaving guests: They have to keep IRQs disabled at
6223                  * least as long as the NMI handler runs. Otherwise we may
6224                  * cause NMI nesting, maybe breaking the guest. But as this is
6225                  * highly unlikely, we can live with the residual risk.
6226                  */
6227                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6228                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6229         }
6230
6231         ++vcpu->stat.nmi_injections;
6232         vmx->loaded_vmcs->nmi_known_unmasked = false;
6233
6234         if (vmx->rmode.vm86_active) {
6235                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6236                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6237                 return;
6238         }
6239
6240         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6241                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6242
6243         vmx_clear_hlt(vcpu);
6244 }
6245
6246 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6247 {
6248         struct vcpu_vmx *vmx = to_vmx(vcpu);
6249         bool masked;
6250
6251         if (!enable_vnmi)
6252                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6253         if (vmx->loaded_vmcs->nmi_known_unmasked)
6254                 return false;
6255         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6256         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6257         return masked;
6258 }
6259
6260 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6261 {
6262         struct vcpu_vmx *vmx = to_vmx(vcpu);
6263
6264         if (!enable_vnmi) {
6265                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6266                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6267                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6268                 }
6269         } else {
6270                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6271                 if (masked)
6272                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6273                                       GUEST_INTR_STATE_NMI);
6274                 else
6275                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6276                                         GUEST_INTR_STATE_NMI);
6277         }
6278 }
6279
6280 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6281 {
6282         if (to_vmx(vcpu)->nested.nested_run_pending)
6283                 return 0;
6284
6285         if (!enable_vnmi &&
6286             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6287                 return 0;
6288
6289         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6290                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6291                    | GUEST_INTR_STATE_NMI));
6292 }
6293
6294 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6295 {
6296         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6297                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6298                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6299                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6300 }
6301
6302 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6303 {
6304         int ret;
6305
6306         if (enable_unrestricted_guest)
6307                 return 0;
6308
6309         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6310                                     PAGE_SIZE * 3);
6311         if (ret)
6312                 return ret;
6313         to_kvm_vmx(kvm)->tss_addr = addr;
6314         return init_rmode_tss(kvm);
6315 }
6316
6317 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6318 {
6319         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6320         return 0;
6321 }
6322
6323 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6324 {
6325         switch (vec) {
6326         case BP_VECTOR:
6327                 /*
6328                  * Update instruction length as we may reinject the exception
6329                  * from user space while in guest debugging mode.
6330                  */
6331                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6332                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6333                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6334                         return false;
6335                 /* fall through */
6336         case DB_VECTOR:
6337                 if (vcpu->guest_debug &
6338                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6339                         return false;
6340                 /* fall through */
6341         case DE_VECTOR:
6342         case OF_VECTOR:
6343         case BR_VECTOR:
6344         case UD_VECTOR:
6345         case DF_VECTOR:
6346         case SS_VECTOR:
6347         case GP_VECTOR:
6348         case MF_VECTOR:
6349                 return true;
6350         break;
6351         }
6352         return false;
6353 }
6354
6355 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6356                                   int vec, u32 err_code)
6357 {
6358         /*
6359          * Instruction with address size override prefix opcode 0x67
6360          * Cause the #SS fault with 0 error code in VM86 mode.
6361          */
6362         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6363                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6364                         if (vcpu->arch.halt_request) {
6365                                 vcpu->arch.halt_request = 0;
6366                                 return kvm_vcpu_halt(vcpu);
6367                         }
6368                         return 1;
6369                 }
6370                 return 0;
6371         }
6372
6373         /*
6374          * Forward all other exceptions that are valid in real mode.
6375          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6376          *        the required debugging infrastructure rework.
6377          */
6378         kvm_queue_exception(vcpu, vec);
6379         return 1;
6380 }
6381
6382 /*
6383  * Trigger machine check on the host. We assume all the MSRs are already set up
6384  * by the CPU and that we still run on the same CPU as the MCE occurred on.
6385  * We pass a fake environment to the machine check handler because we want
6386  * the guest to be always treated like user space, no matter what context
6387  * it used internally.
6388  */
6389 static void kvm_machine_check(void)
6390 {
6391 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6392         struct pt_regs regs = {
6393                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6394                 .flags = X86_EFLAGS_IF,
6395         };
6396
6397         do_machine_check(&regs, 0);
6398 #endif
6399 }
6400
6401 static int handle_machine_check(struct kvm_vcpu *vcpu)
6402 {
6403         /* already handled by vcpu_run */
6404         return 1;
6405 }
6406
6407 static int handle_exception(struct kvm_vcpu *vcpu)
6408 {
6409         struct vcpu_vmx *vmx = to_vmx(vcpu);
6410         struct kvm_run *kvm_run = vcpu->run;
6411         u32 intr_info, ex_no, error_code;
6412         unsigned long cr2, rip, dr6;
6413         u32 vect_info;
6414         enum emulation_result er;
6415
6416         vect_info = vmx->idt_vectoring_info;
6417         intr_info = vmx->exit_intr_info;
6418
6419         if (is_machine_check(intr_info))
6420                 return handle_machine_check(vcpu);
6421
6422         if (is_nmi(intr_info))
6423                 return 1;  /* already handled by vmx_vcpu_run() */
6424
6425         if (is_invalid_opcode(intr_info))
6426                 return handle_ud(vcpu);
6427
6428         error_code = 0;
6429         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6430                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6431
6432         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6433                 WARN_ON_ONCE(!enable_vmware_backdoor);
6434                 er = emulate_instruction(vcpu,
6435                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6436                 if (er == EMULATE_USER_EXIT)
6437                         return 0;
6438                 else if (er != EMULATE_DONE)
6439                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6440                 return 1;
6441         }
6442
6443         /*
6444          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6445          * MMIO, it is better to report an internal error.
6446          * See the comments in vmx_handle_exit.
6447          */
6448         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6449             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6450                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6451                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6452                 vcpu->run->internal.ndata = 3;
6453                 vcpu->run->internal.data[0] = vect_info;
6454                 vcpu->run->internal.data[1] = intr_info;
6455                 vcpu->run->internal.data[2] = error_code;
6456                 return 0;
6457         }
6458
6459         if (is_page_fault(intr_info)) {
6460                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6461                 /* EPT won't cause page fault directly */
6462                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6463                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6464         }
6465
6466         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6467
6468         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6469                 return handle_rmode_exception(vcpu, ex_no, error_code);
6470
6471         switch (ex_no) {
6472         case AC_VECTOR:
6473                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6474                 return 1;
6475         case DB_VECTOR:
6476                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6477                 if (!(vcpu->guest_debug &
6478                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6479                         vcpu->arch.dr6 &= ~15;
6480                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6481                         if (is_icebp(intr_info))
6482                                 skip_emulated_instruction(vcpu);
6483
6484                         kvm_queue_exception(vcpu, DB_VECTOR);
6485                         return 1;
6486                 }
6487                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6488                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6489                 /* fall through */
6490         case BP_VECTOR:
6491                 /*
6492                  * Update instruction length as we may reinject #BP from
6493                  * user space while in guest debugging mode. Reading it for
6494                  * #DB as well causes no harm, it is not used in that case.
6495                  */
6496                 vmx->vcpu.arch.event_exit_inst_len =
6497                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6498                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6499                 rip = kvm_rip_read(vcpu);
6500                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6501                 kvm_run->debug.arch.exception = ex_no;
6502                 break;
6503         default:
6504                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6505                 kvm_run->ex.exception = ex_no;
6506                 kvm_run->ex.error_code = error_code;
6507                 break;
6508         }
6509         return 0;
6510 }
6511
6512 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6513 {
6514         ++vcpu->stat.irq_exits;
6515         return 1;
6516 }
6517
6518 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6519 {
6520         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6521         vcpu->mmio_needed = 0;
6522         return 0;
6523 }
6524
6525 static int handle_io(struct kvm_vcpu *vcpu)
6526 {
6527         unsigned long exit_qualification;
6528         int size, in, string;
6529         unsigned port;
6530
6531         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6532         string = (exit_qualification & 16) != 0;
6533
6534         ++vcpu->stat.io_exits;
6535
6536         if (string)
6537                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6538
6539         port = exit_qualification >> 16;
6540         size = (exit_qualification & 7) + 1;
6541         in = (exit_qualification & 8) != 0;
6542
6543         return kvm_fast_pio(vcpu, size, port, in);
6544 }
6545
6546 static void
6547 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6548 {
6549         /*
6550          * Patch in the VMCALL instruction:
6551          */
6552         hypercall[0] = 0x0f;
6553         hypercall[1] = 0x01;
6554         hypercall[2] = 0xc1;
6555 }
6556
6557 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6558 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6559 {
6560         if (is_guest_mode(vcpu)) {
6561                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6562                 unsigned long orig_val = val;
6563
6564                 /*
6565                  * We get here when L2 changed cr0 in a way that did not change
6566                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6567                  * but did change L0 shadowed bits. So we first calculate the
6568                  * effective cr0 value that L1 would like to write into the
6569                  * hardware. It consists of the L2-owned bits from the new
6570                  * value combined with the L1-owned bits from L1's guest_cr0.
6571                  */
6572                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6573                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6574
6575                 if (!nested_guest_cr0_valid(vcpu, val))
6576                         return 1;
6577
6578                 if (kvm_set_cr0(vcpu, val))
6579                         return 1;
6580                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6581                 return 0;
6582         } else {
6583                 if (to_vmx(vcpu)->nested.vmxon &&
6584                     !nested_host_cr0_valid(vcpu, val))
6585                         return 1;
6586
6587                 return kvm_set_cr0(vcpu, val);
6588         }
6589 }
6590
6591 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6592 {
6593         if (is_guest_mode(vcpu)) {
6594                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6595                 unsigned long orig_val = val;
6596
6597                 /* analogously to handle_set_cr0 */
6598                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6599                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6600                 if (kvm_set_cr4(vcpu, val))
6601                         return 1;
6602                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6603                 return 0;
6604         } else
6605                 return kvm_set_cr4(vcpu, val);
6606 }
6607
6608 static int handle_desc(struct kvm_vcpu *vcpu)
6609 {
6610         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6611         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6612 }
6613
6614 static int handle_cr(struct kvm_vcpu *vcpu)
6615 {
6616         unsigned long exit_qualification, val;
6617         int cr;
6618         int reg;
6619         int err;
6620         int ret;
6621
6622         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6623         cr = exit_qualification & 15;
6624         reg = (exit_qualification >> 8) & 15;
6625         switch ((exit_qualification >> 4) & 3) {
6626         case 0: /* mov to cr */
6627                 val = kvm_register_readl(vcpu, reg);
6628                 trace_kvm_cr_write(cr, val);
6629                 switch (cr) {
6630                 case 0:
6631                         err = handle_set_cr0(vcpu, val);
6632                         return kvm_complete_insn_gp(vcpu, err);
6633                 case 3:
6634                         WARN_ON_ONCE(enable_unrestricted_guest);
6635                         err = kvm_set_cr3(vcpu, val);
6636                         return kvm_complete_insn_gp(vcpu, err);
6637                 case 4:
6638                         err = handle_set_cr4(vcpu, val);
6639                         return kvm_complete_insn_gp(vcpu, err);
6640                 case 8: {
6641                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6642                                 u8 cr8 = (u8)val;
6643                                 err = kvm_set_cr8(vcpu, cr8);
6644                                 ret = kvm_complete_insn_gp(vcpu, err);
6645                                 if (lapic_in_kernel(vcpu))
6646                                         return ret;
6647                                 if (cr8_prev <= cr8)
6648                                         return ret;
6649                                 /*
6650                                  * TODO: we might be squashing a
6651                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6652                                  * KVM_EXIT_DEBUG here.
6653                                  */
6654                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6655                                 return 0;
6656                         }
6657                 }
6658                 break;
6659         case 2: /* clts */
6660                 WARN_ONCE(1, "Guest should always own CR0.TS");
6661                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6662                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6663                 return kvm_skip_emulated_instruction(vcpu);
6664         case 1: /*mov from cr*/
6665                 switch (cr) {
6666                 case 3:
6667                         WARN_ON_ONCE(enable_unrestricted_guest);
6668                         val = kvm_read_cr3(vcpu);
6669                         kvm_register_write(vcpu, reg, val);
6670                         trace_kvm_cr_read(cr, val);
6671                         return kvm_skip_emulated_instruction(vcpu);
6672                 case 8:
6673                         val = kvm_get_cr8(vcpu);
6674                         kvm_register_write(vcpu, reg, val);
6675                         trace_kvm_cr_read(cr, val);
6676                         return kvm_skip_emulated_instruction(vcpu);
6677                 }
6678                 break;
6679         case 3: /* lmsw */
6680                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6681                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6682                 kvm_lmsw(vcpu, val);
6683
6684                 return kvm_skip_emulated_instruction(vcpu);
6685         default:
6686                 break;
6687         }
6688         vcpu->run->exit_reason = 0;
6689         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6690                (int)(exit_qualification >> 4) & 3, cr);
6691         return 0;
6692 }
6693
6694 static int handle_dr(struct kvm_vcpu *vcpu)
6695 {
6696         unsigned long exit_qualification;
6697         int dr, dr7, reg;
6698
6699         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6700         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6701
6702         /* First, if DR does not exist, trigger UD */
6703         if (!kvm_require_dr(vcpu, dr))
6704                 return 1;
6705
6706         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6707         if (!kvm_require_cpl(vcpu, 0))
6708                 return 1;
6709         dr7 = vmcs_readl(GUEST_DR7);
6710         if (dr7 & DR7_GD) {
6711                 /*
6712                  * As the vm-exit takes precedence over the debug trap, we
6713                  * need to emulate the latter, either for the host or the
6714                  * guest debugging itself.
6715                  */
6716                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6717                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6718                         vcpu->run->debug.arch.dr7 = dr7;
6719                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6720                         vcpu->run->debug.arch.exception = DB_VECTOR;
6721                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6722                         return 0;
6723                 } else {
6724                         vcpu->arch.dr6 &= ~15;
6725                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6726                         kvm_queue_exception(vcpu, DB_VECTOR);
6727                         return 1;
6728                 }
6729         }
6730
6731         if (vcpu->guest_debug == 0) {
6732                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6733                                 CPU_BASED_MOV_DR_EXITING);
6734
6735                 /*
6736                  * No more DR vmexits; force a reload of the debug registers
6737                  * and reenter on this instruction.  The next vmexit will
6738                  * retrieve the full state of the debug registers.
6739                  */
6740                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6741                 return 1;
6742         }
6743
6744         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6745         if (exit_qualification & TYPE_MOV_FROM_DR) {
6746                 unsigned long val;
6747
6748                 if (kvm_get_dr(vcpu, dr, &val))
6749                         return 1;
6750                 kvm_register_write(vcpu, reg, val);
6751         } else
6752                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6753                         return 1;
6754
6755         return kvm_skip_emulated_instruction(vcpu);
6756 }
6757
6758 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6759 {
6760         return vcpu->arch.dr6;
6761 }
6762
6763 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6764 {
6765 }
6766
6767 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6768 {
6769         get_debugreg(vcpu->arch.db[0], 0);
6770         get_debugreg(vcpu->arch.db[1], 1);
6771         get_debugreg(vcpu->arch.db[2], 2);
6772         get_debugreg(vcpu->arch.db[3], 3);
6773         get_debugreg(vcpu->arch.dr6, 6);
6774         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6775
6776         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6777         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6778 }
6779
6780 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6781 {
6782         vmcs_writel(GUEST_DR7, val);
6783 }
6784
6785 static int handle_cpuid(struct kvm_vcpu *vcpu)
6786 {
6787         return kvm_emulate_cpuid(vcpu);
6788 }
6789
6790 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6791 {
6792         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6793         struct msr_data msr_info;
6794
6795         msr_info.index = ecx;
6796         msr_info.host_initiated = false;
6797         if (vmx_get_msr(vcpu, &msr_info)) {
6798                 trace_kvm_msr_read_ex(ecx);
6799                 kvm_inject_gp(vcpu, 0);
6800                 return 1;
6801         }
6802
6803         trace_kvm_msr_read(ecx, msr_info.data);
6804
6805         /* FIXME: handling of bits 32:63 of rax, rdx */
6806         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6807         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6808         return kvm_skip_emulated_instruction(vcpu);
6809 }
6810
6811 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6812 {
6813         struct msr_data msr;
6814         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6815         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6816                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6817
6818         msr.data = data;
6819         msr.index = ecx;
6820         msr.host_initiated = false;
6821         if (kvm_set_msr(vcpu, &msr) != 0) {
6822                 trace_kvm_msr_write_ex(ecx, data);
6823                 kvm_inject_gp(vcpu, 0);
6824                 return 1;
6825         }
6826
6827         trace_kvm_msr_write(ecx, data);
6828         return kvm_skip_emulated_instruction(vcpu);
6829 }
6830
6831 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6832 {
6833         kvm_apic_update_ppr(vcpu);
6834         return 1;
6835 }
6836
6837 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6838 {
6839         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6840                         CPU_BASED_VIRTUAL_INTR_PENDING);
6841
6842         kvm_make_request(KVM_REQ_EVENT, vcpu);
6843
6844         ++vcpu->stat.irq_window_exits;
6845         return 1;
6846 }
6847
6848 static int handle_halt(struct kvm_vcpu *vcpu)
6849 {
6850         return kvm_emulate_halt(vcpu);
6851 }
6852
6853 static int handle_vmcall(struct kvm_vcpu *vcpu)
6854 {
6855         return kvm_emulate_hypercall(vcpu);
6856 }
6857
6858 static int handle_invd(struct kvm_vcpu *vcpu)
6859 {
6860         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6861 }
6862
6863 static int handle_invlpg(struct kvm_vcpu *vcpu)
6864 {
6865         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6866
6867         kvm_mmu_invlpg(vcpu, exit_qualification);
6868         return kvm_skip_emulated_instruction(vcpu);
6869 }
6870
6871 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6872 {
6873         int err;
6874
6875         err = kvm_rdpmc(vcpu);
6876         return kvm_complete_insn_gp(vcpu, err);
6877 }
6878
6879 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6880 {
6881         return kvm_emulate_wbinvd(vcpu);
6882 }
6883
6884 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6885 {
6886         u64 new_bv = kvm_read_edx_eax(vcpu);
6887         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6888
6889         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6890                 return kvm_skip_emulated_instruction(vcpu);
6891         return 1;
6892 }
6893
6894 static int handle_xsaves(struct kvm_vcpu *vcpu)
6895 {
6896         kvm_skip_emulated_instruction(vcpu);
6897         WARN(1, "this should never happen\n");
6898         return 1;
6899 }
6900
6901 static int handle_xrstors(struct kvm_vcpu *vcpu)
6902 {
6903         kvm_skip_emulated_instruction(vcpu);
6904         WARN(1, "this should never happen\n");
6905         return 1;
6906 }
6907
6908 static int handle_apic_access(struct kvm_vcpu *vcpu)
6909 {
6910         if (likely(fasteoi)) {
6911                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6912                 int access_type, offset;
6913
6914                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6915                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6916                 /*
6917                  * Sane guest uses MOV to write EOI, with written value
6918                  * not cared. So make a short-circuit here by avoiding
6919                  * heavy instruction emulation.
6920                  */
6921                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6922                     (offset == APIC_EOI)) {
6923                         kvm_lapic_set_eoi(vcpu);
6924                         return kvm_skip_emulated_instruction(vcpu);
6925                 }
6926         }
6927         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6928 }
6929
6930 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6931 {
6932         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6933         int vector = exit_qualification & 0xff;
6934
6935         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6936         kvm_apic_set_eoi_accelerated(vcpu, vector);
6937         return 1;
6938 }
6939
6940 static int handle_apic_write(struct kvm_vcpu *vcpu)
6941 {
6942         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6943         u32 offset = exit_qualification & 0xfff;
6944
6945         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6946         kvm_apic_write_nodecode(vcpu, offset);
6947         return 1;
6948 }
6949
6950 static int handle_task_switch(struct kvm_vcpu *vcpu)
6951 {
6952         struct vcpu_vmx *vmx = to_vmx(vcpu);
6953         unsigned long exit_qualification;
6954         bool has_error_code = false;
6955         u32 error_code = 0;
6956         u16 tss_selector;
6957         int reason, type, idt_v, idt_index;
6958
6959         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6960         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6961         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6962
6963         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6964
6965         reason = (u32)exit_qualification >> 30;
6966         if (reason == TASK_SWITCH_GATE && idt_v) {
6967                 switch (type) {
6968                 case INTR_TYPE_NMI_INTR:
6969                         vcpu->arch.nmi_injected = false;
6970                         vmx_set_nmi_mask(vcpu, true);
6971                         break;
6972                 case INTR_TYPE_EXT_INTR:
6973                 case INTR_TYPE_SOFT_INTR:
6974                         kvm_clear_interrupt_queue(vcpu);
6975                         break;
6976                 case INTR_TYPE_HARD_EXCEPTION:
6977                         if (vmx->idt_vectoring_info &
6978                             VECTORING_INFO_DELIVER_CODE_MASK) {
6979                                 has_error_code = true;
6980                                 error_code =
6981                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6982                         }
6983                         /* fall through */
6984                 case INTR_TYPE_SOFT_EXCEPTION:
6985                         kvm_clear_exception_queue(vcpu);
6986                         break;
6987                 default:
6988                         break;
6989                 }
6990         }
6991         tss_selector = exit_qualification;
6992
6993         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6994                        type != INTR_TYPE_EXT_INTR &&
6995                        type != INTR_TYPE_NMI_INTR))
6996                 skip_emulated_instruction(vcpu);
6997
6998         if (kvm_task_switch(vcpu, tss_selector,
6999                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7000                             has_error_code, error_code) == EMULATE_FAIL) {
7001                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7002                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7003                 vcpu->run->internal.ndata = 0;
7004                 return 0;
7005         }
7006
7007         /*
7008          * TODO: What about debug traps on tss switch?
7009          *       Are we supposed to inject them and update dr6?
7010          */
7011
7012         return 1;
7013 }
7014
7015 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7016 {
7017         unsigned long exit_qualification;
7018         gpa_t gpa;
7019         u64 error_code;
7020
7021         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7022
7023         /*
7024          * EPT violation happened while executing iret from NMI,
7025          * "blocked by NMI" bit has to be set before next VM entry.
7026          * There are errata that may cause this bit to not be set:
7027          * AAK134, BY25.
7028          */
7029         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7030                         enable_vnmi &&
7031                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7032                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7033
7034         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7035         trace_kvm_page_fault(gpa, exit_qualification);
7036
7037         /* Is it a read fault? */
7038         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7039                      ? PFERR_USER_MASK : 0;
7040         /* Is it a write fault? */
7041         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7042                       ? PFERR_WRITE_MASK : 0;
7043         /* Is it a fetch fault? */
7044         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7045                       ? PFERR_FETCH_MASK : 0;
7046         /* ept page table entry is present? */
7047         error_code |= (exit_qualification &
7048                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7049                         EPT_VIOLATION_EXECUTABLE))
7050                       ? PFERR_PRESENT_MASK : 0;
7051
7052         error_code |= (exit_qualification & 0x100) != 0 ?
7053                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7054
7055         vcpu->arch.exit_qualification = exit_qualification;
7056         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7057 }
7058
7059 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7060 {
7061         gpa_t gpa;
7062
7063         /*
7064          * A nested guest cannot optimize MMIO vmexits, because we have an
7065          * nGPA here instead of the required GPA.
7066          */
7067         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7068         if (!is_guest_mode(vcpu) &&
7069             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7070                 trace_kvm_fast_mmio(gpa);
7071                 /*
7072                  * Doing kvm_skip_emulated_instruction() depends on undefined
7073                  * behavior: Intel's manual doesn't mandate
7074                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7075                  * occurs and while on real hardware it was observed to be set,
7076                  * other hypervisors (namely Hyper-V) don't set it, we end up
7077                  * advancing IP with some random value. Disable fast mmio when
7078                  * running nested and keep it for real hardware in hope that
7079                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7080                  */
7081                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7082                         return kvm_skip_emulated_instruction(vcpu);
7083                 else
7084                         return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7085                                                        NULL, 0) == EMULATE_DONE;
7086         }
7087
7088         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7089 }
7090
7091 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7092 {
7093         WARN_ON_ONCE(!enable_vnmi);
7094         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7095                         CPU_BASED_VIRTUAL_NMI_PENDING);
7096         ++vcpu->stat.nmi_window_exits;
7097         kvm_make_request(KVM_REQ_EVENT, vcpu);
7098
7099         return 1;
7100 }
7101
7102 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7103 {
7104         struct vcpu_vmx *vmx = to_vmx(vcpu);
7105         enum emulation_result err = EMULATE_DONE;
7106         int ret = 1;
7107         u32 cpu_exec_ctrl;
7108         bool intr_window_requested;
7109         unsigned count = 130;
7110
7111         /*
7112          * We should never reach the point where we are emulating L2
7113          * due to invalid guest state as that means we incorrectly
7114          * allowed a nested VMEntry with an invalid vmcs12.
7115          */
7116         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7117
7118         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7119         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7120
7121         while (vmx->emulation_required && count-- != 0) {
7122                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7123                         return handle_interrupt_window(&vmx->vcpu);
7124
7125                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7126                         return 1;
7127
7128                 err = emulate_instruction(vcpu, 0);
7129
7130                 if (err == EMULATE_USER_EXIT) {
7131                         ++vcpu->stat.mmio_exits;
7132                         ret = 0;
7133                         goto out;
7134                 }
7135
7136                 if (err != EMULATE_DONE)
7137                         goto emulation_error;
7138
7139                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7140                     vcpu->arch.exception.pending)
7141                         goto emulation_error;
7142
7143                 if (vcpu->arch.halt_request) {
7144                         vcpu->arch.halt_request = 0;
7145                         ret = kvm_vcpu_halt(vcpu);
7146                         goto out;
7147                 }
7148
7149                 if (signal_pending(current))
7150                         goto out;
7151                 if (need_resched())
7152                         schedule();
7153         }
7154
7155 out:
7156         return ret;
7157
7158 emulation_error:
7159         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7160         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7161         vcpu->run->internal.ndata = 0;
7162         return 0;
7163 }
7164
7165 static void grow_ple_window(struct kvm_vcpu *vcpu)
7166 {
7167         struct vcpu_vmx *vmx = to_vmx(vcpu);
7168         int old = vmx->ple_window;
7169
7170         vmx->ple_window = __grow_ple_window(old, ple_window,
7171                                             ple_window_grow,
7172                                             ple_window_max);
7173
7174         if (vmx->ple_window != old)
7175                 vmx->ple_window_dirty = true;
7176
7177         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7178 }
7179
7180 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7181 {
7182         struct vcpu_vmx *vmx = to_vmx(vcpu);
7183         int old = vmx->ple_window;
7184
7185         vmx->ple_window = __shrink_ple_window(old, ple_window,
7186                                               ple_window_shrink,
7187                                               ple_window);
7188
7189         if (vmx->ple_window != old)
7190                 vmx->ple_window_dirty = true;
7191
7192         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7193 }
7194
7195 /*
7196  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7197  */
7198 static void wakeup_handler(void)
7199 {
7200         struct kvm_vcpu *vcpu;
7201         int cpu = smp_processor_id();
7202
7203         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7204         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7205                         blocked_vcpu_list) {
7206                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7207
7208                 if (pi_test_on(pi_desc) == 1)
7209                         kvm_vcpu_kick(vcpu);
7210         }
7211         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7212 }
7213
7214 static void vmx_enable_tdp(void)
7215 {
7216         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7217                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7218                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7219                 0ull, VMX_EPT_EXECUTABLE_MASK,
7220                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7221                 VMX_EPT_RWX_MASK, 0ull);
7222
7223         ept_set_mmio_spte_mask();
7224         kvm_enable_tdp();
7225 }
7226
7227 static __init int hardware_setup(void)
7228 {
7229         int r = -ENOMEM, i;
7230
7231         rdmsrl_safe(MSR_EFER, &host_efer);
7232
7233         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7234                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7235
7236         for (i = 0; i < VMX_BITMAP_NR; i++) {
7237                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7238                 if (!vmx_bitmap[i])
7239                         goto out;
7240         }
7241
7242         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7243         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7244
7245         if (setup_vmcs_config(&vmcs_config) < 0) {
7246                 r = -EIO;
7247                 goto out;
7248         }
7249
7250         if (boot_cpu_has(X86_FEATURE_NX))
7251                 kvm_enable_efer_bits(EFER_NX);
7252
7253         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7254                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7255                 enable_vpid = 0;
7256
7257         if (!cpu_has_vmx_ept() ||
7258             !cpu_has_vmx_ept_4levels() ||
7259             !cpu_has_vmx_ept_mt_wb() ||
7260             !cpu_has_vmx_invept_global())
7261                 enable_ept = 0;
7262
7263         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7264                 enable_ept_ad_bits = 0;
7265
7266         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7267                 enable_unrestricted_guest = 0;
7268
7269         if (!cpu_has_vmx_flexpriority())
7270                 flexpriority_enabled = 0;
7271
7272         if (!cpu_has_virtual_nmis())
7273                 enable_vnmi = 0;
7274
7275         /*
7276          * set_apic_access_page_addr() is used to reload apic access
7277          * page upon invalidation.  No need to do anything if not
7278          * using the APIC_ACCESS_ADDR VMCS field.
7279          */
7280         if (!flexpriority_enabled)
7281                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7282
7283         if (!cpu_has_vmx_tpr_shadow())
7284                 kvm_x86_ops->update_cr8_intercept = NULL;
7285
7286         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7287                 kvm_disable_largepages();
7288
7289         if (!cpu_has_vmx_ple()) {
7290                 ple_gap = 0;
7291                 ple_window = 0;
7292                 ple_window_grow = 0;
7293                 ple_window_max = 0;
7294                 ple_window_shrink = 0;
7295         }
7296
7297         if (!cpu_has_vmx_apicv()) {
7298                 enable_apicv = 0;
7299                 kvm_x86_ops->sync_pir_to_irr = NULL;
7300         }
7301
7302         if (cpu_has_vmx_tsc_scaling()) {
7303                 kvm_has_tsc_control = true;
7304                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7305                 kvm_tsc_scaling_ratio_frac_bits = 48;
7306         }
7307
7308         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7309
7310         if (enable_ept)
7311                 vmx_enable_tdp();
7312         else
7313                 kvm_disable_tdp();
7314
7315         /*
7316          * Only enable PML when hardware supports PML feature, and both EPT
7317          * and EPT A/D bit features are enabled -- PML depends on them to work.
7318          */
7319         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7320                 enable_pml = 0;
7321
7322         if (!enable_pml) {
7323                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7324                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7325                 kvm_x86_ops->flush_log_dirty = NULL;
7326                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7327         }
7328
7329         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7330                 u64 vmx_msr;
7331
7332                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7333                 cpu_preemption_timer_multi =
7334                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7335         } else {
7336                 kvm_x86_ops->set_hv_timer = NULL;
7337                 kvm_x86_ops->cancel_hv_timer = NULL;
7338         }
7339
7340         if (!cpu_has_vmx_shadow_vmcs())
7341                 enable_shadow_vmcs = 0;
7342         if (enable_shadow_vmcs)
7343                 init_vmcs_shadow_fields();
7344
7345         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7346         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7347
7348         kvm_mce_cap_supported |= MCG_LMCE_P;
7349
7350         return alloc_kvm_area();
7351
7352 out:
7353         for (i = 0; i < VMX_BITMAP_NR; i++)
7354                 free_page((unsigned long)vmx_bitmap[i]);
7355
7356     return r;
7357 }
7358
7359 static __exit void hardware_unsetup(void)
7360 {
7361         int i;
7362
7363         for (i = 0; i < VMX_BITMAP_NR; i++)
7364                 free_page((unsigned long)vmx_bitmap[i]);
7365
7366         free_kvm_area();
7367 }
7368
7369 /*
7370  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7371  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7372  */
7373 static int handle_pause(struct kvm_vcpu *vcpu)
7374 {
7375         if (!kvm_pause_in_guest(vcpu->kvm))
7376                 grow_ple_window(vcpu);
7377
7378         /*
7379          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7380          * VM-execution control is ignored if CPL > 0. OTOH, KVM
7381          * never set PAUSE_EXITING and just set PLE if supported,
7382          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7383          */
7384         kvm_vcpu_on_spin(vcpu, true);
7385         return kvm_skip_emulated_instruction(vcpu);
7386 }
7387
7388 static int handle_nop(struct kvm_vcpu *vcpu)
7389 {
7390         return kvm_skip_emulated_instruction(vcpu);
7391 }
7392
7393 static int handle_mwait(struct kvm_vcpu *vcpu)
7394 {
7395         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7396         return handle_nop(vcpu);
7397 }
7398
7399 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7400 {
7401         kvm_queue_exception(vcpu, UD_VECTOR);
7402         return 1;
7403 }
7404
7405 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7406 {
7407         return 1;
7408 }
7409
7410 static int handle_monitor(struct kvm_vcpu *vcpu)
7411 {
7412         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7413         return handle_nop(vcpu);
7414 }
7415
7416 /*
7417  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7418  * set the success or error code of an emulated VMX instruction, as specified
7419  * by Vol 2B, VMX Instruction Reference, "Conventions".
7420  */
7421 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7422 {
7423         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7424                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7425                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7426 }
7427
7428 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7429 {
7430         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7431                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7432                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7433                         | X86_EFLAGS_CF);
7434 }
7435
7436 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7437                                         u32 vm_instruction_error)
7438 {
7439         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7440                 /*
7441                  * failValid writes the error number to the current VMCS, which
7442                  * can't be done there isn't a current VMCS.
7443                  */
7444                 nested_vmx_failInvalid(vcpu);
7445                 return;
7446         }
7447         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7448                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7449                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7450                         | X86_EFLAGS_ZF);
7451         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7452         /*
7453          * We don't need to force a shadow sync because
7454          * VM_INSTRUCTION_ERROR is not shadowed
7455          */
7456 }
7457
7458 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7459 {
7460         /* TODO: not to reset guest simply here. */
7461         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7462         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7463 }
7464
7465 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7466 {
7467         struct vcpu_vmx *vmx =
7468                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7469
7470         vmx->nested.preemption_timer_expired = true;
7471         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7472         kvm_vcpu_kick(&vmx->vcpu);
7473
7474         return HRTIMER_NORESTART;
7475 }
7476
7477 /*
7478  * Decode the memory-address operand of a vmx instruction, as recorded on an
7479  * exit caused by such an instruction (run by a guest hypervisor).
7480  * On success, returns 0. When the operand is invalid, returns 1 and throws
7481  * #UD or #GP.
7482  */
7483 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7484                                  unsigned long exit_qualification,
7485                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7486 {
7487         gva_t off;
7488         bool exn;
7489         struct kvm_segment s;
7490
7491         /*
7492          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7493          * Execution", on an exit, vmx_instruction_info holds most of the
7494          * addressing components of the operand. Only the displacement part
7495          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7496          * For how an actual address is calculated from all these components,
7497          * refer to Vol. 1, "Operand Addressing".
7498          */
7499         int  scaling = vmx_instruction_info & 3;
7500         int  addr_size = (vmx_instruction_info >> 7) & 7;
7501         bool is_reg = vmx_instruction_info & (1u << 10);
7502         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7503         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7504         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7505         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7506         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7507
7508         if (is_reg) {
7509                 kvm_queue_exception(vcpu, UD_VECTOR);
7510                 return 1;
7511         }
7512
7513         /* Addr = segment_base + offset */
7514         /* offset = base + [index * scale] + displacement */
7515         off = exit_qualification; /* holds the displacement */
7516         if (base_is_valid)
7517                 off += kvm_register_read(vcpu, base_reg);
7518         if (index_is_valid)
7519                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7520         vmx_get_segment(vcpu, &s, seg_reg);
7521         *ret = s.base + off;
7522
7523         if (addr_size == 1) /* 32 bit */
7524                 *ret &= 0xffffffff;
7525
7526         /* Checks for #GP/#SS exceptions. */
7527         exn = false;
7528         if (is_long_mode(vcpu)) {
7529                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7530                  * non-canonical form. This is the only check on the memory
7531                  * destination for long mode!
7532                  */
7533                 exn = is_noncanonical_address(*ret, vcpu);
7534         } else if (is_protmode(vcpu)) {
7535                 /* Protected mode: apply checks for segment validity in the
7536                  * following order:
7537                  * - segment type check (#GP(0) may be thrown)
7538                  * - usability check (#GP(0)/#SS(0))
7539                  * - limit check (#GP(0)/#SS(0))
7540                  */
7541                 if (wr)
7542                         /* #GP(0) if the destination operand is located in a
7543                          * read-only data segment or any code segment.
7544                          */
7545                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7546                 else
7547                         /* #GP(0) if the source operand is located in an
7548                          * execute-only code segment
7549                          */
7550                         exn = ((s.type & 0xa) == 8);
7551                 if (exn) {
7552                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7553                         return 1;
7554                 }
7555                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7556                  */
7557                 exn = (s.unusable != 0);
7558                 /* Protected mode: #GP(0)/#SS(0) if the memory
7559                  * operand is outside the segment limit.
7560                  */
7561                 exn = exn || (off + sizeof(u64) > s.limit);
7562         }
7563         if (exn) {
7564                 kvm_queue_exception_e(vcpu,
7565                                       seg_reg == VCPU_SREG_SS ?
7566                                                 SS_VECTOR : GP_VECTOR,
7567                                       0);
7568                 return 1;
7569         }
7570
7571         return 0;
7572 }
7573
7574 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7575 {
7576         gva_t gva;
7577         struct x86_exception e;
7578
7579         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7580                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7581                 return 1;
7582
7583         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7584                                 sizeof(*vmpointer), &e)) {
7585                 kvm_inject_page_fault(vcpu, &e);
7586                 return 1;
7587         }
7588
7589         return 0;
7590 }
7591
7592 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7593 {
7594         struct vcpu_vmx *vmx = to_vmx(vcpu);
7595         struct vmcs *shadow_vmcs;
7596         int r;
7597
7598         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7599         if (r < 0)
7600                 goto out_vmcs02;
7601
7602         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7603         if (!vmx->nested.cached_vmcs12)
7604                 goto out_cached_vmcs12;
7605
7606         if (enable_shadow_vmcs) {
7607                 shadow_vmcs = alloc_vmcs();
7608                 if (!shadow_vmcs)
7609                         goto out_shadow_vmcs;
7610                 /* mark vmcs as shadow */
7611                 shadow_vmcs->revision_id |= (1u << 31);
7612                 /* init shadow vmcs */
7613                 vmcs_clear(shadow_vmcs);
7614                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7615         }
7616
7617         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7618                      HRTIMER_MODE_REL_PINNED);
7619         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7620
7621         vmx->nested.vmxon = true;
7622         return 0;
7623
7624 out_shadow_vmcs:
7625         kfree(vmx->nested.cached_vmcs12);
7626
7627 out_cached_vmcs12:
7628         free_loaded_vmcs(&vmx->nested.vmcs02);
7629
7630 out_vmcs02:
7631         return -ENOMEM;
7632 }
7633
7634 /*
7635  * Emulate the VMXON instruction.
7636  * Currently, we just remember that VMX is active, and do not save or even
7637  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7638  * do not currently need to store anything in that guest-allocated memory
7639  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7640  * argument is different from the VMXON pointer (which the spec says they do).
7641  */
7642 static int handle_vmon(struct kvm_vcpu *vcpu)
7643 {
7644         int ret;
7645         gpa_t vmptr;
7646         struct page *page;
7647         struct vcpu_vmx *vmx = to_vmx(vcpu);
7648         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7649                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7650
7651         /*
7652          * The Intel VMX Instruction Reference lists a bunch of bits that are
7653          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7654          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7655          * Otherwise, we should fail with #UD.  But most faulting conditions
7656          * have already been checked by hardware, prior to the VM-exit for
7657          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7658          * that bit set to 1 in non-root mode.
7659          */
7660         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7661                 kvm_queue_exception(vcpu, UD_VECTOR);
7662                 return 1;
7663         }
7664
7665         if (vmx->nested.vmxon) {
7666                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7667                 return kvm_skip_emulated_instruction(vcpu);
7668         }
7669
7670         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7671                         != VMXON_NEEDED_FEATURES) {
7672                 kvm_inject_gp(vcpu, 0);
7673                 return 1;
7674         }
7675
7676         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7677                 return 1;
7678
7679         /*
7680          * SDM 3: 24.11.5
7681          * The first 4 bytes of VMXON region contain the supported
7682          * VMCS revision identifier
7683          *
7684          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7685          * which replaces physical address width with 32
7686          */
7687         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7688                 nested_vmx_failInvalid(vcpu);
7689                 return kvm_skip_emulated_instruction(vcpu);
7690         }
7691
7692         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7693         if (is_error_page(page)) {
7694                 nested_vmx_failInvalid(vcpu);
7695                 return kvm_skip_emulated_instruction(vcpu);
7696         }
7697         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7698                 kunmap(page);
7699                 kvm_release_page_clean(page);
7700                 nested_vmx_failInvalid(vcpu);
7701                 return kvm_skip_emulated_instruction(vcpu);
7702         }
7703         kunmap(page);
7704         kvm_release_page_clean(page);
7705
7706         vmx->nested.vmxon_ptr = vmptr;
7707         ret = enter_vmx_operation(vcpu);
7708         if (ret)
7709                 return ret;
7710
7711         nested_vmx_succeed(vcpu);
7712         return kvm_skip_emulated_instruction(vcpu);
7713 }
7714
7715 /*
7716  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7717  * for running VMX instructions (except VMXON, whose prerequisites are
7718  * slightly different). It also specifies what exception to inject otherwise.
7719  * Note that many of these exceptions have priority over VM exits, so they
7720  * don't have to be checked again here.
7721  */
7722 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7723 {
7724         if (!to_vmx(vcpu)->nested.vmxon) {
7725                 kvm_queue_exception(vcpu, UD_VECTOR);
7726                 return 0;
7727         }
7728         return 1;
7729 }
7730
7731 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7732 {
7733         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7734         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7735 }
7736
7737 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7738 {
7739         if (vmx->nested.current_vmptr == -1ull)
7740                 return;
7741
7742         if (enable_shadow_vmcs) {
7743                 /* copy to memory all shadowed fields in case
7744                    they were modified */
7745                 copy_shadow_to_vmcs12(vmx);
7746                 vmx->nested.sync_shadow_vmcs = false;
7747                 vmx_disable_shadow_vmcs(vmx);
7748         }
7749         vmx->nested.posted_intr_nv = -1;
7750
7751         /* Flush VMCS12 to guest memory */
7752         kvm_vcpu_write_guest_page(&vmx->vcpu,
7753                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7754                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7755
7756         vmx->nested.current_vmptr = -1ull;
7757 }
7758
7759 /*
7760  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7761  * just stops using VMX.
7762  */
7763 static void free_nested(struct vcpu_vmx *vmx)
7764 {
7765         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
7766                 return;
7767
7768         vmx->nested.vmxon = false;
7769         vmx->nested.smm.vmxon = false;
7770         free_vpid(vmx->nested.vpid02);
7771         vmx->nested.posted_intr_nv = -1;
7772         vmx->nested.current_vmptr = -1ull;
7773         if (enable_shadow_vmcs) {
7774                 vmx_disable_shadow_vmcs(vmx);
7775                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7776                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7777                 vmx->vmcs01.shadow_vmcs = NULL;
7778         }
7779         kfree(vmx->nested.cached_vmcs12);
7780         /* Unpin physical memory we referred to in the vmcs02 */
7781         if (vmx->nested.apic_access_page) {
7782                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7783                 vmx->nested.apic_access_page = NULL;
7784         }
7785         if (vmx->nested.virtual_apic_page) {
7786                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7787                 vmx->nested.virtual_apic_page = NULL;
7788         }
7789         if (vmx->nested.pi_desc_page) {
7790                 kunmap(vmx->nested.pi_desc_page);
7791                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7792                 vmx->nested.pi_desc_page = NULL;
7793                 vmx->nested.pi_desc = NULL;
7794         }
7795
7796         free_loaded_vmcs(&vmx->nested.vmcs02);
7797 }
7798
7799 /* Emulate the VMXOFF instruction */
7800 static int handle_vmoff(struct kvm_vcpu *vcpu)
7801 {
7802         if (!nested_vmx_check_permission(vcpu))
7803                 return 1;
7804         free_nested(to_vmx(vcpu));
7805         nested_vmx_succeed(vcpu);
7806         return kvm_skip_emulated_instruction(vcpu);
7807 }
7808
7809 /* Emulate the VMCLEAR instruction */
7810 static int handle_vmclear(struct kvm_vcpu *vcpu)
7811 {
7812         struct vcpu_vmx *vmx = to_vmx(vcpu);
7813         u32 zero = 0;
7814         gpa_t vmptr;
7815
7816         if (!nested_vmx_check_permission(vcpu))
7817                 return 1;
7818
7819         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7820                 return 1;
7821
7822         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7823                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7824                 return kvm_skip_emulated_instruction(vcpu);
7825         }
7826
7827         if (vmptr == vmx->nested.vmxon_ptr) {
7828                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7829                 return kvm_skip_emulated_instruction(vcpu);
7830         }
7831
7832         if (vmptr == vmx->nested.current_vmptr)
7833                 nested_release_vmcs12(vmx);
7834
7835         kvm_vcpu_write_guest(vcpu,
7836                         vmptr + offsetof(struct vmcs12, launch_state),
7837                         &zero, sizeof(zero));
7838
7839         nested_vmx_succeed(vcpu);
7840         return kvm_skip_emulated_instruction(vcpu);
7841 }
7842
7843 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7844
7845 /* Emulate the VMLAUNCH instruction */
7846 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7847 {
7848         return nested_vmx_run(vcpu, true);
7849 }
7850
7851 /* Emulate the VMRESUME instruction */
7852 static int handle_vmresume(struct kvm_vcpu *vcpu)
7853 {
7854
7855         return nested_vmx_run(vcpu, false);
7856 }
7857
7858 /*
7859  * Read a vmcs12 field. Since these can have varying lengths and we return
7860  * one type, we chose the biggest type (u64) and zero-extend the return value
7861  * to that size. Note that the caller, handle_vmread, might need to use only
7862  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7863  * 64-bit fields are to be returned).
7864  */
7865 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7866                                   unsigned long field, u64 *ret)
7867 {
7868         short offset = vmcs_field_to_offset(field);
7869         char *p;
7870
7871         if (offset < 0)
7872                 return offset;
7873
7874         p = ((char *)(get_vmcs12(vcpu))) + offset;
7875
7876         switch (vmcs_field_width(field)) {
7877         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7878                 *ret = *((natural_width *)p);
7879                 return 0;
7880         case VMCS_FIELD_WIDTH_U16:
7881                 *ret = *((u16 *)p);
7882                 return 0;
7883         case VMCS_FIELD_WIDTH_U32:
7884                 *ret = *((u32 *)p);
7885                 return 0;
7886         case VMCS_FIELD_WIDTH_U64:
7887                 *ret = *((u64 *)p);
7888                 return 0;
7889         default:
7890                 WARN_ON(1);
7891                 return -ENOENT;
7892         }
7893 }
7894
7895
7896 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7897                                    unsigned long field, u64 field_value){
7898         short offset = vmcs_field_to_offset(field);
7899         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7900         if (offset < 0)
7901                 return offset;
7902
7903         switch (vmcs_field_width(field)) {
7904         case VMCS_FIELD_WIDTH_U16:
7905                 *(u16 *)p = field_value;
7906                 return 0;
7907         case VMCS_FIELD_WIDTH_U32:
7908                 *(u32 *)p = field_value;
7909                 return 0;
7910         case VMCS_FIELD_WIDTH_U64:
7911                 *(u64 *)p = field_value;
7912                 return 0;
7913         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7914                 *(natural_width *)p = field_value;
7915                 return 0;
7916         default:
7917                 WARN_ON(1);
7918                 return -ENOENT;
7919         }
7920
7921 }
7922
7923 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7924 {
7925         int i;
7926         unsigned long field;
7927         u64 field_value;
7928         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7929         const u16 *fields = shadow_read_write_fields;
7930         const int num_fields = max_shadow_read_write_fields;
7931
7932         preempt_disable();
7933
7934         vmcs_load(shadow_vmcs);
7935
7936         for (i = 0; i < num_fields; i++) {
7937                 field = fields[i];
7938                 field_value = __vmcs_readl(field);
7939                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7940         }
7941
7942         vmcs_clear(shadow_vmcs);
7943         vmcs_load(vmx->loaded_vmcs->vmcs);
7944
7945         preempt_enable();
7946 }
7947
7948 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7949 {
7950         const u16 *fields[] = {
7951                 shadow_read_write_fields,
7952                 shadow_read_only_fields
7953         };
7954         const int max_fields[] = {
7955                 max_shadow_read_write_fields,
7956                 max_shadow_read_only_fields
7957         };
7958         int i, q;
7959         unsigned long field;
7960         u64 field_value = 0;
7961         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7962
7963         vmcs_load(shadow_vmcs);
7964
7965         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7966                 for (i = 0; i < max_fields[q]; i++) {
7967                         field = fields[q][i];
7968                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7969                         __vmcs_writel(field, field_value);
7970                 }
7971         }
7972
7973         vmcs_clear(shadow_vmcs);
7974         vmcs_load(vmx->loaded_vmcs->vmcs);
7975 }
7976
7977 /*
7978  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7979  * used before) all generate the same failure when it is missing.
7980  */
7981 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7982 {
7983         struct vcpu_vmx *vmx = to_vmx(vcpu);
7984         if (vmx->nested.current_vmptr == -1ull) {
7985                 nested_vmx_failInvalid(vcpu);
7986                 return 0;
7987         }
7988         return 1;
7989 }
7990
7991 static int handle_vmread(struct kvm_vcpu *vcpu)
7992 {
7993         unsigned long field;
7994         u64 field_value;
7995         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7996         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7997         gva_t gva = 0;
7998
7999         if (!nested_vmx_check_permission(vcpu))
8000                 return 1;
8001
8002         if (!nested_vmx_check_vmcs12(vcpu))
8003                 return kvm_skip_emulated_instruction(vcpu);
8004
8005         /* Decode instruction info and find the field to read */
8006         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8007         /* Read the field, zero-extended to a u64 field_value */
8008         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8009                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8010                 return kvm_skip_emulated_instruction(vcpu);
8011         }
8012         /*
8013          * Now copy part of this value to register or memory, as requested.
8014          * Note that the number of bits actually copied is 32 or 64 depending
8015          * on the guest's mode (32 or 64 bit), not on the given field's length.
8016          */
8017         if (vmx_instruction_info & (1u << 10)) {
8018                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8019                         field_value);
8020         } else {
8021                 if (get_vmx_mem_address(vcpu, exit_qualification,
8022                                 vmx_instruction_info, true, &gva))
8023                         return 1;
8024                 /* _system ok, as hardware has verified cpl=0 */
8025                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
8026                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
8027         }
8028
8029         nested_vmx_succeed(vcpu);
8030         return kvm_skip_emulated_instruction(vcpu);
8031 }
8032
8033
8034 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8035 {
8036         unsigned long field;
8037         gva_t gva;
8038         struct vcpu_vmx *vmx = to_vmx(vcpu);
8039         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8040         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8041
8042         /* The value to write might be 32 or 64 bits, depending on L1's long
8043          * mode, and eventually we need to write that into a field of several
8044          * possible lengths. The code below first zero-extends the value to 64
8045          * bit (field_value), and then copies only the appropriate number of
8046          * bits into the vmcs12 field.
8047          */
8048         u64 field_value = 0;
8049         struct x86_exception e;
8050
8051         if (!nested_vmx_check_permission(vcpu))
8052                 return 1;
8053
8054         if (!nested_vmx_check_vmcs12(vcpu))
8055                 return kvm_skip_emulated_instruction(vcpu);
8056
8057         if (vmx_instruction_info & (1u << 10))
8058                 field_value = kvm_register_readl(vcpu,
8059                         (((vmx_instruction_info) >> 3) & 0xf));
8060         else {
8061                 if (get_vmx_mem_address(vcpu, exit_qualification,
8062                                 vmx_instruction_info, false, &gva))
8063                         return 1;
8064                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
8065                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8066                         kvm_inject_page_fault(vcpu, &e);
8067                         return 1;
8068                 }
8069         }
8070
8071
8072         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8073         if (vmcs_field_readonly(field)) {
8074                 nested_vmx_failValid(vcpu,
8075                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8076                 return kvm_skip_emulated_instruction(vcpu);
8077         }
8078
8079         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8080                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8081                 return kvm_skip_emulated_instruction(vcpu);
8082         }
8083
8084         switch (field) {
8085 #define SHADOW_FIELD_RW(x) case x:
8086 #include "vmx_shadow_fields.h"
8087                 /*
8088                  * The fields that can be updated by L1 without a vmexit are
8089                  * always updated in the vmcs02, the others go down the slow
8090                  * path of prepare_vmcs02.
8091                  */
8092                 break;
8093         default:
8094                 vmx->nested.dirty_vmcs12 = true;
8095                 break;
8096         }
8097
8098         nested_vmx_succeed(vcpu);
8099         return kvm_skip_emulated_instruction(vcpu);
8100 }
8101
8102 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8103 {
8104         vmx->nested.current_vmptr = vmptr;
8105         if (enable_shadow_vmcs) {
8106                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8107                               SECONDARY_EXEC_SHADOW_VMCS);
8108                 vmcs_write64(VMCS_LINK_POINTER,
8109                              __pa(vmx->vmcs01.shadow_vmcs));
8110                 vmx->nested.sync_shadow_vmcs = true;
8111         }
8112         vmx->nested.dirty_vmcs12 = true;
8113 }
8114
8115 /* Emulate the VMPTRLD instruction */
8116 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8117 {
8118         struct vcpu_vmx *vmx = to_vmx(vcpu);
8119         gpa_t vmptr;
8120
8121         if (!nested_vmx_check_permission(vcpu))
8122                 return 1;
8123
8124         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8125                 return 1;
8126
8127         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8128                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8129                 return kvm_skip_emulated_instruction(vcpu);
8130         }
8131
8132         if (vmptr == vmx->nested.vmxon_ptr) {
8133                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8134                 return kvm_skip_emulated_instruction(vcpu);
8135         }
8136
8137         if (vmx->nested.current_vmptr != vmptr) {
8138                 struct vmcs12 *new_vmcs12;
8139                 struct page *page;
8140                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8141                 if (is_error_page(page)) {
8142                         nested_vmx_failInvalid(vcpu);
8143                         return kvm_skip_emulated_instruction(vcpu);
8144                 }
8145                 new_vmcs12 = kmap(page);
8146                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8147                         kunmap(page);
8148                         kvm_release_page_clean(page);
8149                         nested_vmx_failValid(vcpu,
8150                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8151                         return kvm_skip_emulated_instruction(vcpu);
8152                 }
8153
8154                 nested_release_vmcs12(vmx);
8155                 /*
8156                  * Load VMCS12 from guest memory since it is not already
8157                  * cached.
8158                  */
8159                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8160                 kunmap(page);
8161                 kvm_release_page_clean(page);
8162
8163                 set_current_vmptr(vmx, vmptr);
8164         }
8165
8166         nested_vmx_succeed(vcpu);
8167         return kvm_skip_emulated_instruction(vcpu);
8168 }
8169
8170 /* Emulate the VMPTRST instruction */
8171 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8172 {
8173         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8174         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8175         gva_t vmcs_gva;
8176         struct x86_exception e;
8177
8178         if (!nested_vmx_check_permission(vcpu))
8179                 return 1;
8180
8181         if (get_vmx_mem_address(vcpu, exit_qualification,
8182                         vmx_instruction_info, true, &vmcs_gva))
8183                 return 1;
8184         /* ok to use *_system, as hardware has verified cpl=0 */
8185         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
8186                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
8187                                  sizeof(u64), &e)) {
8188                 kvm_inject_page_fault(vcpu, &e);
8189                 return 1;
8190         }
8191         nested_vmx_succeed(vcpu);
8192         return kvm_skip_emulated_instruction(vcpu);
8193 }
8194
8195 /* Emulate the INVEPT instruction */
8196 static int handle_invept(struct kvm_vcpu *vcpu)
8197 {
8198         struct vcpu_vmx *vmx = to_vmx(vcpu);
8199         u32 vmx_instruction_info, types;
8200         unsigned long type;
8201         gva_t gva;
8202         struct x86_exception e;
8203         struct {
8204                 u64 eptp, gpa;
8205         } operand;
8206
8207         if (!(vmx->nested.msrs.secondary_ctls_high &
8208               SECONDARY_EXEC_ENABLE_EPT) ||
8209             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8210                 kvm_queue_exception(vcpu, UD_VECTOR);
8211                 return 1;
8212         }
8213
8214         if (!nested_vmx_check_permission(vcpu))
8215                 return 1;
8216
8217         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8218         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8219
8220         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8221
8222         if (type >= 32 || !(types & (1 << type))) {
8223                 nested_vmx_failValid(vcpu,
8224                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8225                 return kvm_skip_emulated_instruction(vcpu);
8226         }
8227
8228         /* According to the Intel VMX instruction reference, the memory
8229          * operand is read even if it isn't needed (e.g., for type==global)
8230          */
8231         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8232                         vmx_instruction_info, false, &gva))
8233                 return 1;
8234         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8235                                 sizeof(operand), &e)) {
8236                 kvm_inject_page_fault(vcpu, &e);
8237                 return 1;
8238         }
8239
8240         switch (type) {
8241         case VMX_EPT_EXTENT_GLOBAL:
8242         /*
8243          * TODO: track mappings and invalidate
8244          * single context requests appropriately
8245          */
8246         case VMX_EPT_EXTENT_CONTEXT:
8247                 kvm_mmu_sync_roots(vcpu);
8248                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8249                 nested_vmx_succeed(vcpu);
8250                 break;
8251         default:
8252                 BUG_ON(1);
8253                 break;
8254         }
8255
8256         return kvm_skip_emulated_instruction(vcpu);
8257 }
8258
8259 static int handle_invvpid(struct kvm_vcpu *vcpu)
8260 {
8261         struct vcpu_vmx *vmx = to_vmx(vcpu);
8262         u32 vmx_instruction_info;
8263         unsigned long type, types;
8264         gva_t gva;
8265         struct x86_exception e;
8266         struct {
8267                 u64 vpid;
8268                 u64 gla;
8269         } operand;
8270
8271         if (!(vmx->nested.msrs.secondary_ctls_high &
8272               SECONDARY_EXEC_ENABLE_VPID) ||
8273                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8274                 kvm_queue_exception(vcpu, UD_VECTOR);
8275                 return 1;
8276         }
8277
8278         if (!nested_vmx_check_permission(vcpu))
8279                 return 1;
8280
8281         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8282         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8283
8284         types = (vmx->nested.msrs.vpid_caps &
8285                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8286
8287         if (type >= 32 || !(types & (1 << type))) {
8288                 nested_vmx_failValid(vcpu,
8289                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8290                 return kvm_skip_emulated_instruction(vcpu);
8291         }
8292
8293         /* according to the intel vmx instruction reference, the memory
8294          * operand is read even if it isn't needed (e.g., for type==global)
8295          */
8296         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8297                         vmx_instruction_info, false, &gva))
8298                 return 1;
8299         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8300                                 sizeof(operand), &e)) {
8301                 kvm_inject_page_fault(vcpu, &e);
8302                 return 1;
8303         }
8304         if (operand.vpid >> 16) {
8305                 nested_vmx_failValid(vcpu,
8306                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8307                 return kvm_skip_emulated_instruction(vcpu);
8308         }
8309
8310         switch (type) {
8311         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8312                 if (is_noncanonical_address(operand.gla, vcpu)) {
8313                         nested_vmx_failValid(vcpu,
8314                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8315                         return kvm_skip_emulated_instruction(vcpu);
8316                 }
8317                 /* fall through */
8318         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8319         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8320                 if (!operand.vpid) {
8321                         nested_vmx_failValid(vcpu,
8322                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8323                         return kvm_skip_emulated_instruction(vcpu);
8324                 }
8325                 break;
8326         case VMX_VPID_EXTENT_ALL_CONTEXT:
8327                 break;
8328         default:
8329                 WARN_ON_ONCE(1);
8330                 return kvm_skip_emulated_instruction(vcpu);
8331         }
8332
8333         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8334         nested_vmx_succeed(vcpu);
8335
8336         return kvm_skip_emulated_instruction(vcpu);
8337 }
8338
8339 static int handle_pml_full(struct kvm_vcpu *vcpu)
8340 {
8341         unsigned long exit_qualification;
8342
8343         trace_kvm_pml_full(vcpu->vcpu_id);
8344
8345         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8346
8347         /*
8348          * PML buffer FULL happened while executing iret from NMI,
8349          * "blocked by NMI" bit has to be set before next VM entry.
8350          */
8351         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8352                         enable_vnmi &&
8353                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8354                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8355                                 GUEST_INTR_STATE_NMI);
8356
8357         /*
8358          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8359          * here.., and there's no userspace involvement needed for PML.
8360          */
8361         return 1;
8362 }
8363
8364 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8365 {
8366         kvm_lapic_expired_hv_timer(vcpu);
8367         return 1;
8368 }
8369
8370 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8371 {
8372         struct vcpu_vmx *vmx = to_vmx(vcpu);
8373         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8374
8375         /* Check for memory type validity */
8376         switch (address & VMX_EPTP_MT_MASK) {
8377         case VMX_EPTP_MT_UC:
8378                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
8379                         return false;
8380                 break;
8381         case VMX_EPTP_MT_WB:
8382                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
8383                         return false;
8384                 break;
8385         default:
8386                 return false;
8387         }
8388
8389         /* only 4 levels page-walk length are valid */
8390         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8391                 return false;
8392
8393         /* Reserved bits should not be set */
8394         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8395                 return false;
8396
8397         /* AD, if set, should be supported */
8398         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8399                 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
8400                         return false;
8401         }
8402
8403         return true;
8404 }
8405
8406 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8407                                      struct vmcs12 *vmcs12)
8408 {
8409         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8410         u64 address;
8411         bool accessed_dirty;
8412         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8413
8414         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8415             !nested_cpu_has_ept(vmcs12))
8416                 return 1;
8417
8418         if (index >= VMFUNC_EPTP_ENTRIES)
8419                 return 1;
8420
8421
8422         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8423                                      &address, index * 8, 8))
8424                 return 1;
8425
8426         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8427
8428         /*
8429          * If the (L2) guest does a vmfunc to the currently
8430          * active ept pointer, we don't have to do anything else
8431          */
8432         if (vmcs12->ept_pointer != address) {
8433                 if (!valid_ept_address(vcpu, address))
8434                         return 1;
8435
8436                 kvm_mmu_unload(vcpu);
8437                 mmu->ept_ad = accessed_dirty;
8438                 mmu->base_role.ad_disabled = !accessed_dirty;
8439                 vmcs12->ept_pointer = address;
8440                 /*
8441                  * TODO: Check what's the correct approach in case
8442                  * mmu reload fails. Currently, we just let the next
8443                  * reload potentially fail
8444                  */
8445                 kvm_mmu_reload(vcpu);
8446         }
8447
8448         return 0;
8449 }
8450
8451 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8452 {
8453         struct vcpu_vmx *vmx = to_vmx(vcpu);
8454         struct vmcs12 *vmcs12;
8455         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8456
8457         /*
8458          * VMFUNC is only supported for nested guests, but we always enable the
8459          * secondary control for simplicity; for non-nested mode, fake that we
8460          * didn't by injecting #UD.
8461          */
8462         if (!is_guest_mode(vcpu)) {
8463                 kvm_queue_exception(vcpu, UD_VECTOR);
8464                 return 1;
8465         }
8466
8467         vmcs12 = get_vmcs12(vcpu);
8468         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8469                 goto fail;
8470
8471         switch (function) {
8472         case 0:
8473                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8474                         goto fail;
8475                 break;
8476         default:
8477                 goto fail;
8478         }
8479         return kvm_skip_emulated_instruction(vcpu);
8480
8481 fail:
8482         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8483                           vmcs_read32(VM_EXIT_INTR_INFO),
8484                           vmcs_readl(EXIT_QUALIFICATION));
8485         return 1;
8486 }
8487
8488 /*
8489  * The exit handlers return 1 if the exit was handled fully and guest execution
8490  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8491  * to be done to userspace and return 0.
8492  */
8493 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8494         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8495         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8496         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8497         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8498         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8499         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8500         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8501         [EXIT_REASON_CPUID]                   = handle_cpuid,
8502         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8503         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8504         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8505         [EXIT_REASON_HLT]                     = handle_halt,
8506         [EXIT_REASON_INVD]                    = handle_invd,
8507         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8508         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8509         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8510         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8511         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8512         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8513         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8514         [EXIT_REASON_VMREAD]                  = handle_vmread,
8515         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8516         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8517         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8518         [EXIT_REASON_VMON]                    = handle_vmon,
8519         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8520         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8521         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8522         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8523         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8524         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8525         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8526         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8527         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
8528         [EXIT_REASON_LDTR_TR]                 = handle_desc,
8529         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8530         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8531         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8532         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8533         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8534         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8535         [EXIT_REASON_INVEPT]                  = handle_invept,
8536         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8537         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8538         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8539         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8540         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8541         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8542         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8543         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8544 };
8545
8546 static const int kvm_vmx_max_exit_handlers =
8547         ARRAY_SIZE(kvm_vmx_exit_handlers);
8548
8549 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8550                                        struct vmcs12 *vmcs12)
8551 {
8552         unsigned long exit_qualification;
8553         gpa_t bitmap, last_bitmap;
8554         unsigned int port;
8555         int size;
8556         u8 b;
8557
8558         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8559                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8560
8561         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8562
8563         port = exit_qualification >> 16;
8564         size = (exit_qualification & 7) + 1;
8565
8566         last_bitmap = (gpa_t)-1;
8567         b = -1;
8568
8569         while (size > 0) {
8570                 if (port < 0x8000)
8571                         bitmap = vmcs12->io_bitmap_a;
8572                 else if (port < 0x10000)
8573                         bitmap = vmcs12->io_bitmap_b;
8574                 else
8575                         return true;
8576                 bitmap += (port & 0x7fff) / 8;
8577
8578                 if (last_bitmap != bitmap)
8579                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8580                                 return true;
8581                 if (b & (1 << (port & 7)))
8582                         return true;
8583
8584                 port++;
8585                 size--;
8586                 last_bitmap = bitmap;
8587         }
8588
8589         return false;
8590 }
8591
8592 /*
8593  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8594  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8595  * disinterest in the current event (read or write a specific MSR) by using an
8596  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8597  */
8598 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8599         struct vmcs12 *vmcs12, u32 exit_reason)
8600 {
8601         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8602         gpa_t bitmap;
8603
8604         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8605                 return true;
8606
8607         /*
8608          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8609          * for the four combinations of read/write and low/high MSR numbers.
8610          * First we need to figure out which of the four to use:
8611          */
8612         bitmap = vmcs12->msr_bitmap;
8613         if (exit_reason == EXIT_REASON_MSR_WRITE)
8614                 bitmap += 2048;
8615         if (msr_index >= 0xc0000000) {
8616                 msr_index -= 0xc0000000;
8617                 bitmap += 1024;
8618         }
8619
8620         /* Then read the msr_index'th bit from this bitmap: */
8621         if (msr_index < 1024*8) {
8622                 unsigned char b;
8623                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8624                         return true;
8625                 return 1 & (b >> (msr_index & 7));
8626         } else
8627                 return true; /* let L1 handle the wrong parameter */
8628 }
8629
8630 /*
8631  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8632  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8633  * intercept (via guest_host_mask etc.) the current event.
8634  */
8635 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8636         struct vmcs12 *vmcs12)
8637 {
8638         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8639         int cr = exit_qualification & 15;
8640         int reg;
8641         unsigned long val;
8642
8643         switch ((exit_qualification >> 4) & 3) {
8644         case 0: /* mov to cr */
8645                 reg = (exit_qualification >> 8) & 15;
8646                 val = kvm_register_readl(vcpu, reg);
8647                 switch (cr) {
8648                 case 0:
8649                         if (vmcs12->cr0_guest_host_mask &
8650                             (val ^ vmcs12->cr0_read_shadow))
8651                                 return true;
8652                         break;
8653                 case 3:
8654                         if ((vmcs12->cr3_target_count >= 1 &&
8655                                         vmcs12->cr3_target_value0 == val) ||
8656                                 (vmcs12->cr3_target_count >= 2 &&
8657                                         vmcs12->cr3_target_value1 == val) ||
8658                                 (vmcs12->cr3_target_count >= 3 &&
8659                                         vmcs12->cr3_target_value2 == val) ||
8660                                 (vmcs12->cr3_target_count >= 4 &&
8661                                         vmcs12->cr3_target_value3 == val))
8662                                 return false;
8663                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8664                                 return true;
8665                         break;
8666                 case 4:
8667                         if (vmcs12->cr4_guest_host_mask &
8668                             (vmcs12->cr4_read_shadow ^ val))
8669                                 return true;
8670                         break;
8671                 case 8:
8672                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8673                                 return true;
8674                         break;
8675                 }
8676                 break;
8677         case 2: /* clts */
8678                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8679                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8680                         return true;
8681                 break;
8682         case 1: /* mov from cr */
8683                 switch (cr) {
8684                 case 3:
8685                         if (vmcs12->cpu_based_vm_exec_control &
8686                             CPU_BASED_CR3_STORE_EXITING)
8687                                 return true;
8688                         break;
8689                 case 8:
8690                         if (vmcs12->cpu_based_vm_exec_control &
8691                             CPU_BASED_CR8_STORE_EXITING)
8692                                 return true;
8693                         break;
8694                 }
8695                 break;
8696         case 3: /* lmsw */
8697                 /*
8698                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8699                  * cr0. Other attempted changes are ignored, with no exit.
8700                  */
8701                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8702                 if (vmcs12->cr0_guest_host_mask & 0xe &
8703                     (val ^ vmcs12->cr0_read_shadow))
8704                         return true;
8705                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8706                     !(vmcs12->cr0_read_shadow & 0x1) &&
8707                     (val & 0x1))
8708                         return true;
8709                 break;
8710         }
8711         return false;
8712 }
8713
8714 /*
8715  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8716  * should handle it ourselves in L0 (and then continue L2). Only call this
8717  * when in is_guest_mode (L2).
8718  */
8719 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8720 {
8721         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8722         struct vcpu_vmx *vmx = to_vmx(vcpu);
8723         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8724
8725         if (vmx->nested.nested_run_pending)
8726                 return false;
8727
8728         if (unlikely(vmx->fail)) {
8729                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8730                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8731                 return true;
8732         }
8733
8734         /*
8735          * The host physical addresses of some pages of guest memory
8736          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8737          * Page). The CPU may write to these pages via their host
8738          * physical address while L2 is running, bypassing any
8739          * address-translation-based dirty tracking (e.g. EPT write
8740          * protection).
8741          *
8742          * Mark them dirty on every exit from L2 to prevent them from
8743          * getting out of sync with dirty tracking.
8744          */
8745         nested_mark_vmcs12_pages_dirty(vcpu);
8746
8747         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8748                                 vmcs_readl(EXIT_QUALIFICATION),
8749                                 vmx->idt_vectoring_info,
8750                                 intr_info,
8751                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8752                                 KVM_ISA_VMX);
8753
8754         switch (exit_reason) {
8755         case EXIT_REASON_EXCEPTION_NMI:
8756                 if (is_nmi(intr_info))
8757                         return false;
8758                 else if (is_page_fault(intr_info))
8759                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8760                 else if (is_no_device(intr_info) &&
8761                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8762                         return false;
8763                 else if (is_debug(intr_info) &&
8764                          vcpu->guest_debug &
8765                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8766                         return false;
8767                 else if (is_breakpoint(intr_info) &&
8768                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8769                         return false;
8770                 return vmcs12->exception_bitmap &
8771                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8772         case EXIT_REASON_EXTERNAL_INTERRUPT:
8773                 return false;
8774         case EXIT_REASON_TRIPLE_FAULT:
8775                 return true;
8776         case EXIT_REASON_PENDING_INTERRUPT:
8777                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8778         case EXIT_REASON_NMI_WINDOW:
8779                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8780         case EXIT_REASON_TASK_SWITCH:
8781                 return true;
8782         case EXIT_REASON_CPUID:
8783                 return true;
8784         case EXIT_REASON_HLT:
8785                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8786         case EXIT_REASON_INVD:
8787                 return true;
8788         case EXIT_REASON_INVLPG:
8789                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8790         case EXIT_REASON_RDPMC:
8791                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8792         case EXIT_REASON_RDRAND:
8793                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
8794         case EXIT_REASON_RDSEED:
8795                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
8796         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8797                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8798         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8799         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8800         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8801         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8802         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8803         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8804                 /*
8805                  * VMX instructions trap unconditionally. This allows L1 to
8806                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8807                  */
8808                 return true;
8809         case EXIT_REASON_CR_ACCESS:
8810                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8811         case EXIT_REASON_DR_ACCESS:
8812                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8813         case EXIT_REASON_IO_INSTRUCTION:
8814                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8815         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8816                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8817         case EXIT_REASON_MSR_READ:
8818         case EXIT_REASON_MSR_WRITE:
8819                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8820         case EXIT_REASON_INVALID_STATE:
8821                 return true;
8822         case EXIT_REASON_MWAIT_INSTRUCTION:
8823                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8824         case EXIT_REASON_MONITOR_TRAP_FLAG:
8825                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8826         case EXIT_REASON_MONITOR_INSTRUCTION:
8827                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8828         case EXIT_REASON_PAUSE_INSTRUCTION:
8829                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8830                         nested_cpu_has2(vmcs12,
8831                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8832         case EXIT_REASON_MCE_DURING_VMENTRY:
8833                 return false;
8834         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8835                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8836         case EXIT_REASON_APIC_ACCESS:
8837                 return nested_cpu_has2(vmcs12,
8838                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8839         case EXIT_REASON_APIC_WRITE:
8840         case EXIT_REASON_EOI_INDUCED:
8841                 /* apic_write and eoi_induced should exit unconditionally. */
8842                 return true;
8843         case EXIT_REASON_EPT_VIOLATION:
8844                 /*
8845                  * L0 always deals with the EPT violation. If nested EPT is
8846                  * used, and the nested mmu code discovers that the address is
8847                  * missing in the guest EPT table (EPT12), the EPT violation
8848                  * will be injected with nested_ept_inject_page_fault()
8849                  */
8850                 return false;
8851         case EXIT_REASON_EPT_MISCONFIG:
8852                 /*
8853                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8854                  * table (shadow on EPT) or a merged EPT table that L0 built
8855                  * (EPT on EPT). So any problems with the structure of the
8856                  * table is L0's fault.
8857                  */
8858                 return false;
8859         case EXIT_REASON_INVPCID:
8860                 return
8861                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8862                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8863         case EXIT_REASON_WBINVD:
8864                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8865         case EXIT_REASON_XSETBV:
8866                 return true;
8867         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8868                 /*
8869                  * This should never happen, since it is not possible to
8870                  * set XSS to a non-zero value---neither in L1 nor in L2.
8871                  * If if it were, XSS would have to be checked against
8872                  * the XSS exit bitmap in vmcs12.
8873                  */
8874                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8875         case EXIT_REASON_PREEMPTION_TIMER:
8876                 return false;
8877         case EXIT_REASON_PML_FULL:
8878                 /* We emulate PML support to L1. */
8879                 return false;
8880         case EXIT_REASON_VMFUNC:
8881                 /* VM functions are emulated through L2->L0 vmexits. */
8882                 return false;
8883         default:
8884                 return true;
8885         }
8886 }
8887
8888 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8889 {
8890         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8891
8892         /*
8893          * At this point, the exit interruption info in exit_intr_info
8894          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8895          * we need to query the in-kernel LAPIC.
8896          */
8897         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8898         if ((exit_intr_info &
8899              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8900             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8901                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8902                 vmcs12->vm_exit_intr_error_code =
8903                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8904         }
8905
8906         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8907                           vmcs_readl(EXIT_QUALIFICATION));
8908         return 1;
8909 }
8910
8911 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8912 {
8913         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8914         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8915 }
8916
8917 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8918 {
8919         if (vmx->pml_pg) {
8920                 __free_page(vmx->pml_pg);
8921                 vmx->pml_pg = NULL;
8922         }
8923 }
8924
8925 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8926 {
8927         struct vcpu_vmx *vmx = to_vmx(vcpu);
8928         u64 *pml_buf;
8929         u16 pml_idx;
8930
8931         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8932
8933         /* Do nothing if PML buffer is empty */
8934         if (pml_idx == (PML_ENTITY_NUM - 1))
8935                 return;
8936
8937         /* PML index always points to next available PML buffer entity */
8938         if (pml_idx >= PML_ENTITY_NUM)
8939                 pml_idx = 0;
8940         else
8941                 pml_idx++;
8942
8943         pml_buf = page_address(vmx->pml_pg);
8944         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8945                 u64 gpa;
8946
8947                 gpa = pml_buf[pml_idx];
8948                 WARN_ON(gpa & (PAGE_SIZE - 1));
8949                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8950         }
8951
8952         /* reset PML index */
8953         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8954 }
8955
8956 /*
8957  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8958  * Called before reporting dirty_bitmap to userspace.
8959  */
8960 static void kvm_flush_pml_buffers(struct kvm *kvm)
8961 {
8962         int i;
8963         struct kvm_vcpu *vcpu;
8964         /*
8965          * We only need to kick vcpu out of guest mode here, as PML buffer
8966          * is flushed at beginning of all VMEXITs, and it's obvious that only
8967          * vcpus running in guest are possible to have unflushed GPAs in PML
8968          * buffer.
8969          */
8970         kvm_for_each_vcpu(i, vcpu, kvm)
8971                 kvm_vcpu_kick(vcpu);
8972 }
8973
8974 static void vmx_dump_sel(char *name, uint32_t sel)
8975 {
8976         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8977                name, vmcs_read16(sel),
8978                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8979                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8980                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8981 }
8982
8983 static void vmx_dump_dtsel(char *name, uint32_t limit)
8984 {
8985         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8986                name, vmcs_read32(limit),
8987                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8988 }
8989
8990 static void dump_vmcs(void)
8991 {
8992         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8993         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8994         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8995         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8996         u32 secondary_exec_control = 0;
8997         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8998         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8999         int i, n;
9000
9001         if (cpu_has_secondary_exec_ctrls())
9002                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9003
9004         pr_err("*** Guest State ***\n");
9005         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9006                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9007                vmcs_readl(CR0_GUEST_HOST_MASK));
9008         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9009                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9010         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9011         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9012             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9013         {
9014                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
9015                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9016                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
9017                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9018         }
9019         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
9020                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9021         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
9022                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9023         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9024                vmcs_readl(GUEST_SYSENTER_ESP),
9025                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9026         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
9027         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
9028         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
9029         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
9030         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
9031         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
9032         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9033         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9034         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9035         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
9036         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9037             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9038                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
9039                        efer, vmcs_read64(GUEST_IA32_PAT));
9040         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
9041                vmcs_read64(GUEST_IA32_DEBUGCTL),
9042                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9043         if (cpu_has_load_perf_global_ctrl &&
9044             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9045                 pr_err("PerfGlobCtl = 0x%016llx\n",
9046                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9047         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9048                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9049         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
9050                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9051                vmcs_read32(GUEST_ACTIVITY_STATE));
9052         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9053                 pr_err("InterruptStatus = %04x\n",
9054                        vmcs_read16(GUEST_INTR_STATUS));
9055
9056         pr_err("*** Host State ***\n");
9057         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
9058                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9059         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9060                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9061                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9062                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9063                vmcs_read16(HOST_TR_SELECTOR));
9064         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9065                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9066                vmcs_readl(HOST_TR_BASE));
9067         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9068                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9069         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9070                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9071                vmcs_readl(HOST_CR4));
9072         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9073                vmcs_readl(HOST_IA32_SYSENTER_ESP),
9074                vmcs_read32(HOST_IA32_SYSENTER_CS),
9075                vmcs_readl(HOST_IA32_SYSENTER_EIP));
9076         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9077                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
9078                        vmcs_read64(HOST_IA32_EFER),
9079                        vmcs_read64(HOST_IA32_PAT));
9080         if (cpu_has_load_perf_global_ctrl &&
9081             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9082                 pr_err("PerfGlobCtl = 0x%016llx\n",
9083                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9084
9085         pr_err("*** Control State ***\n");
9086         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9087                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9088         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9089         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9090                vmcs_read32(EXCEPTION_BITMAP),
9091                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9092                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9093         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9094                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9095                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9096                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9097         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9098                vmcs_read32(VM_EXIT_INTR_INFO),
9099                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9100                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9101         pr_err("        reason=%08x qualification=%016lx\n",
9102                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9103         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9104                vmcs_read32(IDT_VECTORING_INFO_FIELD),
9105                vmcs_read32(IDT_VECTORING_ERROR_CODE));
9106         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9107         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9108                 pr_err("TSC Multiplier = 0x%016llx\n",
9109                        vmcs_read64(TSC_MULTIPLIER));
9110         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9111                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9112         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9113                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9114         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9115                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9116         n = vmcs_read32(CR3_TARGET_COUNT);
9117         for (i = 0; i + 1 < n; i += 4)
9118                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9119                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9120                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9121         if (i < n)
9122                 pr_err("CR3 target%u=%016lx\n",
9123                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9124         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9125                 pr_err("PLE Gap=%08x Window=%08x\n",
9126                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9127         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9128                 pr_err("Virtual processor ID = 0x%04x\n",
9129                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
9130 }
9131
9132 /*
9133  * The guest has exited.  See if we can fix it or if we need userspace
9134  * assistance.
9135  */
9136 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9137 {
9138         struct vcpu_vmx *vmx = to_vmx(vcpu);
9139         u32 exit_reason = vmx->exit_reason;
9140         u32 vectoring_info = vmx->idt_vectoring_info;
9141
9142         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9143
9144         /*
9145          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9146          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9147          * querying dirty_bitmap, we only need to kick all vcpus out of guest
9148          * mode as if vcpus is in root mode, the PML buffer must has been
9149          * flushed already.
9150          */
9151         if (enable_pml)
9152                 vmx_flush_pml_buffer(vcpu);
9153
9154         /* If guest state is invalid, start emulating */
9155         if (vmx->emulation_required)
9156                 return handle_invalid_guest_state(vcpu);
9157
9158         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9159                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9160
9161         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9162                 dump_vmcs();
9163                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9164                 vcpu->run->fail_entry.hardware_entry_failure_reason
9165                         = exit_reason;
9166                 return 0;
9167         }
9168
9169         if (unlikely(vmx->fail)) {
9170                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9171                 vcpu->run->fail_entry.hardware_entry_failure_reason
9172                         = vmcs_read32(VM_INSTRUCTION_ERROR);
9173                 return 0;
9174         }
9175
9176         /*
9177          * Note:
9178          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9179          * delivery event since it indicates guest is accessing MMIO.
9180          * The vm-exit can be triggered again after return to guest that
9181          * will cause infinite loop.
9182          */
9183         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9184                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9185                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
9186                         exit_reason != EXIT_REASON_PML_FULL &&
9187                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
9188                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9189                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9190                 vcpu->run->internal.ndata = 3;
9191                 vcpu->run->internal.data[0] = vectoring_info;
9192                 vcpu->run->internal.data[1] = exit_reason;
9193                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9194                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9195                         vcpu->run->internal.ndata++;
9196                         vcpu->run->internal.data[3] =
9197                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9198                 }
9199                 return 0;
9200         }
9201
9202         if (unlikely(!enable_vnmi &&
9203                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
9204                 if (vmx_interrupt_allowed(vcpu)) {
9205                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9206                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9207                            vcpu->arch.nmi_pending) {
9208                         /*
9209                          * This CPU don't support us in finding the end of an
9210                          * NMI-blocked window if the guest runs with IRQs
9211                          * disabled. So we pull the trigger after 1 s of
9212                          * futile waiting, but inform the user about this.
9213                          */
9214                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9215                                "state on VCPU %d after 1 s timeout\n",
9216                                __func__, vcpu->vcpu_id);
9217                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9218                 }
9219         }
9220
9221         if (exit_reason < kvm_vmx_max_exit_handlers
9222             && kvm_vmx_exit_handlers[exit_reason])
9223                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9224         else {
9225                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9226                                 exit_reason);
9227                 kvm_queue_exception(vcpu, UD_VECTOR);
9228                 return 1;
9229         }
9230 }
9231
9232 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9233 {
9234         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9235
9236         if (is_guest_mode(vcpu) &&
9237                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9238                 return;
9239
9240         if (irr == -1 || tpr < irr) {
9241                 vmcs_write32(TPR_THRESHOLD, 0);
9242                 return;
9243         }
9244
9245         vmcs_write32(TPR_THRESHOLD, irr);
9246 }
9247
9248 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
9249 {
9250         u32 sec_exec_control;
9251
9252         /* Postpone execution until vmcs01 is the current VMCS. */
9253         if (is_guest_mode(vcpu)) {
9254                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
9255                 return;
9256         }
9257
9258         if (!cpu_has_vmx_virtualize_x2apic_mode())
9259                 return;
9260
9261         if (!cpu_need_tpr_shadow(vcpu))
9262                 return;
9263
9264         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9265
9266         if (set) {
9267                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9268                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9269         } else {
9270                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9271                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9272                 vmx_flush_tlb(vcpu, true);
9273         }
9274         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9275
9276         vmx_update_msr_bitmap(vcpu);
9277 }
9278
9279 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9280 {
9281         struct vcpu_vmx *vmx = to_vmx(vcpu);
9282
9283         /*
9284          * Currently we do not handle the nested case where L2 has an
9285          * APIC access page of its own; that page is still pinned.
9286          * Hence, we skip the case where the VCPU is in guest mode _and_
9287          * L1 prepared an APIC access page for L2.
9288          *
9289          * For the case where L1 and L2 share the same APIC access page
9290          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9291          * in the vmcs12), this function will only update either the vmcs01
9292          * or the vmcs02.  If the former, the vmcs02 will be updated by
9293          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
9294          * the next L2->L1 exit.
9295          */
9296         if (!is_guest_mode(vcpu) ||
9297             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9298                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9299                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9300                 vmx_flush_tlb(vcpu, true);
9301         }
9302 }
9303
9304 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9305 {
9306         u16 status;
9307         u8 old;
9308
9309         if (max_isr == -1)
9310                 max_isr = 0;
9311
9312         status = vmcs_read16(GUEST_INTR_STATUS);
9313         old = status >> 8;
9314         if (max_isr != old) {
9315                 status &= 0xff;
9316                 status |= max_isr << 8;
9317                 vmcs_write16(GUEST_INTR_STATUS, status);
9318         }
9319 }
9320
9321 static void vmx_set_rvi(int vector)
9322 {
9323         u16 status;
9324         u8 old;
9325
9326         if (vector == -1)
9327                 vector = 0;
9328
9329         status = vmcs_read16(GUEST_INTR_STATUS);
9330         old = (u8)status & 0xff;
9331         if ((u8)vector != old) {
9332                 status &= ~0xff;
9333                 status |= (u8)vector;
9334                 vmcs_write16(GUEST_INTR_STATUS, status);
9335         }
9336 }
9337
9338 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9339 {
9340         /*
9341          * When running L2, updating RVI is only relevant when
9342          * vmcs12 virtual-interrupt-delivery enabled.
9343          * However, it can be enabled only when L1 also
9344          * intercepts external-interrupts and in that case
9345          * we should not update vmcs02 RVI but instead intercept
9346          * interrupt. Therefore, do nothing when running L2.
9347          */
9348         if (!is_guest_mode(vcpu))
9349                 vmx_set_rvi(max_irr);
9350 }
9351
9352 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9353 {
9354         struct vcpu_vmx *vmx = to_vmx(vcpu);
9355         int max_irr;
9356         bool max_irr_updated;
9357
9358         WARN_ON(!vcpu->arch.apicv_active);
9359         if (pi_test_on(&vmx->pi_desc)) {
9360                 pi_clear_on(&vmx->pi_desc);
9361                 /*
9362                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9363                  * But on x86 this is just a compiler barrier anyway.
9364                  */
9365                 smp_mb__after_atomic();
9366                 max_irr_updated =
9367                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9368
9369                 /*
9370                  * If we are running L2 and L1 has a new pending interrupt
9371                  * which can be injected, we should re-evaluate
9372                  * what should be done with this new L1 interrupt.
9373                  * If L1 intercepts external-interrupts, we should
9374                  * exit from L2 to L1. Otherwise, interrupt should be
9375                  * delivered directly to L2.
9376                  */
9377                 if (is_guest_mode(vcpu) && max_irr_updated) {
9378                         if (nested_exit_on_intr(vcpu))
9379                                 kvm_vcpu_exiting_guest_mode(vcpu);
9380                         else
9381                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9382                 }
9383         } else {
9384                 max_irr = kvm_lapic_find_highest_irr(vcpu);
9385         }
9386         vmx_hwapic_irr_update(vcpu, max_irr);
9387         return max_irr;
9388 }
9389
9390 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9391 {
9392         if (!kvm_vcpu_apicv_active(vcpu))
9393                 return;
9394
9395         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9396         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9397         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9398         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9399 }
9400
9401 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9402 {
9403         struct vcpu_vmx *vmx = to_vmx(vcpu);
9404
9405         pi_clear_on(&vmx->pi_desc);
9406         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9407 }
9408
9409 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9410 {
9411         u32 exit_intr_info = 0;
9412         u16 basic_exit_reason = (u16)vmx->exit_reason;
9413
9414         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9415               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9416                 return;
9417
9418         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9419                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9420         vmx->exit_intr_info = exit_intr_info;
9421
9422         /* if exit due to PF check for async PF */
9423         if (is_page_fault(exit_intr_info))
9424                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9425
9426         /* Handle machine checks before interrupts are enabled */
9427         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9428             is_machine_check(exit_intr_info))
9429                 kvm_machine_check();
9430
9431         /* We need to handle NMIs before interrupts are enabled */
9432         if (is_nmi(exit_intr_info)) {
9433                 kvm_before_interrupt(&vmx->vcpu);
9434                 asm("int $2");
9435                 kvm_after_interrupt(&vmx->vcpu);
9436         }
9437 }
9438
9439 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9440 {
9441         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9442
9443         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9444                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9445                 unsigned int vector;
9446                 unsigned long entry;
9447                 gate_desc *desc;
9448                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9449 #ifdef CONFIG_X86_64
9450                 unsigned long tmp;
9451 #endif
9452
9453                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9454                 desc = (gate_desc *)vmx->host_idt_base + vector;
9455                 entry = gate_offset(desc);
9456                 asm volatile(
9457 #ifdef CONFIG_X86_64
9458                         "mov %%" _ASM_SP ", %[sp]\n\t"
9459                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9460                         "push $%c[ss]\n\t"
9461                         "push %[sp]\n\t"
9462 #endif
9463                         "pushf\n\t"
9464                         __ASM_SIZE(push) " $%c[cs]\n\t"
9465                         CALL_NOSPEC
9466                         :
9467 #ifdef CONFIG_X86_64
9468                         [sp]"=&r"(tmp),
9469 #endif
9470                         ASM_CALL_CONSTRAINT
9471                         :
9472                         THUNK_TARGET(entry),
9473                         [ss]"i"(__KERNEL_DS),
9474                         [cs]"i"(__KERNEL_CS)
9475                         );
9476         }
9477 }
9478 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9479
9480 static bool vmx_has_high_real_mode_segbase(void)
9481 {
9482         return enable_unrestricted_guest || emulate_invalid_guest_state;
9483 }
9484
9485 static bool vmx_mpx_supported(void)
9486 {
9487         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9488                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9489 }
9490
9491 static bool vmx_xsaves_supported(void)
9492 {
9493         return vmcs_config.cpu_based_2nd_exec_ctrl &
9494                 SECONDARY_EXEC_XSAVES;
9495 }
9496
9497 static bool vmx_umip_emulated(void)
9498 {
9499         return vmcs_config.cpu_based_2nd_exec_ctrl &
9500                 SECONDARY_EXEC_DESC;
9501 }
9502
9503 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9504 {
9505         u32 exit_intr_info;
9506         bool unblock_nmi;
9507         u8 vector;
9508         bool idtv_info_valid;
9509
9510         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9511
9512         if (enable_vnmi) {
9513                 if (vmx->loaded_vmcs->nmi_known_unmasked)
9514                         return;
9515                 /*
9516                  * Can't use vmx->exit_intr_info since we're not sure what
9517                  * the exit reason is.
9518                  */
9519                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9520                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9521                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9522                 /*
9523                  * SDM 3: 27.7.1.2 (September 2008)
9524                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
9525                  * a guest IRET fault.
9526                  * SDM 3: 23.2.2 (September 2008)
9527                  * Bit 12 is undefined in any of the following cases:
9528                  *  If the VM exit sets the valid bit in the IDT-vectoring
9529                  *   information field.
9530                  *  If the VM exit is due to a double fault.
9531                  */
9532                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9533                     vector != DF_VECTOR && !idtv_info_valid)
9534                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9535                                       GUEST_INTR_STATE_NMI);
9536                 else
9537                         vmx->loaded_vmcs->nmi_known_unmasked =
9538                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9539                                   & GUEST_INTR_STATE_NMI);
9540         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9541                 vmx->loaded_vmcs->vnmi_blocked_time +=
9542                         ktime_to_ns(ktime_sub(ktime_get(),
9543                                               vmx->loaded_vmcs->entry_time));
9544 }
9545
9546 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9547                                       u32 idt_vectoring_info,
9548                                       int instr_len_field,
9549                                       int error_code_field)
9550 {
9551         u8 vector;
9552         int type;
9553         bool idtv_info_valid;
9554
9555         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9556
9557         vcpu->arch.nmi_injected = false;
9558         kvm_clear_exception_queue(vcpu);
9559         kvm_clear_interrupt_queue(vcpu);
9560
9561         if (!idtv_info_valid)
9562                 return;
9563
9564         kvm_make_request(KVM_REQ_EVENT, vcpu);
9565
9566         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9567         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9568
9569         switch (type) {
9570         case INTR_TYPE_NMI_INTR:
9571                 vcpu->arch.nmi_injected = true;
9572                 /*
9573                  * SDM 3: 27.7.1.2 (September 2008)
9574                  * Clear bit "block by NMI" before VM entry if a NMI
9575                  * delivery faulted.
9576                  */
9577                 vmx_set_nmi_mask(vcpu, false);
9578                 break;
9579         case INTR_TYPE_SOFT_EXCEPTION:
9580                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9581                 /* fall through */
9582         case INTR_TYPE_HARD_EXCEPTION:
9583                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9584                         u32 err = vmcs_read32(error_code_field);
9585                         kvm_requeue_exception_e(vcpu, vector, err);
9586                 } else
9587                         kvm_requeue_exception(vcpu, vector);
9588                 break;
9589         case INTR_TYPE_SOFT_INTR:
9590                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9591                 /* fall through */
9592         case INTR_TYPE_EXT_INTR:
9593                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9594                 break;
9595         default:
9596                 break;
9597         }
9598 }
9599
9600 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9601 {
9602         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9603                                   VM_EXIT_INSTRUCTION_LEN,
9604                                   IDT_VECTORING_ERROR_CODE);
9605 }
9606
9607 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9608 {
9609         __vmx_complete_interrupts(vcpu,
9610                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9611                                   VM_ENTRY_INSTRUCTION_LEN,
9612                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9613
9614         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9615 }
9616
9617 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9618 {
9619         int i, nr_msrs;
9620         struct perf_guest_switch_msr *msrs;
9621
9622         msrs = perf_guest_get_msrs(&nr_msrs);
9623
9624         if (!msrs)
9625                 return;
9626
9627         for (i = 0; i < nr_msrs; i++)
9628                 if (msrs[i].host == msrs[i].guest)
9629                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9630                 else
9631                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9632                                         msrs[i].host);
9633 }
9634
9635 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9636 {
9637         struct vcpu_vmx *vmx = to_vmx(vcpu);
9638         u64 tscl;
9639         u32 delta_tsc;
9640
9641         if (vmx->hv_deadline_tsc == -1)
9642                 return;
9643
9644         tscl = rdtsc();
9645         if (vmx->hv_deadline_tsc > tscl)
9646                 /* sure to be 32 bit only because checked on set_hv_timer */
9647                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9648                         cpu_preemption_timer_multi);
9649         else
9650                 delta_tsc = 0;
9651
9652         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9653 }
9654
9655 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9656 {
9657         struct vcpu_vmx *vmx = to_vmx(vcpu);
9658         unsigned long cr3, cr4, evmcs_rsp;
9659
9660         /* Record the guest's net vcpu time for enforced NMI injections. */
9661         if (unlikely(!enable_vnmi &&
9662                      vmx->loaded_vmcs->soft_vnmi_blocked))
9663                 vmx->loaded_vmcs->entry_time = ktime_get();
9664
9665         /* Don't enter VMX if guest state is invalid, let the exit handler
9666            start emulation until we arrive back to a valid state */
9667         if (vmx->emulation_required)
9668                 return;
9669
9670         if (vmx->ple_window_dirty) {
9671                 vmx->ple_window_dirty = false;
9672                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9673         }
9674
9675         if (vmx->nested.sync_shadow_vmcs) {
9676                 copy_vmcs12_to_shadow(vmx);
9677                 vmx->nested.sync_shadow_vmcs = false;
9678         }
9679
9680         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9681                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9682         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9683                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9684
9685         cr3 = __get_current_cr3_fast();
9686         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9687                 vmcs_writel(HOST_CR3, cr3);
9688                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9689         }
9690
9691         cr4 = cr4_read_shadow();
9692         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9693                 vmcs_writel(HOST_CR4, cr4);
9694                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9695         }
9696
9697         /* When single-stepping over STI and MOV SS, we must clear the
9698          * corresponding interruptibility bits in the guest state. Otherwise
9699          * vmentry fails as it then expects bit 14 (BS) in pending debug
9700          * exceptions being set, but that's not correct for the guest debugging
9701          * case. */
9702         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9703                 vmx_set_interrupt_shadow(vcpu, 0);
9704
9705         if (static_cpu_has(X86_FEATURE_PKU) &&
9706             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9707             vcpu->arch.pkru != vmx->host_pkru)
9708                 __write_pkru(vcpu->arch.pkru);
9709
9710         atomic_switch_perf_msrs(vmx);
9711
9712         vmx_arm_hv_timer(vcpu);
9713
9714         /*
9715          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9716          * it's non-zero. Since vmentry is serialising on affected CPUs, there
9717          * is no need to worry about the conditional branch over the wrmsr
9718          * being speculatively taken.
9719          */
9720         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
9721
9722         vmx->__launched = vmx->loaded_vmcs->launched;
9723
9724         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
9725                 (unsigned long)&current_evmcs->host_rsp : 0;
9726
9727         asm(
9728                 /* Store host registers */
9729                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9730                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9731                 "push %%" _ASM_CX " \n\t"
9732                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9733                 "je 1f \n\t"
9734                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9735                 /* Avoid VMWRITE when Enlightened VMCS is in use */
9736                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
9737                 "jz 2f \n\t"
9738                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
9739                 "jmp 1f \n\t"
9740                 "2: \n\t"
9741                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9742                 "1: \n\t"
9743                 /* Reload cr2 if changed */
9744                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9745                 "mov %%cr2, %%" _ASM_DX " \n\t"
9746                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9747                 "je 3f \n\t"
9748                 "mov %%" _ASM_AX", %%cr2 \n\t"
9749                 "3: \n\t"
9750                 /* Check if vmlaunch of vmresume is needed */
9751                 "cmpl $0, %c[launched](%0) \n\t"
9752                 /* Load guest registers.  Don't clobber flags. */
9753                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9754                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9755                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9756                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9757                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9758                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9759 #ifdef CONFIG_X86_64
9760                 "mov %c[r8](%0),  %%r8  \n\t"
9761                 "mov %c[r9](%0),  %%r9  \n\t"
9762                 "mov %c[r10](%0), %%r10 \n\t"
9763                 "mov %c[r11](%0), %%r11 \n\t"
9764                 "mov %c[r12](%0), %%r12 \n\t"
9765                 "mov %c[r13](%0), %%r13 \n\t"
9766                 "mov %c[r14](%0), %%r14 \n\t"
9767                 "mov %c[r15](%0), %%r15 \n\t"
9768 #endif
9769                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9770
9771                 /* Enter guest mode */
9772                 "jne 1f \n\t"
9773                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9774                 "jmp 2f \n\t"
9775                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9776                 "2: "
9777                 /* Save guest registers, load host registers, keep flags */
9778                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9779                 "pop %0 \n\t"
9780                 "setbe %c[fail](%0)\n\t"
9781                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9782                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9783                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9784                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9785                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9786                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9787                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9788 #ifdef CONFIG_X86_64
9789                 "mov %%r8,  %c[r8](%0) \n\t"
9790                 "mov %%r9,  %c[r9](%0) \n\t"
9791                 "mov %%r10, %c[r10](%0) \n\t"
9792                 "mov %%r11, %c[r11](%0) \n\t"
9793                 "mov %%r12, %c[r12](%0) \n\t"
9794                 "mov %%r13, %c[r13](%0) \n\t"
9795                 "mov %%r14, %c[r14](%0) \n\t"
9796                 "mov %%r15, %c[r15](%0) \n\t"
9797                 "xor %%r8d,  %%r8d \n\t"
9798                 "xor %%r9d,  %%r9d \n\t"
9799                 "xor %%r10d, %%r10d \n\t"
9800                 "xor %%r11d, %%r11d \n\t"
9801                 "xor %%r12d, %%r12d \n\t"
9802                 "xor %%r13d, %%r13d \n\t"
9803                 "xor %%r14d, %%r14d \n\t"
9804                 "xor %%r15d, %%r15d \n\t"
9805 #endif
9806                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9807                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9808
9809                 "xor %%eax, %%eax \n\t"
9810                 "xor %%ebx, %%ebx \n\t"
9811                 "xor %%esi, %%esi \n\t"
9812                 "xor %%edi, %%edi \n\t"
9813                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9814                 ".pushsection .rodata \n\t"
9815                 ".global vmx_return \n\t"
9816                 "vmx_return: " _ASM_PTR " 2b \n\t"
9817                 ".popsection"
9818               : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
9819                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9820                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9821                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9822                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9823                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9824                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9825                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9826                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9827                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9828                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9829 #ifdef CONFIG_X86_64
9830                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9831                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9832                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9833                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9834                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9835                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9836                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9837                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9838 #endif
9839                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9840                 [wordsize]"i"(sizeof(ulong))
9841               : "cc", "memory"
9842 #ifdef CONFIG_X86_64
9843                 , "rax", "rbx", "rdi"
9844                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9845 #else
9846                 , "eax", "ebx", "edi"
9847 #endif
9848               );
9849
9850         /*
9851          * We do not use IBRS in the kernel. If this vCPU has used the
9852          * SPEC_CTRL MSR it may have left it on; save the value and
9853          * turn it off. This is much more efficient than blindly adding
9854          * it to the atomic save/restore list. Especially as the former
9855          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9856          *
9857          * For non-nested case:
9858          * If the L01 MSR bitmap does not intercept the MSR, then we need to
9859          * save it.
9860          *
9861          * For nested case:
9862          * If the L02 MSR bitmap does not intercept the MSR, then we need to
9863          * save it.
9864          */
9865         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
9866                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
9867
9868         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
9869
9870         /* Eliminate branch target predictions from guest mode */
9871         vmexit_fill_RSB();
9872
9873         /* All fields are clean at this point */
9874         if (static_branch_unlikely(&enable_evmcs))
9875                 current_evmcs->hv_clean_fields |=
9876                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
9877
9878         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9879         if (vmx->host_debugctlmsr)
9880                 update_debugctlmsr(vmx->host_debugctlmsr);
9881
9882 #ifndef CONFIG_X86_64
9883         /*
9884          * The sysexit path does not restore ds/es, so we must set them to
9885          * a reasonable value ourselves.
9886          *
9887          * We can't defer this to vmx_load_host_state() since that function
9888          * may be executed in interrupt context, which saves and restore segments
9889          * around it, nullifying its effect.
9890          */
9891         loadsegment(ds, __USER_DS);
9892         loadsegment(es, __USER_DS);
9893 #endif
9894
9895         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9896                                   | (1 << VCPU_EXREG_RFLAGS)
9897                                   | (1 << VCPU_EXREG_PDPTR)
9898                                   | (1 << VCPU_EXREG_SEGMENTS)
9899                                   | (1 << VCPU_EXREG_CR3));
9900         vcpu->arch.regs_dirty = 0;
9901
9902         /*
9903          * eager fpu is enabled if PKEY is supported and CR4 is switched
9904          * back on host, so it is safe to read guest PKRU from current
9905          * XSAVE.
9906          */
9907         if (static_cpu_has(X86_FEATURE_PKU) &&
9908             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9909                 vcpu->arch.pkru = __read_pkru();
9910                 if (vcpu->arch.pkru != vmx->host_pkru)
9911                         __write_pkru(vmx->host_pkru);
9912         }
9913
9914         vmx->nested.nested_run_pending = 0;
9915         vmx->idt_vectoring_info = 0;
9916
9917         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9918         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9919                 return;
9920
9921         vmx->loaded_vmcs->launched = 1;
9922         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9923
9924         vmx_complete_atomic_exit(vmx);
9925         vmx_recover_nmi_blocking(vmx);
9926         vmx_complete_interrupts(vmx);
9927 }
9928 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9929
9930 static struct kvm *vmx_vm_alloc(void)
9931 {
9932         struct kvm_vmx *kvm_vmx = kzalloc(sizeof(struct kvm_vmx), GFP_KERNEL);
9933         return &kvm_vmx->kvm;
9934 }
9935
9936 static void vmx_vm_free(struct kvm *kvm)
9937 {
9938         kfree(to_kvm_vmx(kvm));
9939 }
9940
9941 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9942 {
9943         struct vcpu_vmx *vmx = to_vmx(vcpu);
9944         int cpu;
9945
9946         if (vmx->loaded_vmcs == vmcs)
9947                 return;
9948
9949         cpu = get_cpu();
9950         vmx->loaded_vmcs = vmcs;
9951         vmx_vcpu_put(vcpu);
9952         vmx_vcpu_load(vcpu, cpu);
9953         put_cpu();
9954 }
9955
9956 /*
9957  * Ensure that the current vmcs of the logical processor is the
9958  * vmcs01 of the vcpu before calling free_nested().
9959  */
9960 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9961 {
9962        struct vcpu_vmx *vmx = to_vmx(vcpu);
9963
9964        vcpu_load(vcpu);
9965        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9966        free_nested(vmx);
9967        vcpu_put(vcpu);
9968 }
9969
9970 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9971 {
9972         struct vcpu_vmx *vmx = to_vmx(vcpu);
9973
9974         if (enable_pml)
9975                 vmx_destroy_pml_buffer(vmx);
9976         free_vpid(vmx->vpid);
9977         leave_guest_mode(vcpu);
9978         vmx_free_vcpu_nested(vcpu);
9979         free_loaded_vmcs(vmx->loaded_vmcs);
9980         kfree(vmx->guest_msrs);
9981         kvm_vcpu_uninit(vcpu);
9982         kmem_cache_free(kvm_vcpu_cache, vmx);
9983 }
9984
9985 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9986 {
9987         int err;
9988         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9989         unsigned long *msr_bitmap;
9990         int cpu;
9991
9992         if (!vmx)
9993                 return ERR_PTR(-ENOMEM);
9994
9995         vmx->vpid = allocate_vpid();
9996
9997         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9998         if (err)
9999                 goto free_vcpu;
10000
10001         err = -ENOMEM;
10002
10003         /*
10004          * If PML is turned on, failure on enabling PML just results in failure
10005          * of creating the vcpu, therefore we can simplify PML logic (by
10006          * avoiding dealing with cases, such as enabling PML partially on vcpus
10007          * for the guest, etc.
10008          */
10009         if (enable_pml) {
10010                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10011                 if (!vmx->pml_pg)
10012                         goto uninit_vcpu;
10013         }
10014
10015         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10016         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10017                      > PAGE_SIZE);
10018
10019         if (!vmx->guest_msrs)
10020                 goto free_pml;
10021
10022         err = alloc_loaded_vmcs(&vmx->vmcs01);
10023         if (err < 0)
10024                 goto free_msrs;
10025
10026         msr_bitmap = vmx->vmcs01.msr_bitmap;
10027         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10028         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10029         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10030         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10031         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10032         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10033         vmx->msr_bitmap_mode = 0;
10034
10035         vmx->loaded_vmcs = &vmx->vmcs01;
10036         cpu = get_cpu();
10037         vmx_vcpu_load(&vmx->vcpu, cpu);
10038         vmx->vcpu.cpu = cpu;
10039         vmx_vcpu_setup(vmx);
10040         vmx_vcpu_put(&vmx->vcpu);
10041         put_cpu();
10042         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10043                 err = alloc_apic_access_page(kvm);
10044                 if (err)
10045                         goto free_vmcs;
10046         }
10047
10048         if (enable_ept && !enable_unrestricted_guest) {
10049                 err = init_rmode_identity_map(kvm);
10050                 if (err)
10051                         goto free_vmcs;
10052         }
10053
10054         if (nested) {
10055                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
10056                                            kvm_vcpu_apicv_active(&vmx->vcpu));
10057                 vmx->nested.vpid02 = allocate_vpid();
10058         }
10059
10060         vmx->nested.posted_intr_nv = -1;
10061         vmx->nested.current_vmptr = -1ull;
10062
10063         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10064
10065         /*
10066          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10067          * or POSTED_INTR_WAKEUP_VECTOR.
10068          */
10069         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10070         vmx->pi_desc.sn = 1;
10071
10072         return &vmx->vcpu;
10073
10074 free_vmcs:
10075         free_vpid(vmx->nested.vpid02);
10076         free_loaded_vmcs(vmx->loaded_vmcs);
10077 free_msrs:
10078         kfree(vmx->guest_msrs);
10079 free_pml:
10080         vmx_destroy_pml_buffer(vmx);
10081 uninit_vcpu:
10082         kvm_vcpu_uninit(&vmx->vcpu);
10083 free_vcpu:
10084         free_vpid(vmx->vpid);
10085         kmem_cache_free(kvm_vcpu_cache, vmx);
10086         return ERR_PTR(err);
10087 }
10088
10089 static int vmx_vm_init(struct kvm *kvm)
10090 {
10091         if (!ple_gap)
10092                 kvm->arch.pause_in_guest = true;
10093         return 0;
10094 }
10095
10096 static void __init vmx_check_processor_compat(void *rtn)
10097 {
10098         struct vmcs_config vmcs_conf;
10099
10100         *(int *)rtn = 0;
10101         if (setup_vmcs_config(&vmcs_conf) < 0)
10102                 *(int *)rtn = -EIO;
10103         nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
10104         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10105                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10106                                 smp_processor_id());
10107                 *(int *)rtn = -EIO;
10108         }
10109 }
10110
10111 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10112 {
10113         u8 cache;
10114         u64 ipat = 0;
10115
10116         /* For VT-d and EPT combination
10117          * 1. MMIO: always map as UC
10118          * 2. EPT with VT-d:
10119          *   a. VT-d without snooping control feature: can't guarantee the
10120          *      result, try to trust guest.
10121          *   b. VT-d with snooping control feature: snooping control feature of
10122          *      VT-d engine can guarantee the cache correctness. Just set it
10123          *      to WB to keep consistent with host. So the same as item 3.
10124          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10125          *    consistent with host MTRR
10126          */
10127         if (is_mmio) {
10128                 cache = MTRR_TYPE_UNCACHABLE;
10129                 goto exit;
10130         }
10131
10132         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10133                 ipat = VMX_EPT_IPAT_BIT;
10134                 cache = MTRR_TYPE_WRBACK;
10135                 goto exit;
10136         }
10137
10138         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10139                 ipat = VMX_EPT_IPAT_BIT;
10140                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10141                         cache = MTRR_TYPE_WRBACK;
10142                 else
10143                         cache = MTRR_TYPE_UNCACHABLE;
10144                 goto exit;
10145         }
10146
10147         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10148
10149 exit:
10150         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10151 }
10152
10153 static int vmx_get_lpage_level(void)
10154 {
10155         if (enable_ept && !cpu_has_vmx_ept_1g_page())
10156                 return PT_DIRECTORY_LEVEL;
10157         else
10158                 /* For shadow and EPT supported 1GB page */
10159                 return PT_PDPE_LEVEL;
10160 }
10161
10162 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10163 {
10164         /*
10165          * These bits in the secondary execution controls field
10166          * are dynamic, the others are mostly based on the hypervisor
10167          * architecture and the guest's CPUID.  Do not touch the
10168          * dynamic bits.
10169          */
10170         u32 mask =
10171                 SECONDARY_EXEC_SHADOW_VMCS |
10172                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10173                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10174                 SECONDARY_EXEC_DESC;
10175
10176         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10177
10178         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10179                      (new_ctl & ~mask) | (cur_ctl & mask));
10180 }
10181
10182 /*
10183  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10184  * (indicating "allowed-1") if they are supported in the guest's CPUID.
10185  */
10186 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10187 {
10188         struct vcpu_vmx *vmx = to_vmx(vcpu);
10189         struct kvm_cpuid_entry2 *entry;
10190
10191         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
10192         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
10193
10194 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
10195         if (entry && (entry->_reg & (_cpuid_mask)))                     \
10196                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
10197 } while (0)
10198
10199         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10200         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
10201         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
10202         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
10203         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
10204         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
10205         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
10206         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
10207         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
10208         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
10209         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10210         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
10211         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
10212         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
10213         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
10214
10215         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10216         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
10217         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
10218         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
10219         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
10220         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
10221
10222 #undef cr4_fixed1_update
10223 }
10224
10225 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10226 {
10227         struct vcpu_vmx *vmx = to_vmx(vcpu);
10228
10229         if (cpu_has_secondary_exec_ctrls()) {
10230                 vmx_compute_secondary_exec_control(vmx);
10231                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10232         }
10233
10234         if (nested_vmx_allowed(vcpu))
10235                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10236                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10237         else
10238                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10239                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10240
10241         if (nested_vmx_allowed(vcpu))
10242                 nested_vmx_cr_fixed1_bits_update(vcpu);
10243 }
10244
10245 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10246 {
10247         if (func == 1 && nested)
10248                 entry->ecx |= bit(X86_FEATURE_VMX);
10249 }
10250
10251 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10252                 struct x86_exception *fault)
10253 {
10254         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10255         struct vcpu_vmx *vmx = to_vmx(vcpu);
10256         u32 exit_reason;
10257         unsigned long exit_qualification = vcpu->arch.exit_qualification;
10258
10259         if (vmx->nested.pml_full) {
10260                 exit_reason = EXIT_REASON_PML_FULL;
10261                 vmx->nested.pml_full = false;
10262                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10263         } else if (fault->error_code & PFERR_RSVD_MASK)
10264                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10265         else
10266                 exit_reason = EXIT_REASON_EPT_VIOLATION;
10267
10268         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10269         vmcs12->guest_physical_address = fault->address;
10270 }
10271
10272 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10273 {
10274         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10275 }
10276
10277 /* Callbacks for nested_ept_init_mmu_context: */
10278
10279 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10280 {
10281         /* return the page table to be shadowed - in our case, EPT12 */
10282         return get_vmcs12(vcpu)->ept_pointer;
10283 }
10284
10285 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10286 {
10287         WARN_ON(mmu_is_nested(vcpu));
10288         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10289                 return 1;
10290
10291         kvm_mmu_unload(vcpu);
10292         kvm_init_shadow_ept_mmu(vcpu,
10293                         to_vmx(vcpu)->nested.msrs.ept_caps &
10294                         VMX_EPT_EXECUTE_ONLY_BIT,
10295                         nested_ept_ad_enabled(vcpu));
10296         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
10297         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
10298         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10299
10300         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
10301         return 0;
10302 }
10303
10304 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10305 {
10306         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10307 }
10308
10309 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10310                                             u16 error_code)
10311 {
10312         bool inequality, bit;
10313
10314         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10315         inequality =
10316                 (error_code & vmcs12->page_fault_error_code_mask) !=
10317                  vmcs12->page_fault_error_code_match;
10318         return inequality ^ bit;
10319 }
10320
10321 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10322                 struct x86_exception *fault)
10323 {
10324         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10325
10326         WARN_ON(!is_guest_mode(vcpu));
10327
10328         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10329                 !to_vmx(vcpu)->nested.nested_run_pending) {
10330                 vmcs12->vm_exit_intr_error_code = fault->error_code;
10331                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10332                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10333                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10334                                   fault->address);
10335         } else {
10336                 kvm_inject_page_fault(vcpu, fault);
10337         }
10338 }
10339
10340 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10341                                                  struct vmcs12 *vmcs12);
10342
10343 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10344                                         struct vmcs12 *vmcs12)
10345 {
10346         struct vcpu_vmx *vmx = to_vmx(vcpu);
10347         struct page *page;
10348         u64 hpa;
10349
10350         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10351                 /*
10352                  * Translate L1 physical address to host physical
10353                  * address for vmcs02. Keep the page pinned, so this
10354                  * physical address remains valid. We keep a reference
10355                  * to it so we can release it later.
10356                  */
10357                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10358                         kvm_release_page_dirty(vmx->nested.apic_access_page);
10359                         vmx->nested.apic_access_page = NULL;
10360                 }
10361                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10362                 /*
10363                  * If translation failed, no matter: This feature asks
10364                  * to exit when accessing the given address, and if it
10365                  * can never be accessed, this feature won't do
10366                  * anything anyway.
10367                  */
10368                 if (!is_error_page(page)) {
10369                         vmx->nested.apic_access_page = page;
10370                         hpa = page_to_phys(vmx->nested.apic_access_page);
10371                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
10372                 } else {
10373                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10374                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10375                 }
10376         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10377                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10378                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
10379                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10380                 kvm_vcpu_reload_apic_access_page(vcpu);
10381         }
10382
10383         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10384                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10385                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10386                         vmx->nested.virtual_apic_page = NULL;
10387                 }
10388                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10389
10390                 /*
10391                  * If translation failed, VM entry will fail because
10392                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10393                  * Failing the vm entry is _not_ what the processor
10394                  * does but it's basically the only possibility we
10395                  * have.  We could still enter the guest if CR8 load
10396                  * exits are enabled, CR8 store exits are enabled, and
10397                  * virtualize APIC access is disabled; in this case
10398                  * the processor would never use the TPR shadow and we
10399                  * could simply clear the bit from the execution
10400                  * control.  But such a configuration is useless, so
10401                  * let's keep the code simple.
10402                  */
10403                 if (!is_error_page(page)) {
10404                         vmx->nested.virtual_apic_page = page;
10405                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
10406                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10407                 }
10408         }
10409
10410         if (nested_cpu_has_posted_intr(vmcs12)) {
10411                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10412                         kunmap(vmx->nested.pi_desc_page);
10413                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
10414                         vmx->nested.pi_desc_page = NULL;
10415                 }
10416                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10417                 if (is_error_page(page))
10418                         return;
10419                 vmx->nested.pi_desc_page = page;
10420                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10421                 vmx->nested.pi_desc =
10422                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
10423                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10424                         (PAGE_SIZE - 1)));
10425                 vmcs_write64(POSTED_INTR_DESC_ADDR,
10426                         page_to_phys(vmx->nested.pi_desc_page) +
10427                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10428                         (PAGE_SIZE - 1)));
10429         }
10430         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10431                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10432                               CPU_BASED_USE_MSR_BITMAPS);
10433         else
10434                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10435                                 CPU_BASED_USE_MSR_BITMAPS);
10436 }
10437
10438 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10439 {
10440         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10441         struct vcpu_vmx *vmx = to_vmx(vcpu);
10442
10443         if (vcpu->arch.virtual_tsc_khz == 0)
10444                 return;
10445
10446         /* Make sure short timeouts reliably trigger an immediate vmexit.
10447          * hrtimer_start does not guarantee this. */
10448         if (preemption_timeout <= 1) {
10449                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10450                 return;
10451         }
10452
10453         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10454         preemption_timeout *= 1000000;
10455         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10456         hrtimer_start(&vmx->nested.preemption_timer,
10457                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10458 }
10459
10460 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10461                                                struct vmcs12 *vmcs12)
10462 {
10463         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10464                 return 0;
10465
10466         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10467             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10468                 return -EINVAL;
10469
10470         return 0;
10471 }
10472
10473 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10474                                                 struct vmcs12 *vmcs12)
10475 {
10476         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10477                 return 0;
10478
10479         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10480                 return -EINVAL;
10481
10482         return 0;
10483 }
10484
10485 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10486                                                 struct vmcs12 *vmcs12)
10487 {
10488         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10489                 return 0;
10490
10491         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10492                 return -EINVAL;
10493
10494         return 0;
10495 }
10496
10497 /*
10498  * Merge L0's and L1's MSR bitmap, return false to indicate that
10499  * we do not use the hardware.
10500  */
10501 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10502                                                  struct vmcs12 *vmcs12)
10503 {
10504         int msr;
10505         struct page *page;
10506         unsigned long *msr_bitmap_l1;
10507         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10508         /*
10509          * pred_cmd & spec_ctrl are trying to verify two things:
10510          *
10511          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10512          *    ensures that we do not accidentally generate an L02 MSR bitmap
10513          *    from the L12 MSR bitmap that is too permissive.
10514          * 2. That L1 or L2s have actually used the MSR. This avoids
10515          *    unnecessarily merging of the bitmap if the MSR is unused. This
10516          *    works properly because we only update the L01 MSR bitmap lazily.
10517          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10518          *    updated to reflect this when L1 (or its L2s) actually write to
10519          *    the MSR.
10520          */
10521         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10522         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10523
10524         /* Nothing to do if the MSR bitmap is not in use.  */
10525         if (!cpu_has_vmx_msr_bitmap() ||
10526             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10527                 return false;
10528
10529         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10530             !pred_cmd && !spec_ctrl)
10531                 return false;
10532
10533         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10534         if (is_error_page(page))
10535                 return false;
10536
10537         msr_bitmap_l1 = (unsigned long *)kmap(page);
10538         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10539                 /*
10540                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10541                  * just lets the processor take the value from the virtual-APIC page;
10542                  * take those 256 bits directly from the L1 bitmap.
10543                  */
10544                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10545                         unsigned word = msr / BITS_PER_LONG;
10546                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
10547                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10548                 }
10549         } else {
10550                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10551                         unsigned word = msr / BITS_PER_LONG;
10552                         msr_bitmap_l0[word] = ~0;
10553                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10554                 }
10555         }
10556
10557         nested_vmx_disable_intercept_for_msr(
10558                 msr_bitmap_l1, msr_bitmap_l0,
10559                 X2APIC_MSR(APIC_TASKPRI),
10560                 MSR_TYPE_W);
10561
10562         if (nested_cpu_has_vid(vmcs12)) {
10563                 nested_vmx_disable_intercept_for_msr(
10564                         msr_bitmap_l1, msr_bitmap_l0,
10565                         X2APIC_MSR(APIC_EOI),
10566                         MSR_TYPE_W);
10567                 nested_vmx_disable_intercept_for_msr(
10568                         msr_bitmap_l1, msr_bitmap_l0,
10569                         X2APIC_MSR(APIC_SELF_IPI),
10570                         MSR_TYPE_W);
10571         }
10572
10573         if (spec_ctrl)
10574                 nested_vmx_disable_intercept_for_msr(
10575                                         msr_bitmap_l1, msr_bitmap_l0,
10576                                         MSR_IA32_SPEC_CTRL,
10577                                         MSR_TYPE_R | MSR_TYPE_W);
10578
10579         if (pred_cmd)
10580                 nested_vmx_disable_intercept_for_msr(
10581                                         msr_bitmap_l1, msr_bitmap_l0,
10582                                         MSR_IA32_PRED_CMD,
10583                                         MSR_TYPE_W);
10584
10585         kunmap(page);
10586         kvm_release_page_clean(page);
10587
10588         return true;
10589 }
10590
10591 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
10592                                           struct vmcs12 *vmcs12)
10593 {
10594         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
10595             !page_address_valid(vcpu, vmcs12->apic_access_addr))
10596                 return -EINVAL;
10597         else
10598                 return 0;
10599 }
10600
10601 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10602                                            struct vmcs12 *vmcs12)
10603 {
10604         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10605             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10606             !nested_cpu_has_vid(vmcs12) &&
10607             !nested_cpu_has_posted_intr(vmcs12))
10608                 return 0;
10609
10610         /*
10611          * If virtualize x2apic mode is enabled,
10612          * virtualize apic access must be disabled.
10613          */
10614         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10615             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10616                 return -EINVAL;
10617
10618         /*
10619          * If virtual interrupt delivery is enabled,
10620          * we must exit on external interrupts.
10621          */
10622         if (nested_cpu_has_vid(vmcs12) &&
10623            !nested_exit_on_intr(vcpu))
10624                 return -EINVAL;
10625
10626         /*
10627          * bits 15:8 should be zero in posted_intr_nv,
10628          * the descriptor address has been already checked
10629          * in nested_get_vmcs12_pages.
10630          */
10631         if (nested_cpu_has_posted_intr(vmcs12) &&
10632            (!nested_cpu_has_vid(vmcs12) ||
10633             !nested_exit_intr_ack_set(vcpu) ||
10634             vmcs12->posted_intr_nv & 0xff00))
10635                 return -EINVAL;
10636
10637         /* tpr shadow is needed by all apicv features. */
10638         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10639                 return -EINVAL;
10640
10641         return 0;
10642 }
10643
10644 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10645                                        unsigned long count_field,
10646                                        unsigned long addr_field)
10647 {
10648         int maxphyaddr;
10649         u64 count, addr;
10650
10651         if (vmcs12_read_any(vcpu, count_field, &count) ||
10652             vmcs12_read_any(vcpu, addr_field, &addr)) {
10653                 WARN_ON(1);
10654                 return -EINVAL;
10655         }
10656         if (count == 0)
10657                 return 0;
10658         maxphyaddr = cpuid_maxphyaddr(vcpu);
10659         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10660             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10661                 pr_debug_ratelimited(
10662                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10663                         addr_field, maxphyaddr, count, addr);
10664                 return -EINVAL;
10665         }
10666         return 0;
10667 }
10668
10669 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10670                                                 struct vmcs12 *vmcs12)
10671 {
10672         if (vmcs12->vm_exit_msr_load_count == 0 &&
10673             vmcs12->vm_exit_msr_store_count == 0 &&
10674             vmcs12->vm_entry_msr_load_count == 0)
10675                 return 0; /* Fast path */
10676         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10677                                         VM_EXIT_MSR_LOAD_ADDR) ||
10678             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10679                                         VM_EXIT_MSR_STORE_ADDR) ||
10680             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10681                                         VM_ENTRY_MSR_LOAD_ADDR))
10682                 return -EINVAL;
10683         return 0;
10684 }
10685
10686 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10687                                          struct vmcs12 *vmcs12)
10688 {
10689         u64 address = vmcs12->pml_address;
10690         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10691
10692         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10693                 if (!nested_cpu_has_ept(vmcs12) ||
10694                     !IS_ALIGNED(address, 4096)  ||
10695                     address >> maxphyaddr)
10696                         return -EINVAL;
10697         }
10698
10699         return 0;
10700 }
10701
10702 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10703                                        struct vmx_msr_entry *e)
10704 {
10705         /* x2APIC MSR accesses are not allowed */
10706         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10707                 return -EINVAL;
10708         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10709             e->index == MSR_IA32_UCODE_REV)
10710                 return -EINVAL;
10711         if (e->reserved != 0)
10712                 return -EINVAL;
10713         return 0;
10714 }
10715
10716 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10717                                      struct vmx_msr_entry *e)
10718 {
10719         if (e->index == MSR_FS_BASE ||
10720             e->index == MSR_GS_BASE ||
10721             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10722             nested_vmx_msr_check_common(vcpu, e))
10723                 return -EINVAL;
10724         return 0;
10725 }
10726
10727 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10728                                       struct vmx_msr_entry *e)
10729 {
10730         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10731             nested_vmx_msr_check_common(vcpu, e))
10732                 return -EINVAL;
10733         return 0;
10734 }
10735
10736 /*
10737  * Load guest's/host's msr at nested entry/exit.
10738  * return 0 for success, entry index for failure.
10739  */
10740 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10741 {
10742         u32 i;
10743         struct vmx_msr_entry e;
10744         struct msr_data msr;
10745
10746         msr.host_initiated = false;
10747         for (i = 0; i < count; i++) {
10748                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10749                                         &e, sizeof(e))) {
10750                         pr_debug_ratelimited(
10751                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10752                                 __func__, i, gpa + i * sizeof(e));
10753                         goto fail;
10754                 }
10755                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10756                         pr_debug_ratelimited(
10757                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10758                                 __func__, i, e.index, e.reserved);
10759                         goto fail;
10760                 }
10761                 msr.index = e.index;
10762                 msr.data = e.value;
10763                 if (kvm_set_msr(vcpu, &msr)) {
10764                         pr_debug_ratelimited(
10765                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10766                                 __func__, i, e.index, e.value);
10767                         goto fail;
10768                 }
10769         }
10770         return 0;
10771 fail:
10772         return i + 1;
10773 }
10774
10775 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10776 {
10777         u32 i;
10778         struct vmx_msr_entry e;
10779
10780         for (i = 0; i < count; i++) {
10781                 struct msr_data msr_info;
10782                 if (kvm_vcpu_read_guest(vcpu,
10783                                         gpa + i * sizeof(e),
10784                                         &e, 2 * sizeof(u32))) {
10785                         pr_debug_ratelimited(
10786                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10787                                 __func__, i, gpa + i * sizeof(e));
10788                         return -EINVAL;
10789                 }
10790                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10791                         pr_debug_ratelimited(
10792                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10793                                 __func__, i, e.index, e.reserved);
10794                         return -EINVAL;
10795                 }
10796                 msr_info.host_initiated = false;
10797                 msr_info.index = e.index;
10798                 if (kvm_get_msr(vcpu, &msr_info)) {
10799                         pr_debug_ratelimited(
10800                                 "%s cannot read MSR (%u, 0x%x)\n",
10801                                 __func__, i, e.index);
10802                         return -EINVAL;
10803                 }
10804                 if (kvm_vcpu_write_guest(vcpu,
10805                                          gpa + i * sizeof(e) +
10806                                              offsetof(struct vmx_msr_entry, value),
10807                                          &msr_info.data, sizeof(msr_info.data))) {
10808                         pr_debug_ratelimited(
10809                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10810                                 __func__, i, e.index, msr_info.data);
10811                         return -EINVAL;
10812                 }
10813         }
10814         return 0;
10815 }
10816
10817 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10818 {
10819         unsigned long invalid_mask;
10820
10821         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10822         return (val & invalid_mask) == 0;
10823 }
10824
10825 /*
10826  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10827  * emulating VM entry into a guest with EPT enabled.
10828  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10829  * is assigned to entry_failure_code on failure.
10830  */
10831 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10832                                u32 *entry_failure_code)
10833 {
10834         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10835                 if (!nested_cr3_valid(vcpu, cr3)) {
10836                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10837                         return 1;
10838                 }
10839
10840                 /*
10841                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10842                  * must not be dereferenced.
10843                  */
10844                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10845                     !nested_ept) {
10846                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10847                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10848                                 return 1;
10849                         }
10850                 }
10851
10852                 vcpu->arch.cr3 = cr3;
10853                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10854         }
10855
10856         kvm_mmu_reset_context(vcpu);
10857         return 0;
10858 }
10859
10860 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10861                                bool from_vmentry)
10862 {
10863         struct vcpu_vmx *vmx = to_vmx(vcpu);
10864
10865         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10866         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10867         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10868         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10869         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10870         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10871         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10872         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10873         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10874         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10875         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10876         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10877         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10878         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10879         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10880         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10881         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10882         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10883         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10884         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10885         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10886         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10887         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10888         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10889         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10890         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10891         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10892         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10893         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10894         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10895         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10896
10897         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10898         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10899                 vmcs12->guest_pending_dbg_exceptions);
10900         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10901         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10902
10903         if (nested_cpu_has_xsaves(vmcs12))
10904                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10905         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10906
10907         if (cpu_has_vmx_posted_intr())
10908                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10909
10910         /*
10911          * Whether page-faults are trapped is determined by a combination of
10912          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10913          * If enable_ept, L0 doesn't care about page faults and we should
10914          * set all of these to L1's desires. However, if !enable_ept, L0 does
10915          * care about (at least some) page faults, and because it is not easy
10916          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10917          * to exit on each and every L2 page fault. This is done by setting
10918          * MASK=MATCH=0 and (see below) EB.PF=1.
10919          * Note that below we don't need special code to set EB.PF beyond the
10920          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10921          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10922          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10923          */
10924         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10925                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10926         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10927                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10928
10929         /* All VMFUNCs are currently emulated through L0 vmexits.  */
10930         if (cpu_has_vmx_vmfunc())
10931                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
10932
10933         if (cpu_has_vmx_apicv()) {
10934                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
10935                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
10936                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
10937                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
10938         }
10939
10940         /*
10941          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10942          * Some constant fields are set here by vmx_set_constant_host_state().
10943          * Other fields are different per CPU, and will be set later when
10944          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10945          */
10946         vmx_set_constant_host_state(vmx);
10947
10948         /*
10949          * Set the MSR load/store lists to match L0's settings.
10950          */
10951         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10952         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10953         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10954         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10955         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10956
10957         set_cr4_guest_host_mask(vmx);
10958
10959         if (vmx_mpx_supported())
10960                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10961
10962         if (enable_vpid) {
10963                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
10964                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10965                 else
10966                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10967         }
10968
10969         /*
10970          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10971          */
10972         if (enable_ept) {
10973                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10974                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10975                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10976                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10977         }
10978
10979         if (cpu_has_vmx_msr_bitmap())
10980                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
10981 }
10982
10983 /*
10984  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10985  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10986  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10987  * guest in a way that will both be appropriate to L1's requests, and our
10988  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10989  * function also has additional necessary side-effects, like setting various
10990  * vcpu->arch fields.
10991  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10992  * is assigned to entry_failure_code on failure.
10993  */
10994 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10995                           bool from_vmentry, u32 *entry_failure_code)
10996 {
10997         struct vcpu_vmx *vmx = to_vmx(vcpu);
10998         u32 exec_control, vmcs12_exec_ctrl;
10999
11000         if (vmx->nested.dirty_vmcs12) {
11001                 prepare_vmcs02_full(vcpu, vmcs12, from_vmentry);
11002                 vmx->nested.dirty_vmcs12 = false;
11003         }
11004
11005         /*
11006          * First, the fields that are shadowed.  This must be kept in sync
11007          * with vmx_shadow_fields.h.
11008          */
11009
11010         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11011         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11012         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11013         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11014         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11015
11016         /*
11017          * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
11018          * HOST_FS_BASE, HOST_GS_BASE.
11019          */
11020
11021         if (from_vmentry &&
11022             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11023                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11024                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11025         } else {
11026                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11027                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11028         }
11029         if (from_vmentry) {
11030                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11031                              vmcs12->vm_entry_intr_info_field);
11032                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11033                              vmcs12->vm_entry_exception_error_code);
11034                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11035                              vmcs12->vm_entry_instruction_len);
11036                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11037                              vmcs12->guest_interruptibility_info);
11038                 vmx->loaded_vmcs->nmi_known_unmasked =
11039                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11040         } else {
11041                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11042         }
11043         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11044
11045         exec_control = vmcs12->pin_based_vm_exec_control;
11046
11047         /* Preemption timer setting is only taken from vmcs01.  */
11048         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11049         exec_control |= vmcs_config.pin_based_exec_ctrl;
11050         if (vmx->hv_deadline_tsc == -1)
11051                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11052
11053         /* Posted interrupts setting is only taken from vmcs12.  */
11054         if (nested_cpu_has_posted_intr(vmcs12)) {
11055                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11056                 vmx->nested.pi_pending = false;
11057         } else {
11058                 exec_control &= ~PIN_BASED_POSTED_INTR;
11059         }
11060
11061         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11062
11063         vmx->nested.preemption_timer_expired = false;
11064         if (nested_cpu_has_preemption_timer(vmcs12))
11065                 vmx_start_preemption_timer(vcpu);
11066
11067         if (cpu_has_secondary_exec_ctrls()) {
11068                 exec_control = vmx->secondary_exec_control;
11069
11070                 /* Take the following fields only from vmcs12 */
11071                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11072                                   SECONDARY_EXEC_ENABLE_INVPCID |
11073                                   SECONDARY_EXEC_RDTSCP |
11074                                   SECONDARY_EXEC_XSAVES |
11075                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11076                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
11077                                   SECONDARY_EXEC_ENABLE_VMFUNC);
11078                 if (nested_cpu_has(vmcs12,
11079                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11080                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11081                                 ~SECONDARY_EXEC_ENABLE_PML;
11082                         exec_control |= vmcs12_exec_ctrl;
11083                 }
11084
11085                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
11086                         vmcs_write16(GUEST_INTR_STATUS,
11087                                 vmcs12->guest_intr_status);
11088
11089                 /*
11090                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
11091                  * nested_get_vmcs12_pages will either fix it up or
11092                  * remove the VM execution control.
11093                  */
11094                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11095                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11096
11097                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11098         }
11099
11100         /*
11101          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11102          * entry, but only if the current (host) sp changed from the value
11103          * we wrote last (vmx->host_rsp). This cache is no longer relevant
11104          * if we switch vmcs, and rather than hold a separate cache per vmcs,
11105          * here we just force the write to happen on entry.
11106          */
11107         vmx->host_rsp = 0;
11108
11109         exec_control = vmx_exec_control(vmx); /* L0's desires */
11110         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11111         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11112         exec_control &= ~CPU_BASED_TPR_SHADOW;
11113         exec_control |= vmcs12->cpu_based_vm_exec_control;
11114
11115         /*
11116          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11117          * nested_get_vmcs12_pages can't fix it up, the illegal value
11118          * will result in a VM entry failure.
11119          */
11120         if (exec_control & CPU_BASED_TPR_SHADOW) {
11121                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11122                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11123         } else {
11124 #ifdef CONFIG_X86_64
11125                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11126                                 CPU_BASED_CR8_STORE_EXITING;
11127 #endif
11128         }
11129
11130         /*
11131          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
11132          * for I/O port accesses.
11133          */
11134         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11135         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11136
11137         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11138
11139         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11140          * bitwise-or of what L1 wants to trap for L2, and what we want to
11141          * trap. Note that CR0.TS also needs updating - we do this later.
11142          */
11143         update_exception_bitmap(vcpu);
11144         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11145         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11146
11147         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11148          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11149          * bits are further modified by vmx_set_efer() below.
11150          */
11151         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11152
11153         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11154          * emulated by vmx_set_efer(), below.
11155          */
11156         vm_entry_controls_init(vmx,
11157                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11158                         ~VM_ENTRY_IA32E_MODE) |
11159                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11160
11161         if (from_vmentry &&
11162             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11163                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11164                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11165         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11166                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11167         }
11168
11169         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11170
11171         if (kvm_has_tsc_control)
11172                 decache_tsc_multiplier(vmx);
11173
11174         if (enable_vpid) {
11175                 /*
11176                  * There is no direct mapping between vpid02 and vpid12, the
11177                  * vpid02 is per-vCPU for L0 and reused while the value of
11178                  * vpid12 is changed w/ one invvpid during nested vmentry.
11179                  * The vpid12 is allocated by L1 for L2, so it will not
11180                  * influence global bitmap(for vpid01 and vpid02 allocation)
11181                  * even if spawn a lot of nested vCPUs.
11182                  */
11183                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11184                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11185                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11186                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true);
11187                         }
11188                 } else {
11189                         vmx_flush_tlb(vcpu, true);
11190                 }
11191         }
11192
11193         if (enable_pml) {
11194                 /*
11195                  * Conceptually we want to copy the PML address and index from
11196                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11197                  * since we always flush the log on each vmexit, this happens
11198                  * to be equivalent to simply resetting the fields in vmcs02.
11199                  */
11200                 ASSERT(vmx->pml_pg);
11201                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11202                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11203         }
11204
11205         if (nested_cpu_has_ept(vmcs12)) {
11206                 if (nested_ept_init_mmu_context(vcpu)) {
11207                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11208                         return 1;
11209                 }
11210         } else if (nested_cpu_has2(vmcs12,
11211                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11212                 vmx_flush_tlb(vcpu, true);
11213         }
11214
11215         /*
11216          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11217          * bits which we consider mandatory enabled.
11218          * The CR0_READ_SHADOW is what L2 should have expected to read given
11219          * the specifications by L1; It's not enough to take
11220          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11221          * have more bits than L1 expected.
11222          */
11223         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11224         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11225
11226         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11227         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11228
11229         if (from_vmentry &&
11230             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11231                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11232         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11233                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11234         else
11235                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11236         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11237         vmx_set_efer(vcpu, vcpu->arch.efer);
11238
11239         /*
11240          * Guest state is invalid and unrestricted guest is disabled,
11241          * which means L1 attempted VMEntry to L2 with invalid state.
11242          * Fail the VMEntry.
11243          */
11244         if (vmx->emulation_required) {
11245                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11246                 return 1;
11247         }
11248
11249         /* Shadow page tables on either EPT or shadow page tables. */
11250         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11251                                 entry_failure_code))
11252                 return 1;
11253
11254         if (!enable_ept)
11255                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11256
11257         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11258         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11259         return 0;
11260 }
11261
11262 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
11263 {
11264         if (!nested_cpu_has_nmi_exiting(vmcs12) &&
11265             nested_cpu_has_virtual_nmis(vmcs12))
11266                 return -EINVAL;
11267
11268         if (!nested_cpu_has_virtual_nmis(vmcs12) &&
11269             nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
11270                 return -EINVAL;
11271
11272         return 0;
11273 }
11274
11275 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11276 {
11277         struct vcpu_vmx *vmx = to_vmx(vcpu);
11278
11279         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11280             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11281                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11282
11283         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11284                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11285
11286         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11287                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11288
11289         if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11290                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11291
11292         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11293                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11294
11295         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11296                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11297
11298         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11299                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11300
11301         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11302                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11303
11304         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11305                                 vmx->nested.msrs.procbased_ctls_low,
11306                                 vmx->nested.msrs.procbased_ctls_high) ||
11307             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11308              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11309                                  vmx->nested.msrs.secondary_ctls_low,
11310                                  vmx->nested.msrs.secondary_ctls_high)) ||
11311             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11312                                 vmx->nested.msrs.pinbased_ctls_low,
11313                                 vmx->nested.msrs.pinbased_ctls_high) ||
11314             !vmx_control_verify(vmcs12->vm_exit_controls,
11315                                 vmx->nested.msrs.exit_ctls_low,
11316                                 vmx->nested.msrs.exit_ctls_high) ||
11317             !vmx_control_verify(vmcs12->vm_entry_controls,
11318                                 vmx->nested.msrs.entry_ctls_low,
11319                                 vmx->nested.msrs.entry_ctls_high))
11320                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11321
11322         if (nested_vmx_check_nmi_controls(vmcs12))
11323                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11324
11325         if (nested_cpu_has_vmfunc(vmcs12)) {
11326                 if (vmcs12->vm_function_control &
11327                     ~vmx->nested.msrs.vmfunc_controls)
11328                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11329
11330                 if (nested_cpu_has_eptp_switching(vmcs12)) {
11331                         if (!nested_cpu_has_ept(vmcs12) ||
11332                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
11333                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11334                 }
11335         }
11336
11337         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11338                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11339
11340         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11341             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11342             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11343                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11344
11345         return 0;
11346 }
11347
11348 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11349                                   u32 *exit_qual)
11350 {
11351         bool ia32e;
11352
11353         *exit_qual = ENTRY_FAIL_DEFAULT;
11354
11355         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11356             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11357                 return 1;
11358
11359         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11360             vmcs12->vmcs_link_pointer != -1ull) {
11361                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11362                 return 1;
11363         }
11364
11365         /*
11366          * If the load IA32_EFER VM-entry control is 1, the following checks
11367          * are performed on the field for the IA32_EFER MSR:
11368          * - Bits reserved in the IA32_EFER MSR must be 0.
11369          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11370          *   the IA-32e mode guest VM-exit control. It must also be identical
11371          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11372          *   CR0.PG) is 1.
11373          */
11374         if (to_vmx(vcpu)->nested.nested_run_pending &&
11375             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11376                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11377                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11378                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11379                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11380                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11381                         return 1;
11382         }
11383
11384         /*
11385          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11386          * IA32_EFER MSR must be 0 in the field for that register. In addition,
11387          * the values of the LMA and LME bits in the field must each be that of
11388          * the host address-space size VM-exit control.
11389          */
11390         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11391                 ia32e = (vmcs12->vm_exit_controls &
11392                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11393                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11394                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11395                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11396                         return 1;
11397         }
11398
11399         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11400                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11401                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11402                         return 1;
11403
11404         return 0;
11405 }
11406
11407 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
11408 {
11409         struct vcpu_vmx *vmx = to_vmx(vcpu);
11410         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11411         u32 msr_entry_idx;
11412         u32 exit_qual;
11413         int r;
11414
11415         enter_guest_mode(vcpu);
11416
11417         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11418                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11419
11420         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11421         vmx_segment_cache_clear(vmx);
11422
11423         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11424                 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
11425
11426         r = EXIT_REASON_INVALID_STATE;
11427         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual))
11428                 goto fail;
11429
11430         nested_get_vmcs12_pages(vcpu, vmcs12);
11431
11432         r = EXIT_REASON_MSR_LOAD_FAIL;
11433         msr_entry_idx = nested_vmx_load_msr(vcpu,
11434                                             vmcs12->vm_entry_msr_load_addr,
11435                                             vmcs12->vm_entry_msr_load_count);
11436         if (msr_entry_idx)
11437                 goto fail;
11438
11439         /*
11440          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11441          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11442          * returned as far as L1 is concerned. It will only return (and set
11443          * the success flag) when L2 exits (see nested_vmx_vmexit()).
11444          */
11445         return 0;
11446
11447 fail:
11448         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11449                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
11450         leave_guest_mode(vcpu);
11451         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11452         nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual);
11453         return 1;
11454 }
11455
11456 /*
11457  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11458  * for running an L2 nested guest.
11459  */
11460 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11461 {
11462         struct vmcs12 *vmcs12;
11463         struct vcpu_vmx *vmx = to_vmx(vcpu);
11464         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11465         u32 exit_qual;
11466         int ret;
11467
11468         if (!nested_vmx_check_permission(vcpu))
11469                 return 1;
11470
11471         if (!nested_vmx_check_vmcs12(vcpu))
11472                 goto out;
11473
11474         vmcs12 = get_vmcs12(vcpu);
11475
11476         if (enable_shadow_vmcs)
11477                 copy_shadow_to_vmcs12(vmx);
11478
11479         /*
11480          * The nested entry process starts with enforcing various prerequisites
11481          * on vmcs12 as required by the Intel SDM, and act appropriately when
11482          * they fail: As the SDM explains, some conditions should cause the
11483          * instruction to fail, while others will cause the instruction to seem
11484          * to succeed, but return an EXIT_REASON_INVALID_STATE.
11485          * To speed up the normal (success) code path, we should avoid checking
11486          * for misconfigurations which will anyway be caught by the processor
11487          * when using the merged vmcs02.
11488          */
11489         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11490                 nested_vmx_failValid(vcpu,
11491                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11492                 goto out;
11493         }
11494
11495         if (vmcs12->launch_state == launch) {
11496                 nested_vmx_failValid(vcpu,
11497                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11498                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11499                 goto out;
11500         }
11501
11502         ret = check_vmentry_prereqs(vcpu, vmcs12);
11503         if (ret) {
11504                 nested_vmx_failValid(vcpu, ret);
11505                 goto out;
11506         }
11507
11508         /*
11509          * After this point, the trap flag no longer triggers a singlestep trap
11510          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11511          * This is not 100% correct; for performance reasons, we delegate most
11512          * of the checks on host state to the processor.  If those fail,
11513          * the singlestep trap is missed.
11514          */
11515         skip_emulated_instruction(vcpu);
11516
11517         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11518         if (ret) {
11519                 nested_vmx_entry_failure(vcpu, vmcs12,
11520                                          EXIT_REASON_INVALID_STATE, exit_qual);
11521                 return 1;
11522         }
11523
11524         /*
11525          * We're finally done with prerequisite checking, and can start with
11526          * the nested entry.
11527          */
11528
11529         ret = enter_vmx_non_root_mode(vcpu, true);
11530         if (ret)
11531                 return ret;
11532
11533         /*
11534          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11535          * by event injection, halt vcpu.
11536          */
11537         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11538             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK))
11539                 return kvm_vcpu_halt(vcpu);
11540
11541         vmx->nested.nested_run_pending = 1;
11542
11543         return 1;
11544
11545 out:
11546         return kvm_skip_emulated_instruction(vcpu);
11547 }
11548
11549 /*
11550  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11551  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11552  * This function returns the new value we should put in vmcs12.guest_cr0.
11553  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11554  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11555  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11556  *     didn't trap the bit, because if L1 did, so would L0).
11557  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11558  *     been modified by L2, and L1 knows it. So just leave the old value of
11559  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11560  *     isn't relevant, because if L0 traps this bit it can set it to anything.
11561  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11562  *     changed these bits, and therefore they need to be updated, but L0
11563  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11564  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11565  */
11566 static inline unsigned long
11567 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11568 {
11569         return
11570         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11571         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11572         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11573                         vcpu->arch.cr0_guest_owned_bits));
11574 }
11575
11576 static inline unsigned long
11577 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11578 {
11579         return
11580         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11581         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11582         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11583                         vcpu->arch.cr4_guest_owned_bits));
11584 }
11585
11586 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11587                                        struct vmcs12 *vmcs12)
11588 {
11589         u32 idt_vectoring;
11590         unsigned int nr;
11591
11592         if (vcpu->arch.exception.injected) {
11593                 nr = vcpu->arch.exception.nr;
11594                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11595
11596                 if (kvm_exception_is_soft(nr)) {
11597                         vmcs12->vm_exit_instruction_len =
11598                                 vcpu->arch.event_exit_inst_len;
11599                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11600                 } else
11601                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11602
11603                 if (vcpu->arch.exception.has_error_code) {
11604                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11605                         vmcs12->idt_vectoring_error_code =
11606                                 vcpu->arch.exception.error_code;
11607                 }
11608
11609                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11610         } else if (vcpu->arch.nmi_injected) {
11611                 vmcs12->idt_vectoring_info_field =
11612                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11613         } else if (vcpu->arch.interrupt.injected) {
11614                 nr = vcpu->arch.interrupt.nr;
11615                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11616
11617                 if (vcpu->arch.interrupt.soft) {
11618                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11619                         vmcs12->vm_entry_instruction_len =
11620                                 vcpu->arch.event_exit_inst_len;
11621                 } else
11622                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11623
11624                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11625         }
11626 }
11627
11628 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11629 {
11630         struct vcpu_vmx *vmx = to_vmx(vcpu);
11631         unsigned long exit_qual;
11632         bool block_nested_events =
11633             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11634
11635         if (vcpu->arch.exception.pending &&
11636                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11637                 if (block_nested_events)
11638                         return -EBUSY;
11639                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11640                 return 0;
11641         }
11642
11643         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11644             vmx->nested.preemption_timer_expired) {
11645                 if (block_nested_events)
11646                         return -EBUSY;
11647                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11648                 return 0;
11649         }
11650
11651         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11652                 if (block_nested_events)
11653                         return -EBUSY;
11654                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11655                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11656                                   INTR_INFO_VALID_MASK, 0);
11657                 /*
11658                  * The NMI-triggered VM exit counts as injection:
11659                  * clear this one and block further NMIs.
11660                  */
11661                 vcpu->arch.nmi_pending = 0;
11662                 vmx_set_nmi_mask(vcpu, true);
11663                 return 0;
11664         }
11665
11666         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11667             nested_exit_on_intr(vcpu)) {
11668                 if (block_nested_events)
11669                         return -EBUSY;
11670                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11671                 return 0;
11672         }
11673
11674         vmx_complete_nested_posted_interrupt(vcpu);
11675         return 0;
11676 }
11677
11678 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11679 {
11680         ktime_t remaining =
11681                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11682         u64 value;
11683
11684         if (ktime_to_ns(remaining) <= 0)
11685                 return 0;
11686
11687         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11688         do_div(value, 1000000);
11689         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11690 }
11691
11692 /*
11693  * Update the guest state fields of vmcs12 to reflect changes that
11694  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11695  * VM-entry controls is also updated, since this is really a guest
11696  * state bit.)
11697  */
11698 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11699 {
11700         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11701         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11702
11703         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11704         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11705         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11706
11707         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11708         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11709         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11710         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11711         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11712         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11713         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11714         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11715         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11716         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11717         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11718         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11719         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11720         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11721         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11722         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11723         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11724         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11725         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11726         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11727         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11728         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11729         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11730         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11731         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11732         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11733         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11734         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11735         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11736         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11737         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11738         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11739         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11740         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11741         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11742         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11743
11744         vmcs12->guest_interruptibility_info =
11745                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11746         vmcs12->guest_pending_dbg_exceptions =
11747                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11748         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11749                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11750         else
11751                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11752
11753         if (nested_cpu_has_preemption_timer(vmcs12)) {
11754                 if (vmcs12->vm_exit_controls &
11755                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11756                         vmcs12->vmx_preemption_timer_value =
11757                                 vmx_get_preemption_timer_value(vcpu);
11758                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11759         }
11760
11761         /*
11762          * In some cases (usually, nested EPT), L2 is allowed to change its
11763          * own CR3 without exiting. If it has changed it, we must keep it.
11764          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11765          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11766          *
11767          * Additionally, restore L2's PDPTR to vmcs12.
11768          */
11769         if (enable_ept) {
11770                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11771                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11772                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11773                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11774                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11775         }
11776
11777         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11778
11779         if (nested_cpu_has_vid(vmcs12))
11780                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11781
11782         vmcs12->vm_entry_controls =
11783                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11784                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11785
11786         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11787                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11788                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11789         }
11790
11791         /* TODO: These cannot have changed unless we have MSR bitmaps and
11792          * the relevant bit asks not to trap the change */
11793         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11794                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11795         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11796                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11797         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11798         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11799         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11800         if (kvm_mpx_supported())
11801                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11802 }
11803
11804 /*
11805  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11806  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11807  * and this function updates it to reflect the changes to the guest state while
11808  * L2 was running (and perhaps made some exits which were handled directly by L0
11809  * without going back to L1), and to reflect the exit reason.
11810  * Note that we do not have to copy here all VMCS fields, just those that
11811  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11812  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11813  * which already writes to vmcs12 directly.
11814  */
11815 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11816                            u32 exit_reason, u32 exit_intr_info,
11817                            unsigned long exit_qualification)
11818 {
11819         /* update guest state fields: */
11820         sync_vmcs12(vcpu, vmcs12);
11821
11822         /* update exit information fields: */
11823
11824         vmcs12->vm_exit_reason = exit_reason;
11825         vmcs12->exit_qualification = exit_qualification;
11826         vmcs12->vm_exit_intr_info = exit_intr_info;
11827
11828         vmcs12->idt_vectoring_info_field = 0;
11829         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11830         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11831
11832         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11833                 vmcs12->launch_state = 1;
11834
11835                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11836                  * instead of reading the real value. */
11837                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11838
11839                 /*
11840                  * Transfer the event that L0 or L1 may wanted to inject into
11841                  * L2 to IDT_VECTORING_INFO_FIELD.
11842                  */
11843                 vmcs12_save_pending_event(vcpu, vmcs12);
11844         }
11845
11846         /*
11847          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11848          * preserved above and would only end up incorrectly in L1.
11849          */
11850         vcpu->arch.nmi_injected = false;
11851         kvm_clear_exception_queue(vcpu);
11852         kvm_clear_interrupt_queue(vcpu);
11853 }
11854
11855 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
11856                         struct vmcs12 *vmcs12)
11857 {
11858         u32 entry_failure_code;
11859
11860         nested_ept_uninit_mmu_context(vcpu);
11861
11862         /*
11863          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11864          * couldn't have changed.
11865          */
11866         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11867                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11868
11869         if (!enable_ept)
11870                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11871 }
11872
11873 /*
11874  * A part of what we need to when the nested L2 guest exits and we want to
11875  * run its L1 parent, is to reset L1's guest state to the host state specified
11876  * in vmcs12.
11877  * This function is to be called not only on normal nested exit, but also on
11878  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11879  * Failures During or After Loading Guest State").
11880  * This function should be called when the active VMCS is L1's (vmcs01).
11881  */
11882 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11883                                    struct vmcs12 *vmcs12)
11884 {
11885         struct kvm_segment seg;
11886
11887         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11888                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11889         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11890                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11891         else
11892                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11893         vmx_set_efer(vcpu, vcpu->arch.efer);
11894
11895         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11896         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11897         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11898         /*
11899          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11900          * actually changed, because vmx_set_cr0 refers to efer set above.
11901          *
11902          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11903          * (KVM doesn't change it);
11904          */
11905         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11906         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11907
11908         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11909         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11910         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11911
11912         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11913
11914         if (enable_vpid) {
11915                 /*
11916                  * Trivially support vpid by letting L2s share their parent
11917                  * L1's vpid. TODO: move to a more elaborate solution, giving
11918                  * each L2 its own vpid and exposing the vpid feature to L1.
11919                  */
11920                 vmx_flush_tlb(vcpu, true);
11921         }
11922
11923         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11924         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11925         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11926         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11927         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11928         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11929         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
11930
11931         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11932         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11933                 vmcs_write64(GUEST_BNDCFGS, 0);
11934
11935         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11936                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11937                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11938         }
11939         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11940                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11941                         vmcs12->host_ia32_perf_global_ctrl);
11942
11943         /* Set L1 segment info according to Intel SDM
11944             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11945         seg = (struct kvm_segment) {
11946                 .base = 0,
11947                 .limit = 0xFFFFFFFF,
11948                 .selector = vmcs12->host_cs_selector,
11949                 .type = 11,
11950                 .present = 1,
11951                 .s = 1,
11952                 .g = 1
11953         };
11954         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11955                 seg.l = 1;
11956         else
11957                 seg.db = 1;
11958         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11959         seg = (struct kvm_segment) {
11960                 .base = 0,
11961                 .limit = 0xFFFFFFFF,
11962                 .type = 3,
11963                 .present = 1,
11964                 .s = 1,
11965                 .db = 1,
11966                 .g = 1
11967         };
11968         seg.selector = vmcs12->host_ds_selector;
11969         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11970         seg.selector = vmcs12->host_es_selector;
11971         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11972         seg.selector = vmcs12->host_ss_selector;
11973         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11974         seg.selector = vmcs12->host_fs_selector;
11975         seg.base = vmcs12->host_fs_base;
11976         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11977         seg.selector = vmcs12->host_gs_selector;
11978         seg.base = vmcs12->host_gs_base;
11979         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11980         seg = (struct kvm_segment) {
11981                 .base = vmcs12->host_tr_base,
11982                 .limit = 0x67,
11983                 .selector = vmcs12->host_tr_selector,
11984                 .type = 11,
11985                 .present = 1
11986         };
11987         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11988
11989         kvm_set_dr(vcpu, 7, 0x400);
11990         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11991
11992         if (cpu_has_vmx_msr_bitmap())
11993                 vmx_update_msr_bitmap(vcpu);
11994
11995         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11996                                 vmcs12->vm_exit_msr_load_count))
11997                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11998 }
11999
12000 /*
12001  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12002  * and modify vmcs12 to make it see what it would expect to see there if
12003  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12004  */
12005 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12006                               u32 exit_intr_info,
12007                               unsigned long exit_qualification)
12008 {
12009         struct vcpu_vmx *vmx = to_vmx(vcpu);
12010         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12011
12012         /* trying to cancel vmlaunch/vmresume is a bug */
12013         WARN_ON_ONCE(vmx->nested.nested_run_pending);
12014
12015         /*
12016          * The only expected VM-instruction error is "VM entry with
12017          * invalid control field(s)." Anything else indicates a
12018          * problem with L0.
12019          */
12020         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12021                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12022
12023         leave_guest_mode(vcpu);
12024
12025         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12026                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12027
12028         if (likely(!vmx->fail)) {
12029                 if (exit_reason == -1)
12030                         sync_vmcs12(vcpu, vmcs12);
12031                 else
12032                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12033                                        exit_qualification);
12034
12035                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12036                                          vmcs12->vm_exit_msr_store_count))
12037                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12038         }
12039
12040         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12041         vm_entry_controls_reset_shadow(vmx);
12042         vm_exit_controls_reset_shadow(vmx);
12043         vmx_segment_cache_clear(vmx);
12044
12045         /* Update any VMCS fields that might have changed while L2 ran */
12046         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12047         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12048         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12049         if (vmx->hv_deadline_tsc == -1)
12050                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12051                                 PIN_BASED_VMX_PREEMPTION_TIMER);
12052         else
12053                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12054                               PIN_BASED_VMX_PREEMPTION_TIMER);
12055         if (kvm_has_tsc_control)
12056                 decache_tsc_multiplier(vmx);
12057
12058         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
12059                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
12060                 vmx_set_virtual_x2apic_mode(vcpu,
12061                                 vcpu->arch.apic_base & X2APIC_ENABLE);
12062         } else if (!nested_cpu_has_ept(vmcs12) &&
12063                    nested_cpu_has2(vmcs12,
12064                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12065                 vmx_flush_tlb(vcpu, true);
12066         }
12067
12068         /* This is needed for same reason as it was needed in prepare_vmcs02 */
12069         vmx->host_rsp = 0;
12070
12071         /* Unpin physical memory we referred to in vmcs02 */
12072         if (vmx->nested.apic_access_page) {
12073                 kvm_release_page_dirty(vmx->nested.apic_access_page);
12074                 vmx->nested.apic_access_page = NULL;
12075         }
12076         if (vmx->nested.virtual_apic_page) {
12077                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12078                 vmx->nested.virtual_apic_page = NULL;
12079         }
12080         if (vmx->nested.pi_desc_page) {
12081                 kunmap(vmx->nested.pi_desc_page);
12082                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12083                 vmx->nested.pi_desc_page = NULL;
12084                 vmx->nested.pi_desc = NULL;
12085         }
12086
12087         /*
12088          * We are now running in L2, mmu_notifier will force to reload the
12089          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12090          */
12091         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12092
12093         if (enable_shadow_vmcs && exit_reason != -1)
12094                 vmx->nested.sync_shadow_vmcs = true;
12095
12096         /* in case we halted in L2 */
12097         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12098
12099         if (likely(!vmx->fail)) {
12100                 /*
12101                  * TODO: SDM says that with acknowledge interrupt on
12102                  * exit, bit 31 of the VM-exit interrupt information
12103                  * (valid interrupt) is always set to 1 on
12104                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12105                  * need kvm_cpu_has_interrupt().  See the commit
12106                  * message for details.
12107                  */
12108                 if (nested_exit_intr_ack_set(vcpu) &&
12109                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12110                     kvm_cpu_has_interrupt(vcpu)) {
12111                         int irq = kvm_cpu_get_interrupt(vcpu);
12112                         WARN_ON(irq < 0);
12113                         vmcs12->vm_exit_intr_info = irq |
12114                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12115                 }
12116
12117                 if (exit_reason != -1)
12118                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12119                                                        vmcs12->exit_qualification,
12120                                                        vmcs12->idt_vectoring_info_field,
12121                                                        vmcs12->vm_exit_intr_info,
12122                                                        vmcs12->vm_exit_intr_error_code,
12123                                                        KVM_ISA_VMX);
12124
12125                 load_vmcs12_host_state(vcpu, vmcs12);
12126
12127                 return;
12128         }
12129
12130         /*
12131          * After an early L2 VM-entry failure, we're now back
12132          * in L1 which thinks it just finished a VMLAUNCH or
12133          * VMRESUME instruction, so we need to set the failure
12134          * flag and the VM-instruction error field of the VMCS
12135          * accordingly.
12136          */
12137         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12138
12139         load_vmcs12_mmu_host_state(vcpu, vmcs12);
12140
12141         /*
12142          * The emulated instruction was already skipped in
12143          * nested_vmx_run, but the updated RIP was never
12144          * written back to the vmcs01.
12145          */
12146         skip_emulated_instruction(vcpu);
12147         vmx->fail = 0;
12148 }
12149
12150 /*
12151  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12152  */
12153 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12154 {
12155         if (is_guest_mode(vcpu)) {
12156                 to_vmx(vcpu)->nested.nested_run_pending = 0;
12157                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12158         }
12159         free_nested(to_vmx(vcpu));
12160 }
12161
12162 /*
12163  * L1's failure to enter L2 is a subset of a normal exit, as explained in
12164  * 23.7 "VM-entry failures during or after loading guest state" (this also
12165  * lists the acceptable exit-reason and exit-qualification parameters).
12166  * It should only be called before L2 actually succeeded to run, and when
12167  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12168  */
12169 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12170                         struct vmcs12 *vmcs12,
12171                         u32 reason, unsigned long qualification)
12172 {
12173         load_vmcs12_host_state(vcpu, vmcs12);
12174         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12175         vmcs12->exit_qualification = qualification;
12176         nested_vmx_succeed(vcpu);
12177         if (enable_shadow_vmcs)
12178                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12179 }
12180
12181 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12182                                struct x86_instruction_info *info,
12183                                enum x86_intercept_stage stage)
12184 {
12185         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12186         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12187
12188         /*
12189          * RDPID causes #UD if disabled through secondary execution controls.
12190          * Because it is marked as EmulateOnUD, we need to intercept it here.
12191          */
12192         if (info->intercept == x86_intercept_rdtscp &&
12193             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12194                 ctxt->exception.vector = UD_VECTOR;
12195                 ctxt->exception.error_code_valid = false;
12196                 return X86EMUL_PROPAGATE_FAULT;
12197         }
12198
12199         /* TODO: check more intercepts... */
12200         return X86EMUL_CONTINUE;
12201 }
12202
12203 #ifdef CONFIG_X86_64
12204 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12205 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12206                                   u64 divisor, u64 *result)
12207 {
12208         u64 low = a << shift, high = a >> (64 - shift);
12209
12210         /* To avoid the overflow on divq */
12211         if (high >= divisor)
12212                 return 1;
12213
12214         /* Low hold the result, high hold rem which is discarded */
12215         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12216             "rm" (divisor), "0" (low), "1" (high));
12217         *result = low;
12218
12219         return 0;
12220 }
12221
12222 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12223 {
12224         struct vcpu_vmx *vmx;
12225         u64 tscl, guest_tscl, delta_tsc;
12226
12227         if (kvm_mwait_in_guest(vcpu->kvm))
12228                 return -EOPNOTSUPP;
12229
12230         vmx = to_vmx(vcpu);
12231         tscl = rdtsc();
12232         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12233         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12234
12235         /* Convert to host delta tsc if tsc scaling is enabled */
12236         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12237                         u64_shl_div_u64(delta_tsc,
12238                                 kvm_tsc_scaling_ratio_frac_bits,
12239                                 vcpu->arch.tsc_scaling_ratio,
12240                                 &delta_tsc))
12241                 return -ERANGE;
12242
12243         /*
12244          * If the delta tsc can't fit in the 32 bit after the multi shift,
12245          * we can't use the preemption timer.
12246          * It's possible that it fits on later vmentries, but checking
12247          * on every vmentry is costly so we just use an hrtimer.
12248          */
12249         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12250                 return -ERANGE;
12251
12252         vmx->hv_deadline_tsc = tscl + delta_tsc;
12253         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12254                         PIN_BASED_VMX_PREEMPTION_TIMER);
12255
12256         return delta_tsc == 0;
12257 }
12258
12259 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12260 {
12261         struct vcpu_vmx *vmx = to_vmx(vcpu);
12262         vmx->hv_deadline_tsc = -1;
12263         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12264                         PIN_BASED_VMX_PREEMPTION_TIMER);
12265 }
12266 #endif
12267
12268 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12269 {
12270         if (!kvm_pause_in_guest(vcpu->kvm))
12271                 shrink_ple_window(vcpu);
12272 }
12273
12274 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12275                                      struct kvm_memory_slot *slot)
12276 {
12277         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12278         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12279 }
12280
12281 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12282                                        struct kvm_memory_slot *slot)
12283 {
12284         kvm_mmu_slot_set_dirty(kvm, slot);
12285 }
12286
12287 static void vmx_flush_log_dirty(struct kvm *kvm)
12288 {
12289         kvm_flush_pml_buffers(kvm);
12290 }
12291
12292 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
12293 {
12294         struct vmcs12 *vmcs12;
12295         struct vcpu_vmx *vmx = to_vmx(vcpu);
12296         gpa_t gpa;
12297         struct page *page = NULL;
12298         u64 *pml_address;
12299
12300         if (is_guest_mode(vcpu)) {
12301                 WARN_ON_ONCE(vmx->nested.pml_full);
12302
12303                 /*
12304                  * Check if PML is enabled for the nested guest.
12305                  * Whether eptp bit 6 is set is already checked
12306                  * as part of A/D emulation.
12307                  */
12308                 vmcs12 = get_vmcs12(vcpu);
12309                 if (!nested_cpu_has_pml(vmcs12))
12310                         return 0;
12311
12312                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12313                         vmx->nested.pml_full = true;
12314                         return 1;
12315                 }
12316
12317                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
12318
12319                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12320                 if (is_error_page(page))
12321                         return 0;
12322
12323                 pml_address = kmap(page);
12324                 pml_address[vmcs12->guest_pml_index--] = gpa;
12325                 kunmap(page);
12326                 kvm_release_page_clean(page);
12327         }
12328
12329         return 0;
12330 }
12331
12332 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12333                                            struct kvm_memory_slot *memslot,
12334                                            gfn_t offset, unsigned long mask)
12335 {
12336         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12337 }
12338
12339 static void __pi_post_block(struct kvm_vcpu *vcpu)
12340 {
12341         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12342         struct pi_desc old, new;
12343         unsigned int dest;
12344
12345         do {
12346                 old.control = new.control = pi_desc->control;
12347                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12348                      "Wakeup handler not enabled while the VCPU is blocked\n");
12349
12350                 dest = cpu_physical_id(vcpu->cpu);
12351
12352                 if (x2apic_enabled())
12353                         new.ndst = dest;
12354                 else
12355                         new.ndst = (dest << 8) & 0xFF00;
12356
12357                 /* set 'NV' to 'notification vector' */
12358                 new.nv = POSTED_INTR_VECTOR;
12359         } while (cmpxchg64(&pi_desc->control, old.control,
12360                            new.control) != old.control);
12361
12362         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12363                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12364                 list_del(&vcpu->blocked_vcpu_list);
12365                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12366                 vcpu->pre_pcpu = -1;
12367         }
12368 }
12369
12370 /*
12371  * This routine does the following things for vCPU which is going
12372  * to be blocked if VT-d PI is enabled.
12373  * - Store the vCPU to the wakeup list, so when interrupts happen
12374  *   we can find the right vCPU to wake up.
12375  * - Change the Posted-interrupt descriptor as below:
12376  *      'NDST' <-- vcpu->pre_pcpu
12377  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12378  * - If 'ON' is set during this process, which means at least one
12379  *   interrupt is posted for this vCPU, we cannot block it, in
12380  *   this case, return 1, otherwise, return 0.
12381  *
12382  */
12383 static int pi_pre_block(struct kvm_vcpu *vcpu)
12384 {
12385         unsigned int dest;
12386         struct pi_desc old, new;
12387         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12388
12389         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12390                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
12391                 !kvm_vcpu_apicv_active(vcpu))
12392                 return 0;
12393
12394         WARN_ON(irqs_disabled());
12395         local_irq_disable();
12396         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12397                 vcpu->pre_pcpu = vcpu->cpu;
12398                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12399                 list_add_tail(&vcpu->blocked_vcpu_list,
12400                               &per_cpu(blocked_vcpu_on_cpu,
12401                                        vcpu->pre_pcpu));
12402                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12403         }
12404
12405         do {
12406                 old.control = new.control = pi_desc->control;
12407
12408                 WARN((pi_desc->sn == 1),
12409                      "Warning: SN field of posted-interrupts "
12410                      "is set before blocking\n");
12411
12412                 /*
12413                  * Since vCPU can be preempted during this process,
12414                  * vcpu->cpu could be different with pre_pcpu, we
12415                  * need to set pre_pcpu as the destination of wakeup
12416                  * notification event, then we can find the right vCPU
12417                  * to wakeup in wakeup handler if interrupts happen
12418                  * when the vCPU is in blocked state.
12419                  */
12420                 dest = cpu_physical_id(vcpu->pre_pcpu);
12421
12422                 if (x2apic_enabled())
12423                         new.ndst = dest;
12424                 else
12425                         new.ndst = (dest << 8) & 0xFF00;
12426
12427                 /* set 'NV' to 'wakeup vector' */
12428                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12429         } while (cmpxchg64(&pi_desc->control, old.control,
12430                            new.control) != old.control);
12431
12432         /* We should not block the vCPU if an interrupt is posted for it.  */
12433         if (pi_test_on(pi_desc) == 1)
12434                 __pi_post_block(vcpu);
12435
12436         local_irq_enable();
12437         return (vcpu->pre_pcpu == -1);
12438 }
12439
12440 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12441 {
12442         if (pi_pre_block(vcpu))
12443                 return 1;
12444
12445         if (kvm_lapic_hv_timer_in_use(vcpu))
12446                 kvm_lapic_switch_to_sw_timer(vcpu);
12447
12448         return 0;
12449 }
12450
12451 static void pi_post_block(struct kvm_vcpu *vcpu)
12452 {
12453         if (vcpu->pre_pcpu == -1)
12454                 return;
12455
12456         WARN_ON(irqs_disabled());
12457         local_irq_disable();
12458         __pi_post_block(vcpu);
12459         local_irq_enable();
12460 }
12461
12462 static void vmx_post_block(struct kvm_vcpu *vcpu)
12463 {
12464         if (kvm_x86_ops->set_hv_timer)
12465                 kvm_lapic_switch_to_hv_timer(vcpu);
12466
12467         pi_post_block(vcpu);
12468 }
12469
12470 /*
12471  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12472  *
12473  * @kvm: kvm
12474  * @host_irq: host irq of the interrupt
12475  * @guest_irq: gsi of the interrupt
12476  * @set: set or unset PI
12477  * returns 0 on success, < 0 on failure
12478  */
12479 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12480                               uint32_t guest_irq, bool set)
12481 {
12482         struct kvm_kernel_irq_routing_entry *e;
12483         struct kvm_irq_routing_table *irq_rt;
12484         struct kvm_lapic_irq irq;
12485         struct kvm_vcpu *vcpu;
12486         struct vcpu_data vcpu_info;
12487         int idx, ret = 0;
12488
12489         if (!kvm_arch_has_assigned_device(kvm) ||
12490                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12491                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12492                 return 0;
12493
12494         idx = srcu_read_lock(&kvm->irq_srcu);
12495         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12496         if (guest_irq >= irq_rt->nr_rt_entries ||
12497             hlist_empty(&irq_rt->map[guest_irq])) {
12498                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12499                              guest_irq, irq_rt->nr_rt_entries);
12500                 goto out;
12501         }
12502
12503         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12504                 if (e->type != KVM_IRQ_ROUTING_MSI)
12505                         continue;
12506                 /*
12507                  * VT-d PI cannot support posting multicast/broadcast
12508                  * interrupts to a vCPU, we still use interrupt remapping
12509                  * for these kind of interrupts.
12510                  *
12511                  * For lowest-priority interrupts, we only support
12512                  * those with single CPU as the destination, e.g. user
12513                  * configures the interrupts via /proc/irq or uses
12514                  * irqbalance to make the interrupts single-CPU.
12515                  *
12516                  * We will support full lowest-priority interrupt later.
12517                  */
12518
12519                 kvm_set_msi_irq(kvm, e, &irq);
12520                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12521                         /*
12522                          * Make sure the IRTE is in remapped mode if
12523                          * we don't handle it in posted mode.
12524                          */
12525                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12526                         if (ret < 0) {
12527                                 printk(KERN_INFO
12528                                    "failed to back to remapped mode, irq: %u\n",
12529                                    host_irq);
12530                                 goto out;
12531                         }
12532
12533                         continue;
12534                 }
12535
12536                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12537                 vcpu_info.vector = irq.vector;
12538
12539                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12540                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12541
12542                 if (set)
12543                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12544                 else
12545                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12546
12547                 if (ret < 0) {
12548                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
12549                                         __func__);
12550                         goto out;
12551                 }
12552         }
12553
12554         ret = 0;
12555 out:
12556         srcu_read_unlock(&kvm->irq_srcu, idx);
12557         return ret;
12558 }
12559
12560 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12561 {
12562         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12563                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12564                         FEATURE_CONTROL_LMCE;
12565         else
12566                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12567                         ~FEATURE_CONTROL_LMCE;
12568 }
12569
12570 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12571 {
12572         /* we need a nested vmexit to enter SMM, postpone if run is pending */
12573         if (to_vmx(vcpu)->nested.nested_run_pending)
12574                 return 0;
12575         return 1;
12576 }
12577
12578 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12579 {
12580         struct vcpu_vmx *vmx = to_vmx(vcpu);
12581
12582         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12583         if (vmx->nested.smm.guest_mode)
12584                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12585
12586         vmx->nested.smm.vmxon = vmx->nested.vmxon;
12587         vmx->nested.vmxon = false;
12588         vmx_clear_hlt(vcpu);
12589         return 0;
12590 }
12591
12592 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12593 {
12594         struct vcpu_vmx *vmx = to_vmx(vcpu);
12595         int ret;
12596
12597         if (vmx->nested.smm.vmxon) {
12598                 vmx->nested.vmxon = true;
12599                 vmx->nested.smm.vmxon = false;
12600         }
12601
12602         if (vmx->nested.smm.guest_mode) {
12603                 vcpu->arch.hflags &= ~HF_SMM_MASK;
12604                 ret = enter_vmx_non_root_mode(vcpu, false);
12605                 vcpu->arch.hflags |= HF_SMM_MASK;
12606                 if (ret)
12607                         return ret;
12608
12609                 vmx->nested.smm.guest_mode = false;
12610         }
12611         return 0;
12612 }
12613
12614 static int enable_smi_window(struct kvm_vcpu *vcpu)
12615 {
12616         return 0;
12617 }
12618
12619 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12620         .cpu_has_kvm_support = cpu_has_kvm_support,
12621         .disabled_by_bios = vmx_disabled_by_bios,
12622         .hardware_setup = hardware_setup,
12623         .hardware_unsetup = hardware_unsetup,
12624         .check_processor_compatibility = vmx_check_processor_compat,
12625         .hardware_enable = hardware_enable,
12626         .hardware_disable = hardware_disable,
12627         .cpu_has_accelerated_tpr = report_flexpriority,
12628         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12629
12630         .vm_init = vmx_vm_init,
12631         .vm_alloc = vmx_vm_alloc,
12632         .vm_free = vmx_vm_free,
12633
12634         .vcpu_create = vmx_create_vcpu,
12635         .vcpu_free = vmx_free_vcpu,
12636         .vcpu_reset = vmx_vcpu_reset,
12637
12638         .prepare_guest_switch = vmx_save_host_state,
12639         .vcpu_load = vmx_vcpu_load,
12640         .vcpu_put = vmx_vcpu_put,
12641
12642         .update_bp_intercept = update_exception_bitmap,
12643         .get_msr_feature = vmx_get_msr_feature,
12644         .get_msr = vmx_get_msr,
12645         .set_msr = vmx_set_msr,
12646         .get_segment_base = vmx_get_segment_base,
12647         .get_segment = vmx_get_segment,
12648         .set_segment = vmx_set_segment,
12649         .get_cpl = vmx_get_cpl,
12650         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12651         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12652         .decache_cr3 = vmx_decache_cr3,
12653         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12654         .set_cr0 = vmx_set_cr0,
12655         .set_cr3 = vmx_set_cr3,
12656         .set_cr4 = vmx_set_cr4,
12657         .set_efer = vmx_set_efer,
12658         .get_idt = vmx_get_idt,
12659         .set_idt = vmx_set_idt,
12660         .get_gdt = vmx_get_gdt,
12661         .set_gdt = vmx_set_gdt,
12662         .get_dr6 = vmx_get_dr6,
12663         .set_dr6 = vmx_set_dr6,
12664         .set_dr7 = vmx_set_dr7,
12665         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12666         .cache_reg = vmx_cache_reg,
12667         .get_rflags = vmx_get_rflags,
12668         .set_rflags = vmx_set_rflags,
12669
12670         .tlb_flush = vmx_flush_tlb,
12671
12672         .run = vmx_vcpu_run,
12673         .handle_exit = vmx_handle_exit,
12674         .skip_emulated_instruction = skip_emulated_instruction,
12675         .set_interrupt_shadow = vmx_set_interrupt_shadow,
12676         .get_interrupt_shadow = vmx_get_interrupt_shadow,
12677         .patch_hypercall = vmx_patch_hypercall,
12678         .set_irq = vmx_inject_irq,
12679         .set_nmi = vmx_inject_nmi,
12680         .queue_exception = vmx_queue_exception,
12681         .cancel_injection = vmx_cancel_injection,
12682         .interrupt_allowed = vmx_interrupt_allowed,
12683         .nmi_allowed = vmx_nmi_allowed,
12684         .get_nmi_mask = vmx_get_nmi_mask,
12685         .set_nmi_mask = vmx_set_nmi_mask,
12686         .enable_nmi_window = enable_nmi_window,
12687         .enable_irq_window = enable_irq_window,
12688         .update_cr8_intercept = update_cr8_intercept,
12689         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12690         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12691         .get_enable_apicv = vmx_get_enable_apicv,
12692         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12693         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12694         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12695         .hwapic_irr_update = vmx_hwapic_irr_update,
12696         .hwapic_isr_update = vmx_hwapic_isr_update,
12697         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12698         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12699
12700         .set_tss_addr = vmx_set_tss_addr,
12701         .set_identity_map_addr = vmx_set_identity_map_addr,
12702         .get_tdp_level = get_ept_level,
12703         .get_mt_mask = vmx_get_mt_mask,
12704
12705         .get_exit_info = vmx_get_exit_info,
12706
12707         .get_lpage_level = vmx_get_lpage_level,
12708
12709         .cpuid_update = vmx_cpuid_update,
12710
12711         .rdtscp_supported = vmx_rdtscp_supported,
12712         .invpcid_supported = vmx_invpcid_supported,
12713
12714         .set_supported_cpuid = vmx_set_supported_cpuid,
12715
12716         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12717
12718         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
12719         .write_tsc_offset = vmx_write_tsc_offset,
12720
12721         .set_tdp_cr3 = vmx_set_cr3,
12722
12723         .check_intercept = vmx_check_intercept,
12724         .handle_external_intr = vmx_handle_external_intr,
12725         .mpx_supported = vmx_mpx_supported,
12726         .xsaves_supported = vmx_xsaves_supported,
12727         .umip_emulated = vmx_umip_emulated,
12728
12729         .check_nested_events = vmx_check_nested_events,
12730
12731         .sched_in = vmx_sched_in,
12732
12733         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12734         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12735         .flush_log_dirty = vmx_flush_log_dirty,
12736         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12737         .write_log_dirty = vmx_write_pml_buffer,
12738
12739         .pre_block = vmx_pre_block,
12740         .post_block = vmx_post_block,
12741
12742         .pmu_ops = &intel_pmu_ops,
12743
12744         .update_pi_irte = vmx_update_pi_irte,
12745
12746 #ifdef CONFIG_X86_64
12747         .set_hv_timer = vmx_set_hv_timer,
12748         .cancel_hv_timer = vmx_cancel_hv_timer,
12749 #endif
12750
12751         .setup_mce = vmx_setup_mce,
12752
12753         .smi_allowed = vmx_smi_allowed,
12754         .pre_enter_smm = vmx_pre_enter_smm,
12755         .pre_leave_smm = vmx_pre_leave_smm,
12756         .enable_smi_window = enable_smi_window,
12757 };
12758
12759 static int __init vmx_init(void)
12760 {
12761         int r;
12762
12763 #if IS_ENABLED(CONFIG_HYPERV)
12764         /*
12765          * Enlightened VMCS usage should be recommended and the host needs
12766          * to support eVMCS v1 or above. We can also disable eVMCS support
12767          * with module parameter.
12768          */
12769         if (enlightened_vmcs &&
12770             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
12771             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
12772             KVM_EVMCS_VERSION) {
12773                 int cpu;
12774
12775                 /* Check that we have assist pages on all online CPUs */
12776                 for_each_online_cpu(cpu) {
12777                         if (!hv_get_vp_assist_page(cpu)) {
12778                                 enlightened_vmcs = false;
12779                                 break;
12780                         }
12781                 }
12782
12783                 if (enlightened_vmcs) {
12784                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
12785                         static_branch_enable(&enable_evmcs);
12786                 }
12787         } else {
12788                 enlightened_vmcs = false;
12789         }
12790 #endif
12791
12792         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12793                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12794         if (r)
12795                 return r;
12796
12797 #ifdef CONFIG_KEXEC_CORE
12798         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12799                            crash_vmclear_local_loaded_vmcss);
12800 #endif
12801
12802         return 0;
12803 }
12804
12805 static void __exit vmx_exit(void)
12806 {
12807 #ifdef CONFIG_KEXEC_CORE
12808         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12809         synchronize_rcu();
12810 #endif
12811
12812         kvm_exit();
12813
12814 #if IS_ENABLED(CONFIG_HYPERV)
12815         if (static_branch_unlikely(&enable_evmcs)) {
12816                 int cpu;
12817                 struct hv_vp_assist_page *vp_ap;
12818                 /*
12819                  * Reset everything to support using non-enlightened VMCS
12820                  * access later (e.g. when we reload the module with
12821                  * enlightened_vmcs=0)
12822                  */
12823                 for_each_online_cpu(cpu) {
12824                         vp_ap = hv_get_vp_assist_page(cpu);
12825
12826                         if (!vp_ap)
12827                                 continue;
12828
12829                         vp_ap->current_nested_vmcs = 0;
12830                         vp_ap->enlighten_vmentry = 0;
12831                 }
12832
12833                 static_branch_disable(&enable_evmcs);
12834         }
12835 #endif
12836 }
12837
12838 module_init(vmx_init)
12839 module_exit(vmx_exit)