arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49
  50 #include "trace.h"
  51
  52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  53 #define __ex_clear(x, reg) \
  54         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  55
  56 MODULE_AUTHOR("Qumranet");
  57 MODULE_LICENSE("GPL");
  58
  59 static const struct x86_cpu_id vmx_cpu_id[] = {
  60         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  61         {}
  62 };
  63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  64
  65 static bool __read_mostly enable_vpid = 1;
  66 module_param_named(vpid, enable_vpid, bool, 0444);
  67
  68 static bool __read_mostly flexpriority_enabled = 1;
  69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_ept = 1;
  72 module_param_named(ept, enable_ept, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_unrestricted_guest = 1;
  75 module_param_named(unrestricted_guest,
  76                         enable_unrestricted_guest, bool, S_IRUGO);
  77
  78 static bool __read_mostly enable_ept_ad_bits = 1;
  79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  80
  81 static bool __read_mostly emulate_invalid_guest_state = true;
  82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  83
  84 static bool __read_mostly vmm_exclusive = 1;
  85 module_param(vmm_exclusive, bool, S_IRUGO);
  86
  87 static bool __read_mostly fasteoi = 1;
  88 module_param(fasteoi, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_apicv = 1;
  91 module_param(enable_apicv, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_shadow_vmcs = 1;
  94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  95 /*
  96  * If nested=1, nested virtualization is supported, i.e., guests may use
  97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  98  * use VMX instructions.
  99  */
 100 static bool __read_mostly nested = 0;
 101 module_param(nested, bool, S_IRUGO);
 102
 103 static u64 __read_mostly host_xss;
 104
 105 static bool __read_mostly enable_pml = 1;
 106 module_param_named(pml, enable_pml, bool, S_IRUGO);
 107
 108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 110 #define KVM_VM_CR0_ALWAYS_ON                                            \
 111         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 112 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 113         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 114          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 115
 116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 118
 119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 120
 121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 122
 123 /*
 124  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 125  * ple_gap:    upper bound on the amount of time between two successive
 126  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 127  *             According to test, this time is usually smaller than 128 cycles.
 128  * ple_window: upper bound on the amount of time a guest is allowed to execute
 129  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 130  *             less than 2^12 cycles
 131  * Time is measured based on a counter that runs at the same rate as the TSC,
 132  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 133  */
 134 #define KVM_VMX_DEFAULT_PLE_GAP           128
 135 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 139                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 140
 141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 142 module_param(ple_gap, int, S_IRUGO);
 143
 144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 145 module_param(ple_window, int, S_IRUGO);
 146
 147 /* Default doubles per-vcpu window every exit. */
 148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 149 module_param(ple_window_grow, int, S_IRUGO);
 150
 151 /* Default resets per-vcpu window every exit to ple_window. */
 152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 153 module_param(ple_window_shrink, int, S_IRUGO);
 154
 155 /* Default is to compute the maximum so we can never overflow. */
 156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 157 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 158 module_param(ple_window_max, int, S_IRUGO);
 159
 160 extern const ulong vmx_return;
 161
 162 #define NR_AUTOLOAD_MSRS 8
 163 #define VMCS02_POOL_SIZE 1
 164
 165 struct vmcs {
 166         u32 revision_id;
 167         u32 abort;
 168         char data[0];
 169 };
 170
 171 /*
 172  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 173  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 174  * loaded on this CPU (so we can clear them if the CPU goes down).
 175  */
 176 struct loaded_vmcs {
 177         struct vmcs *vmcs;
 178         int cpu;
 179         int launched;
 180         struct list_head loaded_vmcss_on_cpu_link;
 181 };
 182
 183 struct shared_msr_entry {
 184         unsigned index;
 185         u64 data;
 186         u64 mask;
 187 };
 188
 189 /*
 190  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 191  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 192  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 193  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 194  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 195  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 196  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 197  * underlying hardware which will be used to run L2.
 198  * This structure is packed to ensure that its layout is identical across
 199  * machines (necessary for live migration).
 200  * If there are changes in this struct, VMCS12_REVISION must be changed.
 201  */
 202 typedef u64 natural_width;
 203 struct __packed vmcs12 {
 204         /* According to the Intel spec, a VMCS region must start with the
 205          * following two fields. Then follow implementation-specific data.
 206          */
 207         u32 revision_id;
 208         u32 abort;
 209
 210         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 211         u32 padding[7]; /* room for future expansion */
 212
 213         u64 io_bitmap_a;
 214         u64 io_bitmap_b;
 215         u64 msr_bitmap;
 216         u64 vm_exit_msr_store_addr;
 217         u64 vm_exit_msr_load_addr;
 218         u64 vm_entry_msr_load_addr;
 219         u64 tsc_offset;
 220         u64 virtual_apic_page_addr;
 221         u64 apic_access_addr;
 222         u64 posted_intr_desc_addr;
 223         u64 ept_pointer;
 224         u64 eoi_exit_bitmap0;
 225         u64 eoi_exit_bitmap1;
 226         u64 eoi_exit_bitmap2;
 227         u64 eoi_exit_bitmap3;
 228         u64 xss_exit_bitmap;
 229         u64 guest_physical_address;
 230         u64 vmcs_link_pointer;
 231         u64 guest_ia32_debugctl;
 232         u64 guest_ia32_pat;
 233         u64 guest_ia32_efer;
 234         u64 guest_ia32_perf_global_ctrl;
 235         u64 guest_pdptr0;
 236         u64 guest_pdptr1;
 237         u64 guest_pdptr2;
 238         u64 guest_pdptr3;
 239         u64 guest_bndcfgs;
 240         u64 host_ia32_pat;
 241         u64 host_ia32_efer;
 242         u64 host_ia32_perf_global_ctrl;
 243         u64 padding64[8]; /* room for future expansion */
 244         /*
 245          * To allow migration of L1 (complete with its L2 guests) between
 246          * machines of different natural widths (32 or 64 bit), we cannot have
 247          * unsigned long fields with no explict size. We use u64 (aliased
 248          * natural_width) instead. Luckily, x86 is little-endian.
 249          */
 250         natural_width cr0_guest_host_mask;
 251         natural_width cr4_guest_host_mask;
 252         natural_width cr0_read_shadow;
 253         natural_width cr4_read_shadow;
 254         natural_width cr3_target_value0;
 255         natural_width cr3_target_value1;
 256         natural_width cr3_target_value2;
 257         natural_width cr3_target_value3;
 258         natural_width exit_qualification;
 259         natural_width guest_linear_address;
 260         natural_width guest_cr0;
 261         natural_width guest_cr3;
 262         natural_width guest_cr4;
 263         natural_width guest_es_base;
 264         natural_width guest_cs_base;
 265         natural_width guest_ss_base;
 266         natural_width guest_ds_base;
 267         natural_width guest_fs_base;
 268         natural_width guest_gs_base;
 269         natural_width guest_ldtr_base;
 270         natural_width guest_tr_base;
 271         natural_width guest_gdtr_base;
 272         natural_width guest_idtr_base;
 273         natural_width guest_dr7;
 274         natural_width guest_rsp;
 275         natural_width guest_rip;
 276         natural_width guest_rflags;
 277         natural_width guest_pending_dbg_exceptions;
 278         natural_width guest_sysenter_esp;
 279         natural_width guest_sysenter_eip;
 280         natural_width host_cr0;
 281         natural_width host_cr3;
 282         natural_width host_cr4;
 283         natural_width host_fs_base;
 284         natural_width host_gs_base;
 285         natural_width host_tr_base;
 286         natural_width host_gdtr_base;
 287         natural_width host_idtr_base;
 288         natural_width host_ia32_sysenter_esp;
 289         natural_width host_ia32_sysenter_eip;
 290         natural_width host_rsp;
 291         natural_width host_rip;
 292         natural_width paddingl[8]; /* room for future expansion */
 293         u32 pin_based_vm_exec_control;
 294         u32 cpu_based_vm_exec_control;
 295         u32 exception_bitmap;
 296         u32 page_fault_error_code_mask;
 297         u32 page_fault_error_code_match;
 298         u32 cr3_target_count;
 299         u32 vm_exit_controls;
 300         u32 vm_exit_msr_store_count;
 301         u32 vm_exit_msr_load_count;
 302         u32 vm_entry_controls;
 303         u32 vm_entry_msr_load_count;
 304         u32 vm_entry_intr_info_field;
 305         u32 vm_entry_exception_error_code;
 306         u32 vm_entry_instruction_len;
 307         u32 tpr_threshold;
 308         u32 secondary_vm_exec_control;
 309         u32 vm_instruction_error;
 310         u32 vm_exit_reason;
 311         u32 vm_exit_intr_info;
 312         u32 vm_exit_intr_error_code;
 313         u32 idt_vectoring_info_field;
 314         u32 idt_vectoring_error_code;
 315         u32 vm_exit_instruction_len;
 316         u32 vmx_instruction_info;
 317         u32 guest_es_limit;
 318         u32 guest_cs_limit;
 319         u32 guest_ss_limit;
 320         u32 guest_ds_limit;
 321         u32 guest_fs_limit;
 322         u32 guest_gs_limit;
 323         u32 guest_ldtr_limit;
 324         u32 guest_tr_limit;
 325         u32 guest_gdtr_limit;
 326         u32 guest_idtr_limit;
 327         u32 guest_es_ar_bytes;
 328         u32 guest_cs_ar_bytes;
 329         u32 guest_ss_ar_bytes;
 330         u32 guest_ds_ar_bytes;
 331         u32 guest_fs_ar_bytes;
 332         u32 guest_gs_ar_bytes;
 333         u32 guest_ldtr_ar_bytes;
 334         u32 guest_tr_ar_bytes;
 335         u32 guest_interruptibility_info;
 336         u32 guest_activity_state;
 337         u32 guest_sysenter_cs;
 338         u32 host_ia32_sysenter_cs;
 339         u32 vmx_preemption_timer_value;
 340         u32 padding32[7]; /* room for future expansion */
 341         u16 virtual_processor_id;
 342         u16 posted_intr_nv;
 343         u16 guest_es_selector;
 344         u16 guest_cs_selector;
 345         u16 guest_ss_selector;
 346         u16 guest_ds_selector;
 347         u16 guest_fs_selector;
 348         u16 guest_gs_selector;
 349         u16 guest_ldtr_selector;
 350         u16 guest_tr_selector;
 351         u16 guest_intr_status;
 352         u16 host_es_selector;
 353         u16 host_cs_selector;
 354         u16 host_ss_selector;
 355         u16 host_ds_selector;
 356         u16 host_fs_selector;
 357         u16 host_gs_selector;
 358         u16 host_tr_selector;
 359 };
 360
 361 /*
 362  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 363  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 364  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 365  */
 366 #define VMCS12_REVISION 0x11e57ed0
 367
 368 /*
 369  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 370  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 371  * current implementation, 4K are reserved to avoid future complications.
 372  */
 373 #define VMCS12_SIZE 0x1000
 374
 375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 376 struct vmcs02_list {
 377         struct list_head list;
 378         gpa_t vmptr;
 379         struct loaded_vmcs vmcs02;
 380 };
 381
 382 /*
 383  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 384  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 385  */
 386 struct nested_vmx {
 387         /* Has the level1 guest done vmxon? */
 388         bool vmxon;
 389         gpa_t vmxon_ptr;
 390
 391         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 392         gpa_t current_vmptr;
 393         /* The host-usable pointer to the above */
 394         struct page *current_vmcs12_page;
 395         struct vmcs12 *current_vmcs12;
 396         struct vmcs *current_shadow_vmcs;
 397         /*
 398          * Indicates if the shadow vmcs must be updated with the
 399          * data hold by vmcs12
 400          */
 401         bool sync_shadow_vmcs;
 402
 403         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 404         struct list_head vmcs02_pool;
 405         int vmcs02_num;
 406         u64 vmcs01_tsc_offset;
 407         /* L2 must run next, and mustn't decide to exit to L1. */
 408         bool nested_run_pending;
 409         /*
 410          * Guest pages referred to in vmcs02 with host-physical pointers, so
 411          * we must keep them pinned while L2 runs.
 412          */
 413         struct page *apic_access_page;
 414         struct page *virtual_apic_page;
 415         struct page *pi_desc_page;
 416         struct pi_desc *pi_desc;
 417         bool pi_pending;
 418         u16 posted_intr_nv;
 419         u64 msr_ia32_feature_control;
 420
 421         struct hrtimer preemption_timer;
 422         bool preemption_timer_expired;
 423
 424         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 425         u64 vmcs01_debugctl;
 426
 427         u32 nested_vmx_procbased_ctls_low;
 428         u32 nested_vmx_procbased_ctls_high;
 429         u32 nested_vmx_true_procbased_ctls_low;
 430         u32 nested_vmx_secondary_ctls_low;
 431         u32 nested_vmx_secondary_ctls_high;
 432         u32 nested_vmx_pinbased_ctls_low;
 433         u32 nested_vmx_pinbased_ctls_high;
 434         u32 nested_vmx_exit_ctls_low;
 435         u32 nested_vmx_exit_ctls_high;
 436         u32 nested_vmx_true_exit_ctls_low;
 437         u32 nested_vmx_entry_ctls_low;
 438         u32 nested_vmx_entry_ctls_high;
 439         u32 nested_vmx_true_entry_ctls_low;
 440         u32 nested_vmx_misc_low;
 441         u32 nested_vmx_misc_high;
 442         u32 nested_vmx_ept_caps;
 443 };
 444
 445 #define POSTED_INTR_ON  0
 446 /* Posted-Interrupt Descriptor */
 447 struct pi_desc {
 448         u32 pir[8];     /* Posted interrupt requested */
 449         u32 control;    /* bit 0 of control is outstanding notification bit */
 450         u32 rsvd[7];
 451 } __aligned(64);
 452
 453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 454 {
 455         return test_and_set_bit(POSTED_INTR_ON,
 456                         (unsigned long *)&pi_desc->control);
 457 }
 458
 459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 460 {
 461         return test_and_clear_bit(POSTED_INTR_ON,
 462                         (unsigned long *)&pi_desc->control);
 463 }
 464
 465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 466 {
 467         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 468 }
 469
 470 struct vcpu_vmx {
 471         struct kvm_vcpu       vcpu;
 472         unsigned long         host_rsp;
 473         u8                    fail;
 474         bool                  nmi_known_unmasked;
 475         u32                   exit_intr_info;
 476         u32                   idt_vectoring_info;
 477         ulong                 rflags;
 478         struct shared_msr_entry *guest_msrs;
 479         int                   nmsrs;
 480         int                   save_nmsrs;
 481         unsigned long         host_idt_base;
 482 #ifdef CONFIG_X86_64
 483         u64                   msr_host_kernel_gs_base;
 484         u64                   msr_guest_kernel_gs_base;
 485 #endif
 486         u32 vm_entry_controls_shadow;
 487         u32 vm_exit_controls_shadow;
 488         /*
 489          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 490          * non-nested (L1) guest, it always points to vmcs01. For a nested
 491          * guest (L2), it points to a different VMCS.
 492          */
 493         struct loaded_vmcs    vmcs01;
 494         struct loaded_vmcs   *loaded_vmcs;
 495         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 496         struct msr_autoload {
 497                 unsigned nr;
 498                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 499                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 500         } msr_autoload;
 501         struct {
 502                 int           loaded;
 503                 u16           fs_sel, gs_sel, ldt_sel;
 504 #ifdef CONFIG_X86_64
 505                 u16           ds_sel, es_sel;
 506 #endif
 507                 int           gs_ldt_reload_needed;
 508                 int           fs_reload_needed;
 509                 u64           msr_host_bndcfgs;
 510                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 511         } host_state;
 512         struct {
 513                 int vm86_active;
 514                 ulong save_rflags;
 515                 struct kvm_segment segs[8];
 516         } rmode;
 517         struct {
 518                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 519                 struct kvm_save_segment {
 520                         u16 selector;
 521                         unsigned long base;
 522                         u32 limit;
 523                         u32 ar;
 524                 } seg[8];
 525         } segment_cache;
 526         int vpid;
 527         bool emulation_required;
 528
 529         /* Support for vnmi-less CPUs */
 530         int soft_vnmi_blocked;
 531         ktime_t entry_time;
 532         s64 vnmi_blocked_time;
 533         u32 exit_reason;
 534
 535         bool rdtscp_enabled;
 536
 537         /* Posted interrupt descriptor */
 538         struct pi_desc pi_desc;
 539
 540         /* Support for a guest hypervisor (nested VMX) */
 541         struct nested_vmx nested;
 542
 543         /* Dynamic PLE window. */
 544         int ple_window;
 545         bool ple_window_dirty;
 546
 547         /* Support for PML */
 548 #define PML_ENTITY_NUM          512
 549         struct page *pml_pg;
 550 };
 551
 552 enum segment_cache_field {
 553         SEG_FIELD_SEL = 0,
 554         SEG_FIELD_BASE = 1,
 555         SEG_FIELD_LIMIT = 2,
 556         SEG_FIELD_AR = 3,
 557
 558         SEG_FIELD_NR = 4
 559 };
 560
 561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 562 {
 563         return container_of(vcpu, struct vcpu_vmx, vcpu);
 564 }
 565
 566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 567 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 568 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 569                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 570
 571
 572 static unsigned long shadow_read_only_fields[] = {
 573         /*
 574          * We do NOT shadow fields that are modified when L0
 575          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 576          * VMXON...) executed by L1.
 577          * For example, VM_INSTRUCTION_ERROR is read
 578          * by L1 if a vmx instruction fails (part of the error path).
 579          * Note the code assumes this logic. If for some reason
 580          * we start shadowing these fields then we need to
 581          * force a shadow sync when L0 emulates vmx instructions
 582          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 583          * by nested_vmx_failValid)
 584          */
 585         VM_EXIT_REASON,
 586         VM_EXIT_INTR_INFO,
 587         VM_EXIT_INSTRUCTION_LEN,
 588         IDT_VECTORING_INFO_FIELD,
 589         IDT_VECTORING_ERROR_CODE,
 590         VM_EXIT_INTR_ERROR_CODE,
 591         EXIT_QUALIFICATION,
 592         GUEST_LINEAR_ADDRESS,
 593         GUEST_PHYSICAL_ADDRESS
 594 };
 595 static int max_shadow_read_only_fields =
 596         ARRAY_SIZE(shadow_read_only_fields);
 597
 598 static unsigned long shadow_read_write_fields[] = {
 599         TPR_THRESHOLD,
 600         GUEST_RIP,
 601         GUEST_RSP,
 602         GUEST_CR0,
 603         GUEST_CR3,
 604         GUEST_CR4,
 605         GUEST_INTERRUPTIBILITY_INFO,
 606         GUEST_RFLAGS,
 607         GUEST_CS_SELECTOR,
 608         GUEST_CS_AR_BYTES,
 609         GUEST_CS_LIMIT,
 610         GUEST_CS_BASE,
 611         GUEST_ES_BASE,
 612         GUEST_BNDCFGS,
 613         CR0_GUEST_HOST_MASK,
 614         CR0_READ_SHADOW,
 615         CR4_READ_SHADOW,
 616         TSC_OFFSET,
 617         EXCEPTION_BITMAP,
 618         CPU_BASED_VM_EXEC_CONTROL,
 619         VM_ENTRY_EXCEPTION_ERROR_CODE,
 620         VM_ENTRY_INTR_INFO_FIELD,
 621         VM_ENTRY_INSTRUCTION_LEN,
 622         VM_ENTRY_EXCEPTION_ERROR_CODE,
 623         HOST_FS_BASE,
 624         HOST_GS_BASE,
 625         HOST_FS_SELECTOR,
 626         HOST_GS_SELECTOR
 627 };
 628 static int max_shadow_read_write_fields =
 629         ARRAY_SIZE(shadow_read_write_fields);
 630
 631 static const unsigned short vmcs_field_to_offset_table[] = {
 632         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 633         FIELD(POSTED_INTR_NV, posted_intr_nv),
 634         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 635         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 636         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 637         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 638         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 639         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 640         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 641         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 642         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 643         FIELD(HOST_ES_SELECTOR, host_es_selector),
 644         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 645         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 646         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 647         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 648         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 649         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 650         FIELD64(IO_BITMAP_A, io_bitmap_a),
 651         FIELD64(IO_BITMAP_B, io_bitmap_b),
 652         FIELD64(MSR_BITMAP, msr_bitmap),
 653         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 654         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 655         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 656         FIELD64(TSC_OFFSET, tsc_offset),
 657         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 658         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 659         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 660         FIELD64(EPT_POINTER, ept_pointer),
 661         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 662         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 663         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 664         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 665         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 666         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 667         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 668         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 669         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 670         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 671         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 672         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 673         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 674         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 675         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 676         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 677         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 678         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 679         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 680         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 681         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 682         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 683         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 684         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 685         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 686         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 687         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 688         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 689         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 690         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 691         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 692         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 693         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 694         FIELD(TPR_THRESHOLD, tpr_threshold),
 695         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 696         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 697         FIELD(VM_EXIT_REASON, vm_exit_reason),
 698         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 699         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 700         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 701         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 702         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 703         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 704         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 705         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 706         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 707         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 708         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 709         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 710         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 711         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 712         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 713         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 714         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 715         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 716         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 717         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 718         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 719         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 720         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 721         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 722         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 723         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 724         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 725         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 726         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 727         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 728         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 729         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 730         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 731         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 732         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 733         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 734         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 735         FIELD(EXIT_QUALIFICATION, exit_qualification),
 736         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 737         FIELD(GUEST_CR0, guest_cr0),
 738         FIELD(GUEST_CR3, guest_cr3),
 739         FIELD(GUEST_CR4, guest_cr4),
 740         FIELD(GUEST_ES_BASE, guest_es_base),
 741         FIELD(GUEST_CS_BASE, guest_cs_base),
 742         FIELD(GUEST_SS_BASE, guest_ss_base),
 743         FIELD(GUEST_DS_BASE, guest_ds_base),
 744         FIELD(GUEST_FS_BASE, guest_fs_base),
 745         FIELD(GUEST_GS_BASE, guest_gs_base),
 746         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 747         FIELD(GUEST_TR_BASE, guest_tr_base),
 748         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 749         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 750         FIELD(GUEST_DR7, guest_dr7),
 751         FIELD(GUEST_RSP, guest_rsp),
 752         FIELD(GUEST_RIP, guest_rip),
 753         FIELD(GUEST_RFLAGS, guest_rflags),
 754         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 755         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 756         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 757         FIELD(HOST_CR0, host_cr0),
 758         FIELD(HOST_CR3, host_cr3),
 759         FIELD(HOST_CR4, host_cr4),
 760         FIELD(HOST_FS_BASE, host_fs_base),
 761         FIELD(HOST_GS_BASE, host_gs_base),
 762         FIELD(HOST_TR_BASE, host_tr_base),
 763         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 764         FIELD(HOST_IDTR_BASE, host_idtr_base),
 765         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 766         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 767         FIELD(HOST_RSP, host_rsp),
 768         FIELD(HOST_RIP, host_rip),
 769 };
 770
 771 static inline short vmcs_field_to_offset(unsigned long field)
 772 {
 773         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 774
 775         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 776             vmcs_field_to_offset_table[field] == 0)
 777                 return -ENOENT;
 778
 779         return vmcs_field_to_offset_table[field];
 780 }
 781
 782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 783 {
 784         return to_vmx(vcpu)->nested.current_vmcs12;
 785 }
 786
 787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 788 {
 789         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 790         if (is_error_page(page))
 791                 return NULL;
 792
 793         return page;
 794 }
 795
 796 static void nested_release_page(struct page *page)
 797 {
 798         kvm_release_page_dirty(page);
 799 }
 800
 801 static void nested_release_page_clean(struct page *page)
 802 {
 803         kvm_release_page_clean(page);
 804 }
 805
 806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 807 static u64 construct_eptp(unsigned long root_hpa);
 808 static void kvm_cpu_vmxon(u64 addr);
 809 static void kvm_cpu_vmxoff(void);
 810 static bool vmx_mpx_supported(void);
 811 static bool vmx_xsaves_supported(void);
 812 static int vmx_vm_has_apicv(struct kvm *kvm);
 813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 815                             struct kvm_segment *var, int seg);
 816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 817                             struct kvm_segment *var, int seg);
 818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 823 static int alloc_identity_pagetable(struct kvm *kvm);
 824
 825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 827 /*
 828  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 829  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 830  */
 831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 833
 834 static unsigned long *vmx_io_bitmap_a;
 835 static unsigned long *vmx_io_bitmap_b;
 836 static unsigned long *vmx_msr_bitmap_legacy;
 837 static unsigned long *vmx_msr_bitmap_longmode;
 838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 840 static unsigned long *vmx_msr_bitmap_nested;
 841 static unsigned long *vmx_vmread_bitmap;
 842 static unsigned long *vmx_vmwrite_bitmap;
 843
 844 static bool cpu_has_load_ia32_efer;
 845 static bool cpu_has_load_perf_global_ctrl;
 846
 847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 848 static DEFINE_SPINLOCK(vmx_vpid_lock);
 849
 850 static struct vmcs_config {
 851         int size;
 852         int order;
 853         u32 revision_id;
 854         u32 pin_based_exec_ctrl;
 855         u32 cpu_based_exec_ctrl;
 856         u32 cpu_based_2nd_exec_ctrl;
 857         u32 vmexit_ctrl;
 858         u32 vmentry_ctrl;
 859 } vmcs_config;
 860
 861 static struct vmx_capability {
 862         u32 ept;
 863         u32 vpid;
 864 } vmx_capability;
 865
 866 #define VMX_SEGMENT_FIELD(seg)                                  \
 867         [VCPU_SREG_##seg] = {                                   \
 868                 .selector = GUEST_##seg##_SELECTOR,             \
 869                 .base = GUEST_##seg##_BASE,                     \
 870                 .limit = GUEST_##seg##_LIMIT,                   \
 871                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 872         }
 873
 874 static const struct kvm_vmx_segment_field {
 875         unsigned selector;
 876         unsigned base;
 877         unsigned limit;
 878         unsigned ar_bytes;
 879 } kvm_vmx_segment_fields[] = {
 880         VMX_SEGMENT_FIELD(CS),
 881         VMX_SEGMENT_FIELD(DS),
 882         VMX_SEGMENT_FIELD(ES),
 883         VMX_SEGMENT_FIELD(FS),
 884         VMX_SEGMENT_FIELD(GS),
 885         VMX_SEGMENT_FIELD(SS),
 886         VMX_SEGMENT_FIELD(TR),
 887         VMX_SEGMENT_FIELD(LDTR),
 888 };
 889
 890 static u64 host_efer;
 891
 892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 893
 894 /*
 895  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 896  * away by decrementing the array size.
 897  */
 898 static const u32 vmx_msr_index[] = {
 899 #ifdef CONFIG_X86_64
 900         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 901 #endif
 902         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 903 };
 904
 905 static inline bool is_page_fault(u32 intr_info)
 906 {
 907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 908                              INTR_INFO_VALID_MASK)) ==
 909                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 910 }
 911
 912 static inline bool is_no_device(u32 intr_info)
 913 {
 914         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 915                              INTR_INFO_VALID_MASK)) ==
 916                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 917 }
 918
 919 static inline bool is_invalid_opcode(u32 intr_info)
 920 {
 921         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 922                              INTR_INFO_VALID_MASK)) ==
 923                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 924 }
 925
 926 static inline bool is_external_interrupt(u32 intr_info)
 927 {
 928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 929                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 930 }
 931
 932 static inline bool is_machine_check(u32 intr_info)
 933 {
 934         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 935                              INTR_INFO_VALID_MASK)) ==
 936                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 937 }
 938
 939 static inline bool cpu_has_vmx_msr_bitmap(void)
 940 {
 941         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 942 }
 943
 944 static inline bool cpu_has_vmx_tpr_shadow(void)
 945 {
 946         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 947 }
 948
 949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 950 {
 951         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 952 }
 953
 954 static inline bool cpu_has_secondary_exec_ctrls(void)
 955 {
 956         return vmcs_config.cpu_based_exec_ctrl &
 957                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 958 }
 959
 960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 961 {
 962         return vmcs_config.cpu_based_2nd_exec_ctrl &
 963                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 964 }
 965
 966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 967 {
 968         return vmcs_config.cpu_based_2nd_exec_ctrl &
 969                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 970 }
 971
 972 static inline bool cpu_has_vmx_apic_register_virt(void)
 973 {
 974         return vmcs_config.cpu_based_2nd_exec_ctrl &
 975                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 976 }
 977
 978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 979 {
 980         return vmcs_config.cpu_based_2nd_exec_ctrl &
 981                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 982 }
 983
 984 static inline bool cpu_has_vmx_posted_intr(void)
 985 {
 986         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 987 }
 988
 989 static inline bool cpu_has_vmx_apicv(void)
 990 {
 991         return cpu_has_vmx_apic_register_virt() &&
 992                 cpu_has_vmx_virtual_intr_delivery() &&
 993                 cpu_has_vmx_posted_intr();
 994 }
 995
 996 static inline bool cpu_has_vmx_flexpriority(void)
 997 {
 998         return cpu_has_vmx_tpr_shadow() &&
 999                 cpu_has_vmx_virtualize_apic_accesses();
1000 }
1001
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 {
1004         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 {
1009         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1010 }
1011
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 {
1014         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1015 }
1016
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1018 {
1019         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020 }
1021
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 {
1024         return vmx_capability.ept & VMX_EPT_AD_BIT;
1025 }
1026
1027 static inline bool cpu_has_vmx_invept_context(void)
1028 {
1029         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1030 }
1031
1032 static inline bool cpu_has_vmx_invept_global(void)
1033 {
1034         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1035 }
1036
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1038 {
1039         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040 }
1041
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1043 {
1044         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045 }
1046
1047 static inline bool cpu_has_vmx_ept(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_ENABLE_EPT;
1051 }
1052
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057 }
1058
1059 static inline bool cpu_has_vmx_ple(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063 }
1064
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 {
1067         return flexpriority_enabled && irqchip_in_kernel(kvm);
1068 }
1069
1070 static inline bool cpu_has_vmx_vpid(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_ENABLE_VPID;
1074 }
1075
1076 static inline bool cpu_has_vmx_rdtscp(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_RDTSCP;
1080 }
1081
1082 static inline bool cpu_has_vmx_invpcid(void)
1083 {
1084         return vmcs_config.cpu_based_2nd_exec_ctrl &
1085                 SECONDARY_EXEC_ENABLE_INVPCID;
1086 }
1087
1088 static inline bool cpu_has_virtual_nmis(void)
1089 {
1090         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_WBINVD_EXITING;
1097 }
1098
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1100 {
1101         u64 vmx_msr;
1102         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103         /* check if the cpu supports writing r/o exit information fields */
1104         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105                 return false;
1106
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_SHADOW_VMCS;
1109 }
1110
1111 static inline bool cpu_has_vmx_pml(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114 }
1115
1116 static inline bool report_flexpriority(void)
1117 {
1118         return flexpriority_enabled;
1119 }
1120
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 {
1123         return vmcs12->cpu_based_vm_exec_control & bit;
1124 }
1125
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 {
1128         return (vmcs12->cpu_based_vm_exec_control &
1129                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130                 (vmcs12->secondary_vm_exec_control & bit);
1131 }
1132
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 {
1135         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136 }
1137
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 {
1140         return vmcs12->pin_based_vm_exec_control &
1141                 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 {
1146         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147 }
1148
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 {
1151         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152                 vmx_xsaves_supported();
1153 }
1154
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 {
1157         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158 }
1159
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 {
1162         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163 }
1164
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 {
1167         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168 }
1169
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 {
1172         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173 }
1174
1175 static inline bool is_exception(u32 intr_info)
1176 {
1177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179 }
1180
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182                               u32 exit_intr_info,
1183                               unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185                         struct vmcs12 *vmcs12,
1186                         u32 reason, unsigned long qualification);
1187
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1189 {
1190         int i;
1191
1192         for (i = 0; i < vmx->nmsrs; ++i)
1193                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1194                         return i;
1195         return -1;
1196 }
1197
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199 {
1200     struct {
1201         u64 vpid : 16;
1202         u64 rsvd : 48;
1203         u64 gva;
1204     } operand = { vpid, 0, gva };
1205
1206     asm volatile (__ex(ASM_VMX_INVVPID)
1207                   /* CF==1 or ZF==1 --> rc = -1 */
1208                   "; ja 1f ; ud2 ; 1:"
1209                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1210 }
1211
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213 {
1214         struct {
1215                 u64 eptp, gpa;
1216         } operand = {eptp, gpa};
1217
1218         asm volatile (__ex(ASM_VMX_INVEPT)
1219                         /* CF==1 or ZF==1 --> rc = -1 */
1220                         "; ja 1f ; ud2 ; 1:\n"
1221                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1222 }
1223
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1225 {
1226         int i;
1227
1228         i = __find_msr_index(vmx, msr);
1229         if (i >= 0)
1230                 return &vmx->guest_msrs[i];
1231         return NULL;
1232 }
1233
1234 static void vmcs_clear(struct vmcs *vmcs)
1235 {
1236         u64 phys_addr = __pa(vmcs);
1237         u8 error;
1238
1239         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1241                       : "cc", "memory");
1242         if (error)
1243                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244                        vmcs, phys_addr);
1245 }
1246
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 {
1249         vmcs_clear(loaded_vmcs->vmcs);
1250         loaded_vmcs->cpu = -1;
1251         loaded_vmcs->launched = 0;
1252 }
1253
1254 static void vmcs_load(struct vmcs *vmcs)
1255 {
1256         u64 phys_addr = __pa(vmcs);
1257         u8 error;
1258
1259         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1261                         : "cc", "memory");
1262         if (error)
1263                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1264                        vmcs, phys_addr);
1265 }
1266
1267 #ifdef CONFIG_KEXEC
1268 /*
1269  * This bitmap is used to indicate whether the vmclear
1270  * operation is enabled on all cpus. All disabled by
1271  * default.
1272  */
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275 static inline void crash_enable_local_vmclear(int cpu)
1276 {
1277         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278 }
1279
1280 static inline void crash_disable_local_vmclear(int cpu)
1281 {
1282         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283 }
1284
1285 static inline int crash_local_vmclear_enabled(int cpu)
1286 {
1287         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288 }
1289
1290 static void crash_vmclear_local_loaded_vmcss(void)
1291 {
1292         int cpu = raw_smp_processor_id();
1293         struct loaded_vmcs *v;
1294
1295         if (!crash_local_vmclear_enabled(cpu))
1296                 return;
1297
1298         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299                             loaded_vmcss_on_cpu_link)
1300                 vmcs_clear(v->vmcs);
1301 }
1302 #else
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1306
1307 static void __loaded_vmcs_clear(void *arg)
1308 {
1309         struct loaded_vmcs *loaded_vmcs = arg;
1310         int cpu = raw_smp_processor_id();
1311
1312         if (loaded_vmcs->cpu != cpu)
1313                 return; /* vcpu migration can race with cpu offline */
1314         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315                 per_cpu(current_vmcs, cpu) = NULL;
1316         crash_disable_local_vmclear(cpu);
1317         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1318
1319         /*
1320          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321          * is before setting loaded_vmcs->vcpu to -1 which is done in
1322          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323          * then adds the vmcs into percpu list before it is deleted.
1324          */
1325         smp_wmb();
1326
1327         loaded_vmcs_init(loaded_vmcs);
1328         crash_enable_local_vmclear(cpu);
1329 }
1330
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         int cpu = loaded_vmcs->cpu;
1334
1335         if (cpu != -1)
1336                 smp_call_function_single(cpu,
1337                          __loaded_vmcs_clear, loaded_vmcs, 1);
1338 }
1339
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1341 {
1342         if (vmx->vpid == 0)
1343                 return;
1344
1345         if (cpu_has_vmx_invvpid_single())
1346                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1347 }
1348
1349 static inline void vpid_sync_vcpu_global(void)
1350 {
1351         if (cpu_has_vmx_invvpid_global())
1352                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353 }
1354
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 {
1357         if (cpu_has_vmx_invvpid_single())
1358                 vpid_sync_vcpu_single(vmx);
1359         else
1360                 vpid_sync_vcpu_global();
1361 }
1362
1363 static inline void ept_sync_global(void)
1364 {
1365         if (cpu_has_vmx_invept_global())
1366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367 }
1368
1369 static inline void ept_sync_context(u64 eptp)
1370 {
1371         if (enable_ept) {
1372                 if (cpu_has_vmx_invept_context())
1373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374                 else
1375                         ept_sync_global();
1376         }
1377 }
1378
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 {
1381         unsigned long value;
1382
1383         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384                       : "=a"(value) : "d"(field) : "cc");
1385         return value;
1386 }
1387
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1389 {
1390         return vmcs_readl(field);
1391 }
1392
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1394 {
1395         return vmcs_readl(field);
1396 }
1397
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1399 {
1400 #ifdef CONFIG_X86_64
1401         return vmcs_readl(field);
1402 #else
1403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404 #endif
1405 }
1406
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 {
1409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411         dump_stack();
1412 }
1413
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1415 {
1416         u8 error;
1417
1418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1420         if (unlikely(error))
1421                 vmwrite_error(field, value);
1422 }
1423
1424 static void vmcs_write16(unsigned long field, u16 value)
1425 {
1426         vmcs_writel(field, value);
1427 }
1428
1429 static void vmcs_write32(unsigned long field, u32 value)
1430 {
1431         vmcs_writel(field, value);
1432 }
1433
1434 static void vmcs_write64(unsigned long field, u64 value)
1435 {
1436         vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1438         asm volatile ("");
1439         vmcs_writel(field+1, value >> 32);
1440 #endif
1441 }
1442
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 {
1445         vmcs_writel(field, vmcs_readl(field) & ~mask);
1446 }
1447
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 {
1450         vmcs_writel(field, vmcs_readl(field) | mask);
1451 }
1452
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 {
1455         vmcs_write32(VM_ENTRY_CONTROLS, val);
1456         vmx->vm_entry_controls_shadow = val;
1457 }
1458
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 {
1461         if (vmx->vm_entry_controls_shadow != val)
1462                 vm_entry_controls_init(vmx, val);
1463 }
1464
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 {
1467         return vmx->vm_entry_controls_shadow;
1468 }
1469
1470
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 {
1473         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474 }
1475
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 {
1478         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479 }
1480
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 {
1483         vmcs_write32(VM_EXIT_CONTROLS, val);
1484         vmx->vm_exit_controls_shadow = val;
1485 }
1486
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 {
1489         if (vmx->vm_exit_controls_shadow != val)
1490                 vm_exit_controls_init(vmx, val);
1491 }
1492
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 {
1495         return vmx->vm_exit_controls_shadow;
1496 }
1497
1498
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 {
1501         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502 }
1503
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 {
1506         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507 }
1508
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 {
1511         vmx->segment_cache.bitmask = 0;
1512 }
1513
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515                                        unsigned field)
1516 {
1517         bool ret;
1518         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522                 vmx->segment_cache.bitmask = 0;
1523         }
1524         ret = vmx->segment_cache.bitmask & mask;
1525         vmx->segment_cache.bitmask |= mask;
1526         return ret;
1527 }
1528
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 {
1531         u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535         return *p;
1536 }
1537
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 {
1540         ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544         return *p;
1545 }
1546
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 {
1549         u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553         return *p;
1554 }
1555
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 {
1558         u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562         return *p;
1563 }
1564
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566 {
1567         u32 eb;
1568
1569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571         if ((vcpu->guest_debug &
1572              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574                 eb |= 1u << BP_VECTOR;
1575         if (to_vmx(vcpu)->rmode.vm86_active)
1576                 eb = ~0;
1577         if (enable_ept)
1578                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579         if (vcpu->fpu_active)
1580                 eb &= ~(1u << NM_VECTOR);
1581
1582         /* When we are running a nested L2 guest and L1 specified for it a
1583          * certain exception bitmap, we must trap the same exceptions and pass
1584          * them to L1. When running L2, we will only handle the exceptions
1585          * specified above if L1 did not want them.
1586          */
1587         if (is_guest_mode(vcpu))
1588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
1590         vmcs_write32(EXCEPTION_BITMAP, eb);
1591 }
1592
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594                 unsigned long entry, unsigned long exit)
1595 {
1596         vm_entry_controls_clearbit(vmx, entry);
1597         vm_exit_controls_clearbit(vmx, exit);
1598 }
1599
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601 {
1602         unsigned i;
1603         struct msr_autoload *m = &vmx->msr_autoload;
1604
1605         switch (msr) {
1606         case MSR_EFER:
1607                 if (cpu_has_load_ia32_efer) {
1608                         clear_atomic_switch_msr_special(vmx,
1609                                         VM_ENTRY_LOAD_IA32_EFER,
1610                                         VM_EXIT_LOAD_IA32_EFER);
1611                         return;
1612                 }
1613                 break;
1614         case MSR_CORE_PERF_GLOBAL_CTRL:
1615                 if (cpu_has_load_perf_global_ctrl) {
1616                         clear_atomic_switch_msr_special(vmx,
1617                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619                         return;
1620                 }
1621                 break;
1622         }
1623
1624         for (i = 0; i < m->nr; ++i)
1625                 if (m->guest[i].index == msr)
1626                         break;
1627
1628         if (i == m->nr)
1629                 return;
1630         --m->nr;
1631         m->guest[i] = m->guest[m->nr];
1632         m->host[i] = m->host[m->nr];
1633         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635 }
1636
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638                 unsigned long entry, unsigned long exit,
1639                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640                 u64 guest_val, u64 host_val)
1641 {
1642         vmcs_write64(guest_val_vmcs, guest_val);
1643         vmcs_write64(host_val_vmcs, host_val);
1644         vm_entry_controls_setbit(vmx, entry);
1645         vm_exit_controls_setbit(vmx, exit);
1646 }
1647
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649                                   u64 guest_val, u64 host_val)
1650 {
1651         unsigned i;
1652         struct msr_autoload *m = &vmx->msr_autoload;
1653
1654         switch (msr) {
1655         case MSR_EFER:
1656                 if (cpu_has_load_ia32_efer) {
1657                         add_atomic_switch_msr_special(vmx,
1658                                         VM_ENTRY_LOAD_IA32_EFER,
1659                                         VM_EXIT_LOAD_IA32_EFER,
1660                                         GUEST_IA32_EFER,
1661                                         HOST_IA32_EFER,
1662                                         guest_val, host_val);
1663                         return;
1664                 }
1665                 break;
1666         case MSR_CORE_PERF_GLOBAL_CTRL:
1667                 if (cpu_has_load_perf_global_ctrl) {
1668                         add_atomic_switch_msr_special(vmx,
1669                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1672                                         HOST_IA32_PERF_GLOBAL_CTRL,
1673                                         guest_val, host_val);
1674                         return;
1675                 }
1676                 break;
1677         }
1678
1679         for (i = 0; i < m->nr; ++i)
1680                 if (m->guest[i].index == msr)
1681                         break;
1682
1683         if (i == NR_AUTOLOAD_MSRS) {
1684                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685                                 "Can't add msr %x\n", msr);
1686                 return;
1687         } else if (i == m->nr) {
1688                 ++m->nr;
1689                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691         }
1692
1693         m->guest[i].index = msr;
1694         m->guest[i].value = guest_val;
1695         m->host[i].index = msr;
1696         m->host[i].value = host_val;
1697 }
1698
1699 static void reload_tss(void)
1700 {
1701         /*
1702          * VT restores TR but not its size.  Useless.
1703          */
1704         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705         struct desc_struct *descs;
1706
1707         descs = (void *)gdt->address;
1708         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709         load_TR_desc();
1710 }
1711
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1713 {
1714         u64 guest_efer;
1715         u64 ignore_bits;
1716
1717         guest_efer = vmx->vcpu.arch.efer;
1718
1719         /*
1720          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1721          * outside long mode
1722          */
1723         ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725         ignore_bits |= EFER_LMA | EFER_LME;
1726         /* SCE is meaningful only in long mode on Intel */
1727         if (guest_efer & EFER_LMA)
1728                 ignore_bits &= ~(u64)EFER_SCE;
1729 #endif
1730         guest_efer &= ~ignore_bits;
1731         guest_efer |= host_efer & ignore_bits;
1732         vmx->guest_msrs[efer_offset].data = guest_efer;
1733         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734
1735         clear_atomic_switch_msr(vmx, MSR_EFER);
1736
1737         /*
1738          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739          * On CPUs that support "load IA32_EFER", always switch EFER
1740          * atomically, since it's faster than switching it manually.
1741          */
1742         if (cpu_has_load_ia32_efer ||
1743             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744                 guest_efer = vmx->vcpu.arch.efer;
1745                 if (!(guest_efer & EFER_LMA))
1746                         guest_efer &= ~EFER_LME;
1747                 if (guest_efer != host_efer)
1748                         add_atomic_switch_msr(vmx, MSR_EFER,
1749                                               guest_efer, host_efer);
1750                 return false;
1751         }
1752
1753         return true;
1754 }
1755
1756 static unsigned long segment_base(u16 selector)
1757 {
1758         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759         struct desc_struct *d;
1760         unsigned long table_base;
1761         unsigned long v;
1762
1763         if (!(selector & ~3))
1764                 return 0;
1765
1766         table_base = gdt->address;
1767
1768         if (selector & 4) {           /* from ldt */
1769                 u16 ldt_selector = kvm_read_ldt();
1770
1771                 if (!(ldt_selector & ~3))
1772                         return 0;
1773
1774                 table_base = segment_base(ldt_selector);
1775         }
1776         d = (struct desc_struct *)(table_base + (selector & ~7));
1777         v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781 #endif
1782         return v;
1783 }
1784
1785 static inline unsigned long kvm_read_tr_base(void)
1786 {
1787         u16 tr;
1788         asm("str %0" : "=g"(tr));
1789         return segment_base(tr);
1790 }
1791
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         int i;
1796
1797         if (vmx->host_state.loaded)
1798                 return;
1799
1800         vmx->host_state.loaded = 1;
1801         /*
1802          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1803          * allow segment selectors with cpl > 0 or ti == 1.
1804          */
1805         vmx->host_state.ldt_sel = kvm_read_ldt();
1806         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807         savesegment(fs, vmx->host_state.fs_sel);
1808         if (!(vmx->host_state.fs_sel & 7)) {
1809                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810                 vmx->host_state.fs_reload_needed = 0;
1811         } else {
1812                 vmcs_write16(HOST_FS_SELECTOR, 0);
1813                 vmx->host_state.fs_reload_needed = 1;
1814         }
1815         savesegment(gs, vmx->host_state.gs_sel);
1816         if (!(vmx->host_state.gs_sel & 7))
1817                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818         else {
1819                 vmcs_write16(HOST_GS_SELECTOR, 0);
1820                 vmx->host_state.gs_ldt_reload_needed = 1;
1821         }
1822
1823 #ifdef CONFIG_X86_64
1824         savesegment(ds, vmx->host_state.ds_sel);
1825         savesegment(es, vmx->host_state.es_sel);
1826 #endif
1827
1828 #ifdef CONFIG_X86_64
1829         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 #else
1832         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1834 #endif
1835
1836 #ifdef CONFIG_X86_64
1837         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838         if (is_long_mode(&vmx->vcpu))
1839                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 #endif
1841         if (boot_cpu_has(X86_FEATURE_MPX))
1842                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843         for (i = 0; i < vmx->save_nmsrs; ++i)
1844                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845                                    vmx->guest_msrs[i].data,
1846                                    vmx->guest_msrs[i].mask);
1847 }
1848
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 {
1851         if (!vmx->host_state.loaded)
1852                 return;
1853
1854         ++vmx->vcpu.stat.host_state_reload;
1855         vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857         if (is_long_mode(&vmx->vcpu))
1858                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 #endif
1860         if (vmx->host_state.gs_ldt_reload_needed) {
1861                 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863                 load_gs_index(vmx->host_state.gs_sel);
1864 #else
1865                 loadsegment(gs, vmx->host_state.gs_sel);
1866 #endif
1867         }
1868         if (vmx->host_state.fs_reload_needed)
1869                 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872                 loadsegment(ds, vmx->host_state.ds_sel);
1873                 loadsegment(es, vmx->host_state.es_sel);
1874         }
1875 #endif
1876         reload_tss();
1877 #ifdef CONFIG_X86_64
1878         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 #endif
1880         if (vmx->host_state.msr_host_bndcfgs)
1881                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882         /*
1883          * If the FPU is not active (through the host task or
1884          * the guest vcpu), then restore the cr0.TS bit.
1885          */
1886         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887                 stts();
1888         load_gdt(this_cpu_ptr(&host_gdt));
1889 }
1890
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892 {
1893         preempt_disable();
1894         __vmx_load_host_state(vmx);
1895         preempt_enable();
1896 }
1897
1898 /*
1899  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900  * vcpu mutex is already taken.
1901  */
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 {
1904         struct vcpu_vmx *vmx = to_vmx(vcpu);
1905         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1906
1907         if (!vmm_exclusive)
1908                 kvm_cpu_vmxon(phys_addr);
1909         else if (vmx->loaded_vmcs->cpu != cpu)
1910                 loaded_vmcs_clear(vmx->loaded_vmcs);
1911
1912         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914                 vmcs_load(vmx->loaded_vmcs->vmcs);
1915         }
1916
1917         if (vmx->loaded_vmcs->cpu != cpu) {
1918                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919                 unsigned long sysenter_esp;
1920
1921                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922                 local_irq_disable();
1923                 crash_disable_local_vmclear(cpu);
1924
1925                 /*
1926                  * Read loaded_vmcs->cpu should be before fetching
1927                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928                  * See the comments in __loaded_vmcs_clear().
1929                  */
1930                 smp_rmb();
1931
1932                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1934                 crash_enable_local_vmclear(cpu);
1935                 local_irq_enable();
1936
1937                 /*
1938                  * Linux uses per-cpu TSS and GDT, so set these when switching
1939                  * processors.
1940                  */
1941                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1943
1944                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946                 vmx->loaded_vmcs->cpu = cpu;
1947         }
1948 }
1949
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 {
1952         __vmx_load_host_state(to_vmx(vcpu));
1953         if (!vmm_exclusive) {
1954                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955                 vcpu->cpu = -1;
1956                 kvm_cpu_vmxoff();
1957         }
1958 }
1959
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961 {
1962         ulong cr0;
1963
1964         if (vcpu->fpu_active)
1965                 return;
1966         vcpu->fpu_active = 1;
1967         cr0 = vmcs_readl(GUEST_CR0);
1968         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970         vmcs_writel(GUEST_CR0, cr0);
1971         update_exception_bitmap(vcpu);
1972         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973         if (is_guest_mode(vcpu))
1974                 vcpu->arch.cr0_guest_owned_bits &=
1975                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1977 }
1978
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
1981 /*
1982  * Return the cr0 value that a nested guest would read. This is a combination
1983  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984  * its hypervisor (cr0_read_shadow).
1985  */
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 {
1988         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 }
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 {
1993         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995 }
1996
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 {
1999         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000          * set this *before* calling this function.
2001          */
2002         vmx_decache_cr0_guest_bits(vcpu);
2003         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004         update_exception_bitmap(vcpu);
2005         vcpu->arch.cr0_guest_owned_bits = 0;
2006         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007         if (is_guest_mode(vcpu)) {
2008                 /*
2009                  * L1's specified read shadow might not contain the TS bit,
2010                  * so now that we turned on shadowing of this bit, we need to
2011                  * set this bit of the shadow. Like in nested_vmx_run we need
2012                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013                  * up-to-date here because we just decached cr0.TS (and we'll
2014                  * only update vmcs12->guest_cr0 on nested exit).
2015                  */
2016                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018                         (vcpu->arch.cr0 & X86_CR0_TS);
2019                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020         } else
2021                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2022 }
2023
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 {
2026         unsigned long rflags, save_rflags;
2027
2028         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030                 rflags = vmcs_readl(GUEST_RFLAGS);
2031                 if (to_vmx(vcpu)->rmode.vm86_active) {
2032                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035                 }
2036                 to_vmx(vcpu)->rflags = rflags;
2037         }
2038         return to_vmx(vcpu)->rflags;
2039 }
2040
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 {
2043         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044         to_vmx(vcpu)->rflags = rflags;
2045         if (to_vmx(vcpu)->rmode.vm86_active) {
2046                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048         }
2049         vmcs_writel(GUEST_RFLAGS, rflags);
2050 }
2051
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 {
2054         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055         int ret = 0;
2056
2057         if (interruptibility & GUEST_INTR_STATE_STI)
2058                 ret |= KVM_X86_SHADOW_INT_STI;
2059         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2061
2062         return ret;
2063 }
2064
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 {
2067         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068         u32 interruptibility = interruptibility_old;
2069
2070         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
2072         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074         else if (mask & KVM_X86_SHADOW_INT_STI)
2075                 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077         if ((interruptibility != interruptibility_old))
2078                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079 }
2080
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long rip;
2084
2085         rip = kvm_rip_read(vcpu);
2086         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087         kvm_rip_write(vcpu, rip);
2088
2089         /* skipping an emulated instruction also counts */
2090         vmx_set_interrupt_shadow(vcpu, 0);
2091 }
2092
2093 /*
2094  * KVM wants to inject page-faults which it got to the guest. This function
2095  * checks whether in a nested guest, we need to inject them to L1 or L2.
2096  */
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 {
2099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
2101         if (!(vmcs12->exception_bitmap & (1u << nr)))
2102                 return 0;
2103
2104         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105                           vmcs_read32(VM_EXIT_INTR_INFO),
2106                           vmcs_readl(EXIT_QUALIFICATION));
2107         return 1;
2108 }
2109
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111                                 bool has_error_code, u32 error_code,
2112                                 bool reinject)
2113 {
2114         struct vcpu_vmx *vmx = to_vmx(vcpu);
2115         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116
2117         if (!reinject && is_guest_mode(vcpu) &&
2118             nested_vmx_check_exception(vcpu, nr))
2119                 return;
2120
2121         if (has_error_code) {
2122                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124         }
2125
2126         if (vmx->rmode.vm86_active) {
2127                 int inc_eip = 0;
2128                 if (kvm_exception_is_soft(nr))
2129                         inc_eip = vcpu->arch.event_exit_inst_len;
2130                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2132                 return;
2133         }
2134
2135         if (kvm_exception_is_soft(nr)) {
2136                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137                              vmx->vcpu.arch.event_exit_inst_len);
2138                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139         } else
2140                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2143 }
2144
2145 static bool vmx_rdtscp_supported(void)
2146 {
2147         return cpu_has_vmx_rdtscp();
2148 }
2149
2150 static bool vmx_invpcid_supported(void)
2151 {
2152         return cpu_has_vmx_invpcid() && enable_ept;
2153 }
2154
2155 /*
2156  * Swap MSR entry in host/guest MSR entry array.
2157  */
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 {
2160         struct shared_msr_entry tmp;
2161
2162         tmp = vmx->guest_msrs[to];
2163         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164         vmx->guest_msrs[from] = tmp;
2165 }
2166
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 {
2169         unsigned long *msr_bitmap;
2170
2171         if (is_guest_mode(vcpu))
2172                 msr_bitmap = vmx_msr_bitmap_nested;
2173         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2174                 if (is_long_mode(vcpu))
2175                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2176                 else
2177                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2178         } else {
2179                 if (is_long_mode(vcpu))
2180                         msr_bitmap = vmx_msr_bitmap_longmode;
2181                 else
2182                         msr_bitmap = vmx_msr_bitmap_legacy;
2183         }
2184
2185         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2186 }
2187
2188 /*
2189  * Set up the vmcs to automatically save and restore system
2190  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2191  * mode, as fiddling with msrs is very expensive.
2192  */
2193 static void setup_msrs(struct vcpu_vmx *vmx)
2194 {
2195         int save_nmsrs, index;
2196
2197         save_nmsrs = 0;
2198 #ifdef CONFIG_X86_64
2199         if (is_long_mode(&vmx->vcpu)) {
2200                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2201                 if (index >= 0)
2202                         move_msr_up(vmx, index, save_nmsrs++);
2203                 index = __find_msr_index(vmx, MSR_LSTAR);
2204                 if (index >= 0)
2205                         move_msr_up(vmx, index, save_nmsrs++);
2206                 index = __find_msr_index(vmx, MSR_CSTAR);
2207                 if (index >= 0)
2208                         move_msr_up(vmx, index, save_nmsrs++);
2209                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2210                 if (index >= 0 && vmx->rdtscp_enabled)
2211                         move_msr_up(vmx, index, save_nmsrs++);
2212                 /*
2213                  * MSR_STAR is only needed on long mode guests, and only
2214                  * if efer.sce is enabled.
2215                  */
2216                 index = __find_msr_index(vmx, MSR_STAR);
2217                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2218                         move_msr_up(vmx, index, save_nmsrs++);
2219         }
2220 #endif
2221         index = __find_msr_index(vmx, MSR_EFER);
2222         if (index >= 0 && update_transition_efer(vmx, index))
2223                 move_msr_up(vmx, index, save_nmsrs++);
2224
2225         vmx->save_nmsrs = save_nmsrs;
2226
2227         if (cpu_has_vmx_msr_bitmap())
2228                 vmx_set_msr_bitmap(&vmx->vcpu);
2229 }
2230
2231 /*
2232  * reads and returns guest's timestamp counter "register"
2233  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2234  */
2235 static u64 guest_read_tsc(void)
2236 {
2237         u64 host_tsc, tsc_offset;
2238
2239         rdtscll(host_tsc);
2240         tsc_offset = vmcs_read64(TSC_OFFSET);
2241         return host_tsc + tsc_offset;
2242 }
2243
2244 /*
2245  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2246  * counter, even if a nested guest (L2) is currently running.
2247  */
2248 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2249 {
2250         u64 tsc_offset;
2251
2252         tsc_offset = is_guest_mode(vcpu) ?
2253                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2254                 vmcs_read64(TSC_OFFSET);
2255         return host_tsc + tsc_offset;
2256 }
2257
2258 /*
2259  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2260  * software catchup for faster rates on slower CPUs.
2261  */
2262 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2263 {
2264         if (!scale)
2265                 return;
2266
2267         if (user_tsc_khz > tsc_khz) {
2268                 vcpu->arch.tsc_catchup = 1;
2269                 vcpu->arch.tsc_always_catchup = 1;
2270         } else
2271                 WARN(1, "user requested TSC rate below hardware speed\n");
2272 }
2273
2274 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2275 {
2276         return vmcs_read64(TSC_OFFSET);
2277 }
2278
2279 /*
2280  * writes 'offset' into guest's timestamp counter offset register
2281  */
2282 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2283 {
2284         if (is_guest_mode(vcpu)) {
2285                 /*
2286                  * We're here if L1 chose not to trap WRMSR to TSC. According
2287                  * to the spec, this should set L1's TSC; The offset that L1
2288                  * set for L2 remains unchanged, and still needs to be added
2289                  * to the newly set TSC to get L2's TSC.
2290                  */
2291                 struct vmcs12 *vmcs12;
2292                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2293                 /* recalculate vmcs02.TSC_OFFSET: */
2294                 vmcs12 = get_vmcs12(vcpu);
2295                 vmcs_write64(TSC_OFFSET, offset +
2296                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2297                          vmcs12->tsc_offset : 0));
2298         } else {
2299                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2300                                            vmcs_read64(TSC_OFFSET), offset);
2301                 vmcs_write64(TSC_OFFSET, offset);
2302         }
2303 }
2304
2305 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2306 {
2307         u64 offset = vmcs_read64(TSC_OFFSET);
2308
2309         vmcs_write64(TSC_OFFSET, offset + adjustment);
2310         if (is_guest_mode(vcpu)) {
2311                 /* Even when running L2, the adjustment needs to apply to L1 */
2312                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2313         } else
2314                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2315                                            offset + adjustment);
2316 }
2317
2318 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2319 {
2320         return target_tsc - native_read_tsc();
2321 }
2322
2323 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2324 {
2325         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2326         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2327 }
2328
2329 /*
2330  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2331  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2332  * all guests if the "nested" module option is off, and can also be disabled
2333  * for a single guest by disabling its VMX cpuid bit.
2334  */
2335 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2336 {
2337         return nested && guest_cpuid_has_vmx(vcpu);
2338 }
2339
2340 /*
2341  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2342  * returned for the various VMX controls MSRs when nested VMX is enabled.
2343  * The same values should also be used to verify that vmcs12 control fields are
2344  * valid during nested entry from L1 to L2.
2345  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2346  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2347  * bit in the high half is on if the corresponding bit in the control field
2348  * may be on. See also vmx_control_verify().
2349  */
2350 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2351 {
2352         /*
2353          * Note that as a general rule, the high half of the MSRs (bits in
2354          * the control fields which may be 1) should be initialized by the
2355          * intersection of the underlying hardware's MSR (i.e., features which
2356          * can be supported) and the list of features we want to expose -
2357          * because they are known to be properly supported in our code.
2358          * Also, usually, the low half of the MSRs (bits which must be 1) can
2359          * be set to 0, meaning that L1 may turn off any of these bits. The
2360          * reason is that if one of these bits is necessary, it will appear
2361          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2362          * fields of vmcs01 and vmcs02, will turn these bits off - and
2363          * nested_vmx_exit_handled() will not pass related exits to L1.
2364          * These rules have exceptions below.
2365          */
2366
2367         /* pin-based controls */
2368         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2369                 vmx->nested.nested_vmx_pinbased_ctls_low,
2370                 vmx->nested.nested_vmx_pinbased_ctls_high);
2371         vmx->nested.nested_vmx_pinbased_ctls_low |=
2372                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2373         vmx->nested.nested_vmx_pinbased_ctls_high &=
2374                 PIN_BASED_EXT_INTR_MASK |
2375                 PIN_BASED_NMI_EXITING |
2376                 PIN_BASED_VIRTUAL_NMIS;
2377         vmx->nested.nested_vmx_pinbased_ctls_high |=
2378                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2379                 PIN_BASED_VMX_PREEMPTION_TIMER;
2380         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2381                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2382                         PIN_BASED_POSTED_INTR;
2383
2384         /* exit controls */
2385         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2386                 vmx->nested.nested_vmx_exit_ctls_low,
2387                 vmx->nested.nested_vmx_exit_ctls_high);
2388         vmx->nested.nested_vmx_exit_ctls_low =
2389                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2390
2391         vmx->nested.nested_vmx_exit_ctls_high &=
2392 #ifdef CONFIG_X86_64
2393                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2394 #endif
2395                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2396         vmx->nested.nested_vmx_exit_ctls_high |=
2397                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2398                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2399                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2400
2401         if (vmx_mpx_supported())
2402                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2403
2404         /* We support free control of debug control saving. */
2405         vmx->nested.nested_vmx_true_exit_ctls_low =
2406                 vmx->nested.nested_vmx_exit_ctls_low &
2407                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2408
2409         /* entry controls */
2410         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2411                 vmx->nested.nested_vmx_entry_ctls_low,
2412                 vmx->nested.nested_vmx_entry_ctls_high);
2413         vmx->nested.nested_vmx_entry_ctls_low =
2414                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2415         vmx->nested.nested_vmx_entry_ctls_high &=
2416 #ifdef CONFIG_X86_64
2417                 VM_ENTRY_IA32E_MODE |
2418 #endif
2419                 VM_ENTRY_LOAD_IA32_PAT;
2420         vmx->nested.nested_vmx_entry_ctls_high |=
2421                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2422         if (vmx_mpx_supported())
2423                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2424
2425         /* We support free control of debug control loading. */
2426         vmx->nested.nested_vmx_true_entry_ctls_low =
2427                 vmx->nested.nested_vmx_entry_ctls_low &
2428                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2429
2430         /* cpu-based controls */
2431         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2432                 vmx->nested.nested_vmx_procbased_ctls_low,
2433                 vmx->nested.nested_vmx_procbased_ctls_high);
2434         vmx->nested.nested_vmx_procbased_ctls_low =
2435                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2436         vmx->nested.nested_vmx_procbased_ctls_high &=
2437                 CPU_BASED_VIRTUAL_INTR_PENDING |
2438                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2439                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2440                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2441                 CPU_BASED_CR3_STORE_EXITING |
2442 #ifdef CONFIG_X86_64
2443                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2444 #endif
2445                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2446                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2447                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2448                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2449                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2450         /*
2451          * We can allow some features even when not supported by the
2452          * hardware. For example, L1 can specify an MSR bitmap - and we
2453          * can use it to avoid exits to L1 - even when L0 runs L2
2454          * without MSR bitmaps.
2455          */
2456         vmx->nested.nested_vmx_procbased_ctls_high |=
2457                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2458                 CPU_BASED_USE_MSR_BITMAPS;
2459
2460         /* We support free control of CR3 access interception. */
2461         vmx->nested.nested_vmx_true_procbased_ctls_low =
2462                 vmx->nested.nested_vmx_procbased_ctls_low &
2463                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2464
2465         /* secondary cpu-based controls */
2466         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2467                 vmx->nested.nested_vmx_secondary_ctls_low,
2468                 vmx->nested.nested_vmx_secondary_ctls_high);
2469         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2470         vmx->nested.nested_vmx_secondary_ctls_high &=
2471                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2472                 SECONDARY_EXEC_RDTSCP |
2473                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2474                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2475                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2476                 SECONDARY_EXEC_WBINVD_EXITING |
2477                 SECONDARY_EXEC_XSAVES;
2478
2479         if (enable_ept) {
2480                 /* nested EPT: emulate EPT also to L1 */
2481                 vmx->nested.nested_vmx_secondary_ctls_high |=
2482                         SECONDARY_EXEC_ENABLE_EPT;
2483                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2484                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2485                          VMX_EPT_INVEPT_BIT;
2486                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2487                 /*
2488                  * For nested guests, we don't do anything specific
2489                  * for single context invalidation. Hence, only advertise
2490                  * support for global context invalidation.
2491                  */
2492                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2493         } else
2494                 vmx->nested.nested_vmx_ept_caps = 0;
2495
2496         if (enable_unrestricted_guest)
2497                 vmx->nested.nested_vmx_secondary_ctls_high |=
2498                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2499
2500         /* miscellaneous data */
2501         rdmsr(MSR_IA32_VMX_MISC,
2502                 vmx->nested.nested_vmx_misc_low,
2503                 vmx->nested.nested_vmx_misc_high);
2504         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2505         vmx->nested.nested_vmx_misc_low |=
2506                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2507                 VMX_MISC_ACTIVITY_HLT;
2508         vmx->nested.nested_vmx_misc_high = 0;
2509 }
2510
2511 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2512 {
2513         /*
2514          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2515          */
2516         return ((control & high) | low) == control;
2517 }
2518
2519 static inline u64 vmx_control_msr(u32 low, u32 high)
2520 {
2521         return low | ((u64)high << 32);
2522 }
2523
2524 /* Returns 0 on success, non-0 otherwise. */
2525 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2526 {
2527         struct vcpu_vmx *vmx = to_vmx(vcpu);
2528
2529         switch (msr_index) {
2530         case MSR_IA32_VMX_BASIC:
2531                 /*
2532                  * This MSR reports some information about VMX support. We
2533                  * should return information about the VMX we emulate for the
2534                  * guest, and the VMCS structure we give it - not about the
2535                  * VMX support of the underlying hardware.
2536                  */
2537                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2538                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2539                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2540                 break;
2541         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2542         case MSR_IA32_VMX_PINBASED_CTLS:
2543                 *pdata = vmx_control_msr(
2544                         vmx->nested.nested_vmx_pinbased_ctls_low,
2545                         vmx->nested.nested_vmx_pinbased_ctls_high);
2546                 break;
2547         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2548                 *pdata = vmx_control_msr(
2549                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2550                         vmx->nested.nested_vmx_procbased_ctls_high);
2551                 break;
2552         case MSR_IA32_VMX_PROCBASED_CTLS:
2553                 *pdata = vmx_control_msr(
2554                         vmx->nested.nested_vmx_procbased_ctls_low,
2555                         vmx->nested.nested_vmx_procbased_ctls_high);
2556                 break;
2557         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2558                 *pdata = vmx_control_msr(
2559                         vmx->nested.nested_vmx_true_exit_ctls_low,
2560                         vmx->nested.nested_vmx_exit_ctls_high);
2561                 break;
2562         case MSR_IA32_VMX_EXIT_CTLS:
2563                 *pdata = vmx_control_msr(
2564                         vmx->nested.nested_vmx_exit_ctls_low,
2565                         vmx->nested.nested_vmx_exit_ctls_high);
2566                 break;
2567         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2568                 *pdata = vmx_control_msr(
2569                         vmx->nested.nested_vmx_true_entry_ctls_low,
2570                         vmx->nested.nested_vmx_entry_ctls_high);
2571                 break;
2572         case MSR_IA32_VMX_ENTRY_CTLS:
2573                 *pdata = vmx_control_msr(
2574                         vmx->nested.nested_vmx_entry_ctls_low,
2575                         vmx->nested.nested_vmx_entry_ctls_high);
2576                 break;
2577         case MSR_IA32_VMX_MISC:
2578                 *pdata = vmx_control_msr(
2579                         vmx->nested.nested_vmx_misc_low,
2580                         vmx->nested.nested_vmx_misc_high);
2581                 break;
2582         /*
2583          * These MSRs specify bits which the guest must keep fixed (on or off)
2584          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2585          * We picked the standard core2 setting.
2586          */
2587 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2588 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2589         case MSR_IA32_VMX_CR0_FIXED0:
2590                 *pdata = VMXON_CR0_ALWAYSON;
2591                 break;
2592         case MSR_IA32_VMX_CR0_FIXED1:
2593                 *pdata = -1ULL;
2594                 break;
2595         case MSR_IA32_VMX_CR4_FIXED0:
2596                 *pdata = VMXON_CR4_ALWAYSON;
2597                 break;
2598         case MSR_IA32_VMX_CR4_FIXED1:
2599                 *pdata = -1ULL;
2600                 break;
2601         case MSR_IA32_VMX_VMCS_ENUM:
2602                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2603                 break;
2604         case MSR_IA32_VMX_PROCBASED_CTLS2:
2605                 *pdata = vmx_control_msr(
2606                         vmx->nested.nested_vmx_secondary_ctls_low,
2607                         vmx->nested.nested_vmx_secondary_ctls_high);
2608                 break;
2609         case MSR_IA32_VMX_EPT_VPID_CAP:
2610                 /* Currently, no nested vpid support */
2611                 *pdata = vmx->nested.nested_vmx_ept_caps;
2612                 break;
2613         default:
2614                 return 1;
2615         }
2616
2617         return 0;
2618 }
2619
2620 /*
2621  * Reads an msr value (of 'msr_index') into 'pdata'.
2622  * Returns 0 on success, non-0 otherwise.
2623  * Assumes vcpu_load() was already called.
2624  */
2625 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2626 {
2627         u64 data;
2628         struct shared_msr_entry *msr;
2629
2630         if (!pdata) {
2631                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2632                 return -EINVAL;
2633         }
2634
2635         switch (msr_index) {
2636 #ifdef CONFIG_X86_64
2637         case MSR_FS_BASE:
2638                 data = vmcs_readl(GUEST_FS_BASE);
2639                 break;
2640         case MSR_GS_BASE:
2641                 data = vmcs_readl(GUEST_GS_BASE);
2642                 break;
2643         case MSR_KERNEL_GS_BASE:
2644                 vmx_load_host_state(to_vmx(vcpu));
2645                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2646                 break;
2647 #endif
2648         case MSR_EFER:
2649                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2650         case MSR_IA32_TSC:
2651                 data = guest_read_tsc();
2652                 break;
2653         case MSR_IA32_SYSENTER_CS:
2654                 data = vmcs_read32(GUEST_SYSENTER_CS);
2655                 break;
2656         case MSR_IA32_SYSENTER_EIP:
2657                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2658                 break;
2659         case MSR_IA32_SYSENTER_ESP:
2660                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2661                 break;
2662         case MSR_IA32_BNDCFGS:
2663                 if (!vmx_mpx_supported())
2664                         return 1;
2665                 data = vmcs_read64(GUEST_BNDCFGS);
2666                 break;
2667         case MSR_IA32_FEATURE_CONTROL:
2668                 if (!nested_vmx_allowed(vcpu))
2669                         return 1;
2670                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2671                 break;
2672         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2673                 if (!nested_vmx_allowed(vcpu))
2674                         return 1;
2675                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2676         case MSR_IA32_XSS:
2677                 if (!vmx_xsaves_supported())
2678                         return 1;
2679                 data = vcpu->arch.ia32_xss;
2680                 break;
2681         case MSR_TSC_AUX:
2682                 if (!to_vmx(vcpu)->rdtscp_enabled)
2683                         return 1;
2684                 /* Otherwise falls through */
2685         default:
2686                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2687                 if (msr) {
2688                         data = msr->data;
2689                         break;
2690                 }
2691                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2692         }
2693
2694         *pdata = data;
2695         return 0;
2696 }
2697
2698 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2699
2700 /*
2701  * Writes msr value into into the appropriate "register".
2702  * Returns 0 on success, non-0 otherwise.
2703  * Assumes vcpu_load() was already called.
2704  */
2705 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2706 {
2707         struct vcpu_vmx *vmx = to_vmx(vcpu);
2708         struct shared_msr_entry *msr;
2709         int ret = 0;
2710         u32 msr_index = msr_info->index;
2711         u64 data = msr_info->data;
2712
2713         switch (msr_index) {
2714         case MSR_EFER:
2715                 ret = kvm_set_msr_common(vcpu, msr_info);
2716                 break;
2717 #ifdef CONFIG_X86_64
2718         case MSR_FS_BASE:
2719                 vmx_segment_cache_clear(vmx);
2720                 vmcs_writel(GUEST_FS_BASE, data);
2721                 break;
2722         case MSR_GS_BASE:
2723                 vmx_segment_cache_clear(vmx);
2724                 vmcs_writel(GUEST_GS_BASE, data);
2725                 break;
2726         case MSR_KERNEL_GS_BASE:
2727                 vmx_load_host_state(vmx);
2728                 vmx->msr_guest_kernel_gs_base = data;
2729                 break;
2730 #endif
2731         case MSR_IA32_SYSENTER_CS:
2732                 vmcs_write32(GUEST_SYSENTER_CS, data);
2733                 break;
2734         case MSR_IA32_SYSENTER_EIP:
2735                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2736                 break;
2737         case MSR_IA32_SYSENTER_ESP:
2738                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2739                 break;
2740         case MSR_IA32_BNDCFGS:
2741                 if (!vmx_mpx_supported())
2742                         return 1;
2743                 vmcs_write64(GUEST_BNDCFGS, data);
2744                 break;
2745         case MSR_IA32_TSC:
2746                 kvm_write_tsc(vcpu, msr_info);
2747                 break;
2748         case MSR_IA32_CR_PAT:
2749                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2750                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2751                                 return 1;
2752                         vmcs_write64(GUEST_IA32_PAT, data);
2753                         vcpu->arch.pat = data;
2754                         break;
2755                 }
2756                 ret = kvm_set_msr_common(vcpu, msr_info);
2757                 break;
2758         case MSR_IA32_TSC_ADJUST:
2759                 ret = kvm_set_msr_common(vcpu, msr_info);
2760                 break;
2761         case MSR_IA32_FEATURE_CONTROL:
2762                 if (!nested_vmx_allowed(vcpu) ||
2763                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2764                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2765                         return 1;
2766                 vmx->nested.msr_ia32_feature_control = data;
2767                 if (msr_info->host_initiated && data == 0)
2768                         vmx_leave_nested(vcpu);
2769                 break;
2770         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2771                 return 1; /* they are read-only */
2772         case MSR_IA32_XSS:
2773                 if (!vmx_xsaves_supported())
2774                         return 1;
2775                 /*
2776                  * The only supported bit as of Skylake is bit 8, but
2777                  * it is not supported on KVM.
2778                  */
2779                 if (data != 0)
2780                         return 1;
2781                 vcpu->arch.ia32_xss = data;
2782                 if (vcpu->arch.ia32_xss != host_xss)
2783                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2784                                 vcpu->arch.ia32_xss, host_xss);
2785                 else
2786                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2787                 break;
2788         case MSR_TSC_AUX:
2789                 if (!vmx->rdtscp_enabled)
2790                         return 1;
2791                 /* Check reserved bit, higher 32 bits should be zero */
2792                 if ((data >> 32) != 0)
2793                         return 1;
2794                 /* Otherwise falls through */
2795         default:
2796                 msr = find_msr_entry(vmx, msr_index);
2797                 if (msr) {
2798                         u64 old_msr_data = msr->data;
2799                         msr->data = data;
2800                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2801                                 preempt_disable();
2802                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2803                                                          msr->mask);
2804                                 preempt_enable();
2805                                 if (ret)
2806                                         msr->data = old_msr_data;
2807                         }
2808                         break;
2809                 }
2810                 ret = kvm_set_msr_common(vcpu, msr_info);
2811         }
2812
2813         return ret;
2814 }
2815
2816 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2817 {
2818         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2819         switch (reg) {
2820         case VCPU_REGS_RSP:
2821                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2822                 break;
2823         case VCPU_REGS_RIP:
2824                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2825                 break;
2826         case VCPU_EXREG_PDPTR:
2827                 if (enable_ept)
2828                         ept_save_pdptrs(vcpu);
2829                 break;
2830         default:
2831                 break;
2832         }
2833 }
2834
2835 static __init int cpu_has_kvm_support(void)
2836 {
2837         return cpu_has_vmx();
2838 }
2839
2840 static __init int vmx_disabled_by_bios(void)
2841 {
2842         u64 msr;
2843
2844         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2845         if (msr & FEATURE_CONTROL_LOCKED) {
2846                 /* launched w/ TXT and VMX disabled */
2847                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2848                         && tboot_enabled())
2849                         return 1;
2850                 /* launched w/o TXT and VMX only enabled w/ TXT */
2851                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2852                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2853                         && !tboot_enabled()) {
2854                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2855                                 "activate TXT before enabling KVM\n");
2856                         return 1;
2857                 }
2858                 /* launched w/o TXT and VMX disabled */
2859                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2860                         && !tboot_enabled())
2861                         return 1;
2862         }
2863
2864         return 0;
2865 }
2866
2867 static void kvm_cpu_vmxon(u64 addr)
2868 {
2869         asm volatile (ASM_VMX_VMXON_RAX
2870                         : : "a"(&addr), "m"(addr)
2871                         : "memory", "cc");
2872 }
2873
2874 static int hardware_enable(void)
2875 {
2876         int cpu = raw_smp_processor_id();
2877         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2878         u64 old, test_bits;
2879
2880         if (cr4_read_shadow() & X86_CR4_VMXE)
2881                 return -EBUSY;
2882
2883         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2884
2885         /*
2886          * Now we can enable the vmclear operation in kdump
2887          * since the loaded_vmcss_on_cpu list on this cpu
2888          * has been initialized.
2889          *
2890          * Though the cpu is not in VMX operation now, there
2891          * is no problem to enable the vmclear operation
2892          * for the loaded_vmcss_on_cpu list is empty!
2893          */
2894         crash_enable_local_vmclear(cpu);
2895
2896         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2897
2898         test_bits = FEATURE_CONTROL_LOCKED;
2899         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2900         if (tboot_enabled())
2901                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2902
2903         if ((old & test_bits) != test_bits) {
2904                 /* enable and lock */
2905                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2906         }
2907         cr4_set_bits(X86_CR4_VMXE);
2908
2909         if (vmm_exclusive) {
2910                 kvm_cpu_vmxon(phys_addr);
2911                 ept_sync_global();
2912         }
2913
2914         native_store_gdt(this_cpu_ptr(&host_gdt));
2915
2916         return 0;
2917 }
2918
2919 static void vmclear_local_loaded_vmcss(void)
2920 {
2921         int cpu = raw_smp_processor_id();
2922         struct loaded_vmcs *v, *n;
2923
2924         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2925                                  loaded_vmcss_on_cpu_link)
2926                 __loaded_vmcs_clear(v);
2927 }
2928
2929
2930 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2931  * tricks.
2932  */
2933 static void kvm_cpu_vmxoff(void)
2934 {
2935         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2936 }
2937
2938 static void hardware_disable(void)
2939 {
2940         if (vmm_exclusive) {
2941                 vmclear_local_loaded_vmcss();
2942                 kvm_cpu_vmxoff();
2943         }
2944         cr4_clear_bits(X86_CR4_VMXE);
2945 }
2946
2947 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2948                                       u32 msr, u32 *result)
2949 {
2950         u32 vmx_msr_low, vmx_msr_high;
2951         u32 ctl = ctl_min | ctl_opt;
2952
2953         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2954
2955         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2956         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2957
2958         /* Ensure minimum (required) set of control bits are supported. */
2959         if (ctl_min & ~ctl)
2960                 return -EIO;
2961
2962         *result = ctl;
2963         return 0;
2964 }
2965
2966 static __init bool allow_1_setting(u32 msr, u32 ctl)
2967 {
2968         u32 vmx_msr_low, vmx_msr_high;
2969
2970         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2971         return vmx_msr_high & ctl;
2972 }
2973
2974 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2975 {
2976         u32 vmx_msr_low, vmx_msr_high;
2977         u32 min, opt, min2, opt2;
2978         u32 _pin_based_exec_control = 0;
2979         u32 _cpu_based_exec_control = 0;
2980         u32 _cpu_based_2nd_exec_control = 0;
2981         u32 _vmexit_control = 0;
2982         u32 _vmentry_control = 0;
2983
2984         min = CPU_BASED_HLT_EXITING |
2985 #ifdef CONFIG_X86_64
2986               CPU_BASED_CR8_LOAD_EXITING |
2987               CPU_BASED_CR8_STORE_EXITING |
2988 #endif
2989               CPU_BASED_CR3_LOAD_EXITING |
2990               CPU_BASED_CR3_STORE_EXITING |
2991               CPU_BASED_USE_IO_BITMAPS |
2992               CPU_BASED_MOV_DR_EXITING |
2993               CPU_BASED_USE_TSC_OFFSETING |
2994               CPU_BASED_MWAIT_EXITING |
2995               CPU_BASED_MONITOR_EXITING |
2996               CPU_BASED_INVLPG_EXITING |
2997               CPU_BASED_RDPMC_EXITING;
2998
2999         opt = CPU_BASED_TPR_SHADOW |
3000               CPU_BASED_USE_MSR_BITMAPS |
3001               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3002         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3003                                 &_cpu_based_exec_control) < 0)
3004                 return -EIO;
3005 #ifdef CONFIG_X86_64
3006         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3007                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3008                                            ~CPU_BASED_CR8_STORE_EXITING;
3009 #endif
3010         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3011                 min2 = 0;
3012                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3013                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3014                         SECONDARY_EXEC_WBINVD_EXITING |
3015                         SECONDARY_EXEC_ENABLE_VPID |
3016                         SECONDARY_EXEC_ENABLE_EPT |
3017                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3018                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3019                         SECONDARY_EXEC_RDTSCP |
3020                         SECONDARY_EXEC_ENABLE_INVPCID |
3021                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3022                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3023                         SECONDARY_EXEC_SHADOW_VMCS |
3024                         SECONDARY_EXEC_XSAVES |
3025                         SECONDARY_EXEC_ENABLE_PML;
3026                 if (adjust_vmx_controls(min2, opt2,
3027                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3028                                         &_cpu_based_2nd_exec_control) < 0)
3029                         return -EIO;
3030         }
3031 #ifndef CONFIG_X86_64
3032         if (!(_cpu_based_2nd_exec_control &
3033                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3034                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3035 #endif
3036
3037         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3038                 _cpu_based_2nd_exec_control &= ~(
3039                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3040                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3041                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3042
3043         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3044                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3045                    enabled */
3046                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3047                                              CPU_BASED_CR3_STORE_EXITING |
3048                                              CPU_BASED_INVLPG_EXITING);
3049                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3050                       vmx_capability.ept, vmx_capability.vpid);
3051         }
3052
3053         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3054 #ifdef CONFIG_X86_64
3055         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3056 #endif
3057         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3058                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3059         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3060                                 &_vmexit_control) < 0)
3061                 return -EIO;
3062
3063         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3064         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3065         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3066                                 &_pin_based_exec_control) < 0)
3067                 return -EIO;
3068
3069         if (!(_cpu_based_2nd_exec_control &
3070                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3071                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3072                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3073
3074         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3075         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3076         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3077                                 &_vmentry_control) < 0)
3078                 return -EIO;
3079
3080         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3081
3082         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3083         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3084                 return -EIO;
3085
3086 #ifdef CONFIG_X86_64
3087         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3088         if (vmx_msr_high & (1u<<16))
3089                 return -EIO;
3090 #endif
3091
3092         /* Require Write-Back (WB) memory type for VMCS accesses. */
3093         if (((vmx_msr_high >> 18) & 15) != 6)
3094                 return -EIO;
3095
3096         vmcs_conf->size = vmx_msr_high & 0x1fff;
3097         vmcs_conf->order = get_order(vmcs_config.size);
3098         vmcs_conf->revision_id = vmx_msr_low;
3099
3100         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3101         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3102         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3103         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3104         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3105
3106         cpu_has_load_ia32_efer =
3107                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108                                 VM_ENTRY_LOAD_IA32_EFER)
3109                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110                                    VM_EXIT_LOAD_IA32_EFER);
3111
3112         cpu_has_load_perf_global_ctrl =
3113                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3114                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3115                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3116                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3117
3118         /*
3119          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3120          * but due to arrata below it can't be used. Workaround is to use
3121          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3122          *
3123          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3124          *
3125          * AAK155             (model 26)
3126          * AAP115             (model 30)
3127          * AAT100             (model 37)
3128          * BC86,AAY89,BD102   (model 44)
3129          * BA97               (model 46)
3130          *
3131          */
3132         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3133                 switch (boot_cpu_data.x86_model) {
3134                 case 26:
3135                 case 30:
3136                 case 37:
3137                 case 44:
3138                 case 46:
3139                         cpu_has_load_perf_global_ctrl = false;
3140                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3141                                         "does not work properly. Using workaround\n");
3142                         break;
3143                 default:
3144                         break;
3145                 }
3146         }
3147
3148         if (cpu_has_xsaves)
3149                 rdmsrl(MSR_IA32_XSS, host_xss);
3150
3151         return 0;
3152 }
3153
3154 static struct vmcs *alloc_vmcs_cpu(int cpu)
3155 {
3156         int node = cpu_to_node(cpu);
3157         struct page *pages;
3158         struct vmcs *vmcs;
3159
3160         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3161         if (!pages)
3162                 return NULL;
3163         vmcs = page_address(pages);
3164         memset(vmcs, 0, vmcs_config.size);
3165         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3166         return vmcs;
3167 }
3168
3169 static struct vmcs *alloc_vmcs(void)
3170 {
3171         return alloc_vmcs_cpu(raw_smp_processor_id());
3172 }
3173
3174 static void free_vmcs(struct vmcs *vmcs)
3175 {
3176         free_pages((unsigned long)vmcs, vmcs_config.order);
3177 }
3178
3179 /*
3180  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3181  */
3182 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3183 {
3184         if (!loaded_vmcs->vmcs)
3185                 return;
3186         loaded_vmcs_clear(loaded_vmcs);
3187         free_vmcs(loaded_vmcs->vmcs);
3188         loaded_vmcs->vmcs = NULL;
3189 }
3190
3191 static void free_kvm_area(void)
3192 {
3193         int cpu;
3194
3195         for_each_possible_cpu(cpu) {
3196                 free_vmcs(per_cpu(vmxarea, cpu));
3197                 per_cpu(vmxarea, cpu) = NULL;
3198         }
3199 }
3200
3201 static void init_vmcs_shadow_fields(void)
3202 {
3203         int i, j;
3204
3205         /* No checks for read only fields yet */
3206
3207         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3208                 switch (shadow_read_write_fields[i]) {
3209                 case GUEST_BNDCFGS:
3210                         if (!vmx_mpx_supported())
3211                                 continue;
3212                         break;
3213                 default:
3214                         break;
3215                 }
3216
3217                 if (j < i)
3218                         shadow_read_write_fields[j] =
3219                                 shadow_read_write_fields[i];
3220                 j++;
3221         }
3222         max_shadow_read_write_fields = j;
3223
3224         /* shadowed fields guest access without vmexit */
3225         for (i = 0; i < max_shadow_read_write_fields; i++) {
3226                 clear_bit(shadow_read_write_fields[i],
3227                           vmx_vmwrite_bitmap);
3228                 clear_bit(shadow_read_write_fields[i],
3229                           vmx_vmread_bitmap);
3230         }
3231         for (i = 0; i < max_shadow_read_only_fields; i++)
3232                 clear_bit(shadow_read_only_fields[i],
3233                           vmx_vmread_bitmap);
3234 }
3235
3236 static __init int alloc_kvm_area(void)
3237 {
3238         int cpu;
3239
3240         for_each_possible_cpu(cpu) {
3241                 struct vmcs *vmcs;
3242
3243                 vmcs = alloc_vmcs_cpu(cpu);
3244                 if (!vmcs) {
3245                         free_kvm_area();
3246                         return -ENOMEM;
3247                 }
3248
3249                 per_cpu(vmxarea, cpu) = vmcs;
3250         }
3251         return 0;
3252 }
3253
3254 static bool emulation_required(struct kvm_vcpu *vcpu)
3255 {
3256         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3257 }
3258
3259 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3260                 struct kvm_segment *save)
3261 {
3262         if (!emulate_invalid_guest_state) {
3263                 /*
3264                  * CS and SS RPL should be equal during guest entry according
3265                  * to VMX spec, but in reality it is not always so. Since vcpu
3266                  * is in the middle of the transition from real mode to
3267                  * protected mode it is safe to assume that RPL 0 is a good
3268                  * default value.
3269                  */
3270                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3271                         save->selector &= ~SEGMENT_RPL_MASK;
3272                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3273                 save->s = 1;
3274         }
3275         vmx_set_segment(vcpu, save, seg);
3276 }
3277
3278 static void enter_pmode(struct kvm_vcpu *vcpu)
3279 {
3280         unsigned long flags;
3281         struct vcpu_vmx *vmx = to_vmx(vcpu);
3282
3283         /*
3284          * Update real mode segment cache. It may be not up-to-date if sement
3285          * register was written while vcpu was in a guest mode.
3286          */
3287         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3288         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3289         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3290         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3291         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3292         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3293
3294         vmx->rmode.vm86_active = 0;
3295
3296         vmx_segment_cache_clear(vmx);
3297
3298         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3299
3300         flags = vmcs_readl(GUEST_RFLAGS);
3301         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3302         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3303         vmcs_writel(GUEST_RFLAGS, flags);
3304
3305         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3306                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3307
3308         update_exception_bitmap(vcpu);
3309
3310         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3311         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3312         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3313         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3314         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3315         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3316 }
3317
3318 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3319 {
3320         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3321         struct kvm_segment var = *save;
3322
3323         var.dpl = 0x3;
3324         if (seg == VCPU_SREG_CS)
3325                 var.type = 0x3;
3326
3327         if (!emulate_invalid_guest_state) {
3328                 var.selector = var.base >> 4;
3329                 var.base = var.base & 0xffff0;
3330                 var.limit = 0xffff;
3331                 var.g = 0;
3332                 var.db = 0;
3333                 var.present = 1;
3334                 var.s = 1;
3335                 var.l = 0;
3336                 var.unusable = 0;
3337                 var.type = 0x3;
3338                 var.avl = 0;
3339                 if (save->base & 0xf)
3340                         printk_once(KERN_WARNING "kvm: segment base is not "
3341                                         "paragraph aligned when entering "
3342                                         "protected mode (seg=%d)", seg);
3343         }
3344
3345         vmcs_write16(sf->selector, var.selector);
3346         vmcs_write32(sf->base, var.base);
3347         vmcs_write32(sf->limit, var.limit);
3348         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3349 }
3350
3351 static void enter_rmode(struct kvm_vcpu *vcpu)
3352 {
3353         unsigned long flags;
3354         struct vcpu_vmx *vmx = to_vmx(vcpu);
3355
3356         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3357         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3358         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3359         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3360         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3361         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3362         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3363
3364         vmx->rmode.vm86_active = 1;
3365
3366         /*
3367          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3368          * vcpu. Warn the user that an update is overdue.
3369          */
3370         if (!vcpu->kvm->arch.tss_addr)
3371                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3372                              "called before entering vcpu\n");
3373
3374         vmx_segment_cache_clear(vmx);
3375
3376         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3377         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3378         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3379
3380         flags = vmcs_readl(GUEST_RFLAGS);
3381         vmx->rmode.save_rflags = flags;
3382
3383         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3384
3385         vmcs_writel(GUEST_RFLAGS, flags);
3386         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3387         update_exception_bitmap(vcpu);
3388
3389         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3390         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3391         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3392         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3393         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3394         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3395
3396         kvm_mmu_reset_context(vcpu);
3397 }
3398
3399 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3400 {
3401         struct vcpu_vmx *vmx = to_vmx(vcpu);
3402         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3403
3404         if (!msr)
3405                 return;
3406
3407         /*
3408          * Force kernel_gs_base reloading before EFER changes, as control
3409          * of this msr depends on is_long_mode().
3410          */
3411         vmx_load_host_state(to_vmx(vcpu));
3412         vcpu->arch.efer = efer;
3413         if (efer & EFER_LMA) {
3414                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3415                 msr->data = efer;
3416         } else {
3417                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3418
3419                 msr->data = efer & ~EFER_LME;
3420         }
3421         setup_msrs(vmx);
3422 }
3423
3424 #ifdef CONFIG_X86_64
3425
3426 static void enter_lmode(struct kvm_vcpu *vcpu)
3427 {
3428         u32 guest_tr_ar;
3429
3430         vmx_segment_cache_clear(to_vmx(vcpu));
3431
3432         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3433         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3434                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3435                                      __func__);
3436                 vmcs_write32(GUEST_TR_AR_BYTES,
3437                              (guest_tr_ar & ~AR_TYPE_MASK)
3438                              | AR_TYPE_BUSY_64_TSS);
3439         }
3440         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3441 }
3442
3443 static void exit_lmode(struct kvm_vcpu *vcpu)
3444 {
3445         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3446         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3447 }
3448
3449 #endif
3450
3451 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3452 {
3453         vpid_sync_context(to_vmx(vcpu));
3454         if (enable_ept) {
3455                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3456                         return;
3457                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3458         }
3459 }
3460
3461 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3462 {
3463         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3464
3465         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3466         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3467 }
3468
3469 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3470 {
3471         if (enable_ept && is_paging(vcpu))
3472                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3473         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3474 }
3475
3476 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3477 {
3478         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3479
3480         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3481         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3482 }
3483
3484 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3485 {
3486         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3487
3488         if (!test_bit(VCPU_EXREG_PDPTR,
3489                       (unsigned long *)&vcpu->arch.regs_dirty))
3490                 return;
3491
3492         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3493                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3494                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3495                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3496                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3497         }
3498 }
3499
3500 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3501 {
3502         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3503
3504         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3505                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3506                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3507                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3508                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3509         }
3510
3511         __set_bit(VCPU_EXREG_PDPTR,
3512                   (unsigned long *)&vcpu->arch.regs_avail);
3513         __set_bit(VCPU_EXREG_PDPTR,
3514                   (unsigned long *)&vcpu->arch.regs_dirty);
3515 }
3516
3517 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3518
3519 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3520                                         unsigned long cr0,
3521                                         struct kvm_vcpu *vcpu)
3522 {
3523         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3524                 vmx_decache_cr3(vcpu);
3525         if (!(cr0 & X86_CR0_PG)) {
3526                 /* From paging/starting to nonpaging */
3527                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3528                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3529                              (CPU_BASED_CR3_LOAD_EXITING |
3530                               CPU_BASED_CR3_STORE_EXITING));
3531                 vcpu->arch.cr0 = cr0;
3532                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3533         } else if (!is_paging(vcpu)) {
3534                 /* From nonpaging to paging */
3535                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3536                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3537                              ~(CPU_BASED_CR3_LOAD_EXITING |
3538                                CPU_BASED_CR3_STORE_EXITING));
3539                 vcpu->arch.cr0 = cr0;
3540                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3541         }
3542
3543         if (!(cr0 & X86_CR0_WP))
3544                 *hw_cr0 &= ~X86_CR0_WP;
3545 }
3546
3547 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3548 {
3549         struct vcpu_vmx *vmx = to_vmx(vcpu);
3550         unsigned long hw_cr0;
3551
3552         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3553         if (enable_unrestricted_guest)
3554                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3555         else {
3556                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3557
3558                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3559                         enter_pmode(vcpu);
3560
3561                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3562                         enter_rmode(vcpu);
3563         }
3564
3565 #ifdef CONFIG_X86_64
3566         if (vcpu->arch.efer & EFER_LME) {
3567                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3568                         enter_lmode(vcpu);
3569                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3570                         exit_lmode(vcpu);
3571         }
3572 #endif
3573
3574         if (enable_ept)
3575                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3576
3577         if (!vcpu->fpu_active)
3578                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3579
3580         vmcs_writel(CR0_READ_SHADOW, cr0);
3581         vmcs_writel(GUEST_CR0, hw_cr0);
3582         vcpu->arch.cr0 = cr0;
3583
3584         /* depends on vcpu->arch.cr0 to be set to a new value */
3585         vmx->emulation_required = emulation_required(vcpu);
3586 }
3587
3588 static u64 construct_eptp(unsigned long root_hpa)
3589 {
3590         u64 eptp;
3591
3592         /* TODO write the value reading from MSR */
3593         eptp = VMX_EPT_DEFAULT_MT |
3594                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3595         if (enable_ept_ad_bits)
3596                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3597         eptp |= (root_hpa & PAGE_MASK);
3598
3599         return eptp;
3600 }
3601
3602 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3603 {
3604         unsigned long guest_cr3;
3605         u64 eptp;
3606
3607         guest_cr3 = cr3;
3608         if (enable_ept) {
3609                 eptp = construct_eptp(cr3);
3610                 vmcs_write64(EPT_POINTER, eptp);
3611                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3612                         guest_cr3 = kvm_read_cr3(vcpu);
3613                 else
3614                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3615                 ept_load_pdptrs(vcpu);
3616         }
3617
3618         vmx_flush_tlb(vcpu);
3619         vmcs_writel(GUEST_CR3, guest_cr3);
3620 }
3621
3622 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3623 {
3624         /*
3625          * Pass through host's Machine Check Enable value to hw_cr4, which
3626          * is in force while we are in guest mode.  Do not let guests control
3627          * this bit, even if host CR4.MCE == 0.
3628          */
3629         unsigned long hw_cr4 =
3630                 (cr4_read_shadow() & X86_CR4_MCE) |
3631                 (cr4 & ~X86_CR4_MCE) |
3632                 (to_vmx(vcpu)->rmode.vm86_active ?
3633                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3634
3635         if (cr4 & X86_CR4_VMXE) {
3636                 /*
3637                  * To use VMXON (and later other VMX instructions), a guest
3638                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3639                  * So basically the check on whether to allow nested VMX
3640                  * is here.
3641                  */
3642                 if (!nested_vmx_allowed(vcpu))
3643                         return 1;
3644         }
3645         if (to_vmx(vcpu)->nested.vmxon &&
3646             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3647                 return 1;
3648
3649         vcpu->arch.cr4 = cr4;
3650         if (enable_ept) {
3651                 if (!is_paging(vcpu)) {
3652                         hw_cr4 &= ~X86_CR4_PAE;
3653                         hw_cr4 |= X86_CR4_PSE;
3654                         /*
3655                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3656                          * in hardware. However KVM always uses paging mode to
3657                          * emulate guest non-paging mode with TDP.
3658                          * To emulate this behavior, SMEP/SMAP needs to be
3659                          * manually disabled when guest switches to non-paging
3660                          * mode.
3661                          */
3662                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3663                 } else if (!(cr4 & X86_CR4_PAE)) {
3664                         hw_cr4 &= ~X86_CR4_PAE;
3665                 }
3666         }
3667
3668         vmcs_writel(CR4_READ_SHADOW, cr4);
3669         vmcs_writel(GUEST_CR4, hw_cr4);
3670         return 0;
3671 }
3672
3673 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3674                             struct kvm_segment *var, int seg)
3675 {
3676         struct vcpu_vmx *vmx = to_vmx(vcpu);
3677         u32 ar;
3678
3679         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3680                 *var = vmx->rmode.segs[seg];
3681                 if (seg == VCPU_SREG_TR
3682                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3683                         return;
3684                 var->base = vmx_read_guest_seg_base(vmx, seg);
3685                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3686                 return;
3687         }
3688         var->base = vmx_read_guest_seg_base(vmx, seg);
3689         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3690         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3691         ar = vmx_read_guest_seg_ar(vmx, seg);
3692         var->unusable = (ar >> 16) & 1;
3693         var->type = ar & 15;
3694         var->s = (ar >> 4) & 1;
3695         var->dpl = (ar >> 5) & 3;
3696         /*
3697          * Some userspaces do not preserve unusable property. Since usable
3698          * segment has to be present according to VMX spec we can use present
3699          * property to amend userspace bug by making unusable segment always
3700          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3701          * segment as unusable.
3702          */
3703         var->present = !var->unusable;
3704         var->avl = (ar >> 12) & 1;
3705         var->l = (ar >> 13) & 1;
3706         var->db = (ar >> 14) & 1;
3707         var->g = (ar >> 15) & 1;
3708 }
3709
3710 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3711 {
3712         struct kvm_segment s;
3713
3714         if (to_vmx(vcpu)->rmode.vm86_active) {
3715                 vmx_get_segment(vcpu, &s, seg);
3716                 return s.base;
3717         }
3718         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3719 }
3720
3721 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3722 {
3723         struct vcpu_vmx *vmx = to_vmx(vcpu);
3724
3725         if (unlikely(vmx->rmode.vm86_active))
3726                 return 0;
3727         else {
3728                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3729                 return AR_DPL(ar);
3730         }
3731 }
3732
3733 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3734 {
3735         u32 ar;
3736
3737         if (var->unusable || !var->present)
3738                 ar = 1 << 16;
3739         else {
3740                 ar = var->type & 15;
3741                 ar |= (var->s & 1) << 4;
3742                 ar |= (var->dpl & 3) << 5;
3743                 ar |= (var->present & 1) << 7;
3744                 ar |= (var->avl & 1) << 12;
3745                 ar |= (var->l & 1) << 13;
3746                 ar |= (var->db & 1) << 14;
3747                 ar |= (var->g & 1) << 15;
3748         }
3749
3750         return ar;
3751 }
3752
3753 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3754                             struct kvm_segment *var, int seg)
3755 {
3756         struct vcpu_vmx *vmx = to_vmx(vcpu);
3757         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3758
3759         vmx_segment_cache_clear(vmx);
3760
3761         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3762                 vmx->rmode.segs[seg] = *var;
3763                 if (seg == VCPU_SREG_TR)
3764                         vmcs_write16(sf->selector, var->selector);
3765                 else if (var->s)
3766                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3767                 goto out;
3768         }
3769
3770         vmcs_writel(sf->base, var->base);
3771         vmcs_write32(sf->limit, var->limit);
3772         vmcs_write16(sf->selector, var->selector);
3773
3774         /*
3775          *   Fix the "Accessed" bit in AR field of segment registers for older
3776          * qemu binaries.
3777          *   IA32 arch specifies that at the time of processor reset the
3778          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3779          * is setting it to 0 in the userland code. This causes invalid guest
3780          * state vmexit when "unrestricted guest" mode is turned on.
3781          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3782          * tree. Newer qemu binaries with that qemu fix would not need this
3783          * kvm hack.
3784          */
3785         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3786                 var->type |= 0x1; /* Accessed */
3787
3788         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3789
3790 out:
3791         vmx->emulation_required = emulation_required(vcpu);
3792 }
3793
3794 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3795 {
3796         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3797
3798         *db = (ar >> 14) & 1;
3799         *l = (ar >> 13) & 1;
3800 }
3801
3802 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3803 {
3804         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3805         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3806 }
3807
3808 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3809 {
3810         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3811         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3812 }
3813
3814 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3815 {
3816         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3817         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3818 }
3819
3820 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3821 {
3822         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3823         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3824 }
3825
3826 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3827 {
3828         struct kvm_segment var;
3829         u32 ar;
3830
3831         vmx_get_segment(vcpu, &var, seg);
3832         var.dpl = 0x3;
3833         if (seg == VCPU_SREG_CS)
3834                 var.type = 0x3;
3835         ar = vmx_segment_access_rights(&var);
3836
3837         if (var.base != (var.selector << 4))
3838                 return false;
3839         if (var.limit != 0xffff)
3840                 return false;
3841         if (ar != 0xf3)
3842                 return false;
3843
3844         return true;
3845 }
3846
3847 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3848 {
3849         struct kvm_segment cs;
3850         unsigned int cs_rpl;
3851
3852         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3853         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3854
3855         if (cs.unusable)
3856                 return false;
3857         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3858                 return false;
3859         if (!cs.s)
3860                 return false;
3861         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3862                 if (cs.dpl > cs_rpl)
3863                         return false;
3864         } else {
3865                 if (cs.dpl != cs_rpl)
3866                         return false;
3867         }
3868         if (!cs.present)
3869                 return false;
3870
3871         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3872         return true;
3873 }
3874
3875 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3876 {
3877         struct kvm_segment ss;
3878         unsigned int ss_rpl;
3879
3880         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3881         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3882
3883         if (ss.unusable)
3884                 return true;
3885         if (ss.type != 3 && ss.type != 7)
3886                 return false;
3887         if (!ss.s)
3888                 return false;
3889         if (ss.dpl != ss_rpl) /* DPL != RPL */
3890                 return false;
3891         if (!ss.present)
3892                 return false;
3893
3894         return true;
3895 }
3896
3897 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3898 {
3899         struct kvm_segment var;
3900         unsigned int rpl;
3901
3902         vmx_get_segment(vcpu, &var, seg);
3903         rpl = var.selector & SEGMENT_RPL_MASK;
3904
3905         if (var.unusable)
3906                 return true;
3907         if (!var.s)
3908                 return false;
3909         if (!var.present)
3910                 return false;
3911         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3912                 if (var.dpl < rpl) /* DPL < RPL */
3913                         return false;
3914         }
3915
3916         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3917          * rights flags
3918          */
3919         return true;
3920 }
3921
3922 static bool tr_valid(struct kvm_vcpu *vcpu)
3923 {
3924         struct kvm_segment tr;
3925
3926         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3927
3928         if (tr.unusable)
3929                 return false;
3930         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3931                 return false;
3932         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3933                 return false;
3934         if (!tr.present)
3935                 return false;
3936
3937         return true;
3938 }
3939
3940 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3941 {
3942         struct kvm_segment ldtr;
3943
3944         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3945
3946         if (ldtr.unusable)
3947                 return true;
3948         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3949                 return false;
3950         if (ldtr.type != 2)
3951                 return false;
3952         if (!ldtr.present)
3953                 return false;
3954
3955         return true;
3956 }
3957
3958 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3959 {
3960         struct kvm_segment cs, ss;
3961
3962         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3963         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3964
3965         return ((cs.selector & SEGMENT_RPL_MASK) ==
3966                  (ss.selector & SEGMENT_RPL_MASK));
3967 }
3968
3969 /*
3970  * Check if guest state is valid. Returns true if valid, false if
3971  * not.
3972  * We assume that registers are always usable
3973  */
3974 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3975 {
3976         if (enable_unrestricted_guest)
3977                 return true;
3978
3979         /* real mode guest state checks */
3980         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3981                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3982                         return false;
3983                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3984                         return false;
3985                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3986                         return false;
3987                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3988                         return false;
3989                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3990                         return false;
3991                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3992                         return false;
3993         } else {
3994         /* protected mode guest state checks */
3995                 if (!cs_ss_rpl_check(vcpu))
3996                         return false;
3997                 if (!code_segment_valid(vcpu))
3998                         return false;
3999                 if (!stack_segment_valid(vcpu))
4000                         return false;
4001                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4002                         return false;
4003                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4004                         return false;
4005                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4006                         return false;
4007                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4008                         return false;
4009                 if (!tr_valid(vcpu))
4010                         return false;
4011                 if (!ldtr_valid(vcpu))
4012                         return false;
4013         }
4014         /* TODO:
4015          * - Add checks on RIP
4016          * - Add checks on RFLAGS
4017          */
4018
4019         return true;
4020 }
4021
4022 static int init_rmode_tss(struct kvm *kvm)
4023 {
4024         gfn_t fn;
4025         u16 data = 0;
4026         int idx, r;
4027
4028         idx = srcu_read_lock(&kvm->srcu);
4029         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4030         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4031         if (r < 0)
4032                 goto out;
4033         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4034         r = kvm_write_guest_page(kvm, fn++, &data,
4035                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4036         if (r < 0)
4037                 goto out;
4038         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4039         if (r < 0)
4040                 goto out;
4041         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4042         if (r < 0)
4043                 goto out;
4044         data = ~0;
4045         r = kvm_write_guest_page(kvm, fn, &data,
4046                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4047                                  sizeof(u8));
4048 out:
4049         srcu_read_unlock(&kvm->srcu, idx);
4050         return r;
4051 }
4052
4053 static int init_rmode_identity_map(struct kvm *kvm)
4054 {
4055         int i, idx, r = 0;
4056         pfn_t identity_map_pfn;
4057         u32 tmp;
4058
4059         if (!enable_ept)
4060                 return 0;
4061
4062         /* Protect kvm->arch.ept_identity_pagetable_done. */
4063         mutex_lock(&kvm->slots_lock);
4064
4065         if (likely(kvm->arch.ept_identity_pagetable_done))
4066                 goto out2;
4067
4068         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4069
4070         r = alloc_identity_pagetable(kvm);
4071         if (r < 0)
4072                 goto out2;
4073
4074         idx = srcu_read_lock(&kvm->srcu);
4075         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4076         if (r < 0)
4077                 goto out;
4078         /* Set up identity-mapping pagetable for EPT in real mode */
4079         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4080                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4081                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4082                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4083                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4084                 if (r < 0)
4085                         goto out;
4086         }
4087         kvm->arch.ept_identity_pagetable_done = true;
4088
4089 out:
4090         srcu_read_unlock(&kvm->srcu, idx);
4091
4092 out2:
4093         mutex_unlock(&kvm->slots_lock);
4094         return r;
4095 }
4096
4097 static void seg_setup(int seg)
4098 {
4099         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4100         unsigned int ar;
4101
4102         vmcs_write16(sf->selector, 0);
4103         vmcs_writel(sf->base, 0);
4104         vmcs_write32(sf->limit, 0xffff);
4105         ar = 0x93;
4106         if (seg == VCPU_SREG_CS)
4107                 ar |= 0x08; /* code segment */
4108
4109         vmcs_write32(sf->ar_bytes, ar);
4110 }
4111
4112 static int alloc_apic_access_page(struct kvm *kvm)
4113 {
4114         struct page *page;
4115         struct kvm_userspace_memory_region kvm_userspace_mem;
4116         int r = 0;
4117
4118         mutex_lock(&kvm->slots_lock);
4119         if (kvm->arch.apic_access_page_done)
4120                 goto out;
4121         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4122         kvm_userspace_mem.flags = 0;
4123         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4124         kvm_userspace_mem.memory_size = PAGE_SIZE;
4125         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4126         if (r)
4127                 goto out;
4128
4129         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4130         if (is_error_page(page)) {
4131                 r = -EFAULT;
4132                 goto out;
4133         }
4134
4135         /*
4136          * Do not pin the page in memory, so that memory hot-unplug
4137          * is able to migrate it.
4138          */
4139         put_page(page);
4140         kvm->arch.apic_access_page_done = true;
4141 out:
4142         mutex_unlock(&kvm->slots_lock);
4143         return r;
4144 }
4145
4146 static int alloc_identity_pagetable(struct kvm *kvm)
4147 {
4148         /* Called with kvm->slots_lock held. */
4149
4150         struct kvm_userspace_memory_region kvm_userspace_mem;
4151         int r = 0;
4152
4153         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4154
4155         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4156         kvm_userspace_mem.flags = 0;
4157         kvm_userspace_mem.guest_phys_addr =
4158                 kvm->arch.ept_identity_map_addr;
4159         kvm_userspace_mem.memory_size = PAGE_SIZE;
4160         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4161
4162         return r;
4163 }
4164
4165 static void allocate_vpid(struct vcpu_vmx *vmx)
4166 {
4167         int vpid;
4168
4169         vmx->vpid = 0;
4170         if (!enable_vpid)
4171                 return;
4172         spin_lock(&vmx_vpid_lock);
4173         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4174         if (vpid < VMX_NR_VPIDS) {
4175                 vmx->vpid = vpid;
4176                 __set_bit(vpid, vmx_vpid_bitmap);
4177         }
4178         spin_unlock(&vmx_vpid_lock);
4179 }
4180
4181 static void free_vpid(struct vcpu_vmx *vmx)
4182 {
4183         if (!enable_vpid)
4184                 return;
4185         spin_lock(&vmx_vpid_lock);
4186         if (vmx->vpid != 0)
4187                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4188         spin_unlock(&vmx_vpid_lock);
4189 }
4190
4191 #define MSR_TYPE_R      1
4192 #define MSR_TYPE_W      2
4193 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4194                                                 u32 msr, int type)
4195 {
4196         int f = sizeof(unsigned long);
4197
4198         if (!cpu_has_vmx_msr_bitmap())
4199                 return;
4200
4201         /*
4202          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4203          * have the write-low and read-high bitmap offsets the wrong way round.
4204          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4205          */
4206         if (msr <= 0x1fff) {
4207                 if (type & MSR_TYPE_R)
4208                         /* read-low */
4209                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4210
4211                 if (type & MSR_TYPE_W)
4212                         /* write-low */
4213                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4214
4215         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4216                 msr &= 0x1fff;
4217                 if (type & MSR_TYPE_R)
4218                         /* read-high */
4219                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4220
4221                 if (type & MSR_TYPE_W)
4222                         /* write-high */
4223                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4224
4225         }
4226 }
4227
4228 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4229                                                 u32 msr, int type)
4230 {
4231         int f = sizeof(unsigned long);
4232
4233         if (!cpu_has_vmx_msr_bitmap())
4234                 return;
4235
4236         /*
4237          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4238          * have the write-low and read-high bitmap offsets the wrong way round.
4239          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4240          */
4241         if (msr <= 0x1fff) {
4242                 if (type & MSR_TYPE_R)
4243                         /* read-low */
4244                         __set_bit(msr, msr_bitmap + 0x000 / f);
4245
4246                 if (type & MSR_TYPE_W)
4247                         /* write-low */
4248                         __set_bit(msr, msr_bitmap + 0x800 / f);
4249
4250         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4251                 msr &= 0x1fff;
4252                 if (type & MSR_TYPE_R)
4253                         /* read-high */
4254                         __set_bit(msr, msr_bitmap + 0x400 / f);
4255
4256                 if (type & MSR_TYPE_W)
4257                         /* write-high */
4258                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4259
4260         }
4261 }
4262
4263 /*
4264  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4265  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4266  */
4267 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4268                                                unsigned long *msr_bitmap_nested,
4269                                                u32 msr, int type)
4270 {
4271         int f = sizeof(unsigned long);
4272
4273         if (!cpu_has_vmx_msr_bitmap()) {
4274                 WARN_ON(1);
4275                 return;
4276         }
4277
4278         /*
4279          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4280          * have the write-low and read-high bitmap offsets the wrong way round.
4281          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4282          */
4283         if (msr <= 0x1fff) {
4284                 if (type & MSR_TYPE_R &&
4285                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4286                         /* read-low */
4287                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4288
4289                 if (type & MSR_TYPE_W &&
4290                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4291                         /* write-low */
4292                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4293
4294         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4295                 msr &= 0x1fff;
4296                 if (type & MSR_TYPE_R &&
4297                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4298                         /* read-high */
4299                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4300
4301                 if (type & MSR_TYPE_W &&
4302                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4303                         /* write-high */
4304                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4305
4306         }
4307 }
4308
4309 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4310 {
4311         if (!longmode_only)
4312                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4313                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4314         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4315                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4316 }
4317
4318 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4319 {
4320         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4321                         msr, MSR_TYPE_R);
4322         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4323                         msr, MSR_TYPE_R);
4324 }
4325
4326 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4327 {
4328         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4329                         msr, MSR_TYPE_R);
4330         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4331                         msr, MSR_TYPE_R);
4332 }
4333
4334 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4335 {
4336         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4337                         msr, MSR_TYPE_W);
4338         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4339                         msr, MSR_TYPE_W);
4340 }
4341
4342 static int vmx_vm_has_apicv(struct kvm *kvm)
4343 {
4344         return enable_apicv && irqchip_in_kernel(kvm);
4345 }
4346
4347 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4348 {
4349         struct vcpu_vmx *vmx = to_vmx(vcpu);
4350         int max_irr;
4351         void *vapic_page;
4352         u16 status;
4353
4354         if (vmx->nested.pi_desc &&
4355             vmx->nested.pi_pending) {
4356                 vmx->nested.pi_pending = false;
4357                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4358                         return 0;
4359
4360                 max_irr = find_last_bit(
4361                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4362
4363                 if (max_irr == 256)
4364                         return 0;
4365
4366                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4367                 if (!vapic_page) {
4368                         WARN_ON(1);
4369                         return -ENOMEM;
4370                 }
4371                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4372                 kunmap(vmx->nested.virtual_apic_page);
4373
4374                 status = vmcs_read16(GUEST_INTR_STATUS);
4375                 if ((u8)max_irr > ((u8)status & 0xff)) {
4376                         status &= ~0xff;
4377                         status |= (u8)max_irr;
4378                         vmcs_write16(GUEST_INTR_STATUS, status);
4379                 }
4380         }
4381         return 0;
4382 }
4383
4384 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4385 {
4386 #ifdef CONFIG_SMP
4387         if (vcpu->mode == IN_GUEST_MODE) {
4388                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4389                                 POSTED_INTR_VECTOR);
4390                 return true;
4391         }
4392 #endif
4393         return false;
4394 }
4395
4396 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4397                                                 int vector)
4398 {
4399         struct vcpu_vmx *vmx = to_vmx(vcpu);
4400
4401         if (is_guest_mode(vcpu) &&
4402             vector == vmx->nested.posted_intr_nv) {
4403                 /* the PIR and ON have been set by L1. */
4404                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4405                 /*
4406                  * If a posted intr is not recognized by hardware,
4407                  * we will accomplish it in the next vmentry.
4408                  */
4409                 vmx->nested.pi_pending = true;
4410                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4411                 return 0;
4412         }
4413         return -1;
4414 }
4415 /*
4416  * Send interrupt to vcpu via posted interrupt way.
4417  * 1. If target vcpu is running(non-root mode), send posted interrupt
4418  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4419  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4420  * interrupt from PIR in next vmentry.
4421  */
4422 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4423 {
4424         struct vcpu_vmx *vmx = to_vmx(vcpu);
4425         int r;
4426
4427         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4428         if (!r)
4429                 return;
4430
4431         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4432                 return;
4433
4434         r = pi_test_and_set_on(&vmx->pi_desc);
4435         kvm_make_request(KVM_REQ_EVENT, vcpu);
4436         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4437                 kvm_vcpu_kick(vcpu);
4438 }
4439
4440 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4441 {
4442         struct vcpu_vmx *vmx = to_vmx(vcpu);
4443
4444         if (!pi_test_and_clear_on(&vmx->pi_desc))
4445                 return;
4446
4447         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4448 }
4449
4450 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4451 {
4452         return;
4453 }
4454
4455 /*
4456  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4457  * will not change in the lifetime of the guest.
4458  * Note that host-state that does change is set elsewhere. E.g., host-state
4459  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4460  */
4461 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4462 {
4463         u32 low32, high32;
4464         unsigned long tmpl;
4465         struct desc_ptr dt;
4466         unsigned long cr4;
4467
4468         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4469         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4470
4471         /* Save the most likely value for this task's CR4 in the VMCS. */
4472         cr4 = cr4_read_shadow();
4473         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4474         vmx->host_state.vmcs_host_cr4 = cr4;
4475
4476         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4477 #ifdef CONFIG_X86_64
4478         /*
4479          * Load null selectors, so we can avoid reloading them in
4480          * __vmx_load_host_state(), in case userspace uses the null selectors
4481          * too (the expected case).
4482          */
4483         vmcs_write16(HOST_DS_SELECTOR, 0);
4484         vmcs_write16(HOST_ES_SELECTOR, 0);
4485 #else
4486         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4487         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4488 #endif
4489         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4490         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4491
4492         native_store_idt(&dt);
4493         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4494         vmx->host_idt_base = dt.address;
4495
4496         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4497
4498         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4499         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4500         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4501         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4502
4503         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4504                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4505                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4506         }
4507 }
4508
4509 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4510 {
4511         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4512         if (enable_ept)
4513                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4514         if (is_guest_mode(&vmx->vcpu))
4515                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4516                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4517         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4518 }
4519
4520 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4521 {
4522         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4523
4524         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4525                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4526         return pin_based_exec_ctrl;
4527 }
4528
4529 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4530 {
4531         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4532
4533         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4534                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4535
4536         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4537                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4538 #ifdef CONFIG_X86_64
4539                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4540                                 CPU_BASED_CR8_LOAD_EXITING;
4541 #endif
4542         }
4543         if (!enable_ept)
4544                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4545                                 CPU_BASED_CR3_LOAD_EXITING  |
4546                                 CPU_BASED_INVLPG_EXITING;
4547         return exec_control;
4548 }
4549
4550 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4551 {
4552         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4553         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4554                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4555         if (vmx->vpid == 0)
4556                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4557         if (!enable_ept) {
4558                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4559                 enable_unrestricted_guest = 0;
4560                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4561                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4562         }
4563         if (!enable_unrestricted_guest)
4564                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4565         if (!ple_gap)
4566                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4567         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4568                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4569                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4570         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4571         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4572            (handle_vmptrld).
4573            We can NOT enable shadow_vmcs here because we don't have yet
4574            a current VMCS12
4575         */
4576         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4577         /* PML is enabled/disabled in creating/destorying vcpu */
4578         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4579
4580         return exec_control;
4581 }
4582
4583 static void ept_set_mmio_spte_mask(void)
4584 {
4585         /*
4586          * EPT Misconfigurations can be generated if the value of bits 2:0
4587          * of an EPT paging-structure entry is 110b (write/execute).
4588          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4589          * spte.
4590          */
4591         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4592 }
4593
4594 #define VMX_XSS_EXIT_BITMAP 0
4595 /*
4596  * Sets up the vmcs for emulated real mode.
4597  */
4598 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4599 {
4600 #ifdef CONFIG_X86_64
4601         unsigned long a;
4602 #endif
4603         int i;
4604
4605         /* I/O */
4606         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4607         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4608
4609         if (enable_shadow_vmcs) {
4610                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4611                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4612         }
4613         if (cpu_has_vmx_msr_bitmap())
4614                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4615
4616         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4617
4618         /* Control */
4619         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4620
4621         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4622
4623         if (cpu_has_secondary_exec_ctrls()) {
4624                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4625                                 vmx_secondary_exec_control(vmx));
4626         }
4627
4628         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4629                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4630                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4631                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4632                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4633
4634                 vmcs_write16(GUEST_INTR_STATUS, 0);
4635
4636                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4637                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4638         }
4639
4640         if (ple_gap) {
4641                 vmcs_write32(PLE_GAP, ple_gap);
4642                 vmx->ple_window = ple_window;
4643                 vmx->ple_window_dirty = true;
4644         }
4645
4646         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4647         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4648         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4649
4650         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4651         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4652         vmx_set_constant_host_state(vmx);
4653 #ifdef CONFIG_X86_64
4654         rdmsrl(MSR_FS_BASE, a);
4655         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4656         rdmsrl(MSR_GS_BASE, a);
4657         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4658 #else
4659         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4660         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4661 #endif
4662
4663         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4664         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4665         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4666         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4667         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4668
4669         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4670                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4671
4672         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4673                 u32 index = vmx_msr_index[i];
4674                 u32 data_low, data_high;
4675                 int j = vmx->nmsrs;
4676
4677                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4678                         continue;
4679                 if (wrmsr_safe(index, data_low, data_high) < 0)
4680                         continue;
4681                 vmx->guest_msrs[j].index = i;
4682                 vmx->guest_msrs[j].data = 0;
4683                 vmx->guest_msrs[j].mask = -1ull;
4684                 ++vmx->nmsrs;
4685         }
4686
4687
4688         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4689
4690         /* 22.2.1, 20.8.1 */
4691         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4692
4693         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4694         set_cr4_guest_host_mask(vmx);
4695
4696         if (vmx_xsaves_supported())
4697                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4698
4699         return 0;
4700 }
4701
4702 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4703 {
4704         struct vcpu_vmx *vmx = to_vmx(vcpu);
4705         struct msr_data apic_base_msr;
4706         u64 cr0;
4707
4708         vmx->rmode.vm86_active = 0;
4709
4710         vmx->soft_vnmi_blocked = 0;
4711
4712         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4713         kvm_set_cr8(vcpu, 0);
4714
4715         if (!init_event) {
4716                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4717                                      MSR_IA32_APICBASE_ENABLE;
4718                 if (kvm_vcpu_is_reset_bsp(vcpu))
4719                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4720                 apic_base_msr.host_initiated = true;
4721                 kvm_set_apic_base(vcpu, &apic_base_msr);
4722         }
4723
4724         vmx_segment_cache_clear(vmx);
4725
4726         seg_setup(VCPU_SREG_CS);
4727         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4728         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4729
4730         seg_setup(VCPU_SREG_DS);
4731         seg_setup(VCPU_SREG_ES);
4732         seg_setup(VCPU_SREG_FS);
4733         seg_setup(VCPU_SREG_GS);
4734         seg_setup(VCPU_SREG_SS);
4735
4736         vmcs_write16(GUEST_TR_SELECTOR, 0);
4737         vmcs_writel(GUEST_TR_BASE, 0);
4738         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4739         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4740
4741         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4742         vmcs_writel(GUEST_LDTR_BASE, 0);
4743         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4744         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4745
4746         if (!init_event) {
4747                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4748                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4749                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4750                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4751         }
4752
4753         vmcs_writel(GUEST_RFLAGS, 0x02);
4754         kvm_rip_write(vcpu, 0xfff0);
4755
4756         vmcs_writel(GUEST_GDTR_BASE, 0);
4757         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4758
4759         vmcs_writel(GUEST_IDTR_BASE, 0);
4760         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4761
4762         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4763         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4764         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4765
4766         setup_msrs(vmx);
4767
4768         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4769
4770         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4771                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4772                 if (vm_need_tpr_shadow(vcpu->kvm))
4773                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4774                                      __pa(vcpu->arch.apic->regs));
4775                 vmcs_write32(TPR_THRESHOLD, 0);
4776         }
4777
4778         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4779
4780         if (vmx_vm_has_apicv(vcpu->kvm))
4781                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4782
4783         if (vmx->vpid != 0)
4784                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4785
4786         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4787         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4788         vmx->vcpu.arch.cr0 = cr0;
4789         vmx_set_cr4(vcpu, 0);
4790         if (!init_event)
4791                 vmx_set_efer(vcpu, 0);
4792         vmx_fpu_activate(vcpu);
4793         update_exception_bitmap(vcpu);
4794
4795         vpid_sync_context(vmx);
4796 }
4797
4798 /*
4799  * In nested virtualization, check if L1 asked to exit on external interrupts.
4800  * For most existing hypervisors, this will always return true.
4801  */
4802 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4803 {
4804         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4805                 PIN_BASED_EXT_INTR_MASK;
4806 }
4807
4808 /*
4809  * In nested virtualization, check if L1 has set
4810  * VM_EXIT_ACK_INTR_ON_EXIT
4811  */
4812 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4813 {
4814         return get_vmcs12(vcpu)->vm_exit_controls &
4815                 VM_EXIT_ACK_INTR_ON_EXIT;
4816 }
4817
4818 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4819 {
4820         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4821                 PIN_BASED_NMI_EXITING;
4822 }
4823
4824 static void enable_irq_window(struct kvm_vcpu *vcpu)
4825 {
4826         u32 cpu_based_vm_exec_control;
4827
4828         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4829         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4830         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4831 }
4832
4833 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4834 {
4835         u32 cpu_based_vm_exec_control;
4836
4837         if (!cpu_has_virtual_nmis() ||
4838             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4839                 enable_irq_window(vcpu);
4840                 return;
4841         }
4842
4843         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4844         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4845         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4846 }
4847
4848 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4849 {
4850         struct vcpu_vmx *vmx = to_vmx(vcpu);
4851         uint32_t intr;
4852         int irq = vcpu->arch.interrupt.nr;
4853
4854         trace_kvm_inj_virq(irq);
4855
4856         ++vcpu->stat.irq_injections;
4857         if (vmx->rmode.vm86_active) {
4858                 int inc_eip = 0;
4859                 if (vcpu->arch.interrupt.soft)
4860                         inc_eip = vcpu->arch.event_exit_inst_len;
4861                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4862                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4863                 return;
4864         }
4865         intr = irq | INTR_INFO_VALID_MASK;
4866         if (vcpu->arch.interrupt.soft) {
4867                 intr |= INTR_TYPE_SOFT_INTR;
4868                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4869                              vmx->vcpu.arch.event_exit_inst_len);
4870         } else
4871                 intr |= INTR_TYPE_EXT_INTR;
4872         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4873 }
4874
4875 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4876 {
4877         struct vcpu_vmx *vmx = to_vmx(vcpu);
4878
4879         if (is_guest_mode(vcpu))
4880                 return;
4881
4882         if (!cpu_has_virtual_nmis()) {
4883                 /*
4884                  * Tracking the NMI-blocked state in software is built upon
4885                  * finding the next open IRQ window. This, in turn, depends on
4886                  * well-behaving guests: They have to keep IRQs disabled at
4887                  * least as long as the NMI handler runs. Otherwise we may
4888                  * cause NMI nesting, maybe breaking the guest. But as this is
4889                  * highly unlikely, we can live with the residual risk.
4890                  */
4891                 vmx->soft_vnmi_blocked = 1;
4892                 vmx->vnmi_blocked_time = 0;
4893         }
4894
4895         ++vcpu->stat.nmi_injections;
4896         vmx->nmi_known_unmasked = false;
4897         if (vmx->rmode.vm86_active) {
4898                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4899                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4900                 return;
4901         }
4902         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4903                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4904 }
4905
4906 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4907 {
4908         if (!cpu_has_virtual_nmis())
4909                 return to_vmx(vcpu)->soft_vnmi_blocked;
4910         if (to_vmx(vcpu)->nmi_known_unmasked)
4911                 return false;
4912         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4913 }
4914
4915 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4916 {
4917         struct vcpu_vmx *vmx = to_vmx(vcpu);
4918
4919         if (!cpu_has_virtual_nmis()) {
4920                 if (vmx->soft_vnmi_blocked != masked) {
4921                         vmx->soft_vnmi_blocked = masked;
4922                         vmx->vnmi_blocked_time = 0;
4923                 }
4924         } else {
4925                 vmx->nmi_known_unmasked = !masked;
4926                 if (masked)
4927                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4928                                       GUEST_INTR_STATE_NMI);
4929                 else
4930                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4931                                         GUEST_INTR_STATE_NMI);
4932         }
4933 }
4934
4935 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4936 {
4937         if (to_vmx(vcpu)->nested.nested_run_pending)
4938                 return 0;
4939
4940         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4941                 return 0;
4942
4943         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4944                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4945                    | GUEST_INTR_STATE_NMI));
4946 }
4947
4948 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4949 {
4950         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4951                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4952                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4953                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4954 }
4955
4956 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4957 {
4958         int ret;
4959         struct kvm_userspace_memory_region tss_mem = {
4960                 .slot = TSS_PRIVATE_MEMSLOT,
4961                 .guest_phys_addr = addr,
4962                 .memory_size = PAGE_SIZE * 3,
4963                 .flags = 0,
4964         };
4965
4966         ret = kvm_set_memory_region(kvm, &tss_mem);
4967         if (ret)
4968                 return ret;
4969         kvm->arch.tss_addr = addr;
4970         return init_rmode_tss(kvm);
4971 }
4972
4973 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4974 {
4975         switch (vec) {
4976         case BP_VECTOR:
4977                 /*
4978                  * Update instruction length as we may reinject the exception
4979                  * from user space while in guest debugging mode.
4980                  */
4981                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4982                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4983                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4984                         return false;
4985                 /* fall through */
4986         case DB_VECTOR:
4987                 if (vcpu->guest_debug &
4988                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4989                         return false;
4990                 /* fall through */
4991         case DE_VECTOR:
4992         case OF_VECTOR:
4993         case BR_VECTOR:
4994         case UD_VECTOR:
4995         case DF_VECTOR:
4996         case SS_VECTOR:
4997         case GP_VECTOR:
4998         case MF_VECTOR:
4999                 return true;
5000         break;
5001         }
5002         return false;
5003 }
5004
5005 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5006                                   int vec, u32 err_code)
5007 {
5008         /*
5009          * Instruction with address size override prefix opcode 0x67
5010          * Cause the #SS fault with 0 error code in VM86 mode.
5011          */
5012         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5013                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5014                         if (vcpu->arch.halt_request) {
5015                                 vcpu->arch.halt_request = 0;
5016                                 return kvm_vcpu_halt(vcpu);
5017                         }
5018                         return 1;
5019                 }
5020                 return 0;
5021         }
5022
5023         /*
5024          * Forward all other exceptions that are valid in real mode.
5025          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5026          *        the required debugging infrastructure rework.
5027          */
5028         kvm_queue_exception(vcpu, vec);
5029         return 1;
5030 }
5031
5032 /*
5033  * Trigger machine check on the host. We assume all the MSRs are already set up
5034  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5035  * We pass a fake environment to the machine check handler because we want
5036  * the guest to be always treated like user space, no matter what context
5037  * it used internally.
5038  */
5039 static void kvm_machine_check(void)
5040 {
5041 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5042         struct pt_regs regs = {
5043                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5044                 .flags = X86_EFLAGS_IF,
5045         };
5046
5047         do_machine_check(&regs, 0);
5048 #endif
5049 }
5050
5051 static int handle_machine_check(struct kvm_vcpu *vcpu)
5052 {
5053         /* already handled by vcpu_run */
5054         return 1;
5055 }
5056
5057 static int handle_exception(struct kvm_vcpu *vcpu)
5058 {
5059         struct vcpu_vmx *vmx = to_vmx(vcpu);
5060         struct kvm_run *kvm_run = vcpu->run;
5061         u32 intr_info, ex_no, error_code;
5062         unsigned long cr2, rip, dr6;
5063         u32 vect_info;
5064         enum emulation_result er;
5065
5066         vect_info = vmx->idt_vectoring_info;
5067         intr_info = vmx->exit_intr_info;
5068
5069         if (is_machine_check(intr_info))
5070                 return handle_machine_check(vcpu);
5071
5072         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5073                 return 1;  /* already handled by vmx_vcpu_run() */
5074
5075         if (is_no_device(intr_info)) {
5076                 vmx_fpu_activate(vcpu);
5077                 return 1;
5078         }
5079
5080         if (is_invalid_opcode(intr_info)) {
5081                 if (is_guest_mode(vcpu)) {
5082                         kvm_queue_exception(vcpu, UD_VECTOR);
5083                         return 1;
5084                 }
5085                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5086                 if (er != EMULATE_DONE)
5087                         kvm_queue_exception(vcpu, UD_VECTOR);
5088                 return 1;
5089         }
5090
5091         error_code = 0;
5092         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5093                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5094
5095         /*
5096          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5097          * MMIO, it is better to report an internal error.
5098          * See the comments in vmx_handle_exit.
5099          */
5100         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5101             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5102                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5103                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5104                 vcpu->run->internal.ndata = 3;
5105                 vcpu->run->internal.data[0] = vect_info;
5106                 vcpu->run->internal.data[1] = intr_info;
5107                 vcpu->run->internal.data[2] = error_code;
5108                 return 0;
5109         }
5110
5111         if (is_page_fault(intr_info)) {
5112                 /* EPT won't cause page fault directly */
5113                 BUG_ON(enable_ept);
5114                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5115                 trace_kvm_page_fault(cr2, error_code);
5116
5117                 if (kvm_event_needs_reinjection(vcpu))
5118                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5119                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5120         }
5121
5122         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5123
5124         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5125                 return handle_rmode_exception(vcpu, ex_no, error_code);
5126
5127         switch (ex_no) {
5128         case DB_VECTOR:
5129                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5130                 if (!(vcpu->guest_debug &
5131                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5132                         vcpu->arch.dr6 &= ~15;
5133                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5134                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5135                                 skip_emulated_instruction(vcpu);
5136
5137                         kvm_queue_exception(vcpu, DB_VECTOR);
5138                         return 1;
5139                 }
5140                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5141                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5142                 /* fall through */
5143         case BP_VECTOR:
5144                 /*
5145                  * Update instruction length as we may reinject #BP from
5146                  * user space while in guest debugging mode. Reading it for
5147                  * #DB as well causes no harm, it is not used in that case.
5148                  */
5149                 vmx->vcpu.arch.event_exit_inst_len =
5150                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5151                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5152                 rip = kvm_rip_read(vcpu);
5153                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5154                 kvm_run->debug.arch.exception = ex_no;
5155                 break;
5156         default:
5157                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5158                 kvm_run->ex.exception = ex_no;
5159                 kvm_run->ex.error_code = error_code;
5160                 break;
5161         }
5162         return 0;
5163 }
5164
5165 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5166 {
5167         ++vcpu->stat.irq_exits;
5168         return 1;
5169 }
5170
5171 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5172 {
5173         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5174         return 0;
5175 }
5176
5177 static int handle_io(struct kvm_vcpu *vcpu)
5178 {
5179         unsigned long exit_qualification;
5180         int size, in, string;
5181         unsigned port;
5182
5183         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5184         string = (exit_qualification & 16) != 0;
5185         in = (exit_qualification & 8) != 0;
5186
5187         ++vcpu->stat.io_exits;
5188
5189         if (string || in)
5190                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5191
5192         port = exit_qualification >> 16;
5193         size = (exit_qualification & 7) + 1;
5194         skip_emulated_instruction(vcpu);
5195
5196         return kvm_fast_pio_out(vcpu, size, port);
5197 }
5198
5199 static void
5200 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5201 {
5202         /*
5203          * Patch in the VMCALL instruction:
5204          */
5205         hypercall[0] = 0x0f;
5206         hypercall[1] = 0x01;
5207         hypercall[2] = 0xc1;
5208 }
5209
5210 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5211 {
5212         unsigned long always_on = VMXON_CR0_ALWAYSON;
5213         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5214
5215         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5216                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5217             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5218                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5219         return (val & always_on) == always_on;
5220 }
5221
5222 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5223 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5224 {
5225         if (is_guest_mode(vcpu)) {
5226                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5227                 unsigned long orig_val = val;
5228
5229                 /*
5230                  * We get here when L2 changed cr0 in a way that did not change
5231                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5232                  * but did change L0 shadowed bits. So we first calculate the
5233                  * effective cr0 value that L1 would like to write into the
5234                  * hardware. It consists of the L2-owned bits from the new
5235                  * value combined with the L1-owned bits from L1's guest_cr0.
5236                  */
5237                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5238                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5239
5240                 if (!nested_cr0_valid(vcpu, val))
5241                         return 1;
5242
5243                 if (kvm_set_cr0(vcpu, val))
5244                         return 1;
5245                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5246                 return 0;
5247         } else {
5248                 if (to_vmx(vcpu)->nested.vmxon &&
5249                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5250                         return 1;
5251                 return kvm_set_cr0(vcpu, val);
5252         }
5253 }
5254
5255 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5256 {
5257         if (is_guest_mode(vcpu)) {
5258                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5259                 unsigned long orig_val = val;
5260
5261                 /* analogously to handle_set_cr0 */
5262                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5263                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5264                 if (kvm_set_cr4(vcpu, val))
5265                         return 1;
5266                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5267                 return 0;
5268         } else
5269                 return kvm_set_cr4(vcpu, val);
5270 }
5271
5272 /* called to set cr0 as approriate for clts instruction exit. */
5273 static void handle_clts(struct kvm_vcpu *vcpu)
5274 {
5275         if (is_guest_mode(vcpu)) {
5276                 /*
5277                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5278                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5279                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5280                  */
5281                 vmcs_writel(CR0_READ_SHADOW,
5282                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5283                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5284         } else
5285                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5286 }
5287
5288 static int handle_cr(struct kvm_vcpu *vcpu)
5289 {
5290         unsigned long exit_qualification, val;
5291         int cr;
5292         int reg;
5293         int err;
5294
5295         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5296         cr = exit_qualification & 15;
5297         reg = (exit_qualification >> 8) & 15;
5298         switch ((exit_qualification >> 4) & 3) {
5299         case 0: /* mov to cr */
5300                 val = kvm_register_readl(vcpu, reg);
5301                 trace_kvm_cr_write(cr, val);
5302                 switch (cr) {
5303                 case 0:
5304                         err = handle_set_cr0(vcpu, val);
5305                         kvm_complete_insn_gp(vcpu, err);
5306                         return 1;
5307                 case 3:
5308                         err = kvm_set_cr3(vcpu, val);
5309                         kvm_complete_insn_gp(vcpu, err);
5310                         return 1;
5311                 case 4:
5312                         err = handle_set_cr4(vcpu, val);
5313                         kvm_complete_insn_gp(vcpu, err);
5314                         return 1;
5315                 case 8: {
5316                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5317                                 u8 cr8 = (u8)val;
5318                                 err = kvm_set_cr8(vcpu, cr8);
5319                                 kvm_complete_insn_gp(vcpu, err);
5320                                 if (irqchip_in_kernel(vcpu->kvm))
5321                                         return 1;
5322                                 if (cr8_prev <= cr8)
5323                                         return 1;
5324                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5325                                 return 0;
5326                         }
5327                 }
5328                 break;
5329         case 2: /* clts */
5330                 handle_clts(vcpu);
5331                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5332                 skip_emulated_instruction(vcpu);
5333                 vmx_fpu_activate(vcpu);
5334                 return 1;
5335         case 1: /*mov from cr*/
5336                 switch (cr) {
5337                 case 3:
5338                         val = kvm_read_cr3(vcpu);
5339                         kvm_register_write(vcpu, reg, val);
5340                         trace_kvm_cr_read(cr, val);
5341                         skip_emulated_instruction(vcpu);
5342                         return 1;
5343                 case 8:
5344                         val = kvm_get_cr8(vcpu);
5345                         kvm_register_write(vcpu, reg, val);
5346                         trace_kvm_cr_read(cr, val);
5347                         skip_emulated_instruction(vcpu);
5348                         return 1;
5349                 }
5350                 break;
5351         case 3: /* lmsw */
5352                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5353                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5354                 kvm_lmsw(vcpu, val);
5355
5356                 skip_emulated_instruction(vcpu);
5357                 return 1;
5358         default:
5359                 break;
5360         }
5361         vcpu->run->exit_reason = 0;
5362         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5363                (int)(exit_qualification >> 4) & 3, cr);
5364         return 0;
5365 }
5366
5367 static int handle_dr(struct kvm_vcpu *vcpu)
5368 {
5369         unsigned long exit_qualification;
5370         int dr, dr7, reg;
5371
5372         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5373         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5374
5375         /* First, if DR does not exist, trigger UD */
5376         if (!kvm_require_dr(vcpu, dr))
5377                 return 1;
5378
5379         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5380         if (!kvm_require_cpl(vcpu, 0))
5381                 return 1;
5382         dr7 = vmcs_readl(GUEST_DR7);
5383         if (dr7 & DR7_GD) {
5384                 /*
5385                  * As the vm-exit takes precedence over the debug trap, we
5386                  * need to emulate the latter, either for the host or the
5387                  * guest debugging itself.
5388                  */
5389                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5390                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5391                         vcpu->run->debug.arch.dr7 = dr7;
5392                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5393                         vcpu->run->debug.arch.exception = DB_VECTOR;
5394                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5395                         return 0;
5396                 } else {
5397                         vcpu->arch.dr6 &= ~15;
5398                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5399                         kvm_queue_exception(vcpu, DB_VECTOR);
5400                         return 1;
5401                 }
5402         }
5403
5404         if (vcpu->guest_debug == 0) {
5405                 u32 cpu_based_vm_exec_control;
5406
5407                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5408                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5409                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5410
5411                 /*
5412                  * No more DR vmexits; force a reload of the debug registers
5413                  * and reenter on this instruction.  The next vmexit will
5414                  * retrieve the full state of the debug registers.
5415                  */
5416                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5417                 return 1;
5418         }
5419
5420         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5421         if (exit_qualification & TYPE_MOV_FROM_DR) {
5422                 unsigned long val;
5423
5424                 if (kvm_get_dr(vcpu, dr, &val))
5425                         return 1;
5426                 kvm_register_write(vcpu, reg, val);
5427         } else
5428                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5429                         return 1;
5430
5431         skip_emulated_instruction(vcpu);
5432         return 1;
5433 }
5434
5435 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5436 {
5437         return vcpu->arch.dr6;
5438 }
5439
5440 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5441 {
5442 }
5443
5444 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5445 {
5446         u32 cpu_based_vm_exec_control;
5447
5448         get_debugreg(vcpu->arch.db[0], 0);
5449         get_debugreg(vcpu->arch.db[1], 1);
5450         get_debugreg(vcpu->arch.db[2], 2);
5451         get_debugreg(vcpu->arch.db[3], 3);
5452         get_debugreg(vcpu->arch.dr6, 6);
5453         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5454
5455         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5456
5457         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5458         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5459         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5460 }
5461
5462 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5463 {
5464         vmcs_writel(GUEST_DR7, val);
5465 }
5466
5467 static int handle_cpuid(struct kvm_vcpu *vcpu)
5468 {
5469         kvm_emulate_cpuid(vcpu);
5470         return 1;
5471 }
5472
5473 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5474 {
5475         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5476         u64 data;
5477
5478         if (vmx_get_msr(vcpu, ecx, &data)) {
5479                 trace_kvm_msr_read_ex(ecx);
5480                 kvm_inject_gp(vcpu, 0);
5481                 return 1;
5482         }
5483
5484         trace_kvm_msr_read(ecx, data);
5485
5486         /* FIXME: handling of bits 32:63 of rax, rdx */
5487         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5488         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5489         skip_emulated_instruction(vcpu);
5490         return 1;
5491 }
5492
5493 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5494 {
5495         struct msr_data msr;
5496         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5497         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5498                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5499
5500         msr.data = data;
5501         msr.index = ecx;
5502         msr.host_initiated = false;
5503         if (kvm_set_msr(vcpu, &msr) != 0) {
5504                 trace_kvm_msr_write_ex(ecx, data);
5505                 kvm_inject_gp(vcpu, 0);
5506                 return 1;
5507         }
5508
5509         trace_kvm_msr_write(ecx, data);
5510         skip_emulated_instruction(vcpu);
5511         return 1;
5512 }
5513
5514 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5515 {
5516         kvm_make_request(KVM_REQ_EVENT, vcpu);
5517         return 1;
5518 }
5519
5520 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5521 {
5522         u32 cpu_based_vm_exec_control;
5523
5524         /* clear pending irq */
5525         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5526         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5527         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5528
5529         kvm_make_request(KVM_REQ_EVENT, vcpu);
5530
5531         ++vcpu->stat.irq_window_exits;
5532
5533         /*
5534          * If the user space waits to inject interrupts, exit as soon as
5535          * possible
5536          */
5537         if (!irqchip_in_kernel(vcpu->kvm) &&
5538             vcpu->run->request_interrupt_window &&
5539             !kvm_cpu_has_interrupt(vcpu)) {
5540                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5541                 return 0;
5542         }
5543         return 1;
5544 }
5545
5546 static int handle_halt(struct kvm_vcpu *vcpu)
5547 {
5548         return kvm_emulate_halt(vcpu);
5549 }
5550
5551 static int handle_vmcall(struct kvm_vcpu *vcpu)
5552 {
5553         kvm_emulate_hypercall(vcpu);
5554         return 1;
5555 }
5556
5557 static int handle_invd(struct kvm_vcpu *vcpu)
5558 {
5559         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5560 }
5561
5562 static int handle_invlpg(struct kvm_vcpu *vcpu)
5563 {
5564         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5565
5566         kvm_mmu_invlpg(vcpu, exit_qualification);
5567         skip_emulated_instruction(vcpu);
5568         return 1;
5569 }
5570
5571 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5572 {
5573         int err;
5574
5575         err = kvm_rdpmc(vcpu);
5576         kvm_complete_insn_gp(vcpu, err);
5577
5578         return 1;
5579 }
5580
5581 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5582 {
5583         kvm_emulate_wbinvd(vcpu);
5584         return 1;
5585 }
5586
5587 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5588 {
5589         u64 new_bv = kvm_read_edx_eax(vcpu);
5590         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5591
5592         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5593                 skip_emulated_instruction(vcpu);
5594         return 1;
5595 }
5596
5597 static int handle_xsaves(struct kvm_vcpu *vcpu)
5598 {
5599         skip_emulated_instruction(vcpu);
5600         WARN(1, "this should never happen\n");
5601         return 1;
5602 }
5603
5604 static int handle_xrstors(struct kvm_vcpu *vcpu)
5605 {
5606         skip_emulated_instruction(vcpu);
5607         WARN(1, "this should never happen\n");
5608         return 1;
5609 }
5610
5611 static int handle_apic_access(struct kvm_vcpu *vcpu)
5612 {
5613         if (likely(fasteoi)) {
5614                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5615                 int access_type, offset;
5616
5617                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5618                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5619                 /*
5620                  * Sane guest uses MOV to write EOI, with written value
5621                  * not cared. So make a short-circuit here by avoiding
5622                  * heavy instruction emulation.
5623                  */
5624                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5625                     (offset == APIC_EOI)) {
5626                         kvm_lapic_set_eoi(vcpu);
5627                         skip_emulated_instruction(vcpu);
5628                         return 1;
5629                 }
5630         }
5631         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5632 }
5633
5634 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5635 {
5636         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5637         int vector = exit_qualification & 0xff;
5638
5639         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5640         kvm_apic_set_eoi_accelerated(vcpu, vector);
5641         return 1;
5642 }
5643
5644 static int handle_apic_write(struct kvm_vcpu *vcpu)
5645 {
5646         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5647         u32 offset = exit_qualification & 0xfff;
5648
5649         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5650         kvm_apic_write_nodecode(vcpu, offset);
5651         return 1;
5652 }
5653
5654 static int handle_task_switch(struct kvm_vcpu *vcpu)
5655 {
5656         struct vcpu_vmx *vmx = to_vmx(vcpu);
5657         unsigned long exit_qualification;
5658         bool has_error_code = false;
5659         u32 error_code = 0;
5660         u16 tss_selector;
5661         int reason, type, idt_v, idt_index;
5662
5663         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5664         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5665         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5666
5667         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5668
5669         reason = (u32)exit_qualification >> 30;
5670         if (reason == TASK_SWITCH_GATE && idt_v) {
5671                 switch (type) {
5672                 case INTR_TYPE_NMI_INTR:
5673                         vcpu->arch.nmi_injected = false;
5674                         vmx_set_nmi_mask(vcpu, true);
5675                         break;
5676                 case INTR_TYPE_EXT_INTR:
5677                 case INTR_TYPE_SOFT_INTR:
5678                         kvm_clear_interrupt_queue(vcpu);
5679                         break;
5680                 case INTR_TYPE_HARD_EXCEPTION:
5681                         if (vmx->idt_vectoring_info &
5682                             VECTORING_INFO_DELIVER_CODE_MASK) {
5683                                 has_error_code = true;
5684                                 error_code =
5685                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5686                         }
5687                         /* fall through */
5688                 case INTR_TYPE_SOFT_EXCEPTION:
5689                         kvm_clear_exception_queue(vcpu);
5690                         break;
5691                 default:
5692                         break;
5693                 }
5694         }
5695         tss_selector = exit_qualification;
5696
5697         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5698                        type != INTR_TYPE_EXT_INTR &&
5699                        type != INTR_TYPE_NMI_INTR))
5700                 skip_emulated_instruction(vcpu);
5701
5702         if (kvm_task_switch(vcpu, tss_selector,
5703                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5704                             has_error_code, error_code) == EMULATE_FAIL) {
5705                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5706                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5707                 vcpu->run->internal.ndata = 0;
5708                 return 0;
5709         }
5710
5711         /* clear all local breakpoint enable flags */
5712         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5713
5714         /*
5715          * TODO: What about debug traps on tss switch?
5716          *       Are we supposed to inject them and update dr6?
5717          */
5718
5719         return 1;
5720 }
5721
5722 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5723 {
5724         unsigned long exit_qualification;
5725         gpa_t gpa;
5726         u32 error_code;
5727         int gla_validity;
5728
5729         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5730
5731         gla_validity = (exit_qualification >> 7) & 0x3;
5732         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5733                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5734                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5735                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5736                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5737                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5738                         (long unsigned int)exit_qualification);
5739                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5740                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5741                 return 0;
5742         }
5743
5744         /*
5745          * EPT violation happened while executing iret from NMI,
5746          * "blocked by NMI" bit has to be set before next VM entry.
5747          * There are errata that may cause this bit to not be set:
5748          * AAK134, BY25.
5749          */
5750         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5751                         cpu_has_virtual_nmis() &&
5752                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5753                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5754
5755         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5756         trace_kvm_page_fault(gpa, exit_qualification);
5757
5758         /* It is a write fault? */
5759         error_code = exit_qualification & PFERR_WRITE_MASK;
5760         /* It is a fetch fault? */
5761         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5762         /* ept page table is present? */
5763         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5764
5765         vcpu->arch.exit_qualification = exit_qualification;
5766
5767         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5768 }
5769
5770 static u64 ept_rsvd_mask(u64 spte, int level)
5771 {
5772         int i;
5773         u64 mask = 0;
5774
5775         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5776                 mask |= (1ULL << i);
5777
5778         if (level == 4)
5779                 /* bits 7:3 reserved */
5780                 mask |= 0xf8;
5781         else if (spte & (1ULL << 7))
5782                 /*
5783                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5784                  * level == 1 if the hypervisor is using the ignored bit 7.
5785                  */
5786                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5787         else if (level > 1)
5788                 /* bits 6:3 reserved */
5789                 mask |= 0x78;
5790
5791         return mask;
5792 }
5793
5794 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5795                                        int level)
5796 {
5797         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5798
5799         /* 010b (write-only) */
5800         WARN_ON((spte & 0x7) == 0x2);
5801
5802         /* 110b (write/execute) */
5803         WARN_ON((spte & 0x7) == 0x6);
5804
5805         /* 100b (execute-only) and value not supported by logical processor */
5806         if (!cpu_has_vmx_ept_execute_only())
5807                 WARN_ON((spte & 0x7) == 0x4);
5808
5809         /* not 000b */
5810         if ((spte & 0x7)) {
5811                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5812
5813                 if (rsvd_bits != 0) {
5814                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5815                                          __func__, rsvd_bits);
5816                         WARN_ON(1);
5817                 }
5818
5819                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5820                 if ((rsvd_bits & 0x38) == 0) {
5821                         u64 ept_mem_type = (spte & 0x38) >> 3;
5822
5823                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5824                             ept_mem_type == 7) {
5825                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5826                                                 __func__, ept_mem_type);
5827                                 WARN_ON(1);
5828                         }
5829                 }
5830         }
5831 }
5832
5833 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5834 {
5835         u64 sptes[4];
5836         int nr_sptes, i, ret;
5837         gpa_t gpa;
5838
5839         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5840         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5841                 skip_emulated_instruction(vcpu);
5842                 return 1;
5843         }
5844
5845         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5846         if (likely(ret == RET_MMIO_PF_EMULATE))
5847                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5848                                               EMULATE_DONE;
5849
5850         if (unlikely(ret == RET_MMIO_PF_INVALID))
5851                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5852
5853         if (unlikely(ret == RET_MMIO_PF_RETRY))
5854                 return 1;
5855
5856         /* It is the real ept misconfig */
5857         printk(KERN_ERR "EPT: Misconfiguration.\n");
5858         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5859
5860         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5861
5862         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5863                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5864
5865         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5866         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5867
5868         return 0;
5869 }
5870
5871 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5872 {
5873         u32 cpu_based_vm_exec_control;
5874
5875         /* clear pending NMI */
5876         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5877         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5878         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5879         ++vcpu->stat.nmi_window_exits;
5880         kvm_make_request(KVM_REQ_EVENT, vcpu);
5881
5882         return 1;
5883 }
5884
5885 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5886 {
5887         struct vcpu_vmx *vmx = to_vmx(vcpu);
5888         enum emulation_result err = EMULATE_DONE;
5889         int ret = 1;
5890         u32 cpu_exec_ctrl;
5891         bool intr_window_requested;
5892         unsigned count = 130;
5893
5894         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5895         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5896
5897         while (vmx->emulation_required && count-- != 0) {
5898                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5899                         return handle_interrupt_window(&vmx->vcpu);
5900
5901                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5902                         return 1;
5903
5904                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5905
5906                 if (err == EMULATE_USER_EXIT) {
5907                         ++vcpu->stat.mmio_exits;
5908                         ret = 0;
5909                         goto out;
5910                 }
5911
5912                 if (err != EMULATE_DONE) {
5913                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5914                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5915                         vcpu->run->internal.ndata = 0;
5916                         return 0;
5917                 }
5918
5919                 if (vcpu->arch.halt_request) {
5920                         vcpu->arch.halt_request = 0;
5921                         ret = kvm_vcpu_halt(vcpu);
5922                         goto out;
5923                 }
5924
5925                 if (signal_pending(current))
5926                         goto out;
5927                 if (need_resched())
5928                         schedule();
5929         }
5930
5931 out:
5932         return ret;
5933 }
5934
5935 static int __grow_ple_window(int val)
5936 {
5937         if (ple_window_grow < 1)
5938                 return ple_window;
5939
5940         val = min(val, ple_window_actual_max);
5941
5942         if (ple_window_grow < ple_window)
5943                 val *= ple_window_grow;
5944         else
5945                 val += ple_window_grow;
5946
5947         return val;
5948 }
5949
5950 static int __shrink_ple_window(int val, int modifier, int minimum)
5951 {
5952         if (modifier < 1)
5953                 return ple_window;
5954
5955         if (modifier < ple_window)
5956                 val /= modifier;
5957         else
5958                 val -= modifier;
5959
5960         return max(val, minimum);
5961 }
5962
5963 static void grow_ple_window(struct kvm_vcpu *vcpu)
5964 {
5965         struct vcpu_vmx *vmx = to_vmx(vcpu);
5966         int old = vmx->ple_window;
5967
5968         vmx->ple_window = __grow_ple_window(old);
5969
5970         if (vmx->ple_window != old)
5971                 vmx->ple_window_dirty = true;
5972
5973         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5974 }
5975
5976 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5977 {
5978         struct vcpu_vmx *vmx = to_vmx(vcpu);
5979         int old = vmx->ple_window;
5980
5981         vmx->ple_window = __shrink_ple_window(old,
5982                                               ple_window_shrink, ple_window);
5983
5984         if (vmx->ple_window != old)
5985                 vmx->ple_window_dirty = true;
5986
5987         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5988 }
5989
5990 /*
5991  * ple_window_actual_max is computed to be one grow_ple_window() below
5992  * ple_window_max. (See __grow_ple_window for the reason.)
5993  * This prevents overflows, because ple_window_max is int.
5994  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5995  * this process.
5996  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5997  */
5998 static void update_ple_window_actual_max(void)
5999 {
6000         ple_window_actual_max =
6001                         __shrink_ple_window(max(ple_window_max, ple_window),
6002                                             ple_window_grow, INT_MIN);
6003 }
6004
6005 static __init int hardware_setup(void)
6006 {
6007         int r = -ENOMEM, i, msr;
6008
6009         rdmsrl_safe(MSR_EFER, &host_efer);
6010
6011         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6012                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6013
6014         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6015         if (!vmx_io_bitmap_a)
6016                 return r;
6017
6018         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6019         if (!vmx_io_bitmap_b)
6020                 goto out;
6021
6022         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6023         if (!vmx_msr_bitmap_legacy)
6024                 goto out1;
6025
6026         vmx_msr_bitmap_legacy_x2apic =
6027                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6028         if (!vmx_msr_bitmap_legacy_x2apic)
6029                 goto out2;
6030
6031         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6032         if (!vmx_msr_bitmap_longmode)
6033                 goto out3;
6034
6035         vmx_msr_bitmap_longmode_x2apic =
6036                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6037         if (!vmx_msr_bitmap_longmode_x2apic)
6038                 goto out4;
6039
6040         if (nested) {
6041                 vmx_msr_bitmap_nested =
6042                         (unsigned long *)__get_free_page(GFP_KERNEL);
6043                 if (!vmx_msr_bitmap_nested)
6044                         goto out5;
6045         }
6046
6047         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6048         if (!vmx_vmread_bitmap)
6049                 goto out6;
6050
6051         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6052         if (!vmx_vmwrite_bitmap)
6053                 goto out7;
6054
6055         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6056         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6057
6058         /*
6059          * Allow direct access to the PC debug port (it is often used for I/O
6060          * delays, but the vmexits simply slow things down).
6061          */
6062         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6063         clear_bit(0x80, vmx_io_bitmap_a);
6064
6065         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6066
6067         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6068         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6069         if (nested)
6070                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6071
6072         if (setup_vmcs_config(&vmcs_config) < 0) {
6073                 r = -EIO;
6074                 goto out8;
6075         }
6076
6077         if (boot_cpu_has(X86_FEATURE_NX))
6078                 kvm_enable_efer_bits(EFER_NX);
6079
6080         if (!cpu_has_vmx_vpid())
6081                 enable_vpid = 0;
6082         if (!cpu_has_vmx_shadow_vmcs())
6083                 enable_shadow_vmcs = 0;
6084         if (enable_shadow_vmcs)
6085                 init_vmcs_shadow_fields();
6086
6087         if (!cpu_has_vmx_ept() ||
6088             !cpu_has_vmx_ept_4levels()) {
6089                 enable_ept = 0;
6090                 enable_unrestricted_guest = 0;
6091                 enable_ept_ad_bits = 0;
6092         }
6093
6094         if (!cpu_has_vmx_ept_ad_bits())
6095                 enable_ept_ad_bits = 0;
6096
6097         if (!cpu_has_vmx_unrestricted_guest())
6098                 enable_unrestricted_guest = 0;
6099
6100         if (!cpu_has_vmx_flexpriority())
6101                 flexpriority_enabled = 0;
6102
6103         /*
6104          * set_apic_access_page_addr() is used to reload apic access
6105          * page upon invalidation.  No need to do anything if not
6106          * using the APIC_ACCESS_ADDR VMCS field.
6107          */
6108         if (!flexpriority_enabled)
6109                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6110
6111         if (!cpu_has_vmx_tpr_shadow())
6112                 kvm_x86_ops->update_cr8_intercept = NULL;
6113
6114         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6115                 kvm_disable_largepages();
6116
6117         if (!cpu_has_vmx_ple())
6118                 ple_gap = 0;
6119
6120         if (!cpu_has_vmx_apicv())
6121                 enable_apicv = 0;
6122
6123         if (enable_apicv)
6124                 kvm_x86_ops->update_cr8_intercept = NULL;
6125         else {
6126                 kvm_x86_ops->hwapic_irr_update = NULL;
6127                 kvm_x86_ops->hwapic_isr_update = NULL;
6128                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6129                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6130         }
6131
6132         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6133         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6134         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6135         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6136         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6137         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6138         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6139
6140         memcpy(vmx_msr_bitmap_legacy_x2apic,
6141                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6142         memcpy(vmx_msr_bitmap_longmode_x2apic,
6143                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6144
6145         if (enable_apicv) {
6146                 for (msr = 0x800; msr <= 0x8ff; msr++)
6147                         vmx_disable_intercept_msr_read_x2apic(msr);
6148
6149                 /* According SDM, in x2apic mode, the whole id reg is used.
6150                  * But in KVM, it only use the highest eight bits. Need to
6151                  * intercept it */
6152                 vmx_enable_intercept_msr_read_x2apic(0x802);
6153                 /* TMCCT */
6154                 vmx_enable_intercept_msr_read_x2apic(0x839);
6155                 /* TPR */
6156                 vmx_disable_intercept_msr_write_x2apic(0x808);
6157                 /* EOI */
6158                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6159                 /* SELF-IPI */
6160                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6161         }
6162
6163         if (enable_ept) {
6164                 kvm_mmu_set_mask_ptes(0ull,
6165                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6166                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6167                         0ull, VMX_EPT_EXECUTABLE_MASK);
6168                 ept_set_mmio_spte_mask();
6169                 kvm_enable_tdp();
6170         } else
6171                 kvm_disable_tdp();
6172
6173         update_ple_window_actual_max();
6174
6175         /*
6176          * Only enable PML when hardware supports PML feature, and both EPT
6177          * and EPT A/D bit features are enabled -- PML depends on them to work.
6178          */
6179         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6180                 enable_pml = 0;
6181
6182         if (!enable_pml) {
6183                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6184                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6185                 kvm_x86_ops->flush_log_dirty = NULL;
6186                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6187         }
6188
6189         return alloc_kvm_area();
6190
6191 out8:
6192         free_page((unsigned long)vmx_vmwrite_bitmap);
6193 out7:
6194         free_page((unsigned long)vmx_vmread_bitmap);
6195 out6:
6196         if (nested)
6197                 free_page((unsigned long)vmx_msr_bitmap_nested);
6198 out5:
6199         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6200 out4:
6201         free_page((unsigned long)vmx_msr_bitmap_longmode);
6202 out3:
6203         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6204 out2:
6205         free_page((unsigned long)vmx_msr_bitmap_legacy);
6206 out1:
6207         free_page((unsigned long)vmx_io_bitmap_b);
6208 out:
6209         free_page((unsigned long)vmx_io_bitmap_a);
6210
6211     return r;
6212 }
6213
6214 static __exit void hardware_unsetup(void)
6215 {
6216         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6217         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6218         free_page((unsigned long)vmx_msr_bitmap_legacy);
6219         free_page((unsigned long)vmx_msr_bitmap_longmode);
6220         free_page((unsigned long)vmx_io_bitmap_b);
6221         free_page((unsigned long)vmx_io_bitmap_a);
6222         free_page((unsigned long)vmx_vmwrite_bitmap);
6223         free_page((unsigned long)vmx_vmread_bitmap);
6224         if (nested)
6225                 free_page((unsigned long)vmx_msr_bitmap_nested);
6226
6227         free_kvm_area();
6228 }
6229
6230 /*
6231  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6232  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6233  */
6234 static int handle_pause(struct kvm_vcpu *vcpu)
6235 {
6236         if (ple_gap)
6237                 grow_ple_window(vcpu);
6238
6239         skip_emulated_instruction(vcpu);
6240         kvm_vcpu_on_spin(vcpu);
6241
6242         return 1;
6243 }
6244
6245 static int handle_nop(struct kvm_vcpu *vcpu)
6246 {
6247         skip_emulated_instruction(vcpu);
6248         return 1;
6249 }
6250
6251 static int handle_mwait(struct kvm_vcpu *vcpu)
6252 {
6253         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6254         return handle_nop(vcpu);
6255 }
6256
6257 static int handle_monitor(struct kvm_vcpu *vcpu)
6258 {
6259         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6260         return handle_nop(vcpu);
6261 }
6262
6263 /*
6264  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6265  * We could reuse a single VMCS for all the L2 guests, but we also want the
6266  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6267  * allows keeping them loaded on the processor, and in the future will allow
6268  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6269  * every entry if they never change.
6270  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6271  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6272  *
6273  * The following functions allocate and free a vmcs02 in this pool.
6274  */
6275
6276 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6277 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6278 {
6279         struct vmcs02_list *item;
6280         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6281                 if (item->vmptr == vmx->nested.current_vmptr) {
6282                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6283                         return &item->vmcs02;
6284                 }
6285
6286         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6287                 /* Recycle the least recently used VMCS. */
6288                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6289                         struct vmcs02_list, list);
6290                 item->vmptr = vmx->nested.current_vmptr;
6291                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6292                 return &item->vmcs02;
6293         }
6294
6295         /* Create a new VMCS */
6296         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6297         if (!item)
6298                 return NULL;
6299         item->vmcs02.vmcs = alloc_vmcs();
6300         if (!item->vmcs02.vmcs) {
6301                 kfree(item);
6302                 return NULL;
6303         }
6304         loaded_vmcs_init(&item->vmcs02);
6305         item->vmptr = vmx->nested.current_vmptr;
6306         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6307         vmx->nested.vmcs02_num++;
6308         return &item->vmcs02;
6309 }
6310
6311 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6312 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6313 {
6314         struct vmcs02_list *item;
6315         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6316                 if (item->vmptr == vmptr) {
6317                         free_loaded_vmcs(&item->vmcs02);
6318                         list_del(&item->list);
6319                         kfree(item);
6320                         vmx->nested.vmcs02_num--;
6321                         return;
6322                 }
6323 }
6324
6325 /*
6326  * Free all VMCSs saved for this vcpu, except the one pointed by
6327  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6328  * must be &vmx->vmcs01.
6329  */
6330 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6331 {
6332         struct vmcs02_list *item, *n;
6333
6334         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6335         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6336                 /*
6337                  * Something will leak if the above WARN triggers.  Better than
6338                  * a use-after-free.
6339                  */
6340                 if (vmx->loaded_vmcs == &item->vmcs02)
6341                         continue;
6342
6343                 free_loaded_vmcs(&item->vmcs02);
6344                 list_del(&item->list);
6345                 kfree(item);
6346                 vmx->nested.vmcs02_num--;
6347         }
6348 }
6349
6350 /*
6351  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6352  * set the success or error code of an emulated VMX instruction, as specified
6353  * by Vol 2B, VMX Instruction Reference, "Conventions".
6354  */
6355 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6356 {
6357         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6358                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6359                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6360 }
6361
6362 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6363 {
6364         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6365                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6366                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6367                         | X86_EFLAGS_CF);
6368 }
6369
6370 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6371                                         u32 vm_instruction_error)
6372 {
6373         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6374                 /*
6375                  * failValid writes the error number to the current VMCS, which
6376                  * can't be done there isn't a current VMCS.
6377                  */
6378                 nested_vmx_failInvalid(vcpu);
6379                 return;
6380         }
6381         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6382                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6383                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6384                         | X86_EFLAGS_ZF);
6385         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6386         /*
6387          * We don't need to force a shadow sync because
6388          * VM_INSTRUCTION_ERROR is not shadowed
6389          */
6390 }
6391
6392 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6393 {
6394         /* TODO: not to reset guest simply here. */
6395         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6396         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6397 }
6398
6399 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6400 {
6401         struct vcpu_vmx *vmx =
6402                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6403
6404         vmx->nested.preemption_timer_expired = true;
6405         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6406         kvm_vcpu_kick(&vmx->vcpu);
6407
6408         return HRTIMER_NORESTART;
6409 }
6410
6411 /*
6412  * Decode the memory-address operand of a vmx instruction, as recorded on an
6413  * exit caused by such an instruction (run by a guest hypervisor).
6414  * On success, returns 0. When the operand is invalid, returns 1 and throws
6415  * #UD or #GP.
6416  */
6417 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6418                                  unsigned long exit_qualification,
6419                                  u32 vmx_instruction_info, gva_t *ret)
6420 {
6421         /*
6422          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6423          * Execution", on an exit, vmx_instruction_info holds most of the
6424          * addressing components of the operand. Only the displacement part
6425          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6426          * For how an actual address is calculated from all these components,
6427          * refer to Vol. 1, "Operand Addressing".
6428          */
6429         int  scaling = vmx_instruction_info & 3;
6430         int  addr_size = (vmx_instruction_info >> 7) & 7;
6431         bool is_reg = vmx_instruction_info & (1u << 10);
6432         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6433         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6434         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6435         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6436         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6437
6438         if (is_reg) {
6439                 kvm_queue_exception(vcpu, UD_VECTOR);
6440                 return 1;
6441         }
6442
6443         /* Addr = segment_base + offset */
6444         /* offset = base + [index * scale] + displacement */
6445         *ret = vmx_get_segment_base(vcpu, seg_reg);
6446         if (base_is_valid)
6447                 *ret += kvm_register_read(vcpu, base_reg);
6448         if (index_is_valid)
6449                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6450         *ret += exit_qualification; /* holds the displacement */
6451
6452         if (addr_size == 1) /* 32 bit */
6453                 *ret &= 0xffffffff;
6454
6455         /*
6456          * TODO: throw #GP (and return 1) in various cases that the VM*
6457          * instructions require it - e.g., offset beyond segment limit,
6458          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6459          * address, and so on. Currently these are not checked.
6460          */
6461         return 0;
6462 }
6463
6464 /*
6465  * This function performs the various checks including
6466  * - if it's 4KB aligned
6467  * - No bits beyond the physical address width are set
6468  * - Returns 0 on success or else 1
6469  * (Intel SDM Section 30.3)
6470  */
6471 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6472                                   gpa_t *vmpointer)
6473 {
6474         gva_t gva;
6475         gpa_t vmptr;
6476         struct x86_exception e;
6477         struct page *page;
6478         struct vcpu_vmx *vmx = to_vmx(vcpu);
6479         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6480
6481         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6482                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6483                 return 1;
6484
6485         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6486                                 sizeof(vmptr), &e)) {
6487                 kvm_inject_page_fault(vcpu, &e);
6488                 return 1;
6489         }
6490
6491         switch (exit_reason) {
6492         case EXIT_REASON_VMON:
6493                 /*
6494                  * SDM 3: 24.11.5
6495                  * The first 4 bytes of VMXON region contain the supported
6496                  * VMCS revision identifier
6497                  *
6498                  * Note - IA32_VMX_BASIC[48] will never be 1
6499                  * for the nested case;
6500                  * which replaces physical address width with 32
6501                  *
6502                  */
6503                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6504                         nested_vmx_failInvalid(vcpu);
6505                         skip_emulated_instruction(vcpu);
6506                         return 1;
6507                 }
6508
6509                 page = nested_get_page(vcpu, vmptr);
6510                 if (page == NULL ||
6511                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6512                         nested_vmx_failInvalid(vcpu);
6513                         kunmap(page);
6514                         skip_emulated_instruction(vcpu);
6515                         return 1;
6516                 }
6517                 kunmap(page);
6518                 vmx->nested.vmxon_ptr = vmptr;
6519                 break;
6520         case EXIT_REASON_VMCLEAR:
6521                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6522                         nested_vmx_failValid(vcpu,
6523                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6524                         skip_emulated_instruction(vcpu);
6525                         return 1;
6526                 }
6527
6528                 if (vmptr == vmx->nested.vmxon_ptr) {
6529                         nested_vmx_failValid(vcpu,
6530                                              VMXERR_VMCLEAR_VMXON_POINTER);
6531                         skip_emulated_instruction(vcpu);
6532                         return 1;
6533                 }
6534                 break;
6535         case EXIT_REASON_VMPTRLD:
6536                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6537                         nested_vmx_failValid(vcpu,
6538                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6539                         skip_emulated_instruction(vcpu);
6540                         return 1;
6541                 }
6542
6543                 if (vmptr == vmx->nested.vmxon_ptr) {
6544                         nested_vmx_failValid(vcpu,
6545                                              VMXERR_VMCLEAR_VMXON_POINTER);
6546                         skip_emulated_instruction(vcpu);
6547                         return 1;
6548                 }
6549                 break;
6550         default:
6551                 return 1; /* shouldn't happen */
6552         }
6553
6554         if (vmpointer)
6555                 *vmpointer = vmptr;
6556         return 0;
6557 }
6558
6559 /*
6560  * Emulate the VMXON instruction.
6561  * Currently, we just remember that VMX is active, and do not save or even
6562  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6563  * do not currently need to store anything in that guest-allocated memory
6564  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6565  * argument is different from the VMXON pointer (which the spec says they do).
6566  */
6567 static int handle_vmon(struct kvm_vcpu *vcpu)
6568 {
6569         struct kvm_segment cs;
6570         struct vcpu_vmx *vmx = to_vmx(vcpu);
6571         struct vmcs *shadow_vmcs;
6572         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6573                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6574
6575         /* The Intel VMX Instruction Reference lists a bunch of bits that
6576          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6577          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6578          * Otherwise, we should fail with #UD. We test these now:
6579          */
6580         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6581             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6582             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6583                 kvm_queue_exception(vcpu, UD_VECTOR);
6584                 return 1;
6585         }
6586
6587         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6588         if (is_long_mode(vcpu) && !cs.l) {
6589                 kvm_queue_exception(vcpu, UD_VECTOR);
6590                 return 1;
6591         }
6592
6593         if (vmx_get_cpl(vcpu)) {
6594                 kvm_inject_gp(vcpu, 0);
6595                 return 1;
6596         }
6597
6598         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6599                 return 1;
6600
6601         if (vmx->nested.vmxon) {
6602                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6603                 skip_emulated_instruction(vcpu);
6604                 return 1;
6605         }
6606
6607         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6608                         != VMXON_NEEDED_FEATURES) {
6609                 kvm_inject_gp(vcpu, 0);
6610                 return 1;
6611         }
6612
6613         if (enable_shadow_vmcs) {
6614                 shadow_vmcs = alloc_vmcs();
6615                 if (!shadow_vmcs)
6616                         return -ENOMEM;
6617                 /* mark vmcs as shadow */
6618                 shadow_vmcs->revision_id |= (1u << 31);
6619                 /* init shadow vmcs */
6620                 vmcs_clear(shadow_vmcs);
6621                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6622         }
6623
6624         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6625         vmx->nested.vmcs02_num = 0;
6626
6627         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6628                      HRTIMER_MODE_REL);
6629         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6630
6631         vmx->nested.vmxon = true;
6632
6633         skip_emulated_instruction(vcpu);
6634         nested_vmx_succeed(vcpu);
6635         return 1;
6636 }
6637
6638 /*
6639  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6640  * for running VMX instructions (except VMXON, whose prerequisites are
6641  * slightly different). It also specifies what exception to inject otherwise.
6642  */
6643 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6644 {
6645         struct kvm_segment cs;
6646         struct vcpu_vmx *vmx = to_vmx(vcpu);
6647
6648         if (!vmx->nested.vmxon) {
6649                 kvm_queue_exception(vcpu, UD_VECTOR);
6650                 return 0;
6651         }
6652
6653         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6654         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6655             (is_long_mode(vcpu) && !cs.l)) {
6656                 kvm_queue_exception(vcpu, UD_VECTOR);
6657                 return 0;
6658         }
6659
6660         if (vmx_get_cpl(vcpu)) {
6661                 kvm_inject_gp(vcpu, 0);
6662                 return 0;
6663         }
6664
6665         return 1;
6666 }
6667
6668 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6669 {
6670         u32 exec_control;
6671         if (vmx->nested.current_vmptr == -1ull)
6672                 return;
6673
6674         /* current_vmptr and current_vmcs12 are always set/reset together */
6675         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6676                 return;
6677
6678         if (enable_shadow_vmcs) {
6679                 /* copy to memory all shadowed fields in case
6680                    they were modified */
6681                 copy_shadow_to_vmcs12(vmx);
6682                 vmx->nested.sync_shadow_vmcs = false;
6683                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6684                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6685                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6686                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6687         }
6688         vmx->nested.posted_intr_nv = -1;
6689         kunmap(vmx->nested.current_vmcs12_page);
6690         nested_release_page(vmx->nested.current_vmcs12_page);
6691         vmx->nested.current_vmptr = -1ull;
6692         vmx->nested.current_vmcs12 = NULL;
6693 }
6694
6695 /*
6696  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6697  * just stops using VMX.
6698  */
6699 static void free_nested(struct vcpu_vmx *vmx)
6700 {
6701         if (!vmx->nested.vmxon)
6702                 return;
6703
6704         vmx->nested.vmxon = false;
6705         nested_release_vmcs12(vmx);
6706         if (enable_shadow_vmcs)
6707                 free_vmcs(vmx->nested.current_shadow_vmcs);
6708         /* Unpin physical memory we referred to in current vmcs02 */
6709         if (vmx->nested.apic_access_page) {
6710                 nested_release_page(vmx->nested.apic_access_page);
6711                 vmx->nested.apic_access_page = NULL;
6712         }
6713         if (vmx->nested.virtual_apic_page) {
6714                 nested_release_page(vmx->nested.virtual_apic_page);
6715                 vmx->nested.virtual_apic_page = NULL;
6716         }
6717         if (vmx->nested.pi_desc_page) {
6718                 kunmap(vmx->nested.pi_desc_page);
6719                 nested_release_page(vmx->nested.pi_desc_page);
6720                 vmx->nested.pi_desc_page = NULL;
6721                 vmx->nested.pi_desc = NULL;
6722         }
6723
6724         nested_free_all_saved_vmcss(vmx);
6725 }
6726
6727 /* Emulate the VMXOFF instruction */
6728 static int handle_vmoff(struct kvm_vcpu *vcpu)
6729 {
6730         if (!nested_vmx_check_permission(vcpu))
6731                 return 1;
6732         free_nested(to_vmx(vcpu));
6733         skip_emulated_instruction(vcpu);
6734         nested_vmx_succeed(vcpu);
6735         return 1;
6736 }
6737
6738 /* Emulate the VMCLEAR instruction */
6739 static int handle_vmclear(struct kvm_vcpu *vcpu)
6740 {
6741         struct vcpu_vmx *vmx = to_vmx(vcpu);
6742         gpa_t vmptr;
6743         struct vmcs12 *vmcs12;
6744         struct page *page;
6745
6746         if (!nested_vmx_check_permission(vcpu))
6747                 return 1;
6748
6749         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6750                 return 1;
6751
6752         if (vmptr == vmx->nested.current_vmptr)
6753                 nested_release_vmcs12(vmx);
6754
6755         page = nested_get_page(vcpu, vmptr);
6756         if (page == NULL) {
6757                 /*
6758                  * For accurate processor emulation, VMCLEAR beyond available
6759                  * physical memory should do nothing at all. However, it is
6760                  * possible that a nested vmx bug, not a guest hypervisor bug,
6761                  * resulted in this case, so let's shut down before doing any
6762                  * more damage:
6763                  */
6764                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6765                 return 1;
6766         }
6767         vmcs12 = kmap(page);
6768         vmcs12->launch_state = 0;
6769         kunmap(page);
6770         nested_release_page(page);
6771
6772         nested_free_vmcs02(vmx, vmptr);
6773
6774         skip_emulated_instruction(vcpu);
6775         nested_vmx_succeed(vcpu);
6776         return 1;
6777 }
6778
6779 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6780
6781 /* Emulate the VMLAUNCH instruction */
6782 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6783 {
6784         return nested_vmx_run(vcpu, true);
6785 }
6786
6787 /* Emulate the VMRESUME instruction */
6788 static int handle_vmresume(struct kvm_vcpu *vcpu)
6789 {
6790
6791         return nested_vmx_run(vcpu, false);
6792 }
6793
6794 enum vmcs_field_type {
6795         VMCS_FIELD_TYPE_U16 = 0,
6796         VMCS_FIELD_TYPE_U64 = 1,
6797         VMCS_FIELD_TYPE_U32 = 2,
6798         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6799 };
6800
6801 static inline int vmcs_field_type(unsigned long field)
6802 {
6803         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6804                 return VMCS_FIELD_TYPE_U32;
6805         return (field >> 13) & 0x3 ;
6806 }
6807
6808 static inline int vmcs_field_readonly(unsigned long field)
6809 {
6810         return (((field >> 10) & 0x3) == 1);
6811 }
6812
6813 /*
6814  * Read a vmcs12 field. Since these can have varying lengths and we return
6815  * one type, we chose the biggest type (u64) and zero-extend the return value
6816  * to that size. Note that the caller, handle_vmread, might need to use only
6817  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6818  * 64-bit fields are to be returned).
6819  */
6820 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6821                                   unsigned long field, u64 *ret)
6822 {
6823         short offset = vmcs_field_to_offset(field);
6824         char *p;
6825
6826         if (offset < 0)
6827                 return offset;
6828
6829         p = ((char *)(get_vmcs12(vcpu))) + offset;
6830
6831         switch (vmcs_field_type(field)) {
6832         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6833                 *ret = *((natural_width *)p);
6834                 return 0;
6835         case VMCS_FIELD_TYPE_U16:
6836                 *ret = *((u16 *)p);
6837                 return 0;
6838         case VMCS_FIELD_TYPE_U32:
6839                 *ret = *((u32 *)p);
6840                 return 0;
6841         case VMCS_FIELD_TYPE_U64:
6842                 *ret = *((u64 *)p);
6843                 return 0;
6844         default:
6845                 WARN_ON(1);
6846                 return -ENOENT;
6847         }
6848 }
6849
6850
6851 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6852                                    unsigned long field, u64 field_value){
6853         short offset = vmcs_field_to_offset(field);
6854         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6855         if (offset < 0)
6856                 return offset;
6857
6858         switch (vmcs_field_type(field)) {
6859         case VMCS_FIELD_TYPE_U16:
6860                 *(u16 *)p = field_value;
6861                 return 0;
6862         case VMCS_FIELD_TYPE_U32:
6863                 *(u32 *)p = field_value;
6864                 return 0;
6865         case VMCS_FIELD_TYPE_U64:
6866                 *(u64 *)p = field_value;
6867                 return 0;
6868         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6869                 *(natural_width *)p = field_value;
6870                 return 0;
6871         default:
6872                 WARN_ON(1);
6873                 return -ENOENT;
6874         }
6875
6876 }
6877
6878 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6879 {
6880         int i;
6881         unsigned long field;
6882         u64 field_value;
6883         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6884         const unsigned long *fields = shadow_read_write_fields;
6885         const int num_fields = max_shadow_read_write_fields;
6886
6887         preempt_disable();
6888
6889         vmcs_load(shadow_vmcs);
6890
6891         for (i = 0; i < num_fields; i++) {
6892                 field = fields[i];
6893                 switch (vmcs_field_type(field)) {
6894                 case VMCS_FIELD_TYPE_U16:
6895                         field_value = vmcs_read16(field);
6896                         break;
6897                 case VMCS_FIELD_TYPE_U32:
6898                         field_value = vmcs_read32(field);
6899                         break;
6900                 case VMCS_FIELD_TYPE_U64:
6901                         field_value = vmcs_read64(field);
6902                         break;
6903                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6904                         field_value = vmcs_readl(field);
6905                         break;
6906                 default:
6907                         WARN_ON(1);
6908                         continue;
6909                 }
6910                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6911         }
6912
6913         vmcs_clear(shadow_vmcs);
6914         vmcs_load(vmx->loaded_vmcs->vmcs);
6915
6916         preempt_enable();
6917 }
6918
6919 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6920 {
6921         const unsigned long *fields[] = {
6922                 shadow_read_write_fields,
6923                 shadow_read_only_fields
6924         };
6925         const int max_fields[] = {
6926                 max_shadow_read_write_fields,
6927                 max_shadow_read_only_fields
6928         };
6929         int i, q;
6930         unsigned long field;
6931         u64 field_value = 0;
6932         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6933
6934         vmcs_load(shadow_vmcs);
6935
6936         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6937                 for (i = 0; i < max_fields[q]; i++) {
6938                         field = fields[q][i];
6939                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6940
6941                         switch (vmcs_field_type(field)) {
6942                         case VMCS_FIELD_TYPE_U16:
6943                                 vmcs_write16(field, (u16)field_value);
6944                                 break;
6945                         case VMCS_FIELD_TYPE_U32:
6946                                 vmcs_write32(field, (u32)field_value);
6947                                 break;
6948                         case VMCS_FIELD_TYPE_U64:
6949                                 vmcs_write64(field, (u64)field_value);
6950                                 break;
6951                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6952                                 vmcs_writel(field, (long)field_value);
6953                                 break;
6954                         default:
6955                                 WARN_ON(1);
6956                                 break;
6957                         }
6958                 }
6959         }
6960
6961         vmcs_clear(shadow_vmcs);
6962         vmcs_load(vmx->loaded_vmcs->vmcs);
6963 }
6964
6965 /*
6966  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6967  * used before) all generate the same failure when it is missing.
6968  */
6969 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6970 {
6971         struct vcpu_vmx *vmx = to_vmx(vcpu);
6972         if (vmx->nested.current_vmptr == -1ull) {
6973                 nested_vmx_failInvalid(vcpu);
6974                 skip_emulated_instruction(vcpu);
6975                 return 0;
6976         }
6977         return 1;
6978 }
6979
6980 static int handle_vmread(struct kvm_vcpu *vcpu)
6981 {
6982         unsigned long field;
6983         u64 field_value;
6984         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6985         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6986         gva_t gva = 0;
6987
6988         if (!nested_vmx_check_permission(vcpu) ||
6989             !nested_vmx_check_vmcs12(vcpu))
6990                 return 1;
6991
6992         /* Decode instruction info and find the field to read */
6993         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6994         /* Read the field, zero-extended to a u64 field_value */
6995         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6996                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6997                 skip_emulated_instruction(vcpu);
6998                 return 1;
6999         }
7000         /*
7001          * Now copy part of this value to register or memory, as requested.
7002          * Note that the number of bits actually copied is 32 or 64 depending
7003          * on the guest's mode (32 or 64 bit), not on the given field's length.
7004          */
7005         if (vmx_instruction_info & (1u << 10)) {
7006                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7007                         field_value);
7008         } else {
7009                 if (get_vmx_mem_address(vcpu, exit_qualification,
7010                                 vmx_instruction_info, &gva))
7011                         return 1;
7012                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7013                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7014                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7015         }
7016
7017         nested_vmx_succeed(vcpu);
7018         skip_emulated_instruction(vcpu);
7019         return 1;
7020 }
7021
7022
7023 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7024 {
7025         unsigned long field;
7026         gva_t gva;
7027         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7028         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7029         /* The value to write might be 32 or 64 bits, depending on L1's long
7030          * mode, and eventually we need to write that into a field of several
7031          * possible lengths. The code below first zero-extends the value to 64
7032          * bit (field_value), and then copies only the approriate number of
7033          * bits into the vmcs12 field.
7034          */
7035         u64 field_value = 0;
7036         struct x86_exception e;
7037
7038         if (!nested_vmx_check_permission(vcpu) ||
7039             !nested_vmx_check_vmcs12(vcpu))
7040                 return 1;
7041
7042         if (vmx_instruction_info & (1u << 10))
7043                 field_value = kvm_register_readl(vcpu,
7044                         (((vmx_instruction_info) >> 3) & 0xf));
7045         else {
7046                 if (get_vmx_mem_address(vcpu, exit_qualification,
7047                                 vmx_instruction_info, &gva))
7048                         return 1;
7049                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7050                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7051                         kvm_inject_page_fault(vcpu, &e);
7052                         return 1;
7053                 }
7054         }
7055
7056
7057         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7058         if (vmcs_field_readonly(field)) {
7059                 nested_vmx_failValid(vcpu,
7060                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7061                 skip_emulated_instruction(vcpu);
7062                 return 1;
7063         }
7064
7065         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7066                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7067                 skip_emulated_instruction(vcpu);
7068                 return 1;
7069         }
7070
7071         nested_vmx_succeed(vcpu);
7072         skip_emulated_instruction(vcpu);
7073         return 1;
7074 }
7075
7076 /* Emulate the VMPTRLD instruction */
7077 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7078 {
7079         struct vcpu_vmx *vmx = to_vmx(vcpu);
7080         gpa_t vmptr;
7081         u32 exec_control;
7082
7083         if (!nested_vmx_check_permission(vcpu))
7084                 return 1;
7085
7086         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7087                 return 1;
7088
7089         if (vmx->nested.current_vmptr != vmptr) {
7090                 struct vmcs12 *new_vmcs12;
7091                 struct page *page;
7092                 page = nested_get_page(vcpu, vmptr);
7093                 if (page == NULL) {
7094                         nested_vmx_failInvalid(vcpu);
7095                         skip_emulated_instruction(vcpu);
7096                         return 1;
7097                 }
7098                 new_vmcs12 = kmap(page);
7099                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7100                         kunmap(page);
7101                         nested_release_page_clean(page);
7102                         nested_vmx_failValid(vcpu,
7103                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7104                         skip_emulated_instruction(vcpu);
7105                         return 1;
7106                 }
7107
7108                 nested_release_vmcs12(vmx);
7109                 vmx->nested.current_vmptr = vmptr;
7110                 vmx->nested.current_vmcs12 = new_vmcs12;
7111                 vmx->nested.current_vmcs12_page = page;
7112                 if (enable_shadow_vmcs) {
7113                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7114                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7115                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7116                         vmcs_write64(VMCS_LINK_POINTER,
7117                                      __pa(vmx->nested.current_shadow_vmcs));
7118                         vmx->nested.sync_shadow_vmcs = true;
7119                 }
7120         }
7121
7122         nested_vmx_succeed(vcpu);
7123         skip_emulated_instruction(vcpu);
7124         return 1;
7125 }
7126
7127 /* Emulate the VMPTRST instruction */
7128 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7129 {
7130         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7131         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7132         gva_t vmcs_gva;
7133         struct x86_exception e;
7134
7135         if (!nested_vmx_check_permission(vcpu))
7136                 return 1;
7137
7138         if (get_vmx_mem_address(vcpu, exit_qualification,
7139                         vmx_instruction_info, &vmcs_gva))
7140                 return 1;
7141         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7142         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7143                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7144                                  sizeof(u64), &e)) {
7145                 kvm_inject_page_fault(vcpu, &e);
7146                 return 1;
7147         }
7148         nested_vmx_succeed(vcpu);
7149         skip_emulated_instruction(vcpu);
7150         return 1;
7151 }
7152
7153 /* Emulate the INVEPT instruction */
7154 static int handle_invept(struct kvm_vcpu *vcpu)
7155 {
7156         struct vcpu_vmx *vmx = to_vmx(vcpu);
7157         u32 vmx_instruction_info, types;
7158         unsigned long type;
7159         gva_t gva;
7160         struct x86_exception e;
7161         struct {
7162                 u64 eptp, gpa;
7163         } operand;
7164
7165         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7166               SECONDARY_EXEC_ENABLE_EPT) ||
7167             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7168                 kvm_queue_exception(vcpu, UD_VECTOR);
7169                 return 1;
7170         }
7171
7172         if (!nested_vmx_check_permission(vcpu))
7173                 return 1;
7174
7175         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7176                 kvm_queue_exception(vcpu, UD_VECTOR);
7177                 return 1;
7178         }
7179
7180         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7181         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7182
7183         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7184
7185         if (!(types & (1UL << type))) {
7186                 nested_vmx_failValid(vcpu,
7187                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7188                 return 1;
7189         }
7190
7191         /* According to the Intel VMX instruction reference, the memory
7192          * operand is read even if it isn't needed (e.g., for type==global)
7193          */
7194         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7195                         vmx_instruction_info, &gva))
7196                 return 1;
7197         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7198                                 sizeof(operand), &e)) {
7199                 kvm_inject_page_fault(vcpu, &e);
7200                 return 1;
7201         }
7202
7203         switch (type) {
7204         case VMX_EPT_EXTENT_GLOBAL:
7205                 kvm_mmu_sync_roots(vcpu);
7206                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7207                 nested_vmx_succeed(vcpu);
7208                 break;
7209         default:
7210                 /* Trap single context invalidation invept calls */
7211                 BUG_ON(1);
7212                 break;
7213         }
7214
7215         skip_emulated_instruction(vcpu);
7216         return 1;
7217 }
7218
7219 static int handle_invvpid(struct kvm_vcpu *vcpu)
7220 {
7221         kvm_queue_exception(vcpu, UD_VECTOR);
7222         return 1;
7223 }
7224
7225 static int handle_pml_full(struct kvm_vcpu *vcpu)
7226 {
7227         unsigned long exit_qualification;
7228
7229         trace_kvm_pml_full(vcpu->vcpu_id);
7230
7231         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7232
7233         /*
7234          * PML buffer FULL happened while executing iret from NMI,
7235          * "blocked by NMI" bit has to be set before next VM entry.
7236          */
7237         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7238                         cpu_has_virtual_nmis() &&
7239                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7240                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7241                                 GUEST_INTR_STATE_NMI);
7242
7243         /*
7244          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7245          * here.., and there's no userspace involvement needed for PML.
7246          */
7247         return 1;
7248 }
7249
7250 /*
7251  * The exit handlers return 1 if the exit was handled fully and guest execution
7252  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7253  * to be done to userspace and return 0.
7254  */
7255 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7256         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7257         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7258         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7259         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7260         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7261         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7262         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7263         [EXIT_REASON_CPUID]                   = handle_cpuid,
7264         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7265         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7266         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7267         [EXIT_REASON_HLT]                     = handle_halt,
7268         [EXIT_REASON_INVD]                    = handle_invd,
7269         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7270         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7271         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7272         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7273         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7274         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7275         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7276         [EXIT_REASON_VMREAD]                  = handle_vmread,
7277         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7278         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7279         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7280         [EXIT_REASON_VMON]                    = handle_vmon,
7281         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7282         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7283         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7284         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7285         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7286         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7287         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7288         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7289         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7290         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7291         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7292         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7293         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7294         [EXIT_REASON_INVEPT]                  = handle_invept,
7295         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7296         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7297         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7298         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7299 };
7300
7301 static const int kvm_vmx_max_exit_handlers =
7302         ARRAY_SIZE(kvm_vmx_exit_handlers);
7303
7304 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7305                                        struct vmcs12 *vmcs12)
7306 {
7307         unsigned long exit_qualification;
7308         gpa_t bitmap, last_bitmap;
7309         unsigned int port;
7310         int size;
7311         u8 b;
7312
7313         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7314                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7315
7316         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7317
7318         port = exit_qualification >> 16;
7319         size = (exit_qualification & 7) + 1;
7320
7321         last_bitmap = (gpa_t)-1;
7322         b = -1;
7323
7324         while (size > 0) {
7325                 if (port < 0x8000)
7326                         bitmap = vmcs12->io_bitmap_a;
7327                 else if (port < 0x10000)
7328                         bitmap = vmcs12->io_bitmap_b;
7329                 else
7330                         return true;
7331                 bitmap += (port & 0x7fff) / 8;
7332
7333                 if (last_bitmap != bitmap)
7334                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7335                                 return true;
7336                 if (b & (1 << (port & 7)))
7337                         return true;
7338
7339                 port++;
7340                 size--;
7341                 last_bitmap = bitmap;
7342         }
7343
7344         return false;
7345 }
7346
7347 /*
7348  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7349  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7350  * disinterest in the current event (read or write a specific MSR) by using an
7351  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7352  */
7353 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7354         struct vmcs12 *vmcs12, u32 exit_reason)
7355 {
7356         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7357         gpa_t bitmap;
7358
7359         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7360                 return true;
7361
7362         /*
7363          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7364          * for the four combinations of read/write and low/high MSR numbers.
7365          * First we need to figure out which of the four to use:
7366          */
7367         bitmap = vmcs12->msr_bitmap;
7368         if (exit_reason == EXIT_REASON_MSR_WRITE)
7369                 bitmap += 2048;
7370         if (msr_index >= 0xc0000000) {
7371                 msr_index -= 0xc0000000;
7372                 bitmap += 1024;
7373         }
7374
7375         /* Then read the msr_index'th bit from this bitmap: */
7376         if (msr_index < 1024*8) {
7377                 unsigned char b;
7378                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7379                         return true;
7380                 return 1 & (b >> (msr_index & 7));
7381         } else
7382                 return true; /* let L1 handle the wrong parameter */
7383 }
7384
7385 /*
7386  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7387  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7388  * intercept (via guest_host_mask etc.) the current event.
7389  */
7390 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7391         struct vmcs12 *vmcs12)
7392 {
7393         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7394         int cr = exit_qualification & 15;
7395         int reg = (exit_qualification >> 8) & 15;
7396         unsigned long val = kvm_register_readl(vcpu, reg);
7397
7398         switch ((exit_qualification >> 4) & 3) {
7399         case 0: /* mov to cr */
7400                 switch (cr) {
7401                 case 0:
7402                         if (vmcs12->cr0_guest_host_mask &
7403                             (val ^ vmcs12->cr0_read_shadow))
7404                                 return true;
7405                         break;
7406                 case 3:
7407                         if ((vmcs12->cr3_target_count >= 1 &&
7408                                         vmcs12->cr3_target_value0 == val) ||
7409                                 (vmcs12->cr3_target_count >= 2 &&
7410                                         vmcs12->cr3_target_value1 == val) ||
7411                                 (vmcs12->cr3_target_count >= 3 &&
7412                                         vmcs12->cr3_target_value2 == val) ||
7413                                 (vmcs12->cr3_target_count >= 4 &&
7414                                         vmcs12->cr3_target_value3 == val))
7415                                 return false;
7416                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7417                                 return true;
7418                         break;
7419                 case 4:
7420                         if (vmcs12->cr4_guest_host_mask &
7421                             (vmcs12->cr4_read_shadow ^ val))
7422                                 return true;
7423                         break;
7424                 case 8:
7425                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7426                                 return true;
7427                         break;
7428                 }
7429                 break;
7430         case 2: /* clts */
7431                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7432                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7433                         return true;
7434                 break;
7435         case 1: /* mov from cr */
7436                 switch (cr) {
7437                 case 3:
7438                         if (vmcs12->cpu_based_vm_exec_control &
7439                             CPU_BASED_CR3_STORE_EXITING)
7440                                 return true;
7441                         break;
7442                 case 8:
7443                         if (vmcs12->cpu_based_vm_exec_control &
7444                             CPU_BASED_CR8_STORE_EXITING)
7445                                 return true;
7446                         break;
7447                 }
7448                 break;
7449         case 3: /* lmsw */
7450                 /*
7451                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7452                  * cr0. Other attempted changes are ignored, with no exit.
7453                  */
7454                 if (vmcs12->cr0_guest_host_mask & 0xe &
7455                     (val ^ vmcs12->cr0_read_shadow))
7456                         return true;
7457                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7458                     !(vmcs12->cr0_read_shadow & 0x1) &&
7459                     (val & 0x1))
7460                         return true;
7461                 break;
7462         }
7463         return false;
7464 }
7465
7466 /*
7467  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7468  * should handle it ourselves in L0 (and then continue L2). Only call this
7469  * when in is_guest_mode (L2).
7470  */
7471 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7472 {
7473         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7474         struct vcpu_vmx *vmx = to_vmx(vcpu);
7475         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7476         u32 exit_reason = vmx->exit_reason;
7477
7478         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7479                                 vmcs_readl(EXIT_QUALIFICATION),
7480                                 vmx->idt_vectoring_info,
7481                                 intr_info,
7482                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7483                                 KVM_ISA_VMX);
7484
7485         if (vmx->nested.nested_run_pending)
7486                 return false;
7487
7488         if (unlikely(vmx->fail)) {
7489                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7490                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7491                 return true;
7492         }
7493
7494         switch (exit_reason) {
7495         case EXIT_REASON_EXCEPTION_NMI:
7496                 if (!is_exception(intr_info))
7497                         return false;
7498                 else if (is_page_fault(intr_info))
7499                         return enable_ept;
7500                 else if (is_no_device(intr_info) &&
7501                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7502                         return false;
7503                 return vmcs12->exception_bitmap &
7504                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7505         case EXIT_REASON_EXTERNAL_INTERRUPT:
7506                 return false;
7507         case EXIT_REASON_TRIPLE_FAULT:
7508                 return true;
7509         case EXIT_REASON_PENDING_INTERRUPT:
7510                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7511         case EXIT_REASON_NMI_WINDOW:
7512                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7513         case EXIT_REASON_TASK_SWITCH:
7514                 return true;
7515         case EXIT_REASON_CPUID:
7516                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7517                         return false;
7518                 return true;
7519         case EXIT_REASON_HLT:
7520                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7521         case EXIT_REASON_INVD:
7522                 return true;
7523         case EXIT_REASON_INVLPG:
7524                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7525         case EXIT_REASON_RDPMC:
7526                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7527         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7528                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7529         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7530         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7531         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7532         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7533         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7534         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7535                 /*
7536                  * VMX instructions trap unconditionally. This allows L1 to
7537                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7538                  */
7539                 return true;
7540         case EXIT_REASON_CR_ACCESS:
7541                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7542         case EXIT_REASON_DR_ACCESS:
7543                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7544         case EXIT_REASON_IO_INSTRUCTION:
7545                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7546         case EXIT_REASON_MSR_READ:
7547         case EXIT_REASON_MSR_WRITE:
7548                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7549         case EXIT_REASON_INVALID_STATE:
7550                 return true;
7551         case EXIT_REASON_MWAIT_INSTRUCTION:
7552                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7553         case EXIT_REASON_MONITOR_INSTRUCTION:
7554                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7555         case EXIT_REASON_PAUSE_INSTRUCTION:
7556                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7557                         nested_cpu_has2(vmcs12,
7558                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7559         case EXIT_REASON_MCE_DURING_VMENTRY:
7560                 return false;
7561         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7562                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7563         case EXIT_REASON_APIC_ACCESS:
7564                 return nested_cpu_has2(vmcs12,
7565                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7566         case EXIT_REASON_APIC_WRITE:
7567         case EXIT_REASON_EOI_INDUCED:
7568                 /* apic_write and eoi_induced should exit unconditionally. */
7569                 return true;
7570         case EXIT_REASON_EPT_VIOLATION:
7571                 /*
7572                  * L0 always deals with the EPT violation. If nested EPT is
7573                  * used, and the nested mmu code discovers that the address is
7574                  * missing in the guest EPT table (EPT12), the EPT violation
7575                  * will be injected with nested_ept_inject_page_fault()
7576                  */
7577                 return false;
7578         case EXIT_REASON_EPT_MISCONFIG:
7579                 /*
7580                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7581                  * table (shadow on EPT) or a merged EPT table that L0 built
7582                  * (EPT on EPT). So any problems with the structure of the
7583                  * table is L0's fault.
7584                  */
7585                 return false;
7586         case EXIT_REASON_WBINVD:
7587                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7588         case EXIT_REASON_XSETBV:
7589                 return true;
7590         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7591                 /*
7592                  * This should never happen, since it is not possible to
7593                  * set XSS to a non-zero value---neither in L1 nor in L2.
7594                  * If if it were, XSS would have to be checked against
7595                  * the XSS exit bitmap in vmcs12.
7596                  */
7597                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7598         default:
7599                 return true;
7600         }
7601 }
7602
7603 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7604 {
7605         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7606         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7607 }
7608
7609 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7610 {
7611         struct page *pml_pg;
7612         u32 exec_control;
7613
7614         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7615         if (!pml_pg)
7616                 return -ENOMEM;
7617
7618         vmx->pml_pg = pml_pg;
7619
7620         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7621         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7622
7623         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7624         exec_control |= SECONDARY_EXEC_ENABLE_PML;
7625         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7626
7627         return 0;
7628 }
7629
7630 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7631 {
7632         u32 exec_control;
7633
7634         ASSERT(vmx->pml_pg);
7635         __free_page(vmx->pml_pg);
7636         vmx->pml_pg = NULL;
7637
7638         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7639         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7640         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7641 }
7642
7643 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7644 {
7645         struct kvm *kvm = vmx->vcpu.kvm;
7646         u64 *pml_buf;
7647         u16 pml_idx;
7648
7649         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7650
7651         /* Do nothing if PML buffer is empty */
7652         if (pml_idx == (PML_ENTITY_NUM - 1))
7653                 return;
7654
7655         /* PML index always points to next available PML buffer entity */
7656         if (pml_idx >= PML_ENTITY_NUM)
7657                 pml_idx = 0;
7658         else
7659                 pml_idx++;
7660
7661         pml_buf = page_address(vmx->pml_pg);
7662         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7663                 u64 gpa;
7664
7665                 gpa = pml_buf[pml_idx];
7666                 WARN_ON(gpa & (PAGE_SIZE - 1));
7667                 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7668         }
7669
7670         /* reset PML index */
7671         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7672 }
7673
7674 /*
7675  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7676  * Called before reporting dirty_bitmap to userspace.
7677  */
7678 static void kvm_flush_pml_buffers(struct kvm *kvm)
7679 {
7680         int i;
7681         struct kvm_vcpu *vcpu;
7682         /*
7683          * We only need to kick vcpu out of guest mode here, as PML buffer
7684          * is flushed at beginning of all VMEXITs, and it's obvious that only
7685          * vcpus running in guest are possible to have unflushed GPAs in PML
7686          * buffer.
7687          */
7688         kvm_for_each_vcpu(i, vcpu, kvm)
7689                 kvm_vcpu_kick(vcpu);
7690 }
7691
7692 static void vmx_dump_sel(char *name, uint32_t sel)
7693 {
7694         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7695                name, vmcs_read32(sel),
7696                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7697                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7698                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7699 }
7700
7701 static void vmx_dump_dtsel(char *name, uint32_t limit)
7702 {
7703         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7704                name, vmcs_read32(limit),
7705                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7706 }
7707
7708 static void dump_vmcs(void)
7709 {
7710         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7711         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7712         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7713         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7714         u32 secondary_exec_control = 0;
7715         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7716         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7717         int i, n;
7718
7719         if (cpu_has_secondary_exec_ctrls())
7720                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7721
7722         pr_err("*** Guest State ***\n");
7723         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7724                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7725                vmcs_readl(CR0_GUEST_HOST_MASK));
7726         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7727                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7728         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7729         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7730             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7731         {
7732                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7733                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7734                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7735                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7736         }
7737         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7738                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7739         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7740                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7741         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7742                vmcs_readl(GUEST_SYSENTER_ESP),
7743                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7744         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7745         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7746         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7747         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7748         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7749         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7750         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7751         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7752         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7753         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7754         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7755             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7756                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7757                        efer, vmcs_readl(GUEST_IA32_PAT));
7758         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7759                vmcs_readl(GUEST_IA32_DEBUGCTL),
7760                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7761         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7762                 pr_err("PerfGlobCtl = 0x%016lx\n",
7763                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7764         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7765                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7766         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7767                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7768                vmcs_read32(GUEST_ACTIVITY_STATE));
7769         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7770                 pr_err("InterruptStatus = %04x\n",
7771                        vmcs_read16(GUEST_INTR_STATUS));
7772
7773         pr_err("*** Host State ***\n");
7774         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7775                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7776         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7777                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7778                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7779                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7780                vmcs_read16(HOST_TR_SELECTOR));
7781         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7782                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7783                vmcs_readl(HOST_TR_BASE));
7784         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7785                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7786         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7787                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7788                vmcs_readl(HOST_CR4));
7789         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7790                vmcs_readl(HOST_IA32_SYSENTER_ESP),
7791                vmcs_read32(HOST_IA32_SYSENTER_CS),
7792                vmcs_readl(HOST_IA32_SYSENTER_EIP));
7793         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7794                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
7795                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7796         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7797                 pr_err("PerfGlobCtl = 0x%016lx\n",
7798                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7799
7800         pr_err("*** Control State ***\n");
7801         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7802                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7803         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7804         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7805                vmcs_read32(EXCEPTION_BITMAP),
7806                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7807                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7808         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7809                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7810                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7811                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7812         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7813                vmcs_read32(VM_EXIT_INTR_INFO),
7814                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7815                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7816         pr_err("        reason=%08x qualification=%016lx\n",
7817                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7818         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7819                vmcs_read32(IDT_VECTORING_INFO_FIELD),
7820                vmcs_read32(IDT_VECTORING_ERROR_CODE));
7821         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7822         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7823                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7824         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7825                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7826         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7827                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7828         n = vmcs_read32(CR3_TARGET_COUNT);
7829         for (i = 0; i + 1 < n; i += 4)
7830                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7831                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7832                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7833         if (i < n)
7834                 pr_err("CR3 target%u=%016lx\n",
7835                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7836         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7837                 pr_err("PLE Gap=%08x Window=%08x\n",
7838                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7839         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7840                 pr_err("Virtual processor ID = 0x%04x\n",
7841                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
7842 }
7843
7844 /*
7845  * The guest has exited.  See if we can fix it or if we need userspace
7846  * assistance.
7847  */
7848 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7849 {
7850         struct vcpu_vmx *vmx = to_vmx(vcpu);
7851         u32 exit_reason = vmx->exit_reason;
7852         u32 vectoring_info = vmx->idt_vectoring_info;
7853
7854         /*
7855          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7856          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7857          * querying dirty_bitmap, we only need to kick all vcpus out of guest
7858          * mode as if vcpus is in root mode, the PML buffer must has been
7859          * flushed already.
7860          */
7861         if (enable_pml)
7862                 vmx_flush_pml_buffer(vmx);
7863
7864         /* If guest state is invalid, start emulating */
7865         if (vmx->emulation_required)
7866                 return handle_invalid_guest_state(vcpu);
7867
7868         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7869                 nested_vmx_vmexit(vcpu, exit_reason,
7870                                   vmcs_read32(VM_EXIT_INTR_INFO),
7871                                   vmcs_readl(EXIT_QUALIFICATION));
7872                 return 1;
7873         }
7874
7875         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7876                 dump_vmcs();
7877                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7878                 vcpu->run->fail_entry.hardware_entry_failure_reason
7879                         = exit_reason;
7880                 return 0;
7881         }
7882
7883         if (unlikely(vmx->fail)) {
7884                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7885                 vcpu->run->fail_entry.hardware_entry_failure_reason
7886                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7887                 return 0;
7888         }
7889
7890         /*
7891          * Note:
7892          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7893          * delivery event since it indicates guest is accessing MMIO.
7894          * The vm-exit can be triggered again after return to guest that
7895          * will cause infinite loop.
7896          */
7897         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7898                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7899                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7900                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7901                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7902                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7903                 vcpu->run->internal.ndata = 2;
7904                 vcpu->run->internal.data[0] = vectoring_info;
7905                 vcpu->run->internal.data[1] = exit_reason;
7906                 return 0;
7907         }
7908
7909         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7910             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7911                                         get_vmcs12(vcpu))))) {
7912                 if (vmx_interrupt_allowed(vcpu)) {
7913                         vmx->soft_vnmi_blocked = 0;
7914                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7915                            vcpu->arch.nmi_pending) {
7916                         /*
7917                          * This CPU don't support us in finding the end of an
7918                          * NMI-blocked window if the guest runs with IRQs
7919                          * disabled. So we pull the trigger after 1 s of
7920                          * futile waiting, but inform the user about this.
7921                          */
7922                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7923                                "state on VCPU %d after 1 s timeout\n",
7924                                __func__, vcpu->vcpu_id);
7925                         vmx->soft_vnmi_blocked = 0;
7926                 }
7927         }
7928
7929         if (exit_reason < kvm_vmx_max_exit_handlers
7930             && kvm_vmx_exit_handlers[exit_reason])
7931                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7932         else {
7933                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7934                 kvm_queue_exception(vcpu, UD_VECTOR);
7935                 return 1;
7936         }
7937 }
7938
7939 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7940 {
7941         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7942
7943         if (is_guest_mode(vcpu) &&
7944                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7945                 return;
7946
7947         if (irr == -1 || tpr < irr) {
7948                 vmcs_write32(TPR_THRESHOLD, 0);
7949                 return;
7950         }
7951
7952         vmcs_write32(TPR_THRESHOLD, irr);
7953 }
7954
7955 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7956 {
7957         u32 sec_exec_control;
7958
7959         /*
7960          * There is not point to enable virtualize x2apic without enable
7961          * apicv
7962          */
7963         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7964                                 !vmx_vm_has_apicv(vcpu->kvm))
7965                 return;
7966
7967         if (!vm_need_tpr_shadow(vcpu->kvm))
7968                 return;
7969
7970         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7971
7972         if (set) {
7973                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7974                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7975         } else {
7976                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7977                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7978         }
7979         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7980
7981         vmx_set_msr_bitmap(vcpu);
7982 }
7983
7984 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7985 {
7986         struct vcpu_vmx *vmx = to_vmx(vcpu);
7987
7988         /*
7989          * Currently we do not handle the nested case where L2 has an
7990          * APIC access page of its own; that page is still pinned.
7991          * Hence, we skip the case where the VCPU is in guest mode _and_
7992          * L1 prepared an APIC access page for L2.
7993          *
7994          * For the case where L1 and L2 share the same APIC access page
7995          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7996          * in the vmcs12), this function will only update either the vmcs01
7997          * or the vmcs02.  If the former, the vmcs02 will be updated by
7998          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7999          * the next L2->L1 exit.
8000          */
8001         if (!is_guest_mode(vcpu) ||
8002             !nested_cpu_has2(vmx->nested.current_vmcs12,
8003                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8004                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8005 }
8006
8007 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8008 {
8009         u16 status;
8010         u8 old;
8011
8012         if (isr == -1)
8013                 isr = 0;
8014
8015         status = vmcs_read16(GUEST_INTR_STATUS);
8016         old = status >> 8;
8017         if (isr != old) {
8018                 status &= 0xff;
8019                 status |= isr << 8;
8020                 vmcs_write16(GUEST_INTR_STATUS, status);
8021         }
8022 }
8023
8024 static void vmx_set_rvi(int vector)
8025 {
8026         u16 status;
8027         u8 old;
8028
8029         if (vector == -1)
8030                 vector = 0;
8031
8032         status = vmcs_read16(GUEST_INTR_STATUS);
8033         old = (u8)status & 0xff;
8034         if ((u8)vector != old) {
8035                 status &= ~0xff;
8036                 status |= (u8)vector;
8037                 vmcs_write16(GUEST_INTR_STATUS, status);
8038         }
8039 }
8040
8041 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8042 {
8043         if (!is_guest_mode(vcpu)) {
8044                 vmx_set_rvi(max_irr);
8045                 return;
8046         }
8047
8048         if (max_irr == -1)
8049                 return;
8050
8051         /*
8052          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8053          * handles it.
8054          */
8055         if (nested_exit_on_intr(vcpu))
8056                 return;
8057
8058         /*
8059          * Else, fall back to pre-APICv interrupt injection since L2
8060          * is run without virtual interrupt delivery.
8061          */
8062         if (!kvm_event_needs_reinjection(vcpu) &&
8063             vmx_interrupt_allowed(vcpu)) {
8064                 kvm_queue_interrupt(vcpu, max_irr, false);
8065                 vmx_inject_irq(vcpu);
8066         }
8067 }
8068
8069 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8070 {
8071         if (!vmx_vm_has_apicv(vcpu->kvm))
8072                 return;
8073
8074         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8075         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8076         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8077         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8078 }
8079
8080 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8081 {
8082         u32 exit_intr_info;
8083
8084         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8085               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8086                 return;
8087
8088         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8089         exit_intr_info = vmx->exit_intr_info;
8090
8091         /* Handle machine checks before interrupts are enabled */
8092         if (is_machine_check(exit_intr_info))
8093                 kvm_machine_check();
8094
8095         /* We need to handle NMIs before interrupts are enabled */
8096         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8097             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8098                 kvm_before_handle_nmi(&vmx->vcpu);
8099                 asm("int $2");
8100                 kvm_after_handle_nmi(&vmx->vcpu);
8101         }
8102 }
8103
8104 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8105 {
8106         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8107
8108         /*
8109          * If external interrupt exists, IF bit is set in rflags/eflags on the
8110          * interrupt stack frame, and interrupt will be enabled on a return
8111          * from interrupt handler.
8112          */
8113         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8114                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8115                 unsigned int vector;
8116                 unsigned long entry;
8117                 gate_desc *desc;
8118                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8119 #ifdef CONFIG_X86_64
8120                 unsigned long tmp;
8121 #endif
8122
8123                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8124                 desc = (gate_desc *)vmx->host_idt_base + vector;
8125                 entry = gate_offset(*desc);
8126                 asm volatile(
8127 #ifdef CONFIG_X86_64
8128                         "mov %%" _ASM_SP ", %[sp]\n\t"
8129                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8130                         "push $%c[ss]\n\t"
8131                         "push %[sp]\n\t"
8132 #endif
8133                         "pushf\n\t"
8134                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8135                         __ASM_SIZE(push) " $%c[cs]\n\t"
8136                         "call *%[entry]\n\t"
8137                         :
8138 #ifdef CONFIG_X86_64
8139                         [sp]"=&r"(tmp)
8140 #endif
8141                         :
8142                         [entry]"r"(entry),
8143                         [ss]"i"(__KERNEL_DS),
8144                         [cs]"i"(__KERNEL_CS)
8145                         );
8146         } else
8147                 local_irq_enable();
8148 }
8149
8150 static bool vmx_mpx_supported(void)
8151 {
8152         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8153                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8154 }
8155
8156 static bool vmx_xsaves_supported(void)
8157 {
8158         return vmcs_config.cpu_based_2nd_exec_ctrl &
8159                 SECONDARY_EXEC_XSAVES;
8160 }
8161
8162 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8163 {
8164         u32 exit_intr_info;
8165         bool unblock_nmi;
8166         u8 vector;
8167         bool idtv_info_valid;
8168
8169         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8170
8171         if (cpu_has_virtual_nmis()) {
8172                 if (vmx->nmi_known_unmasked)
8173                         return;
8174                 /*
8175                  * Can't use vmx->exit_intr_info since we're not sure what
8176                  * the exit reason is.
8177                  */
8178                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8179                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8180                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8181                 /*
8182                  * SDM 3: 27.7.1.2 (September 2008)
8183                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8184                  * a guest IRET fault.
8185                  * SDM 3: 23.2.2 (September 2008)
8186                  * Bit 12 is undefined in any of the following cases:
8187                  *  If the VM exit sets the valid bit in the IDT-vectoring
8188                  *   information field.
8189                  *  If the VM exit is due to a double fault.
8190                  */
8191                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8192                     vector != DF_VECTOR && !idtv_info_valid)
8193                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8194                                       GUEST_INTR_STATE_NMI);
8195                 else
8196                         vmx->nmi_known_unmasked =
8197                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8198                                   & GUEST_INTR_STATE_NMI);
8199         } else if (unlikely(vmx->soft_vnmi_blocked))
8200                 vmx->vnmi_blocked_time +=
8201                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8202 }
8203
8204 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8205                                       u32 idt_vectoring_info,
8206                                       int instr_len_field,
8207                                       int error_code_field)
8208 {
8209         u8 vector;
8210         int type;
8211         bool idtv_info_valid;
8212
8213         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8214
8215         vcpu->arch.nmi_injected = false;
8216         kvm_clear_exception_queue(vcpu);
8217         kvm_clear_interrupt_queue(vcpu);
8218
8219         if (!idtv_info_valid)
8220                 return;
8221
8222         kvm_make_request(KVM_REQ_EVENT, vcpu);
8223
8224         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8225         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8226
8227         switch (type) {
8228         case INTR_TYPE_NMI_INTR:
8229                 vcpu->arch.nmi_injected = true;
8230                 /*
8231                  * SDM 3: 27.7.1.2 (September 2008)
8232                  * Clear bit "block by NMI" before VM entry if a NMI
8233                  * delivery faulted.
8234                  */
8235                 vmx_set_nmi_mask(vcpu, false);
8236                 break;
8237         case INTR_TYPE_SOFT_EXCEPTION:
8238                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8239                 /* fall through */
8240         case INTR_TYPE_HARD_EXCEPTION:
8241                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8242                         u32 err = vmcs_read32(error_code_field);
8243                         kvm_requeue_exception_e(vcpu, vector, err);
8244                 } else
8245                         kvm_requeue_exception(vcpu, vector);
8246                 break;
8247         case INTR_TYPE_SOFT_INTR:
8248                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8249                 /* fall through */
8250         case INTR_TYPE_EXT_INTR:
8251                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8252                 break;
8253         default:
8254                 break;
8255         }
8256 }
8257
8258 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8259 {
8260         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8261                                   VM_EXIT_INSTRUCTION_LEN,
8262                                   IDT_VECTORING_ERROR_CODE);
8263 }
8264
8265 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8266 {
8267         __vmx_complete_interrupts(vcpu,
8268                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8269                                   VM_ENTRY_INSTRUCTION_LEN,
8270                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8271
8272         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8273 }
8274
8275 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8276 {
8277         int i, nr_msrs;
8278         struct perf_guest_switch_msr *msrs;
8279
8280         msrs = perf_guest_get_msrs(&nr_msrs);
8281
8282         if (!msrs)
8283                 return;
8284
8285         for (i = 0; i < nr_msrs; i++)
8286                 if (msrs[i].host == msrs[i].guest)
8287                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8288                 else
8289                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8290                                         msrs[i].host);
8291 }
8292
8293 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8294 {
8295         struct vcpu_vmx *vmx = to_vmx(vcpu);
8296         unsigned long debugctlmsr, cr4;
8297
8298         /* Record the guest's net vcpu time for enforced NMI injections. */
8299         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8300                 vmx->entry_time = ktime_get();
8301
8302         /* Don't enter VMX if guest state is invalid, let the exit handler
8303            start emulation until we arrive back to a valid state */
8304         if (vmx->emulation_required)
8305                 return;
8306
8307         if (vmx->ple_window_dirty) {
8308                 vmx->ple_window_dirty = false;
8309                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8310         }
8311
8312         if (vmx->nested.sync_shadow_vmcs) {
8313                 copy_vmcs12_to_shadow(vmx);
8314                 vmx->nested.sync_shadow_vmcs = false;
8315         }
8316
8317         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8318                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8319         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8320                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8321
8322         cr4 = cr4_read_shadow();
8323         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8324                 vmcs_writel(HOST_CR4, cr4);
8325                 vmx->host_state.vmcs_host_cr4 = cr4;
8326         }
8327
8328         /* When single-stepping over STI and MOV SS, we must clear the
8329          * corresponding interruptibility bits in the guest state. Otherwise
8330          * vmentry fails as it then expects bit 14 (BS) in pending debug
8331          * exceptions being set, but that's not correct for the guest debugging
8332          * case. */
8333         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8334                 vmx_set_interrupt_shadow(vcpu, 0);
8335
8336         atomic_switch_perf_msrs(vmx);
8337         debugctlmsr = get_debugctlmsr();
8338
8339         vmx->__launched = vmx->loaded_vmcs->launched;
8340         asm(
8341                 /* Store host registers */
8342                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8343                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8344                 "push %%" _ASM_CX " \n\t"
8345                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8346                 "je 1f \n\t"
8347                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8348                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8349                 "1: \n\t"
8350                 /* Reload cr2 if changed */
8351                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8352                 "mov %%cr2, %%" _ASM_DX " \n\t"
8353                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8354                 "je 2f \n\t"
8355                 "mov %%" _ASM_AX", %%cr2 \n\t"
8356                 "2: \n\t"
8357                 /* Check if vmlaunch of vmresume is needed */
8358                 "cmpl $0, %c[launched](%0) \n\t"
8359                 /* Load guest registers.  Don't clobber flags. */
8360                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8361                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8362                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8363                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8364                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8365                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8366 #ifdef CONFIG_X86_64
8367                 "mov %c[r8](%0),  %%r8  \n\t"
8368                 "mov %c[r9](%0),  %%r9  \n\t"
8369                 "mov %c[r10](%0), %%r10 \n\t"
8370                 "mov %c[r11](%0), %%r11 \n\t"
8371                 "mov %c[r12](%0), %%r12 \n\t"
8372                 "mov %c[r13](%0), %%r13 \n\t"
8373                 "mov %c[r14](%0), %%r14 \n\t"
8374                 "mov %c[r15](%0), %%r15 \n\t"
8375 #endif
8376                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8377
8378                 /* Enter guest mode */
8379                 "jne 1f \n\t"
8380                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8381                 "jmp 2f \n\t"
8382                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8383                 "2: "
8384                 /* Save guest registers, load host registers, keep flags */
8385                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8386                 "pop %0 \n\t"
8387                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8388                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8389                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8390                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8391                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8392                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8393                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8394 #ifdef CONFIG_X86_64
8395                 "mov %%r8,  %c[r8](%0) \n\t"
8396                 "mov %%r9,  %c[r9](%0) \n\t"
8397                 "mov %%r10, %c[r10](%0) \n\t"
8398                 "mov %%r11, %c[r11](%0) \n\t"
8399                 "mov %%r12, %c[r12](%0) \n\t"
8400                 "mov %%r13, %c[r13](%0) \n\t"
8401                 "mov %%r14, %c[r14](%0) \n\t"
8402                 "mov %%r15, %c[r15](%0) \n\t"
8403 #endif
8404                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8405                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8406
8407                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8408                 "setbe %c[fail](%0) \n\t"
8409                 ".pushsection .rodata \n\t"
8410                 ".global vmx_return \n\t"
8411                 "vmx_return: " _ASM_PTR " 2b \n\t"
8412                 ".popsection"
8413               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8414                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8415                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8416                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8417                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8418                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8419                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8420                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8421                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8422                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8423                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8424 #ifdef CONFIG_X86_64
8425                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8426                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8427                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8428                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8429                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8430                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8431                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8432                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8433 #endif
8434                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8435                 [wordsize]"i"(sizeof(ulong))
8436               : "cc", "memory"
8437 #ifdef CONFIG_X86_64
8438                 , "rax", "rbx", "rdi", "rsi"
8439                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8440 #else
8441                 , "eax", "ebx", "edi", "esi"
8442 #endif
8443               );
8444
8445         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8446         if (debugctlmsr)
8447                 update_debugctlmsr(debugctlmsr);
8448
8449 #ifndef CONFIG_X86_64
8450         /*
8451          * The sysexit path does not restore ds/es, so we must set them to
8452          * a reasonable value ourselves.
8453          *
8454          * We can't defer this to vmx_load_host_state() since that function
8455          * may be executed in interrupt context, which saves and restore segments
8456          * around it, nullifying its effect.
8457          */
8458         loadsegment(ds, __USER_DS);
8459         loadsegment(es, __USER_DS);
8460 #endif
8461
8462         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8463                                   | (1 << VCPU_EXREG_RFLAGS)
8464                                   | (1 << VCPU_EXREG_PDPTR)
8465                                   | (1 << VCPU_EXREG_SEGMENTS)
8466                                   | (1 << VCPU_EXREG_CR3));
8467         vcpu->arch.regs_dirty = 0;
8468
8469         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8470
8471         vmx->loaded_vmcs->launched = 1;
8472
8473         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8474         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8475
8476         /*
8477          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8478          * we did not inject a still-pending event to L1 now because of
8479          * nested_run_pending, we need to re-enable this bit.
8480          */
8481         if (vmx->nested.nested_run_pending)
8482                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8483
8484         vmx->nested.nested_run_pending = 0;
8485
8486         vmx_complete_atomic_exit(vmx);
8487         vmx_recover_nmi_blocking(vmx);
8488         vmx_complete_interrupts(vmx);
8489 }
8490
8491 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8492 {
8493         struct vcpu_vmx *vmx = to_vmx(vcpu);
8494         int cpu;
8495
8496         if (vmx->loaded_vmcs == &vmx->vmcs01)
8497                 return;
8498
8499         cpu = get_cpu();
8500         vmx->loaded_vmcs = &vmx->vmcs01;
8501         vmx_vcpu_put(vcpu);
8502         vmx_vcpu_load(vcpu, cpu);
8503         vcpu->cpu = cpu;
8504         put_cpu();
8505 }
8506
8507 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8508 {
8509         struct vcpu_vmx *vmx = to_vmx(vcpu);
8510
8511         if (enable_pml)
8512                 vmx_disable_pml(vmx);
8513         free_vpid(vmx);
8514         leave_guest_mode(vcpu);
8515         vmx_load_vmcs01(vcpu);
8516         free_nested(vmx);
8517         free_loaded_vmcs(vmx->loaded_vmcs);
8518         kfree(vmx->guest_msrs);
8519         kvm_vcpu_uninit(vcpu);
8520         kmem_cache_free(kvm_vcpu_cache, vmx);
8521 }
8522
8523 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8524 {
8525         int err;
8526         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8527         int cpu;
8528
8529         if (!vmx)
8530                 return ERR_PTR(-ENOMEM);
8531
8532         allocate_vpid(vmx);
8533
8534         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8535         if (err)
8536                 goto free_vcpu;
8537
8538         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8539         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8540                      > PAGE_SIZE);
8541
8542         err = -ENOMEM;
8543         if (!vmx->guest_msrs) {
8544                 goto uninit_vcpu;
8545         }
8546
8547         vmx->loaded_vmcs = &vmx->vmcs01;
8548         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8549         if (!vmx->loaded_vmcs->vmcs)
8550                 goto free_msrs;
8551         if (!vmm_exclusive)
8552                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8553         loaded_vmcs_init(vmx->loaded_vmcs);
8554         if (!vmm_exclusive)
8555                 kvm_cpu_vmxoff();
8556
8557         cpu = get_cpu();
8558         vmx_vcpu_load(&vmx->vcpu, cpu);
8559         vmx->vcpu.cpu = cpu;
8560         err = vmx_vcpu_setup(vmx);
8561         vmx_vcpu_put(&vmx->vcpu);
8562         put_cpu();
8563         if (err)
8564                 goto free_vmcs;
8565         if (vm_need_virtualize_apic_accesses(kvm)) {
8566                 err = alloc_apic_access_page(kvm);
8567                 if (err)
8568                         goto free_vmcs;
8569         }
8570
8571         if (enable_ept) {
8572                 if (!kvm->arch.ept_identity_map_addr)
8573                         kvm->arch.ept_identity_map_addr =
8574                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8575                 err = init_rmode_identity_map(kvm);
8576                 if (err)
8577                         goto free_vmcs;
8578         }
8579
8580         if (nested)
8581                 nested_vmx_setup_ctls_msrs(vmx);
8582
8583         vmx->nested.posted_intr_nv = -1;
8584         vmx->nested.current_vmptr = -1ull;
8585         vmx->nested.current_vmcs12 = NULL;
8586
8587         /*
8588          * If PML is turned on, failure on enabling PML just results in failure
8589          * of creating the vcpu, therefore we can simplify PML logic (by
8590          * avoiding dealing with cases, such as enabling PML partially on vcpus
8591          * for the guest, etc.
8592          */
8593         if (enable_pml) {
8594                 err = vmx_enable_pml(vmx);
8595                 if (err)
8596                         goto free_vmcs;
8597         }
8598
8599         return &vmx->vcpu;
8600
8601 free_vmcs:
8602         free_loaded_vmcs(vmx->loaded_vmcs);
8603 free_msrs:
8604         kfree(vmx->guest_msrs);
8605 uninit_vcpu:
8606         kvm_vcpu_uninit(&vmx->vcpu);
8607 free_vcpu:
8608         free_vpid(vmx);
8609         kmem_cache_free(kvm_vcpu_cache, vmx);
8610         return ERR_PTR(err);
8611 }
8612
8613 static void __init vmx_check_processor_compat(void *rtn)
8614 {
8615         struct vmcs_config vmcs_conf;
8616
8617         *(int *)rtn = 0;
8618         if (setup_vmcs_config(&vmcs_conf) < 0)
8619                 *(int *)rtn = -EIO;
8620         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8621                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8622                                 smp_processor_id());
8623                 *(int *)rtn = -EIO;
8624         }
8625 }
8626
8627 static int get_ept_level(void)
8628 {
8629         return VMX_EPT_DEFAULT_GAW + 1;
8630 }
8631
8632 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8633 {
8634         u64 ret;
8635
8636         /* For VT-d and EPT combination
8637          * 1. MMIO: always map as UC
8638          * 2. EPT with VT-d:
8639          *   a. VT-d without snooping control feature: can't guarantee the
8640          *      result, try to trust guest.
8641          *   b. VT-d with snooping control feature: snooping control feature of
8642          *      VT-d engine can guarantee the cache correctness. Just set it
8643          *      to WB to keep consistent with host. So the same as item 3.
8644          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8645          *    consistent with host MTRR
8646          */
8647         if (is_mmio)
8648                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8649         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8650                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8651                       VMX_EPT_MT_EPTE_SHIFT;
8652         else
8653                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8654                         | VMX_EPT_IPAT_BIT;
8655
8656         return ret;
8657 }
8658
8659 static int vmx_get_lpage_level(void)
8660 {
8661         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8662                 return PT_DIRECTORY_LEVEL;
8663         else
8664                 /* For shadow and EPT supported 1GB page */
8665                 return PT_PDPE_LEVEL;
8666 }
8667
8668 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8669 {
8670         struct kvm_cpuid_entry2 *best;
8671         struct vcpu_vmx *vmx = to_vmx(vcpu);
8672         u32 exec_control;
8673
8674         vmx->rdtscp_enabled = false;
8675         if (vmx_rdtscp_supported()) {
8676                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8677                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8678                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8679                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8680                                 vmx->rdtscp_enabled = true;
8681                         else {
8682                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8683                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8684                                                 exec_control);
8685                         }
8686                 }
8687                 if (nested && !vmx->rdtscp_enabled)
8688                         vmx->nested.nested_vmx_secondary_ctls_high &=
8689                                 ~SECONDARY_EXEC_RDTSCP;
8690         }
8691
8692         /* Exposing INVPCID only when PCID is exposed */
8693         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8694         if (vmx_invpcid_supported() &&
8695             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8696             guest_cpuid_has_pcid(vcpu)) {
8697                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8698                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8699                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8700                              exec_control);
8701         } else {
8702                 if (cpu_has_secondary_exec_ctrls()) {
8703                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8704                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8705                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8706                                      exec_control);
8707                 }
8708                 if (best)
8709                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8710         }
8711 }
8712
8713 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8714 {
8715         if (func == 1 && nested)
8716                 entry->ecx |= bit(X86_FEATURE_VMX);
8717 }
8718
8719 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8720                 struct x86_exception *fault)
8721 {
8722         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8723         u32 exit_reason;
8724
8725         if (fault->error_code & PFERR_RSVD_MASK)
8726                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8727         else
8728                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8729         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8730         vmcs12->guest_physical_address = fault->address;
8731 }
8732
8733 /* Callbacks for nested_ept_init_mmu_context: */
8734
8735 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8736 {
8737         /* return the page table to be shadowed - in our case, EPT12 */
8738         return get_vmcs12(vcpu)->ept_pointer;
8739 }
8740
8741 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8742 {
8743         WARN_ON(mmu_is_nested(vcpu));
8744         kvm_init_shadow_ept_mmu(vcpu,
8745                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8746                         VMX_EPT_EXECUTE_ONLY_BIT);
8747         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8748         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8749         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8750
8751         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8752 }
8753
8754 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8755 {
8756         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8757 }
8758
8759 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8760                                             u16 error_code)
8761 {
8762         bool inequality, bit;
8763
8764         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8765         inequality =
8766                 (error_code & vmcs12->page_fault_error_code_mask) !=
8767                  vmcs12->page_fault_error_code_match;
8768         return inequality ^ bit;
8769 }
8770
8771 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8772                 struct x86_exception *fault)
8773 {
8774         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8775
8776         WARN_ON(!is_guest_mode(vcpu));
8777
8778         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8779                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8780                                   vmcs_read32(VM_EXIT_INTR_INFO),
8781                                   vmcs_readl(EXIT_QUALIFICATION));
8782         else
8783                 kvm_inject_page_fault(vcpu, fault);
8784 }
8785
8786 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8787                                         struct vmcs12 *vmcs12)
8788 {
8789         struct vcpu_vmx *vmx = to_vmx(vcpu);
8790         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8791
8792         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8793                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8794                     vmcs12->apic_access_addr >> maxphyaddr)
8795                         return false;
8796
8797                 /*
8798                  * Translate L1 physical address to host physical
8799                  * address for vmcs02. Keep the page pinned, so this
8800                  * physical address remains valid. We keep a reference
8801                  * to it so we can release it later.
8802                  */
8803                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8804                         nested_release_page(vmx->nested.apic_access_page);
8805                 vmx->nested.apic_access_page =
8806                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8807         }
8808
8809         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8810                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8811                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
8812                         return false;
8813
8814                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8815                         nested_release_page(vmx->nested.virtual_apic_page);
8816                 vmx->nested.virtual_apic_page =
8817                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8818
8819                 /*
8820                  * Failing the vm entry is _not_ what the processor does
8821                  * but it's basically the only possibility we have.
8822                  * We could still enter the guest if CR8 load exits are
8823                  * enabled, CR8 store exits are enabled, and virtualize APIC
8824                  * access is disabled; in this case the processor would never
8825                  * use the TPR shadow and we could simply clear the bit from
8826                  * the execution control.  But such a configuration is useless,
8827                  * so let's keep the code simple.
8828                  */
8829                 if (!vmx->nested.virtual_apic_page)
8830                         return false;
8831         }
8832
8833         if (nested_cpu_has_posted_intr(vmcs12)) {
8834                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8835                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
8836                         return false;
8837
8838                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8839                         kunmap(vmx->nested.pi_desc_page);
8840                         nested_release_page(vmx->nested.pi_desc_page);
8841                 }
8842                 vmx->nested.pi_desc_page =
8843                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8844                 if (!vmx->nested.pi_desc_page)
8845                         return false;
8846
8847                 vmx->nested.pi_desc =
8848                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8849                 if (!vmx->nested.pi_desc) {
8850                         nested_release_page_clean(vmx->nested.pi_desc_page);
8851                         return false;
8852                 }
8853                 vmx->nested.pi_desc =
8854                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
8855                         (unsigned long)(vmcs12->posted_intr_desc_addr &
8856                         (PAGE_SIZE - 1)));
8857         }
8858
8859         return true;
8860 }
8861
8862 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8863 {
8864         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8865         struct vcpu_vmx *vmx = to_vmx(vcpu);
8866
8867         if (vcpu->arch.virtual_tsc_khz == 0)
8868                 return;
8869
8870         /* Make sure short timeouts reliably trigger an immediate vmexit.
8871          * hrtimer_start does not guarantee this. */
8872         if (preemption_timeout <= 1) {
8873                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8874                 return;
8875         }
8876
8877         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8878         preemption_timeout *= 1000000;
8879         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8880         hrtimer_start(&vmx->nested.preemption_timer,
8881                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8882 }
8883
8884 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8885                                                 struct vmcs12 *vmcs12)
8886 {
8887         int maxphyaddr;
8888         u64 addr;
8889
8890         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8891                 return 0;
8892
8893         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8894                 WARN_ON(1);
8895                 return -EINVAL;
8896         }
8897         maxphyaddr = cpuid_maxphyaddr(vcpu);
8898
8899         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8900            ((addr + PAGE_SIZE) >> maxphyaddr))
8901                 return -EINVAL;
8902
8903         return 0;
8904 }
8905
8906 /*
8907  * Merge L0's and L1's MSR bitmap, return false to indicate that
8908  * we do not use the hardware.
8909  */
8910 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8911                                                struct vmcs12 *vmcs12)
8912 {
8913         int msr;
8914         struct page *page;
8915         unsigned long *msr_bitmap;
8916
8917         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8918                 return false;
8919
8920         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8921         if (!page) {
8922                 WARN_ON(1);
8923                 return false;
8924         }
8925         msr_bitmap = (unsigned long *)kmap(page);
8926         if (!msr_bitmap) {
8927                 nested_release_page_clean(page);
8928                 WARN_ON(1);
8929                 return false;
8930         }
8931
8932         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8933                 if (nested_cpu_has_apic_reg_virt(vmcs12))
8934                         for (msr = 0x800; msr <= 0x8ff; msr++)
8935                                 nested_vmx_disable_intercept_for_msr(
8936                                         msr_bitmap,
8937                                         vmx_msr_bitmap_nested,
8938                                         msr, MSR_TYPE_R);
8939                 /* TPR is allowed */
8940                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8941                                 vmx_msr_bitmap_nested,
8942                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8943                                 MSR_TYPE_R | MSR_TYPE_W);
8944                 if (nested_cpu_has_vid(vmcs12)) {
8945                         /* EOI and self-IPI are allowed */
8946                         nested_vmx_disable_intercept_for_msr(
8947                                 msr_bitmap,
8948                                 vmx_msr_bitmap_nested,
8949                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8950                                 MSR_TYPE_W);
8951                         nested_vmx_disable_intercept_for_msr(
8952                                 msr_bitmap,
8953                                 vmx_msr_bitmap_nested,
8954                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8955                                 MSR_TYPE_W);
8956                 }
8957         } else {
8958                 /*
8959                  * Enable reading intercept of all the x2apic
8960                  * MSRs. We should not rely on vmcs12 to do any
8961                  * optimizations here, it may have been modified
8962                  * by L1.
8963                  */
8964                 for (msr = 0x800; msr <= 0x8ff; msr++)
8965                         __vmx_enable_intercept_for_msr(
8966                                 vmx_msr_bitmap_nested,
8967                                 msr,
8968                                 MSR_TYPE_R);
8969
8970                 __vmx_enable_intercept_for_msr(
8971                                 vmx_msr_bitmap_nested,
8972                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8973                                 MSR_TYPE_W);
8974                 __vmx_enable_intercept_for_msr(
8975                                 vmx_msr_bitmap_nested,
8976                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8977                                 MSR_TYPE_W);
8978                 __vmx_enable_intercept_for_msr(
8979                                 vmx_msr_bitmap_nested,
8980                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8981                                 MSR_TYPE_W);
8982         }
8983         kunmap(page);
8984         nested_release_page_clean(page);
8985
8986         return true;
8987 }
8988
8989 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8990                                            struct vmcs12 *vmcs12)
8991 {
8992         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8993             !nested_cpu_has_apic_reg_virt(vmcs12) &&
8994             !nested_cpu_has_vid(vmcs12) &&
8995             !nested_cpu_has_posted_intr(vmcs12))
8996                 return 0;
8997
8998         /*
8999          * If virtualize x2apic mode is enabled,
9000          * virtualize apic access must be disabled.
9001          */
9002         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9003             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9004                 return -EINVAL;
9005
9006         /*
9007          * If virtual interrupt delivery is enabled,
9008          * we must exit on external interrupts.
9009          */
9010         if (nested_cpu_has_vid(vmcs12) &&
9011            !nested_exit_on_intr(vcpu))
9012                 return -EINVAL;
9013
9014         /*
9015          * bits 15:8 should be zero in posted_intr_nv,
9016          * the descriptor address has been already checked
9017          * in nested_get_vmcs12_pages.
9018          */
9019         if (nested_cpu_has_posted_intr(vmcs12) &&
9020            (!nested_cpu_has_vid(vmcs12) ||
9021             !nested_exit_intr_ack_set(vcpu) ||
9022             vmcs12->posted_intr_nv & 0xff00))
9023                 return -EINVAL;
9024
9025         /* tpr shadow is needed by all apicv features. */
9026         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9027                 return -EINVAL;
9028
9029         return 0;
9030 }
9031
9032 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9033                                        unsigned long count_field,
9034                                        unsigned long addr_field)
9035 {
9036         int maxphyaddr;
9037         u64 count, addr;
9038
9039         if (vmcs12_read_any(vcpu, count_field, &count) ||
9040             vmcs12_read_any(vcpu, addr_field, &addr)) {
9041                 WARN_ON(1);
9042                 return -EINVAL;
9043         }
9044         if (count == 0)
9045                 return 0;
9046         maxphyaddr = cpuid_maxphyaddr(vcpu);
9047         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9048             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9049                 pr_warn_ratelimited(
9050                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9051                         addr_field, maxphyaddr, count, addr);
9052                 return -EINVAL;
9053         }
9054         return 0;
9055 }
9056
9057 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9058                                                 struct vmcs12 *vmcs12)
9059 {
9060         if (vmcs12->vm_exit_msr_load_count == 0 &&
9061             vmcs12->vm_exit_msr_store_count == 0 &&
9062             vmcs12->vm_entry_msr_load_count == 0)
9063                 return 0; /* Fast path */
9064         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9065                                         VM_EXIT_MSR_LOAD_ADDR) ||
9066             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9067                                         VM_EXIT_MSR_STORE_ADDR) ||
9068             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9069                                         VM_ENTRY_MSR_LOAD_ADDR))
9070                 return -EINVAL;
9071         return 0;
9072 }
9073
9074 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9075                                        struct vmx_msr_entry *e)
9076 {
9077         /* x2APIC MSR accesses are not allowed */
9078         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9079                 return -EINVAL;
9080         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9081             e->index == MSR_IA32_UCODE_REV)
9082                 return -EINVAL;
9083         if (e->reserved != 0)
9084                 return -EINVAL;
9085         return 0;
9086 }
9087
9088 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9089                                      struct vmx_msr_entry *e)
9090 {
9091         if (e->index == MSR_FS_BASE ||
9092             e->index == MSR_GS_BASE ||
9093             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9094             nested_vmx_msr_check_common(vcpu, e))
9095                 return -EINVAL;
9096         return 0;
9097 }
9098
9099 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9100                                       struct vmx_msr_entry *e)
9101 {
9102         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9103             nested_vmx_msr_check_common(vcpu, e))
9104                 return -EINVAL;
9105         return 0;
9106 }
9107
9108 /*
9109  * Load guest's/host's msr at nested entry/exit.
9110  * return 0 for success, entry index for failure.
9111  */
9112 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9113 {
9114         u32 i;
9115         struct vmx_msr_entry e;
9116         struct msr_data msr;
9117
9118         msr.host_initiated = false;
9119         for (i = 0; i < count; i++) {
9120                 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
9121                                    &e, sizeof(e))) {
9122                         pr_warn_ratelimited(
9123                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9124                                 __func__, i, gpa + i * sizeof(e));
9125                         goto fail;
9126                 }
9127                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9128                         pr_warn_ratelimited(
9129                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9130                                 __func__, i, e.index, e.reserved);
9131                         goto fail;
9132                 }
9133                 msr.index = e.index;
9134                 msr.data = e.value;
9135                 if (kvm_set_msr(vcpu, &msr)) {
9136                         pr_warn_ratelimited(
9137                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9138                                 __func__, i, e.index, e.value);
9139                         goto fail;
9140                 }
9141         }
9142         return 0;
9143 fail:
9144         return i + 1;
9145 }
9146
9147 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9148 {
9149         u32 i;
9150         struct vmx_msr_entry e;
9151
9152         for (i = 0; i < count; i++) {
9153                 if (kvm_read_guest(vcpu->kvm,
9154                                    gpa + i * sizeof(e),
9155                                    &e, 2 * sizeof(u32))) {
9156                         pr_warn_ratelimited(
9157                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9158                                 __func__, i, gpa + i * sizeof(e));
9159                         return -EINVAL;
9160                 }
9161                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9162                         pr_warn_ratelimited(
9163                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9164                                 __func__, i, e.index, e.reserved);
9165                         return -EINVAL;
9166                 }
9167                 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9168                         pr_warn_ratelimited(
9169                                 "%s cannot read MSR (%u, 0x%x)\n",
9170                                 __func__, i, e.index);
9171                         return -EINVAL;
9172                 }
9173                 if (kvm_write_guest(vcpu->kvm,
9174                                     gpa + i * sizeof(e) +
9175                                         offsetof(struct vmx_msr_entry, value),
9176                                     &e.value, sizeof(e.value))) {
9177                         pr_warn_ratelimited(
9178                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9179                                 __func__, i, e.index, e.value);
9180                         return -EINVAL;
9181                 }
9182         }
9183         return 0;
9184 }
9185
9186 /*
9187  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9188  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9189  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9190  * guest in a way that will both be appropriate to L1's requests, and our
9191  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9192  * function also has additional necessary side-effects, like setting various
9193  * vcpu->arch fields.
9194  */
9195 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9196 {
9197         struct vcpu_vmx *vmx = to_vmx(vcpu);
9198         u32 exec_control;
9199
9200         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9201         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9202         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9203         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9204         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9205         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9206         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9207         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9208         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9209         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9210         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9211         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9212         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9213         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9214         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9215         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9216         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9217         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9218         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9219         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9220         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9221         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9222         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9223         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9224         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9225         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9226         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9227         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9228         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9229         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9230         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9231         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9232         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9233         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9234         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9235         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9236
9237         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9238                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9239                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9240         } else {
9241                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9242                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9243         }
9244         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9245                 vmcs12->vm_entry_intr_info_field);
9246         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9247                 vmcs12->vm_entry_exception_error_code);
9248         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9249                 vmcs12->vm_entry_instruction_len);
9250         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9251                 vmcs12->guest_interruptibility_info);
9252         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9253         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9254         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9255                 vmcs12->guest_pending_dbg_exceptions);
9256         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9257         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9258
9259         if (nested_cpu_has_xsaves(vmcs12))
9260                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9261         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9262
9263         exec_control = vmcs12->pin_based_vm_exec_control;
9264         exec_control |= vmcs_config.pin_based_exec_ctrl;
9265         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9266
9267         if (nested_cpu_has_posted_intr(vmcs12)) {
9268                 /*
9269                  * Note that we use L0's vector here and in
9270                  * vmx_deliver_nested_posted_interrupt.
9271                  */
9272                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9273                 vmx->nested.pi_pending = false;
9274                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9275                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9276                         page_to_phys(vmx->nested.pi_desc_page) +
9277                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9278                         (PAGE_SIZE - 1)));
9279         } else
9280                 exec_control &= ~PIN_BASED_POSTED_INTR;
9281
9282         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9283
9284         vmx->nested.preemption_timer_expired = false;
9285         if (nested_cpu_has_preemption_timer(vmcs12))
9286                 vmx_start_preemption_timer(vcpu);
9287
9288         /*
9289          * Whether page-faults are trapped is determined by a combination of
9290          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9291          * If enable_ept, L0 doesn't care about page faults and we should
9292          * set all of these to L1's desires. However, if !enable_ept, L0 does
9293          * care about (at least some) page faults, and because it is not easy
9294          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9295          * to exit on each and every L2 page fault. This is done by setting
9296          * MASK=MATCH=0 and (see below) EB.PF=1.
9297          * Note that below we don't need special code to set EB.PF beyond the
9298          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9299          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9300          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9301          *
9302          * A problem with this approach (when !enable_ept) is that L1 may be
9303          * injected with more page faults than it asked for. This could have
9304          * caused problems, but in practice existing hypervisors don't care.
9305          * To fix this, we will need to emulate the PFEC checking (on the L1
9306          * page tables), using walk_addr(), when injecting PFs to L1.
9307          */
9308         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9309                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9310         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9311                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9312
9313         if (cpu_has_secondary_exec_ctrls()) {
9314                 exec_control = vmx_secondary_exec_control(vmx);
9315                 if (!vmx->rdtscp_enabled)
9316                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
9317                 /* Take the following fields only from vmcs12 */
9318                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9319                                   SECONDARY_EXEC_RDTSCP |
9320                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9321                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9322                 if (nested_cpu_has(vmcs12,
9323                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9324                         exec_control |= vmcs12->secondary_vm_exec_control;
9325
9326                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9327                         /*
9328                          * If translation failed, no matter: This feature asks
9329                          * to exit when accessing the given address, and if it
9330                          * can never be accessed, this feature won't do
9331                          * anything anyway.
9332                          */
9333                         if (!vmx->nested.apic_access_page)
9334                                 exec_control &=
9335                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9336                         else
9337                                 vmcs_write64(APIC_ACCESS_ADDR,
9338                                   page_to_phys(vmx->nested.apic_access_page));
9339                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9340                             (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9341                         exec_control |=
9342                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9343                         kvm_vcpu_reload_apic_access_page(vcpu);
9344                 }
9345
9346                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9347                         vmcs_write64(EOI_EXIT_BITMAP0,
9348                                 vmcs12->eoi_exit_bitmap0);
9349                         vmcs_write64(EOI_EXIT_BITMAP1,
9350                                 vmcs12->eoi_exit_bitmap1);
9351                         vmcs_write64(EOI_EXIT_BITMAP2,
9352                                 vmcs12->eoi_exit_bitmap2);
9353                         vmcs_write64(EOI_EXIT_BITMAP3,
9354                                 vmcs12->eoi_exit_bitmap3);
9355                         vmcs_write16(GUEST_INTR_STATUS,
9356                                 vmcs12->guest_intr_status);
9357                 }
9358
9359                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9360         }
9361
9362
9363         /*
9364          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9365          * Some constant fields are set here by vmx_set_constant_host_state().
9366          * Other fields are different per CPU, and will be set later when
9367          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9368          */
9369         vmx_set_constant_host_state(vmx);
9370
9371         /*
9372          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9373          * entry, but only if the current (host) sp changed from the value
9374          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9375          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9376          * here we just force the write to happen on entry.
9377          */
9378         vmx->host_rsp = 0;
9379
9380         exec_control = vmx_exec_control(vmx); /* L0's desires */
9381         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9382         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9383         exec_control &= ~CPU_BASED_TPR_SHADOW;
9384         exec_control |= vmcs12->cpu_based_vm_exec_control;
9385
9386         if (exec_control & CPU_BASED_TPR_SHADOW) {
9387                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9388                                 page_to_phys(vmx->nested.virtual_apic_page));
9389                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9390         }
9391
9392         if (cpu_has_vmx_msr_bitmap() &&
9393             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9394                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9395                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9396         } else
9397                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9398
9399         /*
9400          * Merging of IO bitmap not currently supported.
9401          * Rather, exit every time.
9402          */
9403         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9404         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9405
9406         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9407
9408         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9409          * bitwise-or of what L1 wants to trap for L2, and what we want to
9410          * trap. Note that CR0.TS also needs updating - we do this later.
9411          */
9412         update_exception_bitmap(vcpu);
9413         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9414         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9415
9416         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9417          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9418          * bits are further modified by vmx_set_efer() below.
9419          */
9420         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9421
9422         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9423          * emulated by vmx_set_efer(), below.
9424          */
9425         vm_entry_controls_init(vmx,
9426                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9427                         ~VM_ENTRY_IA32E_MODE) |
9428                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9429
9430         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9431                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9432                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9433         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9434                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9435
9436
9437         set_cr4_guest_host_mask(vmx);
9438
9439         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9440                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9441
9442         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9443                 vmcs_write64(TSC_OFFSET,
9444                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9445         else
9446                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9447
9448         if (enable_vpid) {
9449                 /*
9450                  * Trivially support vpid by letting L2s share their parent
9451                  * L1's vpid. TODO: move to a more elaborate solution, giving
9452                  * each L2 its own vpid and exposing the vpid feature to L1.
9453                  */
9454                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9455                 vmx_flush_tlb(vcpu);
9456         }
9457
9458         if (nested_cpu_has_ept(vmcs12)) {
9459                 kvm_mmu_unload(vcpu);
9460                 nested_ept_init_mmu_context(vcpu);
9461         }
9462
9463         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9464                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9465         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9466                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9467         else
9468                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9469         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9470         vmx_set_efer(vcpu, vcpu->arch.efer);
9471
9472         /*
9473          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9474          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9475          * The CR0_READ_SHADOW is what L2 should have expected to read given
9476          * the specifications by L1; It's not enough to take
9477          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9478          * have more bits than L1 expected.
9479          */
9480         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9481         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9482
9483         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9484         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9485
9486         /* shadow page tables on either EPT or shadow page tables */
9487         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9488         kvm_mmu_reset_context(vcpu);
9489
9490         if (!enable_ept)
9491                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9492
9493         /*
9494          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9495          */
9496         if (enable_ept) {
9497                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9498                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9499                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9500                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9501         }
9502
9503         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9504         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9505 }
9506
9507 /*
9508  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9509  * for running an L2 nested guest.
9510  */
9511 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9512 {
9513         struct vmcs12 *vmcs12;
9514         struct vcpu_vmx *vmx = to_vmx(vcpu);
9515         int cpu;
9516         struct loaded_vmcs *vmcs02;
9517         bool ia32e;
9518         u32 msr_entry_idx;
9519
9520         if (!nested_vmx_check_permission(vcpu) ||
9521             !nested_vmx_check_vmcs12(vcpu))
9522                 return 1;
9523
9524         skip_emulated_instruction(vcpu);
9525         vmcs12 = get_vmcs12(vcpu);
9526
9527         if (enable_shadow_vmcs)
9528                 copy_shadow_to_vmcs12(vmx);
9529
9530         /*
9531          * The nested entry process starts with enforcing various prerequisites
9532          * on vmcs12 as required by the Intel SDM, and act appropriately when
9533          * they fail: As the SDM explains, some conditions should cause the
9534          * instruction to fail, while others will cause the instruction to seem
9535          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9536          * To speed up the normal (success) code path, we should avoid checking
9537          * for misconfigurations which will anyway be caught by the processor
9538          * when using the merged vmcs02.
9539          */
9540         if (vmcs12->launch_state == launch) {
9541                 nested_vmx_failValid(vcpu,
9542                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9543                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9544                 return 1;
9545         }
9546
9547         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9548             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9549                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9550                 return 1;
9551         }
9552
9553         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9554                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9555                 return 1;
9556         }
9557
9558         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9559                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9560                 return 1;
9561         }
9562
9563         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9564                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9565                 return 1;
9566         }
9567
9568         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9569                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9570                 return 1;
9571         }
9572
9573         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9574                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9575                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9576             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9577                                 vmx->nested.nested_vmx_secondary_ctls_low,
9578                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9579             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9580                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9581                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9582             !vmx_control_verify(vmcs12->vm_exit_controls,
9583                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9584                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9585             !vmx_control_verify(vmcs12->vm_entry_controls,
9586                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9587                                 vmx->nested.nested_vmx_entry_ctls_high))
9588         {
9589                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9590                 return 1;
9591         }
9592
9593         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9594             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9595                 nested_vmx_failValid(vcpu,
9596                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9597                 return 1;
9598         }
9599
9600         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9601             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9602                 nested_vmx_entry_failure(vcpu, vmcs12,
9603                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9604                 return 1;
9605         }
9606         if (vmcs12->vmcs_link_pointer != -1ull) {
9607                 nested_vmx_entry_failure(vcpu, vmcs12,
9608                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9609                 return 1;
9610         }
9611
9612         /*
9613          * If the load IA32_EFER VM-entry control is 1, the following checks
9614          * are performed on the field for the IA32_EFER MSR:
9615          * - Bits reserved in the IA32_EFER MSR must be 0.
9616          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9617          *   the IA-32e mode guest VM-exit control. It must also be identical
9618          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9619          *   CR0.PG) is 1.
9620          */
9621         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9622                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9623                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9624                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9625                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9626                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9627                         nested_vmx_entry_failure(vcpu, vmcs12,
9628                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9629                         return 1;
9630                 }
9631         }
9632
9633         /*
9634          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9635          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9636          * the values of the LMA and LME bits in the field must each be that of
9637          * the host address-space size VM-exit control.
9638          */
9639         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9640                 ia32e = (vmcs12->vm_exit_controls &
9641                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9642                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9643                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9644                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9645                         nested_vmx_entry_failure(vcpu, vmcs12,
9646                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9647                         return 1;
9648                 }
9649         }
9650
9651         /*
9652          * We're finally done with prerequisite checking, and can start with
9653          * the nested entry.
9654          */
9655
9656         vmcs02 = nested_get_current_vmcs02(vmx);
9657         if (!vmcs02)
9658                 return -ENOMEM;
9659
9660         enter_guest_mode(vcpu);
9661
9662         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9663
9664         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9665                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9666
9667         cpu = get_cpu();
9668         vmx->loaded_vmcs = vmcs02;
9669         vmx_vcpu_put(vcpu);
9670         vmx_vcpu_load(vcpu, cpu);
9671         vcpu->cpu = cpu;
9672         put_cpu();
9673
9674         vmx_segment_cache_clear(vmx);
9675
9676         prepare_vmcs02(vcpu, vmcs12);
9677
9678         msr_entry_idx = nested_vmx_load_msr(vcpu,
9679                                             vmcs12->vm_entry_msr_load_addr,
9680                                             vmcs12->vm_entry_msr_load_count);
9681         if (msr_entry_idx) {
9682                 leave_guest_mode(vcpu);
9683                 vmx_load_vmcs01(vcpu);
9684                 nested_vmx_entry_failure(vcpu, vmcs12,
9685                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9686                 return 1;
9687         }
9688
9689         vmcs12->launch_state = 1;
9690
9691         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9692                 return kvm_vcpu_halt(vcpu);
9693
9694         vmx->nested.nested_run_pending = 1;
9695
9696         /*
9697          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9698          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9699          * returned as far as L1 is concerned. It will only return (and set
9700          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9701          */
9702         return 1;
9703 }
9704
9705 /*
9706  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9707  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9708  * This function returns the new value we should put in vmcs12.guest_cr0.
9709  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9710  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9711  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9712  *     didn't trap the bit, because if L1 did, so would L0).
9713  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9714  *     been modified by L2, and L1 knows it. So just leave the old value of
9715  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9716  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9717  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9718  *     changed these bits, and therefore they need to be updated, but L0
9719  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9720  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9721  */
9722 static inline unsigned long
9723 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9724 {
9725         return
9726         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9727         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9728         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9729                         vcpu->arch.cr0_guest_owned_bits));
9730 }
9731
9732 static inline unsigned long
9733 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9734 {
9735         return
9736         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9737         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9738         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9739                         vcpu->arch.cr4_guest_owned_bits));
9740 }
9741
9742 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9743                                        struct vmcs12 *vmcs12)
9744 {
9745         u32 idt_vectoring;
9746         unsigned int nr;
9747
9748         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9749                 nr = vcpu->arch.exception.nr;
9750                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9751
9752                 if (kvm_exception_is_soft(nr)) {
9753                         vmcs12->vm_exit_instruction_len =
9754                                 vcpu->arch.event_exit_inst_len;
9755                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9756                 } else
9757                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9758
9759                 if (vcpu->arch.exception.has_error_code) {
9760                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9761                         vmcs12->idt_vectoring_error_code =
9762                                 vcpu->arch.exception.error_code;
9763                 }
9764
9765                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9766         } else if (vcpu->arch.nmi_injected) {
9767                 vmcs12->idt_vectoring_info_field =
9768                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9769         } else if (vcpu->arch.interrupt.pending) {
9770                 nr = vcpu->arch.interrupt.nr;
9771                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9772
9773                 if (vcpu->arch.interrupt.soft) {
9774                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
9775                         vmcs12->vm_entry_instruction_len =
9776                                 vcpu->arch.event_exit_inst_len;
9777                 } else
9778                         idt_vectoring |= INTR_TYPE_EXT_INTR;
9779
9780                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9781         }
9782 }
9783
9784 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9785 {
9786         struct vcpu_vmx *vmx = to_vmx(vcpu);
9787
9788         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9789             vmx->nested.preemption_timer_expired) {
9790                 if (vmx->nested.nested_run_pending)
9791                         return -EBUSY;
9792                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9793                 return 0;
9794         }
9795
9796         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9797                 if (vmx->nested.nested_run_pending ||
9798                     vcpu->arch.interrupt.pending)
9799                         return -EBUSY;
9800                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9801                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
9802                                   INTR_INFO_VALID_MASK, 0);
9803                 /*
9804                  * The NMI-triggered VM exit counts as injection:
9805                  * clear this one and block further NMIs.
9806                  */
9807                 vcpu->arch.nmi_pending = 0;
9808                 vmx_set_nmi_mask(vcpu, true);
9809                 return 0;
9810         }
9811
9812         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9813             nested_exit_on_intr(vcpu)) {
9814                 if (vmx->nested.nested_run_pending)
9815                         return -EBUSY;
9816                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9817                 return 0;
9818         }
9819
9820         return vmx_complete_nested_posted_interrupt(vcpu);
9821 }
9822
9823 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9824 {
9825         ktime_t remaining =
9826                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9827         u64 value;
9828
9829         if (ktime_to_ns(remaining) <= 0)
9830                 return 0;
9831
9832         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9833         do_div(value, 1000000);
9834         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9835 }
9836
9837 /*
9838  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9839  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9840  * and this function updates it to reflect the changes to the guest state while
9841  * L2 was running (and perhaps made some exits which were handled directly by L0
9842  * without going back to L1), and to reflect the exit reason.
9843  * Note that we do not have to copy here all VMCS fields, just those that
9844  * could have changed by the L2 guest or the exit - i.e., the guest-state and
9845  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9846  * which already writes to vmcs12 directly.
9847  */
9848 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9849                            u32 exit_reason, u32 exit_intr_info,
9850                            unsigned long exit_qualification)
9851 {
9852         /* update guest state fields: */
9853         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9854         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9855
9856         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9857         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9858         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9859
9860         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9861         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9862         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9863         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9864         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9865         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9866         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9867         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9868         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9869         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9870         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9871         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9872         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9873         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9874         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9875         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9876         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9877         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9878         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9879         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9880         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9881         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9882         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9883         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9884         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9885         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9886         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9887         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9888         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9889         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9890         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9891         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9892         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9893         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9894         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9895         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9896
9897         vmcs12->guest_interruptibility_info =
9898                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9899         vmcs12->guest_pending_dbg_exceptions =
9900                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9901         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9902                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9903         else
9904                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9905
9906         if (nested_cpu_has_preemption_timer(vmcs12)) {
9907                 if (vmcs12->vm_exit_controls &
9908                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9909                         vmcs12->vmx_preemption_timer_value =
9910                                 vmx_get_preemption_timer_value(vcpu);
9911                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9912         }
9913
9914         /*
9915          * In some cases (usually, nested EPT), L2 is allowed to change its
9916          * own CR3 without exiting. If it has changed it, we must keep it.
9917          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9918          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9919          *
9920          * Additionally, restore L2's PDPTR to vmcs12.
9921          */
9922         if (enable_ept) {
9923                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9924                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9925                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9926                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9927                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9928         }
9929
9930         if (nested_cpu_has_vid(vmcs12))
9931                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9932
9933         vmcs12->vm_entry_controls =
9934                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9935                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9936
9937         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9938                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9939                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9940         }
9941
9942         /* TODO: These cannot have changed unless we have MSR bitmaps and
9943          * the relevant bit asks not to trap the change */
9944         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9945                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9946         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9947                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9948         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9949         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9950         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9951         if (vmx_mpx_supported())
9952                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9953         if (nested_cpu_has_xsaves(vmcs12))
9954                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9955
9956         /* update exit information fields: */
9957
9958         vmcs12->vm_exit_reason = exit_reason;
9959         vmcs12->exit_qualification = exit_qualification;
9960
9961         vmcs12->vm_exit_intr_info = exit_intr_info;
9962         if ((vmcs12->vm_exit_intr_info &
9963              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9964             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9965                 vmcs12->vm_exit_intr_error_code =
9966                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9967         vmcs12->idt_vectoring_info_field = 0;
9968         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9969         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9970
9971         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9972                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9973                  * instead of reading the real value. */
9974                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9975
9976                 /*
9977                  * Transfer the event that L0 or L1 may wanted to inject into
9978                  * L2 to IDT_VECTORING_INFO_FIELD.
9979                  */
9980                 vmcs12_save_pending_event(vcpu, vmcs12);
9981         }
9982
9983         /*
9984          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9985          * preserved above and would only end up incorrectly in L1.
9986          */
9987         vcpu->arch.nmi_injected = false;
9988         kvm_clear_exception_queue(vcpu);
9989         kvm_clear_interrupt_queue(vcpu);
9990 }
9991
9992 /*
9993  * A part of what we need to when the nested L2 guest exits and we want to
9994  * run its L1 parent, is to reset L1's guest state to the host state specified
9995  * in vmcs12.
9996  * This function is to be called not only on normal nested exit, but also on
9997  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9998  * Failures During or After Loading Guest State").
9999  * This function should be called when the active VMCS is L1's (vmcs01).
10000  */
10001 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10002                                    struct vmcs12 *vmcs12)
10003 {
10004         struct kvm_segment seg;
10005
10006         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10007                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10008         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10009                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10010         else
10011                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10012         vmx_set_efer(vcpu, vcpu->arch.efer);
10013
10014         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10015         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10016         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10017         /*
10018          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10019          * actually changed, because it depends on the current state of
10020          * fpu_active (which may have changed).
10021          * Note that vmx_set_cr0 refers to efer set above.
10022          */
10023         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10024         /*
10025          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10026          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10027          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10028          */
10029         update_exception_bitmap(vcpu);
10030         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10031         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10032
10033         /*
10034          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10035          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10036          */
10037         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10038         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10039
10040         nested_ept_uninit_mmu_context(vcpu);
10041
10042         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10043         kvm_mmu_reset_context(vcpu);
10044
10045         if (!enable_ept)
10046                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10047
10048         if (enable_vpid) {
10049                 /*
10050                  * Trivially support vpid by letting L2s share their parent
10051                  * L1's vpid. TODO: move to a more elaborate solution, giving
10052                  * each L2 its own vpid and exposing the vpid feature to L1.
10053                  */
10054                 vmx_flush_tlb(vcpu);
10055         }
10056
10057
10058         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10059         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10060         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10061         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10062         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10063
10064         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10065         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10066                 vmcs_write64(GUEST_BNDCFGS, 0);
10067
10068         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10069                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10070                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10071         }
10072         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10073                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10074                         vmcs12->host_ia32_perf_global_ctrl);
10075
10076         /* Set L1 segment info according to Intel SDM
10077             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10078         seg = (struct kvm_segment) {
10079                 .base = 0,
10080                 .limit = 0xFFFFFFFF,
10081                 .selector = vmcs12->host_cs_selector,
10082                 .type = 11,
10083                 .present = 1,
10084                 .s = 1,
10085                 .g = 1
10086         };
10087         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10088                 seg.l = 1;
10089         else
10090                 seg.db = 1;
10091         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10092         seg = (struct kvm_segment) {
10093                 .base = 0,
10094                 .limit = 0xFFFFFFFF,
10095                 .type = 3,
10096                 .present = 1,
10097                 .s = 1,
10098                 .db = 1,
10099                 .g = 1
10100         };
10101         seg.selector = vmcs12->host_ds_selector;
10102         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10103         seg.selector = vmcs12->host_es_selector;
10104         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10105         seg.selector = vmcs12->host_ss_selector;
10106         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10107         seg.selector = vmcs12->host_fs_selector;
10108         seg.base = vmcs12->host_fs_base;
10109         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10110         seg.selector = vmcs12->host_gs_selector;
10111         seg.base = vmcs12->host_gs_base;
10112         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10113         seg = (struct kvm_segment) {
10114                 .base = vmcs12->host_tr_base,
10115                 .limit = 0x67,
10116                 .selector = vmcs12->host_tr_selector,
10117                 .type = 11,
10118                 .present = 1
10119         };
10120         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10121
10122         kvm_set_dr(vcpu, 7, 0x400);
10123         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10124
10125         if (cpu_has_vmx_msr_bitmap())
10126                 vmx_set_msr_bitmap(vcpu);
10127
10128         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10129                                 vmcs12->vm_exit_msr_load_count))
10130                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10131 }
10132
10133 /*
10134  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10135  * and modify vmcs12 to make it see what it would expect to see there if
10136  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10137  */
10138 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10139                               u32 exit_intr_info,
10140                               unsigned long exit_qualification)
10141 {
10142         struct vcpu_vmx *vmx = to_vmx(vcpu);
10143         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10144
10145         /* trying to cancel vmlaunch/vmresume is a bug */
10146         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10147
10148         leave_guest_mode(vcpu);
10149         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10150                        exit_qualification);
10151
10152         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10153                                  vmcs12->vm_exit_msr_store_count))
10154                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10155
10156         vmx_load_vmcs01(vcpu);
10157
10158         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10159             && nested_exit_intr_ack_set(vcpu)) {
10160                 int irq = kvm_cpu_get_interrupt(vcpu);
10161                 WARN_ON(irq < 0);
10162                 vmcs12->vm_exit_intr_info = irq |
10163                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10164         }
10165
10166         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10167                                        vmcs12->exit_qualification,
10168                                        vmcs12->idt_vectoring_info_field,
10169                                        vmcs12->vm_exit_intr_info,
10170                                        vmcs12->vm_exit_intr_error_code,
10171                                        KVM_ISA_VMX);
10172
10173         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10174         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10175         vmx_segment_cache_clear(vmx);
10176
10177         /* if no vmcs02 cache requested, remove the one we used */
10178         if (VMCS02_POOL_SIZE == 0)
10179                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10180
10181         load_vmcs12_host_state(vcpu, vmcs12);
10182
10183         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10184         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10185
10186         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10187         vmx->host_rsp = 0;
10188
10189         /* Unpin physical memory we referred to in vmcs02 */
10190         if (vmx->nested.apic_access_page) {
10191                 nested_release_page(vmx->nested.apic_access_page);
10192                 vmx->nested.apic_access_page = NULL;
10193         }
10194         if (vmx->nested.virtual_apic_page) {
10195                 nested_release_page(vmx->nested.virtual_apic_page);
10196                 vmx->nested.virtual_apic_page = NULL;
10197         }
10198         if (vmx->nested.pi_desc_page) {
10199                 kunmap(vmx->nested.pi_desc_page);
10200                 nested_release_page(vmx->nested.pi_desc_page);
10201                 vmx->nested.pi_desc_page = NULL;
10202                 vmx->nested.pi_desc = NULL;
10203         }
10204
10205         /*
10206          * We are now running in L2, mmu_notifier will force to reload the
10207          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10208          */
10209         kvm_vcpu_reload_apic_access_page(vcpu);
10210
10211         /*
10212          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10213          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10214          * success or failure flag accordingly.
10215          */
10216         if (unlikely(vmx->fail)) {
10217                 vmx->fail = 0;
10218                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10219         } else
10220                 nested_vmx_succeed(vcpu);
10221         if (enable_shadow_vmcs)
10222                 vmx->nested.sync_shadow_vmcs = true;
10223
10224         /* in case we halted in L2 */
10225         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10226 }
10227
10228 /*
10229  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10230  */
10231 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10232 {
10233         if (is_guest_mode(vcpu))
10234                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10235         free_nested(to_vmx(vcpu));
10236 }
10237
10238 /*
10239  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10240  * 23.7 "VM-entry failures during or after loading guest state" (this also
10241  * lists the acceptable exit-reason and exit-qualification parameters).
10242  * It should only be called before L2 actually succeeded to run, and when
10243  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10244  */
10245 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10246                         struct vmcs12 *vmcs12,
10247                         u32 reason, unsigned long qualification)
10248 {
10249         load_vmcs12_host_state(vcpu, vmcs12);
10250         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10251         vmcs12->exit_qualification = qualification;
10252         nested_vmx_succeed(vcpu);
10253         if (enable_shadow_vmcs)
10254                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10255 }
10256
10257 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10258                                struct x86_instruction_info *info,
10259                                enum x86_intercept_stage stage)
10260 {
10261         return X86EMUL_CONTINUE;
10262 }
10263
10264 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10265 {
10266         if (ple_gap)
10267                 shrink_ple_window(vcpu);
10268 }
10269
10270 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10271                                      struct kvm_memory_slot *slot)
10272 {
10273         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10274         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10275 }
10276
10277 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10278                                        struct kvm_memory_slot *slot)
10279 {
10280         kvm_mmu_slot_set_dirty(kvm, slot);
10281 }
10282
10283 static void vmx_flush_log_dirty(struct kvm *kvm)
10284 {
10285         kvm_flush_pml_buffers(kvm);
10286 }
10287
10288 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10289                                            struct kvm_memory_slot *memslot,
10290                                            gfn_t offset, unsigned long mask)
10291 {
10292         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10293 }
10294
10295 static struct kvm_x86_ops vmx_x86_ops = {
10296         .cpu_has_kvm_support = cpu_has_kvm_support,
10297         .disabled_by_bios = vmx_disabled_by_bios,
10298         .hardware_setup = hardware_setup,
10299         .hardware_unsetup = hardware_unsetup,
10300         .check_processor_compatibility = vmx_check_processor_compat,
10301         .hardware_enable = hardware_enable,
10302         .hardware_disable = hardware_disable,
10303         .cpu_has_accelerated_tpr = report_flexpriority,
10304
10305         .vcpu_create = vmx_create_vcpu,
10306         .vcpu_free = vmx_free_vcpu,
10307         .vcpu_reset = vmx_vcpu_reset,
10308
10309         .prepare_guest_switch = vmx_save_host_state,
10310         .vcpu_load = vmx_vcpu_load,
10311         .vcpu_put = vmx_vcpu_put,
10312
10313         .update_db_bp_intercept = update_exception_bitmap,
10314         .get_msr = vmx_get_msr,
10315         .set_msr = vmx_set_msr,
10316         .get_segment_base = vmx_get_segment_base,
10317         .get_segment = vmx_get_segment,
10318         .set_segment = vmx_set_segment,
10319         .get_cpl = vmx_get_cpl,
10320         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10321         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10322         .decache_cr3 = vmx_decache_cr3,
10323         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10324         .set_cr0 = vmx_set_cr0,
10325         .set_cr3 = vmx_set_cr3,
10326         .set_cr4 = vmx_set_cr4,
10327         .set_efer = vmx_set_efer,
10328         .get_idt = vmx_get_idt,
10329         .set_idt = vmx_set_idt,
10330         .get_gdt = vmx_get_gdt,
10331         .set_gdt = vmx_set_gdt,
10332         .get_dr6 = vmx_get_dr6,
10333         .set_dr6 = vmx_set_dr6,
10334         .set_dr7 = vmx_set_dr7,
10335         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10336         .cache_reg = vmx_cache_reg,
10337         .get_rflags = vmx_get_rflags,
10338         .set_rflags = vmx_set_rflags,
10339         .fpu_deactivate = vmx_fpu_deactivate,
10340
10341         .tlb_flush = vmx_flush_tlb,
10342
10343         .run = vmx_vcpu_run,
10344         .handle_exit = vmx_handle_exit,
10345         .skip_emulated_instruction = skip_emulated_instruction,
10346         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10347         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10348         .patch_hypercall = vmx_patch_hypercall,
10349         .set_irq = vmx_inject_irq,
10350         .set_nmi = vmx_inject_nmi,
10351         .queue_exception = vmx_queue_exception,
10352         .cancel_injection = vmx_cancel_injection,
10353         .interrupt_allowed = vmx_interrupt_allowed,
10354         .nmi_allowed = vmx_nmi_allowed,
10355         .get_nmi_mask = vmx_get_nmi_mask,
10356         .set_nmi_mask = vmx_set_nmi_mask,
10357         .enable_nmi_window = enable_nmi_window,
10358         .enable_irq_window = enable_irq_window,
10359         .update_cr8_intercept = update_cr8_intercept,
10360         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10361         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10362         .vm_has_apicv = vmx_vm_has_apicv,
10363         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10364         .hwapic_irr_update = vmx_hwapic_irr_update,
10365         .hwapic_isr_update = vmx_hwapic_isr_update,
10366         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10367         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10368
10369         .set_tss_addr = vmx_set_tss_addr,
10370         .get_tdp_level = get_ept_level,
10371         .get_mt_mask = vmx_get_mt_mask,
10372
10373         .get_exit_info = vmx_get_exit_info,
10374
10375         .get_lpage_level = vmx_get_lpage_level,
10376
10377         .cpuid_update = vmx_cpuid_update,
10378
10379         .rdtscp_supported = vmx_rdtscp_supported,
10380         .invpcid_supported = vmx_invpcid_supported,
10381
10382         .set_supported_cpuid = vmx_set_supported_cpuid,
10383
10384         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10385
10386         .set_tsc_khz = vmx_set_tsc_khz,
10387         .read_tsc_offset = vmx_read_tsc_offset,
10388         .write_tsc_offset = vmx_write_tsc_offset,
10389         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10390         .compute_tsc_offset = vmx_compute_tsc_offset,
10391         .read_l1_tsc = vmx_read_l1_tsc,
10392
10393         .set_tdp_cr3 = vmx_set_cr3,
10394
10395         .check_intercept = vmx_check_intercept,
10396         .handle_external_intr = vmx_handle_external_intr,
10397         .mpx_supported = vmx_mpx_supported,
10398         .xsaves_supported = vmx_xsaves_supported,
10399
10400         .check_nested_events = vmx_check_nested_events,
10401
10402         .sched_in = vmx_sched_in,
10403
10404         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10405         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10406         .flush_log_dirty = vmx_flush_log_dirty,
10407         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10408 };
10409
10410 static int __init vmx_init(void)
10411 {
10412         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10413                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10414         if (r)
10415                 return r;
10416
10417 #ifdef CONFIG_KEXEC
10418         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10419                            crash_vmclear_local_loaded_vmcss);
10420 #endif
10421
10422         return 0;
10423 }
10424
10425 static void __exit vmx_exit(void)
10426 {
10427 #ifdef CONFIG_KEXEC
10428         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10429         synchronize_rcu();
10430 #endif
10431
10432         kvm_exit();
10433 }
10434
10435 module_init(vmx_init)
10436 module_exit(vmx_exit)