arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_ept(void)
1243 {
1244         return vmcs_config.cpu_based_2nd_exec_ctrl &
1245                 SECONDARY_EXEC_ENABLE_EPT;
1246 }
1247
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1249 {
1250         return vmcs_config.cpu_based_2nd_exec_ctrl &
1251                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252 }
1253
1254 static inline bool cpu_has_vmx_ple(void)
1255 {
1256         return vmcs_config.cpu_based_2nd_exec_ctrl &
1257                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258 }
1259
1260 static inline bool cpu_has_vmx_basic_inout(void)
1261 {
1262         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263 }
1264
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1266 {
1267         return flexpriority_enabled && lapic_in_kernel(vcpu);
1268 }
1269
1270 static inline bool cpu_has_vmx_vpid(void)
1271 {
1272         return vmcs_config.cpu_based_2nd_exec_ctrl &
1273                 SECONDARY_EXEC_ENABLE_VPID;
1274 }
1275
1276 static inline bool cpu_has_vmx_rdtscp(void)
1277 {
1278         return vmcs_config.cpu_based_2nd_exec_ctrl &
1279                 SECONDARY_EXEC_RDTSCP;
1280 }
1281
1282 static inline bool cpu_has_vmx_invpcid(void)
1283 {
1284         return vmcs_config.cpu_based_2nd_exec_ctrl &
1285                 SECONDARY_EXEC_ENABLE_INVPCID;
1286 }
1287
1288 static inline bool cpu_has_virtual_nmis(void)
1289 {
1290         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1291 }
1292
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl &
1296                 SECONDARY_EXEC_WBINVD_EXITING;
1297 }
1298
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 {
1301         u64 vmx_msr;
1302         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303         /* check if the cpu supports writing r/o exit information fields */
1304         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1305                 return false;
1306
1307         return vmcs_config.cpu_based_2nd_exec_ctrl &
1308                 SECONDARY_EXEC_SHADOW_VMCS;
1309 }
1310
1311 static inline bool cpu_has_vmx_pml(void)
1312 {
1313         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1314 }
1315
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl &
1319                 SECONDARY_EXEC_TSC_SCALING;
1320 }
1321
1322 static inline bool report_flexpriority(void)
1323 {
1324         return flexpriority_enabled;
1325 }
1326
1327 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328 {
1329         return vmcs12->cpu_based_vm_exec_control & bit;
1330 }
1331
1332 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return (vmcs12->cpu_based_vm_exec_control &
1335                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336                 (vmcs12->secondary_vm_exec_control & bit);
1337 }
1338
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1340 {
1341         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342 }
1343
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control &
1347                 PIN_BASED_VMX_PREEMPTION_TIMER;
1348 }
1349
1350 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351 {
1352         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353 }
1354
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358                 vmx_xsaves_supported();
1359 }
1360
1361 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1362 {
1363         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1364 }
1365
1366 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1369 }
1370
1371 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1374 }
1375
1376 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1379 }
1380
1381 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1382 {
1383         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1384 }
1385
1386 static inline bool is_nmi(u32 intr_info)
1387 {
1388         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1389                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1390 }
1391
1392 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1393                               u32 exit_intr_info,
1394                               unsigned long exit_qualification);
1395 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1396                         struct vmcs12 *vmcs12,
1397                         u32 reason, unsigned long qualification);
1398
1399 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1400 {
1401         int i;
1402
1403         for (i = 0; i < vmx->nmsrs; ++i)
1404                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1405                         return i;
1406         return -1;
1407 }
1408
1409 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1410 {
1411     struct {
1412         u64 vpid : 16;
1413         u64 rsvd : 48;
1414         u64 gva;
1415     } operand = { vpid, 0, gva };
1416
1417     asm volatile (__ex(ASM_VMX_INVVPID)
1418                   /* CF==1 or ZF==1 --> rc = -1 */
1419                   "; ja 1f ; ud2 ; 1:"
1420                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1421 }
1422
1423 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1424 {
1425         struct {
1426                 u64 eptp, gpa;
1427         } operand = {eptp, gpa};
1428
1429         asm volatile (__ex(ASM_VMX_INVEPT)
1430                         /* CF==1 or ZF==1 --> rc = -1 */
1431                         "; ja 1f ; ud2 ; 1:\n"
1432                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1433 }
1434
1435 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1436 {
1437         int i;
1438
1439         i = __find_msr_index(vmx, msr);
1440         if (i >= 0)
1441                 return &vmx->guest_msrs[i];
1442         return NULL;
1443 }
1444
1445 static void vmcs_clear(struct vmcs *vmcs)
1446 {
1447         u64 phys_addr = __pa(vmcs);
1448         u8 error;
1449
1450         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1451                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1452                       : "cc", "memory");
1453         if (error)
1454                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1455                        vmcs, phys_addr);
1456 }
1457
1458 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1459 {
1460         vmcs_clear(loaded_vmcs->vmcs);
1461         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1462                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1463         loaded_vmcs->cpu = -1;
1464         loaded_vmcs->launched = 0;
1465 }
1466
1467 static void vmcs_load(struct vmcs *vmcs)
1468 {
1469         u64 phys_addr = __pa(vmcs);
1470         u8 error;
1471
1472         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1473                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1474                         : "cc", "memory");
1475         if (error)
1476                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1477                        vmcs, phys_addr);
1478 }
1479
1480 #ifdef CONFIG_KEXEC_CORE
1481 /*
1482  * This bitmap is used to indicate whether the vmclear
1483  * operation is enabled on all cpus. All disabled by
1484  * default.
1485  */
1486 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1487
1488 static inline void crash_enable_local_vmclear(int cpu)
1489 {
1490         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1491 }
1492
1493 static inline void crash_disable_local_vmclear(int cpu)
1494 {
1495         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline int crash_local_vmclear_enabled(int cpu)
1499 {
1500         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static void crash_vmclear_local_loaded_vmcss(void)
1504 {
1505         int cpu = raw_smp_processor_id();
1506         struct loaded_vmcs *v;
1507
1508         if (!crash_local_vmclear_enabled(cpu))
1509                 return;
1510
1511         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1512                             loaded_vmcss_on_cpu_link)
1513                 vmcs_clear(v->vmcs);
1514 }
1515 #else
1516 static inline void crash_enable_local_vmclear(int cpu) { }
1517 static inline void crash_disable_local_vmclear(int cpu) { }
1518 #endif /* CONFIG_KEXEC_CORE */
1519
1520 static void __loaded_vmcs_clear(void *arg)
1521 {
1522         struct loaded_vmcs *loaded_vmcs = arg;
1523         int cpu = raw_smp_processor_id();
1524
1525         if (loaded_vmcs->cpu != cpu)
1526                 return; /* vcpu migration can race with cpu offline */
1527         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1528                 per_cpu(current_vmcs, cpu) = NULL;
1529         crash_disable_local_vmclear(cpu);
1530         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1531
1532         /*
1533          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534          * is before setting loaded_vmcs->vcpu to -1 which is done in
1535          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536          * then adds the vmcs into percpu list before it is deleted.
1537          */
1538         smp_wmb();
1539
1540         loaded_vmcs_init(loaded_vmcs);
1541         crash_enable_local_vmclear(cpu);
1542 }
1543
1544 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1545 {
1546         int cpu = loaded_vmcs->cpu;
1547
1548         if (cpu != -1)
1549                 smp_call_function_single(cpu,
1550                          __loaded_vmcs_clear, loaded_vmcs, 1);
1551 }
1552
1553 static inline void vpid_sync_vcpu_single(int vpid)
1554 {
1555         if (vpid == 0)
1556                 return;
1557
1558         if (cpu_has_vmx_invvpid_single())
1559                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1560 }
1561
1562 static inline void vpid_sync_vcpu_global(void)
1563 {
1564         if (cpu_has_vmx_invvpid_global())
1565                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1566 }
1567
1568 static inline void vpid_sync_context(int vpid)
1569 {
1570         if (cpu_has_vmx_invvpid_single())
1571                 vpid_sync_vcpu_single(vpid);
1572         else
1573                 vpid_sync_vcpu_global();
1574 }
1575
1576 static inline void ept_sync_global(void)
1577 {
1578         if (cpu_has_vmx_invept_global())
1579                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1580 }
1581
1582 static inline void ept_sync_context(u64 eptp)
1583 {
1584         if (enable_ept) {
1585                 if (cpu_has_vmx_invept_context())
1586                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1587                 else
1588                         ept_sync_global();
1589         }
1590 }
1591
1592 static __always_inline void vmcs_check16(unsigned long field)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1595                          "16-bit accessor invalid for 64-bit field");
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1597                          "16-bit accessor invalid for 64-bit high field");
1598         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1599                          "16-bit accessor invalid for 32-bit high field");
1600         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1601                          "16-bit accessor invalid for natural width field");
1602 }
1603
1604 static __always_inline void vmcs_check32(unsigned long field)
1605 {
1606         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1607                          "32-bit accessor invalid for 16-bit field");
1608         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609                          "32-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check64(unsigned long field)
1613 {
1614         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615                          "64-bit accessor invalid for 16-bit field");
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1617                          "64-bit accessor invalid for 64-bit high field");
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1619                          "64-bit accessor invalid for 32-bit field");
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1621                          "64-bit accessor invalid for natural width field");
1622 }
1623
1624 static __always_inline void vmcs_checkl(unsigned long field)
1625 {
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1627                          "Natural width accessor invalid for 16-bit field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1629                          "Natural width accessor invalid for 64-bit field");
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1631                          "Natural width accessor invalid for 64-bit high field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1633                          "Natural width accessor invalid for 32-bit field");
1634 }
1635
1636 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1637 {
1638         unsigned long value;
1639
1640         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1641                       : "=a"(value) : "d"(field) : "cc");
1642         return value;
1643 }
1644
1645 static __always_inline u16 vmcs_read16(unsigned long field)
1646 {
1647         vmcs_check16(field);
1648         return __vmcs_readl(field);
1649 }
1650
1651 static __always_inline u32 vmcs_read32(unsigned long field)
1652 {
1653         vmcs_check32(field);
1654         return __vmcs_readl(field);
1655 }
1656
1657 static __always_inline u64 vmcs_read64(unsigned long field)
1658 {
1659         vmcs_check64(field);
1660 #ifdef CONFIG_X86_64
1661         return __vmcs_readl(field);
1662 #else
1663         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1664 #endif
1665 }
1666
1667 static __always_inline unsigned long vmcs_readl(unsigned long field)
1668 {
1669         vmcs_checkl(field);
1670         return __vmcs_readl(field);
1671 }
1672
1673 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1674 {
1675         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1676                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1677         dump_stack();
1678 }
1679
1680 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1681 {
1682         u8 error;
1683
1684         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1685                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1686         if (unlikely(error))
1687                 vmwrite_error(field, value);
1688 }
1689
1690 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1691 {
1692         vmcs_check16(field);
1693         __vmcs_writel(field, value);
1694 }
1695
1696 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1697 {
1698         vmcs_check32(field);
1699         __vmcs_writel(field, value);
1700 }
1701
1702 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1703 {
1704         vmcs_check64(field);
1705         __vmcs_writel(field, value);
1706 #ifndef CONFIG_X86_64
1707         asm volatile ("");
1708         __vmcs_writel(field+1, value >> 32);
1709 #endif
1710 }
1711
1712 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1713 {
1714         vmcs_checkl(field);
1715         __vmcs_writel(field, value);
1716 }
1717
1718 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1719 {
1720         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1721                          "vmcs_clear_bits does not support 64-bit fields");
1722         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1723 }
1724
1725 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1726 {
1727         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1728                          "vmcs_set_bits does not support 64-bit fields");
1729         __vmcs_writel(field, __vmcs_readl(field) | mask);
1730 }
1731
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1733 {
1734         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1735 }
1736
1737 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1738 {
1739         vmcs_write32(VM_ENTRY_CONTROLS, val);
1740         vmx->vm_entry_controls_shadow = val;
1741 }
1742
1743 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1744 {
1745         if (vmx->vm_entry_controls_shadow != val)
1746                 vm_entry_controls_init(vmx, val);
1747 }
1748
1749 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1750 {
1751         return vmx->vm_entry_controls_shadow;
1752 }
1753
1754
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1756 {
1757         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1758 }
1759
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1763 }
1764
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1766 {
1767         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1768 }
1769
1770 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1771 {
1772         vmcs_write32(VM_EXIT_CONTROLS, val);
1773         vmx->vm_exit_controls_shadow = val;
1774 }
1775
1776 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1777 {
1778         if (vmx->vm_exit_controls_shadow != val)
1779                 vm_exit_controls_init(vmx, val);
1780 }
1781
1782 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1783 {
1784         return vmx->vm_exit_controls_shadow;
1785 }
1786
1787
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1789 {
1790         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1791 }
1792
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1796 }
1797
1798 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1799 {
1800         vmx->segment_cache.bitmask = 0;
1801 }
1802
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1804                                        unsigned field)
1805 {
1806         bool ret;
1807         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1808
1809         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1810                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1811                 vmx->segment_cache.bitmask = 0;
1812         }
1813         ret = vmx->segment_cache.bitmask & mask;
1814         vmx->segment_cache.bitmask |= mask;
1815         return ret;
1816 }
1817
1818 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1819 {
1820         u16 *p = &vmx->segment_cache.seg[seg].selector;
1821
1822         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1823                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1824         return *p;
1825 }
1826
1827 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         ulong *p = &vmx->segment_cache.seg[seg].base;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1832                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1833         return *p;
1834 }
1835
1836 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         u32 *p = &vmx->segment_cache.seg[seg].limit;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1841                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].ar;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1851         return *p;
1852 }
1853
1854 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1855 {
1856         u32 eb;
1857
1858         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1859              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1860         if ((vcpu->guest_debug &
1861              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1862             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1863                 eb |= 1u << BP_VECTOR;
1864         if (to_vmx(vcpu)->rmode.vm86_active)
1865                 eb = ~0;
1866         if (enable_ept)
1867                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1868
1869         /* When we are running a nested L2 guest and L1 specified for it a
1870          * certain exception bitmap, we must trap the same exceptions and pass
1871          * them to L1. When running L2, we will only handle the exceptions
1872          * specified above if L1 did not want them.
1873          */
1874         if (is_guest_mode(vcpu))
1875                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1876
1877         vmcs_write32(EXCEPTION_BITMAP, eb);
1878 }
1879
1880 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1881                 unsigned long entry, unsigned long exit)
1882 {
1883         vm_entry_controls_clearbit(vmx, entry);
1884         vm_exit_controls_clearbit(vmx, exit);
1885 }
1886
1887 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1888 {
1889         unsigned i;
1890         struct msr_autoload *m = &vmx->msr_autoload;
1891
1892         switch (msr) {
1893         case MSR_EFER:
1894                 if (cpu_has_load_ia32_efer) {
1895                         clear_atomic_switch_msr_special(vmx,
1896                                         VM_ENTRY_LOAD_IA32_EFER,
1897                                         VM_EXIT_LOAD_IA32_EFER);
1898                         return;
1899                 }
1900                 break;
1901         case MSR_CORE_PERF_GLOBAL_CTRL:
1902                 if (cpu_has_load_perf_global_ctrl) {
1903                         clear_atomic_switch_msr_special(vmx,
1904                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1905                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1906                         return;
1907                 }
1908                 break;
1909         }
1910
1911         for (i = 0; i < m->nr; ++i)
1912                 if (m->guest[i].index == msr)
1913                         break;
1914
1915         if (i == m->nr)
1916                 return;
1917         --m->nr;
1918         m->guest[i] = m->guest[m->nr];
1919         m->host[i] = m->host[m->nr];
1920         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1921         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1922 }
1923
1924 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1925                 unsigned long entry, unsigned long exit,
1926                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1927                 u64 guest_val, u64 host_val)
1928 {
1929         vmcs_write64(guest_val_vmcs, guest_val);
1930         vmcs_write64(host_val_vmcs, host_val);
1931         vm_entry_controls_setbit(vmx, entry);
1932         vm_exit_controls_setbit(vmx, exit);
1933 }
1934
1935 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1936                                   u64 guest_val, u64 host_val)
1937 {
1938         unsigned i;
1939         struct msr_autoload *m = &vmx->msr_autoload;
1940
1941         switch (msr) {
1942         case MSR_EFER:
1943                 if (cpu_has_load_ia32_efer) {
1944                         add_atomic_switch_msr_special(vmx,
1945                                         VM_ENTRY_LOAD_IA32_EFER,
1946                                         VM_EXIT_LOAD_IA32_EFER,
1947                                         GUEST_IA32_EFER,
1948                                         HOST_IA32_EFER,
1949                                         guest_val, host_val);
1950                         return;
1951                 }
1952                 break;
1953         case MSR_CORE_PERF_GLOBAL_CTRL:
1954                 if (cpu_has_load_perf_global_ctrl) {
1955                         add_atomic_switch_msr_special(vmx,
1956                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1957                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1958                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1959                                         HOST_IA32_PERF_GLOBAL_CTRL,
1960                                         guest_val, host_val);
1961                         return;
1962                 }
1963                 break;
1964         case MSR_IA32_PEBS_ENABLE:
1965                 /* PEBS needs a quiescent period after being disabled (to write
1966                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1967                  * provide that period, so a CPU could write host's record into
1968                  * guest's memory.
1969                  */
1970                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1971         }
1972
1973         for (i = 0; i < m->nr; ++i)
1974                 if (m->guest[i].index == msr)
1975                         break;
1976
1977         if (i == NR_AUTOLOAD_MSRS) {
1978                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1979                                 "Can't add msr %x\n", msr);
1980                 return;
1981         } else if (i == m->nr) {
1982                 ++m->nr;
1983                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1984                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1985         }
1986
1987         m->guest[i].index = msr;
1988         m->guest[i].value = guest_val;
1989         m->host[i].index = msr;
1990         m->host[i].value = host_val;
1991 }
1992
1993 static void reload_tss(void)
1994 {
1995         /*
1996          * VT restores TR but not its size.  Useless.
1997          */
1998         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1999         struct desc_struct *descs;
2000
2001         descs = (void *)gdt->address;
2002         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
2003         load_TR_desc();
2004 }
2005
2006 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2007 {
2008         u64 guest_efer = vmx->vcpu.arch.efer;
2009         u64 ignore_bits = 0;
2010
2011         if (!enable_ept) {
2012                 /*
2013                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2014                  * host CPUID is more efficient than testing guest CPUID
2015                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2016                  */
2017                 if (boot_cpu_has(X86_FEATURE_SMEP))
2018                         guest_efer |= EFER_NX;
2019                 else if (!(guest_efer & EFER_NX))
2020                         ignore_bits |= EFER_NX;
2021         }
2022
2023         /*
2024          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2025          */
2026         ignore_bits |= EFER_SCE;
2027 #ifdef CONFIG_X86_64
2028         ignore_bits |= EFER_LMA | EFER_LME;
2029         /* SCE is meaningful only in long mode on Intel */
2030         if (guest_efer & EFER_LMA)
2031                 ignore_bits &= ~(u64)EFER_SCE;
2032 #endif
2033
2034         clear_atomic_switch_msr(vmx, MSR_EFER);
2035
2036         /*
2037          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2038          * On CPUs that support "load IA32_EFER", always switch EFER
2039          * atomically, since it's faster than switching it manually.
2040          */
2041         if (cpu_has_load_ia32_efer ||
2042             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2043                 if (!(guest_efer & EFER_LMA))
2044                         guest_efer &= ~EFER_LME;
2045                 if (guest_efer != host_efer)
2046                         add_atomic_switch_msr(vmx, MSR_EFER,
2047                                               guest_efer, host_efer);
2048                 return false;
2049         } else {
2050                 guest_efer &= ~ignore_bits;
2051                 guest_efer |= host_efer & ignore_bits;
2052
2053                 vmx->guest_msrs[efer_offset].data = guest_efer;
2054                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2055
2056                 return true;
2057         }
2058 }
2059
2060 static unsigned long segment_base(u16 selector)
2061 {
2062         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2063         struct desc_struct *d;
2064         unsigned long table_base;
2065         unsigned long v;
2066
2067         if (!(selector & ~3))
2068                 return 0;
2069
2070         table_base = gdt->address;
2071
2072         if (selector & 4) {           /* from ldt */
2073                 u16 ldt_selector = kvm_read_ldt();
2074
2075                 if (!(ldt_selector & ~3))
2076                         return 0;
2077
2078                 table_base = segment_base(ldt_selector);
2079         }
2080         d = (struct desc_struct *)(table_base + (selector & ~7));
2081         v = get_desc_base(d);
2082 #ifdef CONFIG_X86_64
2083        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2084                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2085 #endif
2086         return v;
2087 }
2088
2089 static inline unsigned long kvm_read_tr_base(void)
2090 {
2091         u16 tr;
2092         asm("str %0" : "=g"(tr));
2093         return segment_base(tr);
2094 }
2095
2096 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2097 {
2098         struct vcpu_vmx *vmx = to_vmx(vcpu);
2099         int i;
2100
2101         if (vmx->host_state.loaded)
2102                 return;
2103
2104         vmx->host_state.loaded = 1;
2105         /*
2106          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2107          * allow segment selectors with cpl > 0 or ti == 1.
2108          */
2109         vmx->host_state.ldt_sel = kvm_read_ldt();
2110         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2111         savesegment(fs, vmx->host_state.fs_sel);
2112         if (!(vmx->host_state.fs_sel & 7)) {
2113                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2114                 vmx->host_state.fs_reload_needed = 0;
2115         } else {
2116                 vmcs_write16(HOST_FS_SELECTOR, 0);
2117                 vmx->host_state.fs_reload_needed = 1;
2118         }
2119         savesegment(gs, vmx->host_state.gs_sel);
2120         if (!(vmx->host_state.gs_sel & 7))
2121                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2122         else {
2123                 vmcs_write16(HOST_GS_SELECTOR, 0);
2124                 vmx->host_state.gs_ldt_reload_needed = 1;
2125         }
2126
2127 #ifdef CONFIG_X86_64
2128         savesegment(ds, vmx->host_state.ds_sel);
2129         savesegment(es, vmx->host_state.es_sel);
2130 #endif
2131
2132 #ifdef CONFIG_X86_64
2133         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2134         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2135 #else
2136         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2137         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2138 #endif
2139
2140 #ifdef CONFIG_X86_64
2141         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2142         if (is_long_mode(&vmx->vcpu))
2143                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2144 #endif
2145         if (boot_cpu_has(X86_FEATURE_MPX))
2146                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2147         for (i = 0; i < vmx->save_nmsrs; ++i)
2148                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2149                                    vmx->guest_msrs[i].data,
2150                                    vmx->guest_msrs[i].mask);
2151 }
2152
2153 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2154 {
2155         if (!vmx->host_state.loaded)
2156                 return;
2157
2158         ++vmx->vcpu.stat.host_state_reload;
2159         vmx->host_state.loaded = 0;
2160 #ifdef CONFIG_X86_64
2161         if (is_long_mode(&vmx->vcpu))
2162                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2163 #endif
2164         if (vmx->host_state.gs_ldt_reload_needed) {
2165                 kvm_load_ldt(vmx->host_state.ldt_sel);
2166 #ifdef CONFIG_X86_64
2167                 load_gs_index(vmx->host_state.gs_sel);
2168 #else
2169                 loadsegment(gs, vmx->host_state.gs_sel);
2170 #endif
2171         }
2172         if (vmx->host_state.fs_reload_needed)
2173                 loadsegment(fs, vmx->host_state.fs_sel);
2174 #ifdef CONFIG_X86_64
2175         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2176                 loadsegment(ds, vmx->host_state.ds_sel);
2177                 loadsegment(es, vmx->host_state.es_sel);
2178         }
2179 #endif
2180         reload_tss();
2181 #ifdef CONFIG_X86_64
2182         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2183 #endif
2184         if (vmx->host_state.msr_host_bndcfgs)
2185                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2186         load_gdt(this_cpu_ptr(&host_gdt));
2187 }
2188
2189 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2190 {
2191         preempt_disable();
2192         __vmx_load_host_state(vmx);
2193         preempt_enable();
2194 }
2195
2196 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2197 {
2198         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2199         struct pi_desc old, new;
2200         unsigned int dest;
2201
2202         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2203                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2204                 !kvm_vcpu_apicv_active(vcpu))
2205                 return;
2206
2207         do {
2208                 old.control = new.control = pi_desc->control;
2209
2210                 /*
2211                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2212                  * are two possible cases:
2213                  * 1. After running 'pre_block', context switch
2214                  *    happened. For this case, 'sn' was set in
2215                  *    vmx_vcpu_put(), so we need to clear it here.
2216                  * 2. After running 'pre_block', we were blocked,
2217                  *    and woken up by some other guy. For this case,
2218                  *    we don't need to do anything, 'pi_post_block'
2219                  *    will do everything for us. However, we cannot
2220                  *    check whether it is case #1 or case #2 here
2221                  *    (maybe, not needed), so we also clear sn here,
2222                  *    I think it is not a big deal.
2223                  */
2224                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2225                         if (vcpu->cpu != cpu) {
2226                                 dest = cpu_physical_id(cpu);
2227
2228                                 if (x2apic_enabled())
2229                                         new.ndst = dest;
2230                                 else
2231                                         new.ndst = (dest << 8) & 0xFF00;
2232                         }
2233
2234                         /* set 'NV' to 'notification vector' */
2235                         new.nv = POSTED_INTR_VECTOR;
2236                 }
2237
2238                 /* Allow posting non-urgent interrupts */
2239                 new.sn = 0;
2240         } while (cmpxchg(&pi_desc->control, old.control,
2241                         new.control) != old.control);
2242 }
2243
2244 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2245 {
2246         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2247         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2248 }
2249
2250 /*
2251  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2252  * vcpu mutex is already taken.
2253  */
2254 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2255 {
2256         struct vcpu_vmx *vmx = to_vmx(vcpu);
2257         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2258         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2259
2260         if (!vmm_exclusive)
2261                 kvm_cpu_vmxon(phys_addr);
2262         else if (!already_loaded)
2263                 loaded_vmcs_clear(vmx->loaded_vmcs);
2264
2265         if (!already_loaded) {
2266                 local_irq_disable();
2267                 crash_disable_local_vmclear(cpu);
2268
2269                 /*
2270                  * Read loaded_vmcs->cpu should be before fetching
2271                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2272                  * See the comments in __loaded_vmcs_clear().
2273                  */
2274                 smp_rmb();
2275
2276                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2277                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2278                 crash_enable_local_vmclear(cpu);
2279                 local_irq_enable();
2280         }
2281
2282         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2283                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2284                 vmcs_load(vmx->loaded_vmcs->vmcs);
2285         }
2286
2287         if (!already_loaded) {
2288                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2289                 unsigned long sysenter_esp;
2290
2291                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2292
2293                 /*
2294                  * Linux uses per-cpu TSS and GDT, so set these when switching
2295                  * processors.
2296                  */
2297                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2298                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2299
2300                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2301                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2302
2303                 vmx->loaded_vmcs->cpu = cpu;
2304         }
2305
2306         /* Setup TSC multiplier */
2307         if (kvm_has_tsc_control &&
2308             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2309                 decache_tsc_multiplier(vmx);
2310
2311         vmx_vcpu_pi_load(vcpu, cpu);
2312         vmx->host_pkru = read_pkru();
2313 }
2314
2315 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2316 {
2317         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2318
2319         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2320                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2321                 !kvm_vcpu_apicv_active(vcpu))
2322                 return;
2323
2324         /* Set SN when the vCPU is preempted */
2325         if (vcpu->preempted)
2326                 pi_set_sn(pi_desc);
2327 }
2328
2329 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2330 {
2331         vmx_vcpu_pi_put(vcpu);
2332
2333         __vmx_load_host_state(to_vmx(vcpu));
2334         if (!vmm_exclusive) {
2335                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2336                 vcpu->cpu = -1;
2337                 kvm_cpu_vmxoff();
2338         }
2339 }
2340
2341 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2342
2343 /*
2344  * Return the cr0 value that a nested guest would read. This is a combination
2345  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2346  * its hypervisor (cr0_read_shadow).
2347  */
2348 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2349 {
2350         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2351                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2352 }
2353 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2354 {
2355         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2356                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2357 }
2358
2359 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2360 {
2361         unsigned long rflags, save_rflags;
2362
2363         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2364                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2365                 rflags = vmcs_readl(GUEST_RFLAGS);
2366                 if (to_vmx(vcpu)->rmode.vm86_active) {
2367                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2368                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2369                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2370                 }
2371                 to_vmx(vcpu)->rflags = rflags;
2372         }
2373         return to_vmx(vcpu)->rflags;
2374 }
2375
2376 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2377 {
2378         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2379         to_vmx(vcpu)->rflags = rflags;
2380         if (to_vmx(vcpu)->rmode.vm86_active) {
2381                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2382                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2383         }
2384         vmcs_writel(GUEST_RFLAGS, rflags);
2385 }
2386
2387 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2388 {
2389         return to_vmx(vcpu)->guest_pkru;
2390 }
2391
2392 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2393 {
2394         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2395         int ret = 0;
2396
2397         if (interruptibility & GUEST_INTR_STATE_STI)
2398                 ret |= KVM_X86_SHADOW_INT_STI;
2399         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2400                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2401
2402         return ret;
2403 }
2404
2405 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2406 {
2407         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2408         u32 interruptibility = interruptibility_old;
2409
2410         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2411
2412         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2413                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2414         else if (mask & KVM_X86_SHADOW_INT_STI)
2415                 interruptibility |= GUEST_INTR_STATE_STI;
2416
2417         if ((interruptibility != interruptibility_old))
2418                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2419 }
2420
2421 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2422 {
2423         unsigned long rip;
2424
2425         rip = kvm_rip_read(vcpu);
2426         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2427         kvm_rip_write(vcpu, rip);
2428
2429         /* skipping an emulated instruction also counts */
2430         vmx_set_interrupt_shadow(vcpu, 0);
2431 }
2432
2433 /*
2434  * KVM wants to inject page-faults which it got to the guest. This function
2435  * checks whether in a nested guest, we need to inject them to L1 or L2.
2436  */
2437 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2438 {
2439         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2440
2441         if (!(vmcs12->exception_bitmap & (1u << nr)))
2442                 return 0;
2443
2444         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2445                           vmcs_read32(VM_EXIT_INTR_INFO),
2446                           vmcs_readl(EXIT_QUALIFICATION));
2447         return 1;
2448 }
2449
2450 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2451                                 bool has_error_code, u32 error_code,
2452                                 bool reinject)
2453 {
2454         struct vcpu_vmx *vmx = to_vmx(vcpu);
2455         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2456
2457         if (!reinject && is_guest_mode(vcpu) &&
2458             nested_vmx_check_exception(vcpu, nr))
2459                 return;
2460
2461         if (has_error_code) {
2462                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2463                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2464         }
2465
2466         if (vmx->rmode.vm86_active) {
2467                 int inc_eip = 0;
2468                 if (kvm_exception_is_soft(nr))
2469                         inc_eip = vcpu->arch.event_exit_inst_len;
2470                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2471                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2472                 return;
2473         }
2474
2475         if (kvm_exception_is_soft(nr)) {
2476                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2477                              vmx->vcpu.arch.event_exit_inst_len);
2478                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2479         } else
2480                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2481
2482         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2483 }
2484
2485 static bool vmx_rdtscp_supported(void)
2486 {
2487         return cpu_has_vmx_rdtscp();
2488 }
2489
2490 static bool vmx_invpcid_supported(void)
2491 {
2492         return cpu_has_vmx_invpcid() && enable_ept;
2493 }
2494
2495 /*
2496  * Swap MSR entry in host/guest MSR entry array.
2497  */
2498 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2499 {
2500         struct shared_msr_entry tmp;
2501
2502         tmp = vmx->guest_msrs[to];
2503         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2504         vmx->guest_msrs[from] = tmp;
2505 }
2506
2507 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2508 {
2509         unsigned long *msr_bitmap;
2510
2511         if (is_guest_mode(vcpu))
2512                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2513         else if (cpu_has_secondary_exec_ctrls() &&
2514                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2515                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2516                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2517                         if (is_long_mode(vcpu))
2518                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2519                         else
2520                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2521                 } else {
2522                         if (is_long_mode(vcpu))
2523                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2524                         else
2525                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2526                 }
2527         } else {
2528                 if (is_long_mode(vcpu))
2529                         msr_bitmap = vmx_msr_bitmap_longmode;
2530                 else
2531                         msr_bitmap = vmx_msr_bitmap_legacy;
2532         }
2533
2534         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2535 }
2536
2537 /*
2538  * Set up the vmcs to automatically save and restore system
2539  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2540  * mode, as fiddling with msrs is very expensive.
2541  */
2542 static void setup_msrs(struct vcpu_vmx *vmx)
2543 {
2544         int save_nmsrs, index;
2545
2546         save_nmsrs = 0;
2547 #ifdef CONFIG_X86_64
2548         if (is_long_mode(&vmx->vcpu)) {
2549                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2550                 if (index >= 0)
2551                         move_msr_up(vmx, index, save_nmsrs++);
2552                 index = __find_msr_index(vmx, MSR_LSTAR);
2553                 if (index >= 0)
2554                         move_msr_up(vmx, index, save_nmsrs++);
2555                 index = __find_msr_index(vmx, MSR_CSTAR);
2556                 if (index >= 0)
2557                         move_msr_up(vmx, index, save_nmsrs++);
2558                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2559                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2560                         move_msr_up(vmx, index, save_nmsrs++);
2561                 /*
2562                  * MSR_STAR is only needed on long mode guests, and only
2563                  * if efer.sce is enabled.
2564                  */
2565                 index = __find_msr_index(vmx, MSR_STAR);
2566                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2567                         move_msr_up(vmx, index, save_nmsrs++);
2568         }
2569 #endif
2570         index = __find_msr_index(vmx, MSR_EFER);
2571         if (index >= 0 && update_transition_efer(vmx, index))
2572                 move_msr_up(vmx, index, save_nmsrs++);
2573
2574         vmx->save_nmsrs = save_nmsrs;
2575
2576         if (cpu_has_vmx_msr_bitmap())
2577                 vmx_set_msr_bitmap(&vmx->vcpu);
2578 }
2579
2580 /*
2581  * reads and returns guest's timestamp counter "register"
2582  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2583  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2584  */
2585 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2586 {
2587         u64 host_tsc, tsc_offset;
2588
2589         host_tsc = rdtsc();
2590         tsc_offset = vmcs_read64(TSC_OFFSET);
2591         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2592 }
2593
2594 /*
2595  * writes 'offset' into guest's timestamp counter offset register
2596  */
2597 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2598 {
2599         if (is_guest_mode(vcpu)) {
2600                 /*
2601                  * We're here if L1 chose not to trap WRMSR to TSC. According
2602                  * to the spec, this should set L1's TSC; The offset that L1
2603                  * set for L2 remains unchanged, and still needs to be added
2604                  * to the newly set TSC to get L2's TSC.
2605                  */
2606                 struct vmcs12 *vmcs12;
2607                 /* recalculate vmcs02.TSC_OFFSET: */
2608                 vmcs12 = get_vmcs12(vcpu);
2609                 vmcs_write64(TSC_OFFSET, offset +
2610                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2611                          vmcs12->tsc_offset : 0));
2612         } else {
2613                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2614                                            vmcs_read64(TSC_OFFSET), offset);
2615                 vmcs_write64(TSC_OFFSET, offset);
2616         }
2617 }
2618
2619 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2620 {
2621         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2622         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2623 }
2624
2625 /*
2626  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2627  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2628  * all guests if the "nested" module option is off, and can also be disabled
2629  * for a single guest by disabling its VMX cpuid bit.
2630  */
2631 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2632 {
2633         return nested && guest_cpuid_has_vmx(vcpu);
2634 }
2635
2636 /*
2637  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2638  * returned for the various VMX controls MSRs when nested VMX is enabled.
2639  * The same values should also be used to verify that vmcs12 control fields are
2640  * valid during nested entry from L1 to L2.
2641  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2642  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2643  * bit in the high half is on if the corresponding bit in the control field
2644  * may be on. See also vmx_control_verify().
2645  */
2646 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2647 {
2648         /*
2649          * Note that as a general rule, the high half of the MSRs (bits in
2650          * the control fields which may be 1) should be initialized by the
2651          * intersection of the underlying hardware's MSR (i.e., features which
2652          * can be supported) and the list of features we want to expose -
2653          * because they are known to be properly supported in our code.
2654          * Also, usually, the low half of the MSRs (bits which must be 1) can
2655          * be set to 0, meaning that L1 may turn off any of these bits. The
2656          * reason is that if one of these bits is necessary, it will appear
2657          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2658          * fields of vmcs01 and vmcs02, will turn these bits off - and
2659          * nested_vmx_exit_handled() will not pass related exits to L1.
2660          * These rules have exceptions below.
2661          */
2662
2663         /* pin-based controls */
2664         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2665                 vmx->nested.nested_vmx_pinbased_ctls_low,
2666                 vmx->nested.nested_vmx_pinbased_ctls_high);
2667         vmx->nested.nested_vmx_pinbased_ctls_low |=
2668                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2669         vmx->nested.nested_vmx_pinbased_ctls_high &=
2670                 PIN_BASED_EXT_INTR_MASK |
2671                 PIN_BASED_NMI_EXITING |
2672                 PIN_BASED_VIRTUAL_NMIS;
2673         vmx->nested.nested_vmx_pinbased_ctls_high |=
2674                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2675                 PIN_BASED_VMX_PREEMPTION_TIMER;
2676         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2677                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2678                         PIN_BASED_POSTED_INTR;
2679
2680         /* exit controls */
2681         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2682                 vmx->nested.nested_vmx_exit_ctls_low,
2683                 vmx->nested.nested_vmx_exit_ctls_high);
2684         vmx->nested.nested_vmx_exit_ctls_low =
2685                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2686
2687         vmx->nested.nested_vmx_exit_ctls_high &=
2688 #ifdef CONFIG_X86_64
2689                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2690 #endif
2691                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2692         vmx->nested.nested_vmx_exit_ctls_high |=
2693                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2694                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2695                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2696
2697         if (kvm_mpx_supported())
2698                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2699
2700         /* We support free control of debug control saving. */
2701         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2702
2703         /* entry controls */
2704         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2705                 vmx->nested.nested_vmx_entry_ctls_low,
2706                 vmx->nested.nested_vmx_entry_ctls_high);
2707         vmx->nested.nested_vmx_entry_ctls_low =
2708                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2709         vmx->nested.nested_vmx_entry_ctls_high &=
2710 #ifdef CONFIG_X86_64
2711                 VM_ENTRY_IA32E_MODE |
2712 #endif
2713                 VM_ENTRY_LOAD_IA32_PAT;
2714         vmx->nested.nested_vmx_entry_ctls_high |=
2715                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2716         if (kvm_mpx_supported())
2717                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2718
2719         /* We support free control of debug control loading. */
2720         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2721
2722         /* cpu-based controls */
2723         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2724                 vmx->nested.nested_vmx_procbased_ctls_low,
2725                 vmx->nested.nested_vmx_procbased_ctls_high);
2726         vmx->nested.nested_vmx_procbased_ctls_low =
2727                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2728         vmx->nested.nested_vmx_procbased_ctls_high &=
2729                 CPU_BASED_VIRTUAL_INTR_PENDING |
2730                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2731                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2732                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2733                 CPU_BASED_CR3_STORE_EXITING |
2734 #ifdef CONFIG_X86_64
2735                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2736 #endif
2737                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2738                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2739                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2740                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2741                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2742         /*
2743          * We can allow some features even when not supported by the
2744          * hardware. For example, L1 can specify an MSR bitmap - and we
2745          * can use it to avoid exits to L1 - even when L0 runs L2
2746          * without MSR bitmaps.
2747          */
2748         vmx->nested.nested_vmx_procbased_ctls_high |=
2749                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2750                 CPU_BASED_USE_MSR_BITMAPS;
2751
2752         /* We support free control of CR3 access interception. */
2753         vmx->nested.nested_vmx_procbased_ctls_low &=
2754                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2755
2756         /* secondary cpu-based controls */
2757         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2758                 vmx->nested.nested_vmx_secondary_ctls_low,
2759                 vmx->nested.nested_vmx_secondary_ctls_high);
2760         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2761         vmx->nested.nested_vmx_secondary_ctls_high &=
2762                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2763                 SECONDARY_EXEC_RDTSCP |
2764                 SECONDARY_EXEC_DESC |
2765                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2766                 SECONDARY_EXEC_ENABLE_VPID |
2767                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2768                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2769                 SECONDARY_EXEC_WBINVD_EXITING |
2770                 SECONDARY_EXEC_XSAVES;
2771
2772         if (enable_ept) {
2773                 /* nested EPT: emulate EPT also to L1 */
2774                 vmx->nested.nested_vmx_secondary_ctls_high |=
2775                         SECONDARY_EXEC_ENABLE_EPT;
2776                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2777                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2778                          VMX_EPT_INVEPT_BIT;
2779                 if (cpu_has_vmx_ept_execute_only())
2780                         vmx->nested.nested_vmx_ept_caps |=
2781                                 VMX_EPT_EXECUTE_ONLY_BIT;
2782                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2783                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2784                         VMX_EPT_EXTENT_CONTEXT_BIT;
2785         } else
2786                 vmx->nested.nested_vmx_ept_caps = 0;
2787
2788         /*
2789          * Old versions of KVM use the single-context version without
2790          * checking for support, so declare that it is supported even
2791          * though it is treated as global context.  The alternative is
2792          * not failing the single-context invvpid, and it is worse.
2793          */
2794         if (enable_vpid)
2795                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2796                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2797         else
2798                 vmx->nested.nested_vmx_vpid_caps = 0;
2799
2800         if (enable_unrestricted_guest)
2801                 vmx->nested.nested_vmx_secondary_ctls_high |=
2802                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2803
2804         /* miscellaneous data */
2805         rdmsr(MSR_IA32_VMX_MISC,
2806                 vmx->nested.nested_vmx_misc_low,
2807                 vmx->nested.nested_vmx_misc_high);
2808         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2809         vmx->nested.nested_vmx_misc_low |=
2810                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2811                 VMX_MISC_ACTIVITY_HLT;
2812         vmx->nested.nested_vmx_misc_high = 0;
2813
2814         /*
2815          * This MSR reports some information about VMX support. We
2816          * should return information about the VMX we emulate for the
2817          * guest, and the VMCS structure we give it - not about the
2818          * VMX support of the underlying hardware.
2819          */
2820         vmx->nested.nested_vmx_basic =
2821                 VMCS12_REVISION |
2822                 VMX_BASIC_TRUE_CTLS |
2823                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2824                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2825
2826         if (cpu_has_vmx_basic_inout())
2827                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2828
2829         /*
2830          * These MSRs specify bits which the guest must keep fixed on
2831          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2832          * We picked the standard core2 setting.
2833          */
2834 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2835 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2836         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2837         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2838
2839         /* These MSRs specify bits which the guest must keep fixed off. */
2840         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2841         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2842
2843         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2844         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2845 }
2846
2847 /*
2848  * if fixed0[i] == 1: val[i] must be 1
2849  * if fixed1[i] == 0: val[i] must be 0
2850  */
2851 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2852 {
2853         return ((val & fixed1) | fixed0) == val;
2854 }
2855
2856 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2857 {
2858         return fixed_bits_valid(control, low, high);
2859 }
2860
2861 static inline u64 vmx_control_msr(u32 low, u32 high)
2862 {
2863         return low | ((u64)high << 32);
2864 }
2865
2866 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2867 {
2868         superset &= mask;
2869         subset &= mask;
2870
2871         return (superset | subset) == superset;
2872 }
2873
2874 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2875 {
2876         const u64 feature_and_reserved =
2877                 /* feature (except bit 48; see below) */
2878                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2879                 /* reserved */
2880                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2881         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2882
2883         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2884                 return -EINVAL;
2885
2886         /*
2887          * KVM does not emulate a version of VMX that constrains physical
2888          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2889          */
2890         if (data & BIT_ULL(48))
2891                 return -EINVAL;
2892
2893         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2894             vmx_basic_vmcs_revision_id(data))
2895                 return -EINVAL;
2896
2897         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2898                 return -EINVAL;
2899
2900         vmx->nested.nested_vmx_basic = data;
2901         return 0;
2902 }
2903
2904 static int
2905 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2906 {
2907         u64 supported;
2908         u32 *lowp, *highp;
2909
2910         switch (msr_index) {
2911         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2912                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2913                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2914                 break;
2915         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2916                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2917                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2918                 break;
2919         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2920                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2921                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2922                 break;
2923         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2924                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2925                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2926                 break;
2927         case MSR_IA32_VMX_PROCBASED_CTLS2:
2928                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2929                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2930                 break;
2931         default:
2932                 BUG();
2933         }
2934
2935         supported = vmx_control_msr(*lowp, *highp);
2936
2937         /* Check must-be-1 bits are still 1. */
2938         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2939                 return -EINVAL;
2940
2941         /* Check must-be-0 bits are still 0. */
2942         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2943                 return -EINVAL;
2944
2945         *lowp = data;
2946         *highp = data >> 32;
2947         return 0;
2948 }
2949
2950 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2951 {
2952         const u64 feature_and_reserved_bits =
2953                 /* feature */
2954                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2955                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2956                 /* reserved */
2957                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2958         u64 vmx_misc;
2959
2960         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2961                                    vmx->nested.nested_vmx_misc_high);
2962
2963         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2964                 return -EINVAL;
2965
2966         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2967              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2968             vmx_misc_preemption_timer_rate(data) !=
2969             vmx_misc_preemption_timer_rate(vmx_misc))
2970                 return -EINVAL;
2971
2972         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2973                 return -EINVAL;
2974
2975         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2976                 return -EINVAL;
2977
2978         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2979                 return -EINVAL;
2980
2981         vmx->nested.nested_vmx_misc_low = data;
2982         vmx->nested.nested_vmx_misc_high = data >> 32;
2983         return 0;
2984 }
2985
2986 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2987 {
2988         u64 vmx_ept_vpid_cap;
2989
2990         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2991                                            vmx->nested.nested_vmx_vpid_caps);
2992
2993         /* Every bit is either reserved or a feature bit. */
2994         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2995                 return -EINVAL;
2996
2997         vmx->nested.nested_vmx_ept_caps = data;
2998         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2999         return 0;
3000 }
3001
3002 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3003 {
3004         u64 *msr;
3005
3006         switch (msr_index) {
3007         case MSR_IA32_VMX_CR0_FIXED0:
3008                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3009                 break;
3010         case MSR_IA32_VMX_CR4_FIXED0:
3011                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3012                 break;
3013         default:
3014                 BUG();
3015         }
3016
3017         /*
3018          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3019          * must be 1 in the restored value.
3020          */
3021         if (!is_bitwise_subset(data, *msr, -1ULL))
3022                 return -EINVAL;
3023
3024         *msr = data;
3025         return 0;
3026 }
3027
3028 /*
3029  * Called when userspace is restoring VMX MSRs.
3030  *
3031  * Returns 0 on success, non-0 otherwise.
3032  */
3033 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3034 {
3035         struct vcpu_vmx *vmx = to_vmx(vcpu);
3036
3037         switch (msr_index) {
3038         case MSR_IA32_VMX_BASIC:
3039                 return vmx_restore_vmx_basic(vmx, data);
3040         case MSR_IA32_VMX_PINBASED_CTLS:
3041         case MSR_IA32_VMX_PROCBASED_CTLS:
3042         case MSR_IA32_VMX_EXIT_CTLS:
3043         case MSR_IA32_VMX_ENTRY_CTLS:
3044                 /*
3045                  * The "non-true" VMX capability MSRs are generated from the
3046                  * "true" MSRs, so we do not support restoring them directly.
3047                  *
3048                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3049                  * should restore the "true" MSRs with the must-be-1 bits
3050                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3051                  * DEFAULT SETTINGS".
3052                  */
3053                 return -EINVAL;
3054         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3055         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3056         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3057         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3058         case MSR_IA32_VMX_PROCBASED_CTLS2:
3059                 return vmx_restore_control_msr(vmx, msr_index, data);
3060         case MSR_IA32_VMX_MISC:
3061                 return vmx_restore_vmx_misc(vmx, data);
3062         case MSR_IA32_VMX_CR0_FIXED0:
3063         case MSR_IA32_VMX_CR4_FIXED0:
3064                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3065         case MSR_IA32_VMX_CR0_FIXED1:
3066         case MSR_IA32_VMX_CR4_FIXED1:
3067                 /*
3068                  * These MSRs are generated based on the vCPU's CPUID, so we
3069                  * do not support restoring them directly.
3070                  */
3071                 return -EINVAL;
3072         case MSR_IA32_VMX_EPT_VPID_CAP:
3073                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3074         case MSR_IA32_VMX_VMCS_ENUM:
3075                 vmx->nested.nested_vmx_vmcs_enum = data;
3076                 return 0;
3077         default:
3078                 /*
3079                  * The rest of the VMX capability MSRs do not support restore.
3080                  */
3081                 return -EINVAL;
3082         }
3083 }
3084
3085 /* Returns 0 on success, non-0 otherwise. */
3086 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3087 {
3088         struct vcpu_vmx *vmx = to_vmx(vcpu);
3089
3090         switch (msr_index) {
3091         case MSR_IA32_VMX_BASIC:
3092                 *pdata = vmx->nested.nested_vmx_basic;
3093                 break;
3094         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3095         case MSR_IA32_VMX_PINBASED_CTLS:
3096                 *pdata = vmx_control_msr(
3097                         vmx->nested.nested_vmx_pinbased_ctls_low,
3098                         vmx->nested.nested_vmx_pinbased_ctls_high);
3099                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3100                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3101                 break;
3102         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3103         case MSR_IA32_VMX_PROCBASED_CTLS:
3104                 *pdata = vmx_control_msr(
3105                         vmx->nested.nested_vmx_procbased_ctls_low,
3106                         vmx->nested.nested_vmx_procbased_ctls_high);
3107                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3108                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3109                 break;
3110         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3111         case MSR_IA32_VMX_EXIT_CTLS:
3112                 *pdata = vmx_control_msr(
3113                         vmx->nested.nested_vmx_exit_ctls_low,
3114                         vmx->nested.nested_vmx_exit_ctls_high);
3115                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3116                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3117                 break;
3118         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3119         case MSR_IA32_VMX_ENTRY_CTLS:
3120                 *pdata = vmx_control_msr(
3121                         vmx->nested.nested_vmx_entry_ctls_low,
3122                         vmx->nested.nested_vmx_entry_ctls_high);
3123                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3124                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3125                 break;
3126         case MSR_IA32_VMX_MISC:
3127                 *pdata = vmx_control_msr(
3128                         vmx->nested.nested_vmx_misc_low,
3129                         vmx->nested.nested_vmx_misc_high);
3130                 break;
3131         case MSR_IA32_VMX_CR0_FIXED0:
3132                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3133                 break;
3134         case MSR_IA32_VMX_CR0_FIXED1:
3135                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3136                 break;
3137         case MSR_IA32_VMX_CR4_FIXED0:
3138                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3139                 break;
3140         case MSR_IA32_VMX_CR4_FIXED1:
3141                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3142                 break;
3143         case MSR_IA32_VMX_VMCS_ENUM:
3144                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3145                 break;
3146         case MSR_IA32_VMX_PROCBASED_CTLS2:
3147                 *pdata = vmx_control_msr(
3148                         vmx->nested.nested_vmx_secondary_ctls_low,
3149                         vmx->nested.nested_vmx_secondary_ctls_high);
3150                 break;
3151         case MSR_IA32_VMX_EPT_VPID_CAP:
3152                 *pdata = vmx->nested.nested_vmx_ept_caps |
3153                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3154                 break;
3155         default:
3156                 return 1;
3157         }
3158
3159         return 0;
3160 }
3161
3162 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3163                                                  uint64_t val)
3164 {
3165         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3166
3167         return !(val & ~valid_bits);
3168 }
3169
3170 /*
3171  * Reads an msr value (of 'msr_index') into 'pdata'.
3172  * Returns 0 on success, non-0 otherwise.
3173  * Assumes vcpu_load() was already called.
3174  */
3175 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3176 {
3177         struct shared_msr_entry *msr;
3178
3179         switch (msr_info->index) {
3180 #ifdef CONFIG_X86_64
3181         case MSR_FS_BASE:
3182                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3183                 break;
3184         case MSR_GS_BASE:
3185                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3186                 break;
3187         case MSR_KERNEL_GS_BASE:
3188                 vmx_load_host_state(to_vmx(vcpu));
3189                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3190                 break;
3191 #endif
3192         case MSR_EFER:
3193                 return kvm_get_msr_common(vcpu, msr_info);
3194         case MSR_IA32_TSC:
3195                 msr_info->data = guest_read_tsc(vcpu);
3196                 break;
3197         case MSR_IA32_SYSENTER_CS:
3198                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3199                 break;
3200         case MSR_IA32_SYSENTER_EIP:
3201                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3202                 break;
3203         case MSR_IA32_SYSENTER_ESP:
3204                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3205                 break;
3206         case MSR_IA32_BNDCFGS:
3207                 if (!kvm_mpx_supported())
3208                         return 1;
3209                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3210                 break;
3211         case MSR_IA32_MCG_EXT_CTL:
3212                 if (!msr_info->host_initiated &&
3213                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3214                       FEATURE_CONTROL_LMCE))
3215                         return 1;
3216                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3217                 break;
3218         case MSR_IA32_FEATURE_CONTROL:
3219                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3220                 break;
3221         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3222                 if (!nested_vmx_allowed(vcpu))
3223                         return 1;
3224                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3225         case MSR_IA32_XSS:
3226                 if (!vmx_xsaves_supported())
3227                         return 1;
3228                 msr_info->data = vcpu->arch.ia32_xss;
3229                 break;
3230         case MSR_TSC_AUX:
3231                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3232                         return 1;
3233                 /* Otherwise falls through */
3234         default:
3235                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3236                 if (msr) {
3237                         msr_info->data = msr->data;
3238                         break;
3239                 }
3240                 return kvm_get_msr_common(vcpu, msr_info);
3241         }
3242
3243         return 0;
3244 }
3245
3246 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3247
3248 /*
3249  * Writes msr value into into the appropriate "register".
3250  * Returns 0 on success, non-0 otherwise.
3251  * Assumes vcpu_load() was already called.
3252  */
3253 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3254 {
3255         struct vcpu_vmx *vmx = to_vmx(vcpu);
3256         struct shared_msr_entry *msr;
3257         int ret = 0;
3258         u32 msr_index = msr_info->index;
3259         u64 data = msr_info->data;
3260
3261         switch (msr_index) {
3262         case MSR_EFER:
3263                 ret = kvm_set_msr_common(vcpu, msr_info);
3264                 break;
3265 #ifdef CONFIG_X86_64
3266         case MSR_FS_BASE:
3267                 vmx_segment_cache_clear(vmx);
3268                 vmcs_writel(GUEST_FS_BASE, data);
3269                 break;
3270         case MSR_GS_BASE:
3271                 vmx_segment_cache_clear(vmx);
3272                 vmcs_writel(GUEST_GS_BASE, data);
3273                 break;
3274         case MSR_KERNEL_GS_BASE:
3275                 vmx_load_host_state(vmx);
3276                 vmx->msr_guest_kernel_gs_base = data;
3277                 break;
3278 #endif
3279         case MSR_IA32_SYSENTER_CS:
3280                 vmcs_write32(GUEST_SYSENTER_CS, data);
3281                 break;
3282         case MSR_IA32_SYSENTER_EIP:
3283                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3284                 break;
3285         case MSR_IA32_SYSENTER_ESP:
3286                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3287                 break;
3288         case MSR_IA32_BNDCFGS:
3289                 if (!kvm_mpx_supported())
3290                         return 1;
3291                 vmcs_write64(GUEST_BNDCFGS, data);
3292                 break;
3293         case MSR_IA32_TSC:
3294                 kvm_write_tsc(vcpu, msr_info);
3295                 break;
3296         case MSR_IA32_CR_PAT:
3297                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3298                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3299                                 return 1;
3300                         vmcs_write64(GUEST_IA32_PAT, data);
3301                         vcpu->arch.pat = data;
3302                         break;
3303                 }
3304                 ret = kvm_set_msr_common(vcpu, msr_info);
3305                 break;
3306         case MSR_IA32_TSC_ADJUST:
3307                 ret = kvm_set_msr_common(vcpu, msr_info);
3308                 break;
3309         case MSR_IA32_MCG_EXT_CTL:
3310                 if ((!msr_info->host_initiated &&
3311                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3312                        FEATURE_CONTROL_LMCE)) ||
3313                     (data & ~MCG_EXT_CTL_LMCE_EN))
3314                         return 1;
3315                 vcpu->arch.mcg_ext_ctl = data;
3316                 break;
3317         case MSR_IA32_FEATURE_CONTROL:
3318                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3319                     (to_vmx(vcpu)->msr_ia32_feature_control &
3320                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3321                         return 1;
3322                 vmx->msr_ia32_feature_control = data;
3323                 if (msr_info->host_initiated && data == 0)
3324                         vmx_leave_nested(vcpu);
3325                 break;
3326         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3327                 if (!msr_info->host_initiated)
3328                         return 1; /* they are read-only */
3329                 if (!nested_vmx_allowed(vcpu))
3330                         return 1;
3331                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3332         case MSR_IA32_XSS:
3333                 if (!vmx_xsaves_supported())
3334                         return 1;
3335                 /*
3336                  * The only supported bit as of Skylake is bit 8, but
3337                  * it is not supported on KVM.
3338                  */
3339                 if (data != 0)
3340                         return 1;
3341                 vcpu->arch.ia32_xss = data;
3342                 if (vcpu->arch.ia32_xss != host_xss)
3343                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3344                                 vcpu->arch.ia32_xss, host_xss);
3345                 else
3346                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3347                 break;
3348         case MSR_TSC_AUX:
3349                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3350                         return 1;
3351                 /* Check reserved bit, higher 32 bits should be zero */
3352                 if ((data >> 32) != 0)
3353                         return 1;
3354                 /* Otherwise falls through */
3355         default:
3356                 msr = find_msr_entry(vmx, msr_index);
3357                 if (msr) {
3358                         u64 old_msr_data = msr->data;
3359                         msr->data = data;
3360                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3361                                 preempt_disable();
3362                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3363                                                          msr->mask);
3364                                 preempt_enable();
3365                                 if (ret)
3366                                         msr->data = old_msr_data;
3367                         }
3368                         break;
3369                 }
3370                 ret = kvm_set_msr_common(vcpu, msr_info);
3371         }
3372
3373         return ret;
3374 }
3375
3376 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3377 {
3378         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3379         switch (reg) {
3380         case VCPU_REGS_RSP:
3381                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3382                 break;
3383         case VCPU_REGS_RIP:
3384                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3385                 break;
3386         case VCPU_EXREG_PDPTR:
3387                 if (enable_ept)
3388                         ept_save_pdptrs(vcpu);
3389                 break;
3390         default:
3391                 break;
3392         }
3393 }
3394
3395 static __init int cpu_has_kvm_support(void)
3396 {
3397         return cpu_has_vmx();
3398 }
3399
3400 static __init int vmx_disabled_by_bios(void)
3401 {
3402         u64 msr;
3403
3404         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3405         if (msr & FEATURE_CONTROL_LOCKED) {
3406                 /* launched w/ TXT and VMX disabled */
3407                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3408                         && tboot_enabled())
3409                         return 1;
3410                 /* launched w/o TXT and VMX only enabled w/ TXT */
3411                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3412                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3413                         && !tboot_enabled()) {
3414                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3415                                 "activate TXT before enabling KVM\n");
3416                         return 1;
3417                 }
3418                 /* launched w/o TXT and VMX disabled */
3419                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3420                         && !tboot_enabled())
3421                         return 1;
3422         }
3423
3424         return 0;
3425 }
3426
3427 static void kvm_cpu_vmxon(u64 addr)
3428 {
3429         intel_pt_handle_vmx(1);
3430
3431         asm volatile (ASM_VMX_VMXON_RAX
3432                         : : "a"(&addr), "m"(addr)
3433                         : "memory", "cc");
3434 }
3435
3436 static int hardware_enable(void)
3437 {
3438         int cpu = raw_smp_processor_id();
3439         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3440         u64 old, test_bits;
3441
3442         if (cr4_read_shadow() & X86_CR4_VMXE)
3443                 return -EBUSY;
3444
3445         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3446         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3447         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3448
3449         /*
3450          * Now we can enable the vmclear operation in kdump
3451          * since the loaded_vmcss_on_cpu list on this cpu
3452          * has been initialized.
3453          *
3454          * Though the cpu is not in VMX operation now, there
3455          * is no problem to enable the vmclear operation
3456          * for the loaded_vmcss_on_cpu list is empty!
3457          */
3458         crash_enable_local_vmclear(cpu);
3459
3460         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3461
3462         test_bits = FEATURE_CONTROL_LOCKED;
3463         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3464         if (tboot_enabled())
3465                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3466
3467         if ((old & test_bits) != test_bits) {
3468                 /* enable and lock */
3469                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3470         }
3471         cr4_set_bits(X86_CR4_VMXE);
3472
3473         if (vmm_exclusive) {
3474                 kvm_cpu_vmxon(phys_addr);
3475                 ept_sync_global();
3476         }
3477
3478         native_store_gdt(this_cpu_ptr(&host_gdt));
3479
3480         return 0;
3481 }
3482
3483 static void vmclear_local_loaded_vmcss(void)
3484 {
3485         int cpu = raw_smp_processor_id();
3486         struct loaded_vmcs *v, *n;
3487
3488         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3489                                  loaded_vmcss_on_cpu_link)
3490                 __loaded_vmcs_clear(v);
3491 }
3492
3493
3494 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3495  * tricks.
3496  */
3497 static void kvm_cpu_vmxoff(void)
3498 {
3499         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3500
3501         intel_pt_handle_vmx(0);
3502 }
3503
3504 static void hardware_disable(void)
3505 {
3506         if (vmm_exclusive) {
3507                 vmclear_local_loaded_vmcss();
3508                 kvm_cpu_vmxoff();
3509         }
3510         cr4_clear_bits(X86_CR4_VMXE);
3511 }
3512
3513 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3514                                       u32 msr, u32 *result)
3515 {
3516         u32 vmx_msr_low, vmx_msr_high;
3517         u32 ctl = ctl_min | ctl_opt;
3518
3519         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3520
3521         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3522         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3523
3524         /* Ensure minimum (required) set of control bits are supported. */
3525         if (ctl_min & ~ctl)
3526                 return -EIO;
3527
3528         *result = ctl;
3529         return 0;
3530 }
3531
3532 static __init bool allow_1_setting(u32 msr, u32 ctl)
3533 {
3534         u32 vmx_msr_low, vmx_msr_high;
3535
3536         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3537         return vmx_msr_high & ctl;
3538 }
3539
3540 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3541 {
3542         u32 vmx_msr_low, vmx_msr_high;
3543         u32 min, opt, min2, opt2;
3544         u32 _pin_based_exec_control = 0;
3545         u32 _cpu_based_exec_control = 0;
3546         u32 _cpu_based_2nd_exec_control = 0;
3547         u32 _vmexit_control = 0;
3548         u32 _vmentry_control = 0;
3549
3550         min = CPU_BASED_HLT_EXITING |
3551 #ifdef CONFIG_X86_64
3552               CPU_BASED_CR8_LOAD_EXITING |
3553               CPU_BASED_CR8_STORE_EXITING |
3554 #endif
3555               CPU_BASED_CR3_LOAD_EXITING |
3556               CPU_BASED_CR3_STORE_EXITING |
3557               CPU_BASED_USE_IO_BITMAPS |
3558               CPU_BASED_MOV_DR_EXITING |
3559               CPU_BASED_USE_TSC_OFFSETING |
3560               CPU_BASED_MWAIT_EXITING |
3561               CPU_BASED_MONITOR_EXITING |
3562               CPU_BASED_INVLPG_EXITING |
3563               CPU_BASED_RDPMC_EXITING;
3564
3565         opt = CPU_BASED_TPR_SHADOW |
3566               CPU_BASED_USE_MSR_BITMAPS |
3567               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3568         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3569                                 &_cpu_based_exec_control) < 0)
3570                 return -EIO;
3571 #ifdef CONFIG_X86_64
3572         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3573                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3574                                            ~CPU_BASED_CR8_STORE_EXITING;
3575 #endif
3576         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3577                 min2 = 0;
3578                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3579                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3580                         SECONDARY_EXEC_WBINVD_EXITING |
3581                         SECONDARY_EXEC_ENABLE_VPID |
3582                         SECONDARY_EXEC_ENABLE_EPT |
3583                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3584                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3585                         SECONDARY_EXEC_RDTSCP |
3586                         SECONDARY_EXEC_ENABLE_INVPCID |
3587                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3588                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3589                         SECONDARY_EXEC_SHADOW_VMCS |
3590                         SECONDARY_EXEC_XSAVES |
3591                         SECONDARY_EXEC_ENABLE_PML |
3592                         SECONDARY_EXEC_TSC_SCALING;
3593                 if (adjust_vmx_controls(min2, opt2,
3594                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3595                                         &_cpu_based_2nd_exec_control) < 0)
3596                         return -EIO;
3597         }
3598 #ifndef CONFIG_X86_64
3599         if (!(_cpu_based_2nd_exec_control &
3600                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3601                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3602 #endif
3603
3604         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3605                 _cpu_based_2nd_exec_control &= ~(
3606                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3607                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3608                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3609
3610         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3611                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3612                    enabled */
3613                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3614                                              CPU_BASED_CR3_STORE_EXITING |
3615                                              CPU_BASED_INVLPG_EXITING);
3616                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3617                       vmx_capability.ept, vmx_capability.vpid);
3618         }
3619
3620         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3621 #ifdef CONFIG_X86_64
3622         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3623 #endif
3624         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3625                 VM_EXIT_CLEAR_BNDCFGS;
3626         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3627                                 &_vmexit_control) < 0)
3628                 return -EIO;
3629
3630         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3631         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3632                  PIN_BASED_VMX_PREEMPTION_TIMER;
3633         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3634                                 &_pin_based_exec_control) < 0)
3635                 return -EIO;
3636
3637         if (cpu_has_broken_vmx_preemption_timer())
3638                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3639         if (!(_cpu_based_2nd_exec_control &
3640                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3641                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3642
3643         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3644         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3645         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3646                                 &_vmentry_control) < 0)
3647                 return -EIO;
3648
3649         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3650
3651         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3652         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3653                 return -EIO;
3654
3655 #ifdef CONFIG_X86_64
3656         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3657         if (vmx_msr_high & (1u<<16))
3658                 return -EIO;
3659 #endif
3660
3661         /* Require Write-Back (WB) memory type for VMCS accesses. */
3662         if (((vmx_msr_high >> 18) & 15) != 6)
3663                 return -EIO;
3664
3665         vmcs_conf->size = vmx_msr_high & 0x1fff;
3666         vmcs_conf->order = get_order(vmcs_conf->size);
3667         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3668         vmcs_conf->revision_id = vmx_msr_low;
3669
3670         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3671         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3672         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3673         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3674         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3675
3676         cpu_has_load_ia32_efer =
3677                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3678                                 VM_ENTRY_LOAD_IA32_EFER)
3679                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3680                                    VM_EXIT_LOAD_IA32_EFER);
3681
3682         cpu_has_load_perf_global_ctrl =
3683                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3684                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3685                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3686                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3687
3688         /*
3689          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3690          * but due to errata below it can't be used. Workaround is to use
3691          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3692          *
3693          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3694          *
3695          * AAK155             (model 26)
3696          * AAP115             (model 30)
3697          * AAT100             (model 37)
3698          * BC86,AAY89,BD102   (model 44)
3699          * BA97               (model 46)
3700          *
3701          */
3702         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3703                 switch (boot_cpu_data.x86_model) {
3704                 case 26:
3705                 case 30:
3706                 case 37:
3707                 case 44:
3708                 case 46:
3709                         cpu_has_load_perf_global_ctrl = false;
3710                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3711                                         "does not work properly. Using workaround\n");
3712                         break;
3713                 default:
3714                         break;
3715                 }
3716         }
3717
3718         if (boot_cpu_has(X86_FEATURE_XSAVES))
3719                 rdmsrl(MSR_IA32_XSS, host_xss);
3720
3721         return 0;
3722 }
3723
3724 static struct vmcs *alloc_vmcs_cpu(int cpu)
3725 {
3726         int node = cpu_to_node(cpu);
3727         struct page *pages;
3728         struct vmcs *vmcs;
3729
3730         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3731         if (!pages)
3732                 return NULL;
3733         vmcs = page_address(pages);
3734         memset(vmcs, 0, vmcs_config.size);
3735         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3736         return vmcs;
3737 }
3738
3739 static struct vmcs *alloc_vmcs(void)
3740 {
3741         return alloc_vmcs_cpu(raw_smp_processor_id());
3742 }
3743
3744 static void free_vmcs(struct vmcs *vmcs)
3745 {
3746         free_pages((unsigned long)vmcs, vmcs_config.order);
3747 }
3748
3749 /*
3750  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3751  */
3752 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3753 {
3754         if (!loaded_vmcs->vmcs)
3755                 return;
3756         loaded_vmcs_clear(loaded_vmcs);
3757         free_vmcs(loaded_vmcs->vmcs);
3758         loaded_vmcs->vmcs = NULL;
3759         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3760 }
3761
3762 static void free_kvm_area(void)
3763 {
3764         int cpu;
3765
3766         for_each_possible_cpu(cpu) {
3767                 free_vmcs(per_cpu(vmxarea, cpu));
3768                 per_cpu(vmxarea, cpu) = NULL;
3769         }
3770 }
3771
3772 static void init_vmcs_shadow_fields(void)
3773 {
3774         int i, j;
3775
3776         /* No checks for read only fields yet */
3777
3778         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3779                 switch (shadow_read_write_fields[i]) {
3780                 case GUEST_BNDCFGS:
3781                         if (!kvm_mpx_supported())
3782                                 continue;
3783                         break;
3784                 default:
3785                         break;
3786                 }
3787
3788                 if (j < i)
3789                         shadow_read_write_fields[j] =
3790                                 shadow_read_write_fields[i];
3791                 j++;
3792         }
3793         max_shadow_read_write_fields = j;
3794
3795         /* shadowed fields guest access without vmexit */
3796         for (i = 0; i < max_shadow_read_write_fields; i++) {
3797                 clear_bit(shadow_read_write_fields[i],
3798                           vmx_vmwrite_bitmap);
3799                 clear_bit(shadow_read_write_fields[i],
3800                           vmx_vmread_bitmap);
3801         }
3802         for (i = 0; i < max_shadow_read_only_fields; i++)
3803                 clear_bit(shadow_read_only_fields[i],
3804                           vmx_vmread_bitmap);
3805 }
3806
3807 static __init int alloc_kvm_area(void)
3808 {
3809         int cpu;
3810
3811         for_each_possible_cpu(cpu) {
3812                 struct vmcs *vmcs;
3813
3814                 vmcs = alloc_vmcs_cpu(cpu);
3815                 if (!vmcs) {
3816                         free_kvm_area();
3817                         return -ENOMEM;
3818                 }
3819
3820                 per_cpu(vmxarea, cpu) = vmcs;
3821         }
3822         return 0;
3823 }
3824
3825 static bool emulation_required(struct kvm_vcpu *vcpu)
3826 {
3827         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3828 }
3829
3830 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3831                 struct kvm_segment *save)
3832 {
3833         if (!emulate_invalid_guest_state) {
3834                 /*
3835                  * CS and SS RPL should be equal during guest entry according
3836                  * to VMX spec, but in reality it is not always so. Since vcpu
3837                  * is in the middle of the transition from real mode to
3838                  * protected mode it is safe to assume that RPL 0 is a good
3839                  * default value.
3840                  */
3841                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3842                         save->selector &= ~SEGMENT_RPL_MASK;
3843                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3844                 save->s = 1;
3845         }
3846         vmx_set_segment(vcpu, save, seg);
3847 }
3848
3849 static void enter_pmode(struct kvm_vcpu *vcpu)
3850 {
3851         unsigned long flags;
3852         struct vcpu_vmx *vmx = to_vmx(vcpu);
3853
3854         /*
3855          * Update real mode segment cache. It may be not up-to-date if sement
3856          * register was written while vcpu was in a guest mode.
3857          */
3858         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3859         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3860         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3861         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3862         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3863         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3864
3865         vmx->rmode.vm86_active = 0;
3866
3867         vmx_segment_cache_clear(vmx);
3868
3869         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3870
3871         flags = vmcs_readl(GUEST_RFLAGS);
3872         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3873         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3874         vmcs_writel(GUEST_RFLAGS, flags);
3875
3876         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3877                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3878
3879         update_exception_bitmap(vcpu);
3880
3881         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3882         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3883         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3884         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3885         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3886         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3887 }
3888
3889 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3890 {
3891         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3892         struct kvm_segment var = *save;
3893
3894         var.dpl = 0x3;
3895         if (seg == VCPU_SREG_CS)
3896                 var.type = 0x3;
3897
3898         if (!emulate_invalid_guest_state) {
3899                 var.selector = var.base >> 4;
3900                 var.base = var.base & 0xffff0;
3901                 var.limit = 0xffff;
3902                 var.g = 0;
3903                 var.db = 0;
3904                 var.present = 1;
3905                 var.s = 1;
3906                 var.l = 0;
3907                 var.unusable = 0;
3908                 var.type = 0x3;
3909                 var.avl = 0;
3910                 if (save->base & 0xf)
3911                         printk_once(KERN_WARNING "kvm: segment base is not "
3912                                         "paragraph aligned when entering "
3913                                         "protected mode (seg=%d)", seg);
3914         }
3915
3916         vmcs_write16(sf->selector, var.selector);
3917         vmcs_write32(sf->base, var.base);
3918         vmcs_write32(sf->limit, var.limit);
3919         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3920 }
3921
3922 static void enter_rmode(struct kvm_vcpu *vcpu)
3923 {
3924         unsigned long flags;
3925         struct vcpu_vmx *vmx = to_vmx(vcpu);
3926
3927         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3928         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3929         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3930         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3931         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3932         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3933         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3934
3935         vmx->rmode.vm86_active = 1;
3936
3937         /*
3938          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3939          * vcpu. Warn the user that an update is overdue.
3940          */
3941         if (!vcpu->kvm->arch.tss_addr)
3942                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3943                              "called before entering vcpu\n");
3944
3945         vmx_segment_cache_clear(vmx);
3946
3947         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3948         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3949         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3950
3951         flags = vmcs_readl(GUEST_RFLAGS);
3952         vmx->rmode.save_rflags = flags;
3953
3954         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3955
3956         vmcs_writel(GUEST_RFLAGS, flags);
3957         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3958         update_exception_bitmap(vcpu);
3959
3960         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3961         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3962         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3963         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3964         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3965         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3966
3967         kvm_mmu_reset_context(vcpu);
3968 }
3969
3970 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3971 {
3972         struct vcpu_vmx *vmx = to_vmx(vcpu);
3973         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3974
3975         if (!msr)
3976                 return;
3977
3978         /*
3979          * Force kernel_gs_base reloading before EFER changes, as control
3980          * of this msr depends on is_long_mode().
3981          */
3982         vmx_load_host_state(to_vmx(vcpu));
3983         vcpu->arch.efer = efer;
3984         if (efer & EFER_LMA) {
3985                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3986                 msr->data = efer;
3987         } else {
3988                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3989
3990                 msr->data = efer & ~EFER_LME;
3991         }
3992         setup_msrs(vmx);
3993 }
3994
3995 #ifdef CONFIG_X86_64
3996
3997 static void enter_lmode(struct kvm_vcpu *vcpu)
3998 {
3999         u32 guest_tr_ar;
4000
4001         vmx_segment_cache_clear(to_vmx(vcpu));
4002
4003         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4004         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4005                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4006                                      __func__);
4007                 vmcs_write32(GUEST_TR_AR_BYTES,
4008                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4009                              | VMX_AR_TYPE_BUSY_64_TSS);
4010         }
4011         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4012 }
4013
4014 static void exit_lmode(struct kvm_vcpu *vcpu)
4015 {
4016         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4017         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4018 }
4019
4020 #endif
4021
4022 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4023 {
4024         vpid_sync_context(vpid);
4025         if (enable_ept) {
4026                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4027                         return;
4028                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4029         }
4030 }
4031
4032 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4033 {
4034         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4035 }
4036
4037 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4038 {
4039         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4040
4041         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4042         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4043 }
4044
4045 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4046 {
4047         if (enable_ept && is_paging(vcpu))
4048                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4049         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4050 }
4051
4052 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4053 {
4054         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4055
4056         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4057         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4058 }
4059
4060 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4061 {
4062         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4063
4064         if (!test_bit(VCPU_EXREG_PDPTR,
4065                       (unsigned long *)&vcpu->arch.regs_dirty))
4066                 return;
4067
4068         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4069                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4070                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4071                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4072                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4073         }
4074 }
4075
4076 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4077 {
4078         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4079
4080         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4081                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4082                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4083                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4084                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4085         }
4086
4087         __set_bit(VCPU_EXREG_PDPTR,
4088                   (unsigned long *)&vcpu->arch.regs_avail);
4089         __set_bit(VCPU_EXREG_PDPTR,
4090                   (unsigned long *)&vcpu->arch.regs_dirty);
4091 }
4092
4093 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4094 {
4095         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4096         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4097         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4098
4099         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4100                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4101             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4102                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4103
4104         return fixed_bits_valid(val, fixed0, fixed1);
4105 }
4106
4107 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4108 {
4109         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4110         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4111
4112         return fixed_bits_valid(val, fixed0, fixed1);
4113 }
4114
4115 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4116 {
4117         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4118         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4119
4120         return fixed_bits_valid(val, fixed0, fixed1);
4121 }
4122
4123 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4124 #define nested_guest_cr4_valid  nested_cr4_valid
4125 #define nested_host_cr4_valid   nested_cr4_valid
4126
4127 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4128
4129 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4130                                         unsigned long cr0,
4131                                         struct kvm_vcpu *vcpu)
4132 {
4133         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4134                 vmx_decache_cr3(vcpu);
4135         if (!(cr0 & X86_CR0_PG)) {
4136                 /* From paging/starting to nonpaging */
4137                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4138                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4139                              (CPU_BASED_CR3_LOAD_EXITING |
4140                               CPU_BASED_CR3_STORE_EXITING));
4141                 vcpu->arch.cr0 = cr0;
4142                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4143         } else if (!is_paging(vcpu)) {
4144                 /* From nonpaging to paging */
4145                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4146                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4147                              ~(CPU_BASED_CR3_LOAD_EXITING |
4148                                CPU_BASED_CR3_STORE_EXITING));
4149                 vcpu->arch.cr0 = cr0;
4150                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4151         }
4152
4153         if (!(cr0 & X86_CR0_WP))
4154                 *hw_cr0 &= ~X86_CR0_WP;
4155 }
4156
4157 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4158 {
4159         struct vcpu_vmx *vmx = to_vmx(vcpu);
4160         unsigned long hw_cr0;
4161
4162         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4163         if (enable_unrestricted_guest)
4164                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4165         else {
4166                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4167
4168                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4169                         enter_pmode(vcpu);
4170
4171                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4172                         enter_rmode(vcpu);
4173         }
4174
4175 #ifdef CONFIG_X86_64
4176         if (vcpu->arch.efer & EFER_LME) {
4177                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4178                         enter_lmode(vcpu);
4179                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4180                         exit_lmode(vcpu);
4181         }
4182 #endif
4183
4184         if (enable_ept)
4185                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4186
4187         vmcs_writel(CR0_READ_SHADOW, cr0);
4188         vmcs_writel(GUEST_CR0, hw_cr0);
4189         vcpu->arch.cr0 = cr0;
4190
4191         /* depends on vcpu->arch.cr0 to be set to a new value */
4192         vmx->emulation_required = emulation_required(vcpu);
4193 }
4194
4195 static u64 construct_eptp(unsigned long root_hpa)
4196 {
4197         u64 eptp;
4198
4199         /* TODO write the value reading from MSR */
4200         eptp = VMX_EPT_DEFAULT_MT |
4201                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4202         if (enable_ept_ad_bits)
4203                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4204         eptp |= (root_hpa & PAGE_MASK);
4205
4206         return eptp;
4207 }
4208
4209 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4210 {
4211         unsigned long guest_cr3;
4212         u64 eptp;
4213
4214         guest_cr3 = cr3;
4215         if (enable_ept) {
4216                 eptp = construct_eptp(cr3);
4217                 vmcs_write64(EPT_POINTER, eptp);
4218                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4219                         guest_cr3 = kvm_read_cr3(vcpu);
4220                 else
4221                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4222                 ept_load_pdptrs(vcpu);
4223         }
4224
4225         vmx_flush_tlb(vcpu);
4226         vmcs_writel(GUEST_CR3, guest_cr3);
4227 }
4228
4229 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4230 {
4231         /*
4232          * Pass through host's Machine Check Enable value to hw_cr4, which
4233          * is in force while we are in guest mode.  Do not let guests control
4234          * this bit, even if host CR4.MCE == 0.
4235          */
4236         unsigned long hw_cr4 =
4237                 (cr4_read_shadow() & X86_CR4_MCE) |
4238                 (cr4 & ~X86_CR4_MCE) |
4239                 (to_vmx(vcpu)->rmode.vm86_active ?
4240                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4241
4242         if (cr4 & X86_CR4_VMXE) {
4243                 /*
4244                  * To use VMXON (and later other VMX instructions), a guest
4245                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4246                  * So basically the check on whether to allow nested VMX
4247                  * is here.
4248                  */
4249                 if (!nested_vmx_allowed(vcpu))
4250                         return 1;
4251         }
4252
4253         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4254                 return 1;
4255
4256         vcpu->arch.cr4 = cr4;
4257         if (enable_ept) {
4258                 if (!is_paging(vcpu)) {
4259                         hw_cr4 &= ~X86_CR4_PAE;
4260                         hw_cr4 |= X86_CR4_PSE;
4261                 } else if (!(cr4 & X86_CR4_PAE)) {
4262                         hw_cr4 &= ~X86_CR4_PAE;
4263                 }
4264         }
4265
4266         if (!enable_unrestricted_guest && !is_paging(vcpu))
4267                 /*
4268                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4269                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4270                  * to be manually disabled when guest switches to non-paging
4271                  * mode.
4272                  *
4273                  * If !enable_unrestricted_guest, the CPU is always running
4274                  * with CR0.PG=1 and CR4 needs to be modified.
4275                  * If enable_unrestricted_guest, the CPU automatically
4276                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4277                  */
4278                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4279
4280         vmcs_writel(CR4_READ_SHADOW, cr4);
4281         vmcs_writel(GUEST_CR4, hw_cr4);
4282         return 0;
4283 }
4284
4285 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4286                             struct kvm_segment *var, int seg)
4287 {
4288         struct vcpu_vmx *vmx = to_vmx(vcpu);
4289         u32 ar;
4290
4291         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4292                 *var = vmx->rmode.segs[seg];
4293                 if (seg == VCPU_SREG_TR
4294                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4295                         return;
4296                 var->base = vmx_read_guest_seg_base(vmx, seg);
4297                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4298                 return;
4299         }
4300         var->base = vmx_read_guest_seg_base(vmx, seg);
4301         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4302         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4303         ar = vmx_read_guest_seg_ar(vmx, seg);
4304         var->unusable = (ar >> 16) & 1;
4305         var->type = ar & 15;
4306         var->s = (ar >> 4) & 1;
4307         var->dpl = (ar >> 5) & 3;
4308         /*
4309          * Some userspaces do not preserve unusable property. Since usable
4310          * segment has to be present according to VMX spec we can use present
4311          * property to amend userspace bug by making unusable segment always
4312          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4313          * segment as unusable.
4314          */
4315         var->present = !var->unusable;
4316         var->avl = (ar >> 12) & 1;
4317         var->l = (ar >> 13) & 1;
4318         var->db = (ar >> 14) & 1;
4319         var->g = (ar >> 15) & 1;
4320 }
4321
4322 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4323 {
4324         struct kvm_segment s;
4325
4326         if (to_vmx(vcpu)->rmode.vm86_active) {
4327                 vmx_get_segment(vcpu, &s, seg);
4328                 return s.base;
4329         }
4330         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4331 }
4332
4333 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4334 {
4335         struct vcpu_vmx *vmx = to_vmx(vcpu);
4336
4337         if (unlikely(vmx->rmode.vm86_active))
4338                 return 0;
4339         else {
4340                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4341                 return VMX_AR_DPL(ar);
4342         }
4343 }
4344
4345 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4346 {
4347         u32 ar;
4348
4349         if (var->unusable || !var->present)
4350                 ar = 1 << 16;
4351         else {
4352                 ar = var->type & 15;
4353                 ar |= (var->s & 1) << 4;
4354                 ar |= (var->dpl & 3) << 5;
4355                 ar |= (var->present & 1) << 7;
4356                 ar |= (var->avl & 1) << 12;
4357                 ar |= (var->l & 1) << 13;
4358                 ar |= (var->db & 1) << 14;
4359                 ar |= (var->g & 1) << 15;
4360         }
4361
4362         return ar;
4363 }
4364
4365 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4366                             struct kvm_segment *var, int seg)
4367 {
4368         struct vcpu_vmx *vmx = to_vmx(vcpu);
4369         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4370
4371         vmx_segment_cache_clear(vmx);
4372
4373         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4374                 vmx->rmode.segs[seg] = *var;
4375                 if (seg == VCPU_SREG_TR)
4376                         vmcs_write16(sf->selector, var->selector);
4377                 else if (var->s)
4378                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4379                 goto out;
4380         }
4381
4382         vmcs_writel(sf->base, var->base);
4383         vmcs_write32(sf->limit, var->limit);
4384         vmcs_write16(sf->selector, var->selector);
4385
4386         /*
4387          *   Fix the "Accessed" bit in AR field of segment registers for older
4388          * qemu binaries.
4389          *   IA32 arch specifies that at the time of processor reset the
4390          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4391          * is setting it to 0 in the userland code. This causes invalid guest
4392          * state vmexit when "unrestricted guest" mode is turned on.
4393          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4394          * tree. Newer qemu binaries with that qemu fix would not need this
4395          * kvm hack.
4396          */
4397         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4398                 var->type |= 0x1; /* Accessed */
4399
4400         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4401
4402 out:
4403         vmx->emulation_required = emulation_required(vcpu);
4404 }
4405
4406 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4407 {
4408         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4409
4410         *db = (ar >> 14) & 1;
4411         *l = (ar >> 13) & 1;
4412 }
4413
4414 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4415 {
4416         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4417         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4418 }
4419
4420 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4421 {
4422         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4423         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4424 }
4425
4426 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4427 {
4428         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4429         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4430 }
4431
4432 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4433 {
4434         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4435         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4436 }
4437
4438 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4439 {
4440         struct kvm_segment var;
4441         u32 ar;
4442
4443         vmx_get_segment(vcpu, &var, seg);
4444         var.dpl = 0x3;
4445         if (seg == VCPU_SREG_CS)
4446                 var.type = 0x3;
4447         ar = vmx_segment_access_rights(&var);
4448
4449         if (var.base != (var.selector << 4))
4450                 return false;
4451         if (var.limit != 0xffff)
4452                 return false;
4453         if (ar != 0xf3)
4454                 return false;
4455
4456         return true;
4457 }
4458
4459 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4460 {
4461         struct kvm_segment cs;
4462         unsigned int cs_rpl;
4463
4464         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4465         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4466
4467         if (cs.unusable)
4468                 return false;
4469         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4470                 return false;
4471         if (!cs.s)
4472                 return false;
4473         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4474                 if (cs.dpl > cs_rpl)
4475                         return false;
4476         } else {
4477                 if (cs.dpl != cs_rpl)
4478                         return false;
4479         }
4480         if (!cs.present)
4481                 return false;
4482
4483         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4484         return true;
4485 }
4486
4487 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4488 {
4489         struct kvm_segment ss;
4490         unsigned int ss_rpl;
4491
4492         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4493         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4494
4495         if (ss.unusable)
4496                 return true;
4497         if (ss.type != 3 && ss.type != 7)
4498                 return false;
4499         if (!ss.s)
4500                 return false;
4501         if (ss.dpl != ss_rpl) /* DPL != RPL */
4502                 return false;
4503         if (!ss.present)
4504                 return false;
4505
4506         return true;
4507 }
4508
4509 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4510 {
4511         struct kvm_segment var;
4512         unsigned int rpl;
4513
4514         vmx_get_segment(vcpu, &var, seg);
4515         rpl = var.selector & SEGMENT_RPL_MASK;
4516
4517         if (var.unusable)
4518                 return true;
4519         if (!var.s)
4520                 return false;
4521         if (!var.present)
4522                 return false;
4523         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4524                 if (var.dpl < rpl) /* DPL < RPL */
4525                         return false;
4526         }
4527
4528         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4529          * rights flags
4530          */
4531         return true;
4532 }
4533
4534 static bool tr_valid(struct kvm_vcpu *vcpu)
4535 {
4536         struct kvm_segment tr;
4537
4538         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4539
4540         if (tr.unusable)
4541                 return false;
4542         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4543                 return false;
4544         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4545                 return false;
4546         if (!tr.present)
4547                 return false;
4548
4549         return true;
4550 }
4551
4552 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4553 {
4554         struct kvm_segment ldtr;
4555
4556         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4557
4558         if (ldtr.unusable)
4559                 return true;
4560         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4561                 return false;
4562         if (ldtr.type != 2)
4563                 return false;
4564         if (!ldtr.present)
4565                 return false;
4566
4567         return true;
4568 }
4569
4570 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4571 {
4572         struct kvm_segment cs, ss;
4573
4574         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4575         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4576
4577         return ((cs.selector & SEGMENT_RPL_MASK) ==
4578                  (ss.selector & SEGMENT_RPL_MASK));
4579 }
4580
4581 /*
4582  * Check if guest state is valid. Returns true if valid, false if
4583  * not.
4584  * We assume that registers are always usable
4585  */
4586 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4587 {
4588         if (enable_unrestricted_guest)
4589                 return true;
4590
4591         /* real mode guest state checks */
4592         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4593                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4594                         return false;
4595                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4596                         return false;
4597                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4598                         return false;
4599                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4600                         return false;
4601                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4602                         return false;
4603                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4604                         return false;
4605         } else {
4606         /* protected mode guest state checks */
4607                 if (!cs_ss_rpl_check(vcpu))
4608                         return false;
4609                 if (!code_segment_valid(vcpu))
4610                         return false;
4611                 if (!stack_segment_valid(vcpu))
4612                         return false;
4613                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4614                         return false;
4615                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4616                         return false;
4617                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4618                         return false;
4619                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4620                         return false;
4621                 if (!tr_valid(vcpu))
4622                         return false;
4623                 if (!ldtr_valid(vcpu))
4624                         return false;
4625         }
4626         /* TODO:
4627          * - Add checks on RIP
4628          * - Add checks on RFLAGS
4629          */
4630
4631         return true;
4632 }
4633
4634 static int init_rmode_tss(struct kvm *kvm)
4635 {
4636         gfn_t fn;
4637         u16 data = 0;
4638         int idx, r;
4639
4640         idx = srcu_read_lock(&kvm->srcu);
4641         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4642         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4643         if (r < 0)
4644                 goto out;
4645         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4646         r = kvm_write_guest_page(kvm, fn++, &data,
4647                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4648         if (r < 0)
4649                 goto out;
4650         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4651         if (r < 0)
4652                 goto out;
4653         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4654         if (r < 0)
4655                 goto out;
4656         data = ~0;
4657         r = kvm_write_guest_page(kvm, fn, &data,
4658                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4659                                  sizeof(u8));
4660 out:
4661         srcu_read_unlock(&kvm->srcu, idx);
4662         return r;
4663 }
4664
4665 static int init_rmode_identity_map(struct kvm *kvm)
4666 {
4667         int i, idx, r = 0;
4668         kvm_pfn_t identity_map_pfn;
4669         u32 tmp;
4670
4671         if (!enable_ept)
4672                 return 0;
4673
4674         /* Protect kvm->arch.ept_identity_pagetable_done. */
4675         mutex_lock(&kvm->slots_lock);
4676
4677         if (likely(kvm->arch.ept_identity_pagetable_done))
4678                 goto out2;
4679
4680         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4681
4682         r = alloc_identity_pagetable(kvm);
4683         if (r < 0)
4684                 goto out2;
4685
4686         idx = srcu_read_lock(&kvm->srcu);
4687         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4688         if (r < 0)
4689                 goto out;
4690         /* Set up identity-mapping pagetable for EPT in real mode */
4691         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4692                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4693                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4694                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4695                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4696                 if (r < 0)
4697                         goto out;
4698         }
4699         kvm->arch.ept_identity_pagetable_done = true;
4700
4701 out:
4702         srcu_read_unlock(&kvm->srcu, idx);
4703
4704 out2:
4705         mutex_unlock(&kvm->slots_lock);
4706         return r;
4707 }
4708
4709 static void seg_setup(int seg)
4710 {
4711         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4712         unsigned int ar;
4713
4714         vmcs_write16(sf->selector, 0);
4715         vmcs_writel(sf->base, 0);
4716         vmcs_write32(sf->limit, 0xffff);
4717         ar = 0x93;
4718         if (seg == VCPU_SREG_CS)
4719                 ar |= 0x08; /* code segment */
4720
4721         vmcs_write32(sf->ar_bytes, ar);
4722 }
4723
4724 static int alloc_apic_access_page(struct kvm *kvm)
4725 {
4726         struct page *page;
4727         int r = 0;
4728
4729         mutex_lock(&kvm->slots_lock);
4730         if (kvm->arch.apic_access_page_done)
4731                 goto out;
4732         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4733                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4734         if (r)
4735                 goto out;
4736
4737         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4738         if (is_error_page(page)) {
4739                 r = -EFAULT;
4740                 goto out;
4741         }
4742
4743         /*
4744          * Do not pin the page in memory, so that memory hot-unplug
4745          * is able to migrate it.
4746          */
4747         put_page(page);
4748         kvm->arch.apic_access_page_done = true;
4749 out:
4750         mutex_unlock(&kvm->slots_lock);
4751         return r;
4752 }
4753
4754 static int alloc_identity_pagetable(struct kvm *kvm)
4755 {
4756         /* Called with kvm->slots_lock held. */
4757
4758         int r = 0;
4759
4760         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4761
4762         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4763                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4764
4765         return r;
4766 }
4767
4768 static int allocate_vpid(void)
4769 {
4770         int vpid;
4771
4772         if (!enable_vpid)
4773                 return 0;
4774         spin_lock(&vmx_vpid_lock);
4775         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4776         if (vpid < VMX_NR_VPIDS)
4777                 __set_bit(vpid, vmx_vpid_bitmap);
4778         else
4779                 vpid = 0;
4780         spin_unlock(&vmx_vpid_lock);
4781         return vpid;
4782 }
4783
4784 static void free_vpid(int vpid)
4785 {
4786         if (!enable_vpid || vpid == 0)
4787                 return;
4788         spin_lock(&vmx_vpid_lock);
4789         __clear_bit(vpid, vmx_vpid_bitmap);
4790         spin_unlock(&vmx_vpid_lock);
4791 }
4792
4793 #define MSR_TYPE_R      1
4794 #define MSR_TYPE_W      2
4795 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4796                                                 u32 msr, int type)
4797 {
4798         int f = sizeof(unsigned long);
4799
4800         if (!cpu_has_vmx_msr_bitmap())
4801                 return;
4802
4803         /*
4804          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4805          * have the write-low and read-high bitmap offsets the wrong way round.
4806          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4807          */
4808         if (msr <= 0x1fff) {
4809                 if (type & MSR_TYPE_R)
4810                         /* read-low */
4811                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4812
4813                 if (type & MSR_TYPE_W)
4814                         /* write-low */
4815                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4816
4817         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4818                 msr &= 0x1fff;
4819                 if (type & MSR_TYPE_R)
4820                         /* read-high */
4821                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4822
4823                 if (type & MSR_TYPE_W)
4824                         /* write-high */
4825                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4826
4827         }
4828 }
4829
4830 /*
4831  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4832  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4833  */
4834 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4835                                                unsigned long *msr_bitmap_nested,
4836                                                u32 msr, int type)
4837 {
4838         int f = sizeof(unsigned long);
4839
4840         if (!cpu_has_vmx_msr_bitmap()) {
4841                 WARN_ON(1);
4842                 return;
4843         }
4844
4845         /*
4846          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4847          * have the write-low and read-high bitmap offsets the wrong way round.
4848          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4849          */
4850         if (msr <= 0x1fff) {
4851                 if (type & MSR_TYPE_R &&
4852                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4853                         /* read-low */
4854                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4855
4856                 if (type & MSR_TYPE_W &&
4857                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4858                         /* write-low */
4859                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4860
4861         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4862                 msr &= 0x1fff;
4863                 if (type & MSR_TYPE_R &&
4864                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4865                         /* read-high */
4866                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4867
4868                 if (type & MSR_TYPE_W &&
4869                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4870                         /* write-high */
4871                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4872
4873         }
4874 }
4875
4876 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4877 {
4878         if (!longmode_only)
4879                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4880                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4881         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4882                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4883 }
4884
4885 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4886 {
4887         if (apicv_active) {
4888                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4889                                 msr, type);
4890                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4891                                 msr, type);
4892         } else {
4893                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4894                                 msr, type);
4895                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4896                                 msr, type);
4897         }
4898 }
4899
4900 static bool vmx_get_enable_apicv(void)
4901 {
4902         return enable_apicv;
4903 }
4904
4905 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4906 {
4907         struct vcpu_vmx *vmx = to_vmx(vcpu);
4908         int max_irr;
4909         void *vapic_page;
4910         u16 status;
4911
4912         if (vmx->nested.pi_desc &&
4913             vmx->nested.pi_pending) {
4914                 vmx->nested.pi_pending = false;
4915                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4916                         return;
4917
4918                 max_irr = find_last_bit(
4919                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4920
4921                 if (max_irr == 256)
4922                         return;
4923
4924                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4925                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4926                 kunmap(vmx->nested.virtual_apic_page);
4927
4928                 status = vmcs_read16(GUEST_INTR_STATUS);
4929                 if ((u8)max_irr > ((u8)status & 0xff)) {
4930                         status &= ~0xff;
4931                         status |= (u8)max_irr;
4932                         vmcs_write16(GUEST_INTR_STATUS, status);
4933                 }
4934         }
4935 }
4936
4937 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4938 {
4939 #ifdef CONFIG_SMP
4940         if (vcpu->mode == IN_GUEST_MODE) {
4941                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4942
4943                 /*
4944                  * Currently, we don't support urgent interrupt,
4945                  * all interrupts are recognized as non-urgent
4946                  * interrupt, so we cannot post interrupts when
4947                  * 'SN' is set.
4948                  *
4949                  * If the vcpu is in guest mode, it means it is
4950                  * running instead of being scheduled out and
4951                  * waiting in the run queue, and that's the only
4952                  * case when 'SN' is set currently, warning if
4953                  * 'SN' is set.
4954                  */
4955                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4956
4957                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4958                                 POSTED_INTR_VECTOR);
4959                 return true;
4960         }
4961 #endif
4962         return false;
4963 }
4964
4965 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4966                                                 int vector)
4967 {
4968         struct vcpu_vmx *vmx = to_vmx(vcpu);
4969
4970         if (is_guest_mode(vcpu) &&
4971             vector == vmx->nested.posted_intr_nv) {
4972                 /* the PIR and ON have been set by L1. */
4973                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4974                 /*
4975                  * If a posted intr is not recognized by hardware,
4976                  * we will accomplish it in the next vmentry.
4977                  */
4978                 vmx->nested.pi_pending = true;
4979                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4980                 return 0;
4981         }
4982         return -1;
4983 }
4984 /*
4985  * Send interrupt to vcpu via posted interrupt way.
4986  * 1. If target vcpu is running(non-root mode), send posted interrupt
4987  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4988  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4989  * interrupt from PIR in next vmentry.
4990  */
4991 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4992 {
4993         struct vcpu_vmx *vmx = to_vmx(vcpu);
4994         int r;
4995
4996         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4997         if (!r)
4998                 return;
4999
5000         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5001                 return;
5002
5003         /* If a previous notification has sent the IPI, nothing to do.  */
5004         if (pi_test_and_set_on(&vmx->pi_desc))
5005                 return;
5006
5007         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5008                 kvm_vcpu_kick(vcpu);
5009 }
5010
5011 /*
5012  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5013  * will not change in the lifetime of the guest.
5014  * Note that host-state that does change is set elsewhere. E.g., host-state
5015  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5016  */
5017 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5018 {
5019         u32 low32, high32;
5020         unsigned long tmpl;
5021         struct desc_ptr dt;
5022         unsigned long cr0, cr4;
5023
5024         cr0 = read_cr0();
5025         WARN_ON(cr0 & X86_CR0_TS);
5026         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5027         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5028
5029         /* Save the most likely value for this task's CR4 in the VMCS. */
5030         cr4 = cr4_read_shadow();
5031         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5032         vmx->host_state.vmcs_host_cr4 = cr4;
5033
5034         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5035 #ifdef CONFIG_X86_64
5036         /*
5037          * Load null selectors, so we can avoid reloading them in
5038          * __vmx_load_host_state(), in case userspace uses the null selectors
5039          * too (the expected case).
5040          */
5041         vmcs_write16(HOST_DS_SELECTOR, 0);
5042         vmcs_write16(HOST_ES_SELECTOR, 0);
5043 #else
5044         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5045         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5046 #endif
5047         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5048         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5049
5050         native_store_idt(&dt);
5051         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5052         vmx->host_idt_base = dt.address;
5053
5054         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5055
5056         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5057         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5058         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5059         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5060
5061         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5062                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5063                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5064         }
5065 }
5066
5067 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5068 {
5069         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5070         if (enable_ept)
5071                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5072         if (is_guest_mode(&vmx->vcpu))
5073                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5074                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5075         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5076 }
5077
5078 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5079 {
5080         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5081
5082         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5083                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5084         /* Enable the preemption timer dynamically */
5085         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5086         return pin_based_exec_ctrl;
5087 }
5088
5089 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5090 {
5091         struct vcpu_vmx *vmx = to_vmx(vcpu);
5092
5093         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5094         if (cpu_has_secondary_exec_ctrls()) {
5095                 if (kvm_vcpu_apicv_active(vcpu))
5096                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5097                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5098                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5099                 else
5100                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5101                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5102                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5103         }
5104
5105         if (cpu_has_vmx_msr_bitmap())
5106                 vmx_set_msr_bitmap(vcpu);
5107 }
5108
5109 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5110 {
5111         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5112
5113         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5114                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5115
5116         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5117                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5118 #ifdef CONFIG_X86_64
5119                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5120                                 CPU_BASED_CR8_LOAD_EXITING;
5121 #endif
5122         }
5123         if (!enable_ept)
5124                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5125                                 CPU_BASED_CR3_LOAD_EXITING  |
5126                                 CPU_BASED_INVLPG_EXITING;
5127         return exec_control;
5128 }
5129
5130 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5131 {
5132         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5133         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5134                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5135         if (vmx->vpid == 0)
5136                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5137         if (!enable_ept) {
5138                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5139                 enable_unrestricted_guest = 0;
5140                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5141                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5142         }
5143         if (!enable_unrestricted_guest)
5144                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5145         if (!ple_gap)
5146                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5147         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5148                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5149                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5150         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5151         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5152            (handle_vmptrld).
5153            We can NOT enable shadow_vmcs here because we don't have yet
5154            a current VMCS12
5155         */
5156         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5157
5158         if (!enable_pml)
5159                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5160
5161         return exec_control;
5162 }
5163
5164 static void ept_set_mmio_spte_mask(void)
5165 {
5166         /*
5167          * EPT Misconfigurations can be generated if the value of bits 2:0
5168          * of an EPT paging-structure entry is 110b (write/execute).
5169          */
5170         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5171 }
5172
5173 #define VMX_XSS_EXIT_BITMAP 0
5174 /*
5175  * Sets up the vmcs for emulated real mode.
5176  */
5177 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5178 {
5179 #ifdef CONFIG_X86_64
5180         unsigned long a;
5181 #endif
5182         int i;
5183
5184         /* I/O */
5185         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5186         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5187
5188         if (enable_shadow_vmcs) {
5189                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5190                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5191         }
5192         if (cpu_has_vmx_msr_bitmap())
5193                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5194
5195         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5196
5197         /* Control */
5198         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5199         vmx->hv_deadline_tsc = -1;
5200
5201         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5202
5203         if (cpu_has_secondary_exec_ctrls()) {
5204                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5205                                 vmx_secondary_exec_control(vmx));
5206         }
5207
5208         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5209                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5210                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5211                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5212                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5213
5214                 vmcs_write16(GUEST_INTR_STATUS, 0);
5215
5216                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5217                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5218         }
5219
5220         if (ple_gap) {
5221                 vmcs_write32(PLE_GAP, ple_gap);
5222                 vmx->ple_window = ple_window;
5223                 vmx->ple_window_dirty = true;
5224         }
5225
5226         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5227         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5228         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5229
5230         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5231         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5232         vmx_set_constant_host_state(vmx);
5233 #ifdef CONFIG_X86_64
5234         rdmsrl(MSR_FS_BASE, a);
5235         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5236         rdmsrl(MSR_GS_BASE, a);
5237         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5238 #else
5239         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5240         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5241 #endif
5242
5243         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5244         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5245         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5246         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5247         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5248
5249         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5250                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5251
5252         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5253                 u32 index = vmx_msr_index[i];
5254                 u32 data_low, data_high;
5255                 int j = vmx->nmsrs;
5256
5257                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5258                         continue;
5259                 if (wrmsr_safe(index, data_low, data_high) < 0)
5260                         continue;
5261                 vmx->guest_msrs[j].index = i;
5262                 vmx->guest_msrs[j].data = 0;
5263                 vmx->guest_msrs[j].mask = -1ull;
5264                 ++vmx->nmsrs;
5265         }
5266
5267
5268         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5269
5270         /* 22.2.1, 20.8.1 */
5271         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5272
5273         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5274         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5275
5276         set_cr4_guest_host_mask(vmx);
5277
5278         if (vmx_xsaves_supported())
5279                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5280
5281         if (enable_pml) {
5282                 ASSERT(vmx->pml_pg);
5283                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5284                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5285         }
5286
5287         return 0;
5288 }
5289
5290 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5291 {
5292         struct vcpu_vmx *vmx = to_vmx(vcpu);
5293         struct msr_data apic_base_msr;
5294         u64 cr0;
5295
5296         vmx->rmode.vm86_active = 0;
5297
5298         vmx->soft_vnmi_blocked = 0;
5299
5300         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5301         kvm_set_cr8(vcpu, 0);
5302
5303         if (!init_event) {
5304                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5305                                      MSR_IA32_APICBASE_ENABLE;
5306                 if (kvm_vcpu_is_reset_bsp(vcpu))
5307                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5308                 apic_base_msr.host_initiated = true;
5309                 kvm_set_apic_base(vcpu, &apic_base_msr);
5310         }
5311
5312         vmx_segment_cache_clear(vmx);
5313
5314         seg_setup(VCPU_SREG_CS);
5315         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5316         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5317
5318         seg_setup(VCPU_SREG_DS);
5319         seg_setup(VCPU_SREG_ES);
5320         seg_setup(VCPU_SREG_FS);
5321         seg_setup(VCPU_SREG_GS);
5322         seg_setup(VCPU_SREG_SS);
5323
5324         vmcs_write16(GUEST_TR_SELECTOR, 0);
5325         vmcs_writel(GUEST_TR_BASE, 0);
5326         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5327         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5328
5329         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5330         vmcs_writel(GUEST_LDTR_BASE, 0);
5331         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5332         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5333
5334         if (!init_event) {
5335                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5336                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5337                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5338                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5339         }
5340
5341         vmcs_writel(GUEST_RFLAGS, 0x02);
5342         kvm_rip_write(vcpu, 0xfff0);
5343
5344         vmcs_writel(GUEST_GDTR_BASE, 0);
5345         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5346
5347         vmcs_writel(GUEST_IDTR_BASE, 0);
5348         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5349
5350         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5351         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5352         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5353
5354         setup_msrs(vmx);
5355
5356         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5357
5358         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5359                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5360                 if (cpu_need_tpr_shadow(vcpu))
5361                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5362                                      __pa(vcpu->arch.apic->regs));
5363                 vmcs_write32(TPR_THRESHOLD, 0);
5364         }
5365
5366         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5367
5368         if (kvm_vcpu_apicv_active(vcpu))
5369                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5370
5371         if (vmx->vpid != 0)
5372                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5373
5374         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5375         vmx->vcpu.arch.cr0 = cr0;
5376         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5377         vmx_set_cr4(vcpu, 0);
5378         vmx_set_efer(vcpu, 0);
5379
5380         update_exception_bitmap(vcpu);
5381
5382         vpid_sync_context(vmx->vpid);
5383 }
5384
5385 /*
5386  * In nested virtualization, check if L1 asked to exit on external interrupts.
5387  * For most existing hypervisors, this will always return true.
5388  */
5389 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5390 {
5391         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5392                 PIN_BASED_EXT_INTR_MASK;
5393 }
5394
5395 /*
5396  * In nested virtualization, check if L1 has set
5397  * VM_EXIT_ACK_INTR_ON_EXIT
5398  */
5399 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5400 {
5401         return get_vmcs12(vcpu)->vm_exit_controls &
5402                 VM_EXIT_ACK_INTR_ON_EXIT;
5403 }
5404
5405 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5406 {
5407         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5408                 PIN_BASED_NMI_EXITING;
5409 }
5410
5411 static void enable_irq_window(struct kvm_vcpu *vcpu)
5412 {
5413         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5414                       CPU_BASED_VIRTUAL_INTR_PENDING);
5415 }
5416
5417 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5418 {
5419         if (!cpu_has_virtual_nmis() ||
5420             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5421                 enable_irq_window(vcpu);
5422                 return;
5423         }
5424
5425         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5426                       CPU_BASED_VIRTUAL_NMI_PENDING);
5427 }
5428
5429 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5430 {
5431         struct vcpu_vmx *vmx = to_vmx(vcpu);
5432         uint32_t intr;
5433         int irq = vcpu->arch.interrupt.nr;
5434
5435         trace_kvm_inj_virq(irq);
5436
5437         ++vcpu->stat.irq_injections;
5438         if (vmx->rmode.vm86_active) {
5439                 int inc_eip = 0;
5440                 if (vcpu->arch.interrupt.soft)
5441                         inc_eip = vcpu->arch.event_exit_inst_len;
5442                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5443                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5444                 return;
5445         }
5446         intr = irq | INTR_INFO_VALID_MASK;
5447         if (vcpu->arch.interrupt.soft) {
5448                 intr |= INTR_TYPE_SOFT_INTR;
5449                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5450                              vmx->vcpu.arch.event_exit_inst_len);
5451         } else
5452                 intr |= INTR_TYPE_EXT_INTR;
5453         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5454 }
5455
5456 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5457 {
5458         struct vcpu_vmx *vmx = to_vmx(vcpu);
5459
5460         if (!is_guest_mode(vcpu)) {
5461                 if (!cpu_has_virtual_nmis()) {
5462                         /*
5463                          * Tracking the NMI-blocked state in software is built upon
5464                          * finding the next open IRQ window. This, in turn, depends on
5465                          * well-behaving guests: They have to keep IRQs disabled at
5466                          * least as long as the NMI handler runs. Otherwise we may
5467                          * cause NMI nesting, maybe breaking the guest. But as this is
5468                          * highly unlikely, we can live with the residual risk.
5469                          */
5470                         vmx->soft_vnmi_blocked = 1;
5471                         vmx->vnmi_blocked_time = 0;
5472                 }
5473
5474                 ++vcpu->stat.nmi_injections;
5475                 vmx->nmi_known_unmasked = false;
5476         }
5477
5478         if (vmx->rmode.vm86_active) {
5479                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5480                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5481                 return;
5482         }
5483
5484         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5485                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5486 }
5487
5488 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5489 {
5490         if (!cpu_has_virtual_nmis())
5491                 return to_vmx(vcpu)->soft_vnmi_blocked;
5492         if (to_vmx(vcpu)->nmi_known_unmasked)
5493                 return false;
5494         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5495 }
5496
5497 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5498 {
5499         struct vcpu_vmx *vmx = to_vmx(vcpu);
5500
5501         if (!cpu_has_virtual_nmis()) {
5502                 if (vmx->soft_vnmi_blocked != masked) {
5503                         vmx->soft_vnmi_blocked = masked;
5504                         vmx->vnmi_blocked_time = 0;
5505                 }
5506         } else {
5507                 vmx->nmi_known_unmasked = !masked;
5508                 if (masked)
5509                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5510                                       GUEST_INTR_STATE_NMI);
5511                 else
5512                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5513                                         GUEST_INTR_STATE_NMI);
5514         }
5515 }
5516
5517 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5518 {
5519         if (to_vmx(vcpu)->nested.nested_run_pending)
5520                 return 0;
5521
5522         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5523                 return 0;
5524
5525         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5526                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5527                    | GUEST_INTR_STATE_NMI));
5528 }
5529
5530 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5531 {
5532         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5533                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5534                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5535                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5536 }
5537
5538 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5539 {
5540         int ret;
5541
5542         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5543                                     PAGE_SIZE * 3);
5544         if (ret)
5545                 return ret;
5546         kvm->arch.tss_addr = addr;
5547         return init_rmode_tss(kvm);
5548 }
5549
5550 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5551 {
5552         switch (vec) {
5553         case BP_VECTOR:
5554                 /*
5555                  * Update instruction length as we may reinject the exception
5556                  * from user space while in guest debugging mode.
5557                  */
5558                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5559                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5560                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5561                         return false;
5562                 /* fall through */
5563         case DB_VECTOR:
5564                 if (vcpu->guest_debug &
5565                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5566                         return false;
5567                 /* fall through */
5568         case DE_VECTOR:
5569         case OF_VECTOR:
5570         case BR_VECTOR:
5571         case UD_VECTOR:
5572         case DF_VECTOR:
5573         case SS_VECTOR:
5574         case GP_VECTOR:
5575         case MF_VECTOR:
5576                 return true;
5577         break;
5578         }
5579         return false;
5580 }
5581
5582 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5583                                   int vec, u32 err_code)
5584 {
5585         /*
5586          * Instruction with address size override prefix opcode 0x67
5587          * Cause the #SS fault with 0 error code in VM86 mode.
5588          */
5589         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5590                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5591                         if (vcpu->arch.halt_request) {
5592                                 vcpu->arch.halt_request = 0;
5593                                 return kvm_vcpu_halt(vcpu);
5594                         }
5595                         return 1;
5596                 }
5597                 return 0;
5598         }
5599
5600         /*
5601          * Forward all other exceptions that are valid in real mode.
5602          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5603          *        the required debugging infrastructure rework.
5604          */
5605         kvm_queue_exception(vcpu, vec);
5606         return 1;
5607 }
5608
5609 /*
5610  * Trigger machine check on the host. We assume all the MSRs are already set up
5611  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5612  * We pass a fake environment to the machine check handler because we want
5613  * the guest to be always treated like user space, no matter what context
5614  * it used internally.
5615  */
5616 static void kvm_machine_check(void)
5617 {
5618 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5619         struct pt_regs regs = {
5620                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5621                 .flags = X86_EFLAGS_IF,
5622         };
5623
5624         do_machine_check(&regs, 0);
5625 #endif
5626 }
5627
5628 static int handle_machine_check(struct kvm_vcpu *vcpu)
5629 {
5630         /* already handled by vcpu_run */
5631         return 1;
5632 }
5633
5634 static int handle_exception(struct kvm_vcpu *vcpu)
5635 {
5636         struct vcpu_vmx *vmx = to_vmx(vcpu);
5637         struct kvm_run *kvm_run = vcpu->run;
5638         u32 intr_info, ex_no, error_code;
5639         unsigned long cr2, rip, dr6;
5640         u32 vect_info;
5641         enum emulation_result er;
5642
5643         vect_info = vmx->idt_vectoring_info;
5644         intr_info = vmx->exit_intr_info;
5645
5646         if (is_machine_check(intr_info))
5647                 return handle_machine_check(vcpu);
5648
5649         if (is_nmi(intr_info))
5650                 return 1;  /* already handled by vmx_vcpu_run() */
5651
5652         if (is_invalid_opcode(intr_info)) {
5653                 if (is_guest_mode(vcpu)) {
5654                         kvm_queue_exception(vcpu, UD_VECTOR);
5655                         return 1;
5656                 }
5657                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5658                 if (er != EMULATE_DONE)
5659                         kvm_queue_exception(vcpu, UD_VECTOR);
5660                 return 1;
5661         }
5662
5663         error_code = 0;
5664         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5665                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5666
5667         /*
5668          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5669          * MMIO, it is better to report an internal error.
5670          * See the comments in vmx_handle_exit.
5671          */
5672         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5673             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5674                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5675                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5676                 vcpu->run->internal.ndata = 3;
5677                 vcpu->run->internal.data[0] = vect_info;
5678                 vcpu->run->internal.data[1] = intr_info;
5679                 vcpu->run->internal.data[2] = error_code;
5680                 return 0;
5681         }
5682
5683         if (is_page_fault(intr_info)) {
5684                 /* EPT won't cause page fault directly */
5685                 BUG_ON(enable_ept);
5686                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5687                 trace_kvm_page_fault(cr2, error_code);
5688
5689                 if (kvm_event_needs_reinjection(vcpu))
5690                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5691                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5692         }
5693
5694         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5695
5696         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5697                 return handle_rmode_exception(vcpu, ex_no, error_code);
5698
5699         switch (ex_no) {
5700         case AC_VECTOR:
5701                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5702                 return 1;
5703         case DB_VECTOR:
5704                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5705                 if (!(vcpu->guest_debug &
5706                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5707                         vcpu->arch.dr6 &= ~15;
5708                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5709                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5710                                 skip_emulated_instruction(vcpu);
5711
5712                         kvm_queue_exception(vcpu, DB_VECTOR);
5713                         return 1;
5714                 }
5715                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5716                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5717                 /* fall through */
5718         case BP_VECTOR:
5719                 /*
5720                  * Update instruction length as we may reinject #BP from
5721                  * user space while in guest debugging mode. Reading it for
5722                  * #DB as well causes no harm, it is not used in that case.
5723                  */
5724                 vmx->vcpu.arch.event_exit_inst_len =
5725                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5726                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5727                 rip = kvm_rip_read(vcpu);
5728                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5729                 kvm_run->debug.arch.exception = ex_no;
5730                 break;
5731         default:
5732                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5733                 kvm_run->ex.exception = ex_no;
5734                 kvm_run->ex.error_code = error_code;
5735                 break;
5736         }
5737         return 0;
5738 }
5739
5740 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5741 {
5742         ++vcpu->stat.irq_exits;
5743         return 1;
5744 }
5745
5746 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5747 {
5748         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5749         return 0;
5750 }
5751
5752 static int handle_io(struct kvm_vcpu *vcpu)
5753 {
5754         unsigned long exit_qualification;
5755         int size, in, string, ret;
5756         unsigned port;
5757
5758         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5759         string = (exit_qualification & 16) != 0;
5760         in = (exit_qualification & 8) != 0;
5761
5762         ++vcpu->stat.io_exits;
5763
5764         if (string || in)
5765                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5766
5767         port = exit_qualification >> 16;
5768         size = (exit_qualification & 7) + 1;
5769
5770         ret = kvm_skip_emulated_instruction(vcpu);
5771
5772         /*
5773          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5774          * KVM_EXIT_DEBUG here.
5775          */
5776         return kvm_fast_pio_out(vcpu, size, port) && ret;
5777 }
5778
5779 static void
5780 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5781 {
5782         /*
5783          * Patch in the VMCALL instruction:
5784          */
5785         hypercall[0] = 0x0f;
5786         hypercall[1] = 0x01;
5787         hypercall[2] = 0xc1;
5788 }
5789
5790 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5791 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5792 {
5793         if (is_guest_mode(vcpu)) {
5794                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5795                 unsigned long orig_val = val;
5796
5797                 /*
5798                  * We get here when L2 changed cr0 in a way that did not change
5799                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5800                  * but did change L0 shadowed bits. So we first calculate the
5801                  * effective cr0 value that L1 would like to write into the
5802                  * hardware. It consists of the L2-owned bits from the new
5803                  * value combined with the L1-owned bits from L1's guest_cr0.
5804                  */
5805                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5806                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5807
5808                 if (!nested_guest_cr0_valid(vcpu, val))
5809                         return 1;
5810
5811                 if (kvm_set_cr0(vcpu, val))
5812                         return 1;
5813                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5814                 return 0;
5815         } else {
5816                 if (to_vmx(vcpu)->nested.vmxon &&
5817                     !nested_host_cr0_valid(vcpu, val))
5818                         return 1;
5819
5820                 return kvm_set_cr0(vcpu, val);
5821         }
5822 }
5823
5824 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5825 {
5826         if (is_guest_mode(vcpu)) {
5827                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5828                 unsigned long orig_val = val;
5829
5830                 /* analogously to handle_set_cr0 */
5831                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5832                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5833                 if (kvm_set_cr4(vcpu, val))
5834                         return 1;
5835                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5836                 return 0;
5837         } else
5838                 return kvm_set_cr4(vcpu, val);
5839 }
5840
5841 static int handle_cr(struct kvm_vcpu *vcpu)
5842 {
5843         unsigned long exit_qualification, val;
5844         int cr;
5845         int reg;
5846         int err;
5847         int ret;
5848
5849         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5850         cr = exit_qualification & 15;
5851         reg = (exit_qualification >> 8) & 15;
5852         switch ((exit_qualification >> 4) & 3) {
5853         case 0: /* mov to cr */
5854                 val = kvm_register_readl(vcpu, reg);
5855                 trace_kvm_cr_write(cr, val);
5856                 switch (cr) {
5857                 case 0:
5858                         err = handle_set_cr0(vcpu, val);
5859                         return kvm_complete_insn_gp(vcpu, err);
5860                 case 3:
5861                         err = kvm_set_cr3(vcpu, val);
5862                         return kvm_complete_insn_gp(vcpu, err);
5863                 case 4:
5864                         err = handle_set_cr4(vcpu, val);
5865                         return kvm_complete_insn_gp(vcpu, err);
5866                 case 8: {
5867                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5868                                 u8 cr8 = (u8)val;
5869                                 err = kvm_set_cr8(vcpu, cr8);
5870                                 ret = kvm_complete_insn_gp(vcpu, err);
5871                                 if (lapic_in_kernel(vcpu))
5872                                         return ret;
5873                                 if (cr8_prev <= cr8)
5874                                         return ret;
5875                                 /*
5876                                  * TODO: we might be squashing a
5877                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5878                                  * KVM_EXIT_DEBUG here.
5879                                  */
5880                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5881                                 return 0;
5882                         }
5883                 }
5884                 break;
5885         case 2: /* clts */
5886                 WARN_ONCE(1, "Guest should always own CR0.TS");
5887                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5888                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5889                 return kvm_skip_emulated_instruction(vcpu);
5890         case 1: /*mov from cr*/
5891                 switch (cr) {
5892                 case 3:
5893                         val = kvm_read_cr3(vcpu);
5894                         kvm_register_write(vcpu, reg, val);
5895                         trace_kvm_cr_read(cr, val);
5896                         return kvm_skip_emulated_instruction(vcpu);
5897                 case 8:
5898                         val = kvm_get_cr8(vcpu);
5899                         kvm_register_write(vcpu, reg, val);
5900                         trace_kvm_cr_read(cr, val);
5901                         return kvm_skip_emulated_instruction(vcpu);
5902                 }
5903                 break;
5904         case 3: /* lmsw */
5905                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5906                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5907                 kvm_lmsw(vcpu, val);
5908
5909                 return kvm_skip_emulated_instruction(vcpu);
5910         default:
5911                 break;
5912         }
5913         vcpu->run->exit_reason = 0;
5914         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5915                (int)(exit_qualification >> 4) & 3, cr);
5916         return 0;
5917 }
5918
5919 static int handle_dr(struct kvm_vcpu *vcpu)
5920 {
5921         unsigned long exit_qualification;
5922         int dr, dr7, reg;
5923
5924         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5925         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5926
5927         /* First, if DR does not exist, trigger UD */
5928         if (!kvm_require_dr(vcpu, dr))
5929                 return 1;
5930
5931         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5932         if (!kvm_require_cpl(vcpu, 0))
5933                 return 1;
5934         dr7 = vmcs_readl(GUEST_DR7);
5935         if (dr7 & DR7_GD) {
5936                 /*
5937                  * As the vm-exit takes precedence over the debug trap, we
5938                  * need to emulate the latter, either for the host or the
5939                  * guest debugging itself.
5940                  */
5941                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5942                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5943                         vcpu->run->debug.arch.dr7 = dr7;
5944                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5945                         vcpu->run->debug.arch.exception = DB_VECTOR;
5946                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5947                         return 0;
5948                 } else {
5949                         vcpu->arch.dr6 &= ~15;
5950                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5951                         kvm_queue_exception(vcpu, DB_VECTOR);
5952                         return 1;
5953                 }
5954         }
5955
5956         if (vcpu->guest_debug == 0) {
5957                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5958                                 CPU_BASED_MOV_DR_EXITING);
5959
5960                 /*
5961                  * No more DR vmexits; force a reload of the debug registers
5962                  * and reenter on this instruction.  The next vmexit will
5963                  * retrieve the full state of the debug registers.
5964                  */
5965                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5966                 return 1;
5967         }
5968
5969         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5970         if (exit_qualification & TYPE_MOV_FROM_DR) {
5971                 unsigned long val;
5972
5973                 if (kvm_get_dr(vcpu, dr, &val))
5974                         return 1;
5975                 kvm_register_write(vcpu, reg, val);
5976         } else
5977                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5978                         return 1;
5979
5980         return kvm_skip_emulated_instruction(vcpu);
5981 }
5982
5983 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5984 {
5985         return vcpu->arch.dr6;
5986 }
5987
5988 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5989 {
5990 }
5991
5992 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5993 {
5994         get_debugreg(vcpu->arch.db[0], 0);
5995         get_debugreg(vcpu->arch.db[1], 1);
5996         get_debugreg(vcpu->arch.db[2], 2);
5997         get_debugreg(vcpu->arch.db[3], 3);
5998         get_debugreg(vcpu->arch.dr6, 6);
5999         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6000
6001         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6002         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6003 }
6004
6005 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6006 {
6007         vmcs_writel(GUEST_DR7, val);
6008 }
6009
6010 static int handle_cpuid(struct kvm_vcpu *vcpu)
6011 {
6012         return kvm_emulate_cpuid(vcpu);
6013 }
6014
6015 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6016 {
6017         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6018         struct msr_data msr_info;
6019
6020         msr_info.index = ecx;
6021         msr_info.host_initiated = false;
6022         if (vmx_get_msr(vcpu, &msr_info)) {
6023                 trace_kvm_msr_read_ex(ecx);
6024                 kvm_inject_gp(vcpu, 0);
6025                 return 1;
6026         }
6027
6028         trace_kvm_msr_read(ecx, msr_info.data);
6029
6030         /* FIXME: handling of bits 32:63 of rax, rdx */
6031         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6032         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6033         return kvm_skip_emulated_instruction(vcpu);
6034 }
6035
6036 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6037 {
6038         struct msr_data msr;
6039         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6040         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6041                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6042
6043         msr.data = data;
6044         msr.index = ecx;
6045         msr.host_initiated = false;
6046         if (kvm_set_msr(vcpu, &msr) != 0) {
6047                 trace_kvm_msr_write_ex(ecx, data);
6048                 kvm_inject_gp(vcpu, 0);
6049                 return 1;
6050         }
6051
6052         trace_kvm_msr_write(ecx, data);
6053         return kvm_skip_emulated_instruction(vcpu);
6054 }
6055
6056 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6057 {
6058         kvm_apic_update_ppr(vcpu);
6059         return 1;
6060 }
6061
6062 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6063 {
6064         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6065                         CPU_BASED_VIRTUAL_INTR_PENDING);
6066
6067         kvm_make_request(KVM_REQ_EVENT, vcpu);
6068
6069         ++vcpu->stat.irq_window_exits;
6070         return 1;
6071 }
6072
6073 static int handle_halt(struct kvm_vcpu *vcpu)
6074 {
6075         return kvm_emulate_halt(vcpu);
6076 }
6077
6078 static int handle_vmcall(struct kvm_vcpu *vcpu)
6079 {
6080         return kvm_emulate_hypercall(vcpu);
6081 }
6082
6083 static int handle_invd(struct kvm_vcpu *vcpu)
6084 {
6085         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6086 }
6087
6088 static int handle_invlpg(struct kvm_vcpu *vcpu)
6089 {
6090         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6091
6092         kvm_mmu_invlpg(vcpu, exit_qualification);
6093         return kvm_skip_emulated_instruction(vcpu);
6094 }
6095
6096 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6097 {
6098         int err;
6099
6100         err = kvm_rdpmc(vcpu);
6101         return kvm_complete_insn_gp(vcpu, err);
6102 }
6103
6104 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6105 {
6106         return kvm_emulate_wbinvd(vcpu);
6107 }
6108
6109 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6110 {
6111         u64 new_bv = kvm_read_edx_eax(vcpu);
6112         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6113
6114         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6115                 return kvm_skip_emulated_instruction(vcpu);
6116         return 1;
6117 }
6118
6119 static int handle_xsaves(struct kvm_vcpu *vcpu)
6120 {
6121         kvm_skip_emulated_instruction(vcpu);
6122         WARN(1, "this should never happen\n");
6123         return 1;
6124 }
6125
6126 static int handle_xrstors(struct kvm_vcpu *vcpu)
6127 {
6128         kvm_skip_emulated_instruction(vcpu);
6129         WARN(1, "this should never happen\n");
6130         return 1;
6131 }
6132
6133 static int handle_apic_access(struct kvm_vcpu *vcpu)
6134 {
6135         if (likely(fasteoi)) {
6136                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6137                 int access_type, offset;
6138
6139                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6140                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6141                 /*
6142                  * Sane guest uses MOV to write EOI, with written value
6143                  * not cared. So make a short-circuit here by avoiding
6144                  * heavy instruction emulation.
6145                  */
6146                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6147                     (offset == APIC_EOI)) {
6148                         kvm_lapic_set_eoi(vcpu);
6149                         return kvm_skip_emulated_instruction(vcpu);
6150                 }
6151         }
6152         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6153 }
6154
6155 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6156 {
6157         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6158         int vector = exit_qualification & 0xff;
6159
6160         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6161         kvm_apic_set_eoi_accelerated(vcpu, vector);
6162         return 1;
6163 }
6164
6165 static int handle_apic_write(struct kvm_vcpu *vcpu)
6166 {
6167         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6168         u32 offset = exit_qualification & 0xfff;
6169
6170         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6171         kvm_apic_write_nodecode(vcpu, offset);
6172         return 1;
6173 }
6174
6175 static int handle_task_switch(struct kvm_vcpu *vcpu)
6176 {
6177         struct vcpu_vmx *vmx = to_vmx(vcpu);
6178         unsigned long exit_qualification;
6179         bool has_error_code = false;
6180         u32 error_code = 0;
6181         u16 tss_selector;
6182         int reason, type, idt_v, idt_index;
6183
6184         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6185         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6186         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6187
6188         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6189
6190         reason = (u32)exit_qualification >> 30;
6191         if (reason == TASK_SWITCH_GATE && idt_v) {
6192                 switch (type) {
6193                 case INTR_TYPE_NMI_INTR:
6194                         vcpu->arch.nmi_injected = false;
6195                         vmx_set_nmi_mask(vcpu, true);
6196                         break;
6197                 case INTR_TYPE_EXT_INTR:
6198                 case INTR_TYPE_SOFT_INTR:
6199                         kvm_clear_interrupt_queue(vcpu);
6200                         break;
6201                 case INTR_TYPE_HARD_EXCEPTION:
6202                         if (vmx->idt_vectoring_info &
6203                             VECTORING_INFO_DELIVER_CODE_MASK) {
6204                                 has_error_code = true;
6205                                 error_code =
6206                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6207                         }
6208                         /* fall through */
6209                 case INTR_TYPE_SOFT_EXCEPTION:
6210                         kvm_clear_exception_queue(vcpu);
6211                         break;
6212                 default:
6213                         break;
6214                 }
6215         }
6216         tss_selector = exit_qualification;
6217
6218         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6219                        type != INTR_TYPE_EXT_INTR &&
6220                        type != INTR_TYPE_NMI_INTR))
6221                 skip_emulated_instruction(vcpu);
6222
6223         if (kvm_task_switch(vcpu, tss_selector,
6224                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6225                             has_error_code, error_code) == EMULATE_FAIL) {
6226                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6227                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6228                 vcpu->run->internal.ndata = 0;
6229                 return 0;
6230         }
6231
6232         /*
6233          * TODO: What about debug traps on tss switch?
6234          *       Are we supposed to inject them and update dr6?
6235          */
6236
6237         return 1;
6238 }
6239
6240 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6241 {
6242         unsigned long exit_qualification;
6243         gpa_t gpa;
6244         u32 error_code;
6245         int gla_validity;
6246
6247         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6248
6249         gla_validity = (exit_qualification >> 7) & 0x3;
6250         if (gla_validity == 0x2) {
6251                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6252                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6253                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6254                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6255                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6256                         (long unsigned int)exit_qualification);
6257                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6258                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6259                 return 0;
6260         }
6261
6262         /*
6263          * EPT violation happened while executing iret from NMI,
6264          * "blocked by NMI" bit has to be set before next VM entry.
6265          * There are errata that may cause this bit to not be set:
6266          * AAK134, BY25.
6267          */
6268         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6269                         cpu_has_virtual_nmis() &&
6270                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6271                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6272
6273         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6274         trace_kvm_page_fault(gpa, exit_qualification);
6275
6276         /* Is it a read fault? */
6277         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6278                      ? PFERR_USER_MASK : 0;
6279         /* Is it a write fault? */
6280         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6281                       ? PFERR_WRITE_MASK : 0;
6282         /* Is it a fetch fault? */
6283         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6284                       ? PFERR_FETCH_MASK : 0;
6285         /* ept page table entry is present? */
6286         error_code |= (exit_qualification &
6287                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6288                         EPT_VIOLATION_EXECUTABLE))
6289                       ? PFERR_PRESENT_MASK : 0;
6290
6291         vcpu->arch.gpa_available = true;
6292         vcpu->arch.exit_qualification = exit_qualification;
6293
6294         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6295 }
6296
6297 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6298 {
6299         int ret;
6300         gpa_t gpa;
6301
6302         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6303         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6304                 trace_kvm_fast_mmio(gpa);
6305                 return kvm_skip_emulated_instruction(vcpu);
6306         }
6307
6308         ret = handle_mmio_page_fault(vcpu, gpa, true);
6309         vcpu->arch.gpa_available = true;
6310         if (likely(ret == RET_MMIO_PF_EMULATE))
6311                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6312                                               EMULATE_DONE;
6313
6314         if (unlikely(ret == RET_MMIO_PF_INVALID))
6315                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6316
6317         if (unlikely(ret == RET_MMIO_PF_RETRY))
6318                 return 1;
6319
6320         /* It is the real ept misconfig */
6321         WARN_ON(1);
6322
6323         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6324         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6325
6326         return 0;
6327 }
6328
6329 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6330 {
6331         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6332                         CPU_BASED_VIRTUAL_NMI_PENDING);
6333         ++vcpu->stat.nmi_window_exits;
6334         kvm_make_request(KVM_REQ_EVENT, vcpu);
6335
6336         return 1;
6337 }
6338
6339 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6340 {
6341         struct vcpu_vmx *vmx = to_vmx(vcpu);
6342         enum emulation_result err = EMULATE_DONE;
6343         int ret = 1;
6344         u32 cpu_exec_ctrl;
6345         bool intr_window_requested;
6346         unsigned count = 130;
6347
6348         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6349         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6350
6351         while (vmx->emulation_required && count-- != 0) {
6352                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6353                         return handle_interrupt_window(&vmx->vcpu);
6354
6355                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6356                         return 1;
6357
6358                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6359
6360                 if (err == EMULATE_USER_EXIT) {
6361                         ++vcpu->stat.mmio_exits;
6362                         ret = 0;
6363                         goto out;
6364                 }
6365
6366                 if (err != EMULATE_DONE) {
6367                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6368                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6369                         vcpu->run->internal.ndata = 0;
6370                         return 0;
6371                 }
6372
6373                 if (vcpu->arch.halt_request) {
6374                         vcpu->arch.halt_request = 0;
6375                         ret = kvm_vcpu_halt(vcpu);
6376                         goto out;
6377                 }
6378
6379                 if (signal_pending(current))
6380                         goto out;
6381                 if (need_resched())
6382                         schedule();
6383         }
6384
6385 out:
6386         return ret;
6387 }
6388
6389 static int __grow_ple_window(int val)
6390 {
6391         if (ple_window_grow < 1)
6392                 return ple_window;
6393
6394         val = min(val, ple_window_actual_max);
6395
6396         if (ple_window_grow < ple_window)
6397                 val *= ple_window_grow;
6398         else
6399                 val += ple_window_grow;
6400
6401         return val;
6402 }
6403
6404 static int __shrink_ple_window(int val, int modifier, int minimum)
6405 {
6406         if (modifier < 1)
6407                 return ple_window;
6408
6409         if (modifier < ple_window)
6410                 val /= modifier;
6411         else
6412                 val -= modifier;
6413
6414         return max(val, minimum);
6415 }
6416
6417 static void grow_ple_window(struct kvm_vcpu *vcpu)
6418 {
6419         struct vcpu_vmx *vmx = to_vmx(vcpu);
6420         int old = vmx->ple_window;
6421
6422         vmx->ple_window = __grow_ple_window(old);
6423
6424         if (vmx->ple_window != old)
6425                 vmx->ple_window_dirty = true;
6426
6427         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6428 }
6429
6430 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6431 {
6432         struct vcpu_vmx *vmx = to_vmx(vcpu);
6433         int old = vmx->ple_window;
6434
6435         vmx->ple_window = __shrink_ple_window(old,
6436                                               ple_window_shrink, ple_window);
6437
6438         if (vmx->ple_window != old)
6439                 vmx->ple_window_dirty = true;
6440
6441         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6442 }
6443
6444 /*
6445  * ple_window_actual_max is computed to be one grow_ple_window() below
6446  * ple_window_max. (See __grow_ple_window for the reason.)
6447  * This prevents overflows, because ple_window_max is int.
6448  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6449  * this process.
6450  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6451  */
6452 static void update_ple_window_actual_max(void)
6453 {
6454         ple_window_actual_max =
6455                         __shrink_ple_window(max(ple_window_max, ple_window),
6456                                             ple_window_grow, INT_MIN);
6457 }
6458
6459 /*
6460  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6461  */
6462 static void wakeup_handler(void)
6463 {
6464         struct kvm_vcpu *vcpu;
6465         int cpu = smp_processor_id();
6466
6467         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6468         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6469                         blocked_vcpu_list) {
6470                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6471
6472                 if (pi_test_on(pi_desc) == 1)
6473                         kvm_vcpu_kick(vcpu);
6474         }
6475         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6476 }
6477
6478 void vmx_enable_tdp(void)
6479 {
6480         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6481                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6482                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6483                 0ull, VMX_EPT_EXECUTABLE_MASK,
6484                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6485                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6486
6487         ept_set_mmio_spte_mask();
6488         kvm_enable_tdp();
6489 }
6490
6491 static __init int hardware_setup(void)
6492 {
6493         int r = -ENOMEM, i, msr;
6494
6495         rdmsrl_safe(MSR_EFER, &host_efer);
6496
6497         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6498                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6499
6500         for (i = 0; i < VMX_BITMAP_NR; i++) {
6501                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6502                 if (!vmx_bitmap[i])
6503                         goto out;
6504         }
6505
6506         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6507         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6508         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6509
6510         /*
6511          * Allow direct access to the PC debug port (it is often used for I/O
6512          * delays, but the vmexits simply slow things down).
6513          */
6514         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6515         clear_bit(0x80, vmx_io_bitmap_a);
6516
6517         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6518
6519         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6520         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6521
6522         if (setup_vmcs_config(&vmcs_config) < 0) {
6523                 r = -EIO;
6524                 goto out;
6525         }
6526
6527         if (boot_cpu_has(X86_FEATURE_NX))
6528                 kvm_enable_efer_bits(EFER_NX);
6529
6530         if (!cpu_has_vmx_vpid())
6531                 enable_vpid = 0;
6532         if (!cpu_has_vmx_shadow_vmcs())
6533                 enable_shadow_vmcs = 0;
6534         if (enable_shadow_vmcs)
6535                 init_vmcs_shadow_fields();
6536
6537         if (!cpu_has_vmx_ept() ||
6538             !cpu_has_vmx_ept_4levels()) {
6539                 enable_ept = 0;
6540                 enable_unrestricted_guest = 0;
6541                 enable_ept_ad_bits = 0;
6542         }
6543
6544         if (!cpu_has_vmx_ept_ad_bits())
6545                 enable_ept_ad_bits = 0;
6546
6547         if (!cpu_has_vmx_unrestricted_guest())
6548                 enable_unrestricted_guest = 0;
6549
6550         if (!cpu_has_vmx_flexpriority())
6551                 flexpriority_enabled = 0;
6552
6553         /*
6554          * set_apic_access_page_addr() is used to reload apic access
6555          * page upon invalidation.  No need to do anything if not
6556          * using the APIC_ACCESS_ADDR VMCS field.
6557          */
6558         if (!flexpriority_enabled)
6559                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6560
6561         if (!cpu_has_vmx_tpr_shadow())
6562                 kvm_x86_ops->update_cr8_intercept = NULL;
6563
6564         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6565                 kvm_disable_largepages();
6566
6567         if (!cpu_has_vmx_ple())
6568                 ple_gap = 0;
6569
6570         if (!cpu_has_vmx_apicv()) {
6571                 enable_apicv = 0;
6572                 kvm_x86_ops->sync_pir_to_irr = NULL;
6573         }
6574
6575         if (cpu_has_vmx_tsc_scaling()) {
6576                 kvm_has_tsc_control = true;
6577                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6578                 kvm_tsc_scaling_ratio_frac_bits = 48;
6579         }
6580
6581         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6582         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6583         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6584         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6585         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6586         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6587         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6588
6589         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6590                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6591         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6592                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6593         memcpy(vmx_msr_bitmap_legacy_x2apic,
6594                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6595         memcpy(vmx_msr_bitmap_longmode_x2apic,
6596                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6597
6598         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6599
6600         for (msr = 0x800; msr <= 0x8ff; msr++) {
6601                 if (msr == 0x839 /* TMCCT */)
6602                         continue;
6603                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6604         }
6605
6606         /*
6607          * TPR reads and writes can be virtualized even if virtual interrupt
6608          * delivery is not in use.
6609          */
6610         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6611         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6612
6613         /* EOI */
6614         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6615         /* SELF-IPI */
6616         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6617
6618         if (enable_ept)
6619                 vmx_enable_tdp();
6620         else
6621                 kvm_disable_tdp();
6622
6623         update_ple_window_actual_max();
6624
6625         /*
6626          * Only enable PML when hardware supports PML feature, and both EPT
6627          * and EPT A/D bit features are enabled -- PML depends on them to work.
6628          */
6629         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6630                 enable_pml = 0;
6631
6632         if (!enable_pml) {
6633                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6634                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6635                 kvm_x86_ops->flush_log_dirty = NULL;
6636                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6637         }
6638
6639         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6640                 u64 vmx_msr;
6641
6642                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6643                 cpu_preemption_timer_multi =
6644                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6645         } else {
6646                 kvm_x86_ops->set_hv_timer = NULL;
6647                 kvm_x86_ops->cancel_hv_timer = NULL;
6648         }
6649
6650         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6651
6652         kvm_mce_cap_supported |= MCG_LMCE_P;
6653
6654         return alloc_kvm_area();
6655
6656 out:
6657         for (i = 0; i < VMX_BITMAP_NR; i++)
6658                 free_page((unsigned long)vmx_bitmap[i]);
6659
6660     return r;
6661 }
6662
6663 static __exit void hardware_unsetup(void)
6664 {
6665         int i;
6666
6667         for (i = 0; i < VMX_BITMAP_NR; i++)
6668                 free_page((unsigned long)vmx_bitmap[i]);
6669
6670         free_kvm_area();
6671 }
6672
6673 /*
6674  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6675  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6676  */
6677 static int handle_pause(struct kvm_vcpu *vcpu)
6678 {
6679         if (ple_gap)
6680                 grow_ple_window(vcpu);
6681
6682         kvm_vcpu_on_spin(vcpu);
6683         return kvm_skip_emulated_instruction(vcpu);
6684 }
6685
6686 static int handle_nop(struct kvm_vcpu *vcpu)
6687 {
6688         return kvm_skip_emulated_instruction(vcpu);
6689 }
6690
6691 static int handle_mwait(struct kvm_vcpu *vcpu)
6692 {
6693         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6694         return handle_nop(vcpu);
6695 }
6696
6697 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6698 {
6699         return 1;
6700 }
6701
6702 static int handle_monitor(struct kvm_vcpu *vcpu)
6703 {
6704         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6705         return handle_nop(vcpu);
6706 }
6707
6708 /*
6709  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6710  * We could reuse a single VMCS for all the L2 guests, but we also want the
6711  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6712  * allows keeping them loaded on the processor, and in the future will allow
6713  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6714  * every entry if they never change.
6715  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6716  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6717  *
6718  * The following functions allocate and free a vmcs02 in this pool.
6719  */
6720
6721 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6722 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6723 {
6724         struct vmcs02_list *item;
6725         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6726                 if (item->vmptr == vmx->nested.current_vmptr) {
6727                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6728                         return &item->vmcs02;
6729                 }
6730
6731         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6732                 /* Recycle the least recently used VMCS. */
6733                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6734                                        struct vmcs02_list, list);
6735                 item->vmptr = vmx->nested.current_vmptr;
6736                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6737                 return &item->vmcs02;
6738         }
6739
6740         /* Create a new VMCS */
6741         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6742         if (!item)
6743                 return NULL;
6744         item->vmcs02.vmcs = alloc_vmcs();
6745         item->vmcs02.shadow_vmcs = NULL;
6746         if (!item->vmcs02.vmcs) {
6747                 kfree(item);
6748                 return NULL;
6749         }
6750         loaded_vmcs_init(&item->vmcs02);
6751         item->vmptr = vmx->nested.current_vmptr;
6752         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6753         vmx->nested.vmcs02_num++;
6754         return &item->vmcs02;
6755 }
6756
6757 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6758 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6759 {
6760         struct vmcs02_list *item;
6761         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6762                 if (item->vmptr == vmptr) {
6763                         free_loaded_vmcs(&item->vmcs02);
6764                         list_del(&item->list);
6765                         kfree(item);
6766                         vmx->nested.vmcs02_num--;
6767                         return;
6768                 }
6769 }
6770
6771 /*
6772  * Free all VMCSs saved for this vcpu, except the one pointed by
6773  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6774  * must be &vmx->vmcs01.
6775  */
6776 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6777 {
6778         struct vmcs02_list *item, *n;
6779
6780         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6781         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6782                 /*
6783                  * Something will leak if the above WARN triggers.  Better than
6784                  * a use-after-free.
6785                  */
6786                 if (vmx->loaded_vmcs == &item->vmcs02)
6787                         continue;
6788
6789                 free_loaded_vmcs(&item->vmcs02);
6790                 list_del(&item->list);
6791                 kfree(item);
6792                 vmx->nested.vmcs02_num--;
6793         }
6794 }
6795
6796 /*
6797  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6798  * set the success or error code of an emulated VMX instruction, as specified
6799  * by Vol 2B, VMX Instruction Reference, "Conventions".
6800  */
6801 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6802 {
6803         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6804                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6805                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6806 }
6807
6808 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6809 {
6810         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6811                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6812                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6813                         | X86_EFLAGS_CF);
6814 }
6815
6816 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6817                                         u32 vm_instruction_error)
6818 {
6819         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6820                 /*
6821                  * failValid writes the error number to the current VMCS, which
6822                  * can't be done there isn't a current VMCS.
6823                  */
6824                 nested_vmx_failInvalid(vcpu);
6825                 return;
6826         }
6827         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6828                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6829                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6830                         | X86_EFLAGS_ZF);
6831         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6832         /*
6833          * We don't need to force a shadow sync because
6834          * VM_INSTRUCTION_ERROR is not shadowed
6835          */
6836 }
6837
6838 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6839 {
6840         /* TODO: not to reset guest simply here. */
6841         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6842         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6843 }
6844
6845 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6846 {
6847         struct vcpu_vmx *vmx =
6848                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6849
6850         vmx->nested.preemption_timer_expired = true;
6851         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6852         kvm_vcpu_kick(&vmx->vcpu);
6853
6854         return HRTIMER_NORESTART;
6855 }
6856
6857 /*
6858  * Decode the memory-address operand of a vmx instruction, as recorded on an
6859  * exit caused by such an instruction (run by a guest hypervisor).
6860  * On success, returns 0. When the operand is invalid, returns 1 and throws
6861  * #UD or #GP.
6862  */
6863 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6864                                  unsigned long exit_qualification,
6865                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6866 {
6867         gva_t off;
6868         bool exn;
6869         struct kvm_segment s;
6870
6871         /*
6872          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6873          * Execution", on an exit, vmx_instruction_info holds most of the
6874          * addressing components of the operand. Only the displacement part
6875          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6876          * For how an actual address is calculated from all these components,
6877          * refer to Vol. 1, "Operand Addressing".
6878          */
6879         int  scaling = vmx_instruction_info & 3;
6880         int  addr_size = (vmx_instruction_info >> 7) & 7;
6881         bool is_reg = vmx_instruction_info & (1u << 10);
6882         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6883         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6884         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6885         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6886         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6887
6888         if (is_reg) {
6889                 kvm_queue_exception(vcpu, UD_VECTOR);
6890                 return 1;
6891         }
6892
6893         /* Addr = segment_base + offset */
6894         /* offset = base + [index * scale] + displacement */
6895         off = exit_qualification; /* holds the displacement */
6896         if (base_is_valid)
6897                 off += kvm_register_read(vcpu, base_reg);
6898         if (index_is_valid)
6899                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6900         vmx_get_segment(vcpu, &s, seg_reg);
6901         *ret = s.base + off;
6902
6903         if (addr_size == 1) /* 32 bit */
6904                 *ret &= 0xffffffff;
6905
6906         /* Checks for #GP/#SS exceptions. */
6907         exn = false;
6908         if (is_long_mode(vcpu)) {
6909                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6910                  * non-canonical form. This is the only check on the memory
6911                  * destination for long mode!
6912                  */
6913                 exn = is_noncanonical_address(*ret);
6914         } else if (is_protmode(vcpu)) {
6915                 /* Protected mode: apply checks for segment validity in the
6916                  * following order:
6917                  * - segment type check (#GP(0) may be thrown)
6918                  * - usability check (#GP(0)/#SS(0))
6919                  * - limit check (#GP(0)/#SS(0))
6920                  */
6921                 if (wr)
6922                         /* #GP(0) if the destination operand is located in a
6923                          * read-only data segment or any code segment.
6924                          */
6925                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6926                 else
6927                         /* #GP(0) if the source operand is located in an
6928                          * execute-only code segment
6929                          */
6930                         exn = ((s.type & 0xa) == 8);
6931                 if (exn) {
6932                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6933                         return 1;
6934                 }
6935                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6936                  */
6937                 exn = (s.unusable != 0);
6938                 /* Protected mode: #GP(0)/#SS(0) if the memory
6939                  * operand is outside the segment limit.
6940                  */
6941                 exn = exn || (off + sizeof(u64) > s.limit);
6942         }
6943         if (exn) {
6944                 kvm_queue_exception_e(vcpu,
6945                                       seg_reg == VCPU_SREG_SS ?
6946                                                 SS_VECTOR : GP_VECTOR,
6947                                       0);
6948                 return 1;
6949         }
6950
6951         return 0;
6952 }
6953
6954 /*
6955  * This function performs the various checks including
6956  * - if it's 4KB aligned
6957  * - No bits beyond the physical address width are set
6958  * - Returns 0 on success or else 1
6959  * (Intel SDM Section 30.3)
6960  */
6961 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6962                                   gpa_t *vmpointer)
6963 {
6964         gva_t gva;
6965         gpa_t vmptr;
6966         struct x86_exception e;
6967         struct page *page;
6968         struct vcpu_vmx *vmx = to_vmx(vcpu);
6969         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6970
6971         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6972                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6973                 return 1;
6974
6975         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6976                                 sizeof(vmptr), &e)) {
6977                 kvm_inject_page_fault(vcpu, &e);
6978                 return 1;
6979         }
6980
6981         switch (exit_reason) {
6982         case EXIT_REASON_VMON:
6983                 /*
6984                  * SDM 3: 24.11.5
6985                  * The first 4 bytes of VMXON region contain the supported
6986                  * VMCS revision identifier
6987                  *
6988                  * Note - IA32_VMX_BASIC[48] will never be 1
6989                  * for the nested case;
6990                  * which replaces physical address width with 32
6991                  *
6992                  */
6993                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6994                         nested_vmx_failInvalid(vcpu);
6995                         return kvm_skip_emulated_instruction(vcpu);
6996                 }
6997
6998                 page = nested_get_page(vcpu, vmptr);
6999                 if (page == NULL) {
7000                         nested_vmx_failInvalid(vcpu);
7001                         return kvm_skip_emulated_instruction(vcpu);
7002                 }
7003                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7004                         kunmap(page);
7005                         nested_release_page_clean(page);
7006                         nested_vmx_failInvalid(vcpu);
7007                         return kvm_skip_emulated_instruction(vcpu);
7008                 }
7009                 kunmap(page);
7010                 nested_release_page_clean(page);
7011                 vmx->nested.vmxon_ptr = vmptr;
7012                 break;
7013         case EXIT_REASON_VMCLEAR:
7014                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7015                         nested_vmx_failValid(vcpu,
7016                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7017                         return kvm_skip_emulated_instruction(vcpu);
7018                 }
7019
7020                 if (vmptr == vmx->nested.vmxon_ptr) {
7021                         nested_vmx_failValid(vcpu,
7022                                              VMXERR_VMCLEAR_VMXON_POINTER);
7023                         return kvm_skip_emulated_instruction(vcpu);
7024                 }
7025                 break;
7026         case EXIT_REASON_VMPTRLD:
7027                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7028                         nested_vmx_failValid(vcpu,
7029                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7030                         return kvm_skip_emulated_instruction(vcpu);
7031                 }
7032
7033                 if (vmptr == vmx->nested.vmxon_ptr) {
7034                         nested_vmx_failValid(vcpu,
7035                                              VMXERR_VMPTRLD_VMXON_POINTER);
7036                         return kvm_skip_emulated_instruction(vcpu);
7037                 }
7038                 break;
7039         default:
7040                 return 1; /* shouldn't happen */
7041         }
7042
7043         if (vmpointer)
7044                 *vmpointer = vmptr;
7045         return 0;
7046 }
7047
7048 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7049 {
7050         struct vcpu_vmx *vmx = to_vmx(vcpu);
7051         struct vmcs *shadow_vmcs;
7052
7053         if (cpu_has_vmx_msr_bitmap()) {
7054                 vmx->nested.msr_bitmap =
7055                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7056                 if (!vmx->nested.msr_bitmap)
7057                         goto out_msr_bitmap;
7058         }
7059
7060         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7061         if (!vmx->nested.cached_vmcs12)
7062                 goto out_cached_vmcs12;
7063
7064         if (enable_shadow_vmcs) {
7065                 shadow_vmcs = alloc_vmcs();
7066                 if (!shadow_vmcs)
7067                         goto out_shadow_vmcs;
7068                 /* mark vmcs as shadow */
7069                 shadow_vmcs->revision_id |= (1u << 31);
7070                 /* init shadow vmcs */
7071                 vmcs_clear(shadow_vmcs);
7072                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7073         }
7074
7075         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7076         vmx->nested.vmcs02_num = 0;
7077
7078         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7079                      HRTIMER_MODE_REL_PINNED);
7080         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7081
7082         vmx->nested.vmxon = true;
7083         return 0;
7084
7085 out_shadow_vmcs:
7086         kfree(vmx->nested.cached_vmcs12);
7087
7088 out_cached_vmcs12:
7089         free_page((unsigned long)vmx->nested.msr_bitmap);
7090
7091 out_msr_bitmap:
7092         return -ENOMEM;
7093 }
7094
7095 /*
7096  * Emulate the VMXON instruction.
7097  * Currently, we just remember that VMX is active, and do not save or even
7098  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7099  * do not currently need to store anything in that guest-allocated memory
7100  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7101  * argument is different from the VMXON pointer (which the spec says they do).
7102  */
7103 static int handle_vmon(struct kvm_vcpu *vcpu)
7104 {
7105         int ret;
7106         struct kvm_segment cs;
7107         struct vcpu_vmx *vmx = to_vmx(vcpu);
7108         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7109                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7110
7111         /* The Intel VMX Instruction Reference lists a bunch of bits that
7112          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7113          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7114          * Otherwise, we should fail with #UD. We test these now:
7115          */
7116         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7117             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7118             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7119                 kvm_queue_exception(vcpu, UD_VECTOR);
7120                 return 1;
7121         }
7122
7123         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7124         if (is_long_mode(vcpu) && !cs.l) {
7125                 kvm_queue_exception(vcpu, UD_VECTOR);
7126                 return 1;
7127         }
7128
7129         if (vmx_get_cpl(vcpu)) {
7130                 kvm_inject_gp(vcpu, 0);
7131                 return 1;
7132         }
7133
7134         if (vmx->nested.vmxon) {
7135                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7136                 return kvm_skip_emulated_instruction(vcpu);
7137         }
7138
7139         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7140                         != VMXON_NEEDED_FEATURES) {
7141                 kvm_inject_gp(vcpu, 0);
7142                 return 1;
7143         }
7144
7145         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7146                 return 1;
7147
7148         ret = enter_vmx_operation(vcpu);
7149         if (ret)
7150                 return ret;
7151
7152         nested_vmx_succeed(vcpu);
7153         return kvm_skip_emulated_instruction(vcpu);
7154 }
7155
7156 /*
7157  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7158  * for running VMX instructions (except VMXON, whose prerequisites are
7159  * slightly different). It also specifies what exception to inject otherwise.
7160  */
7161 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7162 {
7163         struct kvm_segment cs;
7164         struct vcpu_vmx *vmx = to_vmx(vcpu);
7165
7166         if (!vmx->nested.vmxon) {
7167                 kvm_queue_exception(vcpu, UD_VECTOR);
7168                 return 0;
7169         }
7170
7171         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7172         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7173             (is_long_mode(vcpu) && !cs.l)) {
7174                 kvm_queue_exception(vcpu, UD_VECTOR);
7175                 return 0;
7176         }
7177
7178         if (vmx_get_cpl(vcpu)) {
7179                 kvm_inject_gp(vcpu, 0);
7180                 return 0;
7181         }
7182
7183         return 1;
7184 }
7185
7186 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7187 {
7188         if (vmx->nested.current_vmptr == -1ull)
7189                 return;
7190
7191         /* current_vmptr and current_vmcs12 are always set/reset together */
7192         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7193                 return;
7194
7195         if (enable_shadow_vmcs) {
7196                 /* copy to memory all shadowed fields in case
7197                    they were modified */
7198                 copy_shadow_to_vmcs12(vmx);
7199                 vmx->nested.sync_shadow_vmcs = false;
7200                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7201                                 SECONDARY_EXEC_SHADOW_VMCS);
7202                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7203         }
7204         vmx->nested.posted_intr_nv = -1;
7205
7206         /* Flush VMCS12 to guest memory */
7207         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7208                VMCS12_SIZE);
7209
7210         kunmap(vmx->nested.current_vmcs12_page);
7211         nested_release_page(vmx->nested.current_vmcs12_page);
7212         vmx->nested.current_vmptr = -1ull;
7213         vmx->nested.current_vmcs12 = NULL;
7214 }
7215
7216 /*
7217  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7218  * just stops using VMX.
7219  */
7220 static void free_nested(struct vcpu_vmx *vmx)
7221 {
7222         if (!vmx->nested.vmxon)
7223                 return;
7224
7225         vmx->nested.vmxon = false;
7226         free_vpid(vmx->nested.vpid02);
7227         nested_release_vmcs12(vmx);
7228         if (vmx->nested.msr_bitmap) {
7229                 free_page((unsigned long)vmx->nested.msr_bitmap);
7230                 vmx->nested.msr_bitmap = NULL;
7231         }
7232         if (enable_shadow_vmcs) {
7233                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7234                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7235                 vmx->vmcs01.shadow_vmcs = NULL;
7236         }
7237         kfree(vmx->nested.cached_vmcs12);
7238         /* Unpin physical memory we referred to in current vmcs02 */
7239         if (vmx->nested.apic_access_page) {
7240                 nested_release_page(vmx->nested.apic_access_page);
7241                 vmx->nested.apic_access_page = NULL;
7242         }
7243         if (vmx->nested.virtual_apic_page) {
7244                 nested_release_page(vmx->nested.virtual_apic_page);
7245                 vmx->nested.virtual_apic_page = NULL;
7246         }
7247         if (vmx->nested.pi_desc_page) {
7248                 kunmap(vmx->nested.pi_desc_page);
7249                 nested_release_page(vmx->nested.pi_desc_page);
7250                 vmx->nested.pi_desc_page = NULL;
7251                 vmx->nested.pi_desc = NULL;
7252         }
7253
7254         nested_free_all_saved_vmcss(vmx);
7255 }
7256
7257 /* Emulate the VMXOFF instruction */
7258 static int handle_vmoff(struct kvm_vcpu *vcpu)
7259 {
7260         if (!nested_vmx_check_permission(vcpu))
7261                 return 1;
7262         free_nested(to_vmx(vcpu));
7263         nested_vmx_succeed(vcpu);
7264         return kvm_skip_emulated_instruction(vcpu);
7265 }
7266
7267 /* Emulate the VMCLEAR instruction */
7268 static int handle_vmclear(struct kvm_vcpu *vcpu)
7269 {
7270         struct vcpu_vmx *vmx = to_vmx(vcpu);
7271         gpa_t vmptr;
7272         struct vmcs12 *vmcs12;
7273         struct page *page;
7274
7275         if (!nested_vmx_check_permission(vcpu))
7276                 return 1;
7277
7278         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7279                 return 1;
7280
7281         if (vmptr == vmx->nested.current_vmptr)
7282                 nested_release_vmcs12(vmx);
7283
7284         page = nested_get_page(vcpu, vmptr);
7285         if (page == NULL) {
7286                 /*
7287                  * For accurate processor emulation, VMCLEAR beyond available
7288                  * physical memory should do nothing at all. However, it is
7289                  * possible that a nested vmx bug, not a guest hypervisor bug,
7290                  * resulted in this case, so let's shut down before doing any
7291                  * more damage:
7292                  */
7293                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7294                 return 1;
7295         }
7296         vmcs12 = kmap(page);
7297         vmcs12->launch_state = 0;
7298         kunmap(page);
7299         nested_release_page(page);
7300
7301         nested_free_vmcs02(vmx, vmptr);
7302
7303         nested_vmx_succeed(vcpu);
7304         return kvm_skip_emulated_instruction(vcpu);
7305 }
7306
7307 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7308
7309 /* Emulate the VMLAUNCH instruction */
7310 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7311 {
7312         return nested_vmx_run(vcpu, true);
7313 }
7314
7315 /* Emulate the VMRESUME instruction */
7316 static int handle_vmresume(struct kvm_vcpu *vcpu)
7317 {
7318
7319         return nested_vmx_run(vcpu, false);
7320 }
7321
7322 enum vmcs_field_type {
7323         VMCS_FIELD_TYPE_U16 = 0,
7324         VMCS_FIELD_TYPE_U64 = 1,
7325         VMCS_FIELD_TYPE_U32 = 2,
7326         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7327 };
7328
7329 static inline int vmcs_field_type(unsigned long field)
7330 {
7331         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7332                 return VMCS_FIELD_TYPE_U32;
7333         return (field >> 13) & 0x3 ;
7334 }
7335
7336 static inline int vmcs_field_readonly(unsigned long field)
7337 {
7338         return (((field >> 10) & 0x3) == 1);
7339 }
7340
7341 /*
7342  * Read a vmcs12 field. Since these can have varying lengths and we return
7343  * one type, we chose the biggest type (u64) and zero-extend the return value
7344  * to that size. Note that the caller, handle_vmread, might need to use only
7345  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7346  * 64-bit fields are to be returned).
7347  */
7348 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7349                                   unsigned long field, u64 *ret)
7350 {
7351         short offset = vmcs_field_to_offset(field);
7352         char *p;
7353
7354         if (offset < 0)
7355                 return offset;
7356
7357         p = ((char *)(get_vmcs12(vcpu))) + offset;
7358
7359         switch (vmcs_field_type(field)) {
7360         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7361                 *ret = *((natural_width *)p);
7362                 return 0;
7363         case VMCS_FIELD_TYPE_U16:
7364                 *ret = *((u16 *)p);
7365                 return 0;
7366         case VMCS_FIELD_TYPE_U32:
7367                 *ret = *((u32 *)p);
7368                 return 0;
7369         case VMCS_FIELD_TYPE_U64:
7370                 *ret = *((u64 *)p);
7371                 return 0;
7372         default:
7373                 WARN_ON(1);
7374                 return -ENOENT;
7375         }
7376 }
7377
7378
7379 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7380                                    unsigned long field, u64 field_value){
7381         short offset = vmcs_field_to_offset(field);
7382         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7383         if (offset < 0)
7384                 return offset;
7385
7386         switch (vmcs_field_type(field)) {
7387         case VMCS_FIELD_TYPE_U16:
7388                 *(u16 *)p = field_value;
7389                 return 0;
7390         case VMCS_FIELD_TYPE_U32:
7391                 *(u32 *)p = field_value;
7392                 return 0;
7393         case VMCS_FIELD_TYPE_U64:
7394                 *(u64 *)p = field_value;
7395                 return 0;
7396         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7397                 *(natural_width *)p = field_value;
7398                 return 0;
7399         default:
7400                 WARN_ON(1);
7401                 return -ENOENT;
7402         }
7403
7404 }
7405
7406 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7407 {
7408         int i;
7409         unsigned long field;
7410         u64 field_value;
7411         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7412         const unsigned long *fields = shadow_read_write_fields;
7413         const int num_fields = max_shadow_read_write_fields;
7414
7415         preempt_disable();
7416
7417         vmcs_load(shadow_vmcs);
7418
7419         for (i = 0; i < num_fields; i++) {
7420                 field = fields[i];
7421                 switch (vmcs_field_type(field)) {
7422                 case VMCS_FIELD_TYPE_U16:
7423                         field_value = vmcs_read16(field);
7424                         break;
7425                 case VMCS_FIELD_TYPE_U32:
7426                         field_value = vmcs_read32(field);
7427                         break;
7428                 case VMCS_FIELD_TYPE_U64:
7429                         field_value = vmcs_read64(field);
7430                         break;
7431                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7432                         field_value = vmcs_readl(field);
7433                         break;
7434                 default:
7435                         WARN_ON(1);
7436                         continue;
7437                 }
7438                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7439         }
7440
7441         vmcs_clear(shadow_vmcs);
7442         vmcs_load(vmx->loaded_vmcs->vmcs);
7443
7444         preempt_enable();
7445 }
7446
7447 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7448 {
7449         const unsigned long *fields[] = {
7450                 shadow_read_write_fields,
7451                 shadow_read_only_fields
7452         };
7453         const int max_fields[] = {
7454                 max_shadow_read_write_fields,
7455                 max_shadow_read_only_fields
7456         };
7457         int i, q;
7458         unsigned long field;
7459         u64 field_value = 0;
7460         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7461
7462         vmcs_load(shadow_vmcs);
7463
7464         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7465                 for (i = 0; i < max_fields[q]; i++) {
7466                         field = fields[q][i];
7467                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7468
7469                         switch (vmcs_field_type(field)) {
7470                         case VMCS_FIELD_TYPE_U16:
7471                                 vmcs_write16(field, (u16)field_value);
7472                                 break;
7473                         case VMCS_FIELD_TYPE_U32:
7474                                 vmcs_write32(field, (u32)field_value);
7475                                 break;
7476                         case VMCS_FIELD_TYPE_U64:
7477                                 vmcs_write64(field, (u64)field_value);
7478                                 break;
7479                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7480                                 vmcs_writel(field, (long)field_value);
7481                                 break;
7482                         default:
7483                                 WARN_ON(1);
7484                                 break;
7485                         }
7486                 }
7487         }
7488
7489         vmcs_clear(shadow_vmcs);
7490         vmcs_load(vmx->loaded_vmcs->vmcs);
7491 }
7492
7493 /*
7494  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7495  * used before) all generate the same failure when it is missing.
7496  */
7497 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7498 {
7499         struct vcpu_vmx *vmx = to_vmx(vcpu);
7500         if (vmx->nested.current_vmptr == -1ull) {
7501                 nested_vmx_failInvalid(vcpu);
7502                 return 0;
7503         }
7504         return 1;
7505 }
7506
7507 static int handle_vmread(struct kvm_vcpu *vcpu)
7508 {
7509         unsigned long field;
7510         u64 field_value;
7511         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7512         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7513         gva_t gva = 0;
7514
7515         if (!nested_vmx_check_permission(vcpu))
7516                 return 1;
7517
7518         if (!nested_vmx_check_vmcs12(vcpu))
7519                 return kvm_skip_emulated_instruction(vcpu);
7520
7521         /* Decode instruction info and find the field to read */
7522         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7523         /* Read the field, zero-extended to a u64 field_value */
7524         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7525                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7526                 return kvm_skip_emulated_instruction(vcpu);
7527         }
7528         /*
7529          * Now copy part of this value to register or memory, as requested.
7530          * Note that the number of bits actually copied is 32 or 64 depending
7531          * on the guest's mode (32 or 64 bit), not on the given field's length.
7532          */
7533         if (vmx_instruction_info & (1u << 10)) {
7534                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7535                         field_value);
7536         } else {
7537                 if (get_vmx_mem_address(vcpu, exit_qualification,
7538                                 vmx_instruction_info, true, &gva))
7539                         return 1;
7540                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7541                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7542                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7543         }
7544
7545         nested_vmx_succeed(vcpu);
7546         return kvm_skip_emulated_instruction(vcpu);
7547 }
7548
7549
7550 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7551 {
7552         unsigned long field;
7553         gva_t gva;
7554         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7555         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7556         /* The value to write might be 32 or 64 bits, depending on L1's long
7557          * mode, and eventually we need to write that into a field of several
7558          * possible lengths. The code below first zero-extends the value to 64
7559          * bit (field_value), and then copies only the appropriate number of
7560          * bits into the vmcs12 field.
7561          */
7562         u64 field_value = 0;
7563         struct x86_exception e;
7564
7565         if (!nested_vmx_check_permission(vcpu))
7566                 return 1;
7567
7568         if (!nested_vmx_check_vmcs12(vcpu))
7569                 return kvm_skip_emulated_instruction(vcpu);
7570
7571         if (vmx_instruction_info & (1u << 10))
7572                 field_value = kvm_register_readl(vcpu,
7573                         (((vmx_instruction_info) >> 3) & 0xf));
7574         else {
7575                 if (get_vmx_mem_address(vcpu, exit_qualification,
7576                                 vmx_instruction_info, false, &gva))
7577                         return 1;
7578                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7579                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7580                         kvm_inject_page_fault(vcpu, &e);
7581                         return 1;
7582                 }
7583         }
7584
7585
7586         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7587         if (vmcs_field_readonly(field)) {
7588                 nested_vmx_failValid(vcpu,
7589                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7590                 return kvm_skip_emulated_instruction(vcpu);
7591         }
7592
7593         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7594                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7595                 return kvm_skip_emulated_instruction(vcpu);
7596         }
7597
7598         nested_vmx_succeed(vcpu);
7599         return kvm_skip_emulated_instruction(vcpu);
7600 }
7601
7602 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7603 {
7604         vmx->nested.current_vmptr = vmptr;
7605         if (enable_shadow_vmcs) {
7606                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7607                               SECONDARY_EXEC_SHADOW_VMCS);
7608                 vmcs_write64(VMCS_LINK_POINTER,
7609                              __pa(vmx->vmcs01.shadow_vmcs));
7610                 vmx->nested.sync_shadow_vmcs = true;
7611         }
7612 }
7613
7614 /* Emulate the VMPTRLD instruction */
7615 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7616 {
7617         struct vcpu_vmx *vmx = to_vmx(vcpu);
7618         gpa_t vmptr;
7619
7620         if (!nested_vmx_check_permission(vcpu))
7621                 return 1;
7622
7623         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7624                 return 1;
7625
7626         if (vmx->nested.current_vmptr != vmptr) {
7627                 struct vmcs12 *new_vmcs12;
7628                 struct page *page;
7629                 page = nested_get_page(vcpu, vmptr);
7630                 if (page == NULL) {
7631                         nested_vmx_failInvalid(vcpu);
7632                         return kvm_skip_emulated_instruction(vcpu);
7633                 }
7634                 new_vmcs12 = kmap(page);
7635                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7636                         kunmap(page);
7637                         nested_release_page_clean(page);
7638                         nested_vmx_failValid(vcpu,
7639                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7640                         return kvm_skip_emulated_instruction(vcpu);
7641                 }
7642
7643                 nested_release_vmcs12(vmx);
7644                 vmx->nested.current_vmcs12 = new_vmcs12;
7645                 vmx->nested.current_vmcs12_page = page;
7646                 /*
7647                  * Load VMCS12 from guest memory since it is not already
7648                  * cached.
7649                  */
7650                 memcpy(vmx->nested.cached_vmcs12,
7651                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7652                 set_current_vmptr(vmx, vmptr);
7653         }
7654
7655         nested_vmx_succeed(vcpu);
7656         return kvm_skip_emulated_instruction(vcpu);
7657 }
7658
7659 /* Emulate the VMPTRST instruction */
7660 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7661 {
7662         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7663         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7664         gva_t vmcs_gva;
7665         struct x86_exception e;
7666
7667         if (!nested_vmx_check_permission(vcpu))
7668                 return 1;
7669
7670         if (get_vmx_mem_address(vcpu, exit_qualification,
7671                         vmx_instruction_info, true, &vmcs_gva))
7672                 return 1;
7673         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7674         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7675                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7676                                  sizeof(u64), &e)) {
7677                 kvm_inject_page_fault(vcpu, &e);
7678                 return 1;
7679         }
7680         nested_vmx_succeed(vcpu);
7681         return kvm_skip_emulated_instruction(vcpu);
7682 }
7683
7684 /* Emulate the INVEPT instruction */
7685 static int handle_invept(struct kvm_vcpu *vcpu)
7686 {
7687         struct vcpu_vmx *vmx = to_vmx(vcpu);
7688         u32 vmx_instruction_info, types;
7689         unsigned long type;
7690         gva_t gva;
7691         struct x86_exception e;
7692         struct {
7693                 u64 eptp, gpa;
7694         } operand;
7695
7696         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7697               SECONDARY_EXEC_ENABLE_EPT) ||
7698             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7699                 kvm_queue_exception(vcpu, UD_VECTOR);
7700                 return 1;
7701         }
7702
7703         if (!nested_vmx_check_permission(vcpu))
7704                 return 1;
7705
7706         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7707                 kvm_queue_exception(vcpu, UD_VECTOR);
7708                 return 1;
7709         }
7710
7711         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7712         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7713
7714         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7715
7716         if (type >= 32 || !(types & (1 << type))) {
7717                 nested_vmx_failValid(vcpu,
7718                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7719                 return kvm_skip_emulated_instruction(vcpu);
7720         }
7721
7722         /* According to the Intel VMX instruction reference, the memory
7723          * operand is read even if it isn't needed (e.g., for type==global)
7724          */
7725         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7726                         vmx_instruction_info, false, &gva))
7727                 return 1;
7728         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7729                                 sizeof(operand), &e)) {
7730                 kvm_inject_page_fault(vcpu, &e);
7731                 return 1;
7732         }
7733
7734         switch (type) {
7735         case VMX_EPT_EXTENT_GLOBAL:
7736         /*
7737          * TODO: track mappings and invalidate
7738          * single context requests appropriately
7739          */
7740         case VMX_EPT_EXTENT_CONTEXT:
7741                 kvm_mmu_sync_roots(vcpu);
7742                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7743                 nested_vmx_succeed(vcpu);
7744                 break;
7745         default:
7746                 BUG_ON(1);
7747                 break;
7748         }
7749
7750         return kvm_skip_emulated_instruction(vcpu);
7751 }
7752
7753 static int handle_invvpid(struct kvm_vcpu *vcpu)
7754 {
7755         struct vcpu_vmx *vmx = to_vmx(vcpu);
7756         u32 vmx_instruction_info;
7757         unsigned long type, types;
7758         gva_t gva;
7759         struct x86_exception e;
7760         int vpid;
7761
7762         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7763               SECONDARY_EXEC_ENABLE_VPID) ||
7764                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7765                 kvm_queue_exception(vcpu, UD_VECTOR);
7766                 return 1;
7767         }
7768
7769         if (!nested_vmx_check_permission(vcpu))
7770                 return 1;
7771
7772         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7773         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7774
7775         types = (vmx->nested.nested_vmx_vpid_caps &
7776                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7777
7778         if (type >= 32 || !(types & (1 << type))) {
7779                 nested_vmx_failValid(vcpu,
7780                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7781                 return kvm_skip_emulated_instruction(vcpu);
7782         }
7783
7784         /* according to the intel vmx instruction reference, the memory
7785          * operand is read even if it isn't needed (e.g., for type==global)
7786          */
7787         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7788                         vmx_instruction_info, false, &gva))
7789                 return 1;
7790         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7791                                 sizeof(u32), &e)) {
7792                 kvm_inject_page_fault(vcpu, &e);
7793                 return 1;
7794         }
7795
7796         switch (type) {
7797         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7798         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7799         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7800                 if (!vpid) {
7801                         nested_vmx_failValid(vcpu,
7802                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7803                         return kvm_skip_emulated_instruction(vcpu);
7804                 }
7805                 break;
7806         case VMX_VPID_EXTENT_ALL_CONTEXT:
7807                 break;
7808         default:
7809                 WARN_ON_ONCE(1);
7810                 return kvm_skip_emulated_instruction(vcpu);
7811         }
7812
7813         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7814         nested_vmx_succeed(vcpu);
7815
7816         return kvm_skip_emulated_instruction(vcpu);
7817 }
7818
7819 static int handle_pml_full(struct kvm_vcpu *vcpu)
7820 {
7821         unsigned long exit_qualification;
7822
7823         trace_kvm_pml_full(vcpu->vcpu_id);
7824
7825         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7826
7827         /*
7828          * PML buffer FULL happened while executing iret from NMI,
7829          * "blocked by NMI" bit has to be set before next VM entry.
7830          */
7831         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7832                         cpu_has_virtual_nmis() &&
7833                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7834                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7835                                 GUEST_INTR_STATE_NMI);
7836
7837         /*
7838          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7839          * here.., and there's no userspace involvement needed for PML.
7840          */
7841         return 1;
7842 }
7843
7844 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7845 {
7846         kvm_lapic_expired_hv_timer(vcpu);
7847         return 1;
7848 }
7849
7850 /*
7851  * The exit handlers return 1 if the exit was handled fully and guest execution
7852  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7853  * to be done to userspace and return 0.
7854  */
7855 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7856         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7857         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7858         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7859         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7860         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7861         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7862         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7863         [EXIT_REASON_CPUID]                   = handle_cpuid,
7864         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7865         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7866         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7867         [EXIT_REASON_HLT]                     = handle_halt,
7868         [EXIT_REASON_INVD]                    = handle_invd,
7869         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7870         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7871         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7872         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7873         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7874         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7875         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7876         [EXIT_REASON_VMREAD]                  = handle_vmread,
7877         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7878         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7879         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7880         [EXIT_REASON_VMON]                    = handle_vmon,
7881         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7882         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7883         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7884         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7885         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7886         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7887         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7888         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7889         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7890         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7891         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7892         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7893         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7894         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7895         [EXIT_REASON_INVEPT]                  = handle_invept,
7896         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7897         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7898         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7899         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7900         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7901 };
7902
7903 static const int kvm_vmx_max_exit_handlers =
7904         ARRAY_SIZE(kvm_vmx_exit_handlers);
7905
7906 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7907                                        struct vmcs12 *vmcs12)
7908 {
7909         unsigned long exit_qualification;
7910         gpa_t bitmap, last_bitmap;
7911         unsigned int port;
7912         int size;
7913         u8 b;
7914
7915         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7916                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7917
7918         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7919
7920         port = exit_qualification >> 16;
7921         size = (exit_qualification & 7) + 1;
7922
7923         last_bitmap = (gpa_t)-1;
7924         b = -1;
7925
7926         while (size > 0) {
7927                 if (port < 0x8000)
7928                         bitmap = vmcs12->io_bitmap_a;
7929                 else if (port < 0x10000)
7930                         bitmap = vmcs12->io_bitmap_b;
7931                 else
7932                         return true;
7933                 bitmap += (port & 0x7fff) / 8;
7934
7935                 if (last_bitmap != bitmap)
7936                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7937                                 return true;
7938                 if (b & (1 << (port & 7)))
7939                         return true;
7940
7941                 port++;
7942                 size--;
7943                 last_bitmap = bitmap;
7944         }
7945
7946         return false;
7947 }
7948
7949 /*
7950  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7951  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7952  * disinterest in the current event (read or write a specific MSR) by using an
7953  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7954  */
7955 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7956         struct vmcs12 *vmcs12, u32 exit_reason)
7957 {
7958         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7959         gpa_t bitmap;
7960
7961         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7962                 return true;
7963
7964         /*
7965          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7966          * for the four combinations of read/write and low/high MSR numbers.
7967          * First we need to figure out which of the four to use:
7968          */
7969         bitmap = vmcs12->msr_bitmap;
7970         if (exit_reason == EXIT_REASON_MSR_WRITE)
7971                 bitmap += 2048;
7972         if (msr_index >= 0xc0000000) {
7973                 msr_index -= 0xc0000000;
7974                 bitmap += 1024;
7975         }
7976
7977         /* Then read the msr_index'th bit from this bitmap: */
7978         if (msr_index < 1024*8) {
7979                 unsigned char b;
7980                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7981                         return true;
7982                 return 1 & (b >> (msr_index & 7));
7983         } else
7984                 return true; /* let L1 handle the wrong parameter */
7985 }
7986
7987 /*
7988  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7989  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7990  * intercept (via guest_host_mask etc.) the current event.
7991  */
7992 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7993         struct vmcs12 *vmcs12)
7994 {
7995         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7996         int cr = exit_qualification & 15;
7997         int reg = (exit_qualification >> 8) & 15;
7998         unsigned long val = kvm_register_readl(vcpu, reg);
7999
8000         switch ((exit_qualification >> 4) & 3) {
8001         case 0: /* mov to cr */
8002                 switch (cr) {
8003                 case 0:
8004                         if (vmcs12->cr0_guest_host_mask &
8005                             (val ^ vmcs12->cr0_read_shadow))
8006                                 return true;
8007                         break;
8008                 case 3:
8009                         if ((vmcs12->cr3_target_count >= 1 &&
8010                                         vmcs12->cr3_target_value0 == val) ||
8011                                 (vmcs12->cr3_target_count >= 2 &&
8012                                         vmcs12->cr3_target_value1 == val) ||
8013                                 (vmcs12->cr3_target_count >= 3 &&
8014                                         vmcs12->cr3_target_value2 == val) ||
8015                                 (vmcs12->cr3_target_count >= 4 &&
8016                                         vmcs12->cr3_target_value3 == val))
8017                                 return false;
8018                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8019                                 return true;
8020                         break;
8021                 case 4:
8022                         if (vmcs12->cr4_guest_host_mask &
8023                             (vmcs12->cr4_read_shadow ^ val))
8024                                 return true;
8025                         break;
8026                 case 8:
8027                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8028                                 return true;
8029                         break;
8030                 }
8031                 break;
8032         case 2: /* clts */
8033                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8034                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8035                         return true;
8036                 break;
8037         case 1: /* mov from cr */
8038                 switch (cr) {
8039                 case 3:
8040                         if (vmcs12->cpu_based_vm_exec_control &
8041                             CPU_BASED_CR3_STORE_EXITING)
8042                                 return true;
8043                         break;
8044                 case 8:
8045                         if (vmcs12->cpu_based_vm_exec_control &
8046                             CPU_BASED_CR8_STORE_EXITING)
8047                                 return true;
8048                         break;
8049                 }
8050                 break;
8051         case 3: /* lmsw */
8052                 /*
8053                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8054                  * cr0. Other attempted changes are ignored, with no exit.
8055                  */
8056                 if (vmcs12->cr0_guest_host_mask & 0xe &
8057                     (val ^ vmcs12->cr0_read_shadow))
8058                         return true;
8059                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8060                     !(vmcs12->cr0_read_shadow & 0x1) &&
8061                     (val & 0x1))
8062                         return true;
8063                 break;
8064         }
8065         return false;
8066 }
8067
8068 /*
8069  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8070  * should handle it ourselves in L0 (and then continue L2). Only call this
8071  * when in is_guest_mode (L2).
8072  */
8073 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8074 {
8075         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8076         struct vcpu_vmx *vmx = to_vmx(vcpu);
8077         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8078         u32 exit_reason = vmx->exit_reason;
8079
8080         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8081                                 vmcs_readl(EXIT_QUALIFICATION),
8082                                 vmx->idt_vectoring_info,
8083                                 intr_info,
8084                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8085                                 KVM_ISA_VMX);
8086
8087         if (vmx->nested.nested_run_pending)
8088                 return false;
8089
8090         if (unlikely(vmx->fail)) {
8091                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8092                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8093                 return true;
8094         }
8095
8096         switch (exit_reason) {
8097         case EXIT_REASON_EXCEPTION_NMI:
8098                 if (is_nmi(intr_info))
8099                         return false;
8100                 else if (is_page_fault(intr_info))
8101                         return enable_ept;
8102                 else if (is_no_device(intr_info) &&
8103                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8104                         return false;
8105                 else if (is_debug(intr_info) &&
8106                          vcpu->guest_debug &
8107                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8108                         return false;
8109                 else if (is_breakpoint(intr_info) &&
8110                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8111                         return false;
8112                 return vmcs12->exception_bitmap &
8113                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8114         case EXIT_REASON_EXTERNAL_INTERRUPT:
8115                 return false;
8116         case EXIT_REASON_TRIPLE_FAULT:
8117                 return true;
8118         case EXIT_REASON_PENDING_INTERRUPT:
8119                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8120         case EXIT_REASON_NMI_WINDOW:
8121                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8122         case EXIT_REASON_TASK_SWITCH:
8123                 return true;
8124         case EXIT_REASON_CPUID:
8125                 return true;
8126         case EXIT_REASON_HLT:
8127                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8128         case EXIT_REASON_INVD:
8129                 return true;
8130         case EXIT_REASON_INVLPG:
8131                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8132         case EXIT_REASON_RDPMC:
8133                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8134         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8135                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8136         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8137         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8138         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8139         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8140         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8141         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8142                 /*
8143                  * VMX instructions trap unconditionally. This allows L1 to
8144                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8145                  */
8146                 return true;
8147         case EXIT_REASON_CR_ACCESS:
8148                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8149         case EXIT_REASON_DR_ACCESS:
8150                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8151         case EXIT_REASON_IO_INSTRUCTION:
8152                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8153         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8154                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8155         case EXIT_REASON_MSR_READ:
8156         case EXIT_REASON_MSR_WRITE:
8157                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8158         case EXIT_REASON_INVALID_STATE:
8159                 return true;
8160         case EXIT_REASON_MWAIT_INSTRUCTION:
8161                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8162         case EXIT_REASON_MONITOR_TRAP_FLAG:
8163                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8164         case EXIT_REASON_MONITOR_INSTRUCTION:
8165                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8166         case EXIT_REASON_PAUSE_INSTRUCTION:
8167                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8168                         nested_cpu_has2(vmcs12,
8169                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8170         case EXIT_REASON_MCE_DURING_VMENTRY:
8171                 return false;
8172         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8173                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8174         case EXIT_REASON_APIC_ACCESS:
8175                 return nested_cpu_has2(vmcs12,
8176                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8177         case EXIT_REASON_APIC_WRITE:
8178         case EXIT_REASON_EOI_INDUCED:
8179                 /* apic_write and eoi_induced should exit unconditionally. */
8180                 return true;
8181         case EXIT_REASON_EPT_VIOLATION:
8182                 /*
8183                  * L0 always deals with the EPT violation. If nested EPT is
8184                  * used, and the nested mmu code discovers that the address is
8185                  * missing in the guest EPT table (EPT12), the EPT violation
8186                  * will be injected with nested_ept_inject_page_fault()
8187                  */
8188                 return false;
8189         case EXIT_REASON_EPT_MISCONFIG:
8190                 /*
8191                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8192                  * table (shadow on EPT) or a merged EPT table that L0 built
8193                  * (EPT on EPT). So any problems with the structure of the
8194                  * table is L0's fault.
8195                  */
8196                 return false;
8197         case EXIT_REASON_WBINVD:
8198                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8199         case EXIT_REASON_XSETBV:
8200                 return true;
8201         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8202                 /*
8203                  * This should never happen, since it is not possible to
8204                  * set XSS to a non-zero value---neither in L1 nor in L2.
8205                  * If if it were, XSS would have to be checked against
8206                  * the XSS exit bitmap in vmcs12.
8207                  */
8208                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8209         case EXIT_REASON_PREEMPTION_TIMER:
8210                 return false;
8211         default:
8212                 return true;
8213         }
8214 }
8215
8216 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8217 {
8218         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8219         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8220 }
8221
8222 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8223 {
8224         if (vmx->pml_pg) {
8225                 __free_page(vmx->pml_pg);
8226                 vmx->pml_pg = NULL;
8227         }
8228 }
8229
8230 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8231 {
8232         struct vcpu_vmx *vmx = to_vmx(vcpu);
8233         u64 *pml_buf;
8234         u16 pml_idx;
8235
8236         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8237
8238         /* Do nothing if PML buffer is empty */
8239         if (pml_idx == (PML_ENTITY_NUM - 1))
8240                 return;
8241
8242         /* PML index always points to next available PML buffer entity */
8243         if (pml_idx >= PML_ENTITY_NUM)
8244                 pml_idx = 0;
8245         else
8246                 pml_idx++;
8247
8248         pml_buf = page_address(vmx->pml_pg);
8249         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8250                 u64 gpa;
8251
8252                 gpa = pml_buf[pml_idx];
8253                 WARN_ON(gpa & (PAGE_SIZE - 1));
8254                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8255         }
8256
8257         /* reset PML index */
8258         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8259 }
8260
8261 /*
8262  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8263  * Called before reporting dirty_bitmap to userspace.
8264  */
8265 static void kvm_flush_pml_buffers(struct kvm *kvm)
8266 {
8267         int i;
8268         struct kvm_vcpu *vcpu;
8269         /*
8270          * We only need to kick vcpu out of guest mode here, as PML buffer
8271          * is flushed at beginning of all VMEXITs, and it's obvious that only
8272          * vcpus running in guest are possible to have unflushed GPAs in PML
8273          * buffer.
8274          */
8275         kvm_for_each_vcpu(i, vcpu, kvm)
8276                 kvm_vcpu_kick(vcpu);
8277 }
8278
8279 static void vmx_dump_sel(char *name, uint32_t sel)
8280 {
8281         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8282                name, vmcs_read32(sel),
8283                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8284                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8285                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8286 }
8287
8288 static void vmx_dump_dtsel(char *name, uint32_t limit)
8289 {
8290         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8291                name, vmcs_read32(limit),
8292                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8293 }
8294
8295 static void dump_vmcs(void)
8296 {
8297         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8298         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8299         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8300         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8301         u32 secondary_exec_control = 0;
8302         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8303         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8304         int i, n;
8305
8306         if (cpu_has_secondary_exec_ctrls())
8307                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8308
8309         pr_err("*** Guest State ***\n");
8310         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8311                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8312                vmcs_readl(CR0_GUEST_HOST_MASK));
8313         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8314                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8315         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8316         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8317             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8318         {
8319                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8320                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8321                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8322                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8323         }
8324         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8325                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8326         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8327                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8328         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8329                vmcs_readl(GUEST_SYSENTER_ESP),
8330                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8331         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8332         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8333         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8334         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8335         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8336         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8337         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8338         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8339         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8340         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8341         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8342             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8343                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8344                        efer, vmcs_read64(GUEST_IA32_PAT));
8345         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8346                vmcs_read64(GUEST_IA32_DEBUGCTL),
8347                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8348         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8349                 pr_err("PerfGlobCtl = 0x%016llx\n",
8350                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8351         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8352                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8353         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8354                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8355                vmcs_read32(GUEST_ACTIVITY_STATE));
8356         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8357                 pr_err("InterruptStatus = %04x\n",
8358                        vmcs_read16(GUEST_INTR_STATUS));
8359
8360         pr_err("*** Host State ***\n");
8361         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8362                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8363         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8364                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8365                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8366                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8367                vmcs_read16(HOST_TR_SELECTOR));
8368         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8369                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8370                vmcs_readl(HOST_TR_BASE));
8371         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8372                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8373         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8374                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8375                vmcs_readl(HOST_CR4));
8376         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8377                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8378                vmcs_read32(HOST_IA32_SYSENTER_CS),
8379                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8380         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8381                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8382                        vmcs_read64(HOST_IA32_EFER),
8383                        vmcs_read64(HOST_IA32_PAT));
8384         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8385                 pr_err("PerfGlobCtl = 0x%016llx\n",
8386                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8387
8388         pr_err("*** Control State ***\n");
8389         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8390                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8391         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8392         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8393                vmcs_read32(EXCEPTION_BITMAP),
8394                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8395                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8396         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8397                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8398                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8399                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8400         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8401                vmcs_read32(VM_EXIT_INTR_INFO),
8402                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8403                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8404         pr_err("        reason=%08x qualification=%016lx\n",
8405                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8406         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8407                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8408                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8409         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8410         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8411                 pr_err("TSC Multiplier = 0x%016llx\n",
8412                        vmcs_read64(TSC_MULTIPLIER));
8413         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8414                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8415         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8416                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8417         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8418                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8419         n = vmcs_read32(CR3_TARGET_COUNT);
8420         for (i = 0; i + 1 < n; i += 4)
8421                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8422                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8423                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8424         if (i < n)
8425                 pr_err("CR3 target%u=%016lx\n",
8426                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8427         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8428                 pr_err("PLE Gap=%08x Window=%08x\n",
8429                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8430         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8431                 pr_err("Virtual processor ID = 0x%04x\n",
8432                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8433 }
8434
8435 /*
8436  * The guest has exited.  See if we can fix it or if we need userspace
8437  * assistance.
8438  */
8439 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8440 {
8441         struct vcpu_vmx *vmx = to_vmx(vcpu);
8442         u32 exit_reason = vmx->exit_reason;
8443         u32 vectoring_info = vmx->idt_vectoring_info;
8444
8445         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8446         vcpu->arch.gpa_available = false;
8447
8448         /*
8449          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8450          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8451          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8452          * mode as if vcpus is in root mode, the PML buffer must has been
8453          * flushed already.
8454          */
8455         if (enable_pml)
8456                 vmx_flush_pml_buffer(vcpu);
8457
8458         /* If guest state is invalid, start emulating */
8459         if (vmx->emulation_required)
8460                 return handle_invalid_guest_state(vcpu);
8461
8462         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8463                 nested_vmx_vmexit(vcpu, exit_reason,
8464                                   vmcs_read32(VM_EXIT_INTR_INFO),
8465                                   vmcs_readl(EXIT_QUALIFICATION));
8466                 return 1;
8467         }
8468
8469         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8470                 dump_vmcs();
8471                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8472                 vcpu->run->fail_entry.hardware_entry_failure_reason
8473                         = exit_reason;
8474                 return 0;
8475         }
8476
8477         if (unlikely(vmx->fail)) {
8478                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8479                 vcpu->run->fail_entry.hardware_entry_failure_reason
8480                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8481                 return 0;
8482         }
8483
8484         /*
8485          * Note:
8486          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8487          * delivery event since it indicates guest is accessing MMIO.
8488          * The vm-exit can be triggered again after return to guest that
8489          * will cause infinite loop.
8490          */
8491         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8492                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8493                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8494                         exit_reason != EXIT_REASON_PML_FULL &&
8495                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8496                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8497                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8498                 vcpu->run->internal.ndata = 2;
8499                 vcpu->run->internal.data[0] = vectoring_info;
8500                 vcpu->run->internal.data[1] = exit_reason;
8501                 return 0;
8502         }
8503
8504         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8505             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8506                                         get_vmcs12(vcpu))))) {
8507                 if (vmx_interrupt_allowed(vcpu)) {
8508                         vmx->soft_vnmi_blocked = 0;
8509                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8510                            vcpu->arch.nmi_pending) {
8511                         /*
8512                          * This CPU don't support us in finding the end of an
8513                          * NMI-blocked window if the guest runs with IRQs
8514                          * disabled. So we pull the trigger after 1 s of
8515                          * futile waiting, but inform the user about this.
8516                          */
8517                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8518                                "state on VCPU %d after 1 s timeout\n",
8519                                __func__, vcpu->vcpu_id);
8520                         vmx->soft_vnmi_blocked = 0;
8521                 }
8522         }
8523
8524         if (exit_reason < kvm_vmx_max_exit_handlers
8525             && kvm_vmx_exit_handlers[exit_reason])
8526                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8527         else {
8528                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8529                 kvm_queue_exception(vcpu, UD_VECTOR);
8530                 return 1;
8531         }
8532 }
8533
8534 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8535 {
8536         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8537
8538         if (is_guest_mode(vcpu) &&
8539                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8540                 return;
8541
8542         if (irr == -1 || tpr < irr) {
8543                 vmcs_write32(TPR_THRESHOLD, 0);
8544                 return;
8545         }
8546
8547         vmcs_write32(TPR_THRESHOLD, irr);
8548 }
8549
8550 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8551 {
8552         u32 sec_exec_control;
8553
8554         /* Postpone execution until vmcs01 is the current VMCS. */
8555         if (is_guest_mode(vcpu)) {
8556                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8557                 return;
8558         }
8559
8560         if (!cpu_has_vmx_virtualize_x2apic_mode())
8561                 return;
8562
8563         if (!cpu_need_tpr_shadow(vcpu))
8564                 return;
8565
8566         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8567
8568         if (set) {
8569                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8570                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8571         } else {
8572                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8573                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8574         }
8575         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8576
8577         vmx_set_msr_bitmap(vcpu);
8578 }
8579
8580 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8581 {
8582         struct vcpu_vmx *vmx = to_vmx(vcpu);
8583
8584         /*
8585          * Currently we do not handle the nested case where L2 has an
8586          * APIC access page of its own; that page is still pinned.
8587          * Hence, we skip the case where the VCPU is in guest mode _and_
8588          * L1 prepared an APIC access page for L2.
8589          *
8590          * For the case where L1 and L2 share the same APIC access page
8591          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8592          * in the vmcs12), this function will only update either the vmcs01
8593          * or the vmcs02.  If the former, the vmcs02 will be updated by
8594          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8595          * the next L2->L1 exit.
8596          */
8597         if (!is_guest_mode(vcpu) ||
8598             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8599                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8600                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8601 }
8602
8603 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8604 {
8605         u16 status;
8606         u8 old;
8607
8608         if (max_isr == -1)
8609                 max_isr = 0;
8610
8611         status = vmcs_read16(GUEST_INTR_STATUS);
8612         old = status >> 8;
8613         if (max_isr != old) {
8614                 status &= 0xff;
8615                 status |= max_isr << 8;
8616                 vmcs_write16(GUEST_INTR_STATUS, status);
8617         }
8618 }
8619
8620 static void vmx_set_rvi(int vector)
8621 {
8622         u16 status;
8623         u8 old;
8624
8625         if (vector == -1)
8626                 vector = 0;
8627
8628         status = vmcs_read16(GUEST_INTR_STATUS);
8629         old = (u8)status & 0xff;
8630         if ((u8)vector != old) {
8631                 status &= ~0xff;
8632                 status |= (u8)vector;
8633                 vmcs_write16(GUEST_INTR_STATUS, status);
8634         }
8635 }
8636
8637 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8638 {
8639         if (!is_guest_mode(vcpu)) {
8640                 vmx_set_rvi(max_irr);
8641                 return;
8642         }
8643
8644         if (max_irr == -1)
8645                 return;
8646
8647         /*
8648          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8649          * handles it.
8650          */
8651         if (nested_exit_on_intr(vcpu))
8652                 return;
8653
8654         /*
8655          * Else, fall back to pre-APICv interrupt injection since L2
8656          * is run without virtual interrupt delivery.
8657          */
8658         if (!kvm_event_needs_reinjection(vcpu) &&
8659             vmx_interrupt_allowed(vcpu)) {
8660                 kvm_queue_interrupt(vcpu, max_irr, false);
8661                 vmx_inject_irq(vcpu);
8662         }
8663 }
8664
8665 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8666 {
8667         struct vcpu_vmx *vmx = to_vmx(vcpu);
8668         int max_irr;
8669
8670         WARN_ON(!vcpu->arch.apicv_active);
8671         if (pi_test_on(&vmx->pi_desc)) {
8672                 pi_clear_on(&vmx->pi_desc);
8673                 /*
8674                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8675                  * But on x86 this is just a compiler barrier anyway.
8676                  */
8677                 smp_mb__after_atomic();
8678                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8679         } else {
8680                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8681         }
8682         vmx_hwapic_irr_update(vcpu, max_irr);
8683         return max_irr;
8684 }
8685
8686 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8687 {
8688         if (!kvm_vcpu_apicv_active(vcpu))
8689                 return;
8690
8691         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8692         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8693         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8694         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8695 }
8696
8697 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8698 {
8699         struct vcpu_vmx *vmx = to_vmx(vcpu);
8700
8701         pi_clear_on(&vmx->pi_desc);
8702         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8703 }
8704
8705 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8706 {
8707         u32 exit_intr_info;
8708
8709         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8710               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8711                 return;
8712
8713         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8714         exit_intr_info = vmx->exit_intr_info;
8715
8716         /* Handle machine checks before interrupts are enabled */
8717         if (is_machine_check(exit_intr_info))
8718                 kvm_machine_check();
8719
8720         /* We need to handle NMIs before interrupts are enabled */
8721         if (is_nmi(exit_intr_info)) {
8722                 kvm_before_handle_nmi(&vmx->vcpu);
8723                 asm("int $2");
8724                 kvm_after_handle_nmi(&vmx->vcpu);
8725         }
8726 }
8727
8728 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8729 {
8730         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8731         register void *__sp asm(_ASM_SP);
8732
8733         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8734                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8735                 unsigned int vector;
8736                 unsigned long entry;
8737                 gate_desc *desc;
8738                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8739 #ifdef CONFIG_X86_64
8740                 unsigned long tmp;
8741 #endif
8742
8743                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8744                 desc = (gate_desc *)vmx->host_idt_base + vector;
8745                 entry = gate_offset(*desc);
8746                 asm volatile(
8747 #ifdef CONFIG_X86_64
8748                         "mov %%" _ASM_SP ", %[sp]\n\t"
8749                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8750                         "push $%c[ss]\n\t"
8751                         "push %[sp]\n\t"
8752 #endif
8753                         "pushf\n\t"
8754                         __ASM_SIZE(push) " $%c[cs]\n\t"
8755                         "call *%[entry]\n\t"
8756                         :
8757 #ifdef CONFIG_X86_64
8758                         [sp]"=&r"(tmp),
8759 #endif
8760                         "+r"(__sp)
8761                         :
8762                         [entry]"r"(entry),
8763                         [ss]"i"(__KERNEL_DS),
8764                         [cs]"i"(__KERNEL_CS)
8765                         );
8766         }
8767 }
8768
8769 static bool vmx_has_high_real_mode_segbase(void)
8770 {
8771         return enable_unrestricted_guest || emulate_invalid_guest_state;
8772 }
8773
8774 static bool vmx_mpx_supported(void)
8775 {
8776         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8777                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8778 }
8779
8780 static bool vmx_xsaves_supported(void)
8781 {
8782         return vmcs_config.cpu_based_2nd_exec_ctrl &
8783                 SECONDARY_EXEC_XSAVES;
8784 }
8785
8786 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8787 {
8788         u32 exit_intr_info;
8789         bool unblock_nmi;
8790         u8 vector;
8791         bool idtv_info_valid;
8792
8793         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8794
8795         if (cpu_has_virtual_nmis()) {
8796                 if (vmx->nmi_known_unmasked)
8797                         return;
8798                 /*
8799                  * Can't use vmx->exit_intr_info since we're not sure what
8800                  * the exit reason is.
8801                  */
8802                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8803                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8804                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8805                 /*
8806                  * SDM 3: 27.7.1.2 (September 2008)
8807                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8808                  * a guest IRET fault.
8809                  * SDM 3: 23.2.2 (September 2008)
8810                  * Bit 12 is undefined in any of the following cases:
8811                  *  If the VM exit sets the valid bit in the IDT-vectoring
8812                  *   information field.
8813                  *  If the VM exit is due to a double fault.
8814                  */
8815                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8816                     vector != DF_VECTOR && !idtv_info_valid)
8817                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8818                                       GUEST_INTR_STATE_NMI);
8819                 else
8820                         vmx->nmi_known_unmasked =
8821                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8822                                   & GUEST_INTR_STATE_NMI);
8823         } else if (unlikely(vmx->soft_vnmi_blocked))
8824                 vmx->vnmi_blocked_time +=
8825                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8826 }
8827
8828 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8829                                       u32 idt_vectoring_info,
8830                                       int instr_len_field,
8831                                       int error_code_field)
8832 {
8833         u8 vector;
8834         int type;
8835         bool idtv_info_valid;
8836
8837         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8838
8839         vcpu->arch.nmi_injected = false;
8840         kvm_clear_exception_queue(vcpu);
8841         kvm_clear_interrupt_queue(vcpu);
8842
8843         if (!idtv_info_valid)
8844                 return;
8845
8846         kvm_make_request(KVM_REQ_EVENT, vcpu);
8847
8848         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8849         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8850
8851         switch (type) {
8852         case INTR_TYPE_NMI_INTR:
8853                 vcpu->arch.nmi_injected = true;
8854                 /*
8855                  * SDM 3: 27.7.1.2 (September 2008)
8856                  * Clear bit "block by NMI" before VM entry if a NMI
8857                  * delivery faulted.
8858                  */
8859                 vmx_set_nmi_mask(vcpu, false);
8860                 break;
8861         case INTR_TYPE_SOFT_EXCEPTION:
8862                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8863                 /* fall through */
8864         case INTR_TYPE_HARD_EXCEPTION:
8865                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8866                         u32 err = vmcs_read32(error_code_field);
8867                         kvm_requeue_exception_e(vcpu, vector, err);
8868                 } else
8869                         kvm_requeue_exception(vcpu, vector);
8870                 break;
8871         case INTR_TYPE_SOFT_INTR:
8872                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8873                 /* fall through */
8874         case INTR_TYPE_EXT_INTR:
8875                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8876                 break;
8877         default:
8878                 break;
8879         }
8880 }
8881
8882 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8883 {
8884         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8885                                   VM_EXIT_INSTRUCTION_LEN,
8886                                   IDT_VECTORING_ERROR_CODE);
8887 }
8888
8889 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8890 {
8891         __vmx_complete_interrupts(vcpu,
8892                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8893                                   VM_ENTRY_INSTRUCTION_LEN,
8894                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8895
8896         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8897 }
8898
8899 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8900 {
8901         int i, nr_msrs;
8902         struct perf_guest_switch_msr *msrs;
8903
8904         msrs = perf_guest_get_msrs(&nr_msrs);
8905
8906         if (!msrs)
8907                 return;
8908
8909         for (i = 0; i < nr_msrs; i++)
8910                 if (msrs[i].host == msrs[i].guest)
8911                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8912                 else
8913                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8914                                         msrs[i].host);
8915 }
8916
8917 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8918 {
8919         struct vcpu_vmx *vmx = to_vmx(vcpu);
8920         u64 tscl;
8921         u32 delta_tsc;
8922
8923         if (vmx->hv_deadline_tsc == -1)
8924                 return;
8925
8926         tscl = rdtsc();
8927         if (vmx->hv_deadline_tsc > tscl)
8928                 /* sure to be 32 bit only because checked on set_hv_timer */
8929                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8930                         cpu_preemption_timer_multi);
8931         else
8932                 delta_tsc = 0;
8933
8934         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8935 }
8936
8937 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8938 {
8939         struct vcpu_vmx *vmx = to_vmx(vcpu);
8940         unsigned long debugctlmsr, cr4;
8941
8942         /* Record the guest's net vcpu time for enforced NMI injections. */
8943         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8944                 vmx->entry_time = ktime_get();
8945
8946         /* Don't enter VMX if guest state is invalid, let the exit handler
8947            start emulation until we arrive back to a valid state */
8948         if (vmx->emulation_required)
8949                 return;
8950
8951         if (vmx->ple_window_dirty) {
8952                 vmx->ple_window_dirty = false;
8953                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8954         }
8955
8956         if (vmx->nested.sync_shadow_vmcs) {
8957                 copy_vmcs12_to_shadow(vmx);
8958                 vmx->nested.sync_shadow_vmcs = false;
8959         }
8960
8961         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8962                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8963         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8964                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8965
8966         cr4 = cr4_read_shadow();
8967         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8968                 vmcs_writel(HOST_CR4, cr4);
8969                 vmx->host_state.vmcs_host_cr4 = cr4;
8970         }
8971
8972         /* When single-stepping over STI and MOV SS, we must clear the
8973          * corresponding interruptibility bits in the guest state. Otherwise
8974          * vmentry fails as it then expects bit 14 (BS) in pending debug
8975          * exceptions being set, but that's not correct for the guest debugging
8976          * case. */
8977         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8978                 vmx_set_interrupt_shadow(vcpu, 0);
8979
8980         if (vmx->guest_pkru_valid)
8981                 __write_pkru(vmx->guest_pkru);
8982
8983         atomic_switch_perf_msrs(vmx);
8984         debugctlmsr = get_debugctlmsr();
8985
8986         vmx_arm_hv_timer(vcpu);
8987
8988         vmx->__launched = vmx->loaded_vmcs->launched;
8989         asm(
8990                 /* Store host registers */
8991                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8992                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8993                 "push %%" _ASM_CX " \n\t"
8994                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8995                 "je 1f \n\t"
8996                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8997                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8998                 "1: \n\t"
8999                 /* Reload cr2 if changed */
9000                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9001                 "mov %%cr2, %%" _ASM_DX " \n\t"
9002                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9003                 "je 2f \n\t"
9004                 "mov %%" _ASM_AX", %%cr2 \n\t"
9005                 "2: \n\t"
9006                 /* Check if vmlaunch of vmresume is needed */
9007                 "cmpl $0, %c[launched](%0) \n\t"
9008                 /* Load guest registers.  Don't clobber flags. */
9009                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9010                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9011                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9012                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9013                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9014                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9015 #ifdef CONFIG_X86_64
9016                 "mov %c[r8](%0),  %%r8  \n\t"
9017                 "mov %c[r9](%0),  %%r9  \n\t"
9018                 "mov %c[r10](%0), %%r10 \n\t"
9019                 "mov %c[r11](%0), %%r11 \n\t"
9020                 "mov %c[r12](%0), %%r12 \n\t"
9021                 "mov %c[r13](%0), %%r13 \n\t"
9022                 "mov %c[r14](%0), %%r14 \n\t"
9023                 "mov %c[r15](%0), %%r15 \n\t"
9024 #endif
9025                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9026
9027                 /* Enter guest mode */
9028                 "jne 1f \n\t"
9029                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9030                 "jmp 2f \n\t"
9031                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9032                 "2: "
9033                 /* Save guest registers, load host registers, keep flags */
9034                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9035                 "pop %0 \n\t"
9036                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9037                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9038                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9039                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9040                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9041                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9042                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9043 #ifdef CONFIG_X86_64
9044                 "mov %%r8,  %c[r8](%0) \n\t"
9045                 "mov %%r9,  %c[r9](%0) \n\t"
9046                 "mov %%r10, %c[r10](%0) \n\t"
9047                 "mov %%r11, %c[r11](%0) \n\t"
9048                 "mov %%r12, %c[r12](%0) \n\t"
9049                 "mov %%r13, %c[r13](%0) \n\t"
9050                 "mov %%r14, %c[r14](%0) \n\t"
9051                 "mov %%r15, %c[r15](%0) \n\t"
9052 #endif
9053                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9054                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9055
9056                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9057                 "setbe %c[fail](%0) \n\t"
9058                 ".pushsection .rodata \n\t"
9059                 ".global vmx_return \n\t"
9060                 "vmx_return: " _ASM_PTR " 2b \n\t"
9061                 ".popsection"
9062               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9063                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9064                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9065                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9066                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9067                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9068                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9069                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9070                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9071                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9072                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9073 #ifdef CONFIG_X86_64
9074                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9075                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9076                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9077                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9078                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9079                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9080                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9081                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9082 #endif
9083                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9084                 [wordsize]"i"(sizeof(ulong))
9085               : "cc", "memory"
9086 #ifdef CONFIG_X86_64
9087                 , "rax", "rbx", "rdi", "rsi"
9088                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9089 #else
9090                 , "eax", "ebx", "edi", "esi"
9091 #endif
9092               );
9093
9094         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9095         if (debugctlmsr)
9096                 update_debugctlmsr(debugctlmsr);
9097
9098 #ifndef CONFIG_X86_64
9099         /*
9100          * The sysexit path does not restore ds/es, so we must set them to
9101          * a reasonable value ourselves.
9102          *
9103          * We can't defer this to vmx_load_host_state() since that function
9104          * may be executed in interrupt context, which saves and restore segments
9105          * around it, nullifying its effect.
9106          */
9107         loadsegment(ds, __USER_DS);
9108         loadsegment(es, __USER_DS);
9109 #endif
9110
9111         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9112                                   | (1 << VCPU_EXREG_RFLAGS)
9113                                   | (1 << VCPU_EXREG_PDPTR)
9114                                   | (1 << VCPU_EXREG_SEGMENTS)
9115                                   | (1 << VCPU_EXREG_CR3));
9116         vcpu->arch.regs_dirty = 0;
9117
9118         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9119
9120         vmx->loaded_vmcs->launched = 1;
9121
9122         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9123
9124         /*
9125          * eager fpu is enabled if PKEY is supported and CR4 is switched
9126          * back on host, so it is safe to read guest PKRU from current
9127          * XSAVE.
9128          */
9129         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9130                 vmx->guest_pkru = __read_pkru();
9131                 if (vmx->guest_pkru != vmx->host_pkru) {
9132                         vmx->guest_pkru_valid = true;
9133                         __write_pkru(vmx->host_pkru);
9134                 } else
9135                         vmx->guest_pkru_valid = false;
9136         }
9137
9138         /*
9139          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9140          * we did not inject a still-pending event to L1 now because of
9141          * nested_run_pending, we need to re-enable this bit.
9142          */
9143         if (vmx->nested.nested_run_pending)
9144                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9145
9146         vmx->nested.nested_run_pending = 0;
9147
9148         vmx_complete_atomic_exit(vmx);
9149         vmx_recover_nmi_blocking(vmx);
9150         vmx_complete_interrupts(vmx);
9151 }
9152
9153 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9154 {
9155         struct vcpu_vmx *vmx = to_vmx(vcpu);
9156         int cpu;
9157
9158         if (vmx->loaded_vmcs == &vmx->vmcs01)
9159                 return;
9160
9161         cpu = get_cpu();
9162         vmx->loaded_vmcs = &vmx->vmcs01;
9163         vmx_vcpu_put(vcpu);
9164         vmx_vcpu_load(vcpu, cpu);
9165         vcpu->cpu = cpu;
9166         put_cpu();
9167 }
9168
9169 /*
9170  * Ensure that the current vmcs of the logical processor is the
9171  * vmcs01 of the vcpu before calling free_nested().
9172  */
9173 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9174 {
9175        struct vcpu_vmx *vmx = to_vmx(vcpu);
9176        int r;
9177
9178        r = vcpu_load(vcpu);
9179        BUG_ON(r);
9180        vmx_load_vmcs01(vcpu);
9181        free_nested(vmx);
9182        vcpu_put(vcpu);
9183 }
9184
9185 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9186 {
9187         struct vcpu_vmx *vmx = to_vmx(vcpu);
9188
9189         if (enable_pml)
9190                 vmx_destroy_pml_buffer(vmx);
9191         free_vpid(vmx->vpid);
9192         leave_guest_mode(vcpu);
9193         vmx_free_vcpu_nested(vcpu);
9194         free_loaded_vmcs(vmx->loaded_vmcs);
9195         kfree(vmx->guest_msrs);
9196         kvm_vcpu_uninit(vcpu);
9197         kmem_cache_free(kvm_vcpu_cache, vmx);
9198 }
9199
9200 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9201 {
9202         int err;
9203         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9204         int cpu;
9205
9206         if (!vmx)
9207                 return ERR_PTR(-ENOMEM);
9208
9209         vmx->vpid = allocate_vpid();
9210
9211         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9212         if (err)
9213                 goto free_vcpu;
9214
9215         err = -ENOMEM;
9216
9217         /*
9218          * If PML is turned on, failure on enabling PML just results in failure
9219          * of creating the vcpu, therefore we can simplify PML logic (by
9220          * avoiding dealing with cases, such as enabling PML partially on vcpus
9221          * for the guest, etc.
9222          */
9223         if (enable_pml) {
9224                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9225                 if (!vmx->pml_pg)
9226                         goto uninit_vcpu;
9227         }
9228
9229         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9230         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9231                      > PAGE_SIZE);
9232
9233         if (!vmx->guest_msrs)
9234                 goto free_pml;
9235
9236         vmx->loaded_vmcs = &vmx->vmcs01;
9237         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9238         vmx->loaded_vmcs->shadow_vmcs = NULL;
9239         if (!vmx->loaded_vmcs->vmcs)
9240                 goto free_msrs;
9241         if (!vmm_exclusive)
9242                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9243         loaded_vmcs_init(vmx->loaded_vmcs);
9244         if (!vmm_exclusive)
9245                 kvm_cpu_vmxoff();
9246
9247         cpu = get_cpu();
9248         vmx_vcpu_load(&vmx->vcpu, cpu);
9249         vmx->vcpu.cpu = cpu;
9250         err = vmx_vcpu_setup(vmx);
9251         vmx_vcpu_put(&vmx->vcpu);
9252         put_cpu();
9253         if (err)
9254                 goto free_vmcs;
9255         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9256                 err = alloc_apic_access_page(kvm);
9257                 if (err)
9258                         goto free_vmcs;
9259         }
9260
9261         if (enable_ept) {
9262                 if (!kvm->arch.ept_identity_map_addr)
9263                         kvm->arch.ept_identity_map_addr =
9264                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9265                 err = init_rmode_identity_map(kvm);
9266                 if (err)
9267                         goto free_vmcs;
9268         }
9269
9270         if (nested) {
9271                 nested_vmx_setup_ctls_msrs(vmx);
9272                 vmx->nested.vpid02 = allocate_vpid();
9273         }
9274
9275         vmx->nested.posted_intr_nv = -1;
9276         vmx->nested.current_vmptr = -1ull;
9277         vmx->nested.current_vmcs12 = NULL;
9278
9279         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9280
9281         return &vmx->vcpu;
9282
9283 free_vmcs:
9284         free_vpid(vmx->nested.vpid02);
9285         free_loaded_vmcs(vmx->loaded_vmcs);
9286 free_msrs:
9287         kfree(vmx->guest_msrs);
9288 free_pml:
9289         vmx_destroy_pml_buffer(vmx);
9290 uninit_vcpu:
9291         kvm_vcpu_uninit(&vmx->vcpu);
9292 free_vcpu:
9293         free_vpid(vmx->vpid);
9294         kmem_cache_free(kvm_vcpu_cache, vmx);
9295         return ERR_PTR(err);
9296 }
9297
9298 static void __init vmx_check_processor_compat(void *rtn)
9299 {
9300         struct vmcs_config vmcs_conf;
9301
9302         *(int *)rtn = 0;
9303         if (setup_vmcs_config(&vmcs_conf) < 0)
9304                 *(int *)rtn = -EIO;
9305         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9306                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9307                                 smp_processor_id());
9308                 *(int *)rtn = -EIO;
9309         }
9310 }
9311
9312 static int get_ept_level(void)
9313 {
9314         return VMX_EPT_DEFAULT_GAW + 1;
9315 }
9316
9317 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9318 {
9319         u8 cache;
9320         u64 ipat = 0;
9321
9322         /* For VT-d and EPT combination
9323          * 1. MMIO: always map as UC
9324          * 2. EPT with VT-d:
9325          *   a. VT-d without snooping control feature: can't guarantee the
9326          *      result, try to trust guest.
9327          *   b. VT-d with snooping control feature: snooping control feature of
9328          *      VT-d engine can guarantee the cache correctness. Just set it
9329          *      to WB to keep consistent with host. So the same as item 3.
9330          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9331          *    consistent with host MTRR
9332          */
9333         if (is_mmio) {
9334                 cache = MTRR_TYPE_UNCACHABLE;
9335                 goto exit;
9336         }
9337
9338         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9339                 ipat = VMX_EPT_IPAT_BIT;
9340                 cache = MTRR_TYPE_WRBACK;
9341                 goto exit;
9342         }
9343
9344         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9345                 ipat = VMX_EPT_IPAT_BIT;
9346                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9347                         cache = MTRR_TYPE_WRBACK;
9348                 else
9349                         cache = MTRR_TYPE_UNCACHABLE;
9350                 goto exit;
9351         }
9352
9353         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9354
9355 exit:
9356         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9357 }
9358
9359 static int vmx_get_lpage_level(void)
9360 {
9361         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9362                 return PT_DIRECTORY_LEVEL;
9363         else
9364                 /* For shadow and EPT supported 1GB page */
9365                 return PT_PDPE_LEVEL;
9366 }
9367
9368 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9369 {
9370         /*
9371          * These bits in the secondary execution controls field
9372          * are dynamic, the others are mostly based on the hypervisor
9373          * architecture and the guest's CPUID.  Do not touch the
9374          * dynamic bits.
9375          */
9376         u32 mask =
9377                 SECONDARY_EXEC_SHADOW_VMCS |
9378                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9379                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9380
9381         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9382
9383         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9384                      (new_ctl & ~mask) | (cur_ctl & mask));
9385 }
9386
9387 /*
9388  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9389  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9390  */
9391 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9392 {
9393         struct vcpu_vmx *vmx = to_vmx(vcpu);
9394         struct kvm_cpuid_entry2 *entry;
9395
9396         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9397         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9398
9399 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9400         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9401                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9402 } while (0)
9403
9404         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9405         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9406         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9407         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9408         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9409         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9410         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9411         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9412         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9413         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9414         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9415         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9416         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9417         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9418         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9419
9420         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9421         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9422         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9423         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9424         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9425         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9426         cr4_fixed1_update(bit(11),            ecx, bit(2));
9427
9428 #undef cr4_fixed1_update
9429 }
9430
9431 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9432 {
9433         struct kvm_cpuid_entry2 *best;
9434         struct vcpu_vmx *vmx = to_vmx(vcpu);
9435         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9436
9437         if (vmx_rdtscp_supported()) {
9438                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9439                 if (!rdtscp_enabled)
9440                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9441
9442                 if (nested) {
9443                         if (rdtscp_enabled)
9444                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9445                                         SECONDARY_EXEC_RDTSCP;
9446                         else
9447                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9448                                         ~SECONDARY_EXEC_RDTSCP;
9449                 }
9450         }
9451
9452         /* Exposing INVPCID only when PCID is exposed */
9453         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9454         if (vmx_invpcid_supported() &&
9455             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9456             !guest_cpuid_has_pcid(vcpu))) {
9457                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9458
9459                 if (best)
9460                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9461         }
9462
9463         if (cpu_has_secondary_exec_ctrls())
9464                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9465
9466         if (nested_vmx_allowed(vcpu))
9467                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9468                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9469         else
9470                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9471                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9472
9473         if (nested_vmx_allowed(vcpu))
9474                 nested_vmx_cr_fixed1_bits_update(vcpu);
9475 }
9476
9477 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9478 {
9479         if (func == 1 && nested)
9480                 entry->ecx |= bit(X86_FEATURE_VMX);
9481 }
9482
9483 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9484                 struct x86_exception *fault)
9485 {
9486         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9487         u32 exit_reason;
9488
9489         if (fault->error_code & PFERR_RSVD_MASK)
9490                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9491         else
9492                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9493         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9494         vmcs12->guest_physical_address = fault->address;
9495 }
9496
9497 /* Callbacks for nested_ept_init_mmu_context: */
9498
9499 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9500 {
9501         /* return the page table to be shadowed - in our case, EPT12 */
9502         return get_vmcs12(vcpu)->ept_pointer;
9503 }
9504
9505 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9506 {
9507         WARN_ON(mmu_is_nested(vcpu));
9508         kvm_init_shadow_ept_mmu(vcpu,
9509                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9510                         VMX_EPT_EXECUTE_ONLY_BIT);
9511         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9512         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9513         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9514
9515         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9516 }
9517
9518 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9519 {
9520         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9521 }
9522
9523 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9524                                             u16 error_code)
9525 {
9526         bool inequality, bit;
9527
9528         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9529         inequality =
9530                 (error_code & vmcs12->page_fault_error_code_mask) !=
9531                  vmcs12->page_fault_error_code_match;
9532         return inequality ^ bit;
9533 }
9534
9535 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9536                 struct x86_exception *fault)
9537 {
9538         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9539
9540         WARN_ON(!is_guest_mode(vcpu));
9541
9542         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9543                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9544                                   vmcs_read32(VM_EXIT_INTR_INFO),
9545                                   vmcs_readl(EXIT_QUALIFICATION));
9546         else
9547                 kvm_inject_page_fault(vcpu, fault);
9548 }
9549
9550 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9551                                                struct vmcs12 *vmcs12);
9552
9553 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9554                                         struct vmcs12 *vmcs12)
9555 {
9556         struct vcpu_vmx *vmx = to_vmx(vcpu);
9557         u64 hpa;
9558
9559         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9560                 /*
9561                  * Translate L1 physical address to host physical
9562                  * address for vmcs02. Keep the page pinned, so this
9563                  * physical address remains valid. We keep a reference
9564                  * to it so we can release it later.
9565                  */
9566                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9567                         nested_release_page(vmx->nested.apic_access_page);
9568                 vmx->nested.apic_access_page =
9569                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9570                 /*
9571                  * If translation failed, no matter: This feature asks
9572                  * to exit when accessing the given address, and if it
9573                  * can never be accessed, this feature won't do
9574                  * anything anyway.
9575                  */
9576                 if (vmx->nested.apic_access_page) {
9577                         hpa = page_to_phys(vmx->nested.apic_access_page);
9578                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9579                 } else {
9580                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9581                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9582                 }
9583         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9584                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9585                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9586                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9587                 kvm_vcpu_reload_apic_access_page(vcpu);
9588         }
9589
9590         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9591                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9592                         nested_release_page(vmx->nested.virtual_apic_page);
9593                 vmx->nested.virtual_apic_page =
9594                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9595
9596                 /*
9597                  * If translation failed, VM entry will fail because
9598                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9599                  * Failing the vm entry is _not_ what the processor
9600                  * does but it's basically the only possibility we
9601                  * have.  We could still enter the guest if CR8 load
9602                  * exits are enabled, CR8 store exits are enabled, and
9603                  * virtualize APIC access is disabled; in this case
9604                  * the processor would never use the TPR shadow and we
9605                  * could simply clear the bit from the execution
9606                  * control.  But such a configuration is useless, so
9607                  * let's keep the code simple.
9608                  */
9609                 if (vmx->nested.virtual_apic_page) {
9610                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9611                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9612                 }
9613         }
9614
9615         if (nested_cpu_has_posted_intr(vmcs12)) {
9616                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9617                         kunmap(vmx->nested.pi_desc_page);
9618                         nested_release_page(vmx->nested.pi_desc_page);
9619                 }
9620                 vmx->nested.pi_desc_page =
9621                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9622                 vmx->nested.pi_desc =
9623                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9624                 if (!vmx->nested.pi_desc) {
9625                         nested_release_page_clean(vmx->nested.pi_desc_page);
9626                         return;
9627                 }
9628                 vmx->nested.pi_desc =
9629                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9630                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9631                         (PAGE_SIZE - 1)));
9632                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9633                         page_to_phys(vmx->nested.pi_desc_page) +
9634                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9635                         (PAGE_SIZE - 1)));
9636         }
9637         if (cpu_has_vmx_msr_bitmap() &&
9638             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9639             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9640                 ;
9641         else
9642                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9643                                 CPU_BASED_USE_MSR_BITMAPS);
9644 }
9645
9646 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9647 {
9648         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9649         struct vcpu_vmx *vmx = to_vmx(vcpu);
9650
9651         if (vcpu->arch.virtual_tsc_khz == 0)
9652                 return;
9653
9654         /* Make sure short timeouts reliably trigger an immediate vmexit.
9655          * hrtimer_start does not guarantee this. */
9656         if (preemption_timeout <= 1) {
9657                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9658                 return;
9659         }
9660
9661         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9662         preemption_timeout *= 1000000;
9663         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9664         hrtimer_start(&vmx->nested.preemption_timer,
9665                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9666 }
9667
9668 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9669                                                 struct vmcs12 *vmcs12)
9670 {
9671         int maxphyaddr;
9672         u64 addr;
9673
9674         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9675                 return 0;
9676
9677         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9678                 WARN_ON(1);
9679                 return -EINVAL;
9680         }
9681         maxphyaddr = cpuid_maxphyaddr(vcpu);
9682
9683         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9684            ((addr + PAGE_SIZE) >> maxphyaddr))
9685                 return -EINVAL;
9686
9687         return 0;
9688 }
9689
9690 /*
9691  * Merge L0's and L1's MSR bitmap, return false to indicate that
9692  * we do not use the hardware.
9693  */
9694 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9695                                                struct vmcs12 *vmcs12)
9696 {
9697         int msr;
9698         struct page *page;
9699         unsigned long *msr_bitmap_l1;
9700         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9701
9702         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9703         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9704                 return false;
9705
9706         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9707         if (!page) {
9708                 WARN_ON(1);
9709                 return false;
9710         }
9711         msr_bitmap_l1 = (unsigned long *)kmap(page);
9712
9713         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9714
9715         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9716                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9717                         for (msr = 0x800; msr <= 0x8ff; msr++)
9718                                 nested_vmx_disable_intercept_for_msr(
9719                                         msr_bitmap_l1, msr_bitmap_l0,
9720                                         msr, MSR_TYPE_R);
9721
9722                 nested_vmx_disable_intercept_for_msr(
9723                                 msr_bitmap_l1, msr_bitmap_l0,
9724                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9725                                 MSR_TYPE_R | MSR_TYPE_W);
9726
9727                 if (nested_cpu_has_vid(vmcs12)) {
9728                         nested_vmx_disable_intercept_for_msr(
9729                                 msr_bitmap_l1, msr_bitmap_l0,
9730                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9731                                 MSR_TYPE_W);
9732                         nested_vmx_disable_intercept_for_msr(
9733                                 msr_bitmap_l1, msr_bitmap_l0,
9734                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9735                                 MSR_TYPE_W);
9736                 }
9737         }
9738         kunmap(page);
9739         nested_release_page_clean(page);
9740
9741         return true;
9742 }
9743
9744 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9745                                            struct vmcs12 *vmcs12)
9746 {
9747         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9748             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9749             !nested_cpu_has_vid(vmcs12) &&
9750             !nested_cpu_has_posted_intr(vmcs12))
9751                 return 0;
9752
9753         /*
9754          * If virtualize x2apic mode is enabled,
9755          * virtualize apic access must be disabled.
9756          */
9757         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9758             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9759                 return -EINVAL;
9760
9761         /*
9762          * If virtual interrupt delivery is enabled,
9763          * we must exit on external interrupts.
9764          */
9765         if (nested_cpu_has_vid(vmcs12) &&
9766            !nested_exit_on_intr(vcpu))
9767                 return -EINVAL;
9768
9769         /*
9770          * bits 15:8 should be zero in posted_intr_nv,
9771          * the descriptor address has been already checked
9772          * in nested_get_vmcs12_pages.
9773          */
9774         if (nested_cpu_has_posted_intr(vmcs12) &&
9775            (!nested_cpu_has_vid(vmcs12) ||
9776             !nested_exit_intr_ack_set(vcpu) ||
9777             vmcs12->posted_intr_nv & 0xff00))
9778                 return -EINVAL;
9779
9780         /* tpr shadow is needed by all apicv features. */
9781         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9782                 return -EINVAL;
9783
9784         return 0;
9785 }
9786
9787 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9788                                        unsigned long count_field,
9789                                        unsigned long addr_field)
9790 {
9791         int maxphyaddr;
9792         u64 count, addr;
9793
9794         if (vmcs12_read_any(vcpu, count_field, &count) ||
9795             vmcs12_read_any(vcpu, addr_field, &addr)) {
9796                 WARN_ON(1);
9797                 return -EINVAL;
9798         }
9799         if (count == 0)
9800                 return 0;
9801         maxphyaddr = cpuid_maxphyaddr(vcpu);
9802         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9803             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9804                 pr_debug_ratelimited(
9805                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9806                         addr_field, maxphyaddr, count, addr);
9807                 return -EINVAL;
9808         }
9809         return 0;
9810 }
9811
9812 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9813                                                 struct vmcs12 *vmcs12)
9814 {
9815         if (vmcs12->vm_exit_msr_load_count == 0 &&
9816             vmcs12->vm_exit_msr_store_count == 0 &&
9817             vmcs12->vm_entry_msr_load_count == 0)
9818                 return 0; /* Fast path */
9819         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9820                                         VM_EXIT_MSR_LOAD_ADDR) ||
9821             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9822                                         VM_EXIT_MSR_STORE_ADDR) ||
9823             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9824                                         VM_ENTRY_MSR_LOAD_ADDR))
9825                 return -EINVAL;
9826         return 0;
9827 }
9828
9829 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9830                                        struct vmx_msr_entry *e)
9831 {
9832         /* x2APIC MSR accesses are not allowed */
9833         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9834                 return -EINVAL;
9835         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9836             e->index == MSR_IA32_UCODE_REV)
9837                 return -EINVAL;
9838         if (e->reserved != 0)
9839                 return -EINVAL;
9840         return 0;
9841 }
9842
9843 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9844                                      struct vmx_msr_entry *e)
9845 {
9846         if (e->index == MSR_FS_BASE ||
9847             e->index == MSR_GS_BASE ||
9848             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9849             nested_vmx_msr_check_common(vcpu, e))
9850                 return -EINVAL;
9851         return 0;
9852 }
9853
9854 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9855                                       struct vmx_msr_entry *e)
9856 {
9857         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9858             nested_vmx_msr_check_common(vcpu, e))
9859                 return -EINVAL;
9860         return 0;
9861 }
9862
9863 /*
9864  * Load guest's/host's msr at nested entry/exit.
9865  * return 0 for success, entry index for failure.
9866  */
9867 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9868 {
9869         u32 i;
9870         struct vmx_msr_entry e;
9871         struct msr_data msr;
9872
9873         msr.host_initiated = false;
9874         for (i = 0; i < count; i++) {
9875                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9876                                         &e, sizeof(e))) {
9877                         pr_debug_ratelimited(
9878                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9879                                 __func__, i, gpa + i * sizeof(e));
9880                         goto fail;
9881                 }
9882                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9883                         pr_debug_ratelimited(
9884                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9885                                 __func__, i, e.index, e.reserved);
9886                         goto fail;
9887                 }
9888                 msr.index = e.index;
9889                 msr.data = e.value;
9890                 if (kvm_set_msr(vcpu, &msr)) {
9891                         pr_debug_ratelimited(
9892                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9893                                 __func__, i, e.index, e.value);
9894                         goto fail;
9895                 }
9896         }
9897         return 0;
9898 fail:
9899         return i + 1;
9900 }
9901
9902 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9903 {
9904         u32 i;
9905         struct vmx_msr_entry e;
9906
9907         for (i = 0; i < count; i++) {
9908                 struct msr_data msr_info;
9909                 if (kvm_vcpu_read_guest(vcpu,
9910                                         gpa + i * sizeof(e),
9911                                         &e, 2 * sizeof(u32))) {
9912                         pr_debug_ratelimited(
9913                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9914                                 __func__, i, gpa + i * sizeof(e));
9915                         return -EINVAL;
9916                 }
9917                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9918                         pr_debug_ratelimited(
9919                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9920                                 __func__, i, e.index, e.reserved);
9921                         return -EINVAL;
9922                 }
9923                 msr_info.host_initiated = false;
9924                 msr_info.index = e.index;
9925                 if (kvm_get_msr(vcpu, &msr_info)) {
9926                         pr_debug_ratelimited(
9927                                 "%s cannot read MSR (%u, 0x%x)\n",
9928                                 __func__, i, e.index);
9929                         return -EINVAL;
9930                 }
9931                 if (kvm_vcpu_write_guest(vcpu,
9932                                          gpa + i * sizeof(e) +
9933                                              offsetof(struct vmx_msr_entry, value),
9934                                          &msr_info.data, sizeof(msr_info.data))) {
9935                         pr_debug_ratelimited(
9936                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9937                                 __func__, i, e.index, msr_info.data);
9938                         return -EINVAL;
9939                 }
9940         }
9941         return 0;
9942 }
9943
9944 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9945 {
9946         unsigned long invalid_mask;
9947
9948         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9949         return (val & invalid_mask) == 0;
9950 }
9951
9952 /*
9953  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9954  * emulating VM entry into a guest with EPT enabled.
9955  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9956  * is assigned to entry_failure_code on failure.
9957  */
9958 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9959                                u32 *entry_failure_code)
9960 {
9961         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9962                 if (!nested_cr3_valid(vcpu, cr3)) {
9963                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9964                         return 1;
9965                 }
9966
9967                 /*
9968                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9969                  * must not be dereferenced.
9970                  */
9971                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9972                     !nested_ept) {
9973                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9974                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9975                                 return 1;
9976                         }
9977                 }
9978
9979                 vcpu->arch.cr3 = cr3;
9980                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9981         }
9982
9983         kvm_mmu_reset_context(vcpu);
9984         return 0;
9985 }
9986
9987 /*
9988  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9989  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9990  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9991  * guest in a way that will both be appropriate to L1's requests, and our
9992  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9993  * function also has additional necessary side-effects, like setting various
9994  * vcpu->arch fields.
9995  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9996  * is assigned to entry_failure_code on failure.
9997  */
9998 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9999                           bool from_vmentry, u32 *entry_failure_code)
10000 {
10001         struct vcpu_vmx *vmx = to_vmx(vcpu);
10002         u32 exec_control;
10003         bool nested_ept_enabled = false;
10004
10005         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10006         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10007         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10008         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10009         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10010         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10011         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10012         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10013         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10014         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10015         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10016         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10017         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10018         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10019         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10020         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10021         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10022         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10023         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10024         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10025         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10026         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10027         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10028         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10029         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10030         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10031         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10032         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10033         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10034         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10035         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10036         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10037         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10038         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10039         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10040         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10041
10042         if (from_vmentry &&
10043             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10044                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10045                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10046         } else {
10047                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10048                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10049         }
10050         if (from_vmentry) {
10051                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10052                              vmcs12->vm_entry_intr_info_field);
10053                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10054                              vmcs12->vm_entry_exception_error_code);
10055                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10056                              vmcs12->vm_entry_instruction_len);
10057                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10058                              vmcs12->guest_interruptibility_info);
10059         } else {
10060                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10061         }
10062         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10063         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10064         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10065                 vmcs12->guest_pending_dbg_exceptions);
10066         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10067         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10068
10069         if (nested_cpu_has_xsaves(vmcs12))
10070                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10071         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10072
10073         exec_control = vmcs12->pin_based_vm_exec_control;
10074
10075         /* Preemption timer setting is only taken from vmcs01.  */
10076         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10077         exec_control |= vmcs_config.pin_based_exec_ctrl;
10078         if (vmx->hv_deadline_tsc == -1)
10079                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10080
10081         /* Posted interrupts setting is only taken from vmcs12.  */
10082         if (nested_cpu_has_posted_intr(vmcs12)) {
10083                 /*
10084                  * Note that we use L0's vector here and in
10085                  * vmx_deliver_nested_posted_interrupt.
10086                  */
10087                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10088                 vmx->nested.pi_pending = false;
10089                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10090         } else {
10091                 exec_control &= ~PIN_BASED_POSTED_INTR;
10092         }
10093
10094         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10095
10096         vmx->nested.preemption_timer_expired = false;
10097         if (nested_cpu_has_preemption_timer(vmcs12))
10098                 vmx_start_preemption_timer(vcpu);
10099
10100         /*
10101          * Whether page-faults are trapped is determined by a combination of
10102          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10103          * If enable_ept, L0 doesn't care about page faults and we should
10104          * set all of these to L1's desires. However, if !enable_ept, L0 does
10105          * care about (at least some) page faults, and because it is not easy
10106          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10107          * to exit on each and every L2 page fault. This is done by setting
10108          * MASK=MATCH=0 and (see below) EB.PF=1.
10109          * Note that below we don't need special code to set EB.PF beyond the
10110          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10111          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10112          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10113          *
10114          * A problem with this approach (when !enable_ept) is that L1 may be
10115          * injected with more page faults than it asked for. This could have
10116          * caused problems, but in practice existing hypervisors don't care.
10117          * To fix this, we will need to emulate the PFEC checking (on the L1
10118          * page tables), using walk_addr(), when injecting PFs to L1.
10119          */
10120         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10121                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10122         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10123                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10124
10125         if (cpu_has_secondary_exec_ctrls()) {
10126                 exec_control = vmx_secondary_exec_control(vmx);
10127
10128                 /* Take the following fields only from vmcs12 */
10129                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10130                                   SECONDARY_EXEC_RDTSCP |
10131                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10132                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10133                 if (nested_cpu_has(vmcs12,
10134                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10135                         exec_control |= vmcs12->secondary_vm_exec_control;
10136
10137                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10138                         vmcs_write64(EOI_EXIT_BITMAP0,
10139                                 vmcs12->eoi_exit_bitmap0);
10140                         vmcs_write64(EOI_EXIT_BITMAP1,
10141                                 vmcs12->eoi_exit_bitmap1);
10142                         vmcs_write64(EOI_EXIT_BITMAP2,
10143                                 vmcs12->eoi_exit_bitmap2);
10144                         vmcs_write64(EOI_EXIT_BITMAP3,
10145                                 vmcs12->eoi_exit_bitmap3);
10146                         vmcs_write16(GUEST_INTR_STATUS,
10147                                 vmcs12->guest_intr_status);
10148                 }
10149
10150                 nested_ept_enabled = (exec_control & SECONDARY_EXEC_ENABLE_EPT) != 0;
10151
10152                 /*
10153                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10154                  * nested_get_vmcs12_pages will either fix it up or
10155                  * remove the VM execution control.
10156                  */
10157                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10158                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10159
10160                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10161         }
10162
10163
10164         /*
10165          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10166          * Some constant fields are set here by vmx_set_constant_host_state().
10167          * Other fields are different per CPU, and will be set later when
10168          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10169          */
10170         vmx_set_constant_host_state(vmx);
10171
10172         /*
10173          * Set the MSR load/store lists to match L0's settings.
10174          */
10175         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10176         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10177         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10178         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10179         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10180
10181         /*
10182          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10183          * entry, but only if the current (host) sp changed from the value
10184          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10185          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10186          * here we just force the write to happen on entry.
10187          */
10188         vmx->host_rsp = 0;
10189
10190         exec_control = vmx_exec_control(vmx); /* L0's desires */
10191         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10192         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10193         exec_control &= ~CPU_BASED_TPR_SHADOW;
10194         exec_control |= vmcs12->cpu_based_vm_exec_control;
10195
10196         /*
10197          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10198          * nested_get_vmcs12_pages can't fix it up, the illegal value
10199          * will result in a VM entry failure.
10200          */
10201         if (exec_control & CPU_BASED_TPR_SHADOW) {
10202                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10203                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10204         }
10205
10206         /*
10207          * Merging of IO bitmap not currently supported.
10208          * Rather, exit every time.
10209          */
10210         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10211         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10212
10213         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10214
10215         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10216          * bitwise-or of what L1 wants to trap for L2, and what we want to
10217          * trap. Note that CR0.TS also needs updating - we do this later.
10218          */
10219         update_exception_bitmap(vcpu);
10220         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10221         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10222
10223         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10224          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10225          * bits are further modified by vmx_set_efer() below.
10226          */
10227         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10228
10229         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10230          * emulated by vmx_set_efer(), below.
10231          */
10232         vm_entry_controls_init(vmx,
10233                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10234                         ~VM_ENTRY_IA32E_MODE) |
10235                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10236
10237         if (from_vmentry &&
10238             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10239                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10240                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10241         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10242                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10243         }
10244
10245         set_cr4_guest_host_mask(vmx);
10246
10247         if (from_vmentry &&
10248             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10249                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10250
10251         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10252                 vmcs_write64(TSC_OFFSET,
10253                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10254         else
10255                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10256         if (kvm_has_tsc_control)
10257                 decache_tsc_multiplier(vmx);
10258
10259         if (enable_vpid) {
10260                 /*
10261                  * There is no direct mapping between vpid02 and vpid12, the
10262                  * vpid02 is per-vCPU for L0 and reused while the value of
10263                  * vpid12 is changed w/ one invvpid during nested vmentry.
10264                  * The vpid12 is allocated by L1 for L2, so it will not
10265                  * influence global bitmap(for vpid01 and vpid02 allocation)
10266                  * even if spawn a lot of nested vCPUs.
10267                  */
10268                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10269                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10270                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10271                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10272                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10273                         }
10274                 } else {
10275                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10276                         vmx_flush_tlb(vcpu);
10277                 }
10278
10279         }
10280
10281         if (nested_cpu_has_ept(vmcs12)) {
10282                 kvm_mmu_unload(vcpu);
10283                 nested_ept_init_mmu_context(vcpu);
10284         }
10285
10286         /*
10287          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10288          * bits which we consider mandatory enabled.
10289          * The CR0_READ_SHADOW is what L2 should have expected to read given
10290          * the specifications by L1; It's not enough to take
10291          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10292          * have more bits than L1 expected.
10293          */
10294         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10295         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10296
10297         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10298         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10299
10300         if (from_vmentry &&
10301             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10302                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10303         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10304                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10305         else
10306                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10307         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10308         vmx_set_efer(vcpu, vcpu->arch.efer);
10309
10310         /* Shadow page tables on either EPT or shadow page tables. */
10311         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_ept_enabled,
10312                                 entry_failure_code))
10313                 return 1;
10314
10315         kvm_mmu_reset_context(vcpu);
10316
10317         if (!enable_ept)
10318                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10319
10320         /*
10321          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10322          */
10323         if (enable_ept) {
10324                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10325                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10326                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10327                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10328         }
10329
10330         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10331         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10332         return 0;
10333 }
10334
10335 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10336 {
10337         struct vcpu_vmx *vmx = to_vmx(vcpu);
10338
10339         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10340             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10341                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10342
10343         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10344                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10345
10346         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10347                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10348
10349         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10350                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10351
10352         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10353                                 vmx->nested.nested_vmx_procbased_ctls_low,
10354                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10355             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10356                                 vmx->nested.nested_vmx_secondary_ctls_low,
10357                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10358             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10359                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10360                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10361             !vmx_control_verify(vmcs12->vm_exit_controls,
10362                                 vmx->nested.nested_vmx_exit_ctls_low,
10363                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10364             !vmx_control_verify(vmcs12->vm_entry_controls,
10365                                 vmx->nested.nested_vmx_entry_ctls_low,
10366                                 vmx->nested.nested_vmx_entry_ctls_high))
10367                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10368
10369         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10370             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10371             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10372                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10373
10374         return 0;
10375 }
10376
10377 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10378                                   u32 *exit_qual)
10379 {
10380         bool ia32e;
10381
10382         *exit_qual = ENTRY_FAIL_DEFAULT;
10383
10384         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10385             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10386                 return 1;
10387
10388         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10389             vmcs12->vmcs_link_pointer != -1ull) {
10390                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10391                 return 1;
10392         }
10393
10394         /*
10395          * If the load IA32_EFER VM-entry control is 1, the following checks
10396          * are performed on the field for the IA32_EFER MSR:
10397          * - Bits reserved in the IA32_EFER MSR must be 0.
10398          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10399          *   the IA-32e mode guest VM-exit control. It must also be identical
10400          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10401          *   CR0.PG) is 1.
10402          */
10403         if (to_vmx(vcpu)->nested.nested_run_pending &&
10404             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10405                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10406                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10407                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10408                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10409                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10410                         return 1;
10411         }
10412
10413         /*
10414          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10415          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10416          * the values of the LMA and LME bits in the field must each be that of
10417          * the host address-space size VM-exit control.
10418          */
10419         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10420                 ia32e = (vmcs12->vm_exit_controls &
10421                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10422                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10423                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10424                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10425                         return 1;
10426         }
10427
10428         return 0;
10429 }
10430
10431 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10432 {
10433         struct vcpu_vmx *vmx = to_vmx(vcpu);
10434         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10435         struct loaded_vmcs *vmcs02;
10436         int cpu;
10437         u32 msr_entry_idx;
10438         u32 exit_qual;
10439
10440         vmcs02 = nested_get_current_vmcs02(vmx);
10441         if (!vmcs02)
10442                 return -ENOMEM;
10443
10444         enter_guest_mode(vcpu);
10445
10446         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10447                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10448
10449         cpu = get_cpu();
10450         vmx->loaded_vmcs = vmcs02;
10451         vmx_vcpu_put(vcpu);
10452         vmx_vcpu_load(vcpu, cpu);
10453         vcpu->cpu = cpu;
10454         put_cpu();
10455
10456         vmx_segment_cache_clear(vmx);
10457
10458         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10459                 leave_guest_mode(vcpu);
10460                 vmx_load_vmcs01(vcpu);
10461                 nested_vmx_entry_failure(vcpu, vmcs12,
10462                                          EXIT_REASON_INVALID_STATE, exit_qual);
10463                 return 1;
10464         }
10465
10466         nested_get_vmcs12_pages(vcpu, vmcs12);
10467
10468         msr_entry_idx = nested_vmx_load_msr(vcpu,
10469                                             vmcs12->vm_entry_msr_load_addr,
10470                                             vmcs12->vm_entry_msr_load_count);
10471         if (msr_entry_idx) {
10472                 leave_guest_mode(vcpu);
10473                 vmx_load_vmcs01(vcpu);
10474                 nested_vmx_entry_failure(vcpu, vmcs12,
10475                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10476                 return 1;
10477         }
10478
10479         vmcs12->launch_state = 1;
10480
10481         /*
10482          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10483          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10484          * returned as far as L1 is concerned. It will only return (and set
10485          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10486          */
10487         return 0;
10488 }
10489
10490 /*
10491  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10492  * for running an L2 nested guest.
10493  */
10494 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10495 {
10496         struct vmcs12 *vmcs12;
10497         struct vcpu_vmx *vmx = to_vmx(vcpu);
10498         u32 exit_qual;
10499         int ret;
10500
10501         if (!nested_vmx_check_permission(vcpu))
10502                 return 1;
10503
10504         if (!nested_vmx_check_vmcs12(vcpu))
10505                 goto out;
10506
10507         vmcs12 = get_vmcs12(vcpu);
10508
10509         if (enable_shadow_vmcs)
10510                 copy_shadow_to_vmcs12(vmx);
10511
10512         /*
10513          * The nested entry process starts with enforcing various prerequisites
10514          * on vmcs12 as required by the Intel SDM, and act appropriately when
10515          * they fail: As the SDM explains, some conditions should cause the
10516          * instruction to fail, while others will cause the instruction to seem
10517          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10518          * To speed up the normal (success) code path, we should avoid checking
10519          * for misconfigurations which will anyway be caught by the processor
10520          * when using the merged vmcs02.
10521          */
10522         if (vmcs12->launch_state == launch) {
10523                 nested_vmx_failValid(vcpu,
10524                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10525                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10526                 goto out;
10527         }
10528
10529         ret = check_vmentry_prereqs(vcpu, vmcs12);
10530         if (ret) {
10531                 nested_vmx_failValid(vcpu, ret);
10532                 goto out;
10533         }
10534
10535         /*
10536          * After this point, the trap flag no longer triggers a singlestep trap
10537          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10538          * This is not 100% correct; for performance reasons, we delegate most
10539          * of the checks on host state to the processor.  If those fail,
10540          * the singlestep trap is missed.
10541          */
10542         skip_emulated_instruction(vcpu);
10543
10544         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10545         if (ret) {
10546                 nested_vmx_entry_failure(vcpu, vmcs12,
10547                                          EXIT_REASON_INVALID_STATE, exit_qual);
10548                 return 1;
10549         }
10550
10551         /*
10552          * We're finally done with prerequisite checking, and can start with
10553          * the nested entry.
10554          */
10555
10556         ret = enter_vmx_non_root_mode(vcpu, true);
10557         if (ret)
10558                 return ret;
10559
10560         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10561                 return kvm_vcpu_halt(vcpu);
10562
10563         vmx->nested.nested_run_pending = 1;
10564
10565         return 1;
10566
10567 out:
10568         return kvm_skip_emulated_instruction(vcpu);
10569 }
10570
10571 /*
10572  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10573  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10574  * This function returns the new value we should put in vmcs12.guest_cr0.
10575  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10576  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10577  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10578  *     didn't trap the bit, because if L1 did, so would L0).
10579  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10580  *     been modified by L2, and L1 knows it. So just leave the old value of
10581  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10582  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10583  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10584  *     changed these bits, and therefore they need to be updated, but L0
10585  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10586  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10587  */
10588 static inline unsigned long
10589 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10590 {
10591         return
10592         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10593         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10594         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10595                         vcpu->arch.cr0_guest_owned_bits));
10596 }
10597
10598 static inline unsigned long
10599 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10600 {
10601         return
10602         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10603         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10604         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10605                         vcpu->arch.cr4_guest_owned_bits));
10606 }
10607
10608 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10609                                        struct vmcs12 *vmcs12)
10610 {
10611         u32 idt_vectoring;
10612         unsigned int nr;
10613
10614         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10615                 nr = vcpu->arch.exception.nr;
10616                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10617
10618                 if (kvm_exception_is_soft(nr)) {
10619                         vmcs12->vm_exit_instruction_len =
10620                                 vcpu->arch.event_exit_inst_len;
10621                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10622                 } else
10623                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10624
10625                 if (vcpu->arch.exception.has_error_code) {
10626                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10627                         vmcs12->idt_vectoring_error_code =
10628                                 vcpu->arch.exception.error_code;
10629                 }
10630
10631                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10632         } else if (vcpu->arch.nmi_injected) {
10633                 vmcs12->idt_vectoring_info_field =
10634                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10635         } else if (vcpu->arch.interrupt.pending) {
10636                 nr = vcpu->arch.interrupt.nr;
10637                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10638
10639                 if (vcpu->arch.interrupt.soft) {
10640                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10641                         vmcs12->vm_entry_instruction_len =
10642                                 vcpu->arch.event_exit_inst_len;
10643                 } else
10644                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10645
10646                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10647         }
10648 }
10649
10650 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10651 {
10652         struct vcpu_vmx *vmx = to_vmx(vcpu);
10653
10654         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10655             vmx->nested.preemption_timer_expired) {
10656                 if (vmx->nested.nested_run_pending)
10657                         return -EBUSY;
10658                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10659                 return 0;
10660         }
10661
10662         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10663                 if (vmx->nested.nested_run_pending ||
10664                     vcpu->arch.interrupt.pending)
10665                         return -EBUSY;
10666                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10667                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10668                                   INTR_INFO_VALID_MASK, 0);
10669                 /*
10670                  * The NMI-triggered VM exit counts as injection:
10671                  * clear this one and block further NMIs.
10672                  */
10673                 vcpu->arch.nmi_pending = 0;
10674                 vmx_set_nmi_mask(vcpu, true);
10675                 return 0;
10676         }
10677
10678         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10679             nested_exit_on_intr(vcpu)) {
10680                 if (vmx->nested.nested_run_pending)
10681                         return -EBUSY;
10682                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10683                 return 0;
10684         }
10685
10686         vmx_complete_nested_posted_interrupt(vcpu);
10687         return 0;
10688 }
10689
10690 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10691 {
10692         ktime_t remaining =
10693                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10694         u64 value;
10695
10696         if (ktime_to_ns(remaining) <= 0)
10697                 return 0;
10698
10699         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10700         do_div(value, 1000000);
10701         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10702 }
10703
10704 /*
10705  * Update the guest state fields of vmcs12 to reflect changes that
10706  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10707  * VM-entry controls is also updated, since this is really a guest
10708  * state bit.)
10709  */
10710 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10711 {
10712         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10713         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10714
10715         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10716         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10717         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10718
10719         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10720         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10721         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10722         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10723         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10724         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10725         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10726         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10727         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10728         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10729         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10730         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10731         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10732         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10733         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10734         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10735         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10736         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10737         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10738         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10739         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10740         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10741         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10742         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10743         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10744         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10745         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10746         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10747         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10748         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10749         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10750         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10751         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10752         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10753         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10754         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10755
10756         vmcs12->guest_interruptibility_info =
10757                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10758         vmcs12->guest_pending_dbg_exceptions =
10759                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10760         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10761                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10762         else
10763                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10764
10765         if (nested_cpu_has_preemption_timer(vmcs12)) {
10766                 if (vmcs12->vm_exit_controls &
10767                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10768                         vmcs12->vmx_preemption_timer_value =
10769                                 vmx_get_preemption_timer_value(vcpu);
10770                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10771         }
10772
10773         /*
10774          * In some cases (usually, nested EPT), L2 is allowed to change its
10775          * own CR3 without exiting. If it has changed it, we must keep it.
10776          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10777          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10778          *
10779          * Additionally, restore L2's PDPTR to vmcs12.
10780          */
10781         if (enable_ept) {
10782                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10783                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10784                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10785                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10786                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10787         }
10788
10789         if (nested_cpu_has_ept(vmcs12))
10790                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10791
10792         if (nested_cpu_has_vid(vmcs12))
10793                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10794
10795         vmcs12->vm_entry_controls =
10796                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10797                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10798
10799         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10800                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10801                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10802         }
10803
10804         /* TODO: These cannot have changed unless we have MSR bitmaps and
10805          * the relevant bit asks not to trap the change */
10806         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10807                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10808         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10809                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10810         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10811         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10812         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10813         if (kvm_mpx_supported())
10814                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10815         if (nested_cpu_has_xsaves(vmcs12))
10816                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10817 }
10818
10819 /*
10820  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10821  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10822  * and this function updates it to reflect the changes to the guest state while
10823  * L2 was running (and perhaps made some exits which were handled directly by L0
10824  * without going back to L1), and to reflect the exit reason.
10825  * Note that we do not have to copy here all VMCS fields, just those that
10826  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10827  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10828  * which already writes to vmcs12 directly.
10829  */
10830 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10831                            u32 exit_reason, u32 exit_intr_info,
10832                            unsigned long exit_qualification)
10833 {
10834         /* update guest state fields: */
10835         sync_vmcs12(vcpu, vmcs12);
10836
10837         /* update exit information fields: */
10838
10839         vmcs12->vm_exit_reason = exit_reason;
10840         vmcs12->exit_qualification = exit_qualification;
10841
10842         vmcs12->vm_exit_intr_info = exit_intr_info;
10843         if ((vmcs12->vm_exit_intr_info &
10844              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10845             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10846                 vmcs12->vm_exit_intr_error_code =
10847                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10848         vmcs12->idt_vectoring_info_field = 0;
10849         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10850         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10851
10852         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10853                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10854                  * instead of reading the real value. */
10855                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10856
10857                 /*
10858                  * Transfer the event that L0 or L1 may wanted to inject into
10859                  * L2 to IDT_VECTORING_INFO_FIELD.
10860                  */
10861                 vmcs12_save_pending_event(vcpu, vmcs12);
10862         }
10863
10864         /*
10865          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10866          * preserved above and would only end up incorrectly in L1.
10867          */
10868         vcpu->arch.nmi_injected = false;
10869         kvm_clear_exception_queue(vcpu);
10870         kvm_clear_interrupt_queue(vcpu);
10871 }
10872
10873 /*
10874  * A part of what we need to when the nested L2 guest exits and we want to
10875  * run its L1 parent, is to reset L1's guest state to the host state specified
10876  * in vmcs12.
10877  * This function is to be called not only on normal nested exit, but also on
10878  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10879  * Failures During or After Loading Guest State").
10880  * This function should be called when the active VMCS is L1's (vmcs01).
10881  */
10882 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10883                                    struct vmcs12 *vmcs12)
10884 {
10885         struct kvm_segment seg;
10886         u32 entry_failure_code;
10887
10888         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10889                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10890         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10891                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10892         else
10893                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10894         vmx_set_efer(vcpu, vcpu->arch.efer);
10895
10896         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10897         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10898         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10899         /*
10900          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10901          * actually changed, because vmx_set_cr0 refers to efer set above.
10902          *
10903          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10904          * (KVM doesn't change it);
10905          */
10906         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10907         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10908
10909         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10910         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10911         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10912
10913         nested_ept_uninit_mmu_context(vcpu);
10914
10915         /*
10916          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10917          * couldn't have changed.
10918          */
10919         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10920                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10921
10922         if (!enable_ept)
10923                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10924
10925         if (enable_vpid) {
10926                 /*
10927                  * Trivially support vpid by letting L2s share their parent
10928                  * L1's vpid. TODO: move to a more elaborate solution, giving
10929                  * each L2 its own vpid and exposing the vpid feature to L1.
10930                  */
10931                 vmx_flush_tlb(vcpu);
10932         }
10933
10934
10935         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10936         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10937         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10938         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10939         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10940
10941         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10942         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10943                 vmcs_write64(GUEST_BNDCFGS, 0);
10944
10945         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10946                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10947                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10948         }
10949         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10950                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10951                         vmcs12->host_ia32_perf_global_ctrl);
10952
10953         /* Set L1 segment info according to Intel SDM
10954             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10955         seg = (struct kvm_segment) {
10956                 .base = 0,
10957                 .limit = 0xFFFFFFFF,
10958                 .selector = vmcs12->host_cs_selector,
10959                 .type = 11,
10960                 .present = 1,
10961                 .s = 1,
10962                 .g = 1
10963         };
10964         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10965                 seg.l = 1;
10966         else
10967                 seg.db = 1;
10968         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10969         seg = (struct kvm_segment) {
10970                 .base = 0,
10971                 .limit = 0xFFFFFFFF,
10972                 .type = 3,
10973                 .present = 1,
10974                 .s = 1,
10975                 .db = 1,
10976                 .g = 1
10977         };
10978         seg.selector = vmcs12->host_ds_selector;
10979         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10980         seg.selector = vmcs12->host_es_selector;
10981         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10982         seg.selector = vmcs12->host_ss_selector;
10983         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10984         seg.selector = vmcs12->host_fs_selector;
10985         seg.base = vmcs12->host_fs_base;
10986         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10987         seg.selector = vmcs12->host_gs_selector;
10988         seg.base = vmcs12->host_gs_base;
10989         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10990         seg = (struct kvm_segment) {
10991                 .base = vmcs12->host_tr_base,
10992                 .limit = 0x67,
10993                 .selector = vmcs12->host_tr_selector,
10994                 .type = 11,
10995                 .present = 1
10996         };
10997         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10998
10999         kvm_set_dr(vcpu, 7, 0x400);
11000         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11001
11002         if (cpu_has_vmx_msr_bitmap())
11003                 vmx_set_msr_bitmap(vcpu);
11004
11005         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11006                                 vmcs12->vm_exit_msr_load_count))
11007                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11008 }
11009
11010 /*
11011  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11012  * and modify vmcs12 to make it see what it would expect to see there if
11013  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11014  */
11015 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11016                               u32 exit_intr_info,
11017                               unsigned long exit_qualification)
11018 {
11019         struct vcpu_vmx *vmx = to_vmx(vcpu);
11020         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11021         u32 vm_inst_error = 0;
11022
11023         /* trying to cancel vmlaunch/vmresume is a bug */
11024         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11025
11026         leave_guest_mode(vcpu);
11027         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11028                        exit_qualification);
11029
11030         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11031                                  vmcs12->vm_exit_msr_store_count))
11032                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11033
11034         if (unlikely(vmx->fail))
11035                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11036
11037         vmx_load_vmcs01(vcpu);
11038
11039         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11040             && nested_exit_intr_ack_set(vcpu)) {
11041                 int irq = kvm_cpu_get_interrupt(vcpu);
11042                 WARN_ON(irq < 0);
11043                 vmcs12->vm_exit_intr_info = irq |
11044                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11045         }
11046
11047         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11048                                        vmcs12->exit_qualification,
11049                                        vmcs12->idt_vectoring_info_field,
11050                                        vmcs12->vm_exit_intr_info,
11051                                        vmcs12->vm_exit_intr_error_code,
11052                                        KVM_ISA_VMX);
11053
11054         vm_entry_controls_reset_shadow(vmx);
11055         vm_exit_controls_reset_shadow(vmx);
11056         vmx_segment_cache_clear(vmx);
11057
11058         /* if no vmcs02 cache requested, remove the one we used */
11059         if (VMCS02_POOL_SIZE == 0)
11060                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11061
11062         load_vmcs12_host_state(vcpu, vmcs12);
11063
11064         /* Update any VMCS fields that might have changed while L2 ran */
11065         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11066         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11067         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11068         if (vmx->hv_deadline_tsc == -1)
11069                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11070                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11071         else
11072                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11073                               PIN_BASED_VMX_PREEMPTION_TIMER);
11074         if (kvm_has_tsc_control)
11075                 decache_tsc_multiplier(vmx);
11076
11077         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11078                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11079                 vmx_set_virtual_x2apic_mode(vcpu,
11080                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11081         }
11082
11083         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11084         vmx->host_rsp = 0;
11085
11086         /* Unpin physical memory we referred to in vmcs02 */
11087         if (vmx->nested.apic_access_page) {
11088                 nested_release_page(vmx->nested.apic_access_page);
11089                 vmx->nested.apic_access_page = NULL;
11090         }
11091         if (vmx->nested.virtual_apic_page) {
11092                 nested_release_page(vmx->nested.virtual_apic_page);
11093                 vmx->nested.virtual_apic_page = NULL;
11094         }
11095         if (vmx->nested.pi_desc_page) {
11096                 kunmap(vmx->nested.pi_desc_page);
11097                 nested_release_page(vmx->nested.pi_desc_page);
11098                 vmx->nested.pi_desc_page = NULL;
11099                 vmx->nested.pi_desc = NULL;
11100         }
11101
11102         /*
11103          * We are now running in L2, mmu_notifier will force to reload the
11104          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11105          */
11106         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11107
11108         /*
11109          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11110          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11111          * success or failure flag accordingly.
11112          */
11113         if (unlikely(vmx->fail)) {
11114                 vmx->fail = 0;
11115                 nested_vmx_failValid(vcpu, vm_inst_error);
11116         } else
11117                 nested_vmx_succeed(vcpu);
11118         if (enable_shadow_vmcs)
11119                 vmx->nested.sync_shadow_vmcs = true;
11120
11121         /* in case we halted in L2 */
11122         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11123 }
11124
11125 /*
11126  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11127  */
11128 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11129 {
11130         if (is_guest_mode(vcpu))
11131                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11132         free_nested(to_vmx(vcpu));
11133 }
11134
11135 /*
11136  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11137  * 23.7 "VM-entry failures during or after loading guest state" (this also
11138  * lists the acceptable exit-reason and exit-qualification parameters).
11139  * It should only be called before L2 actually succeeded to run, and when
11140  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11141  */
11142 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11143                         struct vmcs12 *vmcs12,
11144                         u32 reason, unsigned long qualification)
11145 {
11146         load_vmcs12_host_state(vcpu, vmcs12);
11147         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11148         vmcs12->exit_qualification = qualification;
11149         nested_vmx_succeed(vcpu);
11150         if (enable_shadow_vmcs)
11151                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11152 }
11153
11154 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11155                                struct x86_instruction_info *info,
11156                                enum x86_intercept_stage stage)
11157 {
11158         return X86EMUL_CONTINUE;
11159 }
11160
11161 #ifdef CONFIG_X86_64
11162 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11163 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11164                                   u64 divisor, u64 *result)
11165 {
11166         u64 low = a << shift, high = a >> (64 - shift);
11167
11168         /* To avoid the overflow on divq */
11169         if (high >= divisor)
11170                 return 1;
11171
11172         /* Low hold the result, high hold rem which is discarded */
11173         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11174             "rm" (divisor), "0" (low), "1" (high));
11175         *result = low;
11176
11177         return 0;
11178 }
11179
11180 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11181 {
11182         struct vcpu_vmx *vmx = to_vmx(vcpu);
11183         u64 tscl = rdtsc();
11184         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11185         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11186
11187         /* Convert to host delta tsc if tsc scaling is enabled */
11188         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11189                         u64_shl_div_u64(delta_tsc,
11190                                 kvm_tsc_scaling_ratio_frac_bits,
11191                                 vcpu->arch.tsc_scaling_ratio,
11192                                 &delta_tsc))
11193                 return -ERANGE;
11194
11195         /*
11196          * If the delta tsc can't fit in the 32 bit after the multi shift,
11197          * we can't use the preemption timer.
11198          * It's possible that it fits on later vmentries, but checking
11199          * on every vmentry is costly so we just use an hrtimer.
11200          */
11201         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11202                 return -ERANGE;
11203
11204         vmx->hv_deadline_tsc = tscl + delta_tsc;
11205         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11206                         PIN_BASED_VMX_PREEMPTION_TIMER);
11207         return 0;
11208 }
11209
11210 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11211 {
11212         struct vcpu_vmx *vmx = to_vmx(vcpu);
11213         vmx->hv_deadline_tsc = -1;
11214         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11215                         PIN_BASED_VMX_PREEMPTION_TIMER);
11216 }
11217 #endif
11218
11219 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11220 {
11221         if (ple_gap)
11222                 shrink_ple_window(vcpu);
11223 }
11224
11225 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11226                                      struct kvm_memory_slot *slot)
11227 {
11228         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11229         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11230 }
11231
11232 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11233                                        struct kvm_memory_slot *slot)
11234 {
11235         kvm_mmu_slot_set_dirty(kvm, slot);
11236 }
11237
11238 static void vmx_flush_log_dirty(struct kvm *kvm)
11239 {
11240         kvm_flush_pml_buffers(kvm);
11241 }
11242
11243 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11244                                            struct kvm_memory_slot *memslot,
11245                                            gfn_t offset, unsigned long mask)
11246 {
11247         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11248 }
11249
11250 /*
11251  * This routine does the following things for vCPU which is going
11252  * to be blocked if VT-d PI is enabled.
11253  * - Store the vCPU to the wakeup list, so when interrupts happen
11254  *   we can find the right vCPU to wake up.
11255  * - Change the Posted-interrupt descriptor as below:
11256  *      'NDST' <-- vcpu->pre_pcpu
11257  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11258  * - If 'ON' is set during this process, which means at least one
11259  *   interrupt is posted for this vCPU, we cannot block it, in
11260  *   this case, return 1, otherwise, return 0.
11261  *
11262  */
11263 static int pi_pre_block(struct kvm_vcpu *vcpu)
11264 {
11265         unsigned long flags;
11266         unsigned int dest;
11267         struct pi_desc old, new;
11268         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11269
11270         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11271                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11272                 !kvm_vcpu_apicv_active(vcpu))
11273                 return 0;
11274
11275         vcpu->pre_pcpu = vcpu->cpu;
11276         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11277                           vcpu->pre_pcpu), flags);
11278         list_add_tail(&vcpu->blocked_vcpu_list,
11279                       &per_cpu(blocked_vcpu_on_cpu,
11280                       vcpu->pre_pcpu));
11281         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11282                                vcpu->pre_pcpu), flags);
11283
11284         do {
11285                 old.control = new.control = pi_desc->control;
11286
11287                 /*
11288                  * We should not block the vCPU if
11289                  * an interrupt is posted for it.
11290                  */
11291                 if (pi_test_on(pi_desc) == 1) {
11292                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11293                                           vcpu->pre_pcpu), flags);
11294                         list_del(&vcpu->blocked_vcpu_list);
11295                         spin_unlock_irqrestore(
11296                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11297                                         vcpu->pre_pcpu), flags);
11298                         vcpu->pre_pcpu = -1;
11299
11300                         return 1;
11301                 }
11302
11303                 WARN((pi_desc->sn == 1),
11304                      "Warning: SN field of posted-interrupts "
11305                      "is set before blocking\n");
11306
11307                 /*
11308                  * Since vCPU can be preempted during this process,
11309                  * vcpu->cpu could be different with pre_pcpu, we
11310                  * need to set pre_pcpu as the destination of wakeup
11311                  * notification event, then we can find the right vCPU
11312                  * to wakeup in wakeup handler if interrupts happen
11313                  * when the vCPU is in blocked state.
11314                  */
11315                 dest = cpu_physical_id(vcpu->pre_pcpu);
11316
11317                 if (x2apic_enabled())
11318                         new.ndst = dest;
11319                 else
11320                         new.ndst = (dest << 8) & 0xFF00;
11321
11322                 /* set 'NV' to 'wakeup vector' */
11323                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11324         } while (cmpxchg(&pi_desc->control, old.control,
11325                         new.control) != old.control);
11326
11327         return 0;
11328 }
11329
11330 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11331 {
11332         if (pi_pre_block(vcpu))
11333                 return 1;
11334
11335         if (kvm_lapic_hv_timer_in_use(vcpu))
11336                 kvm_lapic_switch_to_sw_timer(vcpu);
11337
11338         return 0;
11339 }
11340
11341 static void pi_post_block(struct kvm_vcpu *vcpu)
11342 {
11343         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11344         struct pi_desc old, new;
11345         unsigned int dest;
11346         unsigned long flags;
11347
11348         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11349                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11350                 !kvm_vcpu_apicv_active(vcpu))
11351                 return;
11352
11353         do {
11354                 old.control = new.control = pi_desc->control;
11355
11356                 dest = cpu_physical_id(vcpu->cpu);
11357
11358                 if (x2apic_enabled())
11359                         new.ndst = dest;
11360                 else
11361                         new.ndst = (dest << 8) & 0xFF00;
11362
11363                 /* Allow posting non-urgent interrupts */
11364                 new.sn = 0;
11365
11366                 /* set 'NV' to 'notification vector' */
11367                 new.nv = POSTED_INTR_VECTOR;
11368         } while (cmpxchg(&pi_desc->control, old.control,
11369                         new.control) != old.control);
11370
11371         if(vcpu->pre_pcpu != -1) {
11372                 spin_lock_irqsave(
11373                         &per_cpu(blocked_vcpu_on_cpu_lock,
11374                         vcpu->pre_pcpu), flags);
11375                 list_del(&vcpu->blocked_vcpu_list);
11376                 spin_unlock_irqrestore(
11377                         &per_cpu(blocked_vcpu_on_cpu_lock,
11378                         vcpu->pre_pcpu), flags);
11379                 vcpu->pre_pcpu = -1;
11380         }
11381 }
11382
11383 static void vmx_post_block(struct kvm_vcpu *vcpu)
11384 {
11385         if (kvm_x86_ops->set_hv_timer)
11386                 kvm_lapic_switch_to_hv_timer(vcpu);
11387
11388         pi_post_block(vcpu);
11389 }
11390
11391 /*
11392  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11393  *
11394  * @kvm: kvm
11395  * @host_irq: host irq of the interrupt
11396  * @guest_irq: gsi of the interrupt
11397  * @set: set or unset PI
11398  * returns 0 on success, < 0 on failure
11399  */
11400 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11401                               uint32_t guest_irq, bool set)
11402 {
11403         struct kvm_kernel_irq_routing_entry *e;
11404         struct kvm_irq_routing_table *irq_rt;
11405         struct kvm_lapic_irq irq;
11406         struct kvm_vcpu *vcpu;
11407         struct vcpu_data vcpu_info;
11408         int idx, ret = -EINVAL;
11409
11410         if (!kvm_arch_has_assigned_device(kvm) ||
11411                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11412                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11413                 return 0;
11414
11415         idx = srcu_read_lock(&kvm->irq_srcu);
11416         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11417         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11418
11419         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11420                 if (e->type != KVM_IRQ_ROUTING_MSI)
11421                         continue;
11422                 /*
11423                  * VT-d PI cannot support posting multicast/broadcast
11424                  * interrupts to a vCPU, we still use interrupt remapping
11425                  * for these kind of interrupts.
11426                  *
11427                  * For lowest-priority interrupts, we only support
11428                  * those with single CPU as the destination, e.g. user
11429                  * configures the interrupts via /proc/irq or uses
11430                  * irqbalance to make the interrupts single-CPU.
11431                  *
11432                  * We will support full lowest-priority interrupt later.
11433                  */
11434
11435                 kvm_set_msi_irq(kvm, e, &irq);
11436                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11437                         /*
11438                          * Make sure the IRTE is in remapped mode if
11439                          * we don't handle it in posted mode.
11440                          */
11441                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11442                         if (ret < 0) {
11443                                 printk(KERN_INFO
11444                                    "failed to back to remapped mode, irq: %u\n",
11445                                    host_irq);
11446                                 goto out;
11447                         }
11448
11449                         continue;
11450                 }
11451
11452                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11453                 vcpu_info.vector = irq.vector;
11454
11455                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11456                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11457
11458                 if (set)
11459                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11460                 else {
11461                         /* suppress notification event before unposting */
11462                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11463                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11464                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11465                 }
11466
11467                 if (ret < 0) {
11468                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11469                                         __func__);
11470                         goto out;
11471                 }
11472         }
11473
11474         ret = 0;
11475 out:
11476         srcu_read_unlock(&kvm->irq_srcu, idx);
11477         return ret;
11478 }
11479
11480 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11481 {
11482         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11483                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11484                         FEATURE_CONTROL_LMCE;
11485         else
11486                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11487                         ~FEATURE_CONTROL_LMCE;
11488 }
11489
11490 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11491         .cpu_has_kvm_support = cpu_has_kvm_support,
11492         .disabled_by_bios = vmx_disabled_by_bios,
11493         .hardware_setup = hardware_setup,
11494         .hardware_unsetup = hardware_unsetup,
11495         .check_processor_compatibility = vmx_check_processor_compat,
11496         .hardware_enable = hardware_enable,
11497         .hardware_disable = hardware_disable,
11498         .cpu_has_accelerated_tpr = report_flexpriority,
11499         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11500
11501         .vcpu_create = vmx_create_vcpu,
11502         .vcpu_free = vmx_free_vcpu,
11503         .vcpu_reset = vmx_vcpu_reset,
11504
11505         .prepare_guest_switch = vmx_save_host_state,
11506         .vcpu_load = vmx_vcpu_load,
11507         .vcpu_put = vmx_vcpu_put,
11508
11509         .update_bp_intercept = update_exception_bitmap,
11510         .get_msr = vmx_get_msr,
11511         .set_msr = vmx_set_msr,
11512         .get_segment_base = vmx_get_segment_base,
11513         .get_segment = vmx_get_segment,
11514         .set_segment = vmx_set_segment,
11515         .get_cpl = vmx_get_cpl,
11516         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11517         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11518         .decache_cr3 = vmx_decache_cr3,
11519         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11520         .set_cr0 = vmx_set_cr0,
11521         .set_cr3 = vmx_set_cr3,
11522         .set_cr4 = vmx_set_cr4,
11523         .set_efer = vmx_set_efer,
11524         .get_idt = vmx_get_idt,
11525         .set_idt = vmx_set_idt,
11526         .get_gdt = vmx_get_gdt,
11527         .set_gdt = vmx_set_gdt,
11528         .get_dr6 = vmx_get_dr6,
11529         .set_dr6 = vmx_set_dr6,
11530         .set_dr7 = vmx_set_dr7,
11531         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11532         .cache_reg = vmx_cache_reg,
11533         .get_rflags = vmx_get_rflags,
11534         .set_rflags = vmx_set_rflags,
11535
11536         .get_pkru = vmx_get_pkru,
11537
11538         .tlb_flush = vmx_flush_tlb,
11539
11540         .run = vmx_vcpu_run,
11541         .handle_exit = vmx_handle_exit,
11542         .skip_emulated_instruction = skip_emulated_instruction,
11543         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11544         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11545         .patch_hypercall = vmx_patch_hypercall,
11546         .set_irq = vmx_inject_irq,
11547         .set_nmi = vmx_inject_nmi,
11548         .queue_exception = vmx_queue_exception,
11549         .cancel_injection = vmx_cancel_injection,
11550         .interrupt_allowed = vmx_interrupt_allowed,
11551         .nmi_allowed = vmx_nmi_allowed,
11552         .get_nmi_mask = vmx_get_nmi_mask,
11553         .set_nmi_mask = vmx_set_nmi_mask,
11554         .enable_nmi_window = enable_nmi_window,
11555         .enable_irq_window = enable_irq_window,
11556         .update_cr8_intercept = update_cr8_intercept,
11557         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11558         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11559         .get_enable_apicv = vmx_get_enable_apicv,
11560         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11561         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11562         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11563         .hwapic_irr_update = vmx_hwapic_irr_update,
11564         .hwapic_isr_update = vmx_hwapic_isr_update,
11565         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11566         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11567
11568         .set_tss_addr = vmx_set_tss_addr,
11569         .get_tdp_level = get_ept_level,
11570         .get_mt_mask = vmx_get_mt_mask,
11571
11572         .get_exit_info = vmx_get_exit_info,
11573
11574         .get_lpage_level = vmx_get_lpage_level,
11575
11576         .cpuid_update = vmx_cpuid_update,
11577
11578         .rdtscp_supported = vmx_rdtscp_supported,
11579         .invpcid_supported = vmx_invpcid_supported,
11580
11581         .set_supported_cpuid = vmx_set_supported_cpuid,
11582
11583         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11584
11585         .write_tsc_offset = vmx_write_tsc_offset,
11586
11587         .set_tdp_cr3 = vmx_set_cr3,
11588
11589         .check_intercept = vmx_check_intercept,
11590         .handle_external_intr = vmx_handle_external_intr,
11591         .mpx_supported = vmx_mpx_supported,
11592         .xsaves_supported = vmx_xsaves_supported,
11593
11594         .check_nested_events = vmx_check_nested_events,
11595
11596         .sched_in = vmx_sched_in,
11597
11598         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11599         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11600         .flush_log_dirty = vmx_flush_log_dirty,
11601         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11602
11603         .pre_block = vmx_pre_block,
11604         .post_block = vmx_post_block,
11605
11606         .pmu_ops = &intel_pmu_ops,
11607
11608         .update_pi_irte = vmx_update_pi_irte,
11609
11610 #ifdef CONFIG_X86_64
11611         .set_hv_timer = vmx_set_hv_timer,
11612         .cancel_hv_timer = vmx_cancel_hv_timer,
11613 #endif
11614
11615         .setup_mce = vmx_setup_mce,
11616 };
11617
11618 static int __init vmx_init(void)
11619 {
11620         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11621                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11622         if (r)
11623                 return r;
11624
11625 #ifdef CONFIG_KEXEC_CORE
11626         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11627                            crash_vmclear_local_loaded_vmcss);
11628 #endif
11629
11630         return 0;
11631 }
11632
11633 static void __exit vmx_exit(void)
11634 {
11635 #ifdef CONFIG_KEXEC_CORE
11636         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11637         synchronize_rcu();
11638 #endif
11639
11640         kvm_exit();
11641 }
11642
11643 module_init(vmx_init)
11644 module_exit(vmx_exit)