arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP           128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 130 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 131 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 132 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 133                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 134
 135 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 136 module_param(ple_gap, int, S_IRUGO);
 137
 138 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 139 module_param(ple_window, int, S_IRUGO);
 140
 141 /* Default doubles per-vcpu window every exit. */
 142 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 143 module_param(ple_window_grow, int, S_IRUGO);
 144
 145 /* Default resets per-vcpu window every exit to ple_window. */
 146 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 147 module_param(ple_window_shrink, int, S_IRUGO);
 148
 149 /* Default is to compute the maximum so we can never overflow. */
 150 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 151 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 152 module_param(ple_window_max, int, S_IRUGO);
 153
 154 extern const ulong vmx_return;
 155
 156 #define NR_AUTOLOAD_MSRS 8
 157 #define VMCS02_POOL_SIZE 1
 158
 159 struct vmcs {
 160         u32 revision_id;
 161         u32 abort;
 162         char data[0];
 163 };
 164
 165 /*
 166  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 167  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 168  * loaded on this CPU (so we can clear them if the CPU goes down).
 169  */
 170 struct loaded_vmcs {
 171         struct vmcs *vmcs;
 172         int cpu;
 173         int launched;
 174         struct list_head loaded_vmcss_on_cpu_link;
 175 };
 176
 177 struct shared_msr_entry {
 178         unsigned index;
 179         u64 data;
 180         u64 mask;
 181 };
 182
 183 /*
 184  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 185  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 186  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 187  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 188  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 189  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 190  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 191  * underlying hardware which will be used to run L2.
 192  * This structure is packed to ensure that its layout is identical across
 193  * machines (necessary for live migration).
 194  * If there are changes in this struct, VMCS12_REVISION must be changed.
 195  */
 196 typedef u64 natural_width;
 197 struct __packed vmcs12 {
 198         /* According to the Intel spec, a VMCS region must start with the
 199          * following two fields. Then follow implementation-specific data.
 200          */
 201         u32 revision_id;
 202         u32 abort;
 203
 204         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 205         u32 padding[7]; /* room for future expansion */
 206
 207         u64 io_bitmap_a;
 208         u64 io_bitmap_b;
 209         u64 msr_bitmap;
 210         u64 vm_exit_msr_store_addr;
 211         u64 vm_exit_msr_load_addr;
 212         u64 vm_entry_msr_load_addr;
 213         u64 tsc_offset;
 214         u64 virtual_apic_page_addr;
 215         u64 apic_access_addr;
 216         u64 ept_pointer;
 217         u64 guest_physical_address;
 218         u64 vmcs_link_pointer;
 219         u64 guest_ia32_debugctl;
 220         u64 guest_ia32_pat;
 221         u64 guest_ia32_efer;
 222         u64 guest_ia32_perf_global_ctrl;
 223         u64 guest_pdptr0;
 224         u64 guest_pdptr1;
 225         u64 guest_pdptr2;
 226         u64 guest_pdptr3;
 227         u64 guest_bndcfgs;
 228         u64 host_ia32_pat;
 229         u64 host_ia32_efer;
 230         u64 host_ia32_perf_global_ctrl;
 231         u64 padding64[8]; /* room for future expansion */
 232         /*
 233          * To allow migration of L1 (complete with its L2 guests) between
 234          * machines of different natural widths (32 or 64 bit), we cannot have
 235          * unsigned long fields with no explict size. We use u64 (aliased
 236          * natural_width) instead. Luckily, x86 is little-endian.
 237          */
 238         natural_width cr0_guest_host_mask;
 239         natural_width cr4_guest_host_mask;
 240         natural_width cr0_read_shadow;
 241         natural_width cr4_read_shadow;
 242         natural_width cr3_target_value0;
 243         natural_width cr3_target_value1;
 244         natural_width cr3_target_value2;
 245         natural_width cr3_target_value3;
 246         natural_width exit_qualification;
 247         natural_width guest_linear_address;
 248         natural_width guest_cr0;
 249         natural_width guest_cr3;
 250         natural_width guest_cr4;
 251         natural_width guest_es_base;
 252         natural_width guest_cs_base;
 253         natural_width guest_ss_base;
 254         natural_width guest_ds_base;
 255         natural_width guest_fs_base;
 256         natural_width guest_gs_base;
 257         natural_width guest_ldtr_base;
 258         natural_width guest_tr_base;
 259         natural_width guest_gdtr_base;
 260         natural_width guest_idtr_base;
 261         natural_width guest_dr7;
 262         natural_width guest_rsp;
 263         natural_width guest_rip;
 264         natural_width guest_rflags;
 265         natural_width guest_pending_dbg_exceptions;
 266         natural_width guest_sysenter_esp;
 267         natural_width guest_sysenter_eip;
 268         natural_width host_cr0;
 269         natural_width host_cr3;
 270         natural_width host_cr4;
 271         natural_width host_fs_base;
 272         natural_width host_gs_base;
 273         natural_width host_tr_base;
 274         natural_width host_gdtr_base;
 275         natural_width host_idtr_base;
 276         natural_width host_ia32_sysenter_esp;
 277         natural_width host_ia32_sysenter_eip;
 278         natural_width host_rsp;
 279         natural_width host_rip;
 280         natural_width paddingl[8]; /* room for future expansion */
 281         u32 pin_based_vm_exec_control;
 282         u32 cpu_based_vm_exec_control;
 283         u32 exception_bitmap;
 284         u32 page_fault_error_code_mask;
 285         u32 page_fault_error_code_match;
 286         u32 cr3_target_count;
 287         u32 vm_exit_controls;
 288         u32 vm_exit_msr_store_count;
 289         u32 vm_exit_msr_load_count;
 290         u32 vm_entry_controls;
 291         u32 vm_entry_msr_load_count;
 292         u32 vm_entry_intr_info_field;
 293         u32 vm_entry_exception_error_code;
 294         u32 vm_entry_instruction_len;
 295         u32 tpr_threshold;
 296         u32 secondary_vm_exec_control;
 297         u32 vm_instruction_error;
 298         u32 vm_exit_reason;
 299         u32 vm_exit_intr_info;
 300         u32 vm_exit_intr_error_code;
 301         u32 idt_vectoring_info_field;
 302         u32 idt_vectoring_error_code;
 303         u32 vm_exit_instruction_len;
 304         u32 vmx_instruction_info;
 305         u32 guest_es_limit;
 306         u32 guest_cs_limit;
 307         u32 guest_ss_limit;
 308         u32 guest_ds_limit;
 309         u32 guest_fs_limit;
 310         u32 guest_gs_limit;
 311         u32 guest_ldtr_limit;
 312         u32 guest_tr_limit;
 313         u32 guest_gdtr_limit;
 314         u32 guest_idtr_limit;
 315         u32 guest_es_ar_bytes;
 316         u32 guest_cs_ar_bytes;
 317         u32 guest_ss_ar_bytes;
 318         u32 guest_ds_ar_bytes;
 319         u32 guest_fs_ar_bytes;
 320         u32 guest_gs_ar_bytes;
 321         u32 guest_ldtr_ar_bytes;
 322         u32 guest_tr_ar_bytes;
 323         u32 guest_interruptibility_info;
 324         u32 guest_activity_state;
 325         u32 guest_sysenter_cs;
 326         u32 host_ia32_sysenter_cs;
 327         u32 vmx_preemption_timer_value;
 328         u32 padding32[7]; /* room for future expansion */
 329         u16 virtual_processor_id;
 330         u16 guest_es_selector;
 331         u16 guest_cs_selector;
 332         u16 guest_ss_selector;
 333         u16 guest_ds_selector;
 334         u16 guest_fs_selector;
 335         u16 guest_gs_selector;
 336         u16 guest_ldtr_selector;
 337         u16 guest_tr_selector;
 338         u16 host_es_selector;
 339         u16 host_cs_selector;
 340         u16 host_ss_selector;
 341         u16 host_ds_selector;
 342         u16 host_fs_selector;
 343         u16 host_gs_selector;
 344         u16 host_tr_selector;
 345 };
 346
 347 /*
 348  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 349  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 350  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 351  */
 352 #define VMCS12_REVISION 0x11e57ed0
 353
 354 /*
 355  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 356  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 357  * current implementation, 4K are reserved to avoid future complications.
 358  */
 359 #define VMCS12_SIZE 0x1000
 360
 361 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 362 struct vmcs02_list {
 363         struct list_head list;
 364         gpa_t vmptr;
 365         struct loaded_vmcs vmcs02;
 366 };
 367
 368 /*
 369  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 370  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 371  */
 372 struct nested_vmx {
 373         /* Has the level1 guest done vmxon? */
 374         bool vmxon;
 375         gpa_t vmxon_ptr;
 376
 377         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 378         gpa_t current_vmptr;
 379         /* The host-usable pointer to the above */
 380         struct page *current_vmcs12_page;
 381         struct vmcs12 *current_vmcs12;
 382         struct vmcs *current_shadow_vmcs;
 383         /*
 384          * Indicates if the shadow vmcs must be updated with the
 385          * data hold by vmcs12
 386          */
 387         bool sync_shadow_vmcs;
 388
 389         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 390         struct list_head vmcs02_pool;
 391         int vmcs02_num;
 392         u64 vmcs01_tsc_offset;
 393         /* L2 must run next, and mustn't decide to exit to L1. */
 394         bool nested_run_pending;
 395         /*
 396          * Guest pages referred to in vmcs02 with host-physical pointers, so
 397          * we must keep them pinned while L2 runs.
 398          */
 399         struct page *apic_access_page;
 400         struct page *virtual_apic_page;
 401         u64 msr_ia32_feature_control;
 402
 403         struct hrtimer preemption_timer;
 404         bool preemption_timer_expired;
 405
 406         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 407         u64 vmcs01_debugctl;
 408 };
 409
 410 #define POSTED_INTR_ON  0
 411 /* Posted-Interrupt Descriptor */
 412 struct pi_desc {
 413         u32 pir[8];     /* Posted interrupt requested */
 414         u32 control;    /* bit 0 of control is outstanding notification bit */
 415         u32 rsvd[7];
 416 } __aligned(64);
 417
 418 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 419 {
 420         return test_and_set_bit(POSTED_INTR_ON,
 421                         (unsigned long *)&pi_desc->control);
 422 }
 423
 424 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 425 {
 426         return test_and_clear_bit(POSTED_INTR_ON,
 427                         (unsigned long *)&pi_desc->control);
 428 }
 429
 430 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 431 {
 432         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 433 }
 434
 435 struct vcpu_vmx {
 436         struct kvm_vcpu       vcpu;
 437         unsigned long         host_rsp;
 438         u8                    fail;
 439         bool                  nmi_known_unmasked;
 440         u32                   exit_intr_info;
 441         u32                   idt_vectoring_info;
 442         ulong                 rflags;
 443         struct shared_msr_entry *guest_msrs;
 444         int                   nmsrs;
 445         int                   save_nmsrs;
 446         unsigned long         host_idt_base;
 447 #ifdef CONFIG_X86_64
 448         u64                   msr_host_kernel_gs_base;
 449         u64                   msr_guest_kernel_gs_base;
 450 #endif
 451         u32 vm_entry_controls_shadow;
 452         u32 vm_exit_controls_shadow;
 453         /*
 454          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 455          * non-nested (L1) guest, it always points to vmcs01. For a nested
 456          * guest (L2), it points to a different VMCS.
 457          */
 458         struct loaded_vmcs    vmcs01;
 459         struct loaded_vmcs   *loaded_vmcs;
 460         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 461         struct msr_autoload {
 462                 unsigned nr;
 463                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 464                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 465         } msr_autoload;
 466         struct {
 467                 int           loaded;
 468                 u16           fs_sel, gs_sel, ldt_sel;
 469 #ifdef CONFIG_X86_64
 470                 u16           ds_sel, es_sel;
 471 #endif
 472                 int           gs_ldt_reload_needed;
 473                 int           fs_reload_needed;
 474                 u64           msr_host_bndcfgs;
 475                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 476         } host_state;
 477         struct {
 478                 int vm86_active;
 479                 ulong save_rflags;
 480                 struct kvm_segment segs[8];
 481         } rmode;
 482         struct {
 483                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 484                 struct kvm_save_segment {
 485                         u16 selector;
 486                         unsigned long base;
 487                         u32 limit;
 488                         u32 ar;
 489                 } seg[8];
 490         } segment_cache;
 491         int vpid;
 492         bool emulation_required;
 493
 494         /* Support for vnmi-less CPUs */
 495         int soft_vnmi_blocked;
 496         ktime_t entry_time;
 497         s64 vnmi_blocked_time;
 498         u32 exit_reason;
 499
 500         bool rdtscp_enabled;
 501
 502         /* Posted interrupt descriptor */
 503         struct pi_desc pi_desc;
 504
 505         /* Support for a guest hypervisor (nested VMX) */
 506         struct nested_vmx nested;
 507
 508         /* Dynamic PLE window. */
 509         int ple_window;
 510         bool ple_window_dirty;
 511 };
 512
 513 enum segment_cache_field {
 514         SEG_FIELD_SEL = 0,
 515         SEG_FIELD_BASE = 1,
 516         SEG_FIELD_LIMIT = 2,
 517         SEG_FIELD_AR = 3,
 518
 519         SEG_FIELD_NR = 4
 520 };
 521
 522 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 523 {
 524         return container_of(vcpu, struct vcpu_vmx, vcpu);
 525 }
 526
 527 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 528 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 529 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 530                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 531
 532
 533 static unsigned long shadow_read_only_fields[] = {
 534         /*
 535          * We do NOT shadow fields that are modified when L0
 536          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 537          * VMXON...) executed by L1.
 538          * For example, VM_INSTRUCTION_ERROR is read
 539          * by L1 if a vmx instruction fails (part of the error path).
 540          * Note the code assumes this logic. If for some reason
 541          * we start shadowing these fields then we need to
 542          * force a shadow sync when L0 emulates vmx instructions
 543          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 544          * by nested_vmx_failValid)
 545          */
 546         VM_EXIT_REASON,
 547         VM_EXIT_INTR_INFO,
 548         VM_EXIT_INSTRUCTION_LEN,
 549         IDT_VECTORING_INFO_FIELD,
 550         IDT_VECTORING_ERROR_CODE,
 551         VM_EXIT_INTR_ERROR_CODE,
 552         EXIT_QUALIFICATION,
 553         GUEST_LINEAR_ADDRESS,
 554         GUEST_PHYSICAL_ADDRESS
 555 };
 556 static int max_shadow_read_only_fields =
 557         ARRAY_SIZE(shadow_read_only_fields);
 558
 559 static unsigned long shadow_read_write_fields[] = {
 560         TPR_THRESHOLD,
 561         GUEST_RIP,
 562         GUEST_RSP,
 563         GUEST_CR0,
 564         GUEST_CR3,
 565         GUEST_CR4,
 566         GUEST_INTERRUPTIBILITY_INFO,
 567         GUEST_RFLAGS,
 568         GUEST_CS_SELECTOR,
 569         GUEST_CS_AR_BYTES,
 570         GUEST_CS_LIMIT,
 571         GUEST_CS_BASE,
 572         GUEST_ES_BASE,
 573         GUEST_BNDCFGS,
 574         CR0_GUEST_HOST_MASK,
 575         CR0_READ_SHADOW,
 576         CR4_READ_SHADOW,
 577         TSC_OFFSET,
 578         EXCEPTION_BITMAP,
 579         CPU_BASED_VM_EXEC_CONTROL,
 580         VM_ENTRY_EXCEPTION_ERROR_CODE,
 581         VM_ENTRY_INTR_INFO_FIELD,
 582         VM_ENTRY_INSTRUCTION_LEN,
 583         VM_ENTRY_EXCEPTION_ERROR_CODE,
 584         HOST_FS_BASE,
 585         HOST_GS_BASE,
 586         HOST_FS_SELECTOR,
 587         HOST_GS_SELECTOR
 588 };
 589 static int max_shadow_read_write_fields =
 590         ARRAY_SIZE(shadow_read_write_fields);
 591
 592 static const unsigned short vmcs_field_to_offset_table[] = {
 593         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 594         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 595         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 596         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 597         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 598         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 599         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 600         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 601         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 602         FIELD(HOST_ES_SELECTOR, host_es_selector),
 603         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 604         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 605         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 606         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 607         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 608         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 609         FIELD64(IO_BITMAP_A, io_bitmap_a),
 610         FIELD64(IO_BITMAP_B, io_bitmap_b),
 611         FIELD64(MSR_BITMAP, msr_bitmap),
 612         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 613         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 614         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 615         FIELD64(TSC_OFFSET, tsc_offset),
 616         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 617         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 618         FIELD64(EPT_POINTER, ept_pointer),
 619         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 620         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 621         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 622         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 623         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 624         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 625         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 626         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 627         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 628         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 629         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 630         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 631         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 632         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 633         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 634         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 635         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 636         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 637         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 638         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 639         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 640         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 641         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 642         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 643         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 644         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 645         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 646         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 647         FIELD(TPR_THRESHOLD, tpr_threshold),
 648         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 649         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 650         FIELD(VM_EXIT_REASON, vm_exit_reason),
 651         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 652         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 653         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 654         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 655         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 656         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 657         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 658         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 659         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 660         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 661         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 662         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 663         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 664         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 665         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 666         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 667         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 668         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 669         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 670         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 671         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 672         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 673         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 674         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 675         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 676         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 677         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 678         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 679         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 680         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 681         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 682         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 683         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 684         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 685         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 686         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 687         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 688         FIELD(EXIT_QUALIFICATION, exit_qualification),
 689         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 690         FIELD(GUEST_CR0, guest_cr0),
 691         FIELD(GUEST_CR3, guest_cr3),
 692         FIELD(GUEST_CR4, guest_cr4),
 693         FIELD(GUEST_ES_BASE, guest_es_base),
 694         FIELD(GUEST_CS_BASE, guest_cs_base),
 695         FIELD(GUEST_SS_BASE, guest_ss_base),
 696         FIELD(GUEST_DS_BASE, guest_ds_base),
 697         FIELD(GUEST_FS_BASE, guest_fs_base),
 698         FIELD(GUEST_GS_BASE, guest_gs_base),
 699         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 700         FIELD(GUEST_TR_BASE, guest_tr_base),
 701         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 702         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 703         FIELD(GUEST_DR7, guest_dr7),
 704         FIELD(GUEST_RSP, guest_rsp),
 705         FIELD(GUEST_RIP, guest_rip),
 706         FIELD(GUEST_RFLAGS, guest_rflags),
 707         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 708         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 709         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 710         FIELD(HOST_CR0, host_cr0),
 711         FIELD(HOST_CR3, host_cr3),
 712         FIELD(HOST_CR4, host_cr4),
 713         FIELD(HOST_FS_BASE, host_fs_base),
 714         FIELD(HOST_GS_BASE, host_gs_base),
 715         FIELD(HOST_TR_BASE, host_tr_base),
 716         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 717         FIELD(HOST_IDTR_BASE, host_idtr_base),
 718         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 719         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 720         FIELD(HOST_RSP, host_rsp),
 721         FIELD(HOST_RIP, host_rip),
 722 };
 723
 724 static inline short vmcs_field_to_offset(unsigned long field)
 725 {
 726         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 727
 728         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 729             vmcs_field_to_offset_table[field] == 0)
 730                 return -ENOENT;
 731
 732         return vmcs_field_to_offset_table[field];
 733 }
 734
 735 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 736 {
 737         return to_vmx(vcpu)->nested.current_vmcs12;
 738 }
 739
 740 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 741 {
 742         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 743         if (is_error_page(page))
 744                 return NULL;
 745
 746         return page;
 747 }
 748
 749 static void nested_release_page(struct page *page)
 750 {
 751         kvm_release_page_dirty(page);
 752 }
 753
 754 static void nested_release_page_clean(struct page *page)
 755 {
 756         kvm_release_page_clean(page);
 757 }
 758
 759 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 760 static u64 construct_eptp(unsigned long root_hpa);
 761 static void kvm_cpu_vmxon(u64 addr);
 762 static void kvm_cpu_vmxoff(void);
 763 static bool vmx_mpx_supported(void);
 764 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 765 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 766                             struct kvm_segment *var, int seg);
 767 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 768                             struct kvm_segment *var, int seg);
 769 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 770 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 771 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 772 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 773 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 774 static int alloc_identity_pagetable(struct kvm *kvm);
 775
 776 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 777 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 778 /*
 779  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 780  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 781  */
 782 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 783 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 784
 785 static unsigned long *vmx_io_bitmap_a;
 786 static unsigned long *vmx_io_bitmap_b;
 787 static unsigned long *vmx_msr_bitmap_legacy;
 788 static unsigned long *vmx_msr_bitmap_longmode;
 789 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 790 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 791 static unsigned long *vmx_vmread_bitmap;
 792 static unsigned long *vmx_vmwrite_bitmap;
 793
 794 static bool cpu_has_load_ia32_efer;
 795 static bool cpu_has_load_perf_global_ctrl;
 796
 797 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 798 static DEFINE_SPINLOCK(vmx_vpid_lock);
 799
 800 static struct vmcs_config {
 801         int size;
 802         int order;
 803         u32 revision_id;
 804         u32 pin_based_exec_ctrl;
 805         u32 cpu_based_exec_ctrl;
 806         u32 cpu_based_2nd_exec_ctrl;
 807         u32 vmexit_ctrl;
 808         u32 vmentry_ctrl;
 809 } vmcs_config;
 810
 811 static struct vmx_capability {
 812         u32 ept;
 813         u32 vpid;
 814 } vmx_capability;
 815
 816 #define VMX_SEGMENT_FIELD(seg)                                  \
 817         [VCPU_SREG_##seg] = {                                   \
 818                 .selector = GUEST_##seg##_SELECTOR,             \
 819                 .base = GUEST_##seg##_BASE,                     \
 820                 .limit = GUEST_##seg##_LIMIT,                   \
 821                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 822         }
 823
 824 static const struct kvm_vmx_segment_field {
 825         unsigned selector;
 826         unsigned base;
 827         unsigned limit;
 828         unsigned ar_bytes;
 829 } kvm_vmx_segment_fields[] = {
 830         VMX_SEGMENT_FIELD(CS),
 831         VMX_SEGMENT_FIELD(DS),
 832         VMX_SEGMENT_FIELD(ES),
 833         VMX_SEGMENT_FIELD(FS),
 834         VMX_SEGMENT_FIELD(GS),
 835         VMX_SEGMENT_FIELD(SS),
 836         VMX_SEGMENT_FIELD(TR),
 837         VMX_SEGMENT_FIELD(LDTR),
 838 };
 839
 840 static u64 host_efer;
 841
 842 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 843
 844 /*
 845  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 846  * away by decrementing the array size.
 847  */
 848 static const u32 vmx_msr_index[] = {
 849 #ifdef CONFIG_X86_64
 850         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 851 #endif
 852         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 853 };
 854
 855 static inline bool is_page_fault(u32 intr_info)
 856 {
 857         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 858                              INTR_INFO_VALID_MASK)) ==
 859                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 860 }
 861
 862 static inline bool is_no_device(u32 intr_info)
 863 {
 864         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 865                              INTR_INFO_VALID_MASK)) ==
 866                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 867 }
 868
 869 static inline bool is_invalid_opcode(u32 intr_info)
 870 {
 871         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 872                              INTR_INFO_VALID_MASK)) ==
 873                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 874 }
 875
 876 static inline bool is_external_interrupt(u32 intr_info)
 877 {
 878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 879                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static inline bool is_machine_check(u32 intr_info)
 883 {
 884         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 885                              INTR_INFO_VALID_MASK)) ==
 886                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 887 }
 888
 889 static inline bool cpu_has_vmx_msr_bitmap(void)
 890 {
 891         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 892 }
 893
 894 static inline bool cpu_has_vmx_tpr_shadow(void)
 895 {
 896         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 897 }
 898
 899 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 900 {
 901         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 902 }
 903
 904 static inline bool cpu_has_secondary_exec_ctrls(void)
 905 {
 906         return vmcs_config.cpu_based_exec_ctrl &
 907                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 908 }
 909
 910 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 911 {
 912         return vmcs_config.cpu_based_2nd_exec_ctrl &
 913                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 914 }
 915
 916 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 917 {
 918         return vmcs_config.cpu_based_2nd_exec_ctrl &
 919                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 920 }
 921
 922 static inline bool cpu_has_vmx_apic_register_virt(void)
 923 {
 924         return vmcs_config.cpu_based_2nd_exec_ctrl &
 925                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 926 }
 927
 928 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 929 {
 930         return vmcs_config.cpu_based_2nd_exec_ctrl &
 931                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 932 }
 933
 934 static inline bool cpu_has_vmx_posted_intr(void)
 935 {
 936         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 937 }
 938
 939 static inline bool cpu_has_vmx_apicv(void)
 940 {
 941         return cpu_has_vmx_apic_register_virt() &&
 942                 cpu_has_vmx_virtual_intr_delivery() &&
 943                 cpu_has_vmx_posted_intr();
 944 }
 945
 946 static inline bool cpu_has_vmx_flexpriority(void)
 947 {
 948         return cpu_has_vmx_tpr_shadow() &&
 949                 cpu_has_vmx_virtualize_apic_accesses();
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_execute_only(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 958 {
 959         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_eptp_writeback(void)
 963 {
 964         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_ept_2m_page(void)
 968 {
 969         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_ept_1g_page(void)
 973 {
 974         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept_4levels(void)
 978 {
 979         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 980 }
 981
 982 static inline bool cpu_has_vmx_ept_ad_bits(void)
 983 {
 984         return vmx_capability.ept & VMX_EPT_AD_BIT;
 985 }
 986
 987 static inline bool cpu_has_vmx_invept_context(void)
 988 {
 989         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 990 }
 991
 992 static inline bool cpu_has_vmx_invept_global(void)
 993 {
 994         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 995 }
 996
 997 static inline bool cpu_has_vmx_invvpid_single(void)
 998 {
 999         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1000 }
1001
1002 static inline bool cpu_has_vmx_invvpid_global(void)
1003 {
1004         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept(void)
1008 {
1009         return vmcs_config.cpu_based_2nd_exec_ctrl &
1010                 SECONDARY_EXEC_ENABLE_EPT;
1011 }
1012
1013 static inline bool cpu_has_vmx_unrestricted_guest(void)
1014 {
1015         return vmcs_config.cpu_based_2nd_exec_ctrl &
1016                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1017 }
1018
1019 static inline bool cpu_has_vmx_ple(void)
1020 {
1021         return vmcs_config.cpu_based_2nd_exec_ctrl &
1022                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1023 }
1024
1025 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1026 {
1027         return flexpriority_enabled && irqchip_in_kernel(kvm);
1028 }
1029
1030 static inline bool cpu_has_vmx_vpid(void)
1031 {
1032         return vmcs_config.cpu_based_2nd_exec_ctrl &
1033                 SECONDARY_EXEC_ENABLE_VPID;
1034 }
1035
1036 static inline bool cpu_has_vmx_rdtscp(void)
1037 {
1038         return vmcs_config.cpu_based_2nd_exec_ctrl &
1039                 SECONDARY_EXEC_RDTSCP;
1040 }
1041
1042 static inline bool cpu_has_vmx_invpcid(void)
1043 {
1044         return vmcs_config.cpu_based_2nd_exec_ctrl &
1045                 SECONDARY_EXEC_ENABLE_INVPCID;
1046 }
1047
1048 static inline bool cpu_has_virtual_nmis(void)
1049 {
1050         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1051 }
1052
1053 static inline bool cpu_has_vmx_wbinvd_exit(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_WBINVD_EXITING;
1057 }
1058
1059 static inline bool cpu_has_vmx_shadow_vmcs(void)
1060 {
1061         u64 vmx_msr;
1062         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1063         /* check if the cpu supports writing r/o exit information fields */
1064         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1065                 return false;
1066
1067         return vmcs_config.cpu_based_2nd_exec_ctrl &
1068                 SECONDARY_EXEC_SHADOW_VMCS;
1069 }
1070
1071 static inline bool report_flexpriority(void)
1072 {
1073         return flexpriority_enabled;
1074 }
1075
1076 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1077 {
1078         return vmcs12->cpu_based_vm_exec_control & bit;
1079 }
1080
1081 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1082 {
1083         return (vmcs12->cpu_based_vm_exec_control &
1084                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1085                 (vmcs12->secondary_vm_exec_control & bit);
1086 }
1087
1088 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1089 {
1090         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1094 {
1095         return vmcs12->pin_based_vm_exec_control &
1096                 PIN_BASED_VMX_PREEMPTION_TIMER;
1097 }
1098
1099 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1100 {
1101         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1102 }
1103
1104 static inline bool is_exception(u32 intr_info)
1105 {
1106         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1107                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1108 }
1109
1110 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1111                               u32 exit_intr_info,
1112                               unsigned long exit_qualification);
1113 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1114                         struct vmcs12 *vmcs12,
1115                         u32 reason, unsigned long qualification);
1116
1117 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1118 {
1119         int i;
1120
1121         for (i = 0; i < vmx->nmsrs; ++i)
1122                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1123                         return i;
1124         return -1;
1125 }
1126
1127 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1128 {
1129     struct {
1130         u64 vpid : 16;
1131         u64 rsvd : 48;
1132         u64 gva;
1133     } operand = { vpid, 0, gva };
1134
1135     asm volatile (__ex(ASM_VMX_INVVPID)
1136                   /* CF==1 or ZF==1 --> rc = -1 */
1137                   "; ja 1f ; ud2 ; 1:"
1138                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1139 }
1140
1141 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1142 {
1143         struct {
1144                 u64 eptp, gpa;
1145         } operand = {eptp, gpa};
1146
1147         asm volatile (__ex(ASM_VMX_INVEPT)
1148                         /* CF==1 or ZF==1 --> rc = -1 */
1149                         "; ja 1f ; ud2 ; 1:\n"
1150                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1151 }
1152
1153 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1154 {
1155         int i;
1156
1157         i = __find_msr_index(vmx, msr);
1158         if (i >= 0)
1159                 return &vmx->guest_msrs[i];
1160         return NULL;
1161 }
1162
1163 static void vmcs_clear(struct vmcs *vmcs)
1164 {
1165         u64 phys_addr = __pa(vmcs);
1166         u8 error;
1167
1168         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1169                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1170                       : "cc", "memory");
1171         if (error)
1172                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1173                        vmcs, phys_addr);
1174 }
1175
1176 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1177 {
1178         vmcs_clear(loaded_vmcs->vmcs);
1179         loaded_vmcs->cpu = -1;
1180         loaded_vmcs->launched = 0;
1181 }
1182
1183 static void vmcs_load(struct vmcs *vmcs)
1184 {
1185         u64 phys_addr = __pa(vmcs);
1186         u8 error;
1187
1188         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1189                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1190                         : "cc", "memory");
1191         if (error)
1192                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1193                        vmcs, phys_addr);
1194 }
1195
1196 #ifdef CONFIG_KEXEC
1197 /*
1198  * This bitmap is used to indicate whether the vmclear
1199  * operation is enabled on all cpus. All disabled by
1200  * default.
1201  */
1202 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1203
1204 static inline void crash_enable_local_vmclear(int cpu)
1205 {
1206         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1207 }
1208
1209 static inline void crash_disable_local_vmclear(int cpu)
1210 {
1211         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1212 }
1213
1214 static inline int crash_local_vmclear_enabled(int cpu)
1215 {
1216         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1217 }
1218
1219 static void crash_vmclear_local_loaded_vmcss(void)
1220 {
1221         int cpu = raw_smp_processor_id();
1222         struct loaded_vmcs *v;
1223
1224         if (!crash_local_vmclear_enabled(cpu))
1225                 return;
1226
1227         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1228                             loaded_vmcss_on_cpu_link)
1229                 vmcs_clear(v->vmcs);
1230 }
1231 #else
1232 static inline void crash_enable_local_vmclear(int cpu) { }
1233 static inline void crash_disable_local_vmclear(int cpu) { }
1234 #endif /* CONFIG_KEXEC */
1235
1236 static void __loaded_vmcs_clear(void *arg)
1237 {
1238         struct loaded_vmcs *loaded_vmcs = arg;
1239         int cpu = raw_smp_processor_id();
1240
1241         if (loaded_vmcs->cpu != cpu)
1242                 return; /* vcpu migration can race with cpu offline */
1243         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1244                 per_cpu(current_vmcs, cpu) = NULL;
1245         crash_disable_local_vmclear(cpu);
1246         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1247
1248         /*
1249          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1250          * is before setting loaded_vmcs->vcpu to -1 which is done in
1251          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1252          * then adds the vmcs into percpu list before it is deleted.
1253          */
1254         smp_wmb();
1255
1256         loaded_vmcs_init(loaded_vmcs);
1257         crash_enable_local_vmclear(cpu);
1258 }
1259
1260 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1261 {
1262         int cpu = loaded_vmcs->cpu;
1263
1264         if (cpu != -1)
1265                 smp_call_function_single(cpu,
1266                          __loaded_vmcs_clear, loaded_vmcs, 1);
1267 }
1268
1269 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1270 {
1271         if (vmx->vpid == 0)
1272                 return;
1273
1274         if (cpu_has_vmx_invvpid_single())
1275                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1276 }
1277
1278 static inline void vpid_sync_vcpu_global(void)
1279 {
1280         if (cpu_has_vmx_invvpid_global())
1281                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1282 }
1283
1284 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1285 {
1286         if (cpu_has_vmx_invvpid_single())
1287                 vpid_sync_vcpu_single(vmx);
1288         else
1289                 vpid_sync_vcpu_global();
1290 }
1291
1292 static inline void ept_sync_global(void)
1293 {
1294         if (cpu_has_vmx_invept_global())
1295                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1296 }
1297
1298 static inline void ept_sync_context(u64 eptp)
1299 {
1300         if (enable_ept) {
1301                 if (cpu_has_vmx_invept_context())
1302                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1303                 else
1304                         ept_sync_global();
1305         }
1306 }
1307
1308 static __always_inline unsigned long vmcs_readl(unsigned long field)
1309 {
1310         unsigned long value;
1311
1312         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1313                       : "=a"(value) : "d"(field) : "cc");
1314         return value;
1315 }
1316
1317 static __always_inline u16 vmcs_read16(unsigned long field)
1318 {
1319         return vmcs_readl(field);
1320 }
1321
1322 static __always_inline u32 vmcs_read32(unsigned long field)
1323 {
1324         return vmcs_readl(field);
1325 }
1326
1327 static __always_inline u64 vmcs_read64(unsigned long field)
1328 {
1329 #ifdef CONFIG_X86_64
1330         return vmcs_readl(field);
1331 #else
1332         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1333 #endif
1334 }
1335
1336 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1337 {
1338         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1339                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1340         dump_stack();
1341 }
1342
1343 static void vmcs_writel(unsigned long field, unsigned long value)
1344 {
1345         u8 error;
1346
1347         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1348                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1349         if (unlikely(error))
1350                 vmwrite_error(field, value);
1351 }
1352
1353 static void vmcs_write16(unsigned long field, u16 value)
1354 {
1355         vmcs_writel(field, value);
1356 }
1357
1358 static void vmcs_write32(unsigned long field, u32 value)
1359 {
1360         vmcs_writel(field, value);
1361 }
1362
1363 static void vmcs_write64(unsigned long field, u64 value)
1364 {
1365         vmcs_writel(field, value);
1366 #ifndef CONFIG_X86_64
1367         asm volatile ("");
1368         vmcs_writel(field+1, value >> 32);
1369 #endif
1370 }
1371
1372 static void vmcs_clear_bits(unsigned long field, u32 mask)
1373 {
1374         vmcs_writel(field, vmcs_readl(field) & ~mask);
1375 }
1376
1377 static void vmcs_set_bits(unsigned long field, u32 mask)
1378 {
1379         vmcs_writel(field, vmcs_readl(field) | mask);
1380 }
1381
1382 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1383 {
1384         vmcs_write32(VM_ENTRY_CONTROLS, val);
1385         vmx->vm_entry_controls_shadow = val;
1386 }
1387
1388 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1389 {
1390         if (vmx->vm_entry_controls_shadow != val)
1391                 vm_entry_controls_init(vmx, val);
1392 }
1393
1394 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1395 {
1396         return vmx->vm_entry_controls_shadow;
1397 }
1398
1399
1400 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1401 {
1402         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1403 }
1404
1405 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1406 {
1407         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1408 }
1409
1410 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1411 {
1412         vmcs_write32(VM_EXIT_CONTROLS, val);
1413         vmx->vm_exit_controls_shadow = val;
1414 }
1415
1416 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1417 {
1418         if (vmx->vm_exit_controls_shadow != val)
1419                 vm_exit_controls_init(vmx, val);
1420 }
1421
1422 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1423 {
1424         return vmx->vm_exit_controls_shadow;
1425 }
1426
1427
1428 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1429 {
1430         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1431 }
1432
1433 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1434 {
1435         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1436 }
1437
1438 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1439 {
1440         vmx->segment_cache.bitmask = 0;
1441 }
1442
1443 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1444                                        unsigned field)
1445 {
1446         bool ret;
1447         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1448
1449         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1450                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1451                 vmx->segment_cache.bitmask = 0;
1452         }
1453         ret = vmx->segment_cache.bitmask & mask;
1454         vmx->segment_cache.bitmask |= mask;
1455         return ret;
1456 }
1457
1458 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1459 {
1460         u16 *p = &vmx->segment_cache.seg[seg].selector;
1461
1462         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1463                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1464         return *p;
1465 }
1466
1467 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1468 {
1469         ulong *p = &vmx->segment_cache.seg[seg].base;
1470
1471         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1472                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1473         return *p;
1474 }
1475
1476 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1477 {
1478         u32 *p = &vmx->segment_cache.seg[seg].limit;
1479
1480         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1481                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1482         return *p;
1483 }
1484
1485 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1486 {
1487         u32 *p = &vmx->segment_cache.seg[seg].ar;
1488
1489         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1490                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1491         return *p;
1492 }
1493
1494 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1495 {
1496         u32 eb;
1497
1498         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1499              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1500         if ((vcpu->guest_debug &
1501              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1502             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1503                 eb |= 1u << BP_VECTOR;
1504         if (to_vmx(vcpu)->rmode.vm86_active)
1505                 eb = ~0;
1506         if (enable_ept)
1507                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1508         if (vcpu->fpu_active)
1509                 eb &= ~(1u << NM_VECTOR);
1510
1511         /* When we are running a nested L2 guest and L1 specified for it a
1512          * certain exception bitmap, we must trap the same exceptions and pass
1513          * them to L1. When running L2, we will only handle the exceptions
1514          * specified above if L1 did not want them.
1515          */
1516         if (is_guest_mode(vcpu))
1517                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1518
1519         vmcs_write32(EXCEPTION_BITMAP, eb);
1520 }
1521
1522 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1523                 unsigned long entry, unsigned long exit)
1524 {
1525         vm_entry_controls_clearbit(vmx, entry);
1526         vm_exit_controls_clearbit(vmx, exit);
1527 }
1528
1529 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1530 {
1531         unsigned i;
1532         struct msr_autoload *m = &vmx->msr_autoload;
1533
1534         switch (msr) {
1535         case MSR_EFER:
1536                 if (cpu_has_load_ia32_efer) {
1537                         clear_atomic_switch_msr_special(vmx,
1538                                         VM_ENTRY_LOAD_IA32_EFER,
1539                                         VM_EXIT_LOAD_IA32_EFER);
1540                         return;
1541                 }
1542                 break;
1543         case MSR_CORE_PERF_GLOBAL_CTRL:
1544                 if (cpu_has_load_perf_global_ctrl) {
1545                         clear_atomic_switch_msr_special(vmx,
1546                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1547                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1548                         return;
1549                 }
1550                 break;
1551         }
1552
1553         for (i = 0; i < m->nr; ++i)
1554                 if (m->guest[i].index == msr)
1555                         break;
1556
1557         if (i == m->nr)
1558                 return;
1559         --m->nr;
1560         m->guest[i] = m->guest[m->nr];
1561         m->host[i] = m->host[m->nr];
1562         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1563         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1564 }
1565
1566 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1567                 unsigned long entry, unsigned long exit,
1568                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1569                 u64 guest_val, u64 host_val)
1570 {
1571         vmcs_write64(guest_val_vmcs, guest_val);
1572         vmcs_write64(host_val_vmcs, host_val);
1573         vm_entry_controls_setbit(vmx, entry);
1574         vm_exit_controls_setbit(vmx, exit);
1575 }
1576
1577 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1578                                   u64 guest_val, u64 host_val)
1579 {
1580         unsigned i;
1581         struct msr_autoload *m = &vmx->msr_autoload;
1582
1583         switch (msr) {
1584         case MSR_EFER:
1585                 if (cpu_has_load_ia32_efer) {
1586                         add_atomic_switch_msr_special(vmx,
1587                                         VM_ENTRY_LOAD_IA32_EFER,
1588                                         VM_EXIT_LOAD_IA32_EFER,
1589                                         GUEST_IA32_EFER,
1590                                         HOST_IA32_EFER,
1591                                         guest_val, host_val);
1592                         return;
1593                 }
1594                 break;
1595         case MSR_CORE_PERF_GLOBAL_CTRL:
1596                 if (cpu_has_load_perf_global_ctrl) {
1597                         add_atomic_switch_msr_special(vmx,
1598                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1599                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1600                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1601                                         HOST_IA32_PERF_GLOBAL_CTRL,
1602                                         guest_val, host_val);
1603                         return;
1604                 }
1605                 break;
1606         }
1607
1608         for (i = 0; i < m->nr; ++i)
1609                 if (m->guest[i].index == msr)
1610                         break;
1611
1612         if (i == NR_AUTOLOAD_MSRS) {
1613                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1614                                 "Can't add msr %x\n", msr);
1615                 return;
1616         } else if (i == m->nr) {
1617                 ++m->nr;
1618                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1619                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1620         }
1621
1622         m->guest[i].index = msr;
1623         m->guest[i].value = guest_val;
1624         m->host[i].index = msr;
1625         m->host[i].value = host_val;
1626 }
1627
1628 static void reload_tss(void)
1629 {
1630         /*
1631          * VT restores TR but not its size.  Useless.
1632          */
1633         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1634         struct desc_struct *descs;
1635
1636         descs = (void *)gdt->address;
1637         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1638         load_TR_desc();
1639 }
1640
1641 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1642 {
1643         u64 guest_efer;
1644         u64 ignore_bits;
1645
1646         guest_efer = vmx->vcpu.arch.efer;
1647
1648         /*
1649          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1650          * outside long mode
1651          */
1652         ignore_bits = EFER_NX | EFER_SCE;
1653 #ifdef CONFIG_X86_64
1654         ignore_bits |= EFER_LMA | EFER_LME;
1655         /* SCE is meaningful only in long mode on Intel */
1656         if (guest_efer & EFER_LMA)
1657                 ignore_bits &= ~(u64)EFER_SCE;
1658 #endif
1659         guest_efer &= ~ignore_bits;
1660         guest_efer |= host_efer & ignore_bits;
1661         vmx->guest_msrs[efer_offset].data = guest_efer;
1662         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1663
1664         clear_atomic_switch_msr(vmx, MSR_EFER);
1665         /* On ept, can't emulate nx, and must switch nx atomically */
1666         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1667                 guest_efer = vmx->vcpu.arch.efer;
1668                 if (!(guest_efer & EFER_LMA))
1669                         guest_efer &= ~EFER_LME;
1670                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1671                 return false;
1672         }
1673
1674         return true;
1675 }
1676
1677 static unsigned long segment_base(u16 selector)
1678 {
1679         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1680         struct desc_struct *d;
1681         unsigned long table_base;
1682         unsigned long v;
1683
1684         if (!(selector & ~3))
1685                 return 0;
1686
1687         table_base = gdt->address;
1688
1689         if (selector & 4) {           /* from ldt */
1690                 u16 ldt_selector = kvm_read_ldt();
1691
1692                 if (!(ldt_selector & ~3))
1693                         return 0;
1694
1695                 table_base = segment_base(ldt_selector);
1696         }
1697         d = (struct desc_struct *)(table_base + (selector & ~7));
1698         v = get_desc_base(d);
1699 #ifdef CONFIG_X86_64
1700        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1701                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1702 #endif
1703         return v;
1704 }
1705
1706 static inline unsigned long kvm_read_tr_base(void)
1707 {
1708         u16 tr;
1709         asm("str %0" : "=g"(tr));
1710         return segment_base(tr);
1711 }
1712
1713 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1714 {
1715         struct vcpu_vmx *vmx = to_vmx(vcpu);
1716         int i;
1717
1718         if (vmx->host_state.loaded)
1719                 return;
1720
1721         vmx->host_state.loaded = 1;
1722         /*
1723          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1724          * allow segment selectors with cpl > 0 or ti == 1.
1725          */
1726         vmx->host_state.ldt_sel = kvm_read_ldt();
1727         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1728         savesegment(fs, vmx->host_state.fs_sel);
1729         if (!(vmx->host_state.fs_sel & 7)) {
1730                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1731                 vmx->host_state.fs_reload_needed = 0;
1732         } else {
1733                 vmcs_write16(HOST_FS_SELECTOR, 0);
1734                 vmx->host_state.fs_reload_needed = 1;
1735         }
1736         savesegment(gs, vmx->host_state.gs_sel);
1737         if (!(vmx->host_state.gs_sel & 7))
1738                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1739         else {
1740                 vmcs_write16(HOST_GS_SELECTOR, 0);
1741                 vmx->host_state.gs_ldt_reload_needed = 1;
1742         }
1743
1744 #ifdef CONFIG_X86_64
1745         savesegment(ds, vmx->host_state.ds_sel);
1746         savesegment(es, vmx->host_state.es_sel);
1747 #endif
1748
1749 #ifdef CONFIG_X86_64
1750         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1751         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1752 #else
1753         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1754         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1755 #endif
1756
1757 #ifdef CONFIG_X86_64
1758         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1759         if (is_long_mode(&vmx->vcpu))
1760                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1761 #endif
1762         if (boot_cpu_has(X86_FEATURE_MPX))
1763                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1764         for (i = 0; i < vmx->save_nmsrs; ++i)
1765                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1766                                    vmx->guest_msrs[i].data,
1767                                    vmx->guest_msrs[i].mask);
1768 }
1769
1770 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1771 {
1772         if (!vmx->host_state.loaded)
1773                 return;
1774
1775         ++vmx->vcpu.stat.host_state_reload;
1776         vmx->host_state.loaded = 0;
1777 #ifdef CONFIG_X86_64
1778         if (is_long_mode(&vmx->vcpu))
1779                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1780 #endif
1781         if (vmx->host_state.gs_ldt_reload_needed) {
1782                 kvm_load_ldt(vmx->host_state.ldt_sel);
1783 #ifdef CONFIG_X86_64
1784                 load_gs_index(vmx->host_state.gs_sel);
1785 #else
1786                 loadsegment(gs, vmx->host_state.gs_sel);
1787 #endif
1788         }
1789         if (vmx->host_state.fs_reload_needed)
1790                 loadsegment(fs, vmx->host_state.fs_sel);
1791 #ifdef CONFIG_X86_64
1792         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1793                 loadsegment(ds, vmx->host_state.ds_sel);
1794                 loadsegment(es, vmx->host_state.es_sel);
1795         }
1796 #endif
1797         reload_tss();
1798 #ifdef CONFIG_X86_64
1799         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1800 #endif
1801         if (vmx->host_state.msr_host_bndcfgs)
1802                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1803         /*
1804          * If the FPU is not active (through the host task or
1805          * the guest vcpu), then restore the cr0.TS bit.
1806          */
1807         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1808                 stts();
1809         load_gdt(this_cpu_ptr(&host_gdt));
1810 }
1811
1812 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1813 {
1814         preempt_disable();
1815         __vmx_load_host_state(vmx);
1816         preempt_enable();
1817 }
1818
1819 /*
1820  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1821  * vcpu mutex is already taken.
1822  */
1823 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1824 {
1825         struct vcpu_vmx *vmx = to_vmx(vcpu);
1826         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1827
1828         if (!vmm_exclusive)
1829                 kvm_cpu_vmxon(phys_addr);
1830         else if (vmx->loaded_vmcs->cpu != cpu)
1831                 loaded_vmcs_clear(vmx->loaded_vmcs);
1832
1833         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1834                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1835                 vmcs_load(vmx->loaded_vmcs->vmcs);
1836         }
1837
1838         if (vmx->loaded_vmcs->cpu != cpu) {
1839                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1840                 unsigned long sysenter_esp;
1841
1842                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1843                 local_irq_disable();
1844                 crash_disable_local_vmclear(cpu);
1845
1846                 /*
1847                  * Read loaded_vmcs->cpu should be before fetching
1848                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1849                  * See the comments in __loaded_vmcs_clear().
1850                  */
1851                 smp_rmb();
1852
1853                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1854                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1855                 crash_enable_local_vmclear(cpu);
1856                 local_irq_enable();
1857
1858                 /*
1859                  * Linux uses per-cpu TSS and GDT, so set these when switching
1860                  * processors.
1861                  */
1862                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1863                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1864
1865                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1866                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1867                 vmx->loaded_vmcs->cpu = cpu;
1868         }
1869 }
1870
1871 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1872 {
1873         __vmx_load_host_state(to_vmx(vcpu));
1874         if (!vmm_exclusive) {
1875                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1876                 vcpu->cpu = -1;
1877                 kvm_cpu_vmxoff();
1878         }
1879 }
1880
1881 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1882 {
1883         ulong cr0;
1884
1885         if (vcpu->fpu_active)
1886                 return;
1887         vcpu->fpu_active = 1;
1888         cr0 = vmcs_readl(GUEST_CR0);
1889         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1890         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1891         vmcs_writel(GUEST_CR0, cr0);
1892         update_exception_bitmap(vcpu);
1893         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1894         if (is_guest_mode(vcpu))
1895                 vcpu->arch.cr0_guest_owned_bits &=
1896                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1897         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898 }
1899
1900 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1901
1902 /*
1903  * Return the cr0 value that a nested guest would read. This is a combination
1904  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1905  * its hypervisor (cr0_read_shadow).
1906  */
1907 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1908 {
1909         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1910                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1911 }
1912 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1913 {
1914         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1915                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1916 }
1917
1918 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1919 {
1920         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1921          * set this *before* calling this function.
1922          */
1923         vmx_decache_cr0_guest_bits(vcpu);
1924         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1925         update_exception_bitmap(vcpu);
1926         vcpu->arch.cr0_guest_owned_bits = 0;
1927         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1928         if (is_guest_mode(vcpu)) {
1929                 /*
1930                  * L1's specified read shadow might not contain the TS bit,
1931                  * so now that we turned on shadowing of this bit, we need to
1932                  * set this bit of the shadow. Like in nested_vmx_run we need
1933                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1934                  * up-to-date here because we just decached cr0.TS (and we'll
1935                  * only update vmcs12->guest_cr0 on nested exit).
1936                  */
1937                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1938                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1939                         (vcpu->arch.cr0 & X86_CR0_TS);
1940                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1941         } else
1942                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1943 }
1944
1945 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1946 {
1947         unsigned long rflags, save_rflags;
1948
1949         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1950                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1951                 rflags = vmcs_readl(GUEST_RFLAGS);
1952                 if (to_vmx(vcpu)->rmode.vm86_active) {
1953                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1954                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1955                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1956                 }
1957                 to_vmx(vcpu)->rflags = rflags;
1958         }
1959         return to_vmx(vcpu)->rflags;
1960 }
1961
1962 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1963 {
1964         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1965         to_vmx(vcpu)->rflags = rflags;
1966         if (to_vmx(vcpu)->rmode.vm86_active) {
1967                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1968                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1969         }
1970         vmcs_writel(GUEST_RFLAGS, rflags);
1971 }
1972
1973 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1974 {
1975         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1976         int ret = 0;
1977
1978         if (interruptibility & GUEST_INTR_STATE_STI)
1979                 ret |= KVM_X86_SHADOW_INT_STI;
1980         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1981                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1982
1983         return ret;
1984 }
1985
1986 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1987 {
1988         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1989         u32 interruptibility = interruptibility_old;
1990
1991         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1992
1993         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1994                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1995         else if (mask & KVM_X86_SHADOW_INT_STI)
1996                 interruptibility |= GUEST_INTR_STATE_STI;
1997
1998         if ((interruptibility != interruptibility_old))
1999                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2000 }
2001
2002 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2003 {
2004         unsigned long rip;
2005
2006         rip = kvm_rip_read(vcpu);
2007         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2008         kvm_rip_write(vcpu, rip);
2009
2010         /* skipping an emulated instruction also counts */
2011         vmx_set_interrupt_shadow(vcpu, 0);
2012 }
2013
2014 /*
2015  * KVM wants to inject page-faults which it got to the guest. This function
2016  * checks whether in a nested guest, we need to inject them to L1 or L2.
2017  */
2018 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2019 {
2020         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2021
2022         if (!(vmcs12->exception_bitmap & (1u << nr)))
2023                 return 0;
2024
2025         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2026                           vmcs_read32(VM_EXIT_INTR_INFO),
2027                           vmcs_readl(EXIT_QUALIFICATION));
2028         return 1;
2029 }
2030
2031 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2032                                 bool has_error_code, u32 error_code,
2033                                 bool reinject)
2034 {
2035         struct vcpu_vmx *vmx = to_vmx(vcpu);
2036         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2037
2038         if (!reinject && is_guest_mode(vcpu) &&
2039             nested_vmx_check_exception(vcpu, nr))
2040                 return;
2041
2042         if (has_error_code) {
2043                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2044                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2045         }
2046
2047         if (vmx->rmode.vm86_active) {
2048                 int inc_eip = 0;
2049                 if (kvm_exception_is_soft(nr))
2050                         inc_eip = vcpu->arch.event_exit_inst_len;
2051                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2052                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2053                 return;
2054         }
2055
2056         if (kvm_exception_is_soft(nr)) {
2057                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2058                              vmx->vcpu.arch.event_exit_inst_len);
2059                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2060         } else
2061                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2062
2063         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2064 }
2065
2066 static bool vmx_rdtscp_supported(void)
2067 {
2068         return cpu_has_vmx_rdtscp();
2069 }
2070
2071 static bool vmx_invpcid_supported(void)
2072 {
2073         return cpu_has_vmx_invpcid() && enable_ept;
2074 }
2075
2076 /*
2077  * Swap MSR entry in host/guest MSR entry array.
2078  */
2079 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2080 {
2081         struct shared_msr_entry tmp;
2082
2083         tmp = vmx->guest_msrs[to];
2084         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2085         vmx->guest_msrs[from] = tmp;
2086 }
2087
2088 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2089 {
2090         unsigned long *msr_bitmap;
2091
2092         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2093                 if (is_long_mode(vcpu))
2094                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2095                 else
2096                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2097         } else {
2098                 if (is_long_mode(vcpu))
2099                         msr_bitmap = vmx_msr_bitmap_longmode;
2100                 else
2101                         msr_bitmap = vmx_msr_bitmap_legacy;
2102         }
2103
2104         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2105 }
2106
2107 /*
2108  * Set up the vmcs to automatically save and restore system
2109  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2110  * mode, as fiddling with msrs is very expensive.
2111  */
2112 static void setup_msrs(struct vcpu_vmx *vmx)
2113 {
2114         int save_nmsrs, index;
2115
2116         save_nmsrs = 0;
2117 #ifdef CONFIG_X86_64
2118         if (is_long_mode(&vmx->vcpu)) {
2119                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2120                 if (index >= 0)
2121                         move_msr_up(vmx, index, save_nmsrs++);
2122                 index = __find_msr_index(vmx, MSR_LSTAR);
2123                 if (index >= 0)
2124                         move_msr_up(vmx, index, save_nmsrs++);
2125                 index = __find_msr_index(vmx, MSR_CSTAR);
2126                 if (index >= 0)
2127                         move_msr_up(vmx, index, save_nmsrs++);
2128                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2129                 if (index >= 0 && vmx->rdtscp_enabled)
2130                         move_msr_up(vmx, index, save_nmsrs++);
2131                 /*
2132                  * MSR_STAR is only needed on long mode guests, and only
2133                  * if efer.sce is enabled.
2134                  */
2135                 index = __find_msr_index(vmx, MSR_STAR);
2136                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2137                         move_msr_up(vmx, index, save_nmsrs++);
2138         }
2139 #endif
2140         index = __find_msr_index(vmx, MSR_EFER);
2141         if (index >= 0 && update_transition_efer(vmx, index))
2142                 move_msr_up(vmx, index, save_nmsrs++);
2143
2144         vmx->save_nmsrs = save_nmsrs;
2145
2146         if (cpu_has_vmx_msr_bitmap())
2147                 vmx_set_msr_bitmap(&vmx->vcpu);
2148 }
2149
2150 /*
2151  * reads and returns guest's timestamp counter "register"
2152  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2153  */
2154 static u64 guest_read_tsc(void)
2155 {
2156         u64 host_tsc, tsc_offset;
2157
2158         rdtscll(host_tsc);
2159         tsc_offset = vmcs_read64(TSC_OFFSET);
2160         return host_tsc + tsc_offset;
2161 }
2162
2163 /*
2164  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2165  * counter, even if a nested guest (L2) is currently running.
2166  */
2167 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2168 {
2169         u64 tsc_offset;
2170
2171         tsc_offset = is_guest_mode(vcpu) ?
2172                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2173                 vmcs_read64(TSC_OFFSET);
2174         return host_tsc + tsc_offset;
2175 }
2176
2177 /*
2178  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2179  * software catchup for faster rates on slower CPUs.
2180  */
2181 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2182 {
2183         if (!scale)
2184                 return;
2185
2186         if (user_tsc_khz > tsc_khz) {
2187                 vcpu->arch.tsc_catchup = 1;
2188                 vcpu->arch.tsc_always_catchup = 1;
2189         } else
2190                 WARN(1, "user requested TSC rate below hardware speed\n");
2191 }
2192
2193 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2194 {
2195         return vmcs_read64(TSC_OFFSET);
2196 }
2197
2198 /*
2199  * writes 'offset' into guest's timestamp counter offset register
2200  */
2201 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2202 {
2203         if (is_guest_mode(vcpu)) {
2204                 /*
2205                  * We're here if L1 chose not to trap WRMSR to TSC. According
2206                  * to the spec, this should set L1's TSC; The offset that L1
2207                  * set for L2 remains unchanged, and still needs to be added
2208                  * to the newly set TSC to get L2's TSC.
2209                  */
2210                 struct vmcs12 *vmcs12;
2211                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2212                 /* recalculate vmcs02.TSC_OFFSET: */
2213                 vmcs12 = get_vmcs12(vcpu);
2214                 vmcs_write64(TSC_OFFSET, offset +
2215                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2216                          vmcs12->tsc_offset : 0));
2217         } else {
2218                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2219                                            vmcs_read64(TSC_OFFSET), offset);
2220                 vmcs_write64(TSC_OFFSET, offset);
2221         }
2222 }
2223
2224 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2225 {
2226         u64 offset = vmcs_read64(TSC_OFFSET);
2227
2228         vmcs_write64(TSC_OFFSET, offset + adjustment);
2229         if (is_guest_mode(vcpu)) {
2230                 /* Even when running L2, the adjustment needs to apply to L1 */
2231                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2232         } else
2233                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2234                                            offset + adjustment);
2235 }
2236
2237 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2238 {
2239         return target_tsc - native_read_tsc();
2240 }
2241
2242 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2243 {
2244         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2245         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2246 }
2247
2248 /*
2249  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2250  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2251  * all guests if the "nested" module option is off, and can also be disabled
2252  * for a single guest by disabling its VMX cpuid bit.
2253  */
2254 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2255 {
2256         return nested && guest_cpuid_has_vmx(vcpu);
2257 }
2258
2259 /*
2260  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2261  * returned for the various VMX controls MSRs when nested VMX is enabled.
2262  * The same values should also be used to verify that vmcs12 control fields are
2263  * valid during nested entry from L1 to L2.
2264  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2265  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2266  * bit in the high half is on if the corresponding bit in the control field
2267  * may be on. See also vmx_control_verify().
2268  * TODO: allow these variables to be modified (downgraded) by module options
2269  * or other means.
2270  */
2271 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2272 static u32 nested_vmx_true_procbased_ctls_low;
2273 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2274 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2275 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2276 static u32 nested_vmx_true_exit_ctls_low;
2277 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2278 static u32 nested_vmx_true_entry_ctls_low;
2279 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2280 static u32 nested_vmx_ept_caps;
2281 static __init void nested_vmx_setup_ctls_msrs(void)
2282 {
2283         /*
2284          * Note that as a general rule, the high half of the MSRs (bits in
2285          * the control fields which may be 1) should be initialized by the
2286          * intersection of the underlying hardware's MSR (i.e., features which
2287          * can be supported) and the list of features we want to expose -
2288          * because they are known to be properly supported in our code.
2289          * Also, usually, the low half of the MSRs (bits which must be 1) can
2290          * be set to 0, meaning that L1 may turn off any of these bits. The
2291          * reason is that if one of these bits is necessary, it will appear
2292          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2293          * fields of vmcs01 and vmcs02, will turn these bits off - and
2294          * nested_vmx_exit_handled() will not pass related exits to L1.
2295          * These rules have exceptions below.
2296          */
2297
2298         /* pin-based controls */
2299         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2300               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2301         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2302         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2303                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2304         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2305                 PIN_BASED_VMX_PREEMPTION_TIMER;
2306
2307         /* exit controls */
2308         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2309                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2310         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2311
2312         nested_vmx_exit_ctls_high &=
2313 #ifdef CONFIG_X86_64
2314                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2315 #endif
2316                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2317         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2318                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2319                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2320
2321         if (vmx_mpx_supported())
2322                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2323
2324         /* We support free control of debug control saving. */
2325         nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2326                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2327
2328         /* entry controls */
2329         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2330                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2331         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2332         nested_vmx_entry_ctls_high &=
2333 #ifdef CONFIG_X86_64
2334                 VM_ENTRY_IA32E_MODE |
2335 #endif
2336                 VM_ENTRY_LOAD_IA32_PAT;
2337         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2338                                        VM_ENTRY_LOAD_IA32_EFER);
2339         if (vmx_mpx_supported())
2340                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2341
2342         /* We support free control of debug control loading. */
2343         nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2344                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2345
2346         /* cpu-based controls */
2347         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2348                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2349         nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2350         nested_vmx_procbased_ctls_high &=
2351                 CPU_BASED_VIRTUAL_INTR_PENDING |
2352                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2353                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2354                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2355                 CPU_BASED_CR3_STORE_EXITING |
2356 #ifdef CONFIG_X86_64
2357                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2358 #endif
2359                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2360                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2361                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2362                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2363                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2364         /*
2365          * We can allow some features even when not supported by the
2366          * hardware. For example, L1 can specify an MSR bitmap - and we
2367          * can use it to avoid exits to L1 - even when L0 runs L2
2368          * without MSR bitmaps.
2369          */
2370         nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2371                 CPU_BASED_USE_MSR_BITMAPS;
2372
2373         /* We support free control of CR3 access interception. */
2374         nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2375                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2376
2377         /* secondary cpu-based controls */
2378         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2379                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2380         nested_vmx_secondary_ctls_low = 0;
2381         nested_vmx_secondary_ctls_high &=
2382                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2383                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2384                 SECONDARY_EXEC_WBINVD_EXITING;
2385
2386         if (enable_ept) {
2387                 /* nested EPT: emulate EPT also to L1 */
2388                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2389                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2390                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2391                          VMX_EPT_INVEPT_BIT;
2392                 nested_vmx_ept_caps &= vmx_capability.ept;
2393                 /*
2394                  * For nested guests, we don't do anything specific
2395                  * for single context invalidation. Hence, only advertise
2396                  * support for global context invalidation.
2397                  */
2398                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2399         } else
2400                 nested_vmx_ept_caps = 0;
2401
2402         /* miscellaneous data */
2403         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2404         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2405         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2406                 VMX_MISC_ACTIVITY_HLT;
2407         nested_vmx_misc_high = 0;
2408 }
2409
2410 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2411 {
2412         /*
2413          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2414          */
2415         return ((control & high) | low) == control;
2416 }
2417
2418 static inline u64 vmx_control_msr(u32 low, u32 high)
2419 {
2420         return low | ((u64)high << 32);
2421 }
2422
2423 /* Returns 0 on success, non-0 otherwise. */
2424 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2425 {
2426         switch (msr_index) {
2427         case MSR_IA32_VMX_BASIC:
2428                 /*
2429                  * This MSR reports some information about VMX support. We
2430                  * should return information about the VMX we emulate for the
2431                  * guest, and the VMCS structure we give it - not about the
2432                  * VMX support of the underlying hardware.
2433                  */
2434                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2435                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2436                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2437                 break;
2438         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2439         case MSR_IA32_VMX_PINBASED_CTLS:
2440                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2441                                         nested_vmx_pinbased_ctls_high);
2442                 break;
2443         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2444                 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2445                                         nested_vmx_procbased_ctls_high);
2446                 break;
2447         case MSR_IA32_VMX_PROCBASED_CTLS:
2448                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2449                                         nested_vmx_procbased_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2452                 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2453                                         nested_vmx_exit_ctls_high);
2454                 break;
2455         case MSR_IA32_VMX_EXIT_CTLS:
2456                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2457                                         nested_vmx_exit_ctls_high);
2458                 break;
2459         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2460                 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2461                                         nested_vmx_entry_ctls_high);
2462                 break;
2463         case MSR_IA32_VMX_ENTRY_CTLS:
2464                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2465                                         nested_vmx_entry_ctls_high);
2466                 break;
2467         case MSR_IA32_VMX_MISC:
2468                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2469                                          nested_vmx_misc_high);
2470                 break;
2471         /*
2472          * These MSRs specify bits which the guest must keep fixed (on or off)
2473          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2474          * We picked the standard core2 setting.
2475          */
2476 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2477 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2478         case MSR_IA32_VMX_CR0_FIXED0:
2479                 *pdata = VMXON_CR0_ALWAYSON;
2480                 break;
2481         case MSR_IA32_VMX_CR0_FIXED1:
2482                 *pdata = -1ULL;
2483                 break;
2484         case MSR_IA32_VMX_CR4_FIXED0:
2485                 *pdata = VMXON_CR4_ALWAYSON;
2486                 break;
2487         case MSR_IA32_VMX_CR4_FIXED1:
2488                 *pdata = -1ULL;
2489                 break;
2490         case MSR_IA32_VMX_VMCS_ENUM:
2491                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2492                 break;
2493         case MSR_IA32_VMX_PROCBASED_CTLS2:
2494                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2495                                         nested_vmx_secondary_ctls_high);
2496                 break;
2497         case MSR_IA32_VMX_EPT_VPID_CAP:
2498                 /* Currently, no nested vpid support */
2499                 *pdata = nested_vmx_ept_caps;
2500                 break;
2501         default:
2502                 return 1;
2503         }
2504
2505         return 0;
2506 }
2507
2508 /*
2509  * Reads an msr value (of 'msr_index') into 'pdata'.
2510  * Returns 0 on success, non-0 otherwise.
2511  * Assumes vcpu_load() was already called.
2512  */
2513 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2514 {
2515         u64 data;
2516         struct shared_msr_entry *msr;
2517
2518         if (!pdata) {
2519                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2520                 return -EINVAL;
2521         }
2522
2523         switch (msr_index) {
2524 #ifdef CONFIG_X86_64
2525         case MSR_FS_BASE:
2526                 data = vmcs_readl(GUEST_FS_BASE);
2527                 break;
2528         case MSR_GS_BASE:
2529                 data = vmcs_readl(GUEST_GS_BASE);
2530                 break;
2531         case MSR_KERNEL_GS_BASE:
2532                 vmx_load_host_state(to_vmx(vcpu));
2533                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2534                 break;
2535 #endif
2536         case MSR_EFER:
2537                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2538         case MSR_IA32_TSC:
2539                 data = guest_read_tsc();
2540                 break;
2541         case MSR_IA32_SYSENTER_CS:
2542                 data = vmcs_read32(GUEST_SYSENTER_CS);
2543                 break;
2544         case MSR_IA32_SYSENTER_EIP:
2545                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2546                 break;
2547         case MSR_IA32_SYSENTER_ESP:
2548                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2549                 break;
2550         case MSR_IA32_BNDCFGS:
2551                 if (!vmx_mpx_supported())
2552                         return 1;
2553                 data = vmcs_read64(GUEST_BNDCFGS);
2554                 break;
2555         case MSR_IA32_FEATURE_CONTROL:
2556                 if (!nested_vmx_allowed(vcpu))
2557                         return 1;
2558                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2559                 break;
2560         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2561                 if (!nested_vmx_allowed(vcpu))
2562                         return 1;
2563                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2564         case MSR_TSC_AUX:
2565                 if (!to_vmx(vcpu)->rdtscp_enabled)
2566                         return 1;
2567                 /* Otherwise falls through */
2568         default:
2569                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2570                 if (msr) {
2571                         data = msr->data;
2572                         break;
2573                 }
2574                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2575         }
2576
2577         *pdata = data;
2578         return 0;
2579 }
2580
2581 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2582
2583 /*
2584  * Writes msr value into into the appropriate "register".
2585  * Returns 0 on success, non-0 otherwise.
2586  * Assumes vcpu_load() was already called.
2587  */
2588 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2589 {
2590         struct vcpu_vmx *vmx = to_vmx(vcpu);
2591         struct shared_msr_entry *msr;
2592         int ret = 0;
2593         u32 msr_index = msr_info->index;
2594         u64 data = msr_info->data;
2595
2596         switch (msr_index) {
2597         case MSR_EFER:
2598                 ret = kvm_set_msr_common(vcpu, msr_info);
2599                 break;
2600 #ifdef CONFIG_X86_64
2601         case MSR_FS_BASE:
2602                 vmx_segment_cache_clear(vmx);
2603                 vmcs_writel(GUEST_FS_BASE, data);
2604                 break;
2605         case MSR_GS_BASE:
2606                 vmx_segment_cache_clear(vmx);
2607                 vmcs_writel(GUEST_GS_BASE, data);
2608                 break;
2609         case MSR_KERNEL_GS_BASE:
2610                 vmx_load_host_state(vmx);
2611                 vmx->msr_guest_kernel_gs_base = data;
2612                 break;
2613 #endif
2614         case MSR_IA32_SYSENTER_CS:
2615                 vmcs_write32(GUEST_SYSENTER_CS, data);
2616                 break;
2617         case MSR_IA32_SYSENTER_EIP:
2618                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2619                 break;
2620         case MSR_IA32_SYSENTER_ESP:
2621                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2622                 break;
2623         case MSR_IA32_BNDCFGS:
2624                 if (!vmx_mpx_supported())
2625                         return 1;
2626                 vmcs_write64(GUEST_BNDCFGS, data);
2627                 break;
2628         case MSR_IA32_TSC:
2629                 kvm_write_tsc(vcpu, msr_info);
2630                 break;
2631         case MSR_IA32_CR_PAT:
2632                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2633                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2634                                 return 1;
2635                         vmcs_write64(GUEST_IA32_PAT, data);
2636                         vcpu->arch.pat = data;
2637                         break;
2638                 }
2639                 ret = kvm_set_msr_common(vcpu, msr_info);
2640                 break;
2641         case MSR_IA32_TSC_ADJUST:
2642                 ret = kvm_set_msr_common(vcpu, msr_info);
2643                 break;
2644         case MSR_IA32_FEATURE_CONTROL:
2645                 if (!nested_vmx_allowed(vcpu) ||
2646                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2647                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2648                         return 1;
2649                 vmx->nested.msr_ia32_feature_control = data;
2650                 if (msr_info->host_initiated && data == 0)
2651                         vmx_leave_nested(vcpu);
2652                 break;
2653         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2654                 return 1; /* they are read-only */
2655         case MSR_TSC_AUX:
2656                 if (!vmx->rdtscp_enabled)
2657                         return 1;
2658                 /* Check reserved bit, higher 32 bits should be zero */
2659                 if ((data >> 32) != 0)
2660                         return 1;
2661                 /* Otherwise falls through */
2662         default:
2663                 msr = find_msr_entry(vmx, msr_index);
2664                 if (msr) {
2665                         u64 old_msr_data = msr->data;
2666                         msr->data = data;
2667                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2668                                 preempt_disable();
2669                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2670                                                          msr->mask);
2671                                 preempt_enable();
2672                                 if (ret)
2673                                         msr->data = old_msr_data;
2674                         }
2675                         break;
2676                 }
2677                 ret = kvm_set_msr_common(vcpu, msr_info);
2678         }
2679
2680         return ret;
2681 }
2682
2683 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2684 {
2685         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2686         switch (reg) {
2687         case VCPU_REGS_RSP:
2688                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2689                 break;
2690         case VCPU_REGS_RIP:
2691                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2692                 break;
2693         case VCPU_EXREG_PDPTR:
2694                 if (enable_ept)
2695                         ept_save_pdptrs(vcpu);
2696                 break;
2697         default:
2698                 break;
2699         }
2700 }
2701
2702 static __init int cpu_has_kvm_support(void)
2703 {
2704         return cpu_has_vmx();
2705 }
2706
2707 static __init int vmx_disabled_by_bios(void)
2708 {
2709         u64 msr;
2710
2711         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2712         if (msr & FEATURE_CONTROL_LOCKED) {
2713                 /* launched w/ TXT and VMX disabled */
2714                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2715                         && tboot_enabled())
2716                         return 1;
2717                 /* launched w/o TXT and VMX only enabled w/ TXT */
2718                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2719                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2720                         && !tboot_enabled()) {
2721                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2722                                 "activate TXT before enabling KVM\n");
2723                         return 1;
2724                 }
2725                 /* launched w/o TXT and VMX disabled */
2726                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2727                         && !tboot_enabled())
2728                         return 1;
2729         }
2730
2731         return 0;
2732 }
2733
2734 static void kvm_cpu_vmxon(u64 addr)
2735 {
2736         asm volatile (ASM_VMX_VMXON_RAX
2737                         : : "a"(&addr), "m"(addr)
2738                         : "memory", "cc");
2739 }
2740
2741 static int hardware_enable(void)
2742 {
2743         int cpu = raw_smp_processor_id();
2744         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2745         u64 old, test_bits;
2746
2747         if (read_cr4() & X86_CR4_VMXE)
2748                 return -EBUSY;
2749
2750         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2751
2752         /*
2753          * Now we can enable the vmclear operation in kdump
2754          * since the loaded_vmcss_on_cpu list on this cpu
2755          * has been initialized.
2756          *
2757          * Though the cpu is not in VMX operation now, there
2758          * is no problem to enable the vmclear operation
2759          * for the loaded_vmcss_on_cpu list is empty!
2760          */
2761         crash_enable_local_vmclear(cpu);
2762
2763         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2764
2765         test_bits = FEATURE_CONTROL_LOCKED;
2766         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2767         if (tboot_enabled())
2768                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2769
2770         if ((old & test_bits) != test_bits) {
2771                 /* enable and lock */
2772                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2773         }
2774         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2775
2776         if (vmm_exclusive) {
2777                 kvm_cpu_vmxon(phys_addr);
2778                 ept_sync_global();
2779         }
2780
2781         native_store_gdt(this_cpu_ptr(&host_gdt));
2782
2783         return 0;
2784 }
2785
2786 static void vmclear_local_loaded_vmcss(void)
2787 {
2788         int cpu = raw_smp_processor_id();
2789         struct loaded_vmcs *v, *n;
2790
2791         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2792                                  loaded_vmcss_on_cpu_link)
2793                 __loaded_vmcs_clear(v);
2794 }
2795
2796
2797 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2798  * tricks.
2799  */
2800 static void kvm_cpu_vmxoff(void)
2801 {
2802         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2803 }
2804
2805 static void hardware_disable(void)
2806 {
2807         if (vmm_exclusive) {
2808                 vmclear_local_loaded_vmcss();
2809                 kvm_cpu_vmxoff();
2810         }
2811         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2812 }
2813
2814 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2815                                       u32 msr, u32 *result)
2816 {
2817         u32 vmx_msr_low, vmx_msr_high;
2818         u32 ctl = ctl_min | ctl_opt;
2819
2820         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2821
2822         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2823         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2824
2825         /* Ensure minimum (required) set of control bits are supported. */
2826         if (ctl_min & ~ctl)
2827                 return -EIO;
2828
2829         *result = ctl;
2830         return 0;
2831 }
2832
2833 static __init bool allow_1_setting(u32 msr, u32 ctl)
2834 {
2835         u32 vmx_msr_low, vmx_msr_high;
2836
2837         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2838         return vmx_msr_high & ctl;
2839 }
2840
2841 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2842 {
2843         u32 vmx_msr_low, vmx_msr_high;
2844         u32 min, opt, min2, opt2;
2845         u32 _pin_based_exec_control = 0;
2846         u32 _cpu_based_exec_control = 0;
2847         u32 _cpu_based_2nd_exec_control = 0;
2848         u32 _vmexit_control = 0;
2849         u32 _vmentry_control = 0;
2850
2851         min = CPU_BASED_HLT_EXITING |
2852 #ifdef CONFIG_X86_64
2853               CPU_BASED_CR8_LOAD_EXITING |
2854               CPU_BASED_CR8_STORE_EXITING |
2855 #endif
2856               CPU_BASED_CR3_LOAD_EXITING |
2857               CPU_BASED_CR3_STORE_EXITING |
2858               CPU_BASED_USE_IO_BITMAPS |
2859               CPU_BASED_MOV_DR_EXITING |
2860               CPU_BASED_USE_TSC_OFFSETING |
2861               CPU_BASED_MWAIT_EXITING |
2862               CPU_BASED_MONITOR_EXITING |
2863               CPU_BASED_INVLPG_EXITING |
2864               CPU_BASED_RDPMC_EXITING;
2865
2866         opt = CPU_BASED_TPR_SHADOW |
2867               CPU_BASED_USE_MSR_BITMAPS |
2868               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2869         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2870                                 &_cpu_based_exec_control) < 0)
2871                 return -EIO;
2872 #ifdef CONFIG_X86_64
2873         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2874                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2875                                            ~CPU_BASED_CR8_STORE_EXITING;
2876 #endif
2877         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2878                 min2 = 0;
2879                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2880                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2881                         SECONDARY_EXEC_WBINVD_EXITING |
2882                         SECONDARY_EXEC_ENABLE_VPID |
2883                         SECONDARY_EXEC_ENABLE_EPT |
2884                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2885                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2886                         SECONDARY_EXEC_RDTSCP |
2887                         SECONDARY_EXEC_ENABLE_INVPCID |
2888                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2889                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2890                         SECONDARY_EXEC_SHADOW_VMCS;
2891                 if (adjust_vmx_controls(min2, opt2,
2892                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2893                                         &_cpu_based_2nd_exec_control) < 0)
2894                         return -EIO;
2895         }
2896 #ifndef CONFIG_X86_64
2897         if (!(_cpu_based_2nd_exec_control &
2898                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2899                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2900 #endif
2901
2902         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2903                 _cpu_based_2nd_exec_control &= ~(
2904                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2905                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2906                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2907
2908         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2909                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2910                    enabled */
2911                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2912                                              CPU_BASED_CR3_STORE_EXITING |
2913                                              CPU_BASED_INVLPG_EXITING);
2914                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2915                       vmx_capability.ept, vmx_capability.vpid);
2916         }
2917
2918         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2919 #ifdef CONFIG_X86_64
2920         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2921 #endif
2922         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2923                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2924         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2925                                 &_vmexit_control) < 0)
2926                 return -EIO;
2927
2928         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2929         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2930         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2931                                 &_pin_based_exec_control) < 0)
2932                 return -EIO;
2933
2934         if (!(_cpu_based_2nd_exec_control &
2935                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2936                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2937                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2938
2939         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2940         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2941         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2942                                 &_vmentry_control) < 0)
2943                 return -EIO;
2944
2945         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2946
2947         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2948         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2949                 return -EIO;
2950
2951 #ifdef CONFIG_X86_64
2952         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2953         if (vmx_msr_high & (1u<<16))
2954                 return -EIO;
2955 #endif
2956
2957         /* Require Write-Back (WB) memory type for VMCS accesses. */
2958         if (((vmx_msr_high >> 18) & 15) != 6)
2959                 return -EIO;
2960
2961         vmcs_conf->size = vmx_msr_high & 0x1fff;
2962         vmcs_conf->order = get_order(vmcs_config.size);
2963         vmcs_conf->revision_id = vmx_msr_low;
2964
2965         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2966         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2967         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2968         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2969         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2970
2971         cpu_has_load_ia32_efer =
2972                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2973                                 VM_ENTRY_LOAD_IA32_EFER)
2974                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2975                                    VM_EXIT_LOAD_IA32_EFER);
2976
2977         cpu_has_load_perf_global_ctrl =
2978                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2979                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2980                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2981                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2982
2983         /*
2984          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2985          * but due to arrata below it can't be used. Workaround is to use
2986          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2987          *
2988          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2989          *
2990          * AAK155             (model 26)
2991          * AAP115             (model 30)
2992          * AAT100             (model 37)
2993          * BC86,AAY89,BD102   (model 44)
2994          * BA97               (model 46)
2995          *
2996          */
2997         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2998                 switch (boot_cpu_data.x86_model) {
2999                 case 26:
3000                 case 30:
3001                 case 37:
3002                 case 44:
3003                 case 46:
3004                         cpu_has_load_perf_global_ctrl = false;
3005                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3006                                         "does not work properly. Using workaround\n");
3007                         break;
3008                 default:
3009                         break;
3010                 }
3011         }
3012
3013         return 0;
3014 }
3015
3016 static struct vmcs *alloc_vmcs_cpu(int cpu)
3017 {
3018         int node = cpu_to_node(cpu);
3019         struct page *pages;
3020         struct vmcs *vmcs;
3021
3022         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3023         if (!pages)
3024                 return NULL;
3025         vmcs = page_address(pages);
3026         memset(vmcs, 0, vmcs_config.size);
3027         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3028         return vmcs;
3029 }
3030
3031 static struct vmcs *alloc_vmcs(void)
3032 {
3033         return alloc_vmcs_cpu(raw_smp_processor_id());
3034 }
3035
3036 static void free_vmcs(struct vmcs *vmcs)
3037 {
3038         free_pages((unsigned long)vmcs, vmcs_config.order);
3039 }
3040
3041 /*
3042  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3043  */
3044 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3045 {
3046         if (!loaded_vmcs->vmcs)
3047                 return;
3048         loaded_vmcs_clear(loaded_vmcs);
3049         free_vmcs(loaded_vmcs->vmcs);
3050         loaded_vmcs->vmcs = NULL;
3051 }
3052
3053 static void free_kvm_area(void)
3054 {
3055         int cpu;
3056
3057         for_each_possible_cpu(cpu) {
3058                 free_vmcs(per_cpu(vmxarea, cpu));
3059                 per_cpu(vmxarea, cpu) = NULL;
3060         }
3061 }
3062
3063 static void init_vmcs_shadow_fields(void)
3064 {
3065         int i, j;
3066
3067         /* No checks for read only fields yet */
3068
3069         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3070                 switch (shadow_read_write_fields[i]) {
3071                 case GUEST_BNDCFGS:
3072                         if (!vmx_mpx_supported())
3073                                 continue;
3074                         break;
3075                 default:
3076                         break;
3077                 }
3078
3079                 if (j < i)
3080                         shadow_read_write_fields[j] =
3081                                 shadow_read_write_fields[i];
3082                 j++;
3083         }
3084         max_shadow_read_write_fields = j;
3085
3086         /* shadowed fields guest access without vmexit */
3087         for (i = 0; i < max_shadow_read_write_fields; i++) {
3088                 clear_bit(shadow_read_write_fields[i],
3089                           vmx_vmwrite_bitmap);
3090                 clear_bit(shadow_read_write_fields[i],
3091                           vmx_vmread_bitmap);
3092         }
3093         for (i = 0; i < max_shadow_read_only_fields; i++)
3094                 clear_bit(shadow_read_only_fields[i],
3095                           vmx_vmread_bitmap);
3096 }
3097
3098 static __init int alloc_kvm_area(void)
3099 {
3100         int cpu;
3101
3102         for_each_possible_cpu(cpu) {
3103                 struct vmcs *vmcs;
3104
3105                 vmcs = alloc_vmcs_cpu(cpu);
3106                 if (!vmcs) {
3107                         free_kvm_area();
3108                         return -ENOMEM;
3109                 }
3110
3111                 per_cpu(vmxarea, cpu) = vmcs;
3112         }
3113         return 0;
3114 }
3115
3116 static bool emulation_required(struct kvm_vcpu *vcpu)
3117 {
3118         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3119 }
3120
3121 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3122                 struct kvm_segment *save)
3123 {
3124         if (!emulate_invalid_guest_state) {
3125                 /*
3126                  * CS and SS RPL should be equal during guest entry according
3127                  * to VMX spec, but in reality it is not always so. Since vcpu
3128                  * is in the middle of the transition from real mode to
3129                  * protected mode it is safe to assume that RPL 0 is a good
3130                  * default value.
3131                  */
3132                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3133                         save->selector &= ~SELECTOR_RPL_MASK;
3134                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3135                 save->s = 1;
3136         }
3137         vmx_set_segment(vcpu, save, seg);
3138 }
3139
3140 static void enter_pmode(struct kvm_vcpu *vcpu)
3141 {
3142         unsigned long flags;
3143         struct vcpu_vmx *vmx = to_vmx(vcpu);
3144
3145         /*
3146          * Update real mode segment cache. It may be not up-to-date if sement
3147          * register was written while vcpu was in a guest mode.
3148          */
3149         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3150         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3151         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3152         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3153         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3154         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3155
3156         vmx->rmode.vm86_active = 0;
3157
3158         vmx_segment_cache_clear(vmx);
3159
3160         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3161
3162         flags = vmcs_readl(GUEST_RFLAGS);
3163         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3164         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3165         vmcs_writel(GUEST_RFLAGS, flags);
3166
3167         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3168                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3169
3170         update_exception_bitmap(vcpu);
3171
3172         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3173         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3174         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3175         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3176         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3177         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3178 }
3179
3180 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3181 {
3182         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3183         struct kvm_segment var = *save;
3184
3185         var.dpl = 0x3;
3186         if (seg == VCPU_SREG_CS)
3187                 var.type = 0x3;
3188
3189         if (!emulate_invalid_guest_state) {
3190                 var.selector = var.base >> 4;
3191                 var.base = var.base & 0xffff0;
3192                 var.limit = 0xffff;
3193                 var.g = 0;
3194                 var.db = 0;
3195                 var.present = 1;
3196                 var.s = 1;
3197                 var.l = 0;
3198                 var.unusable = 0;
3199                 var.type = 0x3;
3200                 var.avl = 0;
3201                 if (save->base & 0xf)
3202                         printk_once(KERN_WARNING "kvm: segment base is not "
3203                                         "paragraph aligned when entering "
3204                                         "protected mode (seg=%d)", seg);
3205         }
3206
3207         vmcs_write16(sf->selector, var.selector);
3208         vmcs_write32(sf->base, var.base);
3209         vmcs_write32(sf->limit, var.limit);
3210         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3211 }
3212
3213 static void enter_rmode(struct kvm_vcpu *vcpu)
3214 {
3215         unsigned long flags;
3216         struct vcpu_vmx *vmx = to_vmx(vcpu);
3217
3218         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3219         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3220         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3221         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3222         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3223         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3224         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3225
3226         vmx->rmode.vm86_active = 1;
3227
3228         /*
3229          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3230          * vcpu. Warn the user that an update is overdue.
3231          */
3232         if (!vcpu->kvm->arch.tss_addr)
3233                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3234                              "called before entering vcpu\n");
3235
3236         vmx_segment_cache_clear(vmx);
3237
3238         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3239         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3240         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3241
3242         flags = vmcs_readl(GUEST_RFLAGS);
3243         vmx->rmode.save_rflags = flags;
3244
3245         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3246
3247         vmcs_writel(GUEST_RFLAGS, flags);
3248         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3249         update_exception_bitmap(vcpu);
3250
3251         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3252         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3253         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3254         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3255         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3256         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3257
3258         kvm_mmu_reset_context(vcpu);
3259 }
3260
3261 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3262 {
3263         struct vcpu_vmx *vmx = to_vmx(vcpu);
3264         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3265
3266         if (!msr)
3267                 return;
3268
3269         /*
3270          * Force kernel_gs_base reloading before EFER changes, as control
3271          * of this msr depends on is_long_mode().
3272          */
3273         vmx_load_host_state(to_vmx(vcpu));
3274         vcpu->arch.efer = efer;
3275         if (efer & EFER_LMA) {
3276                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3277                 msr->data = efer;
3278         } else {
3279                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3280
3281                 msr->data = efer & ~EFER_LME;
3282         }
3283         setup_msrs(vmx);
3284 }
3285
3286 #ifdef CONFIG_X86_64
3287
3288 static void enter_lmode(struct kvm_vcpu *vcpu)
3289 {
3290         u32 guest_tr_ar;
3291
3292         vmx_segment_cache_clear(to_vmx(vcpu));
3293
3294         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3295         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3296                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3297                                      __func__);
3298                 vmcs_write32(GUEST_TR_AR_BYTES,
3299                              (guest_tr_ar & ~AR_TYPE_MASK)
3300                              | AR_TYPE_BUSY_64_TSS);
3301         }
3302         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3303 }
3304
3305 static void exit_lmode(struct kvm_vcpu *vcpu)
3306 {
3307         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3308         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3309 }
3310
3311 #endif
3312
3313 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3314 {
3315         vpid_sync_context(to_vmx(vcpu));
3316         if (enable_ept) {
3317                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3318                         return;
3319                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3320         }
3321 }
3322
3323 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3324 {
3325         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3326
3327         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3328         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3329 }
3330
3331 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3332 {
3333         if (enable_ept && is_paging(vcpu))
3334                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3335         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3336 }
3337
3338 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3339 {
3340         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3341
3342         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3343         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3344 }
3345
3346 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3347 {
3348         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3349
3350         if (!test_bit(VCPU_EXREG_PDPTR,
3351                       (unsigned long *)&vcpu->arch.regs_dirty))
3352                 return;
3353
3354         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3355                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3356                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3357                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3358                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3359         }
3360 }
3361
3362 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3363 {
3364         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3365
3366         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3367                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3368                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3369                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3370                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3371         }
3372
3373         __set_bit(VCPU_EXREG_PDPTR,
3374                   (unsigned long *)&vcpu->arch.regs_avail);
3375         __set_bit(VCPU_EXREG_PDPTR,
3376                   (unsigned long *)&vcpu->arch.regs_dirty);
3377 }
3378
3379 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3380
3381 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3382                                         unsigned long cr0,
3383                                         struct kvm_vcpu *vcpu)
3384 {
3385         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3386                 vmx_decache_cr3(vcpu);
3387         if (!(cr0 & X86_CR0_PG)) {
3388                 /* From paging/starting to nonpaging */
3389                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3390                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3391                              (CPU_BASED_CR3_LOAD_EXITING |
3392                               CPU_BASED_CR3_STORE_EXITING));
3393                 vcpu->arch.cr0 = cr0;
3394                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3395         } else if (!is_paging(vcpu)) {
3396                 /* From nonpaging to paging */
3397                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3398                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3399                              ~(CPU_BASED_CR3_LOAD_EXITING |
3400                                CPU_BASED_CR3_STORE_EXITING));
3401                 vcpu->arch.cr0 = cr0;
3402                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3403         }
3404
3405         if (!(cr0 & X86_CR0_WP))
3406                 *hw_cr0 &= ~X86_CR0_WP;
3407 }
3408
3409 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3410 {
3411         struct vcpu_vmx *vmx = to_vmx(vcpu);
3412         unsigned long hw_cr0;
3413
3414         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3415         if (enable_unrestricted_guest)
3416                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3417         else {
3418                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3419
3420                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3421                         enter_pmode(vcpu);
3422
3423                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3424                         enter_rmode(vcpu);
3425         }
3426
3427 #ifdef CONFIG_X86_64
3428         if (vcpu->arch.efer & EFER_LME) {
3429                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3430                         enter_lmode(vcpu);
3431                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3432                         exit_lmode(vcpu);
3433         }
3434 #endif
3435
3436         if (enable_ept)
3437                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3438
3439         if (!vcpu->fpu_active)
3440                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3441
3442         vmcs_writel(CR0_READ_SHADOW, cr0);
3443         vmcs_writel(GUEST_CR0, hw_cr0);
3444         vcpu->arch.cr0 = cr0;
3445
3446         /* depends on vcpu->arch.cr0 to be set to a new value */
3447         vmx->emulation_required = emulation_required(vcpu);
3448 }
3449
3450 static u64 construct_eptp(unsigned long root_hpa)
3451 {
3452         u64 eptp;
3453
3454         /* TODO write the value reading from MSR */
3455         eptp = VMX_EPT_DEFAULT_MT |
3456                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3457         if (enable_ept_ad_bits)
3458                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3459         eptp |= (root_hpa & PAGE_MASK);
3460
3461         return eptp;
3462 }
3463
3464 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3465 {
3466         unsigned long guest_cr3;
3467         u64 eptp;
3468
3469         guest_cr3 = cr3;
3470         if (enable_ept) {
3471                 eptp = construct_eptp(cr3);
3472                 vmcs_write64(EPT_POINTER, eptp);
3473                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3474                         guest_cr3 = kvm_read_cr3(vcpu);
3475                 else
3476                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3477                 ept_load_pdptrs(vcpu);
3478         }
3479
3480         vmx_flush_tlb(vcpu);
3481         vmcs_writel(GUEST_CR3, guest_cr3);
3482 }
3483
3484 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3485 {
3486         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3487                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3488
3489         if (cr4 & X86_CR4_VMXE) {
3490                 /*
3491                  * To use VMXON (and later other VMX instructions), a guest
3492                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3493                  * So basically the check on whether to allow nested VMX
3494                  * is here.
3495                  */
3496                 if (!nested_vmx_allowed(vcpu))
3497                         return 1;
3498         }
3499         if (to_vmx(vcpu)->nested.vmxon &&
3500             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3501                 return 1;
3502
3503         vcpu->arch.cr4 = cr4;
3504         if (enable_ept) {
3505                 if (!is_paging(vcpu)) {
3506                         hw_cr4 &= ~X86_CR4_PAE;
3507                         hw_cr4 |= X86_CR4_PSE;
3508                         /*
3509                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3510                          * in hardware. However KVM always uses paging mode to
3511                          * emulate guest non-paging mode with TDP.
3512                          * To emulate this behavior, SMEP/SMAP needs to be
3513                          * manually disabled when guest switches to non-paging
3514                          * mode.
3515                          */
3516                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3517                 } else if (!(cr4 & X86_CR4_PAE)) {
3518                         hw_cr4 &= ~X86_CR4_PAE;
3519                 }
3520         }
3521
3522         vmcs_writel(CR4_READ_SHADOW, cr4);
3523         vmcs_writel(GUEST_CR4, hw_cr4);
3524         return 0;
3525 }
3526
3527 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3528                             struct kvm_segment *var, int seg)
3529 {
3530         struct vcpu_vmx *vmx = to_vmx(vcpu);
3531         u32 ar;
3532
3533         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3534                 *var = vmx->rmode.segs[seg];
3535                 if (seg == VCPU_SREG_TR
3536                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3537                         return;
3538                 var->base = vmx_read_guest_seg_base(vmx, seg);
3539                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3540                 return;
3541         }
3542         var->base = vmx_read_guest_seg_base(vmx, seg);
3543         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3544         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3545         ar = vmx_read_guest_seg_ar(vmx, seg);
3546         var->unusable = (ar >> 16) & 1;
3547         var->type = ar & 15;
3548         var->s = (ar >> 4) & 1;
3549         var->dpl = (ar >> 5) & 3;
3550         /*
3551          * Some userspaces do not preserve unusable property. Since usable
3552          * segment has to be present according to VMX spec we can use present
3553          * property to amend userspace bug by making unusable segment always
3554          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3555          * segment as unusable.
3556          */
3557         var->present = !var->unusable;
3558         var->avl = (ar >> 12) & 1;
3559         var->l = (ar >> 13) & 1;
3560         var->db = (ar >> 14) & 1;
3561         var->g = (ar >> 15) & 1;
3562 }
3563
3564 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3565 {
3566         struct kvm_segment s;
3567
3568         if (to_vmx(vcpu)->rmode.vm86_active) {
3569                 vmx_get_segment(vcpu, &s, seg);
3570                 return s.base;
3571         }
3572         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3573 }
3574
3575 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3576 {
3577         struct vcpu_vmx *vmx = to_vmx(vcpu);
3578
3579         if (unlikely(vmx->rmode.vm86_active))
3580                 return 0;
3581         else {
3582                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3583                 return AR_DPL(ar);
3584         }
3585 }
3586
3587 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3588 {
3589         u32 ar;
3590
3591         if (var->unusable || !var->present)
3592                 ar = 1 << 16;
3593         else {
3594                 ar = var->type & 15;
3595                 ar |= (var->s & 1) << 4;
3596                 ar |= (var->dpl & 3) << 5;
3597                 ar |= (var->present & 1) << 7;
3598                 ar |= (var->avl & 1) << 12;
3599                 ar |= (var->l & 1) << 13;
3600                 ar |= (var->db & 1) << 14;
3601                 ar |= (var->g & 1) << 15;
3602         }
3603
3604         return ar;
3605 }
3606
3607 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3608                             struct kvm_segment *var, int seg)
3609 {
3610         struct vcpu_vmx *vmx = to_vmx(vcpu);
3611         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3612
3613         vmx_segment_cache_clear(vmx);
3614
3615         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3616                 vmx->rmode.segs[seg] = *var;
3617                 if (seg == VCPU_SREG_TR)
3618                         vmcs_write16(sf->selector, var->selector);
3619                 else if (var->s)
3620                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3621                 goto out;
3622         }
3623
3624         vmcs_writel(sf->base, var->base);
3625         vmcs_write32(sf->limit, var->limit);
3626         vmcs_write16(sf->selector, var->selector);
3627
3628         /*
3629          *   Fix the "Accessed" bit in AR field of segment registers for older
3630          * qemu binaries.
3631          *   IA32 arch specifies that at the time of processor reset the
3632          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3633          * is setting it to 0 in the userland code. This causes invalid guest
3634          * state vmexit when "unrestricted guest" mode is turned on.
3635          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3636          * tree. Newer qemu binaries with that qemu fix would not need this
3637          * kvm hack.
3638          */
3639         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3640                 var->type |= 0x1; /* Accessed */
3641
3642         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3643
3644 out:
3645         vmx->emulation_required = emulation_required(vcpu);
3646 }
3647
3648 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3649 {
3650         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3651
3652         *db = (ar >> 14) & 1;
3653         *l = (ar >> 13) & 1;
3654 }
3655
3656 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3657 {
3658         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3659         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3660 }
3661
3662 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3663 {
3664         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3665         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3666 }
3667
3668 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3669 {
3670         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3671         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3672 }
3673
3674 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3675 {
3676         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3677         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3678 }
3679
3680 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3681 {
3682         struct kvm_segment var;
3683         u32 ar;
3684
3685         vmx_get_segment(vcpu, &var, seg);
3686         var.dpl = 0x3;
3687         if (seg == VCPU_SREG_CS)
3688                 var.type = 0x3;
3689         ar = vmx_segment_access_rights(&var);
3690
3691         if (var.base != (var.selector << 4))
3692                 return false;
3693         if (var.limit != 0xffff)
3694                 return false;
3695         if (ar != 0xf3)
3696                 return false;
3697
3698         return true;
3699 }
3700
3701 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3702 {
3703         struct kvm_segment cs;
3704         unsigned int cs_rpl;
3705
3706         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3707         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3708
3709         if (cs.unusable)
3710                 return false;
3711         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3712                 return false;
3713         if (!cs.s)
3714                 return false;
3715         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3716                 if (cs.dpl > cs_rpl)
3717                         return false;
3718         } else {
3719                 if (cs.dpl != cs_rpl)
3720                         return false;
3721         }
3722         if (!cs.present)
3723                 return false;
3724
3725         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3726         return true;
3727 }
3728
3729 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3730 {
3731         struct kvm_segment ss;
3732         unsigned int ss_rpl;
3733
3734         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3735         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3736
3737         if (ss.unusable)
3738                 return true;
3739         if (ss.type != 3 && ss.type != 7)
3740                 return false;
3741         if (!ss.s)
3742                 return false;
3743         if (ss.dpl != ss_rpl) /* DPL != RPL */
3744                 return false;
3745         if (!ss.present)
3746                 return false;
3747
3748         return true;
3749 }
3750
3751 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3752 {
3753         struct kvm_segment var;
3754         unsigned int rpl;
3755
3756         vmx_get_segment(vcpu, &var, seg);
3757         rpl = var.selector & SELECTOR_RPL_MASK;
3758
3759         if (var.unusable)
3760                 return true;
3761         if (!var.s)
3762                 return false;
3763         if (!var.present)
3764                 return false;
3765         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3766                 if (var.dpl < rpl) /* DPL < RPL */
3767                         return false;
3768         }
3769
3770         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3771          * rights flags
3772          */
3773         return true;
3774 }
3775
3776 static bool tr_valid(struct kvm_vcpu *vcpu)
3777 {
3778         struct kvm_segment tr;
3779
3780         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3781
3782         if (tr.unusable)
3783                 return false;
3784         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3785                 return false;
3786         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3787                 return false;
3788         if (!tr.present)
3789                 return false;
3790
3791         return true;
3792 }
3793
3794 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3795 {
3796         struct kvm_segment ldtr;
3797
3798         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3799
3800         if (ldtr.unusable)
3801                 return true;
3802         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3803                 return false;
3804         if (ldtr.type != 2)
3805                 return false;
3806         if (!ldtr.present)
3807                 return false;
3808
3809         return true;
3810 }
3811
3812 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3813 {
3814         struct kvm_segment cs, ss;
3815
3816         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3817         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3818
3819         return ((cs.selector & SELECTOR_RPL_MASK) ==
3820                  (ss.selector & SELECTOR_RPL_MASK));
3821 }
3822
3823 /*
3824  * Check if guest state is valid. Returns true if valid, false if
3825  * not.
3826  * We assume that registers are always usable
3827  */
3828 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3829 {
3830         if (enable_unrestricted_guest)
3831                 return true;
3832
3833         /* real mode guest state checks */
3834         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3835                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3836                         return false;
3837                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3838                         return false;
3839                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3840                         return false;
3841                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3842                         return false;
3843                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3844                         return false;
3845                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3846                         return false;
3847         } else {
3848         /* protected mode guest state checks */
3849                 if (!cs_ss_rpl_check(vcpu))
3850                         return false;
3851                 if (!code_segment_valid(vcpu))
3852                         return false;
3853                 if (!stack_segment_valid(vcpu))
3854                         return false;
3855                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3856                         return false;
3857                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3858                         return false;
3859                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3860                         return false;
3861                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3862                         return false;
3863                 if (!tr_valid(vcpu))
3864                         return false;
3865                 if (!ldtr_valid(vcpu))
3866                         return false;
3867         }
3868         /* TODO:
3869          * - Add checks on RIP
3870          * - Add checks on RFLAGS
3871          */
3872
3873         return true;
3874 }
3875
3876 static int init_rmode_tss(struct kvm *kvm)
3877 {
3878         gfn_t fn;
3879         u16 data = 0;
3880         int idx, r;
3881
3882         idx = srcu_read_lock(&kvm->srcu);
3883         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3884         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3885         if (r < 0)
3886                 goto out;
3887         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3888         r = kvm_write_guest_page(kvm, fn++, &data,
3889                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3890         if (r < 0)
3891                 goto out;
3892         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3893         if (r < 0)
3894                 goto out;
3895         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3896         if (r < 0)
3897                 goto out;
3898         data = ~0;
3899         r = kvm_write_guest_page(kvm, fn, &data,
3900                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3901                                  sizeof(u8));
3902 out:
3903         srcu_read_unlock(&kvm->srcu, idx);
3904         return r;
3905 }
3906
3907 static int init_rmode_identity_map(struct kvm *kvm)
3908 {
3909         int i, idx, r = 0;
3910         pfn_t identity_map_pfn;
3911         u32 tmp;
3912
3913         if (!enable_ept)
3914                 return 0;
3915
3916         /* Protect kvm->arch.ept_identity_pagetable_done. */
3917         mutex_lock(&kvm->slots_lock);
3918
3919         if (likely(kvm->arch.ept_identity_pagetable_done))
3920                 goto out2;
3921
3922         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3923
3924         r = alloc_identity_pagetable(kvm);
3925         if (r < 0)
3926                 goto out2;
3927
3928         idx = srcu_read_lock(&kvm->srcu);
3929         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3930         if (r < 0)
3931                 goto out;
3932         /* Set up identity-mapping pagetable for EPT in real mode */
3933         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3934                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3935                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3936                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3937                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3938                 if (r < 0)
3939                         goto out;
3940         }
3941         kvm->arch.ept_identity_pagetable_done = true;
3942
3943 out:
3944         srcu_read_unlock(&kvm->srcu, idx);
3945
3946 out2:
3947         mutex_unlock(&kvm->slots_lock);
3948         return r;
3949 }
3950
3951 static void seg_setup(int seg)
3952 {
3953         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3954         unsigned int ar;
3955
3956         vmcs_write16(sf->selector, 0);
3957         vmcs_writel(sf->base, 0);
3958         vmcs_write32(sf->limit, 0xffff);
3959         ar = 0x93;
3960         if (seg == VCPU_SREG_CS)
3961                 ar |= 0x08; /* code segment */
3962
3963         vmcs_write32(sf->ar_bytes, ar);
3964 }
3965
3966 static int alloc_apic_access_page(struct kvm *kvm)
3967 {
3968         struct page *page;
3969         struct kvm_userspace_memory_region kvm_userspace_mem;
3970         int r = 0;
3971
3972         mutex_lock(&kvm->slots_lock);
3973         if (kvm->arch.apic_access_page_done)
3974                 goto out;
3975         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3976         kvm_userspace_mem.flags = 0;
3977         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
3978         kvm_userspace_mem.memory_size = PAGE_SIZE;
3979         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3980         if (r)
3981                 goto out;
3982
3983         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3984         if (is_error_page(page)) {
3985                 r = -EFAULT;
3986                 goto out;
3987         }
3988
3989         /*
3990          * Do not pin the page in memory, so that memory hot-unplug
3991          * is able to migrate it.
3992          */
3993         put_page(page);
3994         kvm->arch.apic_access_page_done = true;
3995 out:
3996         mutex_unlock(&kvm->slots_lock);
3997         return r;
3998 }
3999
4000 static int alloc_identity_pagetable(struct kvm *kvm)
4001 {
4002         /* Called with kvm->slots_lock held. */
4003
4004         struct kvm_userspace_memory_region kvm_userspace_mem;
4005         int r = 0;
4006
4007         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4008
4009         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4010         kvm_userspace_mem.flags = 0;
4011         kvm_userspace_mem.guest_phys_addr =
4012                 kvm->arch.ept_identity_map_addr;
4013         kvm_userspace_mem.memory_size = PAGE_SIZE;
4014         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4015
4016         return r;
4017 }
4018
4019 static void allocate_vpid(struct vcpu_vmx *vmx)
4020 {
4021         int vpid;
4022
4023         vmx->vpid = 0;
4024         if (!enable_vpid)
4025                 return;
4026         spin_lock(&vmx_vpid_lock);
4027         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4028         if (vpid < VMX_NR_VPIDS) {
4029                 vmx->vpid = vpid;
4030                 __set_bit(vpid, vmx_vpid_bitmap);
4031         }
4032         spin_unlock(&vmx_vpid_lock);
4033 }
4034
4035 static void free_vpid(struct vcpu_vmx *vmx)
4036 {
4037         if (!enable_vpid)
4038                 return;
4039         spin_lock(&vmx_vpid_lock);
4040         if (vmx->vpid != 0)
4041                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4042         spin_unlock(&vmx_vpid_lock);
4043 }
4044
4045 #define MSR_TYPE_R      1
4046 #define MSR_TYPE_W      2
4047 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4048                                                 u32 msr, int type)
4049 {
4050         int f = sizeof(unsigned long);
4051
4052         if (!cpu_has_vmx_msr_bitmap())
4053                 return;
4054
4055         /*
4056          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4057          * have the write-low and read-high bitmap offsets the wrong way round.
4058          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4059          */
4060         if (msr <= 0x1fff) {
4061                 if (type & MSR_TYPE_R)
4062                         /* read-low */
4063                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4064
4065                 if (type & MSR_TYPE_W)
4066                         /* write-low */
4067                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4068
4069         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4070                 msr &= 0x1fff;
4071                 if (type & MSR_TYPE_R)
4072                         /* read-high */
4073                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4074
4075                 if (type & MSR_TYPE_W)
4076                         /* write-high */
4077                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4078
4079         }
4080 }
4081
4082 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4083                                                 u32 msr, int type)
4084 {
4085         int f = sizeof(unsigned long);
4086
4087         if (!cpu_has_vmx_msr_bitmap())
4088                 return;
4089
4090         /*
4091          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4092          * have the write-low and read-high bitmap offsets the wrong way round.
4093          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4094          */
4095         if (msr <= 0x1fff) {
4096                 if (type & MSR_TYPE_R)
4097                         /* read-low */
4098                         __set_bit(msr, msr_bitmap + 0x000 / f);
4099
4100                 if (type & MSR_TYPE_W)
4101                         /* write-low */
4102                         __set_bit(msr, msr_bitmap + 0x800 / f);
4103
4104         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4105                 msr &= 0x1fff;
4106                 if (type & MSR_TYPE_R)
4107                         /* read-high */
4108                         __set_bit(msr, msr_bitmap + 0x400 / f);
4109
4110                 if (type & MSR_TYPE_W)
4111                         /* write-high */
4112                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4113
4114         }
4115 }
4116
4117 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4118 {
4119         if (!longmode_only)
4120                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4121                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4122         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4123                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4124 }
4125
4126 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4127 {
4128         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4129                         msr, MSR_TYPE_R);
4130         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4131                         msr, MSR_TYPE_R);
4132 }
4133
4134 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4135 {
4136         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4137                         msr, MSR_TYPE_R);
4138         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4139                         msr, MSR_TYPE_R);
4140 }
4141
4142 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4143 {
4144         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4145                         msr, MSR_TYPE_W);
4146         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4147                         msr, MSR_TYPE_W);
4148 }
4149
4150 static int vmx_vm_has_apicv(struct kvm *kvm)
4151 {
4152         return enable_apicv && irqchip_in_kernel(kvm);
4153 }
4154
4155 /*
4156  * Send interrupt to vcpu via posted interrupt way.
4157  * 1. If target vcpu is running(non-root mode), send posted interrupt
4158  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4159  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4160  * interrupt from PIR in next vmentry.
4161  */
4162 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4163 {
4164         struct vcpu_vmx *vmx = to_vmx(vcpu);
4165         int r;
4166
4167         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4168                 return;
4169
4170         r = pi_test_and_set_on(&vmx->pi_desc);
4171         kvm_make_request(KVM_REQ_EVENT, vcpu);
4172 #ifdef CONFIG_SMP
4173         if (!r && (vcpu->mode == IN_GUEST_MODE))
4174                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4175                                 POSTED_INTR_VECTOR);
4176         else
4177 #endif
4178                 kvm_vcpu_kick(vcpu);
4179 }
4180
4181 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4182 {
4183         struct vcpu_vmx *vmx = to_vmx(vcpu);
4184
4185         if (!pi_test_and_clear_on(&vmx->pi_desc))
4186                 return;
4187
4188         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4189 }
4190
4191 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4192 {
4193         return;
4194 }
4195
4196 /*
4197  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4198  * will not change in the lifetime of the guest.
4199  * Note that host-state that does change is set elsewhere. E.g., host-state
4200  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4201  */
4202 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4203 {
4204         u32 low32, high32;
4205         unsigned long tmpl;
4206         struct desc_ptr dt;
4207         unsigned long cr4;
4208
4209         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4210         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4211
4212         /* Save the most likely value for this task's CR4 in the VMCS. */
4213         cr4 = read_cr4();
4214         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4215         vmx->host_state.vmcs_host_cr4 = cr4;
4216
4217         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4218 #ifdef CONFIG_X86_64
4219         /*
4220          * Load null selectors, so we can avoid reloading them in
4221          * __vmx_load_host_state(), in case userspace uses the null selectors
4222          * too (the expected case).
4223          */
4224         vmcs_write16(HOST_DS_SELECTOR, 0);
4225         vmcs_write16(HOST_ES_SELECTOR, 0);
4226 #else
4227         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4228         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4229 #endif
4230         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4231         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4232
4233         native_store_idt(&dt);
4234         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4235         vmx->host_idt_base = dt.address;
4236
4237         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4238
4239         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4240         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4241         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4242         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4243
4244         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4245                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4246                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4247         }
4248 }
4249
4250 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4251 {
4252         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4253         if (enable_ept)
4254                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4255         if (is_guest_mode(&vmx->vcpu))
4256                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4257                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4258         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4259 }
4260
4261 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4262 {
4263         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4264
4265         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4266                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4267         return pin_based_exec_ctrl;
4268 }
4269
4270 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4271 {
4272         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4273
4274         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4275                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4276
4277         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4278                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4279 #ifdef CONFIG_X86_64
4280                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4281                                 CPU_BASED_CR8_LOAD_EXITING;
4282 #endif
4283         }
4284         if (!enable_ept)
4285                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4286                                 CPU_BASED_CR3_LOAD_EXITING  |
4287                                 CPU_BASED_INVLPG_EXITING;
4288         return exec_control;
4289 }
4290
4291 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4292 {
4293         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4294         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4295                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4296         if (vmx->vpid == 0)
4297                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4298         if (!enable_ept) {
4299                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4300                 enable_unrestricted_guest = 0;
4301                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4302                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4303         }
4304         if (!enable_unrestricted_guest)
4305                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4306         if (!ple_gap)
4307                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4308         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4309                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4310                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4311         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4312         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4313            (handle_vmptrld).
4314            We can NOT enable shadow_vmcs here because we don't have yet
4315            a current VMCS12
4316         */
4317         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4318         return exec_control;
4319 }
4320
4321 static void ept_set_mmio_spte_mask(void)
4322 {
4323         /*
4324          * EPT Misconfigurations can be generated if the value of bits 2:0
4325          * of an EPT paging-structure entry is 110b (write/execute).
4326          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4327          * spte.
4328          */
4329         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4330 }
4331
4332 /*
4333  * Sets up the vmcs for emulated real mode.
4334  */
4335 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4336 {
4337 #ifdef CONFIG_X86_64
4338         unsigned long a;
4339 #endif
4340         int i;
4341
4342         /* I/O */
4343         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4344         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4345
4346         if (enable_shadow_vmcs) {
4347                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4348                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4349         }
4350         if (cpu_has_vmx_msr_bitmap())
4351                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4352
4353         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4354
4355         /* Control */
4356         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4357
4358         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4359
4360         if (cpu_has_secondary_exec_ctrls()) {
4361                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4362                                 vmx_secondary_exec_control(vmx));
4363         }
4364
4365         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4366                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4367                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4368                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4369                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4370
4371                 vmcs_write16(GUEST_INTR_STATUS, 0);
4372
4373                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4374                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4375         }
4376
4377         if (ple_gap) {
4378                 vmcs_write32(PLE_GAP, ple_gap);
4379                 vmx->ple_window = ple_window;
4380                 vmx->ple_window_dirty = true;
4381         }
4382
4383         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4384         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4385         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4386
4387         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4388         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4389         vmx_set_constant_host_state(vmx);
4390 #ifdef CONFIG_X86_64
4391         rdmsrl(MSR_FS_BASE, a);
4392         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4393         rdmsrl(MSR_GS_BASE, a);
4394         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4395 #else
4396         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4397         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4398 #endif
4399
4400         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4401         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4402         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4403         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4404         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4405
4406         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4407                 u32 msr_low, msr_high;
4408                 u64 host_pat;
4409                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4410                 host_pat = msr_low | ((u64) msr_high << 32);
4411                 /* Write the default value follow host pat */
4412                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4413                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4414                 vmx->vcpu.arch.pat = host_pat;
4415         }
4416
4417         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4418                 u32 index = vmx_msr_index[i];
4419                 u32 data_low, data_high;
4420                 int j = vmx->nmsrs;
4421
4422                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4423                         continue;
4424                 if (wrmsr_safe(index, data_low, data_high) < 0)
4425                         continue;
4426                 vmx->guest_msrs[j].index = i;
4427                 vmx->guest_msrs[j].data = 0;
4428                 vmx->guest_msrs[j].mask = -1ull;
4429                 ++vmx->nmsrs;
4430         }
4431
4432
4433         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4434
4435         /* 22.2.1, 20.8.1 */
4436         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4437
4438         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4439         set_cr4_guest_host_mask(vmx);
4440
4441         return 0;
4442 }
4443
4444 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4445 {
4446         struct vcpu_vmx *vmx = to_vmx(vcpu);
4447         struct msr_data apic_base_msr;
4448
4449         vmx->rmode.vm86_active = 0;
4450
4451         vmx->soft_vnmi_blocked = 0;
4452
4453         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4454         kvm_set_cr8(&vmx->vcpu, 0);
4455         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4456         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4457                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4458         apic_base_msr.host_initiated = true;
4459         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4460
4461         vmx_segment_cache_clear(vmx);
4462
4463         seg_setup(VCPU_SREG_CS);
4464         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4465         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4466
4467         seg_setup(VCPU_SREG_DS);
4468         seg_setup(VCPU_SREG_ES);
4469         seg_setup(VCPU_SREG_FS);
4470         seg_setup(VCPU_SREG_GS);
4471         seg_setup(VCPU_SREG_SS);
4472
4473         vmcs_write16(GUEST_TR_SELECTOR, 0);
4474         vmcs_writel(GUEST_TR_BASE, 0);
4475         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4476         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4477
4478         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4479         vmcs_writel(GUEST_LDTR_BASE, 0);
4480         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4481         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4482
4483         vmcs_write32(GUEST_SYSENTER_CS, 0);
4484         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4485         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4486
4487         vmcs_writel(GUEST_RFLAGS, 0x02);
4488         kvm_rip_write(vcpu, 0xfff0);
4489
4490         vmcs_writel(GUEST_GDTR_BASE, 0);
4491         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4492
4493         vmcs_writel(GUEST_IDTR_BASE, 0);
4494         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4495
4496         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4497         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4498         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4499
4500         /* Special registers */
4501         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4502
4503         setup_msrs(vmx);
4504
4505         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4506
4507         if (cpu_has_vmx_tpr_shadow()) {
4508                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4509                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4510                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4511                                      __pa(vmx->vcpu.arch.apic->regs));
4512                 vmcs_write32(TPR_THRESHOLD, 0);
4513         }
4514
4515         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4516
4517         if (vmx_vm_has_apicv(vcpu->kvm))
4518                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4519
4520         if (vmx->vpid != 0)
4521                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4522
4523         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4524         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4525         vmx_set_cr4(&vmx->vcpu, 0);
4526         vmx_set_efer(&vmx->vcpu, 0);
4527         vmx_fpu_activate(&vmx->vcpu);
4528         update_exception_bitmap(&vmx->vcpu);
4529
4530         vpid_sync_context(vmx);
4531 }
4532
4533 /*
4534  * In nested virtualization, check if L1 asked to exit on external interrupts.
4535  * For most existing hypervisors, this will always return true.
4536  */
4537 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4538 {
4539         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4540                 PIN_BASED_EXT_INTR_MASK;
4541 }
4542
4543 /*
4544  * In nested virtualization, check if L1 has set
4545  * VM_EXIT_ACK_INTR_ON_EXIT
4546  */
4547 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4548 {
4549         return get_vmcs12(vcpu)->vm_exit_controls &
4550                 VM_EXIT_ACK_INTR_ON_EXIT;
4551 }
4552
4553 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4554 {
4555         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4556                 PIN_BASED_NMI_EXITING;
4557 }
4558
4559 static void enable_irq_window(struct kvm_vcpu *vcpu)
4560 {
4561         u32 cpu_based_vm_exec_control;
4562
4563         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4564         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4565         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4566 }
4567
4568 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4569 {
4570         u32 cpu_based_vm_exec_control;
4571
4572         if (!cpu_has_virtual_nmis() ||
4573             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4574                 enable_irq_window(vcpu);
4575                 return;
4576         }
4577
4578         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4579         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4580         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4581 }
4582
4583 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4584 {
4585         struct vcpu_vmx *vmx = to_vmx(vcpu);
4586         uint32_t intr;
4587         int irq = vcpu->arch.interrupt.nr;
4588
4589         trace_kvm_inj_virq(irq);
4590
4591         ++vcpu->stat.irq_injections;
4592         if (vmx->rmode.vm86_active) {
4593                 int inc_eip = 0;
4594                 if (vcpu->arch.interrupt.soft)
4595                         inc_eip = vcpu->arch.event_exit_inst_len;
4596                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4597                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4598                 return;
4599         }
4600         intr = irq | INTR_INFO_VALID_MASK;
4601         if (vcpu->arch.interrupt.soft) {
4602                 intr |= INTR_TYPE_SOFT_INTR;
4603                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4604                              vmx->vcpu.arch.event_exit_inst_len);
4605         } else
4606                 intr |= INTR_TYPE_EXT_INTR;
4607         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4608 }
4609
4610 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4611 {
4612         struct vcpu_vmx *vmx = to_vmx(vcpu);
4613
4614         if (is_guest_mode(vcpu))
4615                 return;
4616
4617         if (!cpu_has_virtual_nmis()) {
4618                 /*
4619                  * Tracking the NMI-blocked state in software is built upon
4620                  * finding the next open IRQ window. This, in turn, depends on
4621                  * well-behaving guests: They have to keep IRQs disabled at
4622                  * least as long as the NMI handler runs. Otherwise we may
4623                  * cause NMI nesting, maybe breaking the guest. But as this is
4624                  * highly unlikely, we can live with the residual risk.
4625                  */
4626                 vmx->soft_vnmi_blocked = 1;
4627                 vmx->vnmi_blocked_time = 0;
4628         }
4629
4630         ++vcpu->stat.nmi_injections;
4631         vmx->nmi_known_unmasked = false;
4632         if (vmx->rmode.vm86_active) {
4633                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4634                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4635                 return;
4636         }
4637         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4638                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4639 }
4640
4641 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4642 {
4643         if (!cpu_has_virtual_nmis())
4644                 return to_vmx(vcpu)->soft_vnmi_blocked;
4645         if (to_vmx(vcpu)->nmi_known_unmasked)
4646                 return false;
4647         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4648 }
4649
4650 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4651 {
4652         struct vcpu_vmx *vmx = to_vmx(vcpu);
4653
4654         if (!cpu_has_virtual_nmis()) {
4655                 if (vmx->soft_vnmi_blocked != masked) {
4656                         vmx->soft_vnmi_blocked = masked;
4657                         vmx->vnmi_blocked_time = 0;
4658                 }
4659         } else {
4660                 vmx->nmi_known_unmasked = !masked;
4661                 if (masked)
4662                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4663                                       GUEST_INTR_STATE_NMI);
4664                 else
4665                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4666                                         GUEST_INTR_STATE_NMI);
4667         }
4668 }
4669
4670 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4671 {
4672         if (to_vmx(vcpu)->nested.nested_run_pending)
4673                 return 0;
4674
4675         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4676                 return 0;
4677
4678         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4679                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4680                    | GUEST_INTR_STATE_NMI));
4681 }
4682
4683 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4684 {
4685         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4686                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4687                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4688                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4689 }
4690
4691 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4692 {
4693         int ret;
4694         struct kvm_userspace_memory_region tss_mem = {
4695                 .slot = TSS_PRIVATE_MEMSLOT,
4696                 .guest_phys_addr = addr,
4697                 .memory_size = PAGE_SIZE * 3,
4698                 .flags = 0,
4699         };
4700
4701         ret = kvm_set_memory_region(kvm, &tss_mem);
4702         if (ret)
4703                 return ret;
4704         kvm->arch.tss_addr = addr;
4705         return init_rmode_tss(kvm);
4706 }
4707
4708 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4709 {
4710         switch (vec) {
4711         case BP_VECTOR:
4712                 /*
4713                  * Update instruction length as we may reinject the exception
4714                  * from user space while in guest debugging mode.
4715                  */
4716                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4717                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4718                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4719                         return false;
4720                 /* fall through */
4721         case DB_VECTOR:
4722                 if (vcpu->guest_debug &
4723                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4724                         return false;
4725                 /* fall through */
4726         case DE_VECTOR:
4727         case OF_VECTOR:
4728         case BR_VECTOR:
4729         case UD_VECTOR:
4730         case DF_VECTOR:
4731         case SS_VECTOR:
4732         case GP_VECTOR:
4733         case MF_VECTOR:
4734                 return true;
4735         break;
4736         }
4737         return false;
4738 }
4739
4740 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4741                                   int vec, u32 err_code)
4742 {
4743         /*
4744          * Instruction with address size override prefix opcode 0x67
4745          * Cause the #SS fault with 0 error code in VM86 mode.
4746          */
4747         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4748                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4749                         if (vcpu->arch.halt_request) {
4750                                 vcpu->arch.halt_request = 0;
4751                                 return kvm_emulate_halt(vcpu);
4752                         }
4753                         return 1;
4754                 }
4755                 return 0;
4756         }
4757
4758         /*
4759          * Forward all other exceptions that are valid in real mode.
4760          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4761          *        the required debugging infrastructure rework.
4762          */
4763         kvm_queue_exception(vcpu, vec);
4764         return 1;
4765 }
4766
4767 /*
4768  * Trigger machine check on the host. We assume all the MSRs are already set up
4769  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4770  * We pass a fake environment to the machine check handler because we want
4771  * the guest to be always treated like user space, no matter what context
4772  * it used internally.
4773  */
4774 static void kvm_machine_check(void)
4775 {
4776 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4777         struct pt_regs regs = {
4778                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4779                 .flags = X86_EFLAGS_IF,
4780         };
4781
4782         do_machine_check(&regs, 0);
4783 #endif
4784 }
4785
4786 static int handle_machine_check(struct kvm_vcpu *vcpu)
4787 {
4788         /* already handled by vcpu_run */
4789         return 1;
4790 }
4791
4792 static int handle_exception(struct kvm_vcpu *vcpu)
4793 {
4794         struct vcpu_vmx *vmx = to_vmx(vcpu);
4795         struct kvm_run *kvm_run = vcpu->run;
4796         u32 intr_info, ex_no, error_code;
4797         unsigned long cr2, rip, dr6;
4798         u32 vect_info;
4799         enum emulation_result er;
4800
4801         vect_info = vmx->idt_vectoring_info;
4802         intr_info = vmx->exit_intr_info;
4803
4804         if (is_machine_check(intr_info))
4805                 return handle_machine_check(vcpu);
4806
4807         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4808                 return 1;  /* already handled by vmx_vcpu_run() */
4809
4810         if (is_no_device(intr_info)) {
4811                 vmx_fpu_activate(vcpu);
4812                 return 1;
4813         }
4814
4815         if (is_invalid_opcode(intr_info)) {
4816                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4817                 if (er != EMULATE_DONE)
4818                         kvm_queue_exception(vcpu, UD_VECTOR);
4819                 return 1;
4820         }
4821
4822         error_code = 0;
4823         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4824                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4825
4826         /*
4827          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4828          * MMIO, it is better to report an internal error.
4829          * See the comments in vmx_handle_exit.
4830          */
4831         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4832             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4833                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4834                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4835                 vcpu->run->internal.ndata = 2;
4836                 vcpu->run->internal.data[0] = vect_info;
4837                 vcpu->run->internal.data[1] = intr_info;
4838                 return 0;
4839         }
4840
4841         if (is_page_fault(intr_info)) {
4842                 /* EPT won't cause page fault directly */
4843                 BUG_ON(enable_ept);
4844                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4845                 trace_kvm_page_fault(cr2, error_code);
4846
4847                 if (kvm_event_needs_reinjection(vcpu))
4848                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4849                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4850         }
4851
4852         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4853
4854         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4855                 return handle_rmode_exception(vcpu, ex_no, error_code);
4856
4857         switch (ex_no) {
4858         case DB_VECTOR:
4859                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4860                 if (!(vcpu->guest_debug &
4861                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4862                         vcpu->arch.dr6 &= ~15;
4863                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4864                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4865                                 skip_emulated_instruction(vcpu);
4866
4867                         kvm_queue_exception(vcpu, DB_VECTOR);
4868                         return 1;
4869                 }
4870                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4871                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4872                 /* fall through */
4873         case BP_VECTOR:
4874                 /*
4875                  * Update instruction length as we may reinject #BP from
4876                  * user space while in guest debugging mode. Reading it for
4877                  * #DB as well causes no harm, it is not used in that case.
4878                  */
4879                 vmx->vcpu.arch.event_exit_inst_len =
4880                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4881                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4882                 rip = kvm_rip_read(vcpu);
4883                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4884                 kvm_run->debug.arch.exception = ex_no;
4885                 break;
4886         default:
4887                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4888                 kvm_run->ex.exception = ex_no;
4889                 kvm_run->ex.error_code = error_code;
4890                 break;
4891         }
4892         return 0;
4893 }
4894
4895 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4896 {
4897         ++vcpu->stat.irq_exits;
4898         return 1;
4899 }
4900
4901 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4902 {
4903         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4904         return 0;
4905 }
4906
4907 static int handle_io(struct kvm_vcpu *vcpu)
4908 {
4909         unsigned long exit_qualification;
4910         int size, in, string;
4911         unsigned port;
4912
4913         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4914         string = (exit_qualification & 16) != 0;
4915         in = (exit_qualification & 8) != 0;
4916
4917         ++vcpu->stat.io_exits;
4918
4919         if (string || in)
4920                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4921
4922         port = exit_qualification >> 16;
4923         size = (exit_qualification & 7) + 1;
4924         skip_emulated_instruction(vcpu);
4925
4926         return kvm_fast_pio_out(vcpu, size, port);
4927 }
4928
4929 static void
4930 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4931 {
4932         /*
4933          * Patch in the VMCALL instruction:
4934          */
4935         hypercall[0] = 0x0f;
4936         hypercall[1] = 0x01;
4937         hypercall[2] = 0xc1;
4938 }
4939
4940 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4941 {
4942         unsigned long always_on = VMXON_CR0_ALWAYSON;
4943
4944         if (nested_vmx_secondary_ctls_high &
4945                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4946             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4947                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4948         return (val & always_on) == always_on;
4949 }
4950
4951 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4952 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4953 {
4954         if (is_guest_mode(vcpu)) {
4955                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4956                 unsigned long orig_val = val;
4957
4958                 /*
4959                  * We get here when L2 changed cr0 in a way that did not change
4960                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4961                  * but did change L0 shadowed bits. So we first calculate the
4962                  * effective cr0 value that L1 would like to write into the
4963                  * hardware. It consists of the L2-owned bits from the new
4964                  * value combined with the L1-owned bits from L1's guest_cr0.
4965                  */
4966                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4967                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4968
4969                 if (!nested_cr0_valid(vmcs12, val))
4970                         return 1;
4971
4972                 if (kvm_set_cr0(vcpu, val))
4973                         return 1;
4974                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4975                 return 0;
4976         } else {
4977                 if (to_vmx(vcpu)->nested.vmxon &&
4978                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4979                         return 1;
4980                 return kvm_set_cr0(vcpu, val);
4981         }
4982 }
4983
4984 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4985 {
4986         if (is_guest_mode(vcpu)) {
4987                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4988                 unsigned long orig_val = val;
4989
4990                 /* analogously to handle_set_cr0 */
4991                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4992                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4993                 if (kvm_set_cr4(vcpu, val))
4994                         return 1;
4995                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4996                 return 0;
4997         } else
4998                 return kvm_set_cr4(vcpu, val);
4999 }
5000
5001 /* called to set cr0 as approriate for clts instruction exit. */
5002 static void handle_clts(struct kvm_vcpu *vcpu)
5003 {
5004         if (is_guest_mode(vcpu)) {
5005                 /*
5006                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5007                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5008                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5009                  */
5010                 vmcs_writel(CR0_READ_SHADOW,
5011                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5012                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5013         } else
5014                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5015 }
5016
5017 static int handle_cr(struct kvm_vcpu *vcpu)
5018 {
5019         unsigned long exit_qualification, val;
5020         int cr;
5021         int reg;
5022         int err;
5023
5024         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5025         cr = exit_qualification & 15;
5026         reg = (exit_qualification >> 8) & 15;
5027         switch ((exit_qualification >> 4) & 3) {
5028         case 0: /* mov to cr */
5029                 val = kvm_register_readl(vcpu, reg);
5030                 trace_kvm_cr_write(cr, val);
5031                 switch (cr) {
5032                 case 0:
5033                         err = handle_set_cr0(vcpu, val);
5034                         kvm_complete_insn_gp(vcpu, err);
5035                         return 1;
5036                 case 3:
5037                         err = kvm_set_cr3(vcpu, val);
5038                         kvm_complete_insn_gp(vcpu, err);
5039                         return 1;
5040                 case 4:
5041                         err = handle_set_cr4(vcpu, val);
5042                         kvm_complete_insn_gp(vcpu, err);
5043                         return 1;
5044                 case 8: {
5045                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5046                                 u8 cr8 = (u8)val;
5047                                 err = kvm_set_cr8(vcpu, cr8);
5048                                 kvm_complete_insn_gp(vcpu, err);
5049                                 if (irqchip_in_kernel(vcpu->kvm))
5050                                         return 1;
5051                                 if (cr8_prev <= cr8)
5052                                         return 1;
5053                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5054                                 return 0;
5055                         }
5056                 }
5057                 break;
5058         case 2: /* clts */
5059                 handle_clts(vcpu);
5060                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5061                 skip_emulated_instruction(vcpu);
5062                 vmx_fpu_activate(vcpu);
5063                 return 1;
5064         case 1: /*mov from cr*/
5065                 switch (cr) {
5066                 case 3:
5067                         val = kvm_read_cr3(vcpu);
5068                         kvm_register_write(vcpu, reg, val);
5069                         trace_kvm_cr_read(cr, val);
5070                         skip_emulated_instruction(vcpu);
5071                         return 1;
5072                 case 8:
5073                         val = kvm_get_cr8(vcpu);
5074                         kvm_register_write(vcpu, reg, val);
5075                         trace_kvm_cr_read(cr, val);
5076                         skip_emulated_instruction(vcpu);
5077                         return 1;
5078                 }
5079                 break;
5080         case 3: /* lmsw */
5081                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5082                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5083                 kvm_lmsw(vcpu, val);
5084
5085                 skip_emulated_instruction(vcpu);
5086                 return 1;
5087         default:
5088                 break;
5089         }
5090         vcpu->run->exit_reason = 0;
5091         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5092                (int)(exit_qualification >> 4) & 3, cr);
5093         return 0;
5094 }
5095
5096 static int handle_dr(struct kvm_vcpu *vcpu)
5097 {
5098         unsigned long exit_qualification;
5099         int dr, dr7, reg;
5100
5101         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5102         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5103
5104         /* First, if DR does not exist, trigger UD */
5105         if (!kvm_require_dr(vcpu, dr))
5106                 return 1;
5107
5108         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5109         if (!kvm_require_cpl(vcpu, 0))
5110                 return 1;
5111         dr7 = vmcs_readl(GUEST_DR7);
5112         if (dr7 & DR7_GD) {
5113                 /*
5114                  * As the vm-exit takes precedence over the debug trap, we
5115                  * need to emulate the latter, either for the host or the
5116                  * guest debugging itself.
5117                  */
5118                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5119                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5120                         vcpu->run->debug.arch.dr7 = dr7;
5121                         vcpu->run->debug.arch.pc =
5122                                 vmcs_readl(GUEST_CS_BASE) +
5123                                 vmcs_readl(GUEST_RIP);
5124                         vcpu->run->debug.arch.exception = DB_VECTOR;
5125                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5126                         return 0;
5127                 } else {
5128                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5129                         kvm_queue_exception(vcpu, DB_VECTOR);
5130                         return 1;
5131                 }
5132         }
5133
5134         if (vcpu->guest_debug == 0) {
5135                 u32 cpu_based_vm_exec_control;
5136
5137                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5138                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5139                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5140
5141                 /*
5142                  * No more DR vmexits; force a reload of the debug registers
5143                  * and reenter on this instruction.  The next vmexit will
5144                  * retrieve the full state of the debug registers.
5145                  */
5146                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5147                 return 1;
5148         }
5149
5150         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5151         if (exit_qualification & TYPE_MOV_FROM_DR) {
5152                 unsigned long val;
5153
5154                 if (kvm_get_dr(vcpu, dr, &val))
5155                         return 1;
5156                 kvm_register_write(vcpu, reg, val);
5157         } else
5158                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5159                         return 1;
5160
5161         skip_emulated_instruction(vcpu);
5162         return 1;
5163 }
5164
5165 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5166 {
5167         return vcpu->arch.dr6;
5168 }
5169
5170 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5171 {
5172 }
5173
5174 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5175 {
5176         u32 cpu_based_vm_exec_control;
5177
5178         get_debugreg(vcpu->arch.db[0], 0);
5179         get_debugreg(vcpu->arch.db[1], 1);
5180         get_debugreg(vcpu->arch.db[2], 2);
5181         get_debugreg(vcpu->arch.db[3], 3);
5182         get_debugreg(vcpu->arch.dr6, 6);
5183         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5184
5185         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5186
5187         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5188         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5189         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5190 }
5191
5192 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5193 {
5194         vmcs_writel(GUEST_DR7, val);
5195 }
5196
5197 static int handle_cpuid(struct kvm_vcpu *vcpu)
5198 {
5199         kvm_emulate_cpuid(vcpu);
5200         return 1;
5201 }
5202
5203 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5204 {
5205         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5206         u64 data;
5207
5208         if (vmx_get_msr(vcpu, ecx, &data)) {
5209                 trace_kvm_msr_read_ex(ecx);
5210                 kvm_inject_gp(vcpu, 0);
5211                 return 1;
5212         }
5213
5214         trace_kvm_msr_read(ecx, data);
5215
5216         /* FIXME: handling of bits 32:63 of rax, rdx */
5217         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5218         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5219         skip_emulated_instruction(vcpu);
5220         return 1;
5221 }
5222
5223 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5224 {
5225         struct msr_data msr;
5226         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5227         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5228                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5229
5230         msr.data = data;
5231         msr.index = ecx;
5232         msr.host_initiated = false;
5233         if (kvm_set_msr(vcpu, &msr) != 0) {
5234                 trace_kvm_msr_write_ex(ecx, data);
5235                 kvm_inject_gp(vcpu, 0);
5236                 return 1;
5237         }
5238
5239         trace_kvm_msr_write(ecx, data);
5240         skip_emulated_instruction(vcpu);
5241         return 1;
5242 }
5243
5244 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5245 {
5246         kvm_make_request(KVM_REQ_EVENT, vcpu);
5247         return 1;
5248 }
5249
5250 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5251 {
5252         u32 cpu_based_vm_exec_control;
5253
5254         /* clear pending irq */
5255         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5256         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5257         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5258
5259         kvm_make_request(KVM_REQ_EVENT, vcpu);
5260
5261         ++vcpu->stat.irq_window_exits;
5262
5263         /*
5264          * If the user space waits to inject interrupts, exit as soon as
5265          * possible
5266          */
5267         if (!irqchip_in_kernel(vcpu->kvm) &&
5268             vcpu->run->request_interrupt_window &&
5269             !kvm_cpu_has_interrupt(vcpu)) {
5270                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5271                 return 0;
5272         }
5273         return 1;
5274 }
5275
5276 static int handle_halt(struct kvm_vcpu *vcpu)
5277 {
5278         skip_emulated_instruction(vcpu);
5279         return kvm_emulate_halt(vcpu);
5280 }
5281
5282 static int handle_vmcall(struct kvm_vcpu *vcpu)
5283 {
5284         skip_emulated_instruction(vcpu);
5285         kvm_emulate_hypercall(vcpu);
5286         return 1;
5287 }
5288
5289 static int handle_invd(struct kvm_vcpu *vcpu)
5290 {
5291         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5292 }
5293
5294 static int handle_invlpg(struct kvm_vcpu *vcpu)
5295 {
5296         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5297
5298         kvm_mmu_invlpg(vcpu, exit_qualification);
5299         skip_emulated_instruction(vcpu);
5300         return 1;
5301 }
5302
5303 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5304 {
5305         int err;
5306
5307         err = kvm_rdpmc(vcpu);
5308         kvm_complete_insn_gp(vcpu, err);
5309
5310         return 1;
5311 }
5312
5313 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5314 {
5315         skip_emulated_instruction(vcpu);
5316         kvm_emulate_wbinvd(vcpu);
5317         return 1;
5318 }
5319
5320 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5321 {
5322         u64 new_bv = kvm_read_edx_eax(vcpu);
5323         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5324
5325         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5326                 skip_emulated_instruction(vcpu);
5327         return 1;
5328 }
5329
5330 static int handle_apic_access(struct kvm_vcpu *vcpu)
5331 {
5332         if (likely(fasteoi)) {
5333                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5334                 int access_type, offset;
5335
5336                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5337                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5338                 /*
5339                  * Sane guest uses MOV to write EOI, with written value
5340                  * not cared. So make a short-circuit here by avoiding
5341                  * heavy instruction emulation.
5342                  */
5343                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5344                     (offset == APIC_EOI)) {
5345                         kvm_lapic_set_eoi(vcpu);
5346                         skip_emulated_instruction(vcpu);
5347                         return 1;
5348                 }
5349         }
5350         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5351 }
5352
5353 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5354 {
5355         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5356         int vector = exit_qualification & 0xff;
5357
5358         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5359         kvm_apic_set_eoi_accelerated(vcpu, vector);
5360         return 1;
5361 }
5362
5363 static int handle_apic_write(struct kvm_vcpu *vcpu)
5364 {
5365         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5366         u32 offset = exit_qualification & 0xfff;
5367
5368         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5369         kvm_apic_write_nodecode(vcpu, offset);
5370         return 1;
5371 }
5372
5373 static int handle_task_switch(struct kvm_vcpu *vcpu)
5374 {
5375         struct vcpu_vmx *vmx = to_vmx(vcpu);
5376         unsigned long exit_qualification;
5377         bool has_error_code = false;
5378         u32 error_code = 0;
5379         u16 tss_selector;
5380         int reason, type, idt_v, idt_index;
5381
5382         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5383         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5384         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5385
5386         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5387
5388         reason = (u32)exit_qualification >> 30;
5389         if (reason == TASK_SWITCH_GATE && idt_v) {
5390                 switch (type) {
5391                 case INTR_TYPE_NMI_INTR:
5392                         vcpu->arch.nmi_injected = false;
5393                         vmx_set_nmi_mask(vcpu, true);
5394                         break;
5395                 case INTR_TYPE_EXT_INTR:
5396                 case INTR_TYPE_SOFT_INTR:
5397                         kvm_clear_interrupt_queue(vcpu);
5398                         break;
5399                 case INTR_TYPE_HARD_EXCEPTION:
5400                         if (vmx->idt_vectoring_info &
5401                             VECTORING_INFO_DELIVER_CODE_MASK) {
5402                                 has_error_code = true;
5403                                 error_code =
5404                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5405                         }
5406                         /* fall through */
5407                 case INTR_TYPE_SOFT_EXCEPTION:
5408                         kvm_clear_exception_queue(vcpu);
5409                         break;
5410                 default:
5411                         break;
5412                 }
5413         }
5414         tss_selector = exit_qualification;
5415
5416         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5417                        type != INTR_TYPE_EXT_INTR &&
5418                        type != INTR_TYPE_NMI_INTR))
5419                 skip_emulated_instruction(vcpu);
5420
5421         if (kvm_task_switch(vcpu, tss_selector,
5422                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5423                             has_error_code, error_code) == EMULATE_FAIL) {
5424                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5425                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5426                 vcpu->run->internal.ndata = 0;
5427                 return 0;
5428         }
5429
5430         /* clear all local breakpoint enable flags */
5431         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5432
5433         /*
5434          * TODO: What about debug traps on tss switch?
5435          *       Are we supposed to inject them and update dr6?
5436          */
5437
5438         return 1;
5439 }
5440
5441 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5442 {
5443         unsigned long exit_qualification;
5444         gpa_t gpa;
5445         u32 error_code;
5446         int gla_validity;
5447
5448         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5449
5450         gla_validity = (exit_qualification >> 7) & 0x3;
5451         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5452                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5453                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5454                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5455                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5456                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5457                         (long unsigned int)exit_qualification);
5458                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5459                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5460                 return 0;
5461         }
5462
5463         /*
5464          * EPT violation happened while executing iret from NMI,
5465          * "blocked by NMI" bit has to be set before next VM entry.
5466          * There are errata that may cause this bit to not be set:
5467          * AAK134, BY25.
5468          */
5469         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5470                         cpu_has_virtual_nmis() &&
5471                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5472                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5473
5474         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5475         trace_kvm_page_fault(gpa, exit_qualification);
5476
5477         /* It is a write fault? */
5478         error_code = exit_qualification & (1U << 1);
5479         /* It is a fetch fault? */
5480         error_code |= (exit_qualification & (1U << 2)) << 2;
5481         /* ept page table is present? */
5482         error_code |= (exit_qualification >> 3) & 0x1;
5483
5484         vcpu->arch.exit_qualification = exit_qualification;
5485
5486         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5487 }
5488
5489 static u64 ept_rsvd_mask(u64 spte, int level)
5490 {
5491         int i;
5492         u64 mask = 0;
5493
5494         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5495                 mask |= (1ULL << i);
5496
5497         if (level == 4)
5498                 /* bits 7:3 reserved */
5499                 mask |= 0xf8;
5500         else if (spte & (1ULL << 7))
5501                 /*
5502                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5503                  * level == 1 if the hypervisor is using the ignored bit 7.
5504                  */
5505                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5506         else if (level > 1)
5507                 /* bits 6:3 reserved */
5508                 mask |= 0x78;
5509
5510         return mask;
5511 }
5512
5513 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5514                                        int level)
5515 {
5516         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5517
5518         /* 010b (write-only) */
5519         WARN_ON((spte & 0x7) == 0x2);
5520
5521         /* 110b (write/execute) */
5522         WARN_ON((spte & 0x7) == 0x6);
5523
5524         /* 100b (execute-only) and value not supported by logical processor */
5525         if (!cpu_has_vmx_ept_execute_only())
5526                 WARN_ON((spte & 0x7) == 0x4);
5527
5528         /* not 000b */
5529         if ((spte & 0x7)) {
5530                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5531
5532                 if (rsvd_bits != 0) {
5533                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5534                                          __func__, rsvd_bits);
5535                         WARN_ON(1);
5536                 }
5537
5538                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5539                 if ((rsvd_bits & 0x38) == 0) {
5540                         u64 ept_mem_type = (spte & 0x38) >> 3;
5541
5542                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5543                             ept_mem_type == 7) {
5544                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5545                                                 __func__, ept_mem_type);
5546                                 WARN_ON(1);
5547                         }
5548                 }
5549         }
5550 }
5551
5552 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5553 {
5554         u64 sptes[4];
5555         int nr_sptes, i, ret;
5556         gpa_t gpa;
5557
5558         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5559         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5560                 skip_emulated_instruction(vcpu);
5561                 return 1;
5562         }
5563
5564         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5565         if (likely(ret == RET_MMIO_PF_EMULATE))
5566                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5567                                               EMULATE_DONE;
5568
5569         if (unlikely(ret == RET_MMIO_PF_INVALID))
5570                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5571
5572         if (unlikely(ret == RET_MMIO_PF_RETRY))
5573                 return 1;
5574
5575         /* It is the real ept misconfig */
5576         printk(KERN_ERR "EPT: Misconfiguration.\n");
5577         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5578
5579         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5580
5581         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5582                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5583
5584         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5585         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5586
5587         return 0;
5588 }
5589
5590 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5591 {
5592         u32 cpu_based_vm_exec_control;
5593
5594         /* clear pending NMI */
5595         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5596         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5597         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5598         ++vcpu->stat.nmi_window_exits;
5599         kvm_make_request(KVM_REQ_EVENT, vcpu);
5600
5601         return 1;
5602 }
5603
5604 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5605 {
5606         struct vcpu_vmx *vmx = to_vmx(vcpu);
5607         enum emulation_result err = EMULATE_DONE;
5608         int ret = 1;
5609         u32 cpu_exec_ctrl;
5610         bool intr_window_requested;
5611         unsigned count = 130;
5612
5613         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5614         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5615
5616         while (vmx->emulation_required && count-- != 0) {
5617                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5618                         return handle_interrupt_window(&vmx->vcpu);
5619
5620                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5621                         return 1;
5622
5623                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5624
5625                 if (err == EMULATE_USER_EXIT) {
5626                         ++vcpu->stat.mmio_exits;
5627                         ret = 0;
5628                         goto out;
5629                 }
5630
5631                 if (err != EMULATE_DONE) {
5632                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5633                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5634                         vcpu->run->internal.ndata = 0;
5635                         return 0;
5636                 }
5637
5638                 if (vcpu->arch.halt_request) {
5639                         vcpu->arch.halt_request = 0;
5640                         ret = kvm_emulate_halt(vcpu);
5641                         goto out;
5642                 }
5643
5644                 if (signal_pending(current))
5645                         goto out;
5646                 if (need_resched())
5647                         schedule();
5648         }
5649
5650 out:
5651         return ret;
5652 }
5653
5654 static int __grow_ple_window(int val)
5655 {
5656         if (ple_window_grow < 1)
5657                 return ple_window;
5658
5659         val = min(val, ple_window_actual_max);
5660
5661         if (ple_window_grow < ple_window)
5662                 val *= ple_window_grow;
5663         else
5664                 val += ple_window_grow;
5665
5666         return val;
5667 }
5668
5669 static int __shrink_ple_window(int val, int modifier, int minimum)
5670 {
5671         if (modifier < 1)
5672                 return ple_window;
5673
5674         if (modifier < ple_window)
5675                 val /= modifier;
5676         else
5677                 val -= modifier;
5678
5679         return max(val, minimum);
5680 }
5681
5682 static void grow_ple_window(struct kvm_vcpu *vcpu)
5683 {
5684         struct vcpu_vmx *vmx = to_vmx(vcpu);
5685         int old = vmx->ple_window;
5686
5687         vmx->ple_window = __grow_ple_window(old);
5688
5689         if (vmx->ple_window != old)
5690                 vmx->ple_window_dirty = true;
5691
5692         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5693 }
5694
5695 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5696 {
5697         struct vcpu_vmx *vmx = to_vmx(vcpu);
5698         int old = vmx->ple_window;
5699
5700         vmx->ple_window = __shrink_ple_window(old,
5701                                               ple_window_shrink, ple_window);
5702
5703         if (vmx->ple_window != old)
5704                 vmx->ple_window_dirty = true;
5705
5706         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5707 }
5708
5709 /*
5710  * ple_window_actual_max is computed to be one grow_ple_window() below
5711  * ple_window_max. (See __grow_ple_window for the reason.)
5712  * This prevents overflows, because ple_window_max is int.
5713  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5714  * this process.
5715  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5716  */
5717 static void update_ple_window_actual_max(void)
5718 {
5719         ple_window_actual_max =
5720                         __shrink_ple_window(max(ple_window_max, ple_window),
5721                                             ple_window_grow, INT_MIN);
5722 }
5723
5724 static __init int hardware_setup(void)
5725 {
5726         int r = -ENOMEM, i, msr;
5727
5728         rdmsrl_safe(MSR_EFER, &host_efer);
5729
5730         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5731                 kvm_define_shared_msr(i, vmx_msr_index[i]);
5732
5733         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5734         if (!vmx_io_bitmap_a)
5735                 return r;
5736
5737         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5738         if (!vmx_io_bitmap_b)
5739                 goto out;
5740
5741         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5742         if (!vmx_msr_bitmap_legacy)
5743                 goto out1;
5744
5745         vmx_msr_bitmap_legacy_x2apic =
5746                                 (unsigned long *)__get_free_page(GFP_KERNEL);
5747         if (!vmx_msr_bitmap_legacy_x2apic)
5748                 goto out2;
5749
5750         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5751         if (!vmx_msr_bitmap_longmode)
5752                 goto out3;
5753
5754         vmx_msr_bitmap_longmode_x2apic =
5755                                 (unsigned long *)__get_free_page(GFP_KERNEL);
5756         if (!vmx_msr_bitmap_longmode_x2apic)
5757                 goto out4;
5758         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5759         if (!vmx_vmread_bitmap)
5760                 goto out5;
5761
5762         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5763         if (!vmx_vmwrite_bitmap)
5764                 goto out6;
5765
5766         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5767         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5768
5769         /*
5770          * Allow direct access to the PC debug port (it is often used for I/O
5771          * delays, but the vmexits simply slow things down).
5772          */
5773         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5774         clear_bit(0x80, vmx_io_bitmap_a);
5775
5776         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5777
5778         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5779         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5780
5781         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5782         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5783         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5784         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5785         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5786         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5787         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5788
5789         memcpy(vmx_msr_bitmap_legacy_x2apic,
5790                         vmx_msr_bitmap_legacy, PAGE_SIZE);
5791         memcpy(vmx_msr_bitmap_longmode_x2apic,
5792                         vmx_msr_bitmap_longmode, PAGE_SIZE);
5793
5794         if (enable_apicv) {
5795                 for (msr = 0x800; msr <= 0x8ff; msr++)
5796                         vmx_disable_intercept_msr_read_x2apic(msr);
5797
5798                 /* According SDM, in x2apic mode, the whole id reg is used.
5799                  * But in KVM, it only use the highest eight bits. Need to
5800                  * intercept it */
5801                 vmx_enable_intercept_msr_read_x2apic(0x802);
5802                 /* TMCCT */
5803                 vmx_enable_intercept_msr_read_x2apic(0x839);
5804                 /* TPR */
5805                 vmx_disable_intercept_msr_write_x2apic(0x808);
5806                 /* EOI */
5807                 vmx_disable_intercept_msr_write_x2apic(0x80b);
5808                 /* SELF-IPI */
5809                 vmx_disable_intercept_msr_write_x2apic(0x83f);
5810         }
5811
5812         if (enable_ept) {
5813                 kvm_mmu_set_mask_ptes(0ull,
5814                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5815                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5816                         0ull, VMX_EPT_EXECUTABLE_MASK);
5817                 ept_set_mmio_spte_mask();
5818                 kvm_enable_tdp();
5819         } else
5820                 kvm_disable_tdp();
5821
5822         update_ple_window_actual_max();
5823
5824         if (setup_vmcs_config(&vmcs_config) < 0) {
5825                 r = -EIO;
5826                 goto out7;
5827     }
5828
5829         if (boot_cpu_has(X86_FEATURE_NX))
5830                 kvm_enable_efer_bits(EFER_NX);
5831
5832         if (!cpu_has_vmx_vpid())
5833                 enable_vpid = 0;
5834         if (!cpu_has_vmx_shadow_vmcs())
5835                 enable_shadow_vmcs = 0;
5836         if (enable_shadow_vmcs)
5837                 init_vmcs_shadow_fields();
5838
5839         if (!cpu_has_vmx_ept() ||
5840             !cpu_has_vmx_ept_4levels()) {
5841                 enable_ept = 0;
5842                 enable_unrestricted_guest = 0;
5843                 enable_ept_ad_bits = 0;
5844         }
5845
5846         if (!cpu_has_vmx_ept_ad_bits())
5847                 enable_ept_ad_bits = 0;
5848
5849         if (!cpu_has_vmx_unrestricted_guest())
5850                 enable_unrestricted_guest = 0;
5851
5852         if (!cpu_has_vmx_flexpriority()) {
5853                 flexpriority_enabled = 0;
5854
5855                 /*
5856                  * set_apic_access_page_addr() is used to reload apic access
5857                  * page upon invalidation.  No need to do anything if the
5858                  * processor does not have the APIC_ACCESS_ADDR VMCS field.
5859                  */
5860                 kvm_x86_ops->set_apic_access_page_addr = NULL;
5861         }
5862
5863         if (!cpu_has_vmx_tpr_shadow())
5864                 kvm_x86_ops->update_cr8_intercept = NULL;
5865
5866         if (enable_ept && !cpu_has_vmx_ept_2m_page())
5867                 kvm_disable_largepages();
5868
5869         if (!cpu_has_vmx_ple())
5870                 ple_gap = 0;
5871
5872         if (!cpu_has_vmx_apicv())
5873                 enable_apicv = 0;
5874
5875         if (enable_apicv)
5876                 kvm_x86_ops->update_cr8_intercept = NULL;
5877         else {
5878                 kvm_x86_ops->hwapic_irr_update = NULL;
5879                 kvm_x86_ops->deliver_posted_interrupt = NULL;
5880                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5881         }
5882
5883         if (nested)
5884                 nested_vmx_setup_ctls_msrs();
5885
5886         return alloc_kvm_area();
5887
5888 out7:
5889         free_page((unsigned long)vmx_vmwrite_bitmap);
5890 out6:
5891         free_page((unsigned long)vmx_vmread_bitmap);
5892 out5:
5893         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5894 out4:
5895         free_page((unsigned long)vmx_msr_bitmap_longmode);
5896 out3:
5897         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5898 out2:
5899         free_page((unsigned long)vmx_msr_bitmap_legacy);
5900 out1:
5901         free_page((unsigned long)vmx_io_bitmap_b);
5902 out:
5903         free_page((unsigned long)vmx_io_bitmap_a);
5904
5905     return r;
5906 }
5907
5908 static __exit void hardware_unsetup(void)
5909 {
5910         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5911         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5912         free_page((unsigned long)vmx_msr_bitmap_legacy);
5913         free_page((unsigned long)vmx_msr_bitmap_longmode);
5914         free_page((unsigned long)vmx_io_bitmap_b);
5915         free_page((unsigned long)vmx_io_bitmap_a);
5916         free_page((unsigned long)vmx_vmwrite_bitmap);
5917         free_page((unsigned long)vmx_vmread_bitmap);
5918
5919         free_kvm_area();
5920 }
5921
5922 /*
5923  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5924  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5925  */
5926 static int handle_pause(struct kvm_vcpu *vcpu)
5927 {
5928         if (ple_gap)
5929                 grow_ple_window(vcpu);
5930
5931         skip_emulated_instruction(vcpu);
5932         kvm_vcpu_on_spin(vcpu);
5933
5934         return 1;
5935 }
5936
5937 static int handle_nop(struct kvm_vcpu *vcpu)
5938 {
5939         skip_emulated_instruction(vcpu);
5940         return 1;
5941 }
5942
5943 static int handle_mwait(struct kvm_vcpu *vcpu)
5944 {
5945         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5946         return handle_nop(vcpu);
5947 }
5948
5949 static int handle_monitor(struct kvm_vcpu *vcpu)
5950 {
5951         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5952         return handle_nop(vcpu);
5953 }
5954
5955 /*
5956  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5957  * We could reuse a single VMCS for all the L2 guests, but we also want the
5958  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5959  * allows keeping them loaded on the processor, and in the future will allow
5960  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5961  * every entry if they never change.
5962  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5963  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5964  *
5965  * The following functions allocate and free a vmcs02 in this pool.
5966  */
5967
5968 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5969 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5970 {
5971         struct vmcs02_list *item;
5972         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5973                 if (item->vmptr == vmx->nested.current_vmptr) {
5974                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5975                         return &item->vmcs02;
5976                 }
5977
5978         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5979                 /* Recycle the least recently used VMCS. */
5980                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5981                         struct vmcs02_list, list);
5982                 item->vmptr = vmx->nested.current_vmptr;
5983                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5984                 return &item->vmcs02;
5985         }
5986
5987         /* Create a new VMCS */
5988         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5989         if (!item)
5990                 return NULL;
5991         item->vmcs02.vmcs = alloc_vmcs();
5992         if (!item->vmcs02.vmcs) {
5993                 kfree(item);
5994                 return NULL;
5995         }
5996         loaded_vmcs_init(&item->vmcs02);
5997         item->vmptr = vmx->nested.current_vmptr;
5998         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5999         vmx->nested.vmcs02_num++;
6000         return &item->vmcs02;
6001 }
6002
6003 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6004 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6005 {
6006         struct vmcs02_list *item;
6007         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6008                 if (item->vmptr == vmptr) {
6009                         free_loaded_vmcs(&item->vmcs02);
6010                         list_del(&item->list);
6011                         kfree(item);
6012                         vmx->nested.vmcs02_num--;
6013                         return;
6014                 }
6015 }
6016
6017 /*
6018  * Free all VMCSs saved for this vcpu, except the one pointed by
6019  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6020  * must be &vmx->vmcs01.
6021  */
6022 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6023 {
6024         struct vmcs02_list *item, *n;
6025
6026         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6027         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6028                 /*
6029                  * Something will leak if the above WARN triggers.  Better than
6030                  * a use-after-free.
6031                  */
6032                 if (vmx->loaded_vmcs == &item->vmcs02)
6033                         continue;
6034
6035                 free_loaded_vmcs(&item->vmcs02);
6036                 list_del(&item->list);
6037                 kfree(item);
6038                 vmx->nested.vmcs02_num--;
6039         }
6040 }
6041
6042 /*
6043  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6044  * set the success or error code of an emulated VMX instruction, as specified
6045  * by Vol 2B, VMX Instruction Reference, "Conventions".
6046  */
6047 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6048 {
6049         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6050                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6051                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6052 }
6053
6054 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6055 {
6056         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6057                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6058                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6059                         | X86_EFLAGS_CF);
6060 }
6061
6062 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6063                                         u32 vm_instruction_error)
6064 {
6065         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6066                 /*
6067                  * failValid writes the error number to the current VMCS, which
6068                  * can't be done there isn't a current VMCS.
6069                  */
6070                 nested_vmx_failInvalid(vcpu);
6071                 return;
6072         }
6073         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6074                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6075                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6076                         | X86_EFLAGS_ZF);
6077         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6078         /*
6079          * We don't need to force a shadow sync because
6080          * VM_INSTRUCTION_ERROR is not shadowed
6081          */
6082 }
6083
6084 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6085 {
6086         struct vcpu_vmx *vmx =
6087                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6088
6089         vmx->nested.preemption_timer_expired = true;
6090         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6091         kvm_vcpu_kick(&vmx->vcpu);
6092
6093         return HRTIMER_NORESTART;
6094 }
6095
6096 /*
6097  * Decode the memory-address operand of a vmx instruction, as recorded on an
6098  * exit caused by such an instruction (run by a guest hypervisor).
6099  * On success, returns 0. When the operand is invalid, returns 1 and throws
6100  * #UD or #GP.
6101  */
6102 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6103                                  unsigned long exit_qualification,
6104                                  u32 vmx_instruction_info, gva_t *ret)
6105 {
6106         /*
6107          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6108          * Execution", on an exit, vmx_instruction_info holds most of the
6109          * addressing components of the operand. Only the displacement part
6110          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6111          * For how an actual address is calculated from all these components,
6112          * refer to Vol. 1, "Operand Addressing".
6113          */
6114         int  scaling = vmx_instruction_info & 3;
6115         int  addr_size = (vmx_instruction_info >> 7) & 7;
6116         bool is_reg = vmx_instruction_info & (1u << 10);
6117         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6118         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6119         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6120         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6121         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6122
6123         if (is_reg) {
6124                 kvm_queue_exception(vcpu, UD_VECTOR);
6125                 return 1;
6126         }
6127
6128         /* Addr = segment_base + offset */
6129         /* offset = base + [index * scale] + displacement */
6130         *ret = vmx_get_segment_base(vcpu, seg_reg);
6131         if (base_is_valid)
6132                 *ret += kvm_register_read(vcpu, base_reg);
6133         if (index_is_valid)
6134                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6135         *ret += exit_qualification; /* holds the displacement */
6136
6137         if (addr_size == 1) /* 32 bit */
6138                 *ret &= 0xffffffff;
6139
6140         /*
6141          * TODO: throw #GP (and return 1) in various cases that the VM*
6142          * instructions require it - e.g., offset beyond segment limit,
6143          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6144          * address, and so on. Currently these are not checked.
6145          */
6146         return 0;
6147 }
6148
6149 /*
6150  * This function performs the various checks including
6151  * - if it's 4KB aligned
6152  * - No bits beyond the physical address width are set
6153  * - Returns 0 on success or else 1
6154  * (Intel SDM Section 30.3)
6155  */
6156 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6157                                   gpa_t *vmpointer)
6158 {
6159         gva_t gva;
6160         gpa_t vmptr;
6161         struct x86_exception e;
6162         struct page *page;
6163         struct vcpu_vmx *vmx = to_vmx(vcpu);
6164         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6165
6166         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6167                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6168                 return 1;
6169
6170         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6171                                 sizeof(vmptr), &e)) {
6172                 kvm_inject_page_fault(vcpu, &e);
6173                 return 1;
6174         }
6175
6176         switch (exit_reason) {
6177         case EXIT_REASON_VMON:
6178                 /*
6179                  * SDM 3: 24.11.5
6180                  * The first 4 bytes of VMXON region contain the supported
6181                  * VMCS revision identifier
6182                  *
6183                  * Note - IA32_VMX_BASIC[48] will never be 1
6184                  * for the nested case;
6185                  * which replaces physical address width with 32
6186                  *
6187                  */
6188                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6189                         nested_vmx_failInvalid(vcpu);
6190                         skip_emulated_instruction(vcpu);
6191                         return 1;
6192                 }
6193
6194                 page = nested_get_page(vcpu, vmptr);
6195                 if (page == NULL ||
6196                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6197                         nested_vmx_failInvalid(vcpu);
6198                         kunmap(page);
6199                         skip_emulated_instruction(vcpu);
6200                         return 1;
6201                 }
6202                 kunmap(page);
6203                 vmx->nested.vmxon_ptr = vmptr;
6204                 break;
6205         case EXIT_REASON_VMCLEAR:
6206                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6207                         nested_vmx_failValid(vcpu,
6208                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6209                         skip_emulated_instruction(vcpu);
6210                         return 1;
6211                 }
6212
6213                 if (vmptr == vmx->nested.vmxon_ptr) {
6214                         nested_vmx_failValid(vcpu,
6215                                              VMXERR_VMCLEAR_VMXON_POINTER);
6216                         skip_emulated_instruction(vcpu);
6217                         return 1;
6218                 }
6219                 break;
6220         case EXIT_REASON_VMPTRLD:
6221                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6222                         nested_vmx_failValid(vcpu,
6223                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6224                         skip_emulated_instruction(vcpu);
6225                         return 1;
6226                 }
6227
6228                 if (vmptr == vmx->nested.vmxon_ptr) {
6229                         nested_vmx_failValid(vcpu,
6230                                              VMXERR_VMCLEAR_VMXON_POINTER);
6231                         skip_emulated_instruction(vcpu);
6232                         return 1;
6233                 }
6234                 break;
6235         default:
6236                 return 1; /* shouldn't happen */
6237         }
6238
6239         if (vmpointer)
6240                 *vmpointer = vmptr;
6241         return 0;
6242 }
6243
6244 /*
6245  * Emulate the VMXON instruction.
6246  * Currently, we just remember that VMX is active, and do not save or even
6247  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6248  * do not currently need to store anything in that guest-allocated memory
6249  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6250  * argument is different from the VMXON pointer (which the spec says they do).
6251  */
6252 static int handle_vmon(struct kvm_vcpu *vcpu)
6253 {
6254         struct kvm_segment cs;
6255         struct vcpu_vmx *vmx = to_vmx(vcpu);
6256         struct vmcs *shadow_vmcs;
6257         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6258                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6259
6260         /* The Intel VMX Instruction Reference lists a bunch of bits that
6261          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6262          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6263          * Otherwise, we should fail with #UD. We test these now:
6264          */
6265         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6266             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6267             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6268                 kvm_queue_exception(vcpu, UD_VECTOR);
6269                 return 1;
6270         }
6271
6272         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6273         if (is_long_mode(vcpu) && !cs.l) {
6274                 kvm_queue_exception(vcpu, UD_VECTOR);
6275                 return 1;
6276         }
6277
6278         if (vmx_get_cpl(vcpu)) {
6279                 kvm_inject_gp(vcpu, 0);
6280                 return 1;
6281         }
6282
6283         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6284                 return 1;
6285
6286         if (vmx->nested.vmxon) {
6287                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6288                 skip_emulated_instruction(vcpu);
6289                 return 1;
6290         }
6291
6292         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6293                         != VMXON_NEEDED_FEATURES) {
6294                 kvm_inject_gp(vcpu, 0);
6295                 return 1;
6296         }
6297
6298         if (enable_shadow_vmcs) {
6299                 shadow_vmcs = alloc_vmcs();
6300                 if (!shadow_vmcs)
6301                         return -ENOMEM;
6302                 /* mark vmcs as shadow */
6303                 shadow_vmcs->revision_id |= (1u << 31);
6304                 /* init shadow vmcs */
6305                 vmcs_clear(shadow_vmcs);
6306                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6307         }
6308
6309         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6310         vmx->nested.vmcs02_num = 0;
6311
6312         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6313                      HRTIMER_MODE_REL);
6314         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6315
6316         vmx->nested.vmxon = true;
6317
6318         skip_emulated_instruction(vcpu);
6319         nested_vmx_succeed(vcpu);
6320         return 1;
6321 }
6322
6323 /*
6324  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6325  * for running VMX instructions (except VMXON, whose prerequisites are
6326  * slightly different). It also specifies what exception to inject otherwise.
6327  */
6328 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6329 {
6330         struct kvm_segment cs;
6331         struct vcpu_vmx *vmx = to_vmx(vcpu);
6332
6333         if (!vmx->nested.vmxon) {
6334                 kvm_queue_exception(vcpu, UD_VECTOR);
6335                 return 0;
6336         }
6337
6338         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6339         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6340             (is_long_mode(vcpu) && !cs.l)) {
6341                 kvm_queue_exception(vcpu, UD_VECTOR);
6342                 return 0;
6343         }
6344
6345         if (vmx_get_cpl(vcpu)) {
6346                 kvm_inject_gp(vcpu, 0);
6347                 return 0;
6348         }
6349
6350         return 1;
6351 }
6352
6353 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6354 {
6355         u32 exec_control;
6356         if (vmx->nested.current_vmptr == -1ull)
6357                 return;
6358
6359         /* current_vmptr and current_vmcs12 are always set/reset together */
6360         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6361                 return;
6362
6363         if (enable_shadow_vmcs) {
6364                 /* copy to memory all shadowed fields in case
6365                    they were modified */
6366                 copy_shadow_to_vmcs12(vmx);
6367                 vmx->nested.sync_shadow_vmcs = false;
6368                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6369                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6370                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6371                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6372         }
6373         kunmap(vmx->nested.current_vmcs12_page);
6374         nested_release_page(vmx->nested.current_vmcs12_page);
6375         vmx->nested.current_vmptr = -1ull;
6376         vmx->nested.current_vmcs12 = NULL;
6377 }
6378
6379 /*
6380  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6381  * just stops using VMX.
6382  */
6383 static void free_nested(struct vcpu_vmx *vmx)
6384 {
6385         if (!vmx->nested.vmxon)
6386                 return;
6387
6388         vmx->nested.vmxon = false;
6389         nested_release_vmcs12(vmx);
6390         if (enable_shadow_vmcs)
6391                 free_vmcs(vmx->nested.current_shadow_vmcs);
6392         /* Unpin physical memory we referred to in current vmcs02 */
6393         if (vmx->nested.apic_access_page) {
6394                 nested_release_page(vmx->nested.apic_access_page);
6395                 vmx->nested.apic_access_page = NULL;
6396         }
6397         if (vmx->nested.virtual_apic_page) {
6398                 nested_release_page(vmx->nested.virtual_apic_page);
6399                 vmx->nested.virtual_apic_page = NULL;
6400         }
6401
6402         nested_free_all_saved_vmcss(vmx);
6403 }
6404
6405 /* Emulate the VMXOFF instruction */
6406 static int handle_vmoff(struct kvm_vcpu *vcpu)
6407 {
6408         if (!nested_vmx_check_permission(vcpu))
6409                 return 1;
6410         free_nested(to_vmx(vcpu));
6411         skip_emulated_instruction(vcpu);
6412         nested_vmx_succeed(vcpu);
6413         return 1;
6414 }
6415
6416 /* Emulate the VMCLEAR instruction */
6417 static int handle_vmclear(struct kvm_vcpu *vcpu)
6418 {
6419         struct vcpu_vmx *vmx = to_vmx(vcpu);
6420         gpa_t vmptr;
6421         struct vmcs12 *vmcs12;
6422         struct page *page;
6423
6424         if (!nested_vmx_check_permission(vcpu))
6425                 return 1;
6426
6427         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6428                 return 1;
6429
6430         if (vmptr == vmx->nested.current_vmptr)
6431                 nested_release_vmcs12(vmx);
6432
6433         page = nested_get_page(vcpu, vmptr);
6434         if (page == NULL) {
6435                 /*
6436                  * For accurate processor emulation, VMCLEAR beyond available
6437                  * physical memory should do nothing at all. However, it is
6438                  * possible that a nested vmx bug, not a guest hypervisor bug,
6439                  * resulted in this case, so let's shut down before doing any
6440                  * more damage:
6441                  */
6442                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6443                 return 1;
6444         }
6445         vmcs12 = kmap(page);
6446         vmcs12->launch_state = 0;
6447         kunmap(page);
6448         nested_release_page(page);
6449
6450         nested_free_vmcs02(vmx, vmptr);
6451
6452         skip_emulated_instruction(vcpu);
6453         nested_vmx_succeed(vcpu);
6454         return 1;
6455 }
6456
6457 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6458
6459 /* Emulate the VMLAUNCH instruction */
6460 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6461 {
6462         return nested_vmx_run(vcpu, true);
6463 }
6464
6465 /* Emulate the VMRESUME instruction */
6466 static int handle_vmresume(struct kvm_vcpu *vcpu)
6467 {
6468
6469         return nested_vmx_run(vcpu, false);
6470 }
6471
6472 enum vmcs_field_type {
6473         VMCS_FIELD_TYPE_U16 = 0,
6474         VMCS_FIELD_TYPE_U64 = 1,
6475         VMCS_FIELD_TYPE_U32 = 2,
6476         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6477 };
6478
6479 static inline int vmcs_field_type(unsigned long field)
6480 {
6481         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6482                 return VMCS_FIELD_TYPE_U32;
6483         return (field >> 13) & 0x3 ;
6484 }
6485
6486 static inline int vmcs_field_readonly(unsigned long field)
6487 {
6488         return (((field >> 10) & 0x3) == 1);
6489 }
6490
6491 /*
6492  * Read a vmcs12 field. Since these can have varying lengths and we return
6493  * one type, we chose the biggest type (u64) and zero-extend the return value
6494  * to that size. Note that the caller, handle_vmread, might need to use only
6495  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6496  * 64-bit fields are to be returned).
6497  */
6498 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6499                                   unsigned long field, u64 *ret)
6500 {
6501         short offset = vmcs_field_to_offset(field);
6502         char *p;
6503
6504         if (offset < 0)
6505                 return offset;
6506
6507         p = ((char *)(get_vmcs12(vcpu))) + offset;
6508
6509         switch (vmcs_field_type(field)) {
6510         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6511                 *ret = *((natural_width *)p);
6512                 return 0;
6513         case VMCS_FIELD_TYPE_U16:
6514                 *ret = *((u16 *)p);
6515                 return 0;
6516         case VMCS_FIELD_TYPE_U32:
6517                 *ret = *((u32 *)p);
6518                 return 0;
6519         case VMCS_FIELD_TYPE_U64:
6520                 *ret = *((u64 *)p);
6521                 return 0;
6522         default:
6523                 WARN_ON(1);
6524                 return -ENOENT;
6525         }
6526 }
6527
6528
6529 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6530                                    unsigned long field, u64 field_value){
6531         short offset = vmcs_field_to_offset(field);
6532         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6533         if (offset < 0)
6534                 return offset;
6535
6536         switch (vmcs_field_type(field)) {
6537         case VMCS_FIELD_TYPE_U16:
6538                 *(u16 *)p = field_value;
6539                 return 0;
6540         case VMCS_FIELD_TYPE_U32:
6541                 *(u32 *)p = field_value;
6542                 return 0;
6543         case VMCS_FIELD_TYPE_U64:
6544                 *(u64 *)p = field_value;
6545                 return 0;
6546         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6547                 *(natural_width *)p = field_value;
6548                 return 0;
6549         default:
6550                 WARN_ON(1);
6551                 return -ENOENT;
6552         }
6553
6554 }
6555
6556 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6557 {
6558         int i;
6559         unsigned long field;
6560         u64 field_value;
6561         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6562         const unsigned long *fields = shadow_read_write_fields;
6563         const int num_fields = max_shadow_read_write_fields;
6564
6565         preempt_disable();
6566
6567         vmcs_load(shadow_vmcs);
6568
6569         for (i = 0; i < num_fields; i++) {
6570                 field = fields[i];
6571                 switch (vmcs_field_type(field)) {
6572                 case VMCS_FIELD_TYPE_U16:
6573                         field_value = vmcs_read16(field);
6574                         break;
6575                 case VMCS_FIELD_TYPE_U32:
6576                         field_value = vmcs_read32(field);
6577                         break;
6578                 case VMCS_FIELD_TYPE_U64:
6579                         field_value = vmcs_read64(field);
6580                         break;
6581                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6582                         field_value = vmcs_readl(field);
6583                         break;
6584                 default:
6585                         WARN_ON(1);
6586                         continue;
6587                 }
6588                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6589         }
6590
6591         vmcs_clear(shadow_vmcs);
6592         vmcs_load(vmx->loaded_vmcs->vmcs);
6593
6594         preempt_enable();
6595 }
6596
6597 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6598 {
6599         const unsigned long *fields[] = {
6600                 shadow_read_write_fields,
6601                 shadow_read_only_fields
6602         };
6603         const int max_fields[] = {
6604                 max_shadow_read_write_fields,
6605                 max_shadow_read_only_fields
6606         };
6607         int i, q;
6608         unsigned long field;
6609         u64 field_value = 0;
6610         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6611
6612         vmcs_load(shadow_vmcs);
6613
6614         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6615                 for (i = 0; i < max_fields[q]; i++) {
6616                         field = fields[q][i];
6617                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6618
6619                         switch (vmcs_field_type(field)) {
6620                         case VMCS_FIELD_TYPE_U16:
6621                                 vmcs_write16(field, (u16)field_value);
6622                                 break;
6623                         case VMCS_FIELD_TYPE_U32:
6624                                 vmcs_write32(field, (u32)field_value);
6625                                 break;
6626                         case VMCS_FIELD_TYPE_U64:
6627                                 vmcs_write64(field, (u64)field_value);
6628                                 break;
6629                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6630                                 vmcs_writel(field, (long)field_value);
6631                                 break;
6632                         default:
6633                                 WARN_ON(1);
6634                                 break;
6635                         }
6636                 }
6637         }
6638
6639         vmcs_clear(shadow_vmcs);
6640         vmcs_load(vmx->loaded_vmcs->vmcs);
6641 }
6642
6643 /*
6644  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6645  * used before) all generate the same failure when it is missing.
6646  */
6647 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6648 {
6649         struct vcpu_vmx *vmx = to_vmx(vcpu);
6650         if (vmx->nested.current_vmptr == -1ull) {
6651                 nested_vmx_failInvalid(vcpu);
6652                 skip_emulated_instruction(vcpu);
6653                 return 0;
6654         }
6655         return 1;
6656 }
6657
6658 static int handle_vmread(struct kvm_vcpu *vcpu)
6659 {
6660         unsigned long field;
6661         u64 field_value;
6662         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6663         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6664         gva_t gva = 0;
6665
6666         if (!nested_vmx_check_permission(vcpu) ||
6667             !nested_vmx_check_vmcs12(vcpu))
6668                 return 1;
6669
6670         /* Decode instruction info and find the field to read */
6671         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6672         /* Read the field, zero-extended to a u64 field_value */
6673         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6674                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6675                 skip_emulated_instruction(vcpu);
6676                 return 1;
6677         }
6678         /*
6679          * Now copy part of this value to register or memory, as requested.
6680          * Note that the number of bits actually copied is 32 or 64 depending
6681          * on the guest's mode (32 or 64 bit), not on the given field's length.
6682          */
6683         if (vmx_instruction_info & (1u << 10)) {
6684                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6685                         field_value);
6686         } else {
6687                 if (get_vmx_mem_address(vcpu, exit_qualification,
6688                                 vmx_instruction_info, &gva))
6689                         return 1;
6690                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6691                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6692                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6693         }
6694
6695         nested_vmx_succeed(vcpu);
6696         skip_emulated_instruction(vcpu);
6697         return 1;
6698 }
6699
6700
6701 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6702 {
6703         unsigned long field;
6704         gva_t gva;
6705         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6706         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6707         /* The value to write might be 32 or 64 bits, depending on L1's long
6708          * mode, and eventually we need to write that into a field of several
6709          * possible lengths. The code below first zero-extends the value to 64
6710          * bit (field_value), and then copies only the approriate number of
6711          * bits into the vmcs12 field.
6712          */
6713         u64 field_value = 0;
6714         struct x86_exception e;
6715
6716         if (!nested_vmx_check_permission(vcpu) ||
6717             !nested_vmx_check_vmcs12(vcpu))
6718                 return 1;
6719
6720         if (vmx_instruction_info & (1u << 10))
6721                 field_value = kvm_register_readl(vcpu,
6722                         (((vmx_instruction_info) >> 3) & 0xf));
6723         else {
6724                 if (get_vmx_mem_address(vcpu, exit_qualification,
6725                                 vmx_instruction_info, &gva))
6726                         return 1;
6727                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6728                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
6729                         kvm_inject_page_fault(vcpu, &e);
6730                         return 1;
6731                 }
6732         }
6733
6734
6735         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6736         if (vmcs_field_readonly(field)) {
6737                 nested_vmx_failValid(vcpu,
6738                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6739                 skip_emulated_instruction(vcpu);
6740                 return 1;
6741         }
6742
6743         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
6744                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6745                 skip_emulated_instruction(vcpu);
6746                 return 1;
6747         }
6748
6749         nested_vmx_succeed(vcpu);
6750         skip_emulated_instruction(vcpu);
6751         return 1;
6752 }
6753
6754 /* Emulate the VMPTRLD instruction */
6755 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6756 {
6757         struct vcpu_vmx *vmx = to_vmx(vcpu);
6758         gpa_t vmptr;
6759         u32 exec_control;
6760
6761         if (!nested_vmx_check_permission(vcpu))
6762                 return 1;
6763
6764         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
6765                 return 1;
6766
6767         if (vmx->nested.current_vmptr != vmptr) {
6768                 struct vmcs12 *new_vmcs12;
6769                 struct page *page;
6770                 page = nested_get_page(vcpu, vmptr);
6771                 if (page == NULL) {
6772                         nested_vmx_failInvalid(vcpu);
6773                         skip_emulated_instruction(vcpu);
6774                         return 1;
6775                 }
6776                 new_vmcs12 = kmap(page);
6777                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6778                         kunmap(page);
6779                         nested_release_page_clean(page);
6780                         nested_vmx_failValid(vcpu,
6781                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6782                         skip_emulated_instruction(vcpu);
6783                         return 1;
6784                 }
6785
6786                 nested_release_vmcs12(vmx);
6787                 vmx->nested.current_vmptr = vmptr;
6788                 vmx->nested.current_vmcs12 = new_vmcs12;
6789                 vmx->nested.current_vmcs12_page = page;
6790                 if (enable_shadow_vmcs) {
6791                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6792                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6793                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6794                         vmcs_write64(VMCS_LINK_POINTER,
6795                                      __pa(vmx->nested.current_shadow_vmcs));
6796                         vmx->nested.sync_shadow_vmcs = true;
6797                 }
6798         }
6799
6800         nested_vmx_succeed(vcpu);
6801         skip_emulated_instruction(vcpu);
6802         return 1;
6803 }
6804
6805 /* Emulate the VMPTRST instruction */
6806 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6807 {
6808         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6809         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6810         gva_t vmcs_gva;
6811         struct x86_exception e;
6812
6813         if (!nested_vmx_check_permission(vcpu))
6814                 return 1;
6815
6816         if (get_vmx_mem_address(vcpu, exit_qualification,
6817                         vmx_instruction_info, &vmcs_gva))
6818                 return 1;
6819         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6820         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6821                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6822                                  sizeof(u64), &e)) {
6823                 kvm_inject_page_fault(vcpu, &e);
6824                 return 1;
6825         }
6826         nested_vmx_succeed(vcpu);
6827         skip_emulated_instruction(vcpu);
6828         return 1;
6829 }
6830
6831 /* Emulate the INVEPT instruction */
6832 static int handle_invept(struct kvm_vcpu *vcpu)
6833 {
6834         u32 vmx_instruction_info, types;
6835         unsigned long type;
6836         gva_t gva;
6837         struct x86_exception e;
6838         struct {
6839                 u64 eptp, gpa;
6840         } operand;
6841
6842         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6843             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6844                 kvm_queue_exception(vcpu, UD_VECTOR);
6845                 return 1;
6846         }
6847
6848         if (!nested_vmx_check_permission(vcpu))
6849                 return 1;
6850
6851         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6852                 kvm_queue_exception(vcpu, UD_VECTOR);
6853                 return 1;
6854         }
6855
6856         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6857         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
6858
6859         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6860
6861         if (!(types & (1UL << type))) {
6862                 nested_vmx_failValid(vcpu,
6863                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6864                 return 1;
6865         }
6866
6867         /* According to the Intel VMX instruction reference, the memory
6868          * operand is read even if it isn't needed (e.g., for type==global)
6869          */
6870         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6871                         vmx_instruction_info, &gva))
6872                 return 1;
6873         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6874                                 sizeof(operand), &e)) {
6875                 kvm_inject_page_fault(vcpu, &e);
6876                 return 1;
6877         }
6878
6879         switch (type) {
6880         case VMX_EPT_EXTENT_GLOBAL:
6881                 kvm_mmu_sync_roots(vcpu);
6882                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
6883                 nested_vmx_succeed(vcpu);
6884                 break;
6885         default:
6886                 /* Trap single context invalidation invept calls */
6887                 BUG_ON(1);
6888                 break;
6889         }
6890
6891         skip_emulated_instruction(vcpu);
6892         return 1;
6893 }
6894
6895 static int handle_invvpid(struct kvm_vcpu *vcpu)
6896 {
6897         kvm_queue_exception(vcpu, UD_VECTOR);
6898         return 1;
6899 }
6900
6901 /*
6902  * The exit handlers return 1 if the exit was handled fully and guest execution
6903  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6904  * to be done to userspace and return 0.
6905  */
6906 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6907         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6908         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6909         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6910         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6911         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6912         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6913         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6914         [EXIT_REASON_CPUID]                   = handle_cpuid,
6915         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6916         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6917         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6918         [EXIT_REASON_HLT]                     = handle_halt,
6919         [EXIT_REASON_INVD]                    = handle_invd,
6920         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6921         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6922         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6923         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6924         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6925         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6926         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6927         [EXIT_REASON_VMREAD]                  = handle_vmread,
6928         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6929         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6930         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6931         [EXIT_REASON_VMON]                    = handle_vmon,
6932         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6933         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6934         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6935         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6936         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6937         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6938         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6939         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6940         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6941         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6942         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6943         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
6944         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
6945         [EXIT_REASON_INVEPT]                  = handle_invept,
6946         [EXIT_REASON_INVVPID]                 = handle_invvpid,
6947 };
6948
6949 static const int kvm_vmx_max_exit_handlers =
6950         ARRAY_SIZE(kvm_vmx_exit_handlers);
6951
6952 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6953                                        struct vmcs12 *vmcs12)
6954 {
6955         unsigned long exit_qualification;
6956         gpa_t bitmap, last_bitmap;
6957         unsigned int port;
6958         int size;
6959         u8 b;
6960
6961         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6962                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6963
6964         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6965
6966         port = exit_qualification >> 16;
6967         size = (exit_qualification & 7) + 1;
6968
6969         last_bitmap = (gpa_t)-1;
6970         b = -1;
6971
6972         while (size > 0) {
6973                 if (port < 0x8000)
6974                         bitmap = vmcs12->io_bitmap_a;
6975                 else if (port < 0x10000)
6976                         bitmap = vmcs12->io_bitmap_b;
6977                 else
6978                         return 1;
6979                 bitmap += (port & 0x7fff) / 8;
6980
6981                 if (last_bitmap != bitmap)
6982                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6983                                 return 1;
6984                 if (b & (1 << (port & 7)))
6985                         return 1;
6986
6987                 port++;
6988                 size--;
6989                 last_bitmap = bitmap;
6990         }
6991
6992         return 0;
6993 }
6994
6995 /*
6996  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6997  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6998  * disinterest in the current event (read or write a specific MSR) by using an
6999  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7000  */
7001 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7002         struct vmcs12 *vmcs12, u32 exit_reason)
7003 {
7004         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7005         gpa_t bitmap;
7006
7007         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7008                 return 1;
7009
7010         /*
7011          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7012          * for the four combinations of read/write and low/high MSR numbers.
7013          * First we need to figure out which of the four to use:
7014          */
7015         bitmap = vmcs12->msr_bitmap;
7016         if (exit_reason == EXIT_REASON_MSR_WRITE)
7017                 bitmap += 2048;
7018         if (msr_index >= 0xc0000000) {
7019                 msr_index -= 0xc0000000;
7020                 bitmap += 1024;
7021         }
7022
7023         /* Then read the msr_index'th bit from this bitmap: */
7024         if (msr_index < 1024*8) {
7025                 unsigned char b;
7026                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7027                         return 1;
7028                 return 1 & (b >> (msr_index & 7));
7029         } else
7030                 return 1; /* let L1 handle the wrong parameter */
7031 }
7032
7033 /*
7034  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7035  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7036  * intercept (via guest_host_mask etc.) the current event.
7037  */
7038 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7039         struct vmcs12 *vmcs12)
7040 {
7041         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7042         int cr = exit_qualification & 15;
7043         int reg = (exit_qualification >> 8) & 15;
7044         unsigned long val = kvm_register_readl(vcpu, reg);
7045
7046         switch ((exit_qualification >> 4) & 3) {
7047         case 0: /* mov to cr */
7048                 switch (cr) {
7049                 case 0:
7050                         if (vmcs12->cr0_guest_host_mask &
7051                             (val ^ vmcs12->cr0_read_shadow))
7052                                 return 1;
7053                         break;
7054                 case 3:
7055                         if ((vmcs12->cr3_target_count >= 1 &&
7056                                         vmcs12->cr3_target_value0 == val) ||
7057                                 (vmcs12->cr3_target_count >= 2 &&
7058                                         vmcs12->cr3_target_value1 == val) ||
7059                                 (vmcs12->cr3_target_count >= 3 &&
7060                                         vmcs12->cr3_target_value2 == val) ||
7061                                 (vmcs12->cr3_target_count >= 4 &&
7062                                         vmcs12->cr3_target_value3 == val))
7063                                 return 0;
7064                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7065                                 return 1;
7066                         break;
7067                 case 4:
7068                         if (vmcs12->cr4_guest_host_mask &
7069                             (vmcs12->cr4_read_shadow ^ val))
7070                                 return 1;
7071                         break;
7072                 case 8:
7073                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7074                                 return 1;
7075                         break;
7076                 }
7077                 break;
7078         case 2: /* clts */
7079                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7080                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7081                         return 1;
7082                 break;
7083         case 1: /* mov from cr */
7084                 switch (cr) {
7085                 case 3:
7086                         if (vmcs12->cpu_based_vm_exec_control &
7087                             CPU_BASED_CR3_STORE_EXITING)
7088                                 return 1;
7089                         break;
7090                 case 8:
7091                         if (vmcs12->cpu_based_vm_exec_control &
7092                             CPU_BASED_CR8_STORE_EXITING)
7093                                 return 1;
7094                         break;
7095                 }
7096                 break;
7097         case 3: /* lmsw */
7098                 /*
7099                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7100                  * cr0. Other attempted changes are ignored, with no exit.
7101                  */
7102                 if (vmcs12->cr0_guest_host_mask & 0xe &
7103                     (val ^ vmcs12->cr0_read_shadow))
7104                         return 1;
7105                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7106                     !(vmcs12->cr0_read_shadow & 0x1) &&
7107                     (val & 0x1))
7108                         return 1;
7109                 break;
7110         }
7111         return 0;
7112 }
7113
7114 /*
7115  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7116  * should handle it ourselves in L0 (and then continue L2). Only call this
7117  * when in is_guest_mode (L2).
7118  */
7119 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7120 {
7121         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7122         struct vcpu_vmx *vmx = to_vmx(vcpu);
7123         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7124         u32 exit_reason = vmx->exit_reason;
7125
7126         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7127                                 vmcs_readl(EXIT_QUALIFICATION),
7128                                 vmx->idt_vectoring_info,
7129                                 intr_info,
7130                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7131                                 KVM_ISA_VMX);
7132
7133         if (vmx->nested.nested_run_pending)
7134                 return 0;
7135
7136         if (unlikely(vmx->fail)) {
7137                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7138                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7139                 return 1;
7140         }
7141
7142         switch (exit_reason) {
7143         case EXIT_REASON_EXCEPTION_NMI:
7144                 if (!is_exception(intr_info))
7145                         return 0;
7146                 else if (is_page_fault(intr_info))
7147                         return enable_ept;
7148                 else if (is_no_device(intr_info) &&
7149                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7150                         return 0;
7151                 return vmcs12->exception_bitmap &
7152                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7153         case EXIT_REASON_EXTERNAL_INTERRUPT:
7154                 return 0;
7155         case EXIT_REASON_TRIPLE_FAULT:
7156                 return 1;
7157         case EXIT_REASON_PENDING_INTERRUPT:
7158                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7159         case EXIT_REASON_NMI_WINDOW:
7160                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7161         case EXIT_REASON_TASK_SWITCH:
7162                 return 1;
7163         case EXIT_REASON_CPUID:
7164                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7165                         return 0;
7166                 return 1;
7167         case EXIT_REASON_HLT:
7168                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7169         case EXIT_REASON_INVD:
7170                 return 1;
7171         case EXIT_REASON_INVLPG:
7172                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7173         case EXIT_REASON_RDPMC:
7174                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7175         case EXIT_REASON_RDTSC:
7176                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7177         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7178         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7179         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7180         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7181         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7182         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7183                 /*
7184                  * VMX instructions trap unconditionally. This allows L1 to
7185                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7186                  */
7187                 return 1;
7188         case EXIT_REASON_CR_ACCESS:
7189                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7190         case EXIT_REASON_DR_ACCESS:
7191                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7192         case EXIT_REASON_IO_INSTRUCTION:
7193                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7194         case EXIT_REASON_MSR_READ:
7195         case EXIT_REASON_MSR_WRITE:
7196                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7197         case EXIT_REASON_INVALID_STATE:
7198                 return 1;
7199         case EXIT_REASON_MWAIT_INSTRUCTION:
7200                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7201         case EXIT_REASON_MONITOR_INSTRUCTION:
7202                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7203         case EXIT_REASON_PAUSE_INSTRUCTION:
7204                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7205                         nested_cpu_has2(vmcs12,
7206                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7207         case EXIT_REASON_MCE_DURING_VMENTRY:
7208                 return 0;
7209         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7210                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7211         case EXIT_REASON_APIC_ACCESS:
7212                 return nested_cpu_has2(vmcs12,
7213                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7214         case EXIT_REASON_EPT_VIOLATION:
7215                 /*
7216                  * L0 always deals with the EPT violation. If nested EPT is
7217                  * used, and the nested mmu code discovers that the address is
7218                  * missing in the guest EPT table (EPT12), the EPT violation
7219                  * will be injected with nested_ept_inject_page_fault()
7220                  */
7221                 return 0;
7222         case EXIT_REASON_EPT_MISCONFIG:
7223                 /*
7224                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7225                  * table (shadow on EPT) or a merged EPT table that L0 built
7226                  * (EPT on EPT). So any problems with the structure of the
7227                  * table is L0's fault.
7228                  */
7229                 return 0;
7230         case EXIT_REASON_WBINVD:
7231                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7232         case EXIT_REASON_XSETBV:
7233                 return 1;
7234         default:
7235                 return 1;
7236         }
7237 }
7238
7239 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7240 {
7241         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7242         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7243 }
7244
7245 /*
7246  * The guest has exited.  See if we can fix it or if we need userspace
7247  * assistance.
7248  */
7249 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7250 {
7251         struct vcpu_vmx *vmx = to_vmx(vcpu);
7252         u32 exit_reason = vmx->exit_reason;
7253         u32 vectoring_info = vmx->idt_vectoring_info;
7254
7255         /* If guest state is invalid, start emulating */
7256         if (vmx->emulation_required)
7257                 return handle_invalid_guest_state(vcpu);
7258
7259         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7260                 nested_vmx_vmexit(vcpu, exit_reason,
7261                                   vmcs_read32(VM_EXIT_INTR_INFO),
7262                                   vmcs_readl(EXIT_QUALIFICATION));
7263                 return 1;
7264         }
7265
7266         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7267                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7268                 vcpu->run->fail_entry.hardware_entry_failure_reason
7269                         = exit_reason;
7270                 return 0;
7271         }
7272
7273         if (unlikely(vmx->fail)) {
7274                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7275                 vcpu->run->fail_entry.hardware_entry_failure_reason
7276                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7277                 return 0;
7278         }
7279
7280         /*
7281          * Note:
7282          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7283          * delivery event since it indicates guest is accessing MMIO.
7284          * The vm-exit can be triggered again after return to guest that
7285          * will cause infinite loop.
7286          */
7287         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7288                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7289                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7290                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7291                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7292                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7293                 vcpu->run->internal.ndata = 2;
7294                 vcpu->run->internal.data[0] = vectoring_info;
7295                 vcpu->run->internal.data[1] = exit_reason;
7296                 return 0;
7297         }
7298
7299         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7300             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7301                                         get_vmcs12(vcpu))))) {
7302                 if (vmx_interrupt_allowed(vcpu)) {
7303                         vmx->soft_vnmi_blocked = 0;
7304                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7305                            vcpu->arch.nmi_pending) {
7306                         /*
7307                          * This CPU don't support us in finding the end of an
7308                          * NMI-blocked window if the guest runs with IRQs
7309                          * disabled. So we pull the trigger after 1 s of
7310                          * futile waiting, but inform the user about this.
7311                          */
7312                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7313                                "state on VCPU %d after 1 s timeout\n",
7314                                __func__, vcpu->vcpu_id);
7315                         vmx->soft_vnmi_blocked = 0;
7316                 }
7317         }
7318
7319         if (exit_reason < kvm_vmx_max_exit_handlers
7320             && kvm_vmx_exit_handlers[exit_reason])
7321                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7322         else {
7323                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7324                 kvm_queue_exception(vcpu, UD_VECTOR);
7325                 return 1;
7326         }
7327 }
7328
7329 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7330 {
7331         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7332
7333         if (is_guest_mode(vcpu) &&
7334                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7335                 return;
7336
7337         if (irr == -1 || tpr < irr) {
7338                 vmcs_write32(TPR_THRESHOLD, 0);
7339                 return;
7340         }
7341
7342         vmcs_write32(TPR_THRESHOLD, irr);
7343 }
7344
7345 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7346 {
7347         u32 sec_exec_control;
7348
7349         /*
7350          * There is not point to enable virtualize x2apic without enable
7351          * apicv
7352          */
7353         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7354                                 !vmx_vm_has_apicv(vcpu->kvm))
7355                 return;
7356
7357         if (!vm_need_tpr_shadow(vcpu->kvm))
7358                 return;
7359
7360         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7361
7362         if (set) {
7363                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7364                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7365         } else {
7366                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7367                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7368         }
7369         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7370
7371         vmx_set_msr_bitmap(vcpu);
7372 }
7373
7374 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7375 {
7376         struct vcpu_vmx *vmx = to_vmx(vcpu);
7377
7378         /*
7379          * Currently we do not handle the nested case where L2 has an
7380          * APIC access page of its own; that page is still pinned.
7381          * Hence, we skip the case where the VCPU is in guest mode _and_
7382          * L1 prepared an APIC access page for L2.
7383          *
7384          * For the case where L1 and L2 share the same APIC access page
7385          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7386          * in the vmcs12), this function will only update either the vmcs01
7387          * or the vmcs02.  If the former, the vmcs02 will be updated by
7388          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7389          * the next L2->L1 exit.
7390          */
7391         if (!is_guest_mode(vcpu) ||
7392             !nested_cpu_has2(vmx->nested.current_vmcs12,
7393                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7394                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7395 }
7396
7397 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7398 {
7399         u16 status;
7400         u8 old;
7401
7402         if (!vmx_vm_has_apicv(kvm))
7403                 return;
7404
7405         if (isr == -1)
7406                 isr = 0;
7407
7408         status = vmcs_read16(GUEST_INTR_STATUS);
7409         old = status >> 8;
7410         if (isr != old) {
7411                 status &= 0xff;
7412                 status |= isr << 8;
7413                 vmcs_write16(GUEST_INTR_STATUS, status);
7414         }
7415 }
7416
7417 static void vmx_set_rvi(int vector)
7418 {
7419         u16 status;
7420         u8 old;
7421
7422         if (vector == -1)
7423                 vector = 0;
7424
7425         status = vmcs_read16(GUEST_INTR_STATUS);
7426         old = (u8)status & 0xff;
7427         if ((u8)vector != old) {
7428                 status &= ~0xff;
7429                 status |= (u8)vector;
7430                 vmcs_write16(GUEST_INTR_STATUS, status);
7431         }
7432 }
7433
7434 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7435 {
7436         if (!is_guest_mode(vcpu)) {
7437                 vmx_set_rvi(max_irr);
7438                 return;
7439         }
7440
7441         if (max_irr == -1)
7442                 return;
7443
7444         /*
7445          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7446          * handles it.
7447          */
7448         if (nested_exit_on_intr(vcpu))
7449                 return;
7450
7451         /*
7452          * Else, fall back to pre-APICv interrupt injection since L2
7453          * is run without virtual interrupt delivery.
7454          */
7455         if (!kvm_event_needs_reinjection(vcpu) &&
7456             vmx_interrupt_allowed(vcpu)) {
7457                 kvm_queue_interrupt(vcpu, max_irr, false);
7458                 vmx_inject_irq(vcpu);
7459         }
7460 }
7461
7462 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7463 {
7464         if (!vmx_vm_has_apicv(vcpu->kvm))
7465                 return;
7466
7467         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7468         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7469         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7470         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7471 }
7472
7473 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7474 {
7475         u32 exit_intr_info;
7476
7477         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7478               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7479                 return;
7480
7481         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7482         exit_intr_info = vmx->exit_intr_info;
7483
7484         /* Handle machine checks before interrupts are enabled */
7485         if (is_machine_check(exit_intr_info))
7486                 kvm_machine_check();
7487
7488         /* We need to handle NMIs before interrupts are enabled */
7489         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7490             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7491                 kvm_before_handle_nmi(&vmx->vcpu);
7492                 asm("int $2");
7493                 kvm_after_handle_nmi(&vmx->vcpu);
7494         }
7495 }
7496
7497 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7498 {
7499         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7500
7501         /*
7502          * If external interrupt exists, IF bit is set in rflags/eflags on the
7503          * interrupt stack frame, and interrupt will be enabled on a return
7504          * from interrupt handler.
7505          */
7506         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7507                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7508                 unsigned int vector;
7509                 unsigned long entry;
7510                 gate_desc *desc;
7511                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7512 #ifdef CONFIG_X86_64
7513                 unsigned long tmp;
7514 #endif
7515
7516                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7517                 desc = (gate_desc *)vmx->host_idt_base + vector;
7518                 entry = gate_offset(*desc);
7519                 asm volatile(
7520 #ifdef CONFIG_X86_64
7521                         "mov %%" _ASM_SP ", %[sp]\n\t"
7522                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7523                         "push $%c[ss]\n\t"
7524                         "push %[sp]\n\t"
7525 #endif
7526                         "pushf\n\t"
7527                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7528                         __ASM_SIZE(push) " $%c[cs]\n\t"
7529                         "call *%[entry]\n\t"
7530                         :
7531 #ifdef CONFIG_X86_64
7532                         [sp]"=&r"(tmp)
7533 #endif
7534                         :
7535                         [entry]"r"(entry),
7536                         [ss]"i"(__KERNEL_DS),
7537                         [cs]"i"(__KERNEL_CS)
7538                         );
7539         } else
7540                 local_irq_enable();
7541 }
7542
7543 static bool vmx_mpx_supported(void)
7544 {
7545         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7546                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7547 }
7548
7549 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7550 {
7551         u32 exit_intr_info;
7552         bool unblock_nmi;
7553         u8 vector;
7554         bool idtv_info_valid;
7555
7556         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7557
7558         if (cpu_has_virtual_nmis()) {
7559                 if (vmx->nmi_known_unmasked)
7560                         return;
7561                 /*
7562                  * Can't use vmx->exit_intr_info since we're not sure what
7563                  * the exit reason is.
7564                  */
7565                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7566                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7567                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7568                 /*
7569                  * SDM 3: 27.7.1.2 (September 2008)
7570                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7571                  * a guest IRET fault.
7572                  * SDM 3: 23.2.2 (September 2008)
7573                  * Bit 12 is undefined in any of the following cases:
7574                  *  If the VM exit sets the valid bit in the IDT-vectoring
7575                  *   information field.
7576                  *  If the VM exit is due to a double fault.
7577                  */
7578                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7579                     vector != DF_VECTOR && !idtv_info_valid)
7580                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7581                                       GUEST_INTR_STATE_NMI);
7582                 else
7583                         vmx->nmi_known_unmasked =
7584                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7585                                   & GUEST_INTR_STATE_NMI);
7586         } else if (unlikely(vmx->soft_vnmi_blocked))
7587                 vmx->vnmi_blocked_time +=
7588                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7589 }
7590
7591 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7592                                       u32 idt_vectoring_info,
7593                                       int instr_len_field,
7594                                       int error_code_field)
7595 {
7596         u8 vector;
7597         int type;
7598         bool idtv_info_valid;
7599
7600         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7601
7602         vcpu->arch.nmi_injected = false;
7603         kvm_clear_exception_queue(vcpu);
7604         kvm_clear_interrupt_queue(vcpu);
7605
7606         if (!idtv_info_valid)
7607                 return;
7608
7609         kvm_make_request(KVM_REQ_EVENT, vcpu);
7610
7611         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7612         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7613
7614         switch (type) {
7615         case INTR_TYPE_NMI_INTR:
7616                 vcpu->arch.nmi_injected = true;
7617                 /*
7618                  * SDM 3: 27.7.1.2 (September 2008)
7619                  * Clear bit "block by NMI" before VM entry if a NMI
7620                  * delivery faulted.
7621                  */
7622                 vmx_set_nmi_mask(vcpu, false);
7623                 break;
7624         case INTR_TYPE_SOFT_EXCEPTION:
7625                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7626                 /* fall through */
7627         case INTR_TYPE_HARD_EXCEPTION:
7628                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7629                         u32 err = vmcs_read32(error_code_field);
7630                         kvm_requeue_exception_e(vcpu, vector, err);
7631                 } else
7632                         kvm_requeue_exception(vcpu, vector);
7633                 break;
7634         case INTR_TYPE_SOFT_INTR:
7635                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7636                 /* fall through */
7637         case INTR_TYPE_EXT_INTR:
7638                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7639                 break;
7640         default:
7641                 break;
7642         }
7643 }
7644
7645 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7646 {
7647         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7648                                   VM_EXIT_INSTRUCTION_LEN,
7649                                   IDT_VECTORING_ERROR_CODE);
7650 }
7651
7652 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7653 {
7654         __vmx_complete_interrupts(vcpu,
7655                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7656                                   VM_ENTRY_INSTRUCTION_LEN,
7657                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7658
7659         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7660 }
7661
7662 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7663 {
7664         int i, nr_msrs;
7665         struct perf_guest_switch_msr *msrs;
7666
7667         msrs = perf_guest_get_msrs(&nr_msrs);
7668
7669         if (!msrs)
7670                 return;
7671
7672         for (i = 0; i < nr_msrs; i++)
7673                 if (msrs[i].host == msrs[i].guest)
7674                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7675                 else
7676                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7677                                         msrs[i].host);
7678 }
7679
7680 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7681 {
7682         struct vcpu_vmx *vmx = to_vmx(vcpu);
7683         unsigned long debugctlmsr, cr4;
7684
7685         /* Record the guest's net vcpu time for enforced NMI injections. */
7686         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7687                 vmx->entry_time = ktime_get();
7688
7689         /* Don't enter VMX if guest state is invalid, let the exit handler
7690            start emulation until we arrive back to a valid state */
7691         if (vmx->emulation_required)
7692                 return;
7693
7694         if (vmx->ple_window_dirty) {
7695                 vmx->ple_window_dirty = false;
7696                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7697         }
7698
7699         if (vmx->nested.sync_shadow_vmcs) {
7700                 copy_vmcs12_to_shadow(vmx);
7701                 vmx->nested.sync_shadow_vmcs = false;
7702         }
7703
7704         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7705                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7706         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7707                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7708
7709         cr4 = read_cr4();
7710         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7711                 vmcs_writel(HOST_CR4, cr4);
7712                 vmx->host_state.vmcs_host_cr4 = cr4;
7713         }
7714
7715         /* When single-stepping over STI and MOV SS, we must clear the
7716          * corresponding interruptibility bits in the guest state. Otherwise
7717          * vmentry fails as it then expects bit 14 (BS) in pending debug
7718          * exceptions being set, but that's not correct for the guest debugging
7719          * case. */
7720         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7721                 vmx_set_interrupt_shadow(vcpu, 0);
7722
7723         atomic_switch_perf_msrs(vmx);
7724         debugctlmsr = get_debugctlmsr();
7725
7726         vmx->__launched = vmx->loaded_vmcs->launched;
7727         asm(
7728                 /* Store host registers */
7729                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7730                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7731                 "push %%" _ASM_CX " \n\t"
7732                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7733                 "je 1f \n\t"
7734                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7735                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7736                 "1: \n\t"
7737                 /* Reload cr2 if changed */
7738                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7739                 "mov %%cr2, %%" _ASM_DX " \n\t"
7740                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7741                 "je 2f \n\t"
7742                 "mov %%" _ASM_AX", %%cr2 \n\t"
7743                 "2: \n\t"
7744                 /* Check if vmlaunch of vmresume is needed */
7745                 "cmpl $0, %c[launched](%0) \n\t"
7746                 /* Load guest registers.  Don't clobber flags. */
7747                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7748                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7749                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7750                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7751                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7752                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7753 #ifdef CONFIG_X86_64
7754                 "mov %c[r8](%0),  %%r8  \n\t"
7755                 "mov %c[r9](%0),  %%r9  \n\t"
7756                 "mov %c[r10](%0), %%r10 \n\t"
7757                 "mov %c[r11](%0), %%r11 \n\t"
7758                 "mov %c[r12](%0), %%r12 \n\t"
7759                 "mov %c[r13](%0), %%r13 \n\t"
7760                 "mov %c[r14](%0), %%r14 \n\t"
7761                 "mov %c[r15](%0), %%r15 \n\t"
7762 #endif
7763                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7764
7765                 /* Enter guest mode */
7766                 "jne 1f \n\t"
7767                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7768                 "jmp 2f \n\t"
7769                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7770                 "2: "
7771                 /* Save guest registers, load host registers, keep flags */
7772                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7773                 "pop %0 \n\t"
7774                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7775                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7776                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7777                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7778                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7779                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7780                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7781 #ifdef CONFIG_X86_64
7782                 "mov %%r8,  %c[r8](%0) \n\t"
7783                 "mov %%r9,  %c[r9](%0) \n\t"
7784                 "mov %%r10, %c[r10](%0) \n\t"
7785                 "mov %%r11, %c[r11](%0) \n\t"
7786                 "mov %%r12, %c[r12](%0) \n\t"
7787                 "mov %%r13, %c[r13](%0) \n\t"
7788                 "mov %%r14, %c[r14](%0) \n\t"
7789                 "mov %%r15, %c[r15](%0) \n\t"
7790 #endif
7791                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7792                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7793
7794                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7795                 "setbe %c[fail](%0) \n\t"
7796                 ".pushsection .rodata \n\t"
7797                 ".global vmx_return \n\t"
7798                 "vmx_return: " _ASM_PTR " 2b \n\t"
7799                 ".popsection"
7800               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7801                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7802                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7803                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7804                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7805                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7806                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7807                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7808                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7809                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7810                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7811 #ifdef CONFIG_X86_64
7812                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7813                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7814                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7815                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7816                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7817                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7818                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7819                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7820 #endif
7821                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7822                 [wordsize]"i"(sizeof(ulong))
7823               : "cc", "memory"
7824 #ifdef CONFIG_X86_64
7825                 , "rax", "rbx", "rdi", "rsi"
7826                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7827 #else
7828                 , "eax", "ebx", "edi", "esi"
7829 #endif
7830               );
7831
7832         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7833         if (debugctlmsr)
7834                 update_debugctlmsr(debugctlmsr);
7835
7836 #ifndef CONFIG_X86_64
7837         /*
7838          * The sysexit path does not restore ds/es, so we must set them to
7839          * a reasonable value ourselves.
7840          *
7841          * We can't defer this to vmx_load_host_state() since that function
7842          * may be executed in interrupt context, which saves and restore segments
7843          * around it, nullifying its effect.
7844          */
7845         loadsegment(ds, __USER_DS);
7846         loadsegment(es, __USER_DS);
7847 #endif
7848
7849         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7850                                   | (1 << VCPU_EXREG_RFLAGS)
7851                                   | (1 << VCPU_EXREG_PDPTR)
7852                                   | (1 << VCPU_EXREG_SEGMENTS)
7853                                   | (1 << VCPU_EXREG_CR3));
7854         vcpu->arch.regs_dirty = 0;
7855
7856         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7857
7858         vmx->loaded_vmcs->launched = 1;
7859
7860         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7861         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7862
7863         /*
7864          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7865          * we did not inject a still-pending event to L1 now because of
7866          * nested_run_pending, we need to re-enable this bit.
7867          */
7868         if (vmx->nested.nested_run_pending)
7869                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7870
7871         vmx->nested.nested_run_pending = 0;
7872
7873         vmx_complete_atomic_exit(vmx);
7874         vmx_recover_nmi_blocking(vmx);
7875         vmx_complete_interrupts(vmx);
7876 }
7877
7878 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7879 {
7880         struct vcpu_vmx *vmx = to_vmx(vcpu);
7881         int cpu;
7882
7883         if (vmx->loaded_vmcs == &vmx->vmcs01)
7884                 return;
7885
7886         cpu = get_cpu();
7887         vmx->loaded_vmcs = &vmx->vmcs01;
7888         vmx_vcpu_put(vcpu);
7889         vmx_vcpu_load(vcpu, cpu);
7890         vcpu->cpu = cpu;
7891         put_cpu();
7892 }
7893
7894 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7895 {
7896         struct vcpu_vmx *vmx = to_vmx(vcpu);
7897
7898         free_vpid(vmx);
7899         leave_guest_mode(vcpu);
7900         vmx_load_vmcs01(vcpu);
7901         free_nested(vmx);
7902         free_loaded_vmcs(vmx->loaded_vmcs);
7903         kfree(vmx->guest_msrs);
7904         kvm_vcpu_uninit(vcpu);
7905         kmem_cache_free(kvm_vcpu_cache, vmx);
7906 }
7907
7908 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7909 {
7910         int err;
7911         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7912         int cpu;
7913
7914         if (!vmx)
7915                 return ERR_PTR(-ENOMEM);
7916
7917         allocate_vpid(vmx);
7918
7919         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7920         if (err)
7921                 goto free_vcpu;
7922
7923         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7924         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7925                      > PAGE_SIZE);
7926
7927         err = -ENOMEM;
7928         if (!vmx->guest_msrs) {
7929                 goto uninit_vcpu;
7930         }
7931
7932         vmx->loaded_vmcs = &vmx->vmcs01;
7933         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7934         if (!vmx->loaded_vmcs->vmcs)
7935                 goto free_msrs;
7936         if (!vmm_exclusive)
7937                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7938         loaded_vmcs_init(vmx->loaded_vmcs);
7939         if (!vmm_exclusive)
7940                 kvm_cpu_vmxoff();
7941
7942         cpu = get_cpu();
7943         vmx_vcpu_load(&vmx->vcpu, cpu);
7944         vmx->vcpu.cpu = cpu;
7945         err = vmx_vcpu_setup(vmx);
7946         vmx_vcpu_put(&vmx->vcpu);
7947         put_cpu();
7948         if (err)
7949                 goto free_vmcs;
7950         if (vm_need_virtualize_apic_accesses(kvm)) {
7951                 err = alloc_apic_access_page(kvm);
7952                 if (err)
7953                         goto free_vmcs;
7954         }
7955
7956         if (enable_ept) {
7957                 if (!kvm->arch.ept_identity_map_addr)
7958                         kvm->arch.ept_identity_map_addr =
7959                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7960                 err = init_rmode_identity_map(kvm);
7961                 if (err)
7962                         goto free_vmcs;
7963         }
7964
7965         vmx->nested.current_vmptr = -1ull;
7966         vmx->nested.current_vmcs12 = NULL;
7967
7968         return &vmx->vcpu;
7969
7970 free_vmcs:
7971         free_loaded_vmcs(vmx->loaded_vmcs);
7972 free_msrs:
7973         kfree(vmx->guest_msrs);
7974 uninit_vcpu:
7975         kvm_vcpu_uninit(&vmx->vcpu);
7976 free_vcpu:
7977         free_vpid(vmx);
7978         kmem_cache_free(kvm_vcpu_cache, vmx);
7979         return ERR_PTR(err);
7980 }
7981
7982 static void __init vmx_check_processor_compat(void *rtn)
7983 {
7984         struct vmcs_config vmcs_conf;
7985
7986         *(int *)rtn = 0;
7987         if (setup_vmcs_config(&vmcs_conf) < 0)
7988                 *(int *)rtn = -EIO;
7989         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7990                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7991                                 smp_processor_id());
7992                 *(int *)rtn = -EIO;
7993         }
7994 }
7995
7996 static int get_ept_level(void)
7997 {
7998         return VMX_EPT_DEFAULT_GAW + 1;
7999 }
8000
8001 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8002 {
8003         u64 ret;
8004
8005         /* For VT-d and EPT combination
8006          * 1. MMIO: always map as UC
8007          * 2. EPT with VT-d:
8008          *   a. VT-d without snooping control feature: can't guarantee the
8009          *      result, try to trust guest.
8010          *   b. VT-d with snooping control feature: snooping control feature of
8011          *      VT-d engine can guarantee the cache correctness. Just set it
8012          *      to WB to keep consistent with host. So the same as item 3.
8013          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8014          *    consistent with host MTRR
8015          */
8016         if (is_mmio)
8017                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8018         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8019                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8020                       VMX_EPT_MT_EPTE_SHIFT;
8021         else
8022                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8023                         | VMX_EPT_IPAT_BIT;
8024
8025         return ret;
8026 }
8027
8028 static int vmx_get_lpage_level(void)
8029 {
8030         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8031                 return PT_DIRECTORY_LEVEL;
8032         else
8033                 /* For shadow and EPT supported 1GB page */
8034                 return PT_PDPE_LEVEL;
8035 }
8036
8037 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8038 {
8039         struct kvm_cpuid_entry2 *best;
8040         struct vcpu_vmx *vmx = to_vmx(vcpu);
8041         u32 exec_control;
8042
8043         vmx->rdtscp_enabled = false;
8044         if (vmx_rdtscp_supported()) {
8045                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8046                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8047                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8048                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8049                                 vmx->rdtscp_enabled = true;
8050                         else {
8051                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8052                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8053                                                 exec_control);
8054                         }
8055                 }
8056         }
8057
8058         /* Exposing INVPCID only when PCID is exposed */
8059         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8060         if (vmx_invpcid_supported() &&
8061             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8062             guest_cpuid_has_pcid(vcpu)) {
8063                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8064                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8065                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8066                              exec_control);
8067         } else {
8068                 if (cpu_has_secondary_exec_ctrls()) {
8069                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8070                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8071                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8072                                      exec_control);
8073                 }
8074                 if (best)
8075                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8076         }
8077 }
8078
8079 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8080 {
8081         if (func == 1 && nested)
8082                 entry->ecx |= bit(X86_FEATURE_VMX);
8083 }
8084
8085 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8086                 struct x86_exception *fault)
8087 {
8088         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8089         u32 exit_reason;
8090
8091         if (fault->error_code & PFERR_RSVD_MASK)
8092                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8093         else
8094                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8095         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8096         vmcs12->guest_physical_address = fault->address;
8097 }
8098
8099 /* Callbacks for nested_ept_init_mmu_context: */
8100
8101 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8102 {
8103         /* return the page table to be shadowed - in our case, EPT12 */
8104         return get_vmcs12(vcpu)->ept_pointer;
8105 }
8106
8107 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8108 {
8109         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
8110                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8111
8112         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8113         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8114         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8115
8116         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8117 }
8118
8119 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8120 {
8121         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8122 }
8123
8124 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8125                 struct x86_exception *fault)
8126 {
8127         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8128
8129         WARN_ON(!is_guest_mode(vcpu));
8130
8131         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8132         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
8133                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8134                                   vmcs_read32(VM_EXIT_INTR_INFO),
8135                                   vmcs_readl(EXIT_QUALIFICATION));
8136         else
8137                 kvm_inject_page_fault(vcpu, fault);
8138 }
8139
8140 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8141                                         struct vmcs12 *vmcs12)
8142 {
8143         struct vcpu_vmx *vmx = to_vmx(vcpu);
8144
8145         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8146                 /* TODO: Also verify bits beyond physical address width are 0 */
8147                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
8148                         return false;
8149
8150                 /*
8151                  * Translate L1 physical address to host physical
8152                  * address for vmcs02. Keep the page pinned, so this
8153                  * physical address remains valid. We keep a reference
8154                  * to it so we can release it later.
8155                  */
8156                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8157                         nested_release_page(vmx->nested.apic_access_page);
8158                 vmx->nested.apic_access_page =
8159                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8160         }
8161
8162         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8163                 /* TODO: Also verify bits beyond physical address width are 0 */
8164                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8165                         return false;
8166
8167                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8168                         nested_release_page(vmx->nested.virtual_apic_page);
8169                 vmx->nested.virtual_apic_page =
8170                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8171
8172                 /*
8173                  * Failing the vm entry is _not_ what the processor does
8174                  * but it's basically the only possibility we have.
8175                  * We could still enter the guest if CR8 load exits are
8176                  * enabled, CR8 store exits are enabled, and virtualize APIC
8177                  * access is disabled; in this case the processor would never
8178                  * use the TPR shadow and we could simply clear the bit from
8179                  * the execution control.  But such a configuration is useless,
8180                  * so let's keep the code simple.
8181                  */
8182                 if (!vmx->nested.virtual_apic_page)
8183                         return false;
8184         }
8185
8186         return true;
8187 }
8188
8189 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8190 {
8191         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8192         struct vcpu_vmx *vmx = to_vmx(vcpu);
8193
8194         if (vcpu->arch.virtual_tsc_khz == 0)
8195                 return;
8196
8197         /* Make sure short timeouts reliably trigger an immediate vmexit.
8198          * hrtimer_start does not guarantee this. */
8199         if (preemption_timeout <= 1) {
8200                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8201                 return;
8202         }
8203
8204         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8205         preemption_timeout *= 1000000;
8206         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8207         hrtimer_start(&vmx->nested.preemption_timer,
8208                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8209 }
8210
8211 /*
8212  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8213  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8214  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
8215  * guest in a way that will both be appropriate to L1's requests, and our
8216  * needs. In addition to modifying the active vmcs (which is vmcs02), this
8217  * function also has additional necessary side-effects, like setting various
8218  * vcpu->arch fields.
8219  */
8220 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8221 {
8222         struct vcpu_vmx *vmx = to_vmx(vcpu);
8223         u32 exec_control;
8224
8225         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8226         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8227         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8228         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8229         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8230         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8231         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8232         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8233         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8234         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8235         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8236         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8237         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8238         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8239         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8240         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8241         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8242         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8243         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8244         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8245         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8246         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8247         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8248         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8249         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8250         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8251         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8252         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8253         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8254         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8255         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8256         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8257         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8258         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8259         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8260         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8261
8262         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8263                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8264                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8265         } else {
8266                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8267                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8268         }
8269         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8270                 vmcs12->vm_entry_intr_info_field);
8271         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8272                 vmcs12->vm_entry_exception_error_code);
8273         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8274                 vmcs12->vm_entry_instruction_len);
8275         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8276                 vmcs12->guest_interruptibility_info);
8277         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
8278         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
8279         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8280                 vmcs12->guest_pending_dbg_exceptions);
8281         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8282         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8283
8284         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8285
8286         exec_control = vmcs12->pin_based_vm_exec_control;
8287         exec_control |= vmcs_config.pin_based_exec_ctrl;
8288         exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8289                           PIN_BASED_POSTED_INTR);
8290         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
8291
8292         vmx->nested.preemption_timer_expired = false;
8293         if (nested_cpu_has_preemption_timer(vmcs12))
8294                 vmx_start_preemption_timer(vcpu);
8295
8296         /*
8297          * Whether page-faults are trapped is determined by a combination of
8298          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8299          * If enable_ept, L0 doesn't care about page faults and we should
8300          * set all of these to L1's desires. However, if !enable_ept, L0 does
8301          * care about (at least some) page faults, and because it is not easy
8302          * (if at all possible?) to merge L0 and L1's desires, we simply ask
8303          * to exit on each and every L2 page fault. This is done by setting
8304          * MASK=MATCH=0 and (see below) EB.PF=1.
8305          * Note that below we don't need special code to set EB.PF beyond the
8306          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8307          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8308          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8309          *
8310          * A problem with this approach (when !enable_ept) is that L1 may be
8311          * injected with more page faults than it asked for. This could have
8312          * caused problems, but in practice existing hypervisors don't care.
8313          * To fix this, we will need to emulate the PFEC checking (on the L1
8314          * page tables), using walk_addr(), when injecting PFs to L1.
8315          */
8316         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8317                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8318         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8319                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8320
8321         if (cpu_has_secondary_exec_ctrls()) {
8322                 exec_control = vmx_secondary_exec_control(vmx);
8323                 if (!vmx->rdtscp_enabled)
8324                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
8325                 /* Take the following fields only from vmcs12 */
8326                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8327                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8328                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
8329                 if (nested_cpu_has(vmcs12,
8330                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8331                         exec_control |= vmcs12->secondary_vm_exec_control;
8332
8333                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
8334                         /*
8335                          * If translation failed, no matter: This feature asks
8336                          * to exit when accessing the given address, and if it
8337                          * can never be accessed, this feature won't do
8338                          * anything anyway.
8339                          */
8340                         if (!vmx->nested.apic_access_page)
8341                                 exec_control &=
8342                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8343                         else
8344                                 vmcs_write64(APIC_ACCESS_ADDR,
8345                                   page_to_phys(vmx->nested.apic_access_page));
8346                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8347                         exec_control |=
8348                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8349                         kvm_vcpu_reload_apic_access_page(vcpu);
8350                 }
8351
8352                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8353         }
8354
8355
8356         /*
8357          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8358          * Some constant fields are set here by vmx_set_constant_host_state().
8359          * Other fields are different per CPU, and will be set later when
8360          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8361          */
8362         vmx_set_constant_host_state(vmx);
8363
8364         /*
8365          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8366          * entry, but only if the current (host) sp changed from the value
8367          * we wrote last (vmx->host_rsp). This cache is no longer relevant
8368          * if we switch vmcs, and rather than hold a separate cache per vmcs,
8369          * here we just force the write to happen on entry.
8370          */
8371         vmx->host_rsp = 0;
8372
8373         exec_control = vmx_exec_control(vmx); /* L0's desires */
8374         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8375         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8376         exec_control &= ~CPU_BASED_TPR_SHADOW;
8377         exec_control |= vmcs12->cpu_based_vm_exec_control;
8378
8379         if (exec_control & CPU_BASED_TPR_SHADOW) {
8380                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8381                                 page_to_phys(vmx->nested.virtual_apic_page));
8382                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8383         }
8384
8385         /*
8386          * Merging of IO and MSR bitmaps not currently supported.
8387          * Rather, exit every time.
8388          */
8389         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8390         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8391         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8392
8393         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8394
8395         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8396          * bitwise-or of what L1 wants to trap for L2, and what we want to
8397          * trap. Note that CR0.TS also needs updating - we do this later.
8398          */
8399         update_exception_bitmap(vcpu);
8400         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8401         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8402
8403         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8404          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8405          * bits are further modified by vmx_set_efer() below.
8406          */
8407         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8408
8409         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8410          * emulated by vmx_set_efer(), below.
8411          */
8412         vm_entry_controls_init(vmx,
8413                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8414                         ~VM_ENTRY_IA32E_MODE) |
8415                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8416
8417         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
8418                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
8419                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8420         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
8421                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8422
8423
8424         set_cr4_guest_host_mask(vmx);
8425
8426         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8427                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8428
8429         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8430                 vmcs_write64(TSC_OFFSET,
8431                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8432         else
8433                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8434
8435         if (enable_vpid) {
8436                 /*
8437                  * Trivially support vpid by letting L2s share their parent
8438                  * L1's vpid. TODO: move to a more elaborate solution, giving
8439                  * each L2 its own vpid and exposing the vpid feature to L1.
8440                  */
8441                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8442                 vmx_flush_tlb(vcpu);
8443         }
8444
8445         if (nested_cpu_has_ept(vmcs12)) {
8446                 kvm_mmu_unload(vcpu);
8447                 nested_ept_init_mmu_context(vcpu);
8448         }
8449
8450         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8451                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
8452         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
8453                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8454         else
8455                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8456         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8457         vmx_set_efer(vcpu, vcpu->arch.efer);
8458
8459         /*
8460          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8461          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8462          * The CR0_READ_SHADOW is what L2 should have expected to read given
8463          * the specifications by L1; It's not enough to take
8464          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8465          * have more bits than L1 expected.
8466          */
8467         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8468         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8469
8470         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8471         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8472
8473         /* shadow page tables on either EPT or shadow page tables */
8474         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8475         kvm_mmu_reset_context(vcpu);
8476
8477         if (!enable_ept)
8478                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8479
8480         /*
8481          * L1 may access the L2's PDPTR, so save them to construct vmcs12
8482          */
8483         if (enable_ept) {
8484                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8485                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8486                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8487                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8488         }
8489
8490         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8491         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8492 }
8493
8494 /*
8495  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8496  * for running an L2 nested guest.
8497  */
8498 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8499 {
8500         struct vmcs12 *vmcs12;
8501         struct vcpu_vmx *vmx = to_vmx(vcpu);
8502         int cpu;
8503         struct loaded_vmcs *vmcs02;
8504         bool ia32e;
8505
8506         if (!nested_vmx_check_permission(vcpu) ||
8507             !nested_vmx_check_vmcs12(vcpu))
8508                 return 1;
8509
8510         skip_emulated_instruction(vcpu);
8511         vmcs12 = get_vmcs12(vcpu);
8512
8513         if (enable_shadow_vmcs)
8514                 copy_shadow_to_vmcs12(vmx);
8515
8516         /*
8517          * The nested entry process starts with enforcing various prerequisites
8518          * on vmcs12 as required by the Intel SDM, and act appropriately when
8519          * they fail: As the SDM explains, some conditions should cause the
8520          * instruction to fail, while others will cause the instruction to seem
8521          * to succeed, but return an EXIT_REASON_INVALID_STATE.
8522          * To speed up the normal (success) code path, we should avoid checking
8523          * for misconfigurations which will anyway be caught by the processor
8524          * when using the merged vmcs02.
8525          */
8526         if (vmcs12->launch_state == launch) {
8527                 nested_vmx_failValid(vcpu,
8528                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8529                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8530                 return 1;
8531         }
8532
8533         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8534             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8535                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8536                 return 1;
8537         }
8538
8539         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8540                         !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
8541                 /*TODO: Also verify bits beyond physical address width are 0*/
8542                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8543                 return 1;
8544         }
8545
8546         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
8547                 /*TODO: Also verify bits beyond physical address width are 0*/
8548                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8549                 return 1;
8550         }
8551
8552         if (vmcs12->vm_entry_msr_load_count > 0 ||
8553             vmcs12->vm_exit_msr_load_count > 0 ||
8554             vmcs12->vm_exit_msr_store_count > 0) {
8555                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8556                                     __func__);
8557                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8558                 return 1;
8559         }
8560
8561         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8562                                 nested_vmx_true_procbased_ctls_low,
8563                                 nested_vmx_procbased_ctls_high) ||
8564             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8565               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8566             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8567               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8568             !vmx_control_verify(vmcs12->vm_exit_controls,
8569                                 nested_vmx_true_exit_ctls_low,
8570                                 nested_vmx_exit_ctls_high) ||
8571             !vmx_control_verify(vmcs12->vm_entry_controls,
8572                                 nested_vmx_true_entry_ctls_low,
8573                                 nested_vmx_entry_ctls_high))
8574         {
8575                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8576                 return 1;
8577         }
8578
8579         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8580             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8581                 nested_vmx_failValid(vcpu,
8582                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8583                 return 1;
8584         }
8585
8586         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8587             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8588                 nested_vmx_entry_failure(vcpu, vmcs12,
8589                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8590                 return 1;
8591         }
8592         if (vmcs12->vmcs_link_pointer != -1ull) {
8593                 nested_vmx_entry_failure(vcpu, vmcs12,
8594                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8595                 return 1;
8596         }
8597
8598         /*
8599          * If the load IA32_EFER VM-entry control is 1, the following checks
8600          * are performed on the field for the IA32_EFER MSR:
8601          * - Bits reserved in the IA32_EFER MSR must be 0.
8602          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8603          *   the IA-32e mode guest VM-exit control. It must also be identical
8604          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8605          *   CR0.PG) is 1.
8606          */
8607         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8608                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8609                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8610                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8611                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8612                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8613                         nested_vmx_entry_failure(vcpu, vmcs12,
8614                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8615                         return 1;
8616                 }
8617         }
8618
8619         /*
8620          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8621          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8622          * the values of the LMA and LME bits in the field must each be that of
8623          * the host address-space size VM-exit control.
8624          */
8625         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8626                 ia32e = (vmcs12->vm_exit_controls &
8627                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8628                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8629                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8630                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8631                         nested_vmx_entry_failure(vcpu, vmcs12,
8632                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8633                         return 1;
8634                 }
8635         }
8636
8637         /*
8638          * We're finally done with prerequisite checking, and can start with
8639          * the nested entry.
8640          */
8641
8642         vmcs02 = nested_get_current_vmcs02(vmx);
8643         if (!vmcs02)
8644                 return -ENOMEM;
8645
8646         enter_guest_mode(vcpu);
8647
8648         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8649
8650         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8651                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8652
8653         cpu = get_cpu();
8654         vmx->loaded_vmcs = vmcs02;
8655         vmx_vcpu_put(vcpu);
8656         vmx_vcpu_load(vcpu, cpu);
8657         vcpu->cpu = cpu;
8658         put_cpu();
8659
8660         vmx_segment_cache_clear(vmx);
8661
8662         vmcs12->launch_state = 1;
8663
8664         prepare_vmcs02(vcpu, vmcs12);
8665
8666         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8667                 return kvm_emulate_halt(vcpu);
8668
8669         vmx->nested.nested_run_pending = 1;
8670
8671         /*
8672          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8673          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8674          * returned as far as L1 is concerned. It will only return (and set
8675          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8676          */
8677         return 1;
8678 }
8679
8680 /*
8681  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8682  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8683  * This function returns the new value we should put in vmcs12.guest_cr0.
8684  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8685  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8686  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8687  *     didn't trap the bit, because if L1 did, so would L0).
8688  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8689  *     been modified by L2, and L1 knows it. So just leave the old value of
8690  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8691  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8692  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8693  *     changed these bits, and therefore they need to be updated, but L0
8694  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8695  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8696  */
8697 static inline unsigned long
8698 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8699 {
8700         return
8701         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8702         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8703         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8704                         vcpu->arch.cr0_guest_owned_bits));
8705 }
8706
8707 static inline unsigned long
8708 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8709 {
8710         return
8711         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8712         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8713         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8714                         vcpu->arch.cr4_guest_owned_bits));
8715 }
8716
8717 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8718                                        struct vmcs12 *vmcs12)
8719 {
8720         u32 idt_vectoring;
8721         unsigned int nr;
8722
8723         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8724                 nr = vcpu->arch.exception.nr;
8725                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8726
8727                 if (kvm_exception_is_soft(nr)) {
8728                         vmcs12->vm_exit_instruction_len =
8729                                 vcpu->arch.event_exit_inst_len;
8730                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8731                 } else
8732                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8733
8734                 if (vcpu->arch.exception.has_error_code) {
8735                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8736                         vmcs12->idt_vectoring_error_code =
8737                                 vcpu->arch.exception.error_code;
8738                 }
8739
8740                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8741         } else if (vcpu->arch.nmi_injected) {
8742                 vmcs12->idt_vectoring_info_field =
8743                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8744         } else if (vcpu->arch.interrupt.pending) {
8745                 nr = vcpu->arch.interrupt.nr;
8746                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8747
8748                 if (vcpu->arch.interrupt.soft) {
8749                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8750                         vmcs12->vm_entry_instruction_len =
8751                                 vcpu->arch.event_exit_inst_len;
8752                 } else
8753                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8754
8755                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8756         }
8757 }
8758
8759 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8760 {
8761         struct vcpu_vmx *vmx = to_vmx(vcpu);
8762
8763         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8764             vmx->nested.preemption_timer_expired) {
8765                 if (vmx->nested.nested_run_pending)
8766                         return -EBUSY;
8767                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8768                 return 0;
8769         }
8770
8771         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8772                 if (vmx->nested.nested_run_pending ||
8773                     vcpu->arch.interrupt.pending)
8774                         return -EBUSY;
8775                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8776                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8777                                   INTR_INFO_VALID_MASK, 0);
8778                 /*
8779                  * The NMI-triggered VM exit counts as injection:
8780                  * clear this one and block further NMIs.
8781                  */
8782                 vcpu->arch.nmi_pending = 0;
8783                 vmx_set_nmi_mask(vcpu, true);
8784                 return 0;
8785         }
8786
8787         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8788             nested_exit_on_intr(vcpu)) {
8789                 if (vmx->nested.nested_run_pending)
8790                         return -EBUSY;
8791                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8792         }
8793
8794         return 0;
8795 }
8796
8797 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8798 {
8799         ktime_t remaining =
8800                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8801         u64 value;
8802
8803         if (ktime_to_ns(remaining) <= 0)
8804                 return 0;
8805
8806         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8807         do_div(value, 1000000);
8808         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8809 }
8810
8811 /*
8812  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8813  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8814  * and this function updates it to reflect the changes to the guest state while
8815  * L2 was running (and perhaps made some exits which were handled directly by L0
8816  * without going back to L1), and to reflect the exit reason.
8817  * Note that we do not have to copy here all VMCS fields, just those that
8818  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8819  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8820  * which already writes to vmcs12 directly.
8821  */
8822 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8823                            u32 exit_reason, u32 exit_intr_info,
8824                            unsigned long exit_qualification)
8825 {
8826         /* update guest state fields: */
8827         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8828         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8829
8830         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8831         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8832         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8833
8834         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8835         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8836         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8837         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8838         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8839         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8840         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8841         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8842         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8843         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8844         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8845         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8846         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8847         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8848         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8849         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8850         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8851         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8852         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8853         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8854         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8855         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8856         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8857         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8858         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8859         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8860         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8861         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8862         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8863         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8864         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8865         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8866         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8867         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8868         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8869         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8870
8871         vmcs12->guest_interruptibility_info =
8872                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8873         vmcs12->guest_pending_dbg_exceptions =
8874                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8875         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8876                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8877         else
8878                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8879
8880         if (nested_cpu_has_preemption_timer(vmcs12)) {
8881                 if (vmcs12->vm_exit_controls &
8882                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8883                         vmcs12->vmx_preemption_timer_value =
8884                                 vmx_get_preemption_timer_value(vcpu);
8885                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8886         }
8887
8888         /*
8889          * In some cases (usually, nested EPT), L2 is allowed to change its
8890          * own CR3 without exiting. If it has changed it, we must keep it.
8891          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8892          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8893          *
8894          * Additionally, restore L2's PDPTR to vmcs12.
8895          */
8896         if (enable_ept) {
8897                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8898                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8899                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8900                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8901                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8902         }
8903
8904         vmcs12->vm_entry_controls =
8905                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8906                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8907
8908         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8909                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8910                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8911         }
8912
8913         /* TODO: These cannot have changed unless we have MSR bitmaps and
8914          * the relevant bit asks not to trap the change */
8915         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8916                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8917         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8918                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8919         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8920         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8921         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8922         if (vmx_mpx_supported())
8923                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8924
8925         /* update exit information fields: */
8926
8927         vmcs12->vm_exit_reason = exit_reason;
8928         vmcs12->exit_qualification = exit_qualification;
8929
8930         vmcs12->vm_exit_intr_info = exit_intr_info;
8931         if ((vmcs12->vm_exit_intr_info &
8932              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8933             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8934                 vmcs12->vm_exit_intr_error_code =
8935                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8936         vmcs12->idt_vectoring_info_field = 0;
8937         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8938         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8939
8940         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8941                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8942                  * instead of reading the real value. */
8943                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8944
8945                 /*
8946                  * Transfer the event that L0 or L1 may wanted to inject into
8947                  * L2 to IDT_VECTORING_INFO_FIELD.
8948                  */
8949                 vmcs12_save_pending_event(vcpu, vmcs12);
8950         }
8951
8952         /*
8953          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8954          * preserved above and would only end up incorrectly in L1.
8955          */
8956         vcpu->arch.nmi_injected = false;
8957         kvm_clear_exception_queue(vcpu);
8958         kvm_clear_interrupt_queue(vcpu);
8959 }
8960
8961 /*
8962  * A part of what we need to when the nested L2 guest exits and we want to
8963  * run its L1 parent, is to reset L1's guest state to the host state specified
8964  * in vmcs12.
8965  * This function is to be called not only on normal nested exit, but also on
8966  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8967  * Failures During or After Loading Guest State").
8968  * This function should be called when the active VMCS is L1's (vmcs01).
8969  */
8970 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8971                                    struct vmcs12 *vmcs12)
8972 {
8973         struct kvm_segment seg;
8974
8975         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8976                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8977         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8978                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8979         else
8980                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8981         vmx_set_efer(vcpu, vcpu->arch.efer);
8982
8983         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8984         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8985         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8986         /*
8987          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8988          * actually changed, because it depends on the current state of
8989          * fpu_active (which may have changed).
8990          * Note that vmx_set_cr0 refers to efer set above.
8991          */
8992         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8993         /*
8994          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8995          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8996          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8997          */
8998         update_exception_bitmap(vcpu);
8999         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9000         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9001
9002         /*
9003          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9004          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9005          */
9006         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9007         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9008
9009         nested_ept_uninit_mmu_context(vcpu);
9010
9011         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9012         kvm_mmu_reset_context(vcpu);
9013
9014         if (!enable_ept)
9015                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9016
9017         if (enable_vpid) {
9018                 /*
9019                  * Trivially support vpid by letting L2s share their parent
9020                  * L1's vpid. TODO: move to a more elaborate solution, giving
9021                  * each L2 its own vpid and exposing the vpid feature to L1.
9022                  */
9023                 vmx_flush_tlb(vcpu);
9024         }
9025
9026
9027         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9028         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9029         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9030         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9031         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9032
9033         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9034         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9035                 vmcs_write64(GUEST_BNDCFGS, 0);
9036
9037         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9038                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9039                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9040         }
9041         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9042                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9043                         vmcs12->host_ia32_perf_global_ctrl);
9044
9045         /* Set L1 segment info according to Intel SDM
9046             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9047         seg = (struct kvm_segment) {
9048                 .base = 0,
9049                 .limit = 0xFFFFFFFF,
9050                 .selector = vmcs12->host_cs_selector,
9051                 .type = 11,
9052                 .present = 1,
9053                 .s = 1,
9054                 .g = 1
9055         };
9056         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9057                 seg.l = 1;
9058         else
9059                 seg.db = 1;
9060         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9061         seg = (struct kvm_segment) {
9062                 .base = 0,
9063                 .limit = 0xFFFFFFFF,
9064                 .type = 3,
9065                 .present = 1,
9066                 .s = 1,
9067                 .db = 1,
9068                 .g = 1
9069         };
9070         seg.selector = vmcs12->host_ds_selector;
9071         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9072         seg.selector = vmcs12->host_es_selector;
9073         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9074         seg.selector = vmcs12->host_ss_selector;
9075         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9076         seg.selector = vmcs12->host_fs_selector;
9077         seg.base = vmcs12->host_fs_base;
9078         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9079         seg.selector = vmcs12->host_gs_selector;
9080         seg.base = vmcs12->host_gs_base;
9081         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9082         seg = (struct kvm_segment) {
9083                 .base = vmcs12->host_tr_base,
9084                 .limit = 0x67,
9085                 .selector = vmcs12->host_tr_selector,
9086                 .type = 11,
9087                 .present = 1
9088         };
9089         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9090
9091         kvm_set_dr(vcpu, 7, 0x400);
9092         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9093 }
9094
9095 /*
9096  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9097  * and modify vmcs12 to make it see what it would expect to see there if
9098  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9099  */
9100 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9101                               u32 exit_intr_info,
9102                               unsigned long exit_qualification)
9103 {
9104         struct vcpu_vmx *vmx = to_vmx(vcpu);
9105         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9106
9107         /* trying to cancel vmlaunch/vmresume is a bug */
9108         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9109
9110         leave_guest_mode(vcpu);
9111         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9112                        exit_qualification);
9113
9114         vmx_load_vmcs01(vcpu);
9115
9116         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9117             && nested_exit_intr_ack_set(vcpu)) {
9118                 int irq = kvm_cpu_get_interrupt(vcpu);
9119                 WARN_ON(irq < 0);
9120                 vmcs12->vm_exit_intr_info = irq |
9121                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9122         }
9123
9124         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9125                                        vmcs12->exit_qualification,
9126                                        vmcs12->idt_vectoring_info_field,
9127                                        vmcs12->vm_exit_intr_info,
9128                                        vmcs12->vm_exit_intr_error_code,
9129                                        KVM_ISA_VMX);
9130
9131         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9132         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
9133         vmx_segment_cache_clear(vmx);
9134
9135         /* if no vmcs02 cache requested, remove the one we used */
9136         if (VMCS02_POOL_SIZE == 0)
9137                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9138
9139         load_vmcs12_host_state(vcpu, vmcs12);
9140
9141         /* Update TSC_OFFSET if TSC was changed while L2 ran */
9142         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9143
9144         /* This is needed for same reason as it was needed in prepare_vmcs02 */
9145         vmx->host_rsp = 0;
9146
9147         /* Unpin physical memory we referred to in vmcs02 */
9148         if (vmx->nested.apic_access_page) {
9149                 nested_release_page(vmx->nested.apic_access_page);
9150                 vmx->nested.apic_access_page = NULL;
9151         }
9152         if (vmx->nested.virtual_apic_page) {
9153                 nested_release_page(vmx->nested.virtual_apic_page);
9154                 vmx->nested.virtual_apic_page = NULL;
9155         }
9156
9157         /*
9158          * We are now running in L2, mmu_notifier will force to reload the
9159          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9160          */
9161         kvm_vcpu_reload_apic_access_page(vcpu);
9162
9163         /*
9164          * Exiting from L2 to L1, we're now back to L1 which thinks it just
9165          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9166          * success or failure flag accordingly.
9167          */
9168         if (unlikely(vmx->fail)) {
9169                 vmx->fail = 0;
9170                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9171         } else
9172                 nested_vmx_succeed(vcpu);
9173         if (enable_shadow_vmcs)
9174                 vmx->nested.sync_shadow_vmcs = true;
9175
9176         /* in case we halted in L2 */
9177         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9178 }
9179
9180 /*
9181  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9182  */
9183 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9184 {
9185         if (is_guest_mode(vcpu))
9186                 nested_vmx_vmexit(vcpu, -1, 0, 0);
9187         free_nested(to_vmx(vcpu));
9188 }
9189
9190 /*
9191  * L1's failure to enter L2 is a subset of a normal exit, as explained in
9192  * 23.7 "VM-entry failures during or after loading guest state" (this also
9193  * lists the acceptable exit-reason and exit-qualification parameters).
9194  * It should only be called before L2 actually succeeded to run, and when
9195  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9196  */
9197 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9198                         struct vmcs12 *vmcs12,
9199                         u32 reason, unsigned long qualification)
9200 {
9201         load_vmcs12_host_state(vcpu, vmcs12);
9202         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9203         vmcs12->exit_qualification = qualification;
9204         nested_vmx_succeed(vcpu);
9205         if (enable_shadow_vmcs)
9206                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
9207 }
9208
9209 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9210                                struct x86_instruction_info *info,
9211                                enum x86_intercept_stage stage)
9212 {
9213         return X86EMUL_CONTINUE;
9214 }
9215
9216 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
9217 {
9218         if (ple_gap)
9219                 shrink_ple_window(vcpu);
9220 }
9221
9222 static struct kvm_x86_ops vmx_x86_ops = {
9223         .cpu_has_kvm_support = cpu_has_kvm_support,
9224         .disabled_by_bios = vmx_disabled_by_bios,
9225         .hardware_setup = hardware_setup,
9226         .hardware_unsetup = hardware_unsetup,
9227         .check_processor_compatibility = vmx_check_processor_compat,
9228         .hardware_enable = hardware_enable,
9229         .hardware_disable = hardware_disable,
9230         .cpu_has_accelerated_tpr = report_flexpriority,
9231
9232         .vcpu_create = vmx_create_vcpu,
9233         .vcpu_free = vmx_free_vcpu,
9234         .vcpu_reset = vmx_vcpu_reset,
9235
9236         .prepare_guest_switch = vmx_save_host_state,
9237         .vcpu_load = vmx_vcpu_load,
9238         .vcpu_put = vmx_vcpu_put,
9239
9240         .update_db_bp_intercept = update_exception_bitmap,
9241         .get_msr = vmx_get_msr,
9242         .set_msr = vmx_set_msr,
9243         .get_segment_base = vmx_get_segment_base,
9244         .get_segment = vmx_get_segment,
9245         .set_segment = vmx_set_segment,
9246         .get_cpl = vmx_get_cpl,
9247         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
9248         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
9249         .decache_cr3 = vmx_decache_cr3,
9250         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
9251         .set_cr0 = vmx_set_cr0,
9252         .set_cr3 = vmx_set_cr3,
9253         .set_cr4 = vmx_set_cr4,
9254         .set_efer = vmx_set_efer,
9255         .get_idt = vmx_get_idt,
9256         .set_idt = vmx_set_idt,
9257         .get_gdt = vmx_get_gdt,
9258         .set_gdt = vmx_set_gdt,
9259         .get_dr6 = vmx_get_dr6,
9260         .set_dr6 = vmx_set_dr6,
9261         .set_dr7 = vmx_set_dr7,
9262         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
9263         .cache_reg = vmx_cache_reg,
9264         .get_rflags = vmx_get_rflags,
9265         .set_rflags = vmx_set_rflags,
9266         .fpu_deactivate = vmx_fpu_deactivate,
9267
9268         .tlb_flush = vmx_flush_tlb,
9269
9270         .run = vmx_vcpu_run,
9271         .handle_exit = vmx_handle_exit,
9272         .skip_emulated_instruction = skip_emulated_instruction,
9273         .set_interrupt_shadow = vmx_set_interrupt_shadow,
9274         .get_interrupt_shadow = vmx_get_interrupt_shadow,
9275         .patch_hypercall = vmx_patch_hypercall,
9276         .set_irq = vmx_inject_irq,
9277         .set_nmi = vmx_inject_nmi,
9278         .queue_exception = vmx_queue_exception,
9279         .cancel_injection = vmx_cancel_injection,
9280         .interrupt_allowed = vmx_interrupt_allowed,
9281         .nmi_allowed = vmx_nmi_allowed,
9282         .get_nmi_mask = vmx_get_nmi_mask,
9283         .set_nmi_mask = vmx_set_nmi_mask,
9284         .enable_nmi_window = enable_nmi_window,
9285         .enable_irq_window = enable_irq_window,
9286         .update_cr8_intercept = update_cr8_intercept,
9287         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
9288         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
9289         .vm_has_apicv = vmx_vm_has_apicv,
9290         .load_eoi_exitmap = vmx_load_eoi_exitmap,
9291         .hwapic_irr_update = vmx_hwapic_irr_update,
9292         .hwapic_isr_update = vmx_hwapic_isr_update,
9293         .sync_pir_to_irr = vmx_sync_pir_to_irr,
9294         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
9295
9296         .set_tss_addr = vmx_set_tss_addr,
9297         .get_tdp_level = get_ept_level,
9298         .get_mt_mask = vmx_get_mt_mask,
9299
9300         .get_exit_info = vmx_get_exit_info,
9301
9302         .get_lpage_level = vmx_get_lpage_level,
9303
9304         .cpuid_update = vmx_cpuid_update,
9305
9306         .rdtscp_supported = vmx_rdtscp_supported,
9307         .invpcid_supported = vmx_invpcid_supported,
9308
9309         .set_supported_cpuid = vmx_set_supported_cpuid,
9310
9311         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
9312
9313         .set_tsc_khz = vmx_set_tsc_khz,
9314         .read_tsc_offset = vmx_read_tsc_offset,
9315         .write_tsc_offset = vmx_write_tsc_offset,
9316         .adjust_tsc_offset = vmx_adjust_tsc_offset,
9317         .compute_tsc_offset = vmx_compute_tsc_offset,
9318         .read_l1_tsc = vmx_read_l1_tsc,
9319
9320         .set_tdp_cr3 = vmx_set_cr3,
9321
9322         .check_intercept = vmx_check_intercept,
9323         .handle_external_intr = vmx_handle_external_intr,
9324         .mpx_supported = vmx_mpx_supported,
9325
9326         .check_nested_events = vmx_check_nested_events,
9327
9328         .sched_in = vmx_sched_in,
9329 };
9330
9331 static int __init vmx_init(void)
9332 {
9333         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9334                      __alignof__(struct vcpu_vmx), THIS_MODULE);
9335         if (r)
9336                 return r;
9337
9338 #ifdef CONFIG_KEXEC
9339         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9340                            crash_vmclear_local_loaded_vmcss);
9341 #endif
9342
9343         return 0;
9344 }
9345
9346 static void __exit vmx_exit(void)
9347 {
9348 #ifdef CONFIG_KEXEC
9349         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
9350         synchronize_rcu();
9351 #endif
9352
9353         kvm_exit();
9354 }
9355
9356 module_init(vmx_init)
9357 module_exit(vmx_exit)