arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/cpu.h>
  42 #include <asm/io.h>
  43 #include <asm/desc.h>
  44 #include <asm/vmx.h>
  45 #include <asm/virtext.h>
  46 #include <asm/mce.h>
  47 #include <asm/fpu/internal.h>
  48 #include <asm/perf_event.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kexec.h>
  51 #include <asm/apic.h>
  52 #include <asm/irq_remapping.h>
  53 #include <asm/mmu_context.h>
  54 #include <asm/microcode.h>
  55 #include <asm/nospec-branch.h>
  56
  57 #include "trace.h"
  58 #include "pmu.h"
  59
  60 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  61 #define __ex_clear(x, reg) \
  62         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  63
  64 MODULE_AUTHOR("Qumranet");
  65 MODULE_LICENSE("GPL");
  66
  67 static const struct x86_cpu_id vmx_cpu_id[] = {
  68         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  69         {}
  70 };
  71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  72
  73 static bool __read_mostly enable_vpid = 1;
  74 module_param_named(vpid, enable_vpid, bool, 0444);
  75
  76 static bool __read_mostly enable_vnmi = 1;
  77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  78
  79 static bool __read_mostly flexpriority_enabled = 1;
  80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  81
  82 static bool __read_mostly enable_ept = 1;
  83 module_param_named(ept, enable_ept, bool, S_IRUGO);
  84
  85 static bool __read_mostly enable_unrestricted_guest = 1;
  86 module_param_named(unrestricted_guest,
  87                         enable_unrestricted_guest, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_ept_ad_bits = 1;
  90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  91
  92 static bool __read_mostly emulate_invalid_guest_state = true;
  93 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  94
  95 static bool __read_mostly fasteoi = 1;
  96 module_param(fasteoi, bool, S_IRUGO);
  97
  98 static bool __read_mostly enable_apicv = 1;
  99 module_param(enable_apicv, bool, S_IRUGO);
 100
 101 static bool __read_mostly enable_shadow_vmcs = 1;
 102 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 103 /*
 104  * If nested=1, nested virtualization is supported, i.e., guests may use
 105  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 106  * use VMX instructions.
 107  */
 108 static bool __read_mostly nested = 0;
 109 module_param(nested, bool, S_IRUGO);
 110
 111 static u64 __read_mostly host_xss;
 112
 113 static bool __read_mostly enable_pml = 1;
 114 module_param_named(pml, enable_pml, bool, S_IRUGO);
 115
 116 #define MSR_TYPE_R      1
 117 #define MSR_TYPE_W      2
 118 #define MSR_TYPE_RW     3
 119
 120 #define MSR_BITMAP_MODE_X2APIC          1
 121 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 122 #define MSR_BITMAP_MODE_LM              4
 123
 124 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 125
 126 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 127 static int __read_mostly cpu_preemption_timer_multi;
 128 static bool __read_mostly enable_preemption_timer = 1;
 129 #ifdef CONFIG_X86_64
 130 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 131 #endif
 132
 133 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 134 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 135 #define KVM_VM_CR0_ALWAYS_ON                                            \
 136         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 137 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 138         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 139          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 140
 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 143
 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 145
 146 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 147
 148 /*
 149  * Hyper-V requires all of these, so mark them as supported even though
 150  * they are just treated the same as all-context.
 151  */
 152 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 153         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 154         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 155         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 156         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 157
 158 /*
 159  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 160  * ple_gap:    upper bound on the amount of time between two successive
 161  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 162  *             According to test, this time is usually smaller than 128 cycles.
 163  * ple_window: upper bound on the amount of time a guest is allowed to execute
 164  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 165  *             less than 2^12 cycles
 166  * Time is measured based on a counter that runs at the same rate as the TSC,
 167  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 168  */
 169 #define KVM_VMX_DEFAULT_PLE_GAP           128
 170 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 171 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 172 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 173 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 174                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 175
 176 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 177 module_param(ple_gap, int, S_IRUGO);
 178
 179 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 180 module_param(ple_window, int, S_IRUGO);
 181
 182 /* Default doubles per-vcpu window every exit. */
 183 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 184 module_param(ple_window_grow, int, S_IRUGO);
 185
 186 /* Default resets per-vcpu window every exit to ple_window. */
 187 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 188 module_param(ple_window_shrink, int, S_IRUGO);
 189
 190 /* Default is to compute the maximum so we can never overflow. */
 191 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 192 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 193 module_param(ple_window_max, int, S_IRUGO);
 194
 195 extern const ulong vmx_return;
 196
 197 #define NR_AUTOLOAD_MSRS 8
 198
 199 struct vmcs {
 200         u32 revision_id;
 201         u32 abort;
 202         char data[0];
 203 };
 204
 205 /*
 206  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 207  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 208  * loaded on this CPU (so we can clear them if the CPU goes down).
 209  */
 210 struct loaded_vmcs {
 211         struct vmcs *vmcs;
 212         struct vmcs *shadow_vmcs;
 213         int cpu;
 214         bool launched;
 215         bool nmi_known_unmasked;
 216         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 217         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 218         /* Support for vnmi-less CPUs */
 219         int soft_vnmi_blocked;
 220         ktime_t entry_time;
 221         s64 vnmi_blocked_time;
 222         unsigned long *msr_bitmap;
 223         struct list_head loaded_vmcss_on_cpu_link;
 224 };
 225
 226 struct shared_msr_entry {
 227         unsigned index;
 228         u64 data;
 229         u64 mask;
 230 };
 231
 232 /*
 233  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 234  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 235  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 236  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 237  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 238  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 239  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 240  * underlying hardware which will be used to run L2.
 241  * This structure is packed to ensure that its layout is identical across
 242  * machines (necessary for live migration).
 243  * If there are changes in this struct, VMCS12_REVISION must be changed.
 244  */
 245 typedef u64 natural_width;
 246 struct __packed vmcs12 {
 247         /* According to the Intel spec, a VMCS region must start with the
 248          * following two fields. Then follow implementation-specific data.
 249          */
 250         u32 revision_id;
 251         u32 abort;
 252
 253         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 254         u32 padding[7]; /* room for future expansion */
 255
 256         u64 io_bitmap_a;
 257         u64 io_bitmap_b;
 258         u64 msr_bitmap;
 259         u64 vm_exit_msr_store_addr;
 260         u64 vm_exit_msr_load_addr;
 261         u64 vm_entry_msr_load_addr;
 262         u64 tsc_offset;
 263         u64 virtual_apic_page_addr;
 264         u64 apic_access_addr;
 265         u64 posted_intr_desc_addr;
 266         u64 vm_function_control;
 267         u64 ept_pointer;
 268         u64 eoi_exit_bitmap0;
 269         u64 eoi_exit_bitmap1;
 270         u64 eoi_exit_bitmap2;
 271         u64 eoi_exit_bitmap3;
 272         u64 eptp_list_address;
 273         u64 xss_exit_bitmap;
 274         u64 guest_physical_address;
 275         u64 vmcs_link_pointer;
 276         u64 pml_address;
 277         u64 guest_ia32_debugctl;
 278         u64 guest_ia32_pat;
 279         u64 guest_ia32_efer;
 280         u64 guest_ia32_perf_global_ctrl;
 281         u64 guest_pdptr0;
 282         u64 guest_pdptr1;
 283         u64 guest_pdptr2;
 284         u64 guest_pdptr3;
 285         u64 guest_bndcfgs;
 286         u64 host_ia32_pat;
 287         u64 host_ia32_efer;
 288         u64 host_ia32_perf_global_ctrl;
 289         u64 padding64[8]; /* room for future expansion */
 290         /*
 291          * To allow migration of L1 (complete with its L2 guests) between
 292          * machines of different natural widths (32 or 64 bit), we cannot have
 293          * unsigned long fields with no explict size. We use u64 (aliased
 294          * natural_width) instead. Luckily, x86 is little-endian.
 295          */
 296         natural_width cr0_guest_host_mask;
 297         natural_width cr4_guest_host_mask;
 298         natural_width cr0_read_shadow;
 299         natural_width cr4_read_shadow;
 300         natural_width cr3_target_value0;
 301         natural_width cr3_target_value1;
 302         natural_width cr3_target_value2;
 303         natural_width cr3_target_value3;
 304         natural_width exit_qualification;
 305         natural_width guest_linear_address;
 306         natural_width guest_cr0;
 307         natural_width guest_cr3;
 308         natural_width guest_cr4;
 309         natural_width guest_es_base;
 310         natural_width guest_cs_base;
 311         natural_width guest_ss_base;
 312         natural_width guest_ds_base;
 313         natural_width guest_fs_base;
 314         natural_width guest_gs_base;
 315         natural_width guest_ldtr_base;
 316         natural_width guest_tr_base;
 317         natural_width guest_gdtr_base;
 318         natural_width guest_idtr_base;
 319         natural_width guest_dr7;
 320         natural_width guest_rsp;
 321         natural_width guest_rip;
 322         natural_width guest_rflags;
 323         natural_width guest_pending_dbg_exceptions;
 324         natural_width guest_sysenter_esp;
 325         natural_width guest_sysenter_eip;
 326         natural_width host_cr0;
 327         natural_width host_cr3;
 328         natural_width host_cr4;
 329         natural_width host_fs_base;
 330         natural_width host_gs_base;
 331         natural_width host_tr_base;
 332         natural_width host_gdtr_base;
 333         natural_width host_idtr_base;
 334         natural_width host_ia32_sysenter_esp;
 335         natural_width host_ia32_sysenter_eip;
 336         natural_width host_rsp;
 337         natural_width host_rip;
 338         natural_width paddingl[8]; /* room for future expansion */
 339         u32 pin_based_vm_exec_control;
 340         u32 cpu_based_vm_exec_control;
 341         u32 exception_bitmap;
 342         u32 page_fault_error_code_mask;
 343         u32 page_fault_error_code_match;
 344         u32 cr3_target_count;
 345         u32 vm_exit_controls;
 346         u32 vm_exit_msr_store_count;
 347         u32 vm_exit_msr_load_count;
 348         u32 vm_entry_controls;
 349         u32 vm_entry_msr_load_count;
 350         u32 vm_entry_intr_info_field;
 351         u32 vm_entry_exception_error_code;
 352         u32 vm_entry_instruction_len;
 353         u32 tpr_threshold;
 354         u32 secondary_vm_exec_control;
 355         u32 vm_instruction_error;
 356         u32 vm_exit_reason;
 357         u32 vm_exit_intr_info;
 358         u32 vm_exit_intr_error_code;
 359         u32 idt_vectoring_info_field;
 360         u32 idt_vectoring_error_code;
 361         u32 vm_exit_instruction_len;
 362         u32 vmx_instruction_info;
 363         u32 guest_es_limit;
 364         u32 guest_cs_limit;
 365         u32 guest_ss_limit;
 366         u32 guest_ds_limit;
 367         u32 guest_fs_limit;
 368         u32 guest_gs_limit;
 369         u32 guest_ldtr_limit;
 370         u32 guest_tr_limit;
 371         u32 guest_gdtr_limit;
 372         u32 guest_idtr_limit;
 373         u32 guest_es_ar_bytes;
 374         u32 guest_cs_ar_bytes;
 375         u32 guest_ss_ar_bytes;
 376         u32 guest_ds_ar_bytes;
 377         u32 guest_fs_ar_bytes;
 378         u32 guest_gs_ar_bytes;
 379         u32 guest_ldtr_ar_bytes;
 380         u32 guest_tr_ar_bytes;
 381         u32 guest_interruptibility_info;
 382         u32 guest_activity_state;
 383         u32 guest_sysenter_cs;
 384         u32 host_ia32_sysenter_cs;
 385         u32 vmx_preemption_timer_value;
 386         u32 padding32[7]; /* room for future expansion */
 387         u16 virtual_processor_id;
 388         u16 posted_intr_nv;
 389         u16 guest_es_selector;
 390         u16 guest_cs_selector;
 391         u16 guest_ss_selector;
 392         u16 guest_ds_selector;
 393         u16 guest_fs_selector;
 394         u16 guest_gs_selector;
 395         u16 guest_ldtr_selector;
 396         u16 guest_tr_selector;
 397         u16 guest_intr_status;
 398         u16 guest_pml_index;
 399         u16 host_es_selector;
 400         u16 host_cs_selector;
 401         u16 host_ss_selector;
 402         u16 host_ds_selector;
 403         u16 host_fs_selector;
 404         u16 host_gs_selector;
 405         u16 host_tr_selector;
 406 };
 407
 408 /*
 409  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 410  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 411  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 412  */
 413 #define VMCS12_REVISION 0x11e57ed0
 414
 415 /*
 416  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 417  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 418  * current implementation, 4K are reserved to avoid future complications.
 419  */
 420 #define VMCS12_SIZE 0x1000
 421
 422 /*
 423  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 424  * supported VMCS12 field encoding.
 425  */
 426 #define VMCS12_MAX_FIELD_INDEX 0x17
 427
 428 /*
 429  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 430  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 431  */
 432 struct nested_vmx {
 433         /* Has the level1 guest done vmxon? */
 434         bool vmxon;
 435         gpa_t vmxon_ptr;
 436         bool pml_full;
 437
 438         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 439         gpa_t current_vmptr;
 440         /*
 441          * Cache of the guest's VMCS, existing outside of guest memory.
 442          * Loaded from guest memory during VMPTRLD. Flushed to guest
 443          * memory during VMCLEAR and VMPTRLD.
 444          */
 445         struct vmcs12 *cached_vmcs12;
 446         /*
 447          * Indicates if the shadow vmcs must be updated with the
 448          * data hold by vmcs12
 449          */
 450         bool sync_shadow_vmcs;
 451         bool dirty_vmcs12;
 452
 453         bool change_vmcs01_virtual_x2apic_mode;
 454         /* L2 must run next, and mustn't decide to exit to L1. */
 455         bool nested_run_pending;
 456
 457         struct loaded_vmcs vmcs02;
 458
 459         /*
 460          * Guest pages referred to in the vmcs02 with host-physical
 461          * pointers, so we must keep them pinned while L2 runs.
 462          */
 463         struct page *apic_access_page;
 464         struct page *virtual_apic_page;
 465         struct page *pi_desc_page;
 466         struct pi_desc *pi_desc;
 467         bool pi_pending;
 468         u16 posted_intr_nv;
 469
 470         struct hrtimer preemption_timer;
 471         bool preemption_timer_expired;
 472
 473         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 474         u64 vmcs01_debugctl;
 475
 476         u16 vpid02;
 477         u16 last_vpid;
 478
 479         /*
 480          * We only store the "true" versions of the VMX capability MSRs. We
 481          * generate the "non-true" versions by setting the must-be-1 bits
 482          * according to the SDM.
 483          */
 484         u32 nested_vmx_procbased_ctls_low;
 485         u32 nested_vmx_procbased_ctls_high;
 486         u32 nested_vmx_secondary_ctls_low;
 487         u32 nested_vmx_secondary_ctls_high;
 488         u32 nested_vmx_pinbased_ctls_low;
 489         u32 nested_vmx_pinbased_ctls_high;
 490         u32 nested_vmx_exit_ctls_low;
 491         u32 nested_vmx_exit_ctls_high;
 492         u32 nested_vmx_entry_ctls_low;
 493         u32 nested_vmx_entry_ctls_high;
 494         u32 nested_vmx_misc_low;
 495         u32 nested_vmx_misc_high;
 496         u32 nested_vmx_ept_caps;
 497         u32 nested_vmx_vpid_caps;
 498         u64 nested_vmx_basic;
 499         u64 nested_vmx_cr0_fixed0;
 500         u64 nested_vmx_cr0_fixed1;
 501         u64 nested_vmx_cr4_fixed0;
 502         u64 nested_vmx_cr4_fixed1;
 503         u64 nested_vmx_vmcs_enum;
 504         u64 nested_vmx_vmfunc_controls;
 505
 506         /* SMM related state */
 507         struct {
 508                 /* in VMX operation on SMM entry? */
 509                 bool vmxon;
 510                 /* in guest mode on SMM entry? */
 511                 bool guest_mode;
 512         } smm;
 513 };
 514
 515 #define POSTED_INTR_ON  0
 516 #define POSTED_INTR_SN  1
 517
 518 /* Posted-Interrupt Descriptor */
 519 struct pi_desc {
 520         u32 pir[8];     /* Posted interrupt requested */
 521         union {
 522                 struct {
 523                                 /* bit 256 - Outstanding Notification */
 524                         u16     on      : 1,
 525                                 /* bit 257 - Suppress Notification */
 526                                 sn      : 1,
 527                                 /* bit 271:258 - Reserved */
 528                                 rsvd_1  : 14;
 529                                 /* bit 279:272 - Notification Vector */
 530                         u8      nv;
 531                                 /* bit 287:280 - Reserved */
 532                         u8      rsvd_2;
 533                                 /* bit 319:288 - Notification Destination */
 534                         u32     ndst;
 535                 };
 536                 u64 control;
 537         };
 538         u32 rsvd[6];
 539 } __aligned(64);
 540
 541 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 542 {
 543         return test_and_set_bit(POSTED_INTR_ON,
 544                         (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 548 {
 549         return test_and_clear_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 554 {
 555         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 556 }
 557
 558 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 559 {
 560         return clear_bit(POSTED_INTR_SN,
 561                         (unsigned long *)&pi_desc->control);
 562 }
 563
 564 static inline void pi_set_sn(struct pi_desc *pi_desc)
 565 {
 566         return set_bit(POSTED_INTR_SN,
 567                         (unsigned long *)&pi_desc->control);
 568 }
 569
 570 static inline void pi_clear_on(struct pi_desc *pi_desc)
 571 {
 572         clear_bit(POSTED_INTR_ON,
 573                   (unsigned long *)&pi_desc->control);
 574 }
 575
 576 static inline int pi_test_on(struct pi_desc *pi_desc)
 577 {
 578         return test_bit(POSTED_INTR_ON,
 579                         (unsigned long *)&pi_desc->control);
 580 }
 581
 582 static inline int pi_test_sn(struct pi_desc *pi_desc)
 583 {
 584         return test_bit(POSTED_INTR_SN,
 585                         (unsigned long *)&pi_desc->control);
 586 }
 587
 588 struct vcpu_vmx {
 589         struct kvm_vcpu       vcpu;
 590         unsigned long         host_rsp;
 591         u8                    fail;
 592         u8                    msr_bitmap_mode;
 593         u32                   exit_intr_info;
 594         u32                   idt_vectoring_info;
 595         ulong                 rflags;
 596         struct shared_msr_entry *guest_msrs;
 597         int                   nmsrs;
 598         int                   save_nmsrs;
 599         unsigned long         host_idt_base;
 600 #ifdef CONFIG_X86_64
 601         u64                   msr_host_kernel_gs_base;
 602         u64                   msr_guest_kernel_gs_base;
 603 #endif
 604
 605         u64                   arch_capabilities;
 606         u64                   spec_ctrl;
 607
 608         u32 vm_entry_controls_shadow;
 609         u32 vm_exit_controls_shadow;
 610         u32 secondary_exec_control;
 611
 612         /*
 613          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 614          * non-nested (L1) guest, it always points to vmcs01. For a nested
 615          * guest (L2), it points to a different VMCS.
 616          */
 617         struct loaded_vmcs    vmcs01;
 618         struct loaded_vmcs   *loaded_vmcs;
 619         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 620         struct msr_autoload {
 621                 unsigned nr;
 622                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 623                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 624         } msr_autoload;
 625         struct {
 626                 int           loaded;
 627                 u16           fs_sel, gs_sel, ldt_sel;
 628 #ifdef CONFIG_X86_64
 629                 u16           ds_sel, es_sel;
 630 #endif
 631                 int           gs_ldt_reload_needed;
 632                 int           fs_reload_needed;
 633                 u64           msr_host_bndcfgs;
 634         } host_state;
 635         struct {
 636                 int vm86_active;
 637                 ulong save_rflags;
 638                 struct kvm_segment segs[8];
 639         } rmode;
 640         struct {
 641                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 642                 struct kvm_save_segment {
 643                         u16 selector;
 644                         unsigned long base;
 645                         u32 limit;
 646                         u32 ar;
 647                 } seg[8];
 648         } segment_cache;
 649         int vpid;
 650         bool emulation_required;
 651
 652         u32 exit_reason;
 653
 654         /* Posted interrupt descriptor */
 655         struct pi_desc pi_desc;
 656
 657         /* Support for a guest hypervisor (nested VMX) */
 658         struct nested_vmx nested;
 659
 660         /* Dynamic PLE window. */
 661         int ple_window;
 662         bool ple_window_dirty;
 663
 664         /* Support for PML */
 665 #define PML_ENTITY_NUM          512
 666         struct page *pml_pg;
 667
 668         /* apic deadline value in host tsc */
 669         u64 hv_deadline_tsc;
 670
 671         u64 current_tsc_ratio;
 672
 673         u32 host_pkru;
 674
 675         unsigned long host_debugctlmsr;
 676
 677         /*
 678          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 679          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 680          * in msr_ia32_feature_control_valid_bits.
 681          */
 682         u64 msr_ia32_feature_control;
 683         u64 msr_ia32_feature_control_valid_bits;
 684 };
 685
 686 enum segment_cache_field {
 687         SEG_FIELD_SEL = 0,
 688         SEG_FIELD_BASE = 1,
 689         SEG_FIELD_LIMIT = 2,
 690         SEG_FIELD_AR = 3,
 691
 692         SEG_FIELD_NR = 4
 693 };
 694
 695 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 696 {
 697         return container_of(vcpu, struct vcpu_vmx, vcpu);
 698 }
 699
 700 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 701 {
 702         return &(to_vmx(vcpu)->pi_desc);
 703 }
 704
 705 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
 706 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 707 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
 708 #define FIELD64(number, name)                                           \
 709         FIELD(number, name),                                            \
 710         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
 711
 712
 713 static u16 shadow_read_only_fields[] = {
 714 #define SHADOW_FIELD_RO(x) x,
 715 #include "vmx_shadow_fields.h"
 716 };
 717 static int max_shadow_read_only_fields =
 718         ARRAY_SIZE(shadow_read_only_fields);
 719
 720 static u16 shadow_read_write_fields[] = {
 721 #define SHADOW_FIELD_RW(x) x,
 722 #include "vmx_shadow_fields.h"
 723 };
 724 static int max_shadow_read_write_fields =
 725         ARRAY_SIZE(shadow_read_write_fields);
 726
 727 static const unsigned short vmcs_field_to_offset_table[] = {
 728         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 729         FIELD(POSTED_INTR_NV, posted_intr_nv),
 730         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 731         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 732         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 733         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 734         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 735         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 736         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 737         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 738         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 739         FIELD(GUEST_PML_INDEX, guest_pml_index),
 740         FIELD(HOST_ES_SELECTOR, host_es_selector),
 741         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 742         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 743         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 744         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 745         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 746         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 747         FIELD64(IO_BITMAP_A, io_bitmap_a),
 748         FIELD64(IO_BITMAP_B, io_bitmap_b),
 749         FIELD64(MSR_BITMAP, msr_bitmap),
 750         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 751         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 752         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 753         FIELD64(TSC_OFFSET, tsc_offset),
 754         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 755         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 756         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 757         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 758         FIELD64(EPT_POINTER, ept_pointer),
 759         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 760         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 761         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 762         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 763         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 764         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 765         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 766         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 767         FIELD64(PML_ADDRESS, pml_address),
 768         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 769         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 770         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 771         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 772         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 773         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 774         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 775         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 776         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 777         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 778         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 779         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 780         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 781         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 782         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 783         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 784         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 785         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 786         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 787         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 788         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 789         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 790         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 791         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 792         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 793         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 794         FIELD(TPR_THRESHOLD, tpr_threshold),
 795         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 796         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 797         FIELD(VM_EXIT_REASON, vm_exit_reason),
 798         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 799         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 800         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 801         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 802         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 803         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 804         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 805         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 806         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 807         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 808         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 809         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 810         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 811         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 812         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 813         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 814         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 815         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 816         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 817         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 818         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 819         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 820         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 821         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 822         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 823         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 824         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 825         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 826         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 827         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 828         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 829         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 830         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 831         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 832         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 833         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 834         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 835         FIELD(EXIT_QUALIFICATION, exit_qualification),
 836         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 837         FIELD(GUEST_CR0, guest_cr0),
 838         FIELD(GUEST_CR3, guest_cr3),
 839         FIELD(GUEST_CR4, guest_cr4),
 840         FIELD(GUEST_ES_BASE, guest_es_base),
 841         FIELD(GUEST_CS_BASE, guest_cs_base),
 842         FIELD(GUEST_SS_BASE, guest_ss_base),
 843         FIELD(GUEST_DS_BASE, guest_ds_base),
 844         FIELD(GUEST_FS_BASE, guest_fs_base),
 845         FIELD(GUEST_GS_BASE, guest_gs_base),
 846         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 847         FIELD(GUEST_TR_BASE, guest_tr_base),
 848         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 849         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 850         FIELD(GUEST_DR7, guest_dr7),
 851         FIELD(GUEST_RSP, guest_rsp),
 852         FIELD(GUEST_RIP, guest_rip),
 853         FIELD(GUEST_RFLAGS, guest_rflags),
 854         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 855         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 856         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 857         FIELD(HOST_CR0, host_cr0),
 858         FIELD(HOST_CR3, host_cr3),
 859         FIELD(HOST_CR4, host_cr4),
 860         FIELD(HOST_FS_BASE, host_fs_base),
 861         FIELD(HOST_GS_BASE, host_gs_base),
 862         FIELD(HOST_TR_BASE, host_tr_base),
 863         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 864         FIELD(HOST_IDTR_BASE, host_idtr_base),
 865         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 866         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 867         FIELD(HOST_RSP, host_rsp),
 868         FIELD(HOST_RIP, host_rip),
 869 };
 870
 871 static inline short vmcs_field_to_offset(unsigned long field)
 872 {
 873         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
 874         unsigned short offset;
 875         unsigned index;
 876
 877         if (field >> 15)
 878                 return -ENOENT;
 879
 880         index = ROL16(field, 6);
 881         if (index >= size)
 882                 return -ENOENT;
 883
 884         index = array_index_nospec(index, size);
 885         offset = vmcs_field_to_offset_table[index];
 886         if (offset == 0)
 887                 return -ENOENT;
 888         return offset;
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 897 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 898 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 899 static bool vmx_xsaves_supported(void);
 900 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 901                             struct kvm_segment *var, int seg);
 902 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 903                             struct kvm_segment *var, int seg);
 904 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 905 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 906 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 907 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 908 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 909 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 910                                             u16 error_code);
 911 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 912 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
 913                                                           u32 msr, int type);
 914
 915 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 916 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 917 /*
 918  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 919  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 920  */
 921 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 922
 923 /*
 924  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 925  * can find which vCPU should be waken up.
 926  */
 927 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 928 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 929
 930 enum {
 931         VMX_VMREAD_BITMAP,
 932         VMX_VMWRITE_BITMAP,
 933         VMX_BITMAP_NR
 934 };
 935
 936 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 937
 938 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 939 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 940
 941 static bool cpu_has_load_ia32_efer;
 942 static bool cpu_has_load_perf_global_ctrl;
 943
 944 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 945 static DEFINE_SPINLOCK(vmx_vpid_lock);
 946
 947 static struct vmcs_config {
 948         int size;
 949         int order;
 950         u32 basic_cap;
 951         u32 revision_id;
 952         u32 pin_based_exec_ctrl;
 953         u32 cpu_based_exec_ctrl;
 954         u32 cpu_based_2nd_exec_ctrl;
 955         u32 vmexit_ctrl;
 956         u32 vmentry_ctrl;
 957 } vmcs_config;
 958
 959 static struct vmx_capability {
 960         u32 ept;
 961         u32 vpid;
 962 } vmx_capability;
 963
 964 #define VMX_SEGMENT_FIELD(seg)                                  \
 965         [VCPU_SREG_##seg] = {                                   \
 966                 .selector = GUEST_##seg##_SELECTOR,             \
 967                 .base = GUEST_##seg##_BASE,                     \
 968                 .limit = GUEST_##seg##_LIMIT,                   \
 969                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 970         }
 971
 972 static const struct kvm_vmx_segment_field {
 973         unsigned selector;
 974         unsigned base;
 975         unsigned limit;
 976         unsigned ar_bytes;
 977 } kvm_vmx_segment_fields[] = {
 978         VMX_SEGMENT_FIELD(CS),
 979         VMX_SEGMENT_FIELD(DS),
 980         VMX_SEGMENT_FIELD(ES),
 981         VMX_SEGMENT_FIELD(FS),
 982         VMX_SEGMENT_FIELD(GS),
 983         VMX_SEGMENT_FIELD(SS),
 984         VMX_SEGMENT_FIELD(TR),
 985         VMX_SEGMENT_FIELD(LDTR),
 986 };
 987
 988 static u64 host_efer;
 989
 990 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 991
 992 /*
 993  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 994  * away by decrementing the array size.
 995  */
 996 static const u32 vmx_msr_index[] = {
 997 #ifdef CONFIG_X86_64
 998         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 999 #endif
1000         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1001 };
1002
1003 static inline bool is_exception_n(u32 intr_info, u8 vector)
1004 {
1005         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1006                              INTR_INFO_VALID_MASK)) ==
1007                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1008 }
1009
1010 static inline bool is_debug(u32 intr_info)
1011 {
1012         return is_exception_n(intr_info, DB_VECTOR);
1013 }
1014
1015 static inline bool is_breakpoint(u32 intr_info)
1016 {
1017         return is_exception_n(intr_info, BP_VECTOR);
1018 }
1019
1020 static inline bool is_page_fault(u32 intr_info)
1021 {
1022         return is_exception_n(intr_info, PF_VECTOR);
1023 }
1024
1025 static inline bool is_no_device(u32 intr_info)
1026 {
1027         return is_exception_n(intr_info, NM_VECTOR);
1028 }
1029
1030 static inline bool is_invalid_opcode(u32 intr_info)
1031 {
1032         return is_exception_n(intr_info, UD_VECTOR);
1033 }
1034
1035 static inline bool is_external_interrupt(u32 intr_info)
1036 {
1037         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1038                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1039 }
1040
1041 static inline bool is_machine_check(u32 intr_info)
1042 {
1043         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1044                              INTR_INFO_VALID_MASK)) ==
1045                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1046 }
1047
1048 static inline bool cpu_has_vmx_msr_bitmap(void)
1049 {
1050         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1051 }
1052
1053 static inline bool cpu_has_vmx_tpr_shadow(void)
1054 {
1055         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1056 }
1057
1058 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1059 {
1060         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1061 }
1062
1063 static inline bool cpu_has_secondary_exec_ctrls(void)
1064 {
1065         return vmcs_config.cpu_based_exec_ctrl &
1066                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1067 }
1068
1069 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1070 {
1071         return vmcs_config.cpu_based_2nd_exec_ctrl &
1072                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1073 }
1074
1075 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1076 {
1077         return vmcs_config.cpu_based_2nd_exec_ctrl &
1078                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1079 }
1080
1081 static inline bool cpu_has_vmx_apic_register_virt(void)
1082 {
1083         return vmcs_config.cpu_based_2nd_exec_ctrl &
1084                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1085 }
1086
1087 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1088 {
1089         return vmcs_config.cpu_based_2nd_exec_ctrl &
1090                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1091 }
1092
1093 /*
1094  * Comment's format: document - errata name - stepping - processor name.
1095  * Refer from
1096  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1097  */
1098 static u32 vmx_preemption_cpu_tfms[] = {
1099 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1100 0x000206E6,
1101 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1102 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1103 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1104 0x00020652,
1105 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1106 0x00020655,
1107 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1108 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1109 /*
1110  * 320767.pdf - AAP86  - B1 -
1111  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1112  */
1113 0x000106E5,
1114 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1115 0x000106A0,
1116 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1117 0x000106A1,
1118 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1119 0x000106A4,
1120  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1121  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1122  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1123 0x000106A5,
1124 };
1125
1126 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1127 {
1128         u32 eax = cpuid_eax(0x00000001), i;
1129
1130         /* Clear the reserved bits */
1131         eax &= ~(0x3U << 14 | 0xfU << 28);
1132         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1133                 if (eax == vmx_preemption_cpu_tfms[i])
1134                         return true;
1135
1136         return false;
1137 }
1138
1139 static inline bool cpu_has_vmx_preemption_timer(void)
1140 {
1141         return vmcs_config.pin_based_exec_ctrl &
1142                 PIN_BASED_VMX_PREEMPTION_TIMER;
1143 }
1144
1145 static inline bool cpu_has_vmx_posted_intr(void)
1146 {
1147         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1148                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1149 }
1150
1151 static inline bool cpu_has_vmx_apicv(void)
1152 {
1153         return cpu_has_vmx_apic_register_virt() &&
1154                 cpu_has_vmx_virtual_intr_delivery() &&
1155                 cpu_has_vmx_posted_intr();
1156 }
1157
1158 static inline bool cpu_has_vmx_flexpriority(void)
1159 {
1160         return cpu_has_vmx_tpr_shadow() &&
1161                 cpu_has_vmx_virtualize_apic_accesses();
1162 }
1163
1164 static inline bool cpu_has_vmx_ept_execute_only(void)
1165 {
1166         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1167 }
1168
1169 static inline bool cpu_has_vmx_ept_2m_page(void)
1170 {
1171         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1172 }
1173
1174 static inline bool cpu_has_vmx_ept_1g_page(void)
1175 {
1176         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1177 }
1178
1179 static inline bool cpu_has_vmx_ept_4levels(void)
1180 {
1181         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1182 }
1183
1184 static inline bool cpu_has_vmx_ept_mt_wb(void)
1185 {
1186         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1187 }
1188
1189 static inline bool cpu_has_vmx_ept_5levels(void)
1190 {
1191         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1192 }
1193
1194 static inline bool cpu_has_vmx_ept_ad_bits(void)
1195 {
1196         return vmx_capability.ept & VMX_EPT_AD_BIT;
1197 }
1198
1199 static inline bool cpu_has_vmx_invept_context(void)
1200 {
1201         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1202 }
1203
1204 static inline bool cpu_has_vmx_invept_global(void)
1205 {
1206         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1207 }
1208
1209 static inline bool cpu_has_vmx_invvpid_single(void)
1210 {
1211         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1212 }
1213
1214 static inline bool cpu_has_vmx_invvpid_global(void)
1215 {
1216         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1217 }
1218
1219 static inline bool cpu_has_vmx_invvpid(void)
1220 {
1221         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1222 }
1223
1224 static inline bool cpu_has_vmx_ept(void)
1225 {
1226         return vmcs_config.cpu_based_2nd_exec_ctrl &
1227                 SECONDARY_EXEC_ENABLE_EPT;
1228 }
1229
1230 static inline bool cpu_has_vmx_unrestricted_guest(void)
1231 {
1232         return vmcs_config.cpu_based_2nd_exec_ctrl &
1233                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1234 }
1235
1236 static inline bool cpu_has_vmx_ple(void)
1237 {
1238         return vmcs_config.cpu_based_2nd_exec_ctrl &
1239                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1240 }
1241
1242 static inline bool cpu_has_vmx_basic_inout(void)
1243 {
1244         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1245 }
1246
1247 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1248 {
1249         return flexpriority_enabled && lapic_in_kernel(vcpu);
1250 }
1251
1252 static inline bool cpu_has_vmx_vpid(void)
1253 {
1254         return vmcs_config.cpu_based_2nd_exec_ctrl &
1255                 SECONDARY_EXEC_ENABLE_VPID;
1256 }
1257
1258 static inline bool cpu_has_vmx_rdtscp(void)
1259 {
1260         return vmcs_config.cpu_based_2nd_exec_ctrl &
1261                 SECONDARY_EXEC_RDTSCP;
1262 }
1263
1264 static inline bool cpu_has_vmx_invpcid(void)
1265 {
1266         return vmcs_config.cpu_based_2nd_exec_ctrl &
1267                 SECONDARY_EXEC_ENABLE_INVPCID;
1268 }
1269
1270 static inline bool cpu_has_virtual_nmis(void)
1271 {
1272         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1273 }
1274
1275 static inline bool cpu_has_vmx_wbinvd_exit(void)
1276 {
1277         return vmcs_config.cpu_based_2nd_exec_ctrl &
1278                 SECONDARY_EXEC_WBINVD_EXITING;
1279 }
1280
1281 static inline bool cpu_has_vmx_shadow_vmcs(void)
1282 {
1283         u64 vmx_msr;
1284         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1285         /* check if the cpu supports writing r/o exit information fields */
1286         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1287                 return false;
1288
1289         return vmcs_config.cpu_based_2nd_exec_ctrl &
1290                 SECONDARY_EXEC_SHADOW_VMCS;
1291 }
1292
1293 static inline bool cpu_has_vmx_pml(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1296 }
1297
1298 static inline bool cpu_has_vmx_tsc_scaling(void)
1299 {
1300         return vmcs_config.cpu_based_2nd_exec_ctrl &
1301                 SECONDARY_EXEC_TSC_SCALING;
1302 }
1303
1304 static inline bool cpu_has_vmx_vmfunc(void)
1305 {
1306         return vmcs_config.cpu_based_2nd_exec_ctrl &
1307                 SECONDARY_EXEC_ENABLE_VMFUNC;
1308 }
1309
1310 static inline bool report_flexpriority(void)
1311 {
1312         return flexpriority_enabled;
1313 }
1314
1315 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1316 {
1317         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1318 }
1319
1320 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1321 {
1322         return vmcs12->cpu_based_vm_exec_control & bit;
1323 }
1324
1325 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1326 {
1327         return (vmcs12->cpu_based_vm_exec_control &
1328                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1329                 (vmcs12->secondary_vm_exec_control & bit);
1330 }
1331
1332 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1333 {
1334         return vmcs12->pin_based_vm_exec_control &
1335                 PIN_BASED_VMX_PREEMPTION_TIMER;
1336 }
1337
1338 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1339 {
1340         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1341 }
1342
1343 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1344 {
1345         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1346 }
1347
1348 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1349 {
1350         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1351 }
1352
1353 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1354 {
1355         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1356 }
1357
1358 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1359 {
1360         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1361 }
1362
1363 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1364 {
1365         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1366 }
1367
1368 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1369 {
1370         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1371 }
1372
1373 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1374 {
1375         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1376 }
1377
1378 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1379 {
1380         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1381 }
1382
1383 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1384 {
1385         return nested_cpu_has_vmfunc(vmcs12) &&
1386                 (vmcs12->vm_function_control &
1387                  VMX_VMFUNC_EPTP_SWITCHING);
1388 }
1389
1390 static inline bool is_nmi(u32 intr_info)
1391 {
1392         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1393                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1394 }
1395
1396 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1397                               u32 exit_intr_info,
1398                               unsigned long exit_qualification);
1399 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1400                         struct vmcs12 *vmcs12,
1401                         u32 reason, unsigned long qualification);
1402
1403 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1404 {
1405         int i;
1406
1407         for (i = 0; i < vmx->nmsrs; ++i)
1408                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1409                         return i;
1410         return -1;
1411 }
1412
1413 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1414 {
1415     struct {
1416         u64 vpid : 16;
1417         u64 rsvd : 48;
1418         u64 gva;
1419     } operand = { vpid, 0, gva };
1420
1421     asm volatile (__ex(ASM_VMX_INVVPID)
1422                   /* CF==1 or ZF==1 --> rc = -1 */
1423                   "; ja 1f ; ud2 ; 1:"
1424                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1425 }
1426
1427 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1428 {
1429         struct {
1430                 u64 eptp, gpa;
1431         } operand = {eptp, gpa};
1432
1433         asm volatile (__ex(ASM_VMX_INVEPT)
1434                         /* CF==1 or ZF==1 --> rc = -1 */
1435                         "; ja 1f ; ud2 ; 1:\n"
1436                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1437 }
1438
1439 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1440 {
1441         int i;
1442
1443         i = __find_msr_index(vmx, msr);
1444         if (i >= 0)
1445                 return &vmx->guest_msrs[i];
1446         return NULL;
1447 }
1448
1449 static void vmcs_clear(struct vmcs *vmcs)
1450 {
1451         u64 phys_addr = __pa(vmcs);
1452         u8 error;
1453
1454         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1455                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1456                       : "cc", "memory");
1457         if (error)
1458                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1459                        vmcs, phys_addr);
1460 }
1461
1462 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1463 {
1464         vmcs_clear(loaded_vmcs->vmcs);
1465         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1466                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1467         loaded_vmcs->cpu = -1;
1468         loaded_vmcs->launched = 0;
1469 }
1470
1471 static void vmcs_load(struct vmcs *vmcs)
1472 {
1473         u64 phys_addr = __pa(vmcs);
1474         u8 error;
1475
1476         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1477                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1478                         : "cc", "memory");
1479         if (error)
1480                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1481                        vmcs, phys_addr);
1482 }
1483
1484 #ifdef CONFIG_KEXEC_CORE
1485 /*
1486  * This bitmap is used to indicate whether the vmclear
1487  * operation is enabled on all cpus. All disabled by
1488  * default.
1489  */
1490 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1491
1492 static inline void crash_enable_local_vmclear(int cpu)
1493 {
1494         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1495 }
1496
1497 static inline void crash_disable_local_vmclear(int cpu)
1498 {
1499         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500 }
1501
1502 static inline int crash_local_vmclear_enabled(int cpu)
1503 {
1504         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505 }
1506
1507 static void crash_vmclear_local_loaded_vmcss(void)
1508 {
1509         int cpu = raw_smp_processor_id();
1510         struct loaded_vmcs *v;
1511
1512         if (!crash_local_vmclear_enabled(cpu))
1513                 return;
1514
1515         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1516                             loaded_vmcss_on_cpu_link)
1517                 vmcs_clear(v->vmcs);
1518 }
1519 #else
1520 static inline void crash_enable_local_vmclear(int cpu) { }
1521 static inline void crash_disable_local_vmclear(int cpu) { }
1522 #endif /* CONFIG_KEXEC_CORE */
1523
1524 static void __loaded_vmcs_clear(void *arg)
1525 {
1526         struct loaded_vmcs *loaded_vmcs = arg;
1527         int cpu = raw_smp_processor_id();
1528
1529         if (loaded_vmcs->cpu != cpu)
1530                 return; /* vcpu migration can race with cpu offline */
1531         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1532                 per_cpu(current_vmcs, cpu) = NULL;
1533         crash_disable_local_vmclear(cpu);
1534         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1535
1536         /*
1537          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1538          * is before setting loaded_vmcs->vcpu to -1 which is done in
1539          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1540          * then adds the vmcs into percpu list before it is deleted.
1541          */
1542         smp_wmb();
1543
1544         loaded_vmcs_init(loaded_vmcs);
1545         crash_enable_local_vmclear(cpu);
1546 }
1547
1548 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1549 {
1550         int cpu = loaded_vmcs->cpu;
1551
1552         if (cpu != -1)
1553                 smp_call_function_single(cpu,
1554                          __loaded_vmcs_clear, loaded_vmcs, 1);
1555 }
1556
1557 static inline void vpid_sync_vcpu_single(int vpid)
1558 {
1559         if (vpid == 0)
1560                 return;
1561
1562         if (cpu_has_vmx_invvpid_single())
1563                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1564 }
1565
1566 static inline void vpid_sync_vcpu_global(void)
1567 {
1568         if (cpu_has_vmx_invvpid_global())
1569                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1570 }
1571
1572 static inline void vpid_sync_context(int vpid)
1573 {
1574         if (cpu_has_vmx_invvpid_single())
1575                 vpid_sync_vcpu_single(vpid);
1576         else
1577                 vpid_sync_vcpu_global();
1578 }
1579
1580 static inline void ept_sync_global(void)
1581 {
1582         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1583 }
1584
1585 static inline void ept_sync_context(u64 eptp)
1586 {
1587         if (cpu_has_vmx_invept_context())
1588                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1589         else
1590                 ept_sync_global();
1591 }
1592
1593 static __always_inline void vmcs_check16(unsigned long field)
1594 {
1595         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1596                          "16-bit accessor invalid for 64-bit field");
1597         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1598                          "16-bit accessor invalid for 64-bit high field");
1599         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1600                          "16-bit accessor invalid for 32-bit high field");
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1602                          "16-bit accessor invalid for natural width field");
1603 }
1604
1605 static __always_inline void vmcs_check32(unsigned long field)
1606 {
1607         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1608                          "32-bit accessor invalid for 16-bit field");
1609         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610                          "32-bit accessor invalid for natural width field");
1611 }
1612
1613 static __always_inline void vmcs_check64(unsigned long field)
1614 {
1615         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616                          "64-bit accessor invalid for 16-bit field");
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1618                          "64-bit accessor invalid for 64-bit high field");
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1620                          "64-bit accessor invalid for 32-bit field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1622                          "64-bit accessor invalid for natural width field");
1623 }
1624
1625 static __always_inline void vmcs_checkl(unsigned long field)
1626 {
1627         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1628                          "Natural width accessor invalid for 16-bit field");
1629         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1630                          "Natural width accessor invalid for 64-bit field");
1631         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1632                          "Natural width accessor invalid for 64-bit high field");
1633         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1634                          "Natural width accessor invalid for 32-bit field");
1635 }
1636
1637 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1638 {
1639         unsigned long value;
1640
1641         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1642                       : "=a"(value) : "d"(field) : "cc");
1643         return value;
1644 }
1645
1646 static __always_inline u16 vmcs_read16(unsigned long field)
1647 {
1648         vmcs_check16(field);
1649         return __vmcs_readl(field);
1650 }
1651
1652 static __always_inline u32 vmcs_read32(unsigned long field)
1653 {
1654         vmcs_check32(field);
1655         return __vmcs_readl(field);
1656 }
1657
1658 static __always_inline u64 vmcs_read64(unsigned long field)
1659 {
1660         vmcs_check64(field);
1661 #ifdef CONFIG_X86_64
1662         return __vmcs_readl(field);
1663 #else
1664         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1665 #endif
1666 }
1667
1668 static __always_inline unsigned long vmcs_readl(unsigned long field)
1669 {
1670         vmcs_checkl(field);
1671         return __vmcs_readl(field);
1672 }
1673
1674 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1675 {
1676         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1677                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1678         dump_stack();
1679 }
1680
1681 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1682 {
1683         u8 error;
1684
1685         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1686                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1687         if (unlikely(error))
1688                 vmwrite_error(field, value);
1689 }
1690
1691 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1692 {
1693         vmcs_check16(field);
1694         __vmcs_writel(field, value);
1695 }
1696
1697 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1698 {
1699         vmcs_check32(field);
1700         __vmcs_writel(field, value);
1701 }
1702
1703 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1704 {
1705         vmcs_check64(field);
1706         __vmcs_writel(field, value);
1707 #ifndef CONFIG_X86_64
1708         asm volatile ("");
1709         __vmcs_writel(field+1, value >> 32);
1710 #endif
1711 }
1712
1713 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1714 {
1715         vmcs_checkl(field);
1716         __vmcs_writel(field, value);
1717 }
1718
1719 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1720 {
1721         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1722                          "vmcs_clear_bits does not support 64-bit fields");
1723         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1724 }
1725
1726 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1727 {
1728         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1729                          "vmcs_set_bits does not support 64-bit fields");
1730         __vmcs_writel(field, __vmcs_readl(field) | mask);
1731 }
1732
1733 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1734 {
1735         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1736 }
1737
1738 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1739 {
1740         vmcs_write32(VM_ENTRY_CONTROLS, val);
1741         vmx->vm_entry_controls_shadow = val;
1742 }
1743
1744 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1745 {
1746         if (vmx->vm_entry_controls_shadow != val)
1747                 vm_entry_controls_init(vmx, val);
1748 }
1749
1750 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1751 {
1752         return vmx->vm_entry_controls_shadow;
1753 }
1754
1755
1756 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1757 {
1758         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1759 }
1760
1761 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1762 {
1763         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1764 }
1765
1766 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1767 {
1768         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1769 }
1770
1771 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1772 {
1773         vmcs_write32(VM_EXIT_CONTROLS, val);
1774         vmx->vm_exit_controls_shadow = val;
1775 }
1776
1777 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1778 {
1779         if (vmx->vm_exit_controls_shadow != val)
1780                 vm_exit_controls_init(vmx, val);
1781 }
1782
1783 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1784 {
1785         return vmx->vm_exit_controls_shadow;
1786 }
1787
1788
1789 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1790 {
1791         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1792 }
1793
1794 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1795 {
1796         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1797 }
1798
1799 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1800 {
1801         vmx->segment_cache.bitmask = 0;
1802 }
1803
1804 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1805                                        unsigned field)
1806 {
1807         bool ret;
1808         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1809
1810         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1811                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1812                 vmx->segment_cache.bitmask = 0;
1813         }
1814         ret = vmx->segment_cache.bitmask & mask;
1815         vmx->segment_cache.bitmask |= mask;
1816         return ret;
1817 }
1818
1819 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1820 {
1821         u16 *p = &vmx->segment_cache.seg[seg].selector;
1822
1823         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1824                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1825         return *p;
1826 }
1827
1828 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1829 {
1830         ulong *p = &vmx->segment_cache.seg[seg].base;
1831
1832         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1833                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1834         return *p;
1835 }
1836
1837 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1838 {
1839         u32 *p = &vmx->segment_cache.seg[seg].limit;
1840
1841         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1842                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1843         return *p;
1844 }
1845
1846 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1847 {
1848         u32 *p = &vmx->segment_cache.seg[seg].ar;
1849
1850         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1851                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1852         return *p;
1853 }
1854
1855 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1856 {
1857         u32 eb;
1858
1859         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1860              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1861         if ((vcpu->guest_debug &
1862              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1863             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1864                 eb |= 1u << BP_VECTOR;
1865         if (to_vmx(vcpu)->rmode.vm86_active)
1866                 eb = ~0;
1867         if (enable_ept)
1868                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1869
1870         /* When we are running a nested L2 guest and L1 specified for it a
1871          * certain exception bitmap, we must trap the same exceptions and pass
1872          * them to L1. When running L2, we will only handle the exceptions
1873          * specified above if L1 did not want them.
1874          */
1875         if (is_guest_mode(vcpu))
1876                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1877
1878         vmcs_write32(EXCEPTION_BITMAP, eb);
1879 }
1880
1881 /*
1882  * Check if MSR is intercepted for currently loaded MSR bitmap.
1883  */
1884 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
1885 {
1886         unsigned long *msr_bitmap;
1887         int f = sizeof(unsigned long);
1888
1889         if (!cpu_has_vmx_msr_bitmap())
1890                 return true;
1891
1892         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
1893
1894         if (msr <= 0x1fff) {
1895                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1896         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1897                 msr &= 0x1fff;
1898                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1899         }
1900
1901         return true;
1902 }
1903
1904 /*
1905  * Check if MSR is intercepted for L01 MSR bitmap.
1906  */
1907 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
1908 {
1909         unsigned long *msr_bitmap;
1910         int f = sizeof(unsigned long);
1911
1912         if (!cpu_has_vmx_msr_bitmap())
1913                 return true;
1914
1915         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
1916
1917         if (msr <= 0x1fff) {
1918                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1919         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1920                 msr &= 0x1fff;
1921                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1922         }
1923
1924         return true;
1925 }
1926
1927 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1928                 unsigned long entry, unsigned long exit)
1929 {
1930         vm_entry_controls_clearbit(vmx, entry);
1931         vm_exit_controls_clearbit(vmx, exit);
1932 }
1933
1934 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1935 {
1936         unsigned i;
1937         struct msr_autoload *m = &vmx->msr_autoload;
1938
1939         switch (msr) {
1940         case MSR_EFER:
1941                 if (cpu_has_load_ia32_efer) {
1942                         clear_atomic_switch_msr_special(vmx,
1943                                         VM_ENTRY_LOAD_IA32_EFER,
1944                                         VM_EXIT_LOAD_IA32_EFER);
1945                         return;
1946                 }
1947                 break;
1948         case MSR_CORE_PERF_GLOBAL_CTRL:
1949                 if (cpu_has_load_perf_global_ctrl) {
1950                         clear_atomic_switch_msr_special(vmx,
1951                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1952                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1953                         return;
1954                 }
1955                 break;
1956         }
1957
1958         for (i = 0; i < m->nr; ++i)
1959                 if (m->guest[i].index == msr)
1960                         break;
1961
1962         if (i == m->nr)
1963                 return;
1964         --m->nr;
1965         m->guest[i] = m->guest[m->nr];
1966         m->host[i] = m->host[m->nr];
1967         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1968         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1969 }
1970
1971 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1972                 unsigned long entry, unsigned long exit,
1973                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1974                 u64 guest_val, u64 host_val)
1975 {
1976         vmcs_write64(guest_val_vmcs, guest_val);
1977         vmcs_write64(host_val_vmcs, host_val);
1978         vm_entry_controls_setbit(vmx, entry);
1979         vm_exit_controls_setbit(vmx, exit);
1980 }
1981
1982 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1983                                   u64 guest_val, u64 host_val)
1984 {
1985         unsigned i;
1986         struct msr_autoload *m = &vmx->msr_autoload;
1987
1988         switch (msr) {
1989         case MSR_EFER:
1990                 if (cpu_has_load_ia32_efer) {
1991                         add_atomic_switch_msr_special(vmx,
1992                                         VM_ENTRY_LOAD_IA32_EFER,
1993                                         VM_EXIT_LOAD_IA32_EFER,
1994                                         GUEST_IA32_EFER,
1995                                         HOST_IA32_EFER,
1996                                         guest_val, host_val);
1997                         return;
1998                 }
1999                 break;
2000         case MSR_CORE_PERF_GLOBAL_CTRL:
2001                 if (cpu_has_load_perf_global_ctrl) {
2002                         add_atomic_switch_msr_special(vmx,
2003                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2004                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2005                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2006                                         HOST_IA32_PERF_GLOBAL_CTRL,
2007                                         guest_val, host_val);
2008                         return;
2009                 }
2010                 break;
2011         case MSR_IA32_PEBS_ENABLE:
2012                 /* PEBS needs a quiescent period after being disabled (to write
2013                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2014                  * provide that period, so a CPU could write host's record into
2015                  * guest's memory.
2016                  */
2017                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2018         }
2019
2020         for (i = 0; i < m->nr; ++i)
2021                 if (m->guest[i].index == msr)
2022                         break;
2023
2024         if (i == NR_AUTOLOAD_MSRS) {
2025                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2026                                 "Can't add msr %x\n", msr);
2027                 return;
2028         } else if (i == m->nr) {
2029                 ++m->nr;
2030                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2031                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2032         }
2033
2034         m->guest[i].index = msr;
2035         m->guest[i].value = guest_val;
2036         m->host[i].index = msr;
2037         m->host[i].value = host_val;
2038 }
2039
2040 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2041 {
2042         u64 guest_efer = vmx->vcpu.arch.efer;
2043         u64 ignore_bits = 0;
2044
2045         if (!enable_ept) {
2046                 /*
2047                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2048                  * host CPUID is more efficient than testing guest CPUID
2049                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2050                  */
2051                 if (boot_cpu_has(X86_FEATURE_SMEP))
2052                         guest_efer |= EFER_NX;
2053                 else if (!(guest_efer & EFER_NX))
2054                         ignore_bits |= EFER_NX;
2055         }
2056
2057         /*
2058          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2059          */
2060         ignore_bits |= EFER_SCE;
2061 #ifdef CONFIG_X86_64
2062         ignore_bits |= EFER_LMA | EFER_LME;
2063         /* SCE is meaningful only in long mode on Intel */
2064         if (guest_efer & EFER_LMA)
2065                 ignore_bits &= ~(u64)EFER_SCE;
2066 #endif
2067
2068         clear_atomic_switch_msr(vmx, MSR_EFER);
2069
2070         /*
2071          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2072          * On CPUs that support "load IA32_EFER", always switch EFER
2073          * atomically, since it's faster than switching it manually.
2074          */
2075         if (cpu_has_load_ia32_efer ||
2076             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2077                 if (!(guest_efer & EFER_LMA))
2078                         guest_efer &= ~EFER_LME;
2079                 if (guest_efer != host_efer)
2080                         add_atomic_switch_msr(vmx, MSR_EFER,
2081                                               guest_efer, host_efer);
2082                 return false;
2083         } else {
2084                 guest_efer &= ~ignore_bits;
2085                 guest_efer |= host_efer & ignore_bits;
2086
2087                 vmx->guest_msrs[efer_offset].data = guest_efer;
2088                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2089
2090                 return true;
2091         }
2092 }
2093
2094 #ifdef CONFIG_X86_32
2095 /*
2096  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2097  * VMCS rather than the segment table.  KVM uses this helper to figure
2098  * out the current bases to poke them into the VMCS before entry.
2099  */
2100 static unsigned long segment_base(u16 selector)
2101 {
2102         struct desc_struct *table;
2103         unsigned long v;
2104
2105         if (!(selector & ~SEGMENT_RPL_MASK))
2106                 return 0;
2107
2108         table = get_current_gdt_ro();
2109
2110         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2111                 u16 ldt_selector = kvm_read_ldt();
2112
2113                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2114                         return 0;
2115
2116                 table = (struct desc_struct *)segment_base(ldt_selector);
2117         }
2118         v = get_desc_base(&table[selector >> 3]);
2119         return v;
2120 }
2121 #endif
2122
2123 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2124 {
2125         struct vcpu_vmx *vmx = to_vmx(vcpu);
2126         int i;
2127
2128         if (vmx->host_state.loaded)
2129                 return;
2130
2131         vmx->host_state.loaded = 1;
2132         /*
2133          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2134          * allow segment selectors with cpl > 0 or ti == 1.
2135          */
2136         vmx->host_state.ldt_sel = kvm_read_ldt();
2137         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2138         savesegment(fs, vmx->host_state.fs_sel);
2139         if (!(vmx->host_state.fs_sel & 7)) {
2140                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2141                 vmx->host_state.fs_reload_needed = 0;
2142         } else {
2143                 vmcs_write16(HOST_FS_SELECTOR, 0);
2144                 vmx->host_state.fs_reload_needed = 1;
2145         }
2146         savesegment(gs, vmx->host_state.gs_sel);
2147         if (!(vmx->host_state.gs_sel & 7))
2148                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2149         else {
2150                 vmcs_write16(HOST_GS_SELECTOR, 0);
2151                 vmx->host_state.gs_ldt_reload_needed = 1;
2152         }
2153
2154 #ifdef CONFIG_X86_64
2155         savesegment(ds, vmx->host_state.ds_sel);
2156         savesegment(es, vmx->host_state.es_sel);
2157 #endif
2158
2159 #ifdef CONFIG_X86_64
2160         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2161         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2162 #else
2163         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2164         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2165 #endif
2166
2167 #ifdef CONFIG_X86_64
2168         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2169         if (is_long_mode(&vmx->vcpu))
2170                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2171 #endif
2172         if (boot_cpu_has(X86_FEATURE_MPX))
2173                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2174         for (i = 0; i < vmx->save_nmsrs; ++i)
2175                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2176                                    vmx->guest_msrs[i].data,
2177                                    vmx->guest_msrs[i].mask);
2178 }
2179
2180 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2181 {
2182         if (!vmx->host_state.loaded)
2183                 return;
2184
2185         ++vmx->vcpu.stat.host_state_reload;
2186         vmx->host_state.loaded = 0;
2187 #ifdef CONFIG_X86_64
2188         if (is_long_mode(&vmx->vcpu))
2189                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2190 #endif
2191         if (vmx->host_state.gs_ldt_reload_needed) {
2192                 kvm_load_ldt(vmx->host_state.ldt_sel);
2193 #ifdef CONFIG_X86_64
2194                 load_gs_index(vmx->host_state.gs_sel);
2195 #else
2196                 loadsegment(gs, vmx->host_state.gs_sel);
2197 #endif
2198         }
2199         if (vmx->host_state.fs_reload_needed)
2200                 loadsegment(fs, vmx->host_state.fs_sel);
2201 #ifdef CONFIG_X86_64
2202         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2203                 loadsegment(ds, vmx->host_state.ds_sel);
2204                 loadsegment(es, vmx->host_state.es_sel);
2205         }
2206 #endif
2207         invalidate_tss_limit();
2208 #ifdef CONFIG_X86_64
2209         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2210 #endif
2211         if (vmx->host_state.msr_host_bndcfgs)
2212                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2213         load_fixmap_gdt(raw_smp_processor_id());
2214 }
2215
2216 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2217 {
2218         preempt_disable();
2219         __vmx_load_host_state(vmx);
2220         preempt_enable();
2221 }
2222
2223 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2224 {
2225         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2226         struct pi_desc old, new;
2227         unsigned int dest;
2228
2229         /*
2230          * In case of hot-plug or hot-unplug, we may have to undo
2231          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2232          * always keep PI.NDST up to date for simplicity: it makes the
2233          * code easier, and CPU migration is not a fast path.
2234          */
2235         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2236                 return;
2237
2238         /*
2239          * First handle the simple case where no cmpxchg is necessary; just
2240          * allow posting non-urgent interrupts.
2241          *
2242          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2243          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2244          * expects the VCPU to be on the blocked_vcpu_list that matches
2245          * PI.NDST.
2246          */
2247         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2248             vcpu->cpu == cpu) {
2249                 pi_clear_sn(pi_desc);
2250                 return;
2251         }
2252
2253         /* The full case.  */
2254         do {
2255                 old.control = new.control = pi_desc->control;
2256
2257                 dest = cpu_physical_id(cpu);
2258
2259                 if (x2apic_enabled())
2260                         new.ndst = dest;
2261                 else
2262                         new.ndst = (dest << 8) & 0xFF00;
2263
2264                 new.sn = 0;
2265         } while (cmpxchg64(&pi_desc->control, old.control,
2266                            new.control) != old.control);
2267 }
2268
2269 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2270 {
2271         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2272         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2273 }
2274
2275 /*
2276  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2277  * vcpu mutex is already taken.
2278  */
2279 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2280 {
2281         struct vcpu_vmx *vmx = to_vmx(vcpu);
2282         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2283
2284         if (!already_loaded) {
2285                 loaded_vmcs_clear(vmx->loaded_vmcs);
2286                 local_irq_disable();
2287                 crash_disable_local_vmclear(cpu);
2288
2289                 /*
2290                  * Read loaded_vmcs->cpu should be before fetching
2291                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2292                  * See the comments in __loaded_vmcs_clear().
2293                  */
2294                 smp_rmb();
2295
2296                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2297                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2298                 crash_enable_local_vmclear(cpu);
2299                 local_irq_enable();
2300         }
2301
2302         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2303                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2304                 vmcs_load(vmx->loaded_vmcs->vmcs);
2305                 indirect_branch_prediction_barrier();
2306         }
2307
2308         if (!already_loaded) {
2309                 void *gdt = get_current_gdt_ro();
2310                 unsigned long sysenter_esp;
2311
2312                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2313
2314                 /*
2315                  * Linux uses per-cpu TSS and GDT, so set these when switching
2316                  * processors.  See 22.2.4.
2317                  */
2318                 vmcs_writel(HOST_TR_BASE,
2319                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2320                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2321
2322                 /*
2323                  * VM exits change the host TR limit to 0x67 after a VM
2324                  * exit.  This is okay, since 0x67 covers everything except
2325                  * the IO bitmap and have have code to handle the IO bitmap
2326                  * being lost after a VM exit.
2327                  */
2328                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2329
2330                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2331                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2332
2333                 vmx->loaded_vmcs->cpu = cpu;
2334         }
2335
2336         /* Setup TSC multiplier */
2337         if (kvm_has_tsc_control &&
2338             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2339                 decache_tsc_multiplier(vmx);
2340
2341         vmx_vcpu_pi_load(vcpu, cpu);
2342         vmx->host_pkru = read_pkru();
2343         vmx->host_debugctlmsr = get_debugctlmsr();
2344 }
2345
2346 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2347 {
2348         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2349
2350         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2351                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2352                 !kvm_vcpu_apicv_active(vcpu))
2353                 return;
2354
2355         /* Set SN when the vCPU is preempted */
2356         if (vcpu->preempted)
2357                 pi_set_sn(pi_desc);
2358 }
2359
2360 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2361 {
2362         vmx_vcpu_pi_put(vcpu);
2363
2364         __vmx_load_host_state(to_vmx(vcpu));
2365 }
2366
2367 static bool emulation_required(struct kvm_vcpu *vcpu)
2368 {
2369         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2370 }
2371
2372 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2373
2374 /*
2375  * Return the cr0 value that a nested guest would read. This is a combination
2376  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2377  * its hypervisor (cr0_read_shadow).
2378  */
2379 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2380 {
2381         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2382                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2383 }
2384 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2385 {
2386         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2387                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2388 }
2389
2390 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2391 {
2392         unsigned long rflags, save_rflags;
2393
2394         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2395                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2396                 rflags = vmcs_readl(GUEST_RFLAGS);
2397                 if (to_vmx(vcpu)->rmode.vm86_active) {
2398                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2399                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2400                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2401                 }
2402                 to_vmx(vcpu)->rflags = rflags;
2403         }
2404         return to_vmx(vcpu)->rflags;
2405 }
2406
2407 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2408 {
2409         unsigned long old_rflags = vmx_get_rflags(vcpu);
2410
2411         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2412         to_vmx(vcpu)->rflags = rflags;
2413         if (to_vmx(vcpu)->rmode.vm86_active) {
2414                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2415                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2416         }
2417         vmcs_writel(GUEST_RFLAGS, rflags);
2418
2419         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2420                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2421 }
2422
2423 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2424 {
2425         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2426         int ret = 0;
2427
2428         if (interruptibility & GUEST_INTR_STATE_STI)
2429                 ret |= KVM_X86_SHADOW_INT_STI;
2430         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2431                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2432
2433         return ret;
2434 }
2435
2436 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2437 {
2438         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2439         u32 interruptibility = interruptibility_old;
2440
2441         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2442
2443         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2444                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2445         else if (mask & KVM_X86_SHADOW_INT_STI)
2446                 interruptibility |= GUEST_INTR_STATE_STI;
2447
2448         if ((interruptibility != interruptibility_old))
2449                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2450 }
2451
2452 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2453 {
2454         unsigned long rip;
2455
2456         rip = kvm_rip_read(vcpu);
2457         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2458         kvm_rip_write(vcpu, rip);
2459
2460         /* skipping an emulated instruction also counts */
2461         vmx_set_interrupt_shadow(vcpu, 0);
2462 }
2463
2464 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2465                                                unsigned long exit_qual)
2466 {
2467         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2468         unsigned int nr = vcpu->arch.exception.nr;
2469         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2470
2471         if (vcpu->arch.exception.has_error_code) {
2472                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2473                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2474         }
2475
2476         if (kvm_exception_is_soft(nr))
2477                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2478         else
2479                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2480
2481         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2482             vmx_get_nmi_mask(vcpu))
2483                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2484
2485         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2486 }
2487
2488 /*
2489  * KVM wants to inject page-faults which it got to the guest. This function
2490  * checks whether in a nested guest, we need to inject them to L1 or L2.
2491  */
2492 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2493 {
2494         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2495         unsigned int nr = vcpu->arch.exception.nr;
2496
2497         if (nr == PF_VECTOR) {
2498                 if (vcpu->arch.exception.nested_apf) {
2499                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2500                         return 1;
2501                 }
2502                 /*
2503                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2504                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2505                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2506                  * can be written only when inject_pending_event runs.  This should be
2507                  * conditional on a new capability---if the capability is disabled,
2508                  * kvm_multiple_exception would write the ancillary information to
2509                  * CR2 or DR6, for backwards ABI-compatibility.
2510                  */
2511                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2512                                                     vcpu->arch.exception.error_code)) {
2513                         *exit_qual = vcpu->arch.cr2;
2514                         return 1;
2515                 }
2516         } else {
2517                 if (vmcs12->exception_bitmap & (1u << nr)) {
2518                         if (nr == DB_VECTOR)
2519                                 *exit_qual = vcpu->arch.dr6;
2520                         else
2521                                 *exit_qual = 0;
2522                         return 1;
2523                 }
2524         }
2525
2526         return 0;
2527 }
2528
2529 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2530 {
2531         struct vcpu_vmx *vmx = to_vmx(vcpu);
2532         unsigned nr = vcpu->arch.exception.nr;
2533         bool has_error_code = vcpu->arch.exception.has_error_code;
2534         u32 error_code = vcpu->arch.exception.error_code;
2535         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2536
2537         if (has_error_code) {
2538                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2539                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2540         }
2541
2542         if (vmx->rmode.vm86_active) {
2543                 int inc_eip = 0;
2544                 if (kvm_exception_is_soft(nr))
2545                         inc_eip = vcpu->arch.event_exit_inst_len;
2546                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2547                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2548                 return;
2549         }
2550
2551         if (kvm_exception_is_soft(nr)) {
2552                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2553                              vmx->vcpu.arch.event_exit_inst_len);
2554                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2555         } else
2556                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2557
2558         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2559 }
2560
2561 static bool vmx_rdtscp_supported(void)
2562 {
2563         return cpu_has_vmx_rdtscp();
2564 }
2565
2566 static bool vmx_invpcid_supported(void)
2567 {
2568         return cpu_has_vmx_invpcid() && enable_ept;
2569 }
2570
2571 /*
2572  * Swap MSR entry in host/guest MSR entry array.
2573  */
2574 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2575 {
2576         struct shared_msr_entry tmp;
2577
2578         tmp = vmx->guest_msrs[to];
2579         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2580         vmx->guest_msrs[from] = tmp;
2581 }
2582
2583 /*
2584  * Set up the vmcs to automatically save and restore system
2585  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2586  * mode, as fiddling with msrs is very expensive.
2587  */
2588 static void setup_msrs(struct vcpu_vmx *vmx)
2589 {
2590         int save_nmsrs, index;
2591
2592         save_nmsrs = 0;
2593 #ifdef CONFIG_X86_64
2594         if (is_long_mode(&vmx->vcpu)) {
2595                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2596                 if (index >= 0)
2597                         move_msr_up(vmx, index, save_nmsrs++);
2598                 index = __find_msr_index(vmx, MSR_LSTAR);
2599                 if (index >= 0)
2600                         move_msr_up(vmx, index, save_nmsrs++);
2601                 index = __find_msr_index(vmx, MSR_CSTAR);
2602                 if (index >= 0)
2603                         move_msr_up(vmx, index, save_nmsrs++);
2604                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2605                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2606                         move_msr_up(vmx, index, save_nmsrs++);
2607                 /*
2608                  * MSR_STAR is only needed on long mode guests, and only
2609                  * if efer.sce is enabled.
2610                  */
2611                 index = __find_msr_index(vmx, MSR_STAR);
2612                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2613                         move_msr_up(vmx, index, save_nmsrs++);
2614         }
2615 #endif
2616         index = __find_msr_index(vmx, MSR_EFER);
2617         if (index >= 0 && update_transition_efer(vmx, index))
2618                 move_msr_up(vmx, index, save_nmsrs++);
2619
2620         vmx->save_nmsrs = save_nmsrs;
2621
2622         if (cpu_has_vmx_msr_bitmap())
2623                 vmx_update_msr_bitmap(&vmx->vcpu);
2624 }
2625
2626 /*
2627  * reads and returns guest's timestamp counter "register"
2628  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2629  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2630  */
2631 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2632 {
2633         u64 host_tsc, tsc_offset;
2634
2635         host_tsc = rdtsc();
2636         tsc_offset = vmcs_read64(TSC_OFFSET);
2637         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2638 }
2639
2640 /*
2641  * writes 'offset' into guest's timestamp counter offset register
2642  */
2643 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2644 {
2645         if (is_guest_mode(vcpu)) {
2646                 /*
2647                  * We're here if L1 chose not to trap WRMSR to TSC. According
2648                  * to the spec, this should set L1's TSC; The offset that L1
2649                  * set for L2 remains unchanged, and still needs to be added
2650                  * to the newly set TSC to get L2's TSC.
2651                  */
2652                 struct vmcs12 *vmcs12;
2653                 /* recalculate vmcs02.TSC_OFFSET: */
2654                 vmcs12 = get_vmcs12(vcpu);
2655                 vmcs_write64(TSC_OFFSET, offset +
2656                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2657                          vmcs12->tsc_offset : 0));
2658         } else {
2659                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2660                                            vmcs_read64(TSC_OFFSET), offset);
2661                 vmcs_write64(TSC_OFFSET, offset);
2662         }
2663 }
2664
2665 /*
2666  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2667  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2668  * all guests if the "nested" module option is off, and can also be disabled
2669  * for a single guest by disabling its VMX cpuid bit.
2670  */
2671 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2672 {
2673         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2674 }
2675
2676 /*
2677  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2678  * returned for the various VMX controls MSRs when nested VMX is enabled.
2679  * The same values should also be used to verify that vmcs12 control fields are
2680  * valid during nested entry from L1 to L2.
2681  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2682  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2683  * bit in the high half is on if the corresponding bit in the control field
2684  * may be on. See also vmx_control_verify().
2685  */
2686 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2687 {
2688         /*
2689          * Note that as a general rule, the high half of the MSRs (bits in
2690          * the control fields which may be 1) should be initialized by the
2691          * intersection of the underlying hardware's MSR (i.e., features which
2692          * can be supported) and the list of features we want to expose -
2693          * because they are known to be properly supported in our code.
2694          * Also, usually, the low half of the MSRs (bits which must be 1) can
2695          * be set to 0, meaning that L1 may turn off any of these bits. The
2696          * reason is that if one of these bits is necessary, it will appear
2697          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2698          * fields of vmcs01 and vmcs02, will turn these bits off - and
2699          * nested_vmx_exit_reflected() will not pass related exits to L1.
2700          * These rules have exceptions below.
2701          */
2702
2703         /* pin-based controls */
2704         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2705                 vmx->nested.nested_vmx_pinbased_ctls_low,
2706                 vmx->nested.nested_vmx_pinbased_ctls_high);
2707         vmx->nested.nested_vmx_pinbased_ctls_low |=
2708                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2709         vmx->nested.nested_vmx_pinbased_ctls_high &=
2710                 PIN_BASED_EXT_INTR_MASK |
2711                 PIN_BASED_NMI_EXITING |
2712                 PIN_BASED_VIRTUAL_NMIS;
2713         vmx->nested.nested_vmx_pinbased_ctls_high |=
2714                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2715                 PIN_BASED_VMX_PREEMPTION_TIMER;
2716         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2717                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2718                         PIN_BASED_POSTED_INTR;
2719
2720         /* exit controls */
2721         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2722                 vmx->nested.nested_vmx_exit_ctls_low,
2723                 vmx->nested.nested_vmx_exit_ctls_high);
2724         vmx->nested.nested_vmx_exit_ctls_low =
2725                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2726
2727         vmx->nested.nested_vmx_exit_ctls_high &=
2728 #ifdef CONFIG_X86_64
2729                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2730 #endif
2731                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2732         vmx->nested.nested_vmx_exit_ctls_high |=
2733                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2734                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2735                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2736
2737         if (kvm_mpx_supported())
2738                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2739
2740         /* We support free control of debug control saving. */
2741         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2742
2743         /* entry controls */
2744         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2745                 vmx->nested.nested_vmx_entry_ctls_low,
2746                 vmx->nested.nested_vmx_entry_ctls_high);
2747         vmx->nested.nested_vmx_entry_ctls_low =
2748                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2749         vmx->nested.nested_vmx_entry_ctls_high &=
2750 #ifdef CONFIG_X86_64
2751                 VM_ENTRY_IA32E_MODE |
2752 #endif
2753                 VM_ENTRY_LOAD_IA32_PAT;
2754         vmx->nested.nested_vmx_entry_ctls_high |=
2755                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2756         if (kvm_mpx_supported())
2757                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2758
2759         /* We support free control of debug control loading. */
2760         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2761
2762         /* cpu-based controls */
2763         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2764                 vmx->nested.nested_vmx_procbased_ctls_low,
2765                 vmx->nested.nested_vmx_procbased_ctls_high);
2766         vmx->nested.nested_vmx_procbased_ctls_low =
2767                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2768         vmx->nested.nested_vmx_procbased_ctls_high &=
2769                 CPU_BASED_VIRTUAL_INTR_PENDING |
2770                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2771                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2772                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2773                 CPU_BASED_CR3_STORE_EXITING |
2774 #ifdef CONFIG_X86_64
2775                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2776 #endif
2777                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2778                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2779                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2780                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2781                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2782         /*
2783          * We can allow some features even when not supported by the
2784          * hardware. For example, L1 can specify an MSR bitmap - and we
2785          * can use it to avoid exits to L1 - even when L0 runs L2
2786          * without MSR bitmaps.
2787          */
2788         vmx->nested.nested_vmx_procbased_ctls_high |=
2789                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2790                 CPU_BASED_USE_MSR_BITMAPS;
2791
2792         /* We support free control of CR3 access interception. */
2793         vmx->nested.nested_vmx_procbased_ctls_low &=
2794                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2795
2796         /*
2797          * secondary cpu-based controls.  Do not include those that
2798          * depend on CPUID bits, they are added later by vmx_cpuid_update.
2799          */
2800         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2801                 vmx->nested.nested_vmx_secondary_ctls_low,
2802                 vmx->nested.nested_vmx_secondary_ctls_high);
2803         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2804         vmx->nested.nested_vmx_secondary_ctls_high &=
2805                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2806                 SECONDARY_EXEC_DESC |
2807                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2808                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2809                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2810                 SECONDARY_EXEC_WBINVD_EXITING;
2811
2812         if (enable_ept) {
2813                 /* nested EPT: emulate EPT also to L1 */
2814                 vmx->nested.nested_vmx_secondary_ctls_high |=
2815                         SECONDARY_EXEC_ENABLE_EPT;
2816                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2817                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2818                 if (cpu_has_vmx_ept_execute_only())
2819                         vmx->nested.nested_vmx_ept_caps |=
2820                                 VMX_EPT_EXECUTE_ONLY_BIT;
2821                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2822                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2823                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2824                         VMX_EPT_1GB_PAGE_BIT;
2825                 if (enable_ept_ad_bits) {
2826                         vmx->nested.nested_vmx_secondary_ctls_high |=
2827                                 SECONDARY_EXEC_ENABLE_PML;
2828                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2829                 }
2830         }
2831
2832         if (cpu_has_vmx_vmfunc()) {
2833                 vmx->nested.nested_vmx_secondary_ctls_high |=
2834                         SECONDARY_EXEC_ENABLE_VMFUNC;
2835                 /*
2836                  * Advertise EPTP switching unconditionally
2837                  * since we emulate it
2838                  */
2839                 if (enable_ept)
2840                         vmx->nested.nested_vmx_vmfunc_controls =
2841                                 VMX_VMFUNC_EPTP_SWITCHING;
2842         }
2843
2844         /*
2845          * Old versions of KVM use the single-context version without
2846          * checking for support, so declare that it is supported even
2847          * though it is treated as global context.  The alternative is
2848          * not failing the single-context invvpid, and it is worse.
2849          */
2850         if (enable_vpid) {
2851                 vmx->nested.nested_vmx_secondary_ctls_high |=
2852                         SECONDARY_EXEC_ENABLE_VPID;
2853                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2854                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2855         }
2856
2857         if (enable_unrestricted_guest)
2858                 vmx->nested.nested_vmx_secondary_ctls_high |=
2859                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2860
2861         /* miscellaneous data */
2862         rdmsr(MSR_IA32_VMX_MISC,
2863                 vmx->nested.nested_vmx_misc_low,
2864                 vmx->nested.nested_vmx_misc_high);
2865         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2866         vmx->nested.nested_vmx_misc_low |=
2867                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2868                 VMX_MISC_ACTIVITY_HLT;
2869         vmx->nested.nested_vmx_misc_high = 0;
2870
2871         /*
2872          * This MSR reports some information about VMX support. We
2873          * should return information about the VMX we emulate for the
2874          * guest, and the VMCS structure we give it - not about the
2875          * VMX support of the underlying hardware.
2876          */
2877         vmx->nested.nested_vmx_basic =
2878                 VMCS12_REVISION |
2879                 VMX_BASIC_TRUE_CTLS |
2880                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2881                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2882
2883         if (cpu_has_vmx_basic_inout())
2884                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2885
2886         /*
2887          * These MSRs specify bits which the guest must keep fixed on
2888          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2889          * We picked the standard core2 setting.
2890          */
2891 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2892 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2893         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2894         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2895
2896         /* These MSRs specify bits which the guest must keep fixed off. */
2897         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2898         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2899
2900         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2901         vmx->nested.nested_vmx_vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
2902 }
2903
2904 /*
2905  * if fixed0[i] == 1: val[i] must be 1
2906  * if fixed1[i] == 0: val[i] must be 0
2907  */
2908 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2909 {
2910         return ((val & fixed1) | fixed0) == val;
2911 }
2912
2913 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2914 {
2915         return fixed_bits_valid(control, low, high);
2916 }
2917
2918 static inline u64 vmx_control_msr(u32 low, u32 high)
2919 {
2920         return low | ((u64)high << 32);
2921 }
2922
2923 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2924 {
2925         superset &= mask;
2926         subset &= mask;
2927
2928         return (superset | subset) == superset;
2929 }
2930
2931 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2932 {
2933         const u64 feature_and_reserved =
2934                 /* feature (except bit 48; see below) */
2935                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2936                 /* reserved */
2937                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2938         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2939
2940         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2941                 return -EINVAL;
2942
2943         /*
2944          * KVM does not emulate a version of VMX that constrains physical
2945          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2946          */
2947         if (data & BIT_ULL(48))
2948                 return -EINVAL;
2949
2950         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2951             vmx_basic_vmcs_revision_id(data))
2952                 return -EINVAL;
2953
2954         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2955                 return -EINVAL;
2956
2957         vmx->nested.nested_vmx_basic = data;
2958         return 0;
2959 }
2960
2961 static int
2962 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2963 {
2964         u64 supported;
2965         u32 *lowp, *highp;
2966
2967         switch (msr_index) {
2968         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2969                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2970                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2971                 break;
2972         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2973                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2974                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2975                 break;
2976         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2977                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2978                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2979                 break;
2980         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2981                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2982                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2983                 break;
2984         case MSR_IA32_VMX_PROCBASED_CTLS2:
2985                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2986                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2987                 break;
2988         default:
2989                 BUG();
2990         }
2991
2992         supported = vmx_control_msr(*lowp, *highp);
2993
2994         /* Check must-be-1 bits are still 1. */
2995         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2996                 return -EINVAL;
2997
2998         /* Check must-be-0 bits are still 0. */
2999         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3000                 return -EINVAL;
3001
3002         *lowp = data;
3003         *highp = data >> 32;
3004         return 0;
3005 }
3006
3007 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3008 {
3009         const u64 feature_and_reserved_bits =
3010                 /* feature */
3011                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3012                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3013                 /* reserved */
3014                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3015         u64 vmx_misc;
3016
3017         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3018                                    vmx->nested.nested_vmx_misc_high);
3019
3020         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3021                 return -EINVAL;
3022
3023         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3024              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3025             vmx_misc_preemption_timer_rate(data) !=
3026             vmx_misc_preemption_timer_rate(vmx_misc))
3027                 return -EINVAL;
3028
3029         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3030                 return -EINVAL;
3031
3032         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3033                 return -EINVAL;
3034
3035         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3036                 return -EINVAL;
3037
3038         vmx->nested.nested_vmx_misc_low = data;
3039         vmx->nested.nested_vmx_misc_high = data >> 32;
3040         return 0;
3041 }
3042
3043 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3044 {
3045         u64 vmx_ept_vpid_cap;
3046
3047         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3048                                            vmx->nested.nested_vmx_vpid_caps);
3049
3050         /* Every bit is either reserved or a feature bit. */
3051         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3052                 return -EINVAL;
3053
3054         vmx->nested.nested_vmx_ept_caps = data;
3055         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3056         return 0;
3057 }
3058
3059 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3060 {
3061         u64 *msr;
3062
3063         switch (msr_index) {
3064         case MSR_IA32_VMX_CR0_FIXED0:
3065                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3066                 break;
3067         case MSR_IA32_VMX_CR4_FIXED0:
3068                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3069                 break;
3070         default:
3071                 BUG();
3072         }
3073
3074         /*
3075          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3076          * must be 1 in the restored value.
3077          */
3078         if (!is_bitwise_subset(data, *msr, -1ULL))
3079                 return -EINVAL;
3080
3081         *msr = data;
3082         return 0;
3083 }
3084
3085 /*
3086  * Called when userspace is restoring VMX MSRs.
3087  *
3088  * Returns 0 on success, non-0 otherwise.
3089  */
3090 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3091 {
3092         struct vcpu_vmx *vmx = to_vmx(vcpu);
3093
3094         switch (msr_index) {
3095         case MSR_IA32_VMX_BASIC:
3096                 return vmx_restore_vmx_basic(vmx, data);
3097         case MSR_IA32_VMX_PINBASED_CTLS:
3098         case MSR_IA32_VMX_PROCBASED_CTLS:
3099         case MSR_IA32_VMX_EXIT_CTLS:
3100         case MSR_IA32_VMX_ENTRY_CTLS:
3101                 /*
3102                  * The "non-true" VMX capability MSRs are generated from the
3103                  * "true" MSRs, so we do not support restoring them directly.
3104                  *
3105                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3106                  * should restore the "true" MSRs with the must-be-1 bits
3107                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3108                  * DEFAULT SETTINGS".
3109                  */
3110                 return -EINVAL;
3111         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3112         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3113         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3114         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3115         case MSR_IA32_VMX_PROCBASED_CTLS2:
3116                 return vmx_restore_control_msr(vmx, msr_index, data);
3117         case MSR_IA32_VMX_MISC:
3118                 return vmx_restore_vmx_misc(vmx, data);
3119         case MSR_IA32_VMX_CR0_FIXED0:
3120         case MSR_IA32_VMX_CR4_FIXED0:
3121                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3122         case MSR_IA32_VMX_CR0_FIXED1:
3123         case MSR_IA32_VMX_CR4_FIXED1:
3124                 /*
3125                  * These MSRs are generated based on the vCPU's CPUID, so we
3126                  * do not support restoring them directly.
3127                  */
3128                 return -EINVAL;
3129         case MSR_IA32_VMX_EPT_VPID_CAP:
3130                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3131         case MSR_IA32_VMX_VMCS_ENUM:
3132                 vmx->nested.nested_vmx_vmcs_enum = data;
3133                 return 0;
3134         default:
3135                 /*
3136                  * The rest of the VMX capability MSRs do not support restore.
3137                  */
3138                 return -EINVAL;
3139         }
3140 }
3141
3142 /* Returns 0 on success, non-0 otherwise. */
3143 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3144 {
3145         struct vcpu_vmx *vmx = to_vmx(vcpu);
3146
3147         switch (msr_index) {
3148         case MSR_IA32_VMX_BASIC:
3149                 *pdata = vmx->nested.nested_vmx_basic;
3150                 break;
3151         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3152         case MSR_IA32_VMX_PINBASED_CTLS:
3153                 *pdata = vmx_control_msr(
3154                         vmx->nested.nested_vmx_pinbased_ctls_low,
3155                         vmx->nested.nested_vmx_pinbased_ctls_high);
3156                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3157                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3158                 break;
3159         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3160         case MSR_IA32_VMX_PROCBASED_CTLS:
3161                 *pdata = vmx_control_msr(
3162                         vmx->nested.nested_vmx_procbased_ctls_low,
3163                         vmx->nested.nested_vmx_procbased_ctls_high);
3164                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3165                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3166                 break;
3167         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3168         case MSR_IA32_VMX_EXIT_CTLS:
3169                 *pdata = vmx_control_msr(
3170                         vmx->nested.nested_vmx_exit_ctls_low,
3171                         vmx->nested.nested_vmx_exit_ctls_high);
3172                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3173                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3174                 break;
3175         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3176         case MSR_IA32_VMX_ENTRY_CTLS:
3177                 *pdata = vmx_control_msr(
3178                         vmx->nested.nested_vmx_entry_ctls_low,
3179                         vmx->nested.nested_vmx_entry_ctls_high);
3180                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3181                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3182                 break;
3183         case MSR_IA32_VMX_MISC:
3184                 *pdata = vmx_control_msr(
3185                         vmx->nested.nested_vmx_misc_low,
3186                         vmx->nested.nested_vmx_misc_high);
3187                 break;
3188         case MSR_IA32_VMX_CR0_FIXED0:
3189                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3190                 break;
3191         case MSR_IA32_VMX_CR0_FIXED1:
3192                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3193                 break;
3194         case MSR_IA32_VMX_CR4_FIXED0:
3195                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3196                 break;
3197         case MSR_IA32_VMX_CR4_FIXED1:
3198                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3199                 break;
3200         case MSR_IA32_VMX_VMCS_ENUM:
3201                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3202                 break;
3203         case MSR_IA32_VMX_PROCBASED_CTLS2:
3204                 *pdata = vmx_control_msr(
3205                         vmx->nested.nested_vmx_secondary_ctls_low,
3206                         vmx->nested.nested_vmx_secondary_ctls_high);
3207                 break;
3208         case MSR_IA32_VMX_EPT_VPID_CAP:
3209                 *pdata = vmx->nested.nested_vmx_ept_caps |
3210                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3211                 break;
3212         case MSR_IA32_VMX_VMFUNC:
3213                 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3214                 break;
3215         default:
3216                 return 1;
3217         }
3218
3219         return 0;
3220 }
3221
3222 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3223                                                  uint64_t val)
3224 {
3225         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3226
3227         return !(val & ~valid_bits);
3228 }
3229
3230 /*
3231  * Reads an msr value (of 'msr_index') into 'pdata'.
3232  * Returns 0 on success, non-0 otherwise.
3233  * Assumes vcpu_load() was already called.
3234  */
3235 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3236 {
3237         struct vcpu_vmx *vmx = to_vmx(vcpu);
3238         struct shared_msr_entry *msr;
3239
3240         switch (msr_info->index) {
3241 #ifdef CONFIG_X86_64
3242         case MSR_FS_BASE:
3243                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3244                 break;
3245         case MSR_GS_BASE:
3246                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3247                 break;
3248         case MSR_KERNEL_GS_BASE:
3249                 vmx_load_host_state(vmx);
3250                 msr_info->data = vmx->msr_guest_kernel_gs_base;
3251                 break;
3252 #endif
3253         case MSR_EFER:
3254                 return kvm_get_msr_common(vcpu, msr_info);
3255         case MSR_IA32_TSC:
3256                 msr_info->data = guest_read_tsc(vcpu);
3257                 break;
3258         case MSR_IA32_SPEC_CTRL:
3259                 if (!msr_info->host_initiated &&
3260                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3261                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3262                         return 1;
3263
3264                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3265                 break;
3266         case MSR_IA32_ARCH_CAPABILITIES:
3267                 if (!msr_info->host_initiated &&
3268                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3269                         return 1;
3270                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3271                 break;
3272         case MSR_IA32_SYSENTER_CS:
3273                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3274                 break;
3275         case MSR_IA32_SYSENTER_EIP:
3276                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3277                 break;
3278         case MSR_IA32_SYSENTER_ESP:
3279                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3280                 break;
3281         case MSR_IA32_BNDCFGS:
3282                 if (!kvm_mpx_supported() ||
3283                     (!msr_info->host_initiated &&
3284                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3285                         return 1;
3286                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3287                 break;
3288         case MSR_IA32_MCG_EXT_CTL:
3289                 if (!msr_info->host_initiated &&
3290                     !(vmx->msr_ia32_feature_control &
3291                       FEATURE_CONTROL_LMCE))
3292                         return 1;
3293                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3294                 break;
3295         case MSR_IA32_FEATURE_CONTROL:
3296                 msr_info->data = vmx->msr_ia32_feature_control;
3297                 break;
3298         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3299                 if (!nested_vmx_allowed(vcpu))
3300                         return 1;
3301                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3302         case MSR_IA32_XSS:
3303                 if (!vmx_xsaves_supported())
3304                         return 1;
3305                 msr_info->data = vcpu->arch.ia32_xss;
3306                 break;
3307         case MSR_TSC_AUX:
3308                 if (!msr_info->host_initiated &&
3309                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3310                         return 1;
3311                 /* Otherwise falls through */
3312         default:
3313                 msr = find_msr_entry(vmx, msr_info->index);
3314                 if (msr) {
3315                         msr_info->data = msr->data;
3316                         break;
3317                 }
3318                 return kvm_get_msr_common(vcpu, msr_info);
3319         }
3320
3321         return 0;
3322 }
3323
3324 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3325
3326 /*
3327  * Writes msr value into into the appropriate "register".
3328  * Returns 0 on success, non-0 otherwise.
3329  * Assumes vcpu_load() was already called.
3330  */
3331 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3332 {
3333         struct vcpu_vmx *vmx = to_vmx(vcpu);
3334         struct shared_msr_entry *msr;
3335         int ret = 0;
3336         u32 msr_index = msr_info->index;
3337         u64 data = msr_info->data;
3338
3339         switch (msr_index) {
3340         case MSR_EFER:
3341                 ret = kvm_set_msr_common(vcpu, msr_info);
3342                 break;
3343 #ifdef CONFIG_X86_64
3344         case MSR_FS_BASE:
3345                 vmx_segment_cache_clear(vmx);
3346                 vmcs_writel(GUEST_FS_BASE, data);
3347                 break;
3348         case MSR_GS_BASE:
3349                 vmx_segment_cache_clear(vmx);
3350                 vmcs_writel(GUEST_GS_BASE, data);
3351                 break;
3352         case MSR_KERNEL_GS_BASE:
3353                 vmx_load_host_state(vmx);
3354                 vmx->msr_guest_kernel_gs_base = data;
3355                 break;
3356 #endif
3357         case MSR_IA32_SYSENTER_CS:
3358                 vmcs_write32(GUEST_SYSENTER_CS, data);
3359                 break;
3360         case MSR_IA32_SYSENTER_EIP:
3361                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3362                 break;
3363         case MSR_IA32_SYSENTER_ESP:
3364                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3365                 break;
3366         case MSR_IA32_BNDCFGS:
3367                 if (!kvm_mpx_supported() ||
3368                     (!msr_info->host_initiated &&
3369                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3370                         return 1;
3371                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3372                     (data & MSR_IA32_BNDCFGS_RSVD))
3373                         return 1;
3374                 vmcs_write64(GUEST_BNDCFGS, data);
3375                 break;
3376         case MSR_IA32_TSC:
3377                 kvm_write_tsc(vcpu, msr_info);
3378                 break;
3379         case MSR_IA32_SPEC_CTRL:
3380                 if (!msr_info->host_initiated &&
3381                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3382                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3383                         return 1;
3384
3385                 /* The STIBP bit doesn't fault even if it's not advertised */
3386                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
3387                         return 1;
3388
3389                 vmx->spec_ctrl = data;
3390
3391                 if (!data)
3392                         break;
3393
3394                 /*
3395                  * For non-nested:
3396                  * When it's written (to non-zero) for the first time, pass
3397                  * it through.
3398                  *
3399                  * For nested:
3400                  * The handling of the MSR bitmap for L2 guests is done in
3401                  * nested_vmx_merge_msr_bitmap. We should not touch the
3402                  * vmcs02.msr_bitmap here since it gets completely overwritten
3403                  * in the merging. We update the vmcs01 here for L1 as well
3404                  * since it will end up touching the MSR anyway now.
3405                  */
3406                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3407                                               MSR_IA32_SPEC_CTRL,
3408                                               MSR_TYPE_RW);
3409                 break;
3410         case MSR_IA32_PRED_CMD:
3411                 if (!msr_info->host_initiated &&
3412                     !guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&
3413                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3414                         return 1;
3415
3416                 if (data & ~PRED_CMD_IBPB)
3417                         return 1;
3418
3419                 if (!data)
3420                         break;
3421
3422                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3423
3424                 /*
3425                  * For non-nested:
3426                  * When it's written (to non-zero) for the first time, pass
3427                  * it through.
3428                  *
3429                  * For nested:
3430                  * The handling of the MSR bitmap for L2 guests is done in
3431                  * nested_vmx_merge_msr_bitmap. We should not touch the
3432                  * vmcs02.msr_bitmap here since it gets completely overwritten
3433                  * in the merging.
3434                  */
3435                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3436                                               MSR_TYPE_W);
3437                 break;
3438         case MSR_IA32_ARCH_CAPABILITIES:
3439                 if (!msr_info->host_initiated)
3440                         return 1;
3441                 vmx->arch_capabilities = data;
3442                 break;
3443         case MSR_IA32_CR_PAT:
3444                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3445                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3446                                 return 1;
3447                         vmcs_write64(GUEST_IA32_PAT, data);
3448                         vcpu->arch.pat = data;
3449                         break;
3450                 }
3451                 ret = kvm_set_msr_common(vcpu, msr_info);
3452                 break;
3453         case MSR_IA32_TSC_ADJUST:
3454                 ret = kvm_set_msr_common(vcpu, msr_info);
3455                 break;
3456         case MSR_IA32_MCG_EXT_CTL:
3457                 if ((!msr_info->host_initiated &&
3458                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3459                        FEATURE_CONTROL_LMCE)) ||
3460                     (data & ~MCG_EXT_CTL_LMCE_EN))
3461                         return 1;
3462                 vcpu->arch.mcg_ext_ctl = data;
3463                 break;
3464         case MSR_IA32_FEATURE_CONTROL:
3465                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3466                     (to_vmx(vcpu)->msr_ia32_feature_control &
3467                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3468                         return 1;
3469                 vmx->msr_ia32_feature_control = data;
3470                 if (msr_info->host_initiated && data == 0)
3471                         vmx_leave_nested(vcpu);
3472                 break;
3473         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3474                 if (!msr_info->host_initiated)
3475                         return 1; /* they are read-only */
3476                 if (!nested_vmx_allowed(vcpu))
3477                         return 1;
3478                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3479         case MSR_IA32_XSS:
3480                 if (!vmx_xsaves_supported())
3481                         return 1;
3482                 /*
3483                  * The only supported bit as of Skylake is bit 8, but
3484                  * it is not supported on KVM.
3485                  */
3486                 if (data != 0)
3487                         return 1;
3488                 vcpu->arch.ia32_xss = data;
3489                 if (vcpu->arch.ia32_xss != host_xss)
3490                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3491                                 vcpu->arch.ia32_xss, host_xss);
3492                 else
3493                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3494                 break;
3495         case MSR_TSC_AUX:
3496                 if (!msr_info->host_initiated &&
3497                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3498                         return 1;
3499                 /* Check reserved bit, higher 32 bits should be zero */
3500                 if ((data >> 32) != 0)
3501                         return 1;
3502                 /* Otherwise falls through */
3503         default:
3504                 msr = find_msr_entry(vmx, msr_index);
3505                 if (msr) {
3506                         u64 old_msr_data = msr->data;
3507                         msr->data = data;
3508                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3509                                 preempt_disable();
3510                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3511                                                          msr->mask);
3512                                 preempt_enable();
3513                                 if (ret)
3514                                         msr->data = old_msr_data;
3515                         }
3516                         break;
3517                 }
3518                 ret = kvm_set_msr_common(vcpu, msr_info);
3519         }
3520
3521         return ret;
3522 }
3523
3524 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3525 {
3526         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3527         switch (reg) {
3528         case VCPU_REGS_RSP:
3529                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3530                 break;
3531         case VCPU_REGS_RIP:
3532                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3533                 break;
3534         case VCPU_EXREG_PDPTR:
3535                 if (enable_ept)
3536                         ept_save_pdptrs(vcpu);
3537                 break;
3538         default:
3539                 break;
3540         }
3541 }
3542
3543 static __init int cpu_has_kvm_support(void)
3544 {
3545         return cpu_has_vmx();
3546 }
3547
3548 static __init int vmx_disabled_by_bios(void)
3549 {
3550         u64 msr;
3551
3552         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3553         if (msr & FEATURE_CONTROL_LOCKED) {
3554                 /* launched w/ TXT and VMX disabled */
3555                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3556                         && tboot_enabled())
3557                         return 1;
3558                 /* launched w/o TXT and VMX only enabled w/ TXT */
3559                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3560                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3561                         && !tboot_enabled()) {
3562                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3563                                 "activate TXT before enabling KVM\n");
3564                         return 1;
3565                 }
3566                 /* launched w/o TXT and VMX disabled */
3567                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3568                         && !tboot_enabled())
3569                         return 1;
3570         }
3571
3572         return 0;
3573 }
3574
3575 static void kvm_cpu_vmxon(u64 addr)
3576 {
3577         cr4_set_bits(X86_CR4_VMXE);
3578         intel_pt_handle_vmx(1);
3579
3580         asm volatile (ASM_VMX_VMXON_RAX
3581                         : : "a"(&addr), "m"(addr)
3582                         : "memory", "cc");
3583 }
3584
3585 static int hardware_enable(void)
3586 {
3587         int cpu = raw_smp_processor_id();
3588         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3589         u64 old, test_bits;
3590
3591         if (cr4_read_shadow() & X86_CR4_VMXE)
3592                 return -EBUSY;
3593
3594         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3595         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3596         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3597
3598         /*
3599          * Now we can enable the vmclear operation in kdump
3600          * since the loaded_vmcss_on_cpu list on this cpu
3601          * has been initialized.
3602          *
3603          * Though the cpu is not in VMX operation now, there
3604          * is no problem to enable the vmclear operation
3605          * for the loaded_vmcss_on_cpu list is empty!
3606          */
3607         crash_enable_local_vmclear(cpu);
3608
3609         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3610
3611         test_bits = FEATURE_CONTROL_LOCKED;
3612         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3613         if (tboot_enabled())
3614                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3615
3616         if ((old & test_bits) != test_bits) {
3617                 /* enable and lock */
3618                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3619         }
3620         kvm_cpu_vmxon(phys_addr);
3621         if (enable_ept)
3622                 ept_sync_global();
3623
3624         return 0;
3625 }
3626
3627 static void vmclear_local_loaded_vmcss(void)
3628 {
3629         int cpu = raw_smp_processor_id();
3630         struct loaded_vmcs *v, *n;
3631
3632         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3633                                  loaded_vmcss_on_cpu_link)
3634                 __loaded_vmcs_clear(v);
3635 }
3636
3637
3638 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3639  * tricks.
3640  */
3641 static void kvm_cpu_vmxoff(void)
3642 {
3643         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3644
3645         intel_pt_handle_vmx(0);
3646         cr4_clear_bits(X86_CR4_VMXE);
3647 }
3648
3649 static void hardware_disable(void)
3650 {
3651         vmclear_local_loaded_vmcss();
3652         kvm_cpu_vmxoff();
3653 }
3654
3655 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3656                                       u32 msr, u32 *result)
3657 {
3658         u32 vmx_msr_low, vmx_msr_high;
3659         u32 ctl = ctl_min | ctl_opt;
3660
3661         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3662
3663         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3664         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3665
3666         /* Ensure minimum (required) set of control bits are supported. */
3667         if (ctl_min & ~ctl)
3668                 return -EIO;
3669
3670         *result = ctl;
3671         return 0;
3672 }
3673
3674 static __init bool allow_1_setting(u32 msr, u32 ctl)
3675 {
3676         u32 vmx_msr_low, vmx_msr_high;
3677
3678         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3679         return vmx_msr_high & ctl;
3680 }
3681
3682 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3683 {
3684         u32 vmx_msr_low, vmx_msr_high;
3685         u32 min, opt, min2, opt2;
3686         u32 _pin_based_exec_control = 0;
3687         u32 _cpu_based_exec_control = 0;
3688         u32 _cpu_based_2nd_exec_control = 0;
3689         u32 _vmexit_control = 0;
3690         u32 _vmentry_control = 0;
3691
3692         min = CPU_BASED_HLT_EXITING |
3693 #ifdef CONFIG_X86_64
3694               CPU_BASED_CR8_LOAD_EXITING |
3695               CPU_BASED_CR8_STORE_EXITING |
3696 #endif
3697               CPU_BASED_CR3_LOAD_EXITING |
3698               CPU_BASED_CR3_STORE_EXITING |
3699               CPU_BASED_UNCOND_IO_EXITING |
3700               CPU_BASED_MOV_DR_EXITING |
3701               CPU_BASED_USE_TSC_OFFSETING |
3702               CPU_BASED_INVLPG_EXITING |
3703               CPU_BASED_RDPMC_EXITING;
3704
3705         if (!kvm_mwait_in_guest())
3706                 min |= CPU_BASED_MWAIT_EXITING |
3707                         CPU_BASED_MONITOR_EXITING;
3708
3709         opt = CPU_BASED_TPR_SHADOW |
3710               CPU_BASED_USE_MSR_BITMAPS |
3711               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3712         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3713                                 &_cpu_based_exec_control) < 0)
3714                 return -EIO;
3715 #ifdef CONFIG_X86_64
3716         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3717                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3718                                            ~CPU_BASED_CR8_STORE_EXITING;
3719 #endif
3720         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3721                 min2 = 0;
3722                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3723                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3724                         SECONDARY_EXEC_WBINVD_EXITING |
3725                         SECONDARY_EXEC_ENABLE_VPID |
3726                         SECONDARY_EXEC_ENABLE_EPT |
3727                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3728                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3729                         SECONDARY_EXEC_DESC |
3730                         SECONDARY_EXEC_RDTSCP |
3731                         SECONDARY_EXEC_ENABLE_INVPCID |
3732                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3733                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3734                         SECONDARY_EXEC_SHADOW_VMCS |
3735                         SECONDARY_EXEC_XSAVES |
3736                         SECONDARY_EXEC_RDSEED_EXITING |
3737                         SECONDARY_EXEC_RDRAND_EXITING |
3738                         SECONDARY_EXEC_ENABLE_PML |
3739                         SECONDARY_EXEC_TSC_SCALING |
3740                         SECONDARY_EXEC_ENABLE_VMFUNC;
3741                 if (adjust_vmx_controls(min2, opt2,
3742                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3743                                         &_cpu_based_2nd_exec_control) < 0)
3744                         return -EIO;
3745         }
3746 #ifndef CONFIG_X86_64
3747         if (!(_cpu_based_2nd_exec_control &
3748                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3749                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3750 #endif
3751
3752         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3753                 _cpu_based_2nd_exec_control &= ~(
3754                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3755                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3756                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3757
3758         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
3759                 &vmx_capability.ept, &vmx_capability.vpid);
3760
3761         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3762                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3763                    enabled */
3764                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3765                                              CPU_BASED_CR3_STORE_EXITING |
3766                                              CPU_BASED_INVLPG_EXITING);
3767         } else if (vmx_capability.ept) {
3768                 vmx_capability.ept = 0;
3769                 pr_warn_once("EPT CAP should not exist if not support "
3770                                 "1-setting enable EPT VM-execution control\n");
3771         }
3772         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
3773                 vmx_capability.vpid) {
3774                 vmx_capability.vpid = 0;
3775                 pr_warn_once("VPID CAP should not exist if not support "
3776                                 "1-setting enable VPID VM-execution control\n");
3777         }
3778
3779         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3780 #ifdef CONFIG_X86_64
3781         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3782 #endif
3783         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3784                 VM_EXIT_CLEAR_BNDCFGS;
3785         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3786                                 &_vmexit_control) < 0)
3787                 return -EIO;
3788
3789         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3790         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3791                  PIN_BASED_VMX_PREEMPTION_TIMER;
3792         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3793                                 &_pin_based_exec_control) < 0)
3794                 return -EIO;
3795
3796         if (cpu_has_broken_vmx_preemption_timer())
3797                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3798         if (!(_cpu_based_2nd_exec_control &
3799                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3800                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3801
3802         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3803         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3804         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3805                                 &_vmentry_control) < 0)
3806                 return -EIO;
3807
3808         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3809
3810         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3811         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3812                 return -EIO;
3813
3814 #ifdef CONFIG_X86_64
3815         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3816         if (vmx_msr_high & (1u<<16))
3817                 return -EIO;
3818 #endif
3819
3820         /* Require Write-Back (WB) memory type for VMCS accesses. */
3821         if (((vmx_msr_high >> 18) & 15) != 6)
3822                 return -EIO;
3823
3824         vmcs_conf->size = vmx_msr_high & 0x1fff;
3825         vmcs_conf->order = get_order(vmcs_conf->size);
3826         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3827         vmcs_conf->revision_id = vmx_msr_low;
3828
3829         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3830         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3831         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3832         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3833         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3834
3835         cpu_has_load_ia32_efer =
3836                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3837                                 VM_ENTRY_LOAD_IA32_EFER)
3838                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3839                                    VM_EXIT_LOAD_IA32_EFER);
3840
3841         cpu_has_load_perf_global_ctrl =
3842                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3843                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3844                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3845                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3846
3847         /*
3848          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3849          * but due to errata below it can't be used. Workaround is to use
3850          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3851          *
3852          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3853          *
3854          * AAK155             (model 26)
3855          * AAP115             (model 30)
3856          * AAT100             (model 37)
3857          * BC86,AAY89,BD102   (model 44)
3858          * BA97               (model 46)
3859          *
3860          */
3861         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3862                 switch (boot_cpu_data.x86_model) {
3863                 case 26:
3864                 case 30:
3865                 case 37:
3866                 case 44:
3867                 case 46:
3868                         cpu_has_load_perf_global_ctrl = false;
3869                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3870                                         "does not work properly. Using workaround\n");
3871                         break;
3872                 default:
3873                         break;
3874                 }
3875         }
3876
3877         if (boot_cpu_has(X86_FEATURE_XSAVES))
3878                 rdmsrl(MSR_IA32_XSS, host_xss);
3879
3880         return 0;
3881 }
3882
3883 static struct vmcs *alloc_vmcs_cpu(int cpu)
3884 {
3885         int node = cpu_to_node(cpu);
3886         struct page *pages;
3887         struct vmcs *vmcs;
3888
3889         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3890         if (!pages)
3891                 return NULL;
3892         vmcs = page_address(pages);
3893         memset(vmcs, 0, vmcs_config.size);
3894         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3895         return vmcs;
3896 }
3897
3898 static void free_vmcs(struct vmcs *vmcs)
3899 {
3900         free_pages((unsigned long)vmcs, vmcs_config.order);
3901 }
3902
3903 /*
3904  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3905  */
3906 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3907 {
3908         if (!loaded_vmcs->vmcs)
3909                 return;
3910         loaded_vmcs_clear(loaded_vmcs);
3911         free_vmcs(loaded_vmcs->vmcs);
3912         loaded_vmcs->vmcs = NULL;
3913         if (loaded_vmcs->msr_bitmap)
3914                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
3915         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3916 }
3917
3918 static struct vmcs *alloc_vmcs(void)
3919 {
3920         return alloc_vmcs_cpu(raw_smp_processor_id());
3921 }
3922
3923 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3924 {
3925         loaded_vmcs->vmcs = alloc_vmcs();
3926         if (!loaded_vmcs->vmcs)
3927                 return -ENOMEM;
3928
3929         loaded_vmcs->shadow_vmcs = NULL;
3930         loaded_vmcs_init(loaded_vmcs);
3931
3932         if (cpu_has_vmx_msr_bitmap()) {
3933                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
3934                 if (!loaded_vmcs->msr_bitmap)
3935                         goto out_vmcs;
3936                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
3937         }
3938         return 0;
3939
3940 out_vmcs:
3941         free_loaded_vmcs(loaded_vmcs);
3942         return -ENOMEM;
3943 }
3944
3945 static void free_kvm_area(void)
3946 {
3947         int cpu;
3948
3949         for_each_possible_cpu(cpu) {
3950                 free_vmcs(per_cpu(vmxarea, cpu));
3951                 per_cpu(vmxarea, cpu) = NULL;
3952         }
3953 }
3954
3955 enum vmcs_field_width {
3956         VMCS_FIELD_WIDTH_U16 = 0,
3957         VMCS_FIELD_WIDTH_U64 = 1,
3958         VMCS_FIELD_WIDTH_U32 = 2,
3959         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
3960 };
3961
3962 static inline int vmcs_field_width(unsigned long field)
3963 {
3964         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3965                 return VMCS_FIELD_WIDTH_U32;
3966         return (field >> 13) & 0x3 ;
3967 }
3968
3969 static inline int vmcs_field_readonly(unsigned long field)
3970 {
3971         return (((field >> 10) & 0x3) == 1);
3972 }
3973
3974 static void init_vmcs_shadow_fields(void)
3975 {
3976         int i, j;
3977
3978         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
3979                 u16 field = shadow_read_only_fields[i];
3980                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
3981                     (i + 1 == max_shadow_read_only_fields ||
3982                      shadow_read_only_fields[i + 1] != field + 1))
3983                         pr_err("Missing field from shadow_read_only_field %x\n",
3984                                field + 1);
3985
3986                 clear_bit(field, vmx_vmread_bitmap);
3987 #ifdef CONFIG_X86_64
3988                 if (field & 1)
3989                         continue;
3990 #endif
3991                 if (j < i)
3992                         shadow_read_only_fields[j] = field;
3993                 j++;
3994         }
3995         max_shadow_read_only_fields = j;
3996
3997         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3998                 u16 field = shadow_read_write_fields[i];
3999                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4000                     (i + 1 == max_shadow_read_write_fields ||
4001                      shadow_read_write_fields[i + 1] != field + 1))
4002                         pr_err("Missing field from shadow_read_write_field %x\n",
4003                                field + 1);
4004
4005                 /*
4006                  * PML and the preemption timer can be emulated, but the
4007                  * processor cannot vmwrite to fields that don't exist
4008                  * on bare metal.
4009                  */
4010                 switch (field) {
4011                 case GUEST_PML_INDEX:
4012                         if (!cpu_has_vmx_pml())
4013                                 continue;
4014                         break;
4015                 case VMX_PREEMPTION_TIMER_VALUE:
4016                         if (!cpu_has_vmx_preemption_timer())
4017                                 continue;
4018                         break;
4019                 case GUEST_INTR_STATUS:
4020                         if (!cpu_has_vmx_apicv())
4021                                 continue;
4022                         break;
4023                 default:
4024                         break;
4025                 }
4026
4027                 clear_bit(field, vmx_vmwrite_bitmap);
4028                 clear_bit(field, vmx_vmread_bitmap);
4029 #ifdef CONFIG_X86_64
4030                 if (field & 1)
4031                         continue;
4032 #endif
4033                 if (j < i)
4034                         shadow_read_write_fields[j] = field;
4035                 j++;
4036         }
4037         max_shadow_read_write_fields = j;
4038 }
4039
4040 static __init int alloc_kvm_area(void)
4041 {
4042         int cpu;
4043
4044         for_each_possible_cpu(cpu) {
4045                 struct vmcs *vmcs;
4046
4047                 vmcs = alloc_vmcs_cpu(cpu);
4048                 if (!vmcs) {
4049                         free_kvm_area();
4050                         return -ENOMEM;
4051                 }
4052
4053                 per_cpu(vmxarea, cpu) = vmcs;
4054         }
4055         return 0;
4056 }
4057
4058 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4059                 struct kvm_segment *save)
4060 {
4061         if (!emulate_invalid_guest_state) {
4062                 /*
4063                  * CS and SS RPL should be equal during guest entry according
4064                  * to VMX spec, but in reality it is not always so. Since vcpu
4065                  * is in the middle of the transition from real mode to
4066                  * protected mode it is safe to assume that RPL 0 is a good
4067                  * default value.
4068                  */
4069                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4070                         save->selector &= ~SEGMENT_RPL_MASK;
4071                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4072                 save->s = 1;
4073         }
4074         vmx_set_segment(vcpu, save, seg);
4075 }
4076
4077 static void enter_pmode(struct kvm_vcpu *vcpu)
4078 {
4079         unsigned long flags;
4080         struct vcpu_vmx *vmx = to_vmx(vcpu);
4081
4082         /*
4083          * Update real mode segment cache. It may be not up-to-date if sement
4084          * register was written while vcpu was in a guest mode.
4085          */
4086         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4087         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4088         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4089         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4090         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4091         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4092
4093         vmx->rmode.vm86_active = 0;
4094
4095         vmx_segment_cache_clear(vmx);
4096
4097         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4098
4099         flags = vmcs_readl(GUEST_RFLAGS);
4100         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4101         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4102         vmcs_writel(GUEST_RFLAGS, flags);
4103
4104         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4105                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4106
4107         update_exception_bitmap(vcpu);
4108
4109         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4110         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4111         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4112         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4113         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4114         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4115 }
4116
4117 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4118 {
4119         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4120         struct kvm_segment var = *save;
4121
4122         var.dpl = 0x3;
4123         if (seg == VCPU_SREG_CS)
4124                 var.type = 0x3;
4125
4126         if (!emulate_invalid_guest_state) {
4127                 var.selector = var.base >> 4;
4128                 var.base = var.base & 0xffff0;
4129                 var.limit = 0xffff;
4130                 var.g = 0;
4131                 var.db = 0;
4132                 var.present = 1;
4133                 var.s = 1;
4134                 var.l = 0;
4135                 var.unusable = 0;
4136                 var.type = 0x3;
4137                 var.avl = 0;
4138                 if (save->base & 0xf)
4139                         printk_once(KERN_WARNING "kvm: segment base is not "
4140                                         "paragraph aligned when entering "
4141                                         "protected mode (seg=%d)", seg);
4142         }
4143
4144         vmcs_write16(sf->selector, var.selector);
4145         vmcs_writel(sf->base, var.base);
4146         vmcs_write32(sf->limit, var.limit);
4147         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4148 }
4149
4150 static void enter_rmode(struct kvm_vcpu *vcpu)
4151 {
4152         unsigned long flags;
4153         struct vcpu_vmx *vmx = to_vmx(vcpu);
4154
4155         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4156         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4157         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4158         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4159         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4160         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4161         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4162
4163         vmx->rmode.vm86_active = 1;
4164
4165         /*
4166          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4167          * vcpu. Warn the user that an update is overdue.
4168          */
4169         if (!vcpu->kvm->arch.tss_addr)
4170                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4171                              "called before entering vcpu\n");
4172
4173         vmx_segment_cache_clear(vmx);
4174
4175         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4176         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4177         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4178
4179         flags = vmcs_readl(GUEST_RFLAGS);
4180         vmx->rmode.save_rflags = flags;
4181
4182         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4183
4184         vmcs_writel(GUEST_RFLAGS, flags);
4185         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4186         update_exception_bitmap(vcpu);
4187
4188         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4189         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4190         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4191         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4192         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4193         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4194
4195         kvm_mmu_reset_context(vcpu);
4196 }
4197
4198 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4199 {
4200         struct vcpu_vmx *vmx = to_vmx(vcpu);
4201         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4202
4203         if (!msr)
4204                 return;
4205
4206         /*
4207          * Force kernel_gs_base reloading before EFER changes, as control
4208          * of this msr depends on is_long_mode().
4209          */
4210         vmx_load_host_state(to_vmx(vcpu));
4211         vcpu->arch.efer = efer;
4212         if (efer & EFER_LMA) {
4213                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4214                 msr->data = efer;
4215         } else {
4216                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4217
4218                 msr->data = efer & ~EFER_LME;
4219         }
4220         setup_msrs(vmx);
4221 }
4222
4223 #ifdef CONFIG_X86_64
4224
4225 static void enter_lmode(struct kvm_vcpu *vcpu)
4226 {
4227         u32 guest_tr_ar;
4228
4229         vmx_segment_cache_clear(to_vmx(vcpu));
4230
4231         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4232         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4233                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4234                                      __func__);
4235                 vmcs_write32(GUEST_TR_AR_BYTES,
4236                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4237                              | VMX_AR_TYPE_BUSY_64_TSS);
4238         }
4239         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4240 }
4241
4242 static void exit_lmode(struct kvm_vcpu *vcpu)
4243 {
4244         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4245         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4246 }
4247
4248 #endif
4249
4250 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4251                                 bool invalidate_gpa)
4252 {
4253         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4254                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4255                         return;
4256                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4257         } else {
4258                 vpid_sync_context(vpid);
4259         }
4260 }
4261
4262 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4263 {
4264         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4265 }
4266
4267 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4268 {
4269         if (enable_ept)
4270                 vmx_flush_tlb(vcpu, true);
4271 }
4272
4273 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4274 {
4275         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4276
4277         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4278         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4279 }
4280
4281 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4282 {
4283         if (enable_ept && is_paging(vcpu))
4284                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4285         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4286 }
4287
4288 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4289 {
4290         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4291
4292         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4293         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4294 }
4295
4296 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4297 {
4298         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4299
4300         if (!test_bit(VCPU_EXREG_PDPTR,
4301                       (unsigned long *)&vcpu->arch.regs_dirty))
4302                 return;
4303
4304         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4305                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4306                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4307                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4308                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4309         }
4310 }
4311
4312 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4313 {
4314         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4315
4316         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4317                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4318                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4319                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4320                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4321         }
4322
4323         __set_bit(VCPU_EXREG_PDPTR,
4324                   (unsigned long *)&vcpu->arch.regs_avail);
4325         __set_bit(VCPU_EXREG_PDPTR,
4326                   (unsigned long *)&vcpu->arch.regs_dirty);
4327 }
4328
4329 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4330 {
4331         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4332         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4333         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4334
4335         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4336                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4337             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4338                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4339
4340         return fixed_bits_valid(val, fixed0, fixed1);
4341 }
4342
4343 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4344 {
4345         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4346         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4347
4348         return fixed_bits_valid(val, fixed0, fixed1);
4349 }
4350
4351 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4352 {
4353         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4354         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4355
4356         return fixed_bits_valid(val, fixed0, fixed1);
4357 }
4358
4359 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4360 #define nested_guest_cr4_valid  nested_cr4_valid
4361 #define nested_host_cr4_valid   nested_cr4_valid
4362
4363 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4364
4365 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4366                                         unsigned long cr0,
4367                                         struct kvm_vcpu *vcpu)
4368 {
4369         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4370                 vmx_decache_cr3(vcpu);
4371         if (!(cr0 & X86_CR0_PG)) {
4372                 /* From paging/starting to nonpaging */
4373                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4374                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4375                              (CPU_BASED_CR3_LOAD_EXITING |
4376                               CPU_BASED_CR3_STORE_EXITING));
4377                 vcpu->arch.cr0 = cr0;
4378                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4379         } else if (!is_paging(vcpu)) {
4380                 /* From nonpaging to paging */
4381                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4382                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4383                              ~(CPU_BASED_CR3_LOAD_EXITING |
4384                                CPU_BASED_CR3_STORE_EXITING));
4385                 vcpu->arch.cr0 = cr0;
4386                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4387         }
4388
4389         if (!(cr0 & X86_CR0_WP))
4390                 *hw_cr0 &= ~X86_CR0_WP;
4391 }
4392
4393 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4394 {
4395         struct vcpu_vmx *vmx = to_vmx(vcpu);
4396         unsigned long hw_cr0;
4397
4398         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4399         if (enable_unrestricted_guest)
4400                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4401         else {
4402                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4403
4404                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4405                         enter_pmode(vcpu);
4406
4407                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4408                         enter_rmode(vcpu);
4409         }
4410
4411 #ifdef CONFIG_X86_64
4412         if (vcpu->arch.efer & EFER_LME) {
4413                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4414                         enter_lmode(vcpu);
4415                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4416                         exit_lmode(vcpu);
4417         }
4418 #endif
4419
4420         if (enable_ept)
4421                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4422
4423         vmcs_writel(CR0_READ_SHADOW, cr0);
4424         vmcs_writel(GUEST_CR0, hw_cr0);
4425         vcpu->arch.cr0 = cr0;
4426
4427         /* depends on vcpu->arch.cr0 to be set to a new value */
4428         vmx->emulation_required = emulation_required(vcpu);
4429 }
4430
4431 static int get_ept_level(struct kvm_vcpu *vcpu)
4432 {
4433         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4434                 return 5;
4435         return 4;
4436 }
4437
4438 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4439 {
4440         u64 eptp = VMX_EPTP_MT_WB;
4441
4442         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4443
4444         if (enable_ept_ad_bits &&
4445             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4446                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4447         eptp |= (root_hpa & PAGE_MASK);
4448
4449         return eptp;
4450 }
4451
4452 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4453 {
4454         unsigned long guest_cr3;
4455         u64 eptp;
4456
4457         guest_cr3 = cr3;
4458         if (enable_ept) {
4459                 eptp = construct_eptp(vcpu, cr3);
4460                 vmcs_write64(EPT_POINTER, eptp);
4461                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4462                         guest_cr3 = kvm_read_cr3(vcpu);
4463                 else
4464                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4465                 ept_load_pdptrs(vcpu);
4466         }
4467
4468         vmx_flush_tlb(vcpu, true);
4469         vmcs_writel(GUEST_CR3, guest_cr3);
4470 }
4471
4472 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4473 {
4474         /*
4475          * Pass through host's Machine Check Enable value to hw_cr4, which
4476          * is in force while we are in guest mode.  Do not let guests control
4477          * this bit, even if host CR4.MCE == 0.
4478          */
4479         unsigned long hw_cr4 =
4480                 (cr4_read_shadow() & X86_CR4_MCE) |
4481                 (cr4 & ~X86_CR4_MCE) |
4482                 (to_vmx(vcpu)->rmode.vm86_active ?
4483                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4484
4485         if ((cr4 & X86_CR4_UMIP) && !boot_cpu_has(X86_FEATURE_UMIP)) {
4486                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4487                               SECONDARY_EXEC_DESC);
4488                 hw_cr4 &= ~X86_CR4_UMIP;
4489         } else if (!is_guest_mode(vcpu) ||
4490                    !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
4491                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4492                                 SECONDARY_EXEC_DESC);
4493
4494         if (cr4 & X86_CR4_VMXE) {
4495                 /*
4496                  * To use VMXON (and later other VMX instructions), a guest
4497                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4498                  * So basically the check on whether to allow nested VMX
4499                  * is here.
4500                  */
4501                 if (!nested_vmx_allowed(vcpu))
4502                         return 1;
4503         }
4504
4505         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4506                 return 1;
4507
4508         vcpu->arch.cr4 = cr4;
4509         if (enable_ept) {
4510                 if (!is_paging(vcpu)) {
4511                         hw_cr4 &= ~X86_CR4_PAE;
4512                         hw_cr4 |= X86_CR4_PSE;
4513                 } else if (!(cr4 & X86_CR4_PAE)) {
4514                         hw_cr4 &= ~X86_CR4_PAE;
4515                 }
4516         }
4517
4518         if (!enable_unrestricted_guest && !is_paging(vcpu))
4519                 /*
4520                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4521                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4522                  * to be manually disabled when guest switches to non-paging
4523                  * mode.
4524                  *
4525                  * If !enable_unrestricted_guest, the CPU is always running
4526                  * with CR0.PG=1 and CR4 needs to be modified.
4527                  * If enable_unrestricted_guest, the CPU automatically
4528                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4529                  */
4530                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4531
4532         vmcs_writel(CR4_READ_SHADOW, cr4);
4533         vmcs_writel(GUEST_CR4, hw_cr4);
4534         return 0;
4535 }
4536
4537 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4538                             struct kvm_segment *var, int seg)
4539 {
4540         struct vcpu_vmx *vmx = to_vmx(vcpu);
4541         u32 ar;
4542
4543         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4544                 *var = vmx->rmode.segs[seg];
4545                 if (seg == VCPU_SREG_TR
4546                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4547                         return;
4548                 var->base = vmx_read_guest_seg_base(vmx, seg);
4549                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4550                 return;
4551         }
4552         var->base = vmx_read_guest_seg_base(vmx, seg);
4553         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4554         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4555         ar = vmx_read_guest_seg_ar(vmx, seg);
4556         var->unusable = (ar >> 16) & 1;
4557         var->type = ar & 15;
4558         var->s = (ar >> 4) & 1;
4559         var->dpl = (ar >> 5) & 3;
4560         /*
4561          * Some userspaces do not preserve unusable property. Since usable
4562          * segment has to be present according to VMX spec we can use present
4563          * property to amend userspace bug by making unusable segment always
4564          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4565          * segment as unusable.
4566          */
4567         var->present = !var->unusable;
4568         var->avl = (ar >> 12) & 1;
4569         var->l = (ar >> 13) & 1;
4570         var->db = (ar >> 14) & 1;
4571         var->g = (ar >> 15) & 1;
4572 }
4573
4574 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4575 {
4576         struct kvm_segment s;
4577
4578         if (to_vmx(vcpu)->rmode.vm86_active) {
4579                 vmx_get_segment(vcpu, &s, seg);
4580                 return s.base;
4581         }
4582         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4583 }
4584
4585 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4586 {
4587         struct vcpu_vmx *vmx = to_vmx(vcpu);
4588
4589         if (unlikely(vmx->rmode.vm86_active))
4590                 return 0;
4591         else {
4592                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4593                 return VMX_AR_DPL(ar);
4594         }
4595 }
4596
4597 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4598 {
4599         u32 ar;
4600
4601         if (var->unusable || !var->present)
4602                 ar = 1 << 16;
4603         else {
4604                 ar = var->type & 15;
4605                 ar |= (var->s & 1) << 4;
4606                 ar |= (var->dpl & 3) << 5;
4607                 ar |= (var->present & 1) << 7;
4608                 ar |= (var->avl & 1) << 12;
4609                 ar |= (var->l & 1) << 13;
4610                 ar |= (var->db & 1) << 14;
4611                 ar |= (var->g & 1) << 15;
4612         }
4613
4614         return ar;
4615 }
4616
4617 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4618                             struct kvm_segment *var, int seg)
4619 {
4620         struct vcpu_vmx *vmx = to_vmx(vcpu);
4621         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4622
4623         vmx_segment_cache_clear(vmx);
4624
4625         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4626                 vmx->rmode.segs[seg] = *var;
4627                 if (seg == VCPU_SREG_TR)
4628                         vmcs_write16(sf->selector, var->selector);
4629                 else if (var->s)
4630                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4631                 goto out;
4632         }
4633
4634         vmcs_writel(sf->base, var->base);
4635         vmcs_write32(sf->limit, var->limit);
4636         vmcs_write16(sf->selector, var->selector);
4637
4638         /*
4639          *   Fix the "Accessed" bit in AR field of segment registers for older
4640          * qemu binaries.
4641          *   IA32 arch specifies that at the time of processor reset the
4642          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4643          * is setting it to 0 in the userland code. This causes invalid guest
4644          * state vmexit when "unrestricted guest" mode is turned on.
4645          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4646          * tree. Newer qemu binaries with that qemu fix would not need this
4647          * kvm hack.
4648          */
4649         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4650                 var->type |= 0x1; /* Accessed */
4651
4652         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4653
4654 out:
4655         vmx->emulation_required = emulation_required(vcpu);
4656 }
4657
4658 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4659 {
4660         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4661
4662         *db = (ar >> 14) & 1;
4663         *l = (ar >> 13) & 1;
4664 }
4665
4666 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4667 {
4668         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4669         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4670 }
4671
4672 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4673 {
4674         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4675         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4676 }
4677
4678 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4679 {
4680         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4681         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4682 }
4683
4684 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4685 {
4686         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4687         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4688 }
4689
4690 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4691 {
4692         struct kvm_segment var;
4693         u32 ar;
4694
4695         vmx_get_segment(vcpu, &var, seg);
4696         var.dpl = 0x3;
4697         if (seg == VCPU_SREG_CS)
4698                 var.type = 0x3;
4699         ar = vmx_segment_access_rights(&var);
4700
4701         if (var.base != (var.selector << 4))
4702                 return false;
4703         if (var.limit != 0xffff)
4704                 return false;
4705         if (ar != 0xf3)
4706                 return false;
4707
4708         return true;
4709 }
4710
4711 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4712 {
4713         struct kvm_segment cs;
4714         unsigned int cs_rpl;
4715
4716         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4717         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4718
4719         if (cs.unusable)
4720                 return false;
4721         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4722                 return false;
4723         if (!cs.s)
4724                 return false;
4725         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4726                 if (cs.dpl > cs_rpl)
4727                         return false;
4728         } else {
4729                 if (cs.dpl != cs_rpl)
4730                         return false;
4731         }
4732         if (!cs.present)
4733                 return false;
4734
4735         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4736         return true;
4737 }
4738
4739 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4740 {
4741         struct kvm_segment ss;
4742         unsigned int ss_rpl;
4743
4744         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4745         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4746
4747         if (ss.unusable)
4748                 return true;
4749         if (ss.type != 3 && ss.type != 7)
4750                 return false;
4751         if (!ss.s)
4752                 return false;
4753         if (ss.dpl != ss_rpl) /* DPL != RPL */
4754                 return false;
4755         if (!ss.present)
4756                 return false;
4757
4758         return true;
4759 }
4760
4761 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4762 {
4763         struct kvm_segment var;
4764         unsigned int rpl;
4765
4766         vmx_get_segment(vcpu, &var, seg);
4767         rpl = var.selector & SEGMENT_RPL_MASK;
4768
4769         if (var.unusable)
4770                 return true;
4771         if (!var.s)
4772                 return false;
4773         if (!var.present)
4774                 return false;
4775         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4776                 if (var.dpl < rpl) /* DPL < RPL */
4777                         return false;
4778         }
4779
4780         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4781          * rights flags
4782          */
4783         return true;
4784 }
4785
4786 static bool tr_valid(struct kvm_vcpu *vcpu)
4787 {
4788         struct kvm_segment tr;
4789
4790         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4791
4792         if (tr.unusable)
4793                 return false;
4794         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4795                 return false;
4796         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4797                 return false;
4798         if (!tr.present)
4799                 return false;
4800
4801         return true;
4802 }
4803
4804 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4805 {
4806         struct kvm_segment ldtr;
4807
4808         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4809
4810         if (ldtr.unusable)
4811                 return true;
4812         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4813                 return false;
4814         if (ldtr.type != 2)
4815                 return false;
4816         if (!ldtr.present)
4817                 return false;
4818
4819         return true;
4820 }
4821
4822 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4823 {
4824         struct kvm_segment cs, ss;
4825
4826         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4827         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4828
4829         return ((cs.selector & SEGMENT_RPL_MASK) ==
4830                  (ss.selector & SEGMENT_RPL_MASK));
4831 }
4832
4833 /*
4834  * Check if guest state is valid. Returns true if valid, false if
4835  * not.
4836  * We assume that registers are always usable
4837  */
4838 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4839 {
4840         if (enable_unrestricted_guest)
4841                 return true;
4842
4843         /* real mode guest state checks */
4844         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4845                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4846                         return false;
4847                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4848                         return false;
4849                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4850                         return false;
4851                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4852                         return false;
4853                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4854                         return false;
4855                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4856                         return false;
4857         } else {
4858         /* protected mode guest state checks */
4859                 if (!cs_ss_rpl_check(vcpu))
4860                         return false;
4861                 if (!code_segment_valid(vcpu))
4862                         return false;
4863                 if (!stack_segment_valid(vcpu))
4864                         return false;
4865                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4866                         return false;
4867                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4868                         return false;
4869                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4870                         return false;
4871                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4872                         return false;
4873                 if (!tr_valid(vcpu))
4874                         return false;
4875                 if (!ldtr_valid(vcpu))
4876                         return false;
4877         }
4878         /* TODO:
4879          * - Add checks on RIP
4880          * - Add checks on RFLAGS
4881          */
4882
4883         return true;
4884 }
4885
4886 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4887 {
4888         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4889 }
4890
4891 static int init_rmode_tss(struct kvm *kvm)
4892 {
4893         gfn_t fn;
4894         u16 data = 0;
4895         int idx, r;
4896
4897         idx = srcu_read_lock(&kvm->srcu);
4898         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4899         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4900         if (r < 0)
4901                 goto out;
4902         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4903         r = kvm_write_guest_page(kvm, fn++, &data,
4904                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4905         if (r < 0)
4906                 goto out;
4907         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4908         if (r < 0)
4909                 goto out;
4910         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4911         if (r < 0)
4912                 goto out;
4913         data = ~0;
4914         r = kvm_write_guest_page(kvm, fn, &data,
4915                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4916                                  sizeof(u8));
4917 out:
4918         srcu_read_unlock(&kvm->srcu, idx);
4919         return r;
4920 }
4921
4922 static int init_rmode_identity_map(struct kvm *kvm)
4923 {
4924         int i, idx, r = 0;
4925         kvm_pfn_t identity_map_pfn;
4926         u32 tmp;
4927
4928         /* Protect kvm->arch.ept_identity_pagetable_done. */
4929         mutex_lock(&kvm->slots_lock);
4930
4931         if (likely(kvm->arch.ept_identity_pagetable_done))
4932                 goto out2;
4933
4934         if (!kvm->arch.ept_identity_map_addr)
4935                 kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4936         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4937
4938         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4939                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4940         if (r < 0)
4941                 goto out2;
4942
4943         idx = srcu_read_lock(&kvm->srcu);
4944         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4945         if (r < 0)
4946                 goto out;
4947         /* Set up identity-mapping pagetable for EPT in real mode */
4948         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4949                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4950                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4951                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4952                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4953                 if (r < 0)
4954                         goto out;
4955         }
4956         kvm->arch.ept_identity_pagetable_done = true;
4957
4958 out:
4959         srcu_read_unlock(&kvm->srcu, idx);
4960
4961 out2:
4962         mutex_unlock(&kvm->slots_lock);
4963         return r;
4964 }
4965
4966 static void seg_setup(int seg)
4967 {
4968         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4969         unsigned int ar;
4970
4971         vmcs_write16(sf->selector, 0);
4972         vmcs_writel(sf->base, 0);
4973         vmcs_write32(sf->limit, 0xffff);
4974         ar = 0x93;
4975         if (seg == VCPU_SREG_CS)
4976                 ar |= 0x08; /* code segment */
4977
4978         vmcs_write32(sf->ar_bytes, ar);
4979 }
4980
4981 static int alloc_apic_access_page(struct kvm *kvm)
4982 {
4983         struct page *page;
4984         int r = 0;
4985
4986         mutex_lock(&kvm->slots_lock);
4987         if (kvm->arch.apic_access_page_done)
4988                 goto out;
4989         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4990                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4991         if (r)
4992                 goto out;
4993
4994         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4995         if (is_error_page(page)) {
4996                 r = -EFAULT;
4997                 goto out;
4998         }
4999
5000         /*
5001          * Do not pin the page in memory, so that memory hot-unplug
5002          * is able to migrate it.
5003          */
5004         put_page(page);
5005         kvm->arch.apic_access_page_done = true;
5006 out:
5007         mutex_unlock(&kvm->slots_lock);
5008         return r;
5009 }
5010
5011 static int allocate_vpid(void)
5012 {
5013         int vpid;
5014
5015         if (!enable_vpid)
5016                 return 0;
5017         spin_lock(&vmx_vpid_lock);
5018         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5019         if (vpid < VMX_NR_VPIDS)
5020                 __set_bit(vpid, vmx_vpid_bitmap);
5021         else
5022                 vpid = 0;
5023         spin_unlock(&vmx_vpid_lock);
5024         return vpid;
5025 }
5026
5027 static void free_vpid(int vpid)
5028 {
5029         if (!enable_vpid || vpid == 0)
5030                 return;
5031         spin_lock(&vmx_vpid_lock);
5032         __clear_bit(vpid, vmx_vpid_bitmap);
5033         spin_unlock(&vmx_vpid_lock);
5034 }
5035
5036 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5037                                                           u32 msr, int type)
5038 {
5039         int f = sizeof(unsigned long);
5040
5041         if (!cpu_has_vmx_msr_bitmap())
5042                 return;
5043
5044         /*
5045          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5046          * have the write-low and read-high bitmap offsets the wrong way round.
5047          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5048          */
5049         if (msr <= 0x1fff) {
5050                 if (type & MSR_TYPE_R)
5051                         /* read-low */
5052                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5053
5054                 if (type & MSR_TYPE_W)
5055                         /* write-low */
5056                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5057
5058         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5059                 msr &= 0x1fff;
5060                 if (type & MSR_TYPE_R)
5061                         /* read-high */
5062                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5063
5064                 if (type & MSR_TYPE_W)
5065                         /* write-high */
5066                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5067
5068         }
5069 }
5070
5071 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5072                                                          u32 msr, int type)
5073 {
5074         int f = sizeof(unsigned long);
5075
5076         if (!cpu_has_vmx_msr_bitmap())
5077                 return;
5078
5079         /*
5080          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5081          * have the write-low and read-high bitmap offsets the wrong way round.
5082          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5083          */
5084         if (msr <= 0x1fff) {
5085                 if (type & MSR_TYPE_R)
5086                         /* read-low */
5087                         __set_bit(msr, msr_bitmap + 0x000 / f);
5088
5089                 if (type & MSR_TYPE_W)
5090                         /* write-low */
5091                         __set_bit(msr, msr_bitmap + 0x800 / f);
5092
5093         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5094                 msr &= 0x1fff;
5095                 if (type & MSR_TYPE_R)
5096                         /* read-high */
5097                         __set_bit(msr, msr_bitmap + 0x400 / f);
5098
5099                 if (type & MSR_TYPE_W)
5100                         /* write-high */
5101                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5102
5103         }
5104 }
5105
5106 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5107                                                       u32 msr, int type, bool value)
5108 {
5109         if (value)
5110                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5111         else
5112                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5113 }
5114
5115 /*
5116  * If a msr is allowed by L0, we should check whether it is allowed by L1.
5117  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5118  */
5119 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5120                                                unsigned long *msr_bitmap_nested,
5121                                                u32 msr, int type)
5122 {
5123         int f = sizeof(unsigned long);
5124
5125         /*
5126          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5127          * have the write-low and read-high bitmap offsets the wrong way round.
5128          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5129          */
5130         if (msr <= 0x1fff) {
5131                 if (type & MSR_TYPE_R &&
5132                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5133                         /* read-low */
5134                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5135
5136                 if (type & MSR_TYPE_W &&
5137                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5138                         /* write-low */
5139                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5140
5141         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5142                 msr &= 0x1fff;
5143                 if (type & MSR_TYPE_R &&
5144                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5145                         /* read-high */
5146                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5147
5148                 if (type & MSR_TYPE_W &&
5149                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5150                         /* write-high */
5151                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5152
5153         }
5154 }
5155
5156 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5157 {
5158         u8 mode = 0;
5159
5160         if (cpu_has_secondary_exec_ctrls() &&
5161             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5162              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5163                 mode |= MSR_BITMAP_MODE_X2APIC;
5164                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5165                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5166         }
5167
5168         if (is_long_mode(vcpu))
5169                 mode |= MSR_BITMAP_MODE_LM;
5170
5171         return mode;
5172 }
5173
5174 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5175
5176 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5177                                          u8 mode)
5178 {
5179         int msr;
5180
5181         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5182                 unsigned word = msr / BITS_PER_LONG;
5183                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5184                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5185         }
5186
5187         if (mode & MSR_BITMAP_MODE_X2APIC) {
5188                 /*
5189                  * TPR reads and writes can be virtualized even if virtual interrupt
5190                  * delivery is not in use.
5191                  */
5192                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5193                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5194                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5195                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5196                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5197                 }
5198         }
5199 }
5200
5201 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5202 {
5203         struct vcpu_vmx *vmx = to_vmx(vcpu);
5204         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5205         u8 mode = vmx_msr_bitmap_mode(vcpu);
5206         u8 changed = mode ^ vmx->msr_bitmap_mode;
5207
5208         if (!changed)
5209                 return;
5210
5211         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5212                                   !(mode & MSR_BITMAP_MODE_LM));
5213
5214         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5215                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5216
5217         vmx->msr_bitmap_mode = mode;
5218 }
5219
5220 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5221 {
5222         return enable_apicv;
5223 }
5224
5225 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5226 {
5227         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5228         gfn_t gfn;
5229
5230         /*
5231          * Don't need to mark the APIC access page dirty; it is never
5232          * written to by the CPU during APIC virtualization.
5233          */
5234
5235         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5236                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5237                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5238         }
5239
5240         if (nested_cpu_has_posted_intr(vmcs12)) {
5241                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5242                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5243         }
5244 }
5245
5246
5247 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5248 {
5249         struct vcpu_vmx *vmx = to_vmx(vcpu);
5250         int max_irr;
5251         void *vapic_page;
5252         u16 status;
5253
5254         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5255                 return;
5256
5257         vmx->nested.pi_pending = false;
5258         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5259                 return;
5260
5261         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5262         if (max_irr != 256) {
5263                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5264                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5265                         vapic_page, &max_irr);
5266                 kunmap(vmx->nested.virtual_apic_page);
5267
5268                 status = vmcs_read16(GUEST_INTR_STATUS);
5269                 if ((u8)max_irr > ((u8)status & 0xff)) {
5270                         status &= ~0xff;
5271                         status |= (u8)max_irr;
5272                         vmcs_write16(GUEST_INTR_STATUS, status);
5273                 }
5274         }
5275
5276         nested_mark_vmcs12_pages_dirty(vcpu);
5277 }
5278
5279 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5280                                                      bool nested)
5281 {
5282 #ifdef CONFIG_SMP
5283         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5284
5285         if (vcpu->mode == IN_GUEST_MODE) {
5286                 /*
5287                  * The vector of interrupt to be delivered to vcpu had
5288                  * been set in PIR before this function.
5289                  *
5290                  * Following cases will be reached in this block, and
5291                  * we always send a notification event in all cases as
5292                  * explained below.
5293                  *
5294                  * Case 1: vcpu keeps in non-root mode. Sending a
5295                  * notification event posts the interrupt to vcpu.
5296                  *
5297                  * Case 2: vcpu exits to root mode and is still
5298                  * runnable. PIR will be synced to vIRR before the
5299                  * next vcpu entry. Sending a notification event in
5300                  * this case has no effect, as vcpu is not in root
5301                  * mode.
5302                  *
5303                  * Case 3: vcpu exits to root mode and is blocked.
5304                  * vcpu_block() has already synced PIR to vIRR and
5305                  * never blocks vcpu if vIRR is not cleared. Therefore,
5306                  * a blocked vcpu here does not wait for any requested
5307                  * interrupts in PIR, and sending a notification event
5308                  * which has no effect is safe here.
5309                  */
5310
5311                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5312                 return true;
5313         }
5314 #endif
5315         return false;
5316 }
5317
5318 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5319                                                 int vector)
5320 {
5321         struct vcpu_vmx *vmx = to_vmx(vcpu);
5322
5323         if (is_guest_mode(vcpu) &&
5324             vector == vmx->nested.posted_intr_nv) {
5325                 /*
5326                  * If a posted intr is not recognized by hardware,
5327                  * we will accomplish it in the next vmentry.
5328                  */
5329                 vmx->nested.pi_pending = true;
5330                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5331                 /* the PIR and ON have been set by L1. */
5332                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5333                         kvm_vcpu_kick(vcpu);
5334                 return 0;
5335         }
5336         return -1;
5337 }
5338 /*
5339  * Send interrupt to vcpu via posted interrupt way.
5340  * 1. If target vcpu is running(non-root mode), send posted interrupt
5341  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5342  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5343  * interrupt from PIR in next vmentry.
5344  */
5345 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5346 {
5347         struct vcpu_vmx *vmx = to_vmx(vcpu);
5348         int r;
5349
5350         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5351         if (!r)
5352                 return;
5353
5354         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5355                 return;
5356
5357         /* If a previous notification has sent the IPI, nothing to do.  */
5358         if (pi_test_and_set_on(&vmx->pi_desc))
5359                 return;
5360
5361         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5362                 kvm_vcpu_kick(vcpu);
5363 }
5364
5365 /*
5366  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5367  * will not change in the lifetime of the guest.
5368  * Note that host-state that does change is set elsewhere. E.g., host-state
5369  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5370  */
5371 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5372 {
5373         u32 low32, high32;
5374         unsigned long tmpl;
5375         struct desc_ptr dt;
5376         unsigned long cr0, cr3, cr4;
5377
5378         cr0 = read_cr0();
5379         WARN_ON(cr0 & X86_CR0_TS);
5380         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5381
5382         /*
5383          * Save the most likely value for this task's CR3 in the VMCS.
5384          * We can't use __get_current_cr3_fast() because we're not atomic.
5385          */
5386         cr3 = __read_cr3();
5387         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5388         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5389
5390         /* Save the most likely value for this task's CR4 in the VMCS. */
5391         cr4 = cr4_read_shadow();
5392         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5393         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5394
5395         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5396 #ifdef CONFIG_X86_64
5397         /*
5398          * Load null selectors, so we can avoid reloading them in
5399          * __vmx_load_host_state(), in case userspace uses the null selectors
5400          * too (the expected case).
5401          */
5402         vmcs_write16(HOST_DS_SELECTOR, 0);
5403         vmcs_write16(HOST_ES_SELECTOR, 0);
5404 #else
5405         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5406         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5407 #endif
5408         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5409         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5410
5411         store_idt(&dt);
5412         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5413         vmx->host_idt_base = dt.address;
5414
5415         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5416
5417         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5418         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5419         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5420         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5421
5422         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5423                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5424                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5425         }
5426 }
5427
5428 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5429 {
5430         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5431         if (enable_ept)
5432                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5433         if (is_guest_mode(&vmx->vcpu))
5434                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5435                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5436         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5437 }
5438
5439 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5440 {
5441         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5442
5443         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5444                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5445
5446         if (!enable_vnmi)
5447                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5448
5449         /* Enable the preemption timer dynamically */
5450         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5451         return pin_based_exec_ctrl;
5452 }
5453
5454 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5455 {
5456         struct vcpu_vmx *vmx = to_vmx(vcpu);
5457
5458         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5459         if (cpu_has_secondary_exec_ctrls()) {
5460                 if (kvm_vcpu_apicv_active(vcpu))
5461                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5462                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5463                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5464                 else
5465                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5466                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5467                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5468         }
5469
5470         if (cpu_has_vmx_msr_bitmap())
5471                 vmx_update_msr_bitmap(vcpu);
5472 }
5473
5474 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5475 {
5476         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5477
5478         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5479                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5480
5481         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5482                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5483 #ifdef CONFIG_X86_64
5484                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5485                                 CPU_BASED_CR8_LOAD_EXITING;
5486 #endif
5487         }
5488         if (!enable_ept)
5489                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5490                                 CPU_BASED_CR3_LOAD_EXITING  |
5491                                 CPU_BASED_INVLPG_EXITING;
5492         return exec_control;
5493 }
5494
5495 static bool vmx_rdrand_supported(void)
5496 {
5497         return vmcs_config.cpu_based_2nd_exec_ctrl &
5498                 SECONDARY_EXEC_RDRAND_EXITING;
5499 }
5500
5501 static bool vmx_rdseed_supported(void)
5502 {
5503         return vmcs_config.cpu_based_2nd_exec_ctrl &
5504                 SECONDARY_EXEC_RDSEED_EXITING;
5505 }
5506
5507 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5508 {
5509         struct kvm_vcpu *vcpu = &vmx->vcpu;
5510
5511         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5512
5513         if (!cpu_need_virtualize_apic_accesses(vcpu))
5514                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5515         if (vmx->vpid == 0)
5516                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5517         if (!enable_ept) {
5518                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5519                 enable_unrestricted_guest = 0;
5520                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5521                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5522         }
5523         if (!enable_unrestricted_guest)
5524                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5525         if (!ple_gap)
5526                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5527         if (!kvm_vcpu_apicv_active(vcpu))
5528                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5529                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5530         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5531
5532         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
5533          * in vmx_set_cr4.  */
5534         exec_control &= ~SECONDARY_EXEC_DESC;
5535
5536         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5537            (handle_vmptrld).
5538            We can NOT enable shadow_vmcs here because we don't have yet
5539            a current VMCS12
5540         */
5541         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5542
5543         if (!enable_pml)
5544                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5545
5546         if (vmx_xsaves_supported()) {
5547                 /* Exposing XSAVES only when XSAVE is exposed */
5548                 bool xsaves_enabled =
5549                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5550                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5551
5552                 if (!xsaves_enabled)
5553                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5554
5555                 if (nested) {
5556                         if (xsaves_enabled)
5557                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5558                                         SECONDARY_EXEC_XSAVES;
5559                         else
5560                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5561                                         ~SECONDARY_EXEC_XSAVES;
5562                 }
5563         }
5564
5565         if (vmx_rdtscp_supported()) {
5566                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5567                 if (!rdtscp_enabled)
5568                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5569
5570                 if (nested) {
5571                         if (rdtscp_enabled)
5572                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5573                                         SECONDARY_EXEC_RDTSCP;
5574                         else
5575                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5576                                         ~SECONDARY_EXEC_RDTSCP;
5577                 }
5578         }
5579
5580         if (vmx_invpcid_supported()) {
5581                 /* Exposing INVPCID only when PCID is exposed */
5582                 bool invpcid_enabled =
5583                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5584                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5585
5586                 if (!invpcid_enabled) {
5587                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5588                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5589                 }
5590
5591                 if (nested) {
5592                         if (invpcid_enabled)
5593                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5594                                         SECONDARY_EXEC_ENABLE_INVPCID;
5595                         else
5596                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5597                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5598                 }
5599         }
5600
5601         if (vmx_rdrand_supported()) {
5602                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5603                 if (rdrand_enabled)
5604                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
5605
5606                 if (nested) {
5607                         if (rdrand_enabled)
5608                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5609                                         SECONDARY_EXEC_RDRAND_EXITING;
5610                         else
5611                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5612                                         ~SECONDARY_EXEC_RDRAND_EXITING;
5613                 }
5614         }
5615
5616         if (vmx_rdseed_supported()) {
5617                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5618                 if (rdseed_enabled)
5619                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
5620
5621                 if (nested) {
5622                         if (rdseed_enabled)
5623                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5624                                         SECONDARY_EXEC_RDSEED_EXITING;
5625                         else
5626                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5627                                         ~SECONDARY_EXEC_RDSEED_EXITING;
5628                 }
5629         }
5630
5631         vmx->secondary_exec_control = exec_control;
5632 }
5633
5634 static void ept_set_mmio_spte_mask(void)
5635 {
5636         /*
5637          * EPT Misconfigurations can be generated if the value of bits 2:0
5638          * of an EPT paging-structure entry is 110b (write/execute).
5639          */
5640         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5641                                    VMX_EPT_MISCONFIG_WX_VALUE);
5642 }
5643
5644 #define VMX_XSS_EXIT_BITMAP 0
5645 /*
5646  * Sets up the vmcs for emulated real mode.
5647  */
5648 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
5649 {
5650 #ifdef CONFIG_X86_64
5651         unsigned long a;
5652 #endif
5653         int i;
5654
5655         if (enable_shadow_vmcs) {
5656                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5657                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5658         }
5659         if (cpu_has_vmx_msr_bitmap())
5660                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
5661
5662         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5663
5664         /* Control */
5665         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5666         vmx->hv_deadline_tsc = -1;
5667
5668         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5669
5670         if (cpu_has_secondary_exec_ctrls()) {
5671                 vmx_compute_secondary_exec_control(vmx);
5672                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5673                              vmx->secondary_exec_control);
5674         }
5675
5676         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5677                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5678                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5679                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5680                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5681
5682                 vmcs_write16(GUEST_INTR_STATUS, 0);
5683
5684                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5685                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5686         }
5687
5688         if (ple_gap) {
5689                 vmcs_write32(PLE_GAP, ple_gap);
5690                 vmx->ple_window = ple_window;
5691                 vmx->ple_window_dirty = true;
5692         }
5693
5694         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5695         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5696         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5697
5698         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5699         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5700         vmx_set_constant_host_state(vmx);
5701 #ifdef CONFIG_X86_64
5702         rdmsrl(MSR_FS_BASE, a);
5703         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5704         rdmsrl(MSR_GS_BASE, a);
5705         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5706 #else
5707         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5708         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5709 #endif
5710
5711         if (cpu_has_vmx_vmfunc())
5712                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5713
5714         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5715         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5716         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5717         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5718         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5719
5720         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5721                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5722
5723         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5724                 u32 index = vmx_msr_index[i];
5725                 u32 data_low, data_high;
5726                 int j = vmx->nmsrs;
5727
5728                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5729                         continue;
5730                 if (wrmsr_safe(index, data_low, data_high) < 0)
5731                         continue;
5732                 vmx->guest_msrs[j].index = i;
5733                 vmx->guest_msrs[j].data = 0;
5734                 vmx->guest_msrs[j].mask = -1ull;
5735                 ++vmx->nmsrs;
5736         }
5737
5738         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
5739                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
5740
5741         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5742
5743         /* 22.2.1, 20.8.1 */
5744         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5745
5746         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5747         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5748
5749         set_cr4_guest_host_mask(vmx);
5750
5751         if (vmx_xsaves_supported())
5752                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5753
5754         if (enable_pml) {
5755                 ASSERT(vmx->pml_pg);
5756                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5757                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5758         }
5759 }
5760
5761 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5762 {
5763         struct vcpu_vmx *vmx = to_vmx(vcpu);
5764         struct msr_data apic_base_msr;
5765         u64 cr0;
5766
5767         vmx->rmode.vm86_active = 0;
5768         vmx->spec_ctrl = 0;
5769
5770         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5771         kvm_set_cr8(vcpu, 0);
5772
5773         if (!init_event) {
5774                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5775                                      MSR_IA32_APICBASE_ENABLE;
5776                 if (kvm_vcpu_is_reset_bsp(vcpu))
5777                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5778                 apic_base_msr.host_initiated = true;
5779                 kvm_set_apic_base(vcpu, &apic_base_msr);
5780         }
5781
5782         vmx_segment_cache_clear(vmx);
5783
5784         seg_setup(VCPU_SREG_CS);
5785         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5786         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5787
5788         seg_setup(VCPU_SREG_DS);
5789         seg_setup(VCPU_SREG_ES);
5790         seg_setup(VCPU_SREG_FS);
5791         seg_setup(VCPU_SREG_GS);
5792         seg_setup(VCPU_SREG_SS);
5793
5794         vmcs_write16(GUEST_TR_SELECTOR, 0);
5795         vmcs_writel(GUEST_TR_BASE, 0);
5796         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5797         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5798
5799         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5800         vmcs_writel(GUEST_LDTR_BASE, 0);
5801         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5802         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5803
5804         if (!init_event) {
5805                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5806                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5807                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5808                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5809         }
5810
5811         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
5812         kvm_rip_write(vcpu, 0xfff0);
5813
5814         vmcs_writel(GUEST_GDTR_BASE, 0);
5815         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5816
5817         vmcs_writel(GUEST_IDTR_BASE, 0);
5818         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5819
5820         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5821         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5822         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5823         if (kvm_mpx_supported())
5824                 vmcs_write64(GUEST_BNDCFGS, 0);
5825
5826         setup_msrs(vmx);
5827
5828         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5829
5830         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5831                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5832                 if (cpu_need_tpr_shadow(vcpu))
5833                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5834                                      __pa(vcpu->arch.apic->regs));
5835                 vmcs_write32(TPR_THRESHOLD, 0);
5836         }
5837
5838         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5839
5840         if (vmx->vpid != 0)
5841                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5842
5843         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5844         vmx->vcpu.arch.cr0 = cr0;
5845         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5846         vmx_set_cr4(vcpu, 0);
5847         vmx_set_efer(vcpu, 0);
5848
5849         update_exception_bitmap(vcpu);
5850
5851         vpid_sync_context(vmx->vpid);
5852 }
5853
5854 /*
5855  * In nested virtualization, check if L1 asked to exit on external interrupts.
5856  * For most existing hypervisors, this will always return true.
5857  */
5858 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5859 {
5860         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5861                 PIN_BASED_EXT_INTR_MASK;
5862 }
5863
5864 /*
5865  * In nested virtualization, check if L1 has set
5866  * VM_EXIT_ACK_INTR_ON_EXIT
5867  */
5868 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5869 {
5870         return get_vmcs12(vcpu)->vm_exit_controls &
5871                 VM_EXIT_ACK_INTR_ON_EXIT;
5872 }
5873
5874 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5875 {
5876         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5877                 PIN_BASED_NMI_EXITING;
5878 }
5879
5880 static void enable_irq_window(struct kvm_vcpu *vcpu)
5881 {
5882         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5883                       CPU_BASED_VIRTUAL_INTR_PENDING);
5884 }
5885
5886 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5887 {
5888         if (!enable_vnmi ||
5889             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5890                 enable_irq_window(vcpu);
5891                 return;
5892         }
5893
5894         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5895                       CPU_BASED_VIRTUAL_NMI_PENDING);
5896 }
5897
5898 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5899 {
5900         struct vcpu_vmx *vmx = to_vmx(vcpu);
5901         uint32_t intr;
5902         int irq = vcpu->arch.interrupt.nr;
5903
5904         trace_kvm_inj_virq(irq);
5905
5906         ++vcpu->stat.irq_injections;
5907         if (vmx->rmode.vm86_active) {
5908                 int inc_eip = 0;
5909                 if (vcpu->arch.interrupt.soft)
5910                         inc_eip = vcpu->arch.event_exit_inst_len;
5911                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5912                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5913                 return;
5914         }
5915         intr = irq | INTR_INFO_VALID_MASK;
5916         if (vcpu->arch.interrupt.soft) {
5917                 intr |= INTR_TYPE_SOFT_INTR;
5918                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5919                              vmx->vcpu.arch.event_exit_inst_len);
5920         } else
5921                 intr |= INTR_TYPE_EXT_INTR;
5922         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5923 }
5924
5925 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5926 {
5927         struct vcpu_vmx *vmx = to_vmx(vcpu);
5928
5929         if (!enable_vnmi) {
5930                 /*
5931                  * Tracking the NMI-blocked state in software is built upon
5932                  * finding the next open IRQ window. This, in turn, depends on
5933                  * well-behaving guests: They have to keep IRQs disabled at
5934                  * least as long as the NMI handler runs. Otherwise we may
5935                  * cause NMI nesting, maybe breaking the guest. But as this is
5936                  * highly unlikely, we can live with the residual risk.
5937                  */
5938                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
5939                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
5940         }
5941
5942         ++vcpu->stat.nmi_injections;
5943         vmx->loaded_vmcs->nmi_known_unmasked = false;
5944
5945         if (vmx->rmode.vm86_active) {
5946                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5947                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5948                 return;
5949         }
5950
5951         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5952                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5953 }
5954
5955 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5956 {
5957         struct vcpu_vmx *vmx = to_vmx(vcpu);
5958         bool masked;
5959
5960         if (!enable_vnmi)
5961                 return vmx->loaded_vmcs->soft_vnmi_blocked;
5962         if (vmx->loaded_vmcs->nmi_known_unmasked)
5963                 return false;
5964         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5965         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5966         return masked;
5967 }
5968
5969 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5970 {
5971         struct vcpu_vmx *vmx = to_vmx(vcpu);
5972
5973         if (!enable_vnmi) {
5974                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
5975                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
5976                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
5977                 }
5978         } else {
5979                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5980                 if (masked)
5981                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5982                                       GUEST_INTR_STATE_NMI);
5983                 else
5984                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5985                                         GUEST_INTR_STATE_NMI);
5986         }
5987 }
5988
5989 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5990 {
5991         if (to_vmx(vcpu)->nested.nested_run_pending)
5992                 return 0;
5993
5994         if (!enable_vnmi &&
5995             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
5996                 return 0;
5997
5998         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5999                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6000                    | GUEST_INTR_STATE_NMI));
6001 }
6002
6003 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6004 {
6005         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6006                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6007                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6008                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6009 }
6010
6011 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6012 {
6013         int ret;
6014
6015         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6016                                     PAGE_SIZE * 3);
6017         if (ret)
6018                 return ret;
6019         kvm->arch.tss_addr = addr;
6020         return init_rmode_tss(kvm);
6021 }
6022
6023 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6024 {
6025         switch (vec) {
6026         case BP_VECTOR:
6027                 /*
6028                  * Update instruction length as we may reinject the exception
6029                  * from user space while in guest debugging mode.
6030                  */
6031                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6032                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6033                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6034                         return false;
6035                 /* fall through */
6036         case DB_VECTOR:
6037                 if (vcpu->guest_debug &
6038                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6039                         return false;
6040                 /* fall through */
6041         case DE_VECTOR:
6042         case OF_VECTOR:
6043         case BR_VECTOR:
6044         case UD_VECTOR:
6045         case DF_VECTOR:
6046         case SS_VECTOR:
6047         case GP_VECTOR:
6048         case MF_VECTOR:
6049                 return true;
6050         break;
6051         }
6052         return false;
6053 }
6054
6055 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6056                                   int vec, u32 err_code)
6057 {
6058         /*
6059          * Instruction with address size override prefix opcode 0x67
6060          * Cause the #SS fault with 0 error code in VM86 mode.
6061          */
6062         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6063                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6064                         if (vcpu->arch.halt_request) {
6065                                 vcpu->arch.halt_request = 0;
6066                                 return kvm_vcpu_halt(vcpu);
6067                         }
6068                         return 1;
6069                 }
6070                 return 0;
6071         }
6072
6073         /*
6074          * Forward all other exceptions that are valid in real mode.
6075          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6076          *        the required debugging infrastructure rework.
6077          */
6078         kvm_queue_exception(vcpu, vec);
6079         return 1;
6080 }
6081
6082 /*
6083  * Trigger machine check on the host. We assume all the MSRs are already set up
6084  * by the CPU and that we still run on the same CPU as the MCE occurred on.
6085  * We pass a fake environment to the machine check handler because we want
6086  * the guest to be always treated like user space, no matter what context
6087  * it used internally.
6088  */
6089 static void kvm_machine_check(void)
6090 {
6091 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6092         struct pt_regs regs = {
6093                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6094                 .flags = X86_EFLAGS_IF,
6095         };
6096
6097         do_machine_check(&regs, 0);
6098 #endif
6099 }
6100
6101 static int handle_machine_check(struct kvm_vcpu *vcpu)
6102 {
6103         /* already handled by vcpu_run */
6104         return 1;
6105 }
6106
6107 static int handle_exception(struct kvm_vcpu *vcpu)
6108 {
6109         struct vcpu_vmx *vmx = to_vmx(vcpu);
6110         struct kvm_run *kvm_run = vcpu->run;
6111         u32 intr_info, ex_no, error_code;
6112         unsigned long cr2, rip, dr6;
6113         u32 vect_info;
6114         enum emulation_result er;
6115
6116         vect_info = vmx->idt_vectoring_info;
6117         intr_info = vmx->exit_intr_info;
6118
6119         if (is_machine_check(intr_info))
6120                 return handle_machine_check(vcpu);
6121
6122         if (is_nmi(intr_info))
6123                 return 1;  /* already handled by vmx_vcpu_run() */
6124
6125         if (is_invalid_opcode(intr_info)) {
6126                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
6127                 if (er == EMULATE_USER_EXIT)
6128                         return 0;
6129                 if (er != EMULATE_DONE)
6130                         kvm_queue_exception(vcpu, UD_VECTOR);
6131                 return 1;
6132         }
6133
6134         error_code = 0;
6135         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6136                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6137
6138         /*
6139          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6140          * MMIO, it is better to report an internal error.
6141          * See the comments in vmx_handle_exit.
6142          */
6143         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6144             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6145                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6146                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6147                 vcpu->run->internal.ndata = 3;
6148                 vcpu->run->internal.data[0] = vect_info;
6149                 vcpu->run->internal.data[1] = intr_info;
6150                 vcpu->run->internal.data[2] = error_code;
6151                 return 0;
6152         }
6153
6154         if (is_page_fault(intr_info)) {
6155                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6156                 /* EPT won't cause page fault directly */
6157                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6158                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6159         }
6160
6161         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6162
6163         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6164                 return handle_rmode_exception(vcpu, ex_no, error_code);
6165
6166         switch (ex_no) {
6167         case AC_VECTOR:
6168                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6169                 return 1;
6170         case DB_VECTOR:
6171                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6172                 if (!(vcpu->guest_debug &
6173                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6174                         vcpu->arch.dr6 &= ~15;
6175                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6176                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
6177                                 skip_emulated_instruction(vcpu);
6178
6179                         kvm_queue_exception(vcpu, DB_VECTOR);
6180                         return 1;
6181                 }
6182                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6183                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6184                 /* fall through */
6185         case BP_VECTOR:
6186                 /*
6187                  * Update instruction length as we may reinject #BP from
6188                  * user space while in guest debugging mode. Reading it for
6189                  * #DB as well causes no harm, it is not used in that case.
6190                  */
6191                 vmx->vcpu.arch.event_exit_inst_len =
6192                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6193                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6194                 rip = kvm_rip_read(vcpu);
6195                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6196                 kvm_run->debug.arch.exception = ex_no;
6197                 break;
6198         default:
6199                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6200                 kvm_run->ex.exception = ex_no;
6201                 kvm_run->ex.error_code = error_code;
6202                 break;
6203         }
6204         return 0;
6205 }
6206
6207 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6208 {
6209         ++vcpu->stat.irq_exits;
6210         return 1;
6211 }
6212
6213 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6214 {
6215         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6216         vcpu->mmio_needed = 0;
6217         return 0;
6218 }
6219
6220 static int handle_io(struct kvm_vcpu *vcpu)
6221 {
6222         unsigned long exit_qualification;
6223         int size, in, string, ret;
6224         unsigned port;
6225
6226         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6227         string = (exit_qualification & 16) != 0;
6228         in = (exit_qualification & 8) != 0;
6229
6230         ++vcpu->stat.io_exits;
6231
6232         if (string || in)
6233                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6234
6235         port = exit_qualification >> 16;
6236         size = (exit_qualification & 7) + 1;
6237
6238         ret = kvm_skip_emulated_instruction(vcpu);
6239
6240         /*
6241          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6242          * KVM_EXIT_DEBUG here.
6243          */
6244         return kvm_fast_pio_out(vcpu, size, port) && ret;
6245 }
6246
6247 static void
6248 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6249 {
6250         /*
6251          * Patch in the VMCALL instruction:
6252          */
6253         hypercall[0] = 0x0f;
6254         hypercall[1] = 0x01;
6255         hypercall[2] = 0xc1;
6256 }
6257
6258 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6259 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6260 {
6261         if (is_guest_mode(vcpu)) {
6262                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6263                 unsigned long orig_val = val;
6264
6265                 /*
6266                  * We get here when L2 changed cr0 in a way that did not change
6267                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6268                  * but did change L0 shadowed bits. So we first calculate the
6269                  * effective cr0 value that L1 would like to write into the
6270                  * hardware. It consists of the L2-owned bits from the new
6271                  * value combined with the L1-owned bits from L1's guest_cr0.
6272                  */
6273                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6274                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6275
6276                 if (!nested_guest_cr0_valid(vcpu, val))
6277                         return 1;
6278
6279                 if (kvm_set_cr0(vcpu, val))
6280                         return 1;
6281                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6282                 return 0;
6283         } else {
6284                 if (to_vmx(vcpu)->nested.vmxon &&
6285                     !nested_host_cr0_valid(vcpu, val))
6286                         return 1;
6287
6288                 return kvm_set_cr0(vcpu, val);
6289         }
6290 }
6291
6292 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6293 {
6294         if (is_guest_mode(vcpu)) {
6295                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6296                 unsigned long orig_val = val;
6297
6298                 /* analogously to handle_set_cr0 */
6299                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6300                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6301                 if (kvm_set_cr4(vcpu, val))
6302                         return 1;
6303                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6304                 return 0;
6305         } else
6306                 return kvm_set_cr4(vcpu, val);
6307 }
6308
6309 static int handle_desc(struct kvm_vcpu *vcpu)
6310 {
6311         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6312         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6313 }
6314
6315 static int handle_cr(struct kvm_vcpu *vcpu)
6316 {
6317         unsigned long exit_qualification, val;
6318         int cr;
6319         int reg;
6320         int err;
6321         int ret;
6322
6323         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6324         cr = exit_qualification & 15;
6325         reg = (exit_qualification >> 8) & 15;
6326         switch ((exit_qualification >> 4) & 3) {
6327         case 0: /* mov to cr */
6328                 val = kvm_register_readl(vcpu, reg);
6329                 trace_kvm_cr_write(cr, val);
6330                 switch (cr) {
6331                 case 0:
6332                         err = handle_set_cr0(vcpu, val);
6333                         return kvm_complete_insn_gp(vcpu, err);
6334                 case 3:
6335                         err = kvm_set_cr3(vcpu, val);
6336                         return kvm_complete_insn_gp(vcpu, err);
6337                 case 4:
6338                         err = handle_set_cr4(vcpu, val);
6339                         return kvm_complete_insn_gp(vcpu, err);
6340                 case 8: {
6341                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6342                                 u8 cr8 = (u8)val;
6343                                 err = kvm_set_cr8(vcpu, cr8);
6344                                 ret = kvm_complete_insn_gp(vcpu, err);
6345                                 if (lapic_in_kernel(vcpu))
6346                                         return ret;
6347                                 if (cr8_prev <= cr8)
6348                                         return ret;
6349                                 /*
6350                                  * TODO: we might be squashing a
6351                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6352                                  * KVM_EXIT_DEBUG here.
6353                                  */
6354                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6355                                 return 0;
6356                         }
6357                 }
6358                 break;
6359         case 2: /* clts */
6360                 WARN_ONCE(1, "Guest should always own CR0.TS");
6361                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6362                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6363                 return kvm_skip_emulated_instruction(vcpu);
6364         case 1: /*mov from cr*/
6365                 switch (cr) {
6366                 case 3:
6367                         val = kvm_read_cr3(vcpu);
6368                         kvm_register_write(vcpu, reg, val);
6369                         trace_kvm_cr_read(cr, val);
6370                         return kvm_skip_emulated_instruction(vcpu);
6371                 case 8:
6372                         val = kvm_get_cr8(vcpu);
6373                         kvm_register_write(vcpu, reg, val);
6374                         trace_kvm_cr_read(cr, val);
6375                         return kvm_skip_emulated_instruction(vcpu);
6376                 }
6377                 break;
6378         case 3: /* lmsw */
6379                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6380                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6381                 kvm_lmsw(vcpu, val);
6382
6383                 return kvm_skip_emulated_instruction(vcpu);
6384         default:
6385                 break;
6386         }
6387         vcpu->run->exit_reason = 0;
6388         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6389                (int)(exit_qualification >> 4) & 3, cr);
6390         return 0;
6391 }
6392
6393 static int handle_dr(struct kvm_vcpu *vcpu)
6394 {
6395         unsigned long exit_qualification;
6396         int dr, dr7, reg;
6397
6398         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6399         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6400
6401         /* First, if DR does not exist, trigger UD */
6402         if (!kvm_require_dr(vcpu, dr))
6403                 return 1;
6404
6405         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6406         if (!kvm_require_cpl(vcpu, 0))
6407                 return 1;
6408         dr7 = vmcs_readl(GUEST_DR7);
6409         if (dr7 & DR7_GD) {
6410                 /*
6411                  * As the vm-exit takes precedence over the debug trap, we
6412                  * need to emulate the latter, either for the host or the
6413                  * guest debugging itself.
6414                  */
6415                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6416                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6417                         vcpu->run->debug.arch.dr7 = dr7;
6418                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6419                         vcpu->run->debug.arch.exception = DB_VECTOR;
6420                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6421                         return 0;
6422                 } else {
6423                         vcpu->arch.dr6 &= ~15;
6424                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6425                         kvm_queue_exception(vcpu, DB_VECTOR);
6426                         return 1;
6427                 }
6428         }
6429
6430         if (vcpu->guest_debug == 0) {
6431                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6432                                 CPU_BASED_MOV_DR_EXITING);
6433
6434                 /*
6435                  * No more DR vmexits; force a reload of the debug registers
6436                  * and reenter on this instruction.  The next vmexit will
6437                  * retrieve the full state of the debug registers.
6438                  */
6439                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6440                 return 1;
6441         }
6442
6443         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6444         if (exit_qualification & TYPE_MOV_FROM_DR) {
6445                 unsigned long val;
6446
6447                 if (kvm_get_dr(vcpu, dr, &val))
6448                         return 1;
6449                 kvm_register_write(vcpu, reg, val);
6450         } else
6451                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6452                         return 1;
6453
6454         return kvm_skip_emulated_instruction(vcpu);
6455 }
6456
6457 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6458 {
6459         return vcpu->arch.dr6;
6460 }
6461
6462 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6463 {
6464 }
6465
6466 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6467 {
6468         get_debugreg(vcpu->arch.db[0], 0);
6469         get_debugreg(vcpu->arch.db[1], 1);
6470         get_debugreg(vcpu->arch.db[2], 2);
6471         get_debugreg(vcpu->arch.db[3], 3);
6472         get_debugreg(vcpu->arch.dr6, 6);
6473         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6474
6475         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6476         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6477 }
6478
6479 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6480 {
6481         vmcs_writel(GUEST_DR7, val);
6482 }
6483
6484 static int handle_cpuid(struct kvm_vcpu *vcpu)
6485 {
6486         return kvm_emulate_cpuid(vcpu);
6487 }
6488
6489 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6490 {
6491         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6492         struct msr_data msr_info;
6493
6494         msr_info.index = ecx;
6495         msr_info.host_initiated = false;
6496         if (vmx_get_msr(vcpu, &msr_info)) {
6497                 trace_kvm_msr_read_ex(ecx);
6498                 kvm_inject_gp(vcpu, 0);
6499                 return 1;
6500         }
6501
6502         trace_kvm_msr_read(ecx, msr_info.data);
6503
6504         /* FIXME: handling of bits 32:63 of rax, rdx */
6505         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6506         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6507         return kvm_skip_emulated_instruction(vcpu);
6508 }
6509
6510 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6511 {
6512         struct msr_data msr;
6513         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6514         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6515                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6516
6517         msr.data = data;
6518         msr.index = ecx;
6519         msr.host_initiated = false;
6520         if (kvm_set_msr(vcpu, &msr) != 0) {
6521                 trace_kvm_msr_write_ex(ecx, data);
6522                 kvm_inject_gp(vcpu, 0);
6523                 return 1;
6524         }
6525
6526         trace_kvm_msr_write(ecx, data);
6527         return kvm_skip_emulated_instruction(vcpu);
6528 }
6529
6530 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6531 {
6532         kvm_apic_update_ppr(vcpu);
6533         return 1;
6534 }
6535
6536 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6537 {
6538         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6539                         CPU_BASED_VIRTUAL_INTR_PENDING);
6540
6541         kvm_make_request(KVM_REQ_EVENT, vcpu);
6542
6543         ++vcpu->stat.irq_window_exits;
6544         return 1;
6545 }
6546
6547 static int handle_halt(struct kvm_vcpu *vcpu)
6548 {
6549         return kvm_emulate_halt(vcpu);
6550 }
6551
6552 static int handle_vmcall(struct kvm_vcpu *vcpu)
6553 {
6554         return kvm_emulate_hypercall(vcpu);
6555 }
6556
6557 static int handle_invd(struct kvm_vcpu *vcpu)
6558 {
6559         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6560 }
6561
6562 static int handle_invlpg(struct kvm_vcpu *vcpu)
6563 {
6564         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6565
6566         kvm_mmu_invlpg(vcpu, exit_qualification);
6567         return kvm_skip_emulated_instruction(vcpu);
6568 }
6569
6570 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6571 {
6572         int err;
6573
6574         err = kvm_rdpmc(vcpu);
6575         return kvm_complete_insn_gp(vcpu, err);
6576 }
6577
6578 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6579 {
6580         return kvm_emulate_wbinvd(vcpu);
6581 }
6582
6583 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6584 {
6585         u64 new_bv = kvm_read_edx_eax(vcpu);
6586         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6587
6588         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6589                 return kvm_skip_emulated_instruction(vcpu);
6590         return 1;
6591 }
6592
6593 static int handle_xsaves(struct kvm_vcpu *vcpu)
6594 {
6595         kvm_skip_emulated_instruction(vcpu);
6596         WARN(1, "this should never happen\n");
6597         return 1;
6598 }
6599
6600 static int handle_xrstors(struct kvm_vcpu *vcpu)
6601 {
6602         kvm_skip_emulated_instruction(vcpu);
6603         WARN(1, "this should never happen\n");
6604         return 1;
6605 }
6606
6607 static int handle_apic_access(struct kvm_vcpu *vcpu)
6608 {
6609         if (likely(fasteoi)) {
6610                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6611                 int access_type, offset;
6612
6613                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6614                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6615                 /*
6616                  * Sane guest uses MOV to write EOI, with written value
6617                  * not cared. So make a short-circuit here by avoiding
6618                  * heavy instruction emulation.
6619                  */
6620                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6621                     (offset == APIC_EOI)) {
6622                         kvm_lapic_set_eoi(vcpu);
6623                         return kvm_skip_emulated_instruction(vcpu);
6624                 }
6625         }
6626         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6627 }
6628
6629 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6630 {
6631         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6632         int vector = exit_qualification & 0xff;
6633
6634         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6635         kvm_apic_set_eoi_accelerated(vcpu, vector);
6636         return 1;
6637 }
6638
6639 static int handle_apic_write(struct kvm_vcpu *vcpu)
6640 {
6641         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6642         u32 offset = exit_qualification & 0xfff;
6643
6644         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6645         kvm_apic_write_nodecode(vcpu, offset);
6646         return 1;
6647 }
6648
6649 static int handle_task_switch(struct kvm_vcpu *vcpu)
6650 {
6651         struct vcpu_vmx *vmx = to_vmx(vcpu);
6652         unsigned long exit_qualification;
6653         bool has_error_code = false;
6654         u32 error_code = 0;
6655         u16 tss_selector;
6656         int reason, type, idt_v, idt_index;
6657
6658         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6659         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6660         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6661
6662         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6663
6664         reason = (u32)exit_qualification >> 30;
6665         if (reason == TASK_SWITCH_GATE && idt_v) {
6666                 switch (type) {
6667                 case INTR_TYPE_NMI_INTR:
6668                         vcpu->arch.nmi_injected = false;
6669                         vmx_set_nmi_mask(vcpu, true);
6670                         break;
6671                 case INTR_TYPE_EXT_INTR:
6672                 case INTR_TYPE_SOFT_INTR:
6673                         kvm_clear_interrupt_queue(vcpu);
6674                         break;
6675                 case INTR_TYPE_HARD_EXCEPTION:
6676                         if (vmx->idt_vectoring_info &
6677                             VECTORING_INFO_DELIVER_CODE_MASK) {
6678                                 has_error_code = true;
6679                                 error_code =
6680                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6681                         }
6682                         /* fall through */
6683                 case INTR_TYPE_SOFT_EXCEPTION:
6684                         kvm_clear_exception_queue(vcpu);
6685                         break;
6686                 default:
6687                         break;
6688                 }
6689         }
6690         tss_selector = exit_qualification;
6691
6692         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6693                        type != INTR_TYPE_EXT_INTR &&
6694                        type != INTR_TYPE_NMI_INTR))
6695                 skip_emulated_instruction(vcpu);
6696
6697         if (kvm_task_switch(vcpu, tss_selector,
6698                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6699                             has_error_code, error_code) == EMULATE_FAIL) {
6700                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6701                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6702                 vcpu->run->internal.ndata = 0;
6703                 return 0;
6704         }
6705
6706         /*
6707          * TODO: What about debug traps on tss switch?
6708          *       Are we supposed to inject them and update dr6?
6709          */
6710
6711         return 1;
6712 }
6713
6714 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6715 {
6716         unsigned long exit_qualification;
6717         gpa_t gpa;
6718         u64 error_code;
6719
6720         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6721
6722         /*
6723          * EPT violation happened while executing iret from NMI,
6724          * "blocked by NMI" bit has to be set before next VM entry.
6725          * There are errata that may cause this bit to not be set:
6726          * AAK134, BY25.
6727          */
6728         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6729                         enable_vnmi &&
6730                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6731                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6732
6733         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6734         trace_kvm_page_fault(gpa, exit_qualification);
6735
6736         /* Is it a read fault? */
6737         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6738                      ? PFERR_USER_MASK : 0;
6739         /* Is it a write fault? */
6740         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6741                       ? PFERR_WRITE_MASK : 0;
6742         /* Is it a fetch fault? */
6743         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6744                       ? PFERR_FETCH_MASK : 0;
6745         /* ept page table entry is present? */
6746         error_code |= (exit_qualification &
6747                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6748                         EPT_VIOLATION_EXECUTABLE))
6749                       ? PFERR_PRESENT_MASK : 0;
6750
6751         error_code |= (exit_qualification & 0x100) != 0 ?
6752                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6753
6754         vcpu->arch.exit_qualification = exit_qualification;
6755         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6756 }
6757
6758 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6759 {
6760         int ret;
6761         gpa_t gpa;
6762
6763         /*
6764          * A nested guest cannot optimize MMIO vmexits, because we have an
6765          * nGPA here instead of the required GPA.
6766          */
6767         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6768         if (!is_guest_mode(vcpu) &&
6769             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6770                 trace_kvm_fast_mmio(gpa);
6771                 /*
6772                  * Doing kvm_skip_emulated_instruction() depends on undefined
6773                  * behavior: Intel's manual doesn't mandate
6774                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
6775                  * occurs and while on real hardware it was observed to be set,
6776                  * other hypervisors (namely Hyper-V) don't set it, we end up
6777                  * advancing IP with some random value. Disable fast mmio when
6778                  * running nested and keep it for real hardware in hope that
6779                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
6780                  */
6781                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
6782                         return kvm_skip_emulated_instruction(vcpu);
6783                 else
6784                         return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
6785                                                        NULL, 0) == EMULATE_DONE;
6786         }
6787
6788         ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6789         if (ret >= 0)
6790                 return ret;
6791
6792         /* It is the real ept misconfig */
6793         WARN_ON(1);
6794
6795         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6796         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6797
6798         return 0;
6799 }
6800
6801 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6802 {
6803         WARN_ON_ONCE(!enable_vnmi);
6804         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6805                         CPU_BASED_VIRTUAL_NMI_PENDING);
6806         ++vcpu->stat.nmi_window_exits;
6807         kvm_make_request(KVM_REQ_EVENT, vcpu);
6808
6809         return 1;
6810 }
6811
6812 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6813 {
6814         struct vcpu_vmx *vmx = to_vmx(vcpu);
6815         enum emulation_result err = EMULATE_DONE;
6816         int ret = 1;
6817         u32 cpu_exec_ctrl;
6818         bool intr_window_requested;
6819         unsigned count = 130;
6820
6821         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6822         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6823
6824         while (vmx->emulation_required && count-- != 0) {
6825                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6826                         return handle_interrupt_window(&vmx->vcpu);
6827
6828                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6829                         return 1;
6830
6831                 err = emulate_instruction(vcpu, 0);
6832
6833                 if (err == EMULATE_USER_EXIT) {
6834                         ++vcpu->stat.mmio_exits;
6835                         ret = 0;
6836                         goto out;
6837                 }
6838
6839                 if (err != EMULATE_DONE) {
6840                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6841                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6842                         vcpu->run->internal.ndata = 0;
6843                         return 0;
6844                 }
6845
6846                 if (vcpu->arch.halt_request) {
6847                         vcpu->arch.halt_request = 0;
6848                         ret = kvm_vcpu_halt(vcpu);
6849                         goto out;
6850                 }
6851
6852                 if (signal_pending(current))
6853                         goto out;
6854                 if (need_resched())
6855                         schedule();
6856         }
6857
6858 out:
6859         return ret;
6860 }
6861
6862 static int __grow_ple_window(int val)
6863 {
6864         if (ple_window_grow < 1)
6865                 return ple_window;
6866
6867         val = min(val, ple_window_actual_max);
6868
6869         if (ple_window_grow < ple_window)
6870                 val *= ple_window_grow;
6871         else
6872                 val += ple_window_grow;
6873
6874         return val;
6875 }
6876
6877 static int __shrink_ple_window(int val, int modifier, int minimum)
6878 {
6879         if (modifier < 1)
6880                 return ple_window;
6881
6882         if (modifier < ple_window)
6883                 val /= modifier;
6884         else
6885                 val -= modifier;
6886
6887         return max(val, minimum);
6888 }
6889
6890 static void grow_ple_window(struct kvm_vcpu *vcpu)
6891 {
6892         struct vcpu_vmx *vmx = to_vmx(vcpu);
6893         int old = vmx->ple_window;
6894
6895         vmx->ple_window = __grow_ple_window(old);
6896
6897         if (vmx->ple_window != old)
6898                 vmx->ple_window_dirty = true;
6899
6900         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6901 }
6902
6903 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6904 {
6905         struct vcpu_vmx *vmx = to_vmx(vcpu);
6906         int old = vmx->ple_window;
6907
6908         vmx->ple_window = __shrink_ple_window(old,
6909                                               ple_window_shrink, ple_window);
6910
6911         if (vmx->ple_window != old)
6912                 vmx->ple_window_dirty = true;
6913
6914         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6915 }
6916
6917 /*
6918  * ple_window_actual_max is computed to be one grow_ple_window() below
6919  * ple_window_max. (See __grow_ple_window for the reason.)
6920  * This prevents overflows, because ple_window_max is int.
6921  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6922  * this process.
6923  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6924  */
6925 static void update_ple_window_actual_max(void)
6926 {
6927         ple_window_actual_max =
6928                         __shrink_ple_window(max(ple_window_max, ple_window),
6929                                             ple_window_grow, INT_MIN);
6930 }
6931
6932 /*
6933  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6934  */
6935 static void wakeup_handler(void)
6936 {
6937         struct kvm_vcpu *vcpu;
6938         int cpu = smp_processor_id();
6939
6940         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6941         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6942                         blocked_vcpu_list) {
6943                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6944
6945                 if (pi_test_on(pi_desc) == 1)
6946                         kvm_vcpu_kick(vcpu);
6947         }
6948         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6949 }
6950
6951 void vmx_enable_tdp(void)
6952 {
6953         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6954                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6955                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6956                 0ull, VMX_EPT_EXECUTABLE_MASK,
6957                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6958                 VMX_EPT_RWX_MASK, 0ull);
6959
6960         ept_set_mmio_spte_mask();
6961         kvm_enable_tdp();
6962 }
6963
6964 static __init int hardware_setup(void)
6965 {
6966         int r = -ENOMEM, i;
6967
6968         rdmsrl_safe(MSR_EFER, &host_efer);
6969
6970         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6971                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6972
6973         for (i = 0; i < VMX_BITMAP_NR; i++) {
6974                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6975                 if (!vmx_bitmap[i])
6976                         goto out;
6977         }
6978
6979         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6980         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6981
6982         if (setup_vmcs_config(&vmcs_config) < 0) {
6983                 r = -EIO;
6984                 goto out;
6985         }
6986
6987         if (boot_cpu_has(X86_FEATURE_NX))
6988                 kvm_enable_efer_bits(EFER_NX);
6989
6990         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6991                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6992                 enable_vpid = 0;
6993
6994         if (!cpu_has_vmx_ept() ||
6995             !cpu_has_vmx_ept_4levels() ||
6996             !cpu_has_vmx_ept_mt_wb() ||
6997             !cpu_has_vmx_invept_global())
6998                 enable_ept = 0;
6999
7000         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7001                 enable_ept_ad_bits = 0;
7002
7003         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7004                 enable_unrestricted_guest = 0;
7005
7006         if (!cpu_has_vmx_flexpriority())
7007                 flexpriority_enabled = 0;
7008
7009         if (!cpu_has_virtual_nmis())
7010                 enable_vnmi = 0;
7011
7012         /*
7013          * set_apic_access_page_addr() is used to reload apic access
7014          * page upon invalidation.  No need to do anything if not
7015          * using the APIC_ACCESS_ADDR VMCS field.
7016          */
7017         if (!flexpriority_enabled)
7018                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7019
7020         if (!cpu_has_vmx_tpr_shadow())
7021                 kvm_x86_ops->update_cr8_intercept = NULL;
7022
7023         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7024                 kvm_disable_largepages();
7025
7026         if (!cpu_has_vmx_ple()) {
7027                 ple_gap = 0;
7028                 ple_window = 0;
7029                 ple_window_grow = 0;
7030                 ple_window_max = 0;
7031                 ple_window_shrink = 0;
7032         }
7033
7034         if (!cpu_has_vmx_apicv()) {
7035                 enable_apicv = 0;
7036                 kvm_x86_ops->sync_pir_to_irr = NULL;
7037         }
7038
7039         if (cpu_has_vmx_tsc_scaling()) {
7040                 kvm_has_tsc_control = true;
7041                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7042                 kvm_tsc_scaling_ratio_frac_bits = 48;
7043         }
7044
7045         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7046
7047         if (enable_ept)
7048                 vmx_enable_tdp();
7049         else
7050                 kvm_disable_tdp();
7051
7052         update_ple_window_actual_max();
7053
7054         /*
7055          * Only enable PML when hardware supports PML feature, and both EPT
7056          * and EPT A/D bit features are enabled -- PML depends on them to work.
7057          */
7058         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7059                 enable_pml = 0;
7060
7061         if (!enable_pml) {
7062                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7063                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7064                 kvm_x86_ops->flush_log_dirty = NULL;
7065                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7066         }
7067
7068         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7069                 u64 vmx_msr;
7070
7071                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7072                 cpu_preemption_timer_multi =
7073                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7074         } else {
7075                 kvm_x86_ops->set_hv_timer = NULL;
7076                 kvm_x86_ops->cancel_hv_timer = NULL;
7077         }
7078
7079         if (!cpu_has_vmx_shadow_vmcs())
7080                 enable_shadow_vmcs = 0;
7081         if (enable_shadow_vmcs)
7082                 init_vmcs_shadow_fields();
7083
7084         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7085
7086         kvm_mce_cap_supported |= MCG_LMCE_P;
7087
7088         return alloc_kvm_area();
7089
7090 out:
7091         for (i = 0; i < VMX_BITMAP_NR; i++)
7092                 free_page((unsigned long)vmx_bitmap[i]);
7093
7094     return r;
7095 }
7096
7097 static __exit void hardware_unsetup(void)
7098 {
7099         int i;
7100
7101         for (i = 0; i < VMX_BITMAP_NR; i++)
7102                 free_page((unsigned long)vmx_bitmap[i]);
7103
7104         free_kvm_area();
7105 }
7106
7107 /*
7108  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7109  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7110  */
7111 static int handle_pause(struct kvm_vcpu *vcpu)
7112 {
7113         if (ple_gap)
7114                 grow_ple_window(vcpu);
7115
7116         /*
7117          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7118          * VM-execution control is ignored if CPL > 0. OTOH, KVM
7119          * never set PAUSE_EXITING and just set PLE if supported,
7120          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7121          */
7122         kvm_vcpu_on_spin(vcpu, true);
7123         return kvm_skip_emulated_instruction(vcpu);
7124 }
7125
7126 static int handle_nop(struct kvm_vcpu *vcpu)
7127 {
7128         return kvm_skip_emulated_instruction(vcpu);
7129 }
7130
7131 static int handle_mwait(struct kvm_vcpu *vcpu)
7132 {
7133         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7134         return handle_nop(vcpu);
7135 }
7136
7137 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7138 {
7139         kvm_queue_exception(vcpu, UD_VECTOR);
7140         return 1;
7141 }
7142
7143 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7144 {
7145         return 1;
7146 }
7147
7148 static int handle_monitor(struct kvm_vcpu *vcpu)
7149 {
7150         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7151         return handle_nop(vcpu);
7152 }
7153
7154 /*
7155  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7156  * set the success or error code of an emulated VMX instruction, as specified
7157  * by Vol 2B, VMX Instruction Reference, "Conventions".
7158  */
7159 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7160 {
7161         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7162                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7163                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7164 }
7165
7166 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7167 {
7168         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7169                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7170                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7171                         | X86_EFLAGS_CF);
7172 }
7173
7174 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7175                                         u32 vm_instruction_error)
7176 {
7177         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7178                 /*
7179                  * failValid writes the error number to the current VMCS, which
7180                  * can't be done there isn't a current VMCS.
7181                  */
7182                 nested_vmx_failInvalid(vcpu);
7183                 return;
7184         }
7185         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7186                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7187                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7188                         | X86_EFLAGS_ZF);
7189         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7190         /*
7191          * We don't need to force a shadow sync because
7192          * VM_INSTRUCTION_ERROR is not shadowed
7193          */
7194 }
7195
7196 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7197 {
7198         /* TODO: not to reset guest simply here. */
7199         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7200         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7201 }
7202
7203 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7204 {
7205         struct vcpu_vmx *vmx =
7206                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7207
7208         vmx->nested.preemption_timer_expired = true;
7209         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7210         kvm_vcpu_kick(&vmx->vcpu);
7211
7212         return HRTIMER_NORESTART;
7213 }
7214
7215 /*
7216  * Decode the memory-address operand of a vmx instruction, as recorded on an
7217  * exit caused by such an instruction (run by a guest hypervisor).
7218  * On success, returns 0. When the operand is invalid, returns 1 and throws
7219  * #UD or #GP.
7220  */
7221 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7222                                  unsigned long exit_qualification,
7223                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7224 {
7225         gva_t off;
7226         bool exn;
7227         struct kvm_segment s;
7228
7229         /*
7230          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7231          * Execution", on an exit, vmx_instruction_info holds most of the
7232          * addressing components of the operand. Only the displacement part
7233          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7234          * For how an actual address is calculated from all these components,
7235          * refer to Vol. 1, "Operand Addressing".
7236          */
7237         int  scaling = vmx_instruction_info & 3;
7238         int  addr_size = (vmx_instruction_info >> 7) & 7;
7239         bool is_reg = vmx_instruction_info & (1u << 10);
7240         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7241         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7242         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7243         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7244         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7245
7246         if (is_reg) {
7247                 kvm_queue_exception(vcpu, UD_VECTOR);
7248                 return 1;
7249         }
7250
7251         /* Addr = segment_base + offset */
7252         /* offset = base + [index * scale] + displacement */
7253         off = exit_qualification; /* holds the displacement */
7254         if (base_is_valid)
7255                 off += kvm_register_read(vcpu, base_reg);
7256         if (index_is_valid)
7257                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7258         vmx_get_segment(vcpu, &s, seg_reg);
7259         *ret = s.base + off;
7260
7261         if (addr_size == 1) /* 32 bit */
7262                 *ret &= 0xffffffff;
7263
7264         /* Checks for #GP/#SS exceptions. */
7265         exn = false;
7266         if (is_long_mode(vcpu)) {
7267                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7268                  * non-canonical form. This is the only check on the memory
7269                  * destination for long mode!
7270                  */
7271                 exn = is_noncanonical_address(*ret, vcpu);
7272         } else if (is_protmode(vcpu)) {
7273                 /* Protected mode: apply checks for segment validity in the
7274                  * following order:
7275                  * - segment type check (#GP(0) may be thrown)
7276                  * - usability check (#GP(0)/#SS(0))
7277                  * - limit check (#GP(0)/#SS(0))
7278                  */
7279                 if (wr)
7280                         /* #GP(0) if the destination operand is located in a
7281                          * read-only data segment or any code segment.
7282                          */
7283                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7284                 else
7285                         /* #GP(0) if the source operand is located in an
7286                          * execute-only code segment
7287                          */
7288                         exn = ((s.type & 0xa) == 8);
7289                 if (exn) {
7290                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7291                         return 1;
7292                 }
7293                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7294                  */
7295                 exn = (s.unusable != 0);
7296                 /* Protected mode: #GP(0)/#SS(0) if the memory
7297                  * operand is outside the segment limit.
7298                  */
7299                 exn = exn || (off + sizeof(u64) > s.limit);
7300         }
7301         if (exn) {
7302                 kvm_queue_exception_e(vcpu,
7303                                       seg_reg == VCPU_SREG_SS ?
7304                                                 SS_VECTOR : GP_VECTOR,
7305                                       0);
7306                 return 1;
7307         }
7308
7309         return 0;
7310 }
7311
7312 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7313 {
7314         gva_t gva;
7315         struct x86_exception e;
7316
7317         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7318                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7319                 return 1;
7320
7321         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7322                                 sizeof(*vmpointer), &e)) {
7323                 kvm_inject_page_fault(vcpu, &e);
7324                 return 1;
7325         }
7326
7327         return 0;
7328 }
7329
7330 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7331 {
7332         struct vcpu_vmx *vmx = to_vmx(vcpu);
7333         struct vmcs *shadow_vmcs;
7334         int r;
7335
7336         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7337         if (r < 0)
7338                 goto out_vmcs02;
7339
7340         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7341         if (!vmx->nested.cached_vmcs12)
7342                 goto out_cached_vmcs12;
7343
7344         if (enable_shadow_vmcs) {
7345                 shadow_vmcs = alloc_vmcs();
7346                 if (!shadow_vmcs)
7347                         goto out_shadow_vmcs;
7348                 /* mark vmcs as shadow */
7349                 shadow_vmcs->revision_id |= (1u << 31);
7350                 /* init shadow vmcs */
7351                 vmcs_clear(shadow_vmcs);
7352                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7353         }
7354
7355         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7356                      HRTIMER_MODE_REL_PINNED);
7357         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7358
7359         vmx->nested.vmxon = true;
7360         return 0;
7361
7362 out_shadow_vmcs:
7363         kfree(vmx->nested.cached_vmcs12);
7364
7365 out_cached_vmcs12:
7366         free_loaded_vmcs(&vmx->nested.vmcs02);
7367
7368 out_vmcs02:
7369         return -ENOMEM;
7370 }
7371
7372 /*
7373  * Emulate the VMXON instruction.
7374  * Currently, we just remember that VMX is active, and do not save or even
7375  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7376  * do not currently need to store anything in that guest-allocated memory
7377  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7378  * argument is different from the VMXON pointer (which the spec says they do).
7379  */
7380 static int handle_vmon(struct kvm_vcpu *vcpu)
7381 {
7382         int ret;
7383         gpa_t vmptr;
7384         struct page *page;
7385         struct vcpu_vmx *vmx = to_vmx(vcpu);
7386         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7387                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7388
7389         /*
7390          * The Intel VMX Instruction Reference lists a bunch of bits that are
7391          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7392          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7393          * Otherwise, we should fail with #UD.  But most faulting conditions
7394          * have already been checked by hardware, prior to the VM-exit for
7395          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7396          * that bit set to 1 in non-root mode.
7397          */
7398         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7399                 kvm_queue_exception(vcpu, UD_VECTOR);
7400                 return 1;
7401         }
7402
7403         if (vmx->nested.vmxon) {
7404                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7405                 return kvm_skip_emulated_instruction(vcpu);
7406         }
7407
7408         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7409                         != VMXON_NEEDED_FEATURES) {
7410                 kvm_inject_gp(vcpu, 0);
7411                 return 1;
7412         }
7413
7414         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7415                 return 1;
7416
7417         /*
7418          * SDM 3: 24.11.5
7419          * The first 4 bytes of VMXON region contain the supported
7420          * VMCS revision identifier
7421          *
7422          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7423          * which replaces physical address width with 32
7424          */
7425         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7426                 nested_vmx_failInvalid(vcpu);
7427                 return kvm_skip_emulated_instruction(vcpu);
7428         }
7429
7430         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7431         if (is_error_page(page)) {
7432                 nested_vmx_failInvalid(vcpu);
7433                 return kvm_skip_emulated_instruction(vcpu);
7434         }
7435         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7436                 kunmap(page);
7437                 kvm_release_page_clean(page);
7438                 nested_vmx_failInvalid(vcpu);
7439                 return kvm_skip_emulated_instruction(vcpu);
7440         }
7441         kunmap(page);
7442         kvm_release_page_clean(page);
7443
7444         vmx->nested.vmxon_ptr = vmptr;
7445         ret = enter_vmx_operation(vcpu);
7446         if (ret)
7447                 return ret;
7448
7449         nested_vmx_succeed(vcpu);
7450         return kvm_skip_emulated_instruction(vcpu);
7451 }
7452
7453 /*
7454  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7455  * for running VMX instructions (except VMXON, whose prerequisites are
7456  * slightly different). It also specifies what exception to inject otherwise.
7457  * Note that many of these exceptions have priority over VM exits, so they
7458  * don't have to be checked again here.
7459  */
7460 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7461 {
7462         if (!to_vmx(vcpu)->nested.vmxon) {
7463                 kvm_queue_exception(vcpu, UD_VECTOR);
7464                 return 0;
7465         }
7466         return 1;
7467 }
7468
7469 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7470 {
7471         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7472         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7473 }
7474
7475 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7476 {
7477         if (vmx->nested.current_vmptr == -1ull)
7478                 return;
7479
7480         if (enable_shadow_vmcs) {
7481                 /* copy to memory all shadowed fields in case
7482                    they were modified */
7483                 copy_shadow_to_vmcs12(vmx);
7484                 vmx->nested.sync_shadow_vmcs = false;
7485                 vmx_disable_shadow_vmcs(vmx);
7486         }
7487         vmx->nested.posted_intr_nv = -1;
7488
7489         /* Flush VMCS12 to guest memory */
7490         kvm_vcpu_write_guest_page(&vmx->vcpu,
7491                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7492                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7493
7494         vmx->nested.current_vmptr = -1ull;
7495 }
7496
7497 /*
7498  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7499  * just stops using VMX.
7500  */
7501 static void free_nested(struct vcpu_vmx *vmx)
7502 {
7503         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
7504                 return;
7505
7506         vmx->nested.vmxon = false;
7507         vmx->nested.smm.vmxon = false;
7508         free_vpid(vmx->nested.vpid02);
7509         vmx->nested.posted_intr_nv = -1;
7510         vmx->nested.current_vmptr = -1ull;
7511         if (enable_shadow_vmcs) {
7512                 vmx_disable_shadow_vmcs(vmx);
7513                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7514                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7515                 vmx->vmcs01.shadow_vmcs = NULL;
7516         }
7517         kfree(vmx->nested.cached_vmcs12);
7518         /* Unpin physical memory we referred to in the vmcs02 */
7519         if (vmx->nested.apic_access_page) {
7520                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7521                 vmx->nested.apic_access_page = NULL;
7522         }
7523         if (vmx->nested.virtual_apic_page) {
7524                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7525                 vmx->nested.virtual_apic_page = NULL;
7526         }
7527         if (vmx->nested.pi_desc_page) {
7528                 kunmap(vmx->nested.pi_desc_page);
7529                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7530                 vmx->nested.pi_desc_page = NULL;
7531                 vmx->nested.pi_desc = NULL;
7532         }
7533
7534         free_loaded_vmcs(&vmx->nested.vmcs02);
7535 }
7536
7537 /* Emulate the VMXOFF instruction */
7538 static int handle_vmoff(struct kvm_vcpu *vcpu)
7539 {
7540         if (!nested_vmx_check_permission(vcpu))
7541                 return 1;
7542         free_nested(to_vmx(vcpu));
7543         nested_vmx_succeed(vcpu);
7544         return kvm_skip_emulated_instruction(vcpu);
7545 }
7546
7547 /* Emulate the VMCLEAR instruction */
7548 static int handle_vmclear(struct kvm_vcpu *vcpu)
7549 {
7550         struct vcpu_vmx *vmx = to_vmx(vcpu);
7551         u32 zero = 0;
7552         gpa_t vmptr;
7553
7554         if (!nested_vmx_check_permission(vcpu))
7555                 return 1;
7556
7557         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7558                 return 1;
7559
7560         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7561                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7562                 return kvm_skip_emulated_instruction(vcpu);
7563         }
7564
7565         if (vmptr == vmx->nested.vmxon_ptr) {
7566                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7567                 return kvm_skip_emulated_instruction(vcpu);
7568         }
7569
7570         if (vmptr == vmx->nested.current_vmptr)
7571                 nested_release_vmcs12(vmx);
7572
7573         kvm_vcpu_write_guest(vcpu,
7574                         vmptr + offsetof(struct vmcs12, launch_state),
7575                         &zero, sizeof(zero));
7576
7577         nested_vmx_succeed(vcpu);
7578         return kvm_skip_emulated_instruction(vcpu);
7579 }
7580
7581 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7582
7583 /* Emulate the VMLAUNCH instruction */
7584 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7585 {
7586         return nested_vmx_run(vcpu, true);
7587 }
7588
7589 /* Emulate the VMRESUME instruction */
7590 static int handle_vmresume(struct kvm_vcpu *vcpu)
7591 {
7592
7593         return nested_vmx_run(vcpu, false);
7594 }
7595
7596 /*
7597  * Read a vmcs12 field. Since these can have varying lengths and we return
7598  * one type, we chose the biggest type (u64) and zero-extend the return value
7599  * to that size. Note that the caller, handle_vmread, might need to use only
7600  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7601  * 64-bit fields are to be returned).
7602  */
7603 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7604                                   unsigned long field, u64 *ret)
7605 {
7606         short offset = vmcs_field_to_offset(field);
7607         char *p;
7608
7609         if (offset < 0)
7610                 return offset;
7611
7612         p = ((char *)(get_vmcs12(vcpu))) + offset;
7613
7614         switch (vmcs_field_width(field)) {
7615         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7616                 *ret = *((natural_width *)p);
7617                 return 0;
7618         case VMCS_FIELD_WIDTH_U16:
7619                 *ret = *((u16 *)p);
7620                 return 0;
7621         case VMCS_FIELD_WIDTH_U32:
7622                 *ret = *((u32 *)p);
7623                 return 0;
7624         case VMCS_FIELD_WIDTH_U64:
7625                 *ret = *((u64 *)p);
7626                 return 0;
7627         default:
7628                 WARN_ON(1);
7629                 return -ENOENT;
7630         }
7631 }
7632
7633
7634 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7635                                    unsigned long field, u64 field_value){
7636         short offset = vmcs_field_to_offset(field);
7637         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7638         if (offset < 0)
7639                 return offset;
7640
7641         switch (vmcs_field_width(field)) {
7642         case VMCS_FIELD_WIDTH_U16:
7643                 *(u16 *)p = field_value;
7644                 return 0;
7645         case VMCS_FIELD_WIDTH_U32:
7646                 *(u32 *)p = field_value;
7647                 return 0;
7648         case VMCS_FIELD_WIDTH_U64:
7649                 *(u64 *)p = field_value;
7650                 return 0;
7651         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
7652                 *(natural_width *)p = field_value;
7653                 return 0;
7654         default:
7655                 WARN_ON(1);
7656                 return -ENOENT;
7657         }
7658
7659 }
7660
7661 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7662 {
7663         int i;
7664         unsigned long field;
7665         u64 field_value;
7666         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7667         const u16 *fields = shadow_read_write_fields;
7668         const int num_fields = max_shadow_read_write_fields;
7669
7670         preempt_disable();
7671
7672         vmcs_load(shadow_vmcs);
7673
7674         for (i = 0; i < num_fields; i++) {
7675                 field = fields[i];
7676                 field_value = __vmcs_readl(field);
7677                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7678         }
7679
7680         vmcs_clear(shadow_vmcs);
7681         vmcs_load(vmx->loaded_vmcs->vmcs);
7682
7683         preempt_enable();
7684 }
7685
7686 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7687 {
7688         const u16 *fields[] = {
7689                 shadow_read_write_fields,
7690                 shadow_read_only_fields
7691         };
7692         const int max_fields[] = {
7693                 max_shadow_read_write_fields,
7694                 max_shadow_read_only_fields
7695         };
7696         int i, q;
7697         unsigned long field;
7698         u64 field_value = 0;
7699         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7700
7701         vmcs_load(shadow_vmcs);
7702
7703         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7704                 for (i = 0; i < max_fields[q]; i++) {
7705                         field = fields[q][i];
7706                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7707                         __vmcs_writel(field, field_value);
7708                 }
7709         }
7710
7711         vmcs_clear(shadow_vmcs);
7712         vmcs_load(vmx->loaded_vmcs->vmcs);
7713 }
7714
7715 /*
7716  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7717  * used before) all generate the same failure when it is missing.
7718  */
7719 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7720 {
7721         struct vcpu_vmx *vmx = to_vmx(vcpu);
7722         if (vmx->nested.current_vmptr == -1ull) {
7723                 nested_vmx_failInvalid(vcpu);
7724                 return 0;
7725         }
7726         return 1;
7727 }
7728
7729 static int handle_vmread(struct kvm_vcpu *vcpu)
7730 {
7731         unsigned long field;
7732         u64 field_value;
7733         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7734         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7735         gva_t gva = 0;
7736
7737         if (!nested_vmx_check_permission(vcpu))
7738                 return 1;
7739
7740         if (!nested_vmx_check_vmcs12(vcpu))
7741                 return kvm_skip_emulated_instruction(vcpu);
7742
7743         /* Decode instruction info and find the field to read */
7744         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7745         /* Read the field, zero-extended to a u64 field_value */
7746         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7747                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7748                 return kvm_skip_emulated_instruction(vcpu);
7749         }
7750         /*
7751          * Now copy part of this value to register or memory, as requested.
7752          * Note that the number of bits actually copied is 32 or 64 depending
7753          * on the guest's mode (32 or 64 bit), not on the given field's length.
7754          */
7755         if (vmx_instruction_info & (1u << 10)) {
7756                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7757                         field_value);
7758         } else {
7759                 if (get_vmx_mem_address(vcpu, exit_qualification,
7760                                 vmx_instruction_info, true, &gva))
7761                         return 1;
7762                 /* _system ok, as hardware has verified cpl=0 */
7763                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7764                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7765         }
7766
7767         nested_vmx_succeed(vcpu);
7768         return kvm_skip_emulated_instruction(vcpu);
7769 }
7770
7771
7772 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7773 {
7774         unsigned long field;
7775         gva_t gva;
7776         struct vcpu_vmx *vmx = to_vmx(vcpu);
7777         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7778         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7779
7780         /* The value to write might be 32 or 64 bits, depending on L1's long
7781          * mode, and eventually we need to write that into a field of several
7782          * possible lengths. The code below first zero-extends the value to 64
7783          * bit (field_value), and then copies only the appropriate number of
7784          * bits into the vmcs12 field.
7785          */
7786         u64 field_value = 0;
7787         struct x86_exception e;
7788
7789         if (!nested_vmx_check_permission(vcpu))
7790                 return 1;
7791
7792         if (!nested_vmx_check_vmcs12(vcpu))
7793                 return kvm_skip_emulated_instruction(vcpu);
7794
7795         if (vmx_instruction_info & (1u << 10))
7796                 field_value = kvm_register_readl(vcpu,
7797                         (((vmx_instruction_info) >> 3) & 0xf));
7798         else {
7799                 if (get_vmx_mem_address(vcpu, exit_qualification,
7800                                 vmx_instruction_info, false, &gva))
7801                         return 1;
7802                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7803                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7804                         kvm_inject_page_fault(vcpu, &e);
7805                         return 1;
7806                 }
7807         }
7808
7809
7810         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7811         if (vmcs_field_readonly(field)) {
7812                 nested_vmx_failValid(vcpu,
7813                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7814                 return kvm_skip_emulated_instruction(vcpu);
7815         }
7816
7817         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7818                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7819                 return kvm_skip_emulated_instruction(vcpu);
7820         }
7821
7822         switch (field) {
7823 #define SHADOW_FIELD_RW(x) case x:
7824 #include "vmx_shadow_fields.h"
7825                 /*
7826                  * The fields that can be updated by L1 without a vmexit are
7827                  * always updated in the vmcs02, the others go down the slow
7828                  * path of prepare_vmcs02.
7829                  */
7830                 break;
7831         default:
7832                 vmx->nested.dirty_vmcs12 = true;
7833                 break;
7834         }
7835
7836         nested_vmx_succeed(vcpu);
7837         return kvm_skip_emulated_instruction(vcpu);
7838 }
7839
7840 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7841 {
7842         vmx->nested.current_vmptr = vmptr;
7843         if (enable_shadow_vmcs) {
7844                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7845                               SECONDARY_EXEC_SHADOW_VMCS);
7846                 vmcs_write64(VMCS_LINK_POINTER,
7847                              __pa(vmx->vmcs01.shadow_vmcs));
7848                 vmx->nested.sync_shadow_vmcs = true;
7849         }
7850         vmx->nested.dirty_vmcs12 = true;
7851 }
7852
7853 /* Emulate the VMPTRLD instruction */
7854 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7855 {
7856         struct vcpu_vmx *vmx = to_vmx(vcpu);
7857         gpa_t vmptr;
7858
7859         if (!nested_vmx_check_permission(vcpu))
7860                 return 1;
7861
7862         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7863                 return 1;
7864
7865         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7866                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7867                 return kvm_skip_emulated_instruction(vcpu);
7868         }
7869
7870         if (vmptr == vmx->nested.vmxon_ptr) {
7871                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7872                 return kvm_skip_emulated_instruction(vcpu);
7873         }
7874
7875         if (vmx->nested.current_vmptr != vmptr) {
7876                 struct vmcs12 *new_vmcs12;
7877                 struct page *page;
7878                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7879                 if (is_error_page(page)) {
7880                         nested_vmx_failInvalid(vcpu);
7881                         return kvm_skip_emulated_instruction(vcpu);
7882                 }
7883                 new_vmcs12 = kmap(page);
7884                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7885                         kunmap(page);
7886                         kvm_release_page_clean(page);
7887                         nested_vmx_failValid(vcpu,
7888                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7889                         return kvm_skip_emulated_instruction(vcpu);
7890                 }
7891
7892                 nested_release_vmcs12(vmx);
7893                 /*
7894                  * Load VMCS12 from guest memory since it is not already
7895                  * cached.
7896                  */
7897                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7898                 kunmap(page);
7899                 kvm_release_page_clean(page);
7900
7901                 set_current_vmptr(vmx, vmptr);
7902         }
7903
7904         nested_vmx_succeed(vcpu);
7905         return kvm_skip_emulated_instruction(vcpu);
7906 }
7907
7908 /* Emulate the VMPTRST instruction */
7909 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7910 {
7911         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7912         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7913         gva_t vmcs_gva;
7914         struct x86_exception e;
7915
7916         if (!nested_vmx_check_permission(vcpu))
7917                 return 1;
7918
7919         if (get_vmx_mem_address(vcpu, exit_qualification,
7920                         vmx_instruction_info, true, &vmcs_gva))
7921                 return 1;
7922         /* ok to use *_system, as hardware has verified cpl=0 */
7923         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7924                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7925                                  sizeof(u64), &e)) {
7926                 kvm_inject_page_fault(vcpu, &e);
7927                 return 1;
7928         }
7929         nested_vmx_succeed(vcpu);
7930         return kvm_skip_emulated_instruction(vcpu);
7931 }
7932
7933 /* Emulate the INVEPT instruction */
7934 static int handle_invept(struct kvm_vcpu *vcpu)
7935 {
7936         struct vcpu_vmx *vmx = to_vmx(vcpu);
7937         u32 vmx_instruction_info, types;
7938         unsigned long type;
7939         gva_t gva;
7940         struct x86_exception e;
7941         struct {
7942                 u64 eptp, gpa;
7943         } operand;
7944
7945         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7946               SECONDARY_EXEC_ENABLE_EPT) ||
7947             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7948                 kvm_queue_exception(vcpu, UD_VECTOR);
7949                 return 1;
7950         }
7951
7952         if (!nested_vmx_check_permission(vcpu))
7953                 return 1;
7954
7955         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7956         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7957
7958         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7959
7960         if (type >= 32 || !(types & (1 << type))) {
7961                 nested_vmx_failValid(vcpu,
7962                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7963                 return kvm_skip_emulated_instruction(vcpu);
7964         }
7965
7966         /* According to the Intel VMX instruction reference, the memory
7967          * operand is read even if it isn't needed (e.g., for type==global)
7968          */
7969         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7970                         vmx_instruction_info, false, &gva))
7971                 return 1;
7972         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7973                                 sizeof(operand), &e)) {
7974                 kvm_inject_page_fault(vcpu, &e);
7975                 return 1;
7976         }
7977
7978         switch (type) {
7979         case VMX_EPT_EXTENT_GLOBAL:
7980         /*
7981          * TODO: track mappings and invalidate
7982          * single context requests appropriately
7983          */
7984         case VMX_EPT_EXTENT_CONTEXT:
7985                 kvm_mmu_sync_roots(vcpu);
7986                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7987                 nested_vmx_succeed(vcpu);
7988                 break;
7989         default:
7990                 BUG_ON(1);
7991                 break;
7992         }
7993
7994         return kvm_skip_emulated_instruction(vcpu);
7995 }
7996
7997 static int handle_invvpid(struct kvm_vcpu *vcpu)
7998 {
7999         struct vcpu_vmx *vmx = to_vmx(vcpu);
8000         u32 vmx_instruction_info;
8001         unsigned long type, types;
8002         gva_t gva;
8003         struct x86_exception e;
8004         struct {
8005                 u64 vpid;
8006                 u64 gla;
8007         } operand;
8008
8009         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
8010               SECONDARY_EXEC_ENABLE_VPID) ||
8011                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
8012                 kvm_queue_exception(vcpu, UD_VECTOR);
8013                 return 1;
8014         }
8015
8016         if (!nested_vmx_check_permission(vcpu))
8017                 return 1;
8018
8019         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8020         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8021
8022         types = (vmx->nested.nested_vmx_vpid_caps &
8023                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8024
8025         if (type >= 32 || !(types & (1 << type))) {
8026                 nested_vmx_failValid(vcpu,
8027                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8028                 return kvm_skip_emulated_instruction(vcpu);
8029         }
8030
8031         /* according to the intel vmx instruction reference, the memory
8032          * operand is read even if it isn't needed (e.g., for type==global)
8033          */
8034         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8035                         vmx_instruction_info, false, &gva))
8036                 return 1;
8037         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8038                                 sizeof(operand), &e)) {
8039                 kvm_inject_page_fault(vcpu, &e);
8040                 return 1;
8041         }
8042         if (operand.vpid >> 16) {
8043                 nested_vmx_failValid(vcpu,
8044                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8045                 return kvm_skip_emulated_instruction(vcpu);
8046         }
8047
8048         switch (type) {
8049         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8050                 if (is_noncanonical_address(operand.gla, vcpu)) {
8051                         nested_vmx_failValid(vcpu,
8052                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8053                         return kvm_skip_emulated_instruction(vcpu);
8054                 }
8055                 /* fall through */
8056         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8057         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8058                 if (!operand.vpid) {
8059                         nested_vmx_failValid(vcpu,
8060                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8061                         return kvm_skip_emulated_instruction(vcpu);
8062                 }
8063                 break;
8064         case VMX_VPID_EXTENT_ALL_CONTEXT:
8065                 break;
8066         default:
8067                 WARN_ON_ONCE(1);
8068                 return kvm_skip_emulated_instruction(vcpu);
8069         }
8070
8071         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8072         nested_vmx_succeed(vcpu);
8073
8074         return kvm_skip_emulated_instruction(vcpu);
8075 }
8076
8077 static int handle_pml_full(struct kvm_vcpu *vcpu)
8078 {
8079         unsigned long exit_qualification;
8080
8081         trace_kvm_pml_full(vcpu->vcpu_id);
8082
8083         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8084
8085         /*
8086          * PML buffer FULL happened while executing iret from NMI,
8087          * "blocked by NMI" bit has to be set before next VM entry.
8088          */
8089         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8090                         enable_vnmi &&
8091                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8092                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8093                                 GUEST_INTR_STATE_NMI);
8094
8095         /*
8096          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8097          * here.., and there's no userspace involvement needed for PML.
8098          */
8099         return 1;
8100 }
8101
8102 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8103 {
8104         kvm_lapic_expired_hv_timer(vcpu);
8105         return 1;
8106 }
8107
8108 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8109 {
8110         struct vcpu_vmx *vmx = to_vmx(vcpu);
8111         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8112
8113         /* Check for memory type validity */
8114         switch (address & VMX_EPTP_MT_MASK) {
8115         case VMX_EPTP_MT_UC:
8116                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8117                         return false;
8118                 break;
8119         case VMX_EPTP_MT_WB:
8120                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8121                         return false;
8122                 break;
8123         default:
8124                 return false;
8125         }
8126
8127         /* only 4 levels page-walk length are valid */
8128         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8129                 return false;
8130
8131         /* Reserved bits should not be set */
8132         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8133                 return false;
8134
8135         /* AD, if set, should be supported */
8136         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8137                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8138                         return false;
8139         }
8140
8141         return true;
8142 }
8143
8144 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8145                                      struct vmcs12 *vmcs12)
8146 {
8147         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8148         u64 address;
8149         bool accessed_dirty;
8150         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8151
8152         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8153             !nested_cpu_has_ept(vmcs12))
8154                 return 1;
8155
8156         if (index >= VMFUNC_EPTP_ENTRIES)
8157                 return 1;
8158
8159
8160         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8161                                      &address, index * 8, 8))
8162                 return 1;
8163
8164         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8165
8166         /*
8167          * If the (L2) guest does a vmfunc to the currently
8168          * active ept pointer, we don't have to do anything else
8169          */
8170         if (vmcs12->ept_pointer != address) {
8171                 if (!valid_ept_address(vcpu, address))
8172                         return 1;
8173
8174                 kvm_mmu_unload(vcpu);
8175                 mmu->ept_ad = accessed_dirty;
8176                 mmu->base_role.ad_disabled = !accessed_dirty;
8177                 vmcs12->ept_pointer = address;
8178                 /*
8179                  * TODO: Check what's the correct approach in case
8180                  * mmu reload fails. Currently, we just let the next
8181                  * reload potentially fail
8182                  */
8183                 kvm_mmu_reload(vcpu);
8184         }
8185
8186         return 0;
8187 }
8188
8189 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8190 {
8191         struct vcpu_vmx *vmx = to_vmx(vcpu);
8192         struct vmcs12 *vmcs12;
8193         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8194
8195         /*
8196          * VMFUNC is only supported for nested guests, but we always enable the
8197          * secondary control for simplicity; for non-nested mode, fake that we
8198          * didn't by injecting #UD.
8199          */
8200         if (!is_guest_mode(vcpu)) {
8201                 kvm_queue_exception(vcpu, UD_VECTOR);
8202                 return 1;
8203         }
8204
8205         vmcs12 = get_vmcs12(vcpu);
8206         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8207                 goto fail;
8208
8209         switch (function) {
8210         case 0:
8211                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8212                         goto fail;
8213                 break;
8214         default:
8215                 goto fail;
8216         }
8217         return kvm_skip_emulated_instruction(vcpu);
8218
8219 fail:
8220         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8221                           vmcs_read32(VM_EXIT_INTR_INFO),
8222                           vmcs_readl(EXIT_QUALIFICATION));
8223         return 1;
8224 }
8225
8226 /*
8227  * The exit handlers return 1 if the exit was handled fully and guest execution
8228  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8229  * to be done to userspace and return 0.
8230  */
8231 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8232         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8233         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8234         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8235         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8236         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8237         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8238         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8239         [EXIT_REASON_CPUID]                   = handle_cpuid,
8240         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8241         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8242         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8243         [EXIT_REASON_HLT]                     = handle_halt,
8244         [EXIT_REASON_INVD]                    = handle_invd,
8245         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8246         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8247         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8248         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8249         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8250         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8251         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8252         [EXIT_REASON_VMREAD]                  = handle_vmread,
8253         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8254         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8255         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8256         [EXIT_REASON_VMON]                    = handle_vmon,
8257         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8258         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8259         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8260         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8261         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8262         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8263         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8264         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8265         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
8266         [EXIT_REASON_LDTR_TR]                 = handle_desc,
8267         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8268         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8269         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8270         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8271         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8272         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8273         [EXIT_REASON_INVEPT]                  = handle_invept,
8274         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8275         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8276         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8277         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8278         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8279         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8280         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8281         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8282 };
8283
8284 static const int kvm_vmx_max_exit_handlers =
8285         ARRAY_SIZE(kvm_vmx_exit_handlers);
8286
8287 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8288                                        struct vmcs12 *vmcs12)
8289 {
8290         unsigned long exit_qualification;
8291         gpa_t bitmap, last_bitmap;
8292         unsigned int port;
8293         int size;
8294         u8 b;
8295
8296         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8297                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8298
8299         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8300
8301         port = exit_qualification >> 16;
8302         size = (exit_qualification & 7) + 1;
8303
8304         last_bitmap = (gpa_t)-1;
8305         b = -1;
8306
8307         while (size > 0) {
8308                 if (port < 0x8000)
8309                         bitmap = vmcs12->io_bitmap_a;
8310                 else if (port < 0x10000)
8311                         bitmap = vmcs12->io_bitmap_b;
8312                 else
8313                         return true;
8314                 bitmap += (port & 0x7fff) / 8;
8315
8316                 if (last_bitmap != bitmap)
8317                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8318                                 return true;
8319                 if (b & (1 << (port & 7)))
8320                         return true;
8321
8322                 port++;
8323                 size--;
8324                 last_bitmap = bitmap;
8325         }
8326
8327         return false;
8328 }
8329
8330 /*
8331  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8332  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8333  * disinterest in the current event (read or write a specific MSR) by using an
8334  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8335  */
8336 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8337         struct vmcs12 *vmcs12, u32 exit_reason)
8338 {
8339         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8340         gpa_t bitmap;
8341
8342         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8343                 return true;
8344
8345         /*
8346          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8347          * for the four combinations of read/write and low/high MSR numbers.
8348          * First we need to figure out which of the four to use:
8349          */
8350         bitmap = vmcs12->msr_bitmap;
8351         if (exit_reason == EXIT_REASON_MSR_WRITE)
8352                 bitmap += 2048;
8353         if (msr_index >= 0xc0000000) {
8354                 msr_index -= 0xc0000000;
8355                 bitmap += 1024;
8356         }
8357
8358         /* Then read the msr_index'th bit from this bitmap: */
8359         if (msr_index < 1024*8) {
8360                 unsigned char b;
8361                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8362                         return true;
8363                 return 1 & (b >> (msr_index & 7));
8364         } else
8365                 return true; /* let L1 handle the wrong parameter */
8366 }
8367
8368 /*
8369  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8370  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8371  * intercept (via guest_host_mask etc.) the current event.
8372  */
8373 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8374         struct vmcs12 *vmcs12)
8375 {
8376         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8377         int cr = exit_qualification & 15;
8378         int reg;
8379         unsigned long val;
8380
8381         switch ((exit_qualification >> 4) & 3) {
8382         case 0: /* mov to cr */
8383                 reg = (exit_qualification >> 8) & 15;
8384                 val = kvm_register_readl(vcpu, reg);
8385                 switch (cr) {
8386                 case 0:
8387                         if (vmcs12->cr0_guest_host_mask &
8388                             (val ^ vmcs12->cr0_read_shadow))
8389                                 return true;
8390                         break;
8391                 case 3:
8392                         if ((vmcs12->cr3_target_count >= 1 &&
8393                                         vmcs12->cr3_target_value0 == val) ||
8394                                 (vmcs12->cr3_target_count >= 2 &&
8395                                         vmcs12->cr3_target_value1 == val) ||
8396                                 (vmcs12->cr3_target_count >= 3 &&
8397                                         vmcs12->cr3_target_value2 == val) ||
8398                                 (vmcs12->cr3_target_count >= 4 &&
8399                                         vmcs12->cr3_target_value3 == val))
8400                                 return false;
8401                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8402                                 return true;
8403                         break;
8404                 case 4:
8405                         if (vmcs12->cr4_guest_host_mask &
8406                             (vmcs12->cr4_read_shadow ^ val))
8407                                 return true;
8408                         break;
8409                 case 8:
8410                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8411                                 return true;
8412                         break;
8413                 }
8414                 break;
8415         case 2: /* clts */
8416                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8417                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8418                         return true;
8419                 break;
8420         case 1: /* mov from cr */
8421                 switch (cr) {
8422                 case 3:
8423                         if (vmcs12->cpu_based_vm_exec_control &
8424                             CPU_BASED_CR3_STORE_EXITING)
8425                                 return true;
8426                         break;
8427                 case 8:
8428                         if (vmcs12->cpu_based_vm_exec_control &
8429                             CPU_BASED_CR8_STORE_EXITING)
8430                                 return true;
8431                         break;
8432                 }
8433                 break;
8434         case 3: /* lmsw */
8435                 /*
8436                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8437                  * cr0. Other attempted changes are ignored, with no exit.
8438                  */
8439                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8440                 if (vmcs12->cr0_guest_host_mask & 0xe &
8441                     (val ^ vmcs12->cr0_read_shadow))
8442                         return true;
8443                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8444                     !(vmcs12->cr0_read_shadow & 0x1) &&
8445                     (val & 0x1))
8446                         return true;
8447                 break;
8448         }
8449         return false;
8450 }
8451
8452 /*
8453  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8454  * should handle it ourselves in L0 (and then continue L2). Only call this
8455  * when in is_guest_mode (L2).
8456  */
8457 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8458 {
8459         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8460         struct vcpu_vmx *vmx = to_vmx(vcpu);
8461         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8462
8463         if (vmx->nested.nested_run_pending)
8464                 return false;
8465
8466         if (unlikely(vmx->fail)) {
8467                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8468                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8469                 return true;
8470         }
8471
8472         /*
8473          * The host physical addresses of some pages of guest memory
8474          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8475          * Page). The CPU may write to these pages via their host
8476          * physical address while L2 is running, bypassing any
8477          * address-translation-based dirty tracking (e.g. EPT write
8478          * protection).
8479          *
8480          * Mark them dirty on every exit from L2 to prevent them from
8481          * getting out of sync with dirty tracking.
8482          */
8483         nested_mark_vmcs12_pages_dirty(vcpu);
8484
8485         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8486                                 vmcs_readl(EXIT_QUALIFICATION),
8487                                 vmx->idt_vectoring_info,
8488                                 intr_info,
8489                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8490                                 KVM_ISA_VMX);
8491
8492         switch (exit_reason) {
8493         case EXIT_REASON_EXCEPTION_NMI:
8494                 if (is_nmi(intr_info))
8495                         return false;
8496                 else if (is_page_fault(intr_info))
8497                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8498                 else if (is_no_device(intr_info) &&
8499                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8500                         return false;
8501                 else if (is_debug(intr_info) &&
8502                          vcpu->guest_debug &
8503                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8504                         return false;
8505                 else if (is_breakpoint(intr_info) &&
8506                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8507                         return false;
8508                 return vmcs12->exception_bitmap &
8509                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8510         case EXIT_REASON_EXTERNAL_INTERRUPT:
8511                 return false;
8512         case EXIT_REASON_TRIPLE_FAULT:
8513                 return true;
8514         case EXIT_REASON_PENDING_INTERRUPT:
8515                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8516         case EXIT_REASON_NMI_WINDOW:
8517                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8518         case EXIT_REASON_TASK_SWITCH:
8519                 return true;
8520         case EXIT_REASON_CPUID:
8521                 return true;
8522         case EXIT_REASON_HLT:
8523                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8524         case EXIT_REASON_INVD:
8525                 return true;
8526         case EXIT_REASON_INVLPG:
8527                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8528         case EXIT_REASON_RDPMC:
8529                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8530         case EXIT_REASON_RDRAND:
8531                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
8532         case EXIT_REASON_RDSEED:
8533                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
8534         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8535                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8536         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8537         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8538         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8539         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8540         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8541         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8542                 /*
8543                  * VMX instructions trap unconditionally. This allows L1 to
8544                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8545                  */
8546                 return true;
8547         case EXIT_REASON_CR_ACCESS:
8548                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8549         case EXIT_REASON_DR_ACCESS:
8550                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8551         case EXIT_REASON_IO_INSTRUCTION:
8552                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8553         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8554                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8555         case EXIT_REASON_MSR_READ:
8556         case EXIT_REASON_MSR_WRITE:
8557                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8558         case EXIT_REASON_INVALID_STATE:
8559                 return true;
8560         case EXIT_REASON_MWAIT_INSTRUCTION:
8561                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8562         case EXIT_REASON_MONITOR_TRAP_FLAG:
8563                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8564         case EXIT_REASON_MONITOR_INSTRUCTION:
8565                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8566         case EXIT_REASON_PAUSE_INSTRUCTION:
8567                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8568                         nested_cpu_has2(vmcs12,
8569                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8570         case EXIT_REASON_MCE_DURING_VMENTRY:
8571                 return false;
8572         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8573                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8574         case EXIT_REASON_APIC_ACCESS:
8575                 return nested_cpu_has2(vmcs12,
8576                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8577         case EXIT_REASON_APIC_WRITE:
8578         case EXIT_REASON_EOI_INDUCED:
8579                 /* apic_write and eoi_induced should exit unconditionally. */
8580                 return true;
8581         case EXIT_REASON_EPT_VIOLATION:
8582                 /*
8583                  * L0 always deals with the EPT violation. If nested EPT is
8584                  * used, and the nested mmu code discovers that the address is
8585                  * missing in the guest EPT table (EPT12), the EPT violation
8586                  * will be injected with nested_ept_inject_page_fault()
8587                  */
8588                 return false;
8589         case EXIT_REASON_EPT_MISCONFIG:
8590                 /*
8591                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8592                  * table (shadow on EPT) or a merged EPT table that L0 built
8593                  * (EPT on EPT). So any problems with the structure of the
8594                  * table is L0's fault.
8595                  */
8596                 return false;
8597         case EXIT_REASON_INVPCID:
8598                 return
8599                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8600                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8601         case EXIT_REASON_WBINVD:
8602                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8603         case EXIT_REASON_XSETBV:
8604                 return true;
8605         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8606                 /*
8607                  * This should never happen, since it is not possible to
8608                  * set XSS to a non-zero value---neither in L1 nor in L2.
8609                  * If if it were, XSS would have to be checked against
8610                  * the XSS exit bitmap in vmcs12.
8611                  */
8612                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8613         case EXIT_REASON_PREEMPTION_TIMER:
8614                 return false;
8615         case EXIT_REASON_PML_FULL:
8616                 /* We emulate PML support to L1. */
8617                 return false;
8618         case EXIT_REASON_VMFUNC:
8619                 /* VM functions are emulated through L2->L0 vmexits. */
8620                 return false;
8621         default:
8622                 return true;
8623         }
8624 }
8625
8626 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8627 {
8628         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8629
8630         /*
8631          * At this point, the exit interruption info in exit_intr_info
8632          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8633          * we need to query the in-kernel LAPIC.
8634          */
8635         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8636         if ((exit_intr_info &
8637              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8638             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8639                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8640                 vmcs12->vm_exit_intr_error_code =
8641                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8642         }
8643
8644         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8645                           vmcs_readl(EXIT_QUALIFICATION));
8646         return 1;
8647 }
8648
8649 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8650 {
8651         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8652         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8653 }
8654
8655 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8656 {
8657         if (vmx->pml_pg) {
8658                 __free_page(vmx->pml_pg);
8659                 vmx->pml_pg = NULL;
8660         }
8661 }
8662
8663 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8664 {
8665         struct vcpu_vmx *vmx = to_vmx(vcpu);
8666         u64 *pml_buf;
8667         u16 pml_idx;
8668
8669         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8670
8671         /* Do nothing if PML buffer is empty */
8672         if (pml_idx == (PML_ENTITY_NUM - 1))
8673                 return;
8674
8675         /* PML index always points to next available PML buffer entity */
8676         if (pml_idx >= PML_ENTITY_NUM)
8677                 pml_idx = 0;
8678         else
8679                 pml_idx++;
8680
8681         pml_buf = page_address(vmx->pml_pg);
8682         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8683                 u64 gpa;
8684
8685                 gpa = pml_buf[pml_idx];
8686                 WARN_ON(gpa & (PAGE_SIZE - 1));
8687                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8688         }
8689
8690         /* reset PML index */
8691         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8692 }
8693
8694 /*
8695  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8696  * Called before reporting dirty_bitmap to userspace.
8697  */
8698 static void kvm_flush_pml_buffers(struct kvm *kvm)
8699 {
8700         int i;
8701         struct kvm_vcpu *vcpu;
8702         /*
8703          * We only need to kick vcpu out of guest mode here, as PML buffer
8704          * is flushed at beginning of all VMEXITs, and it's obvious that only
8705          * vcpus running in guest are possible to have unflushed GPAs in PML
8706          * buffer.
8707          */
8708         kvm_for_each_vcpu(i, vcpu, kvm)
8709                 kvm_vcpu_kick(vcpu);
8710 }
8711
8712 static void vmx_dump_sel(char *name, uint32_t sel)
8713 {
8714         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8715                name, vmcs_read16(sel),
8716                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8717                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8718                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8719 }
8720
8721 static void vmx_dump_dtsel(char *name, uint32_t limit)
8722 {
8723         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8724                name, vmcs_read32(limit),
8725                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8726 }
8727
8728 static void dump_vmcs(void)
8729 {
8730         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8731         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8732         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8733         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8734         u32 secondary_exec_control = 0;
8735         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8736         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8737         int i, n;
8738
8739         if (cpu_has_secondary_exec_ctrls())
8740                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8741
8742         pr_err("*** Guest State ***\n");
8743         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8744                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8745                vmcs_readl(CR0_GUEST_HOST_MASK));
8746         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8747                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8748         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8749         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8750             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8751         {
8752                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8753                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8754                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8755                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8756         }
8757         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8758                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8759         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8760                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8761         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8762                vmcs_readl(GUEST_SYSENTER_ESP),
8763                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8764         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8765         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8766         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8767         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8768         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8769         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8770         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8771         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8772         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8773         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8774         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8775             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8776                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8777                        efer, vmcs_read64(GUEST_IA32_PAT));
8778         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8779                vmcs_read64(GUEST_IA32_DEBUGCTL),
8780                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8781         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8782                 pr_err("PerfGlobCtl = 0x%016llx\n",
8783                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8784         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8785                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8786         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8787                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8788                vmcs_read32(GUEST_ACTIVITY_STATE));
8789         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8790                 pr_err("InterruptStatus = %04x\n",
8791                        vmcs_read16(GUEST_INTR_STATUS));
8792
8793         pr_err("*** Host State ***\n");
8794         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8795                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8796         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8797                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8798                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8799                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8800                vmcs_read16(HOST_TR_SELECTOR));
8801         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8802                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8803                vmcs_readl(HOST_TR_BASE));
8804         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8805                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8806         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8807                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8808                vmcs_readl(HOST_CR4));
8809         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8810                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8811                vmcs_read32(HOST_IA32_SYSENTER_CS),
8812                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8813         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8814                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8815                        vmcs_read64(HOST_IA32_EFER),
8816                        vmcs_read64(HOST_IA32_PAT));
8817         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8818                 pr_err("PerfGlobCtl = 0x%016llx\n",
8819                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8820
8821         pr_err("*** Control State ***\n");
8822         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8823                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8824         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8825         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8826                vmcs_read32(EXCEPTION_BITMAP),
8827                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8828                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8829         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8830                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8831                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8832                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8833         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8834                vmcs_read32(VM_EXIT_INTR_INFO),
8835                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8836                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8837         pr_err("        reason=%08x qualification=%016lx\n",
8838                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8839         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8840                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8841                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8842         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8843         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8844                 pr_err("TSC Multiplier = 0x%016llx\n",
8845                        vmcs_read64(TSC_MULTIPLIER));
8846         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8847                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8848         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8849                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8850         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8851                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8852         n = vmcs_read32(CR3_TARGET_COUNT);
8853         for (i = 0; i + 1 < n; i += 4)
8854                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8855                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8856                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8857         if (i < n)
8858                 pr_err("CR3 target%u=%016lx\n",
8859                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8860         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8861                 pr_err("PLE Gap=%08x Window=%08x\n",
8862                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8863         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8864                 pr_err("Virtual processor ID = 0x%04x\n",
8865                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8866 }
8867
8868 /*
8869  * The guest has exited.  See if we can fix it or if we need userspace
8870  * assistance.
8871  */
8872 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8873 {
8874         struct vcpu_vmx *vmx = to_vmx(vcpu);
8875         u32 exit_reason = vmx->exit_reason;
8876         u32 vectoring_info = vmx->idt_vectoring_info;
8877
8878         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8879
8880         /*
8881          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8882          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8883          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8884          * mode as if vcpus is in root mode, the PML buffer must has been
8885          * flushed already.
8886          */
8887         if (enable_pml)
8888                 vmx_flush_pml_buffer(vcpu);
8889
8890         /* If guest state is invalid, start emulating */
8891         if (vmx->emulation_required)
8892                 return handle_invalid_guest_state(vcpu);
8893
8894         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8895                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8896
8897         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8898                 dump_vmcs();
8899                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8900                 vcpu->run->fail_entry.hardware_entry_failure_reason
8901                         = exit_reason;
8902                 return 0;
8903         }
8904
8905         if (unlikely(vmx->fail)) {
8906                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8907                 vcpu->run->fail_entry.hardware_entry_failure_reason
8908                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8909                 return 0;
8910         }
8911
8912         /*
8913          * Note:
8914          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8915          * delivery event since it indicates guest is accessing MMIO.
8916          * The vm-exit can be triggered again after return to guest that
8917          * will cause infinite loop.
8918          */
8919         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8920                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8921                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8922                         exit_reason != EXIT_REASON_PML_FULL &&
8923                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8924                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8925                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8926                 vcpu->run->internal.ndata = 3;
8927                 vcpu->run->internal.data[0] = vectoring_info;
8928                 vcpu->run->internal.data[1] = exit_reason;
8929                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8930                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8931                         vcpu->run->internal.ndata++;
8932                         vcpu->run->internal.data[3] =
8933                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8934                 }
8935                 return 0;
8936         }
8937
8938         if (unlikely(!enable_vnmi &&
8939                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
8940                 if (vmx_interrupt_allowed(vcpu)) {
8941                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8942                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
8943                            vcpu->arch.nmi_pending) {
8944                         /*
8945                          * This CPU don't support us in finding the end of an
8946                          * NMI-blocked window if the guest runs with IRQs
8947                          * disabled. So we pull the trigger after 1 s of
8948                          * futile waiting, but inform the user about this.
8949                          */
8950                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8951                                "state on VCPU %d after 1 s timeout\n",
8952                                __func__, vcpu->vcpu_id);
8953                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8954                 }
8955         }
8956
8957         if (exit_reason < kvm_vmx_max_exit_handlers
8958             && kvm_vmx_exit_handlers[exit_reason])
8959                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8960         else {
8961                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8962                                 exit_reason);
8963                 kvm_queue_exception(vcpu, UD_VECTOR);
8964                 return 1;
8965         }
8966 }
8967
8968 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8969 {
8970         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8971
8972         if (is_guest_mode(vcpu) &&
8973                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8974                 return;
8975
8976         if (irr == -1 || tpr < irr) {
8977                 vmcs_write32(TPR_THRESHOLD, 0);
8978                 return;
8979         }
8980
8981         vmcs_write32(TPR_THRESHOLD, irr);
8982 }
8983
8984 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8985 {
8986         u32 sec_exec_control;
8987
8988         /* Postpone execution until vmcs01 is the current VMCS. */
8989         if (is_guest_mode(vcpu)) {
8990                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8991                 return;
8992         }
8993
8994         if (!cpu_has_vmx_virtualize_x2apic_mode())
8995                 return;
8996
8997         if (!cpu_need_tpr_shadow(vcpu))
8998                 return;
8999
9000         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9001
9002         if (set) {
9003                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9004                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9005         } else {
9006                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9007                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9008                 vmx_flush_tlb_ept_only(vcpu);
9009         }
9010         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9011
9012         vmx_update_msr_bitmap(vcpu);
9013 }
9014
9015 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9016 {
9017         struct vcpu_vmx *vmx = to_vmx(vcpu);
9018
9019         /*
9020          * Currently we do not handle the nested case where L2 has an
9021          * APIC access page of its own; that page is still pinned.
9022          * Hence, we skip the case where the VCPU is in guest mode _and_
9023          * L1 prepared an APIC access page for L2.
9024          *
9025          * For the case where L1 and L2 share the same APIC access page
9026          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9027          * in the vmcs12), this function will only update either the vmcs01
9028          * or the vmcs02.  If the former, the vmcs02 will be updated by
9029          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
9030          * the next L2->L1 exit.
9031          */
9032         if (!is_guest_mode(vcpu) ||
9033             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9034                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9035                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9036                 vmx_flush_tlb_ept_only(vcpu);
9037         }
9038 }
9039
9040 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9041 {
9042         u16 status;
9043         u8 old;
9044
9045         if (max_isr == -1)
9046                 max_isr = 0;
9047
9048         status = vmcs_read16(GUEST_INTR_STATUS);
9049         old = status >> 8;
9050         if (max_isr != old) {
9051                 status &= 0xff;
9052                 status |= max_isr << 8;
9053                 vmcs_write16(GUEST_INTR_STATUS, status);
9054         }
9055 }
9056
9057 static void vmx_set_rvi(int vector)
9058 {
9059         u16 status;
9060         u8 old;
9061
9062         if (vector == -1)
9063                 vector = 0;
9064
9065         status = vmcs_read16(GUEST_INTR_STATUS);
9066         old = (u8)status & 0xff;
9067         if ((u8)vector != old) {
9068                 status &= ~0xff;
9069                 status |= (u8)vector;
9070                 vmcs_write16(GUEST_INTR_STATUS, status);
9071         }
9072 }
9073
9074 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9075 {
9076         /*
9077          * When running L2, updating RVI is only relevant when
9078          * vmcs12 virtual-interrupt-delivery enabled.
9079          * However, it can be enabled only when L1 also
9080          * intercepts external-interrupts and in that case
9081          * we should not update vmcs02 RVI but instead intercept
9082          * interrupt. Therefore, do nothing when running L2.
9083          */
9084         if (!is_guest_mode(vcpu))
9085                 vmx_set_rvi(max_irr);
9086 }
9087
9088 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9089 {
9090         struct vcpu_vmx *vmx = to_vmx(vcpu);
9091         int max_irr;
9092         bool max_irr_updated;
9093
9094         WARN_ON(!vcpu->arch.apicv_active);
9095         if (pi_test_on(&vmx->pi_desc)) {
9096                 pi_clear_on(&vmx->pi_desc);
9097                 /*
9098                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9099                  * But on x86 this is just a compiler barrier anyway.
9100                  */
9101                 smp_mb__after_atomic();
9102                 max_irr_updated =
9103                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9104
9105                 /*
9106                  * If we are running L2 and L1 has a new pending interrupt
9107                  * which can be injected, we should re-evaluate
9108                  * what should be done with this new L1 interrupt.
9109                  * If L1 intercepts external-interrupts, we should
9110                  * exit from L2 to L1. Otherwise, interrupt should be
9111                  * delivered directly to L2.
9112                  */
9113                 if (is_guest_mode(vcpu) && max_irr_updated) {
9114                         if (nested_exit_on_intr(vcpu))
9115                                 kvm_vcpu_exiting_guest_mode(vcpu);
9116                         else
9117                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9118                 }
9119         } else {
9120                 max_irr = kvm_lapic_find_highest_irr(vcpu);
9121         }
9122         vmx_hwapic_irr_update(vcpu, max_irr);
9123         return max_irr;
9124 }
9125
9126 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9127 {
9128         if (!kvm_vcpu_apicv_active(vcpu))
9129                 return;
9130
9131         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9132         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9133         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9134         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9135 }
9136
9137 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9138 {
9139         struct vcpu_vmx *vmx = to_vmx(vcpu);
9140
9141         pi_clear_on(&vmx->pi_desc);
9142         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9143 }
9144
9145 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9146 {
9147         u32 exit_intr_info = 0;
9148         u16 basic_exit_reason = (u16)vmx->exit_reason;
9149
9150         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9151               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9152                 return;
9153
9154         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9155                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9156         vmx->exit_intr_info = exit_intr_info;
9157
9158         /* if exit due to PF check for async PF */
9159         if (is_page_fault(exit_intr_info))
9160                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9161
9162         /* Handle machine checks before interrupts are enabled */
9163         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9164             is_machine_check(exit_intr_info))
9165                 kvm_machine_check();
9166
9167         /* We need to handle NMIs before interrupts are enabled */
9168         if (is_nmi(exit_intr_info)) {
9169                 kvm_before_handle_nmi(&vmx->vcpu);
9170                 asm("int $2");
9171                 kvm_after_handle_nmi(&vmx->vcpu);
9172         }
9173 }
9174
9175 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9176 {
9177         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9178
9179         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9180                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9181                 unsigned int vector;
9182                 unsigned long entry;
9183                 gate_desc *desc;
9184                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9185 #ifdef CONFIG_X86_64
9186                 unsigned long tmp;
9187 #endif
9188
9189                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9190                 desc = (gate_desc *)vmx->host_idt_base + vector;
9191                 entry = gate_offset(desc);
9192                 asm volatile(
9193 #ifdef CONFIG_X86_64
9194                         "mov %%" _ASM_SP ", %[sp]\n\t"
9195                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9196                         "push $%c[ss]\n\t"
9197                         "push %[sp]\n\t"
9198 #endif
9199                         "pushf\n\t"
9200                         __ASM_SIZE(push) " $%c[cs]\n\t"
9201                         CALL_NOSPEC
9202                         :
9203 #ifdef CONFIG_X86_64
9204                         [sp]"=&r"(tmp),
9205 #endif
9206                         ASM_CALL_CONSTRAINT
9207                         :
9208                         THUNK_TARGET(entry),
9209                         [ss]"i"(__KERNEL_DS),
9210                         [cs]"i"(__KERNEL_CS)
9211                         );
9212         }
9213 }
9214 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9215
9216 static bool vmx_has_high_real_mode_segbase(void)
9217 {
9218         return enable_unrestricted_guest || emulate_invalid_guest_state;
9219 }
9220
9221 static bool vmx_mpx_supported(void)
9222 {
9223         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9224                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9225 }
9226
9227 static bool vmx_xsaves_supported(void)
9228 {
9229         return vmcs_config.cpu_based_2nd_exec_ctrl &
9230                 SECONDARY_EXEC_XSAVES;
9231 }
9232
9233 static bool vmx_umip_emulated(void)
9234 {
9235         return vmcs_config.cpu_based_2nd_exec_ctrl &
9236                 SECONDARY_EXEC_DESC;
9237 }
9238
9239 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9240 {
9241         u32 exit_intr_info;
9242         bool unblock_nmi;
9243         u8 vector;
9244         bool idtv_info_valid;
9245
9246         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9247
9248         if (enable_vnmi) {
9249                 if (vmx->loaded_vmcs->nmi_known_unmasked)
9250                         return;
9251                 /*
9252                  * Can't use vmx->exit_intr_info since we're not sure what
9253                  * the exit reason is.
9254                  */
9255                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9256                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9257                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9258                 /*
9259                  * SDM 3: 27.7.1.2 (September 2008)
9260                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
9261                  * a guest IRET fault.
9262                  * SDM 3: 23.2.2 (September 2008)
9263                  * Bit 12 is undefined in any of the following cases:
9264                  *  If the VM exit sets the valid bit in the IDT-vectoring
9265                  *   information field.
9266                  *  If the VM exit is due to a double fault.
9267                  */
9268                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9269                     vector != DF_VECTOR && !idtv_info_valid)
9270                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9271                                       GUEST_INTR_STATE_NMI);
9272                 else
9273                         vmx->loaded_vmcs->nmi_known_unmasked =
9274                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9275                                   & GUEST_INTR_STATE_NMI);
9276         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9277                 vmx->loaded_vmcs->vnmi_blocked_time +=
9278                         ktime_to_ns(ktime_sub(ktime_get(),
9279                                               vmx->loaded_vmcs->entry_time));
9280 }
9281
9282 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9283                                       u32 idt_vectoring_info,
9284                                       int instr_len_field,
9285                                       int error_code_field)
9286 {
9287         u8 vector;
9288         int type;
9289         bool idtv_info_valid;
9290
9291         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9292
9293         vcpu->arch.nmi_injected = false;
9294         kvm_clear_exception_queue(vcpu);
9295         kvm_clear_interrupt_queue(vcpu);
9296
9297         if (!idtv_info_valid)
9298                 return;
9299
9300         kvm_make_request(KVM_REQ_EVENT, vcpu);
9301
9302         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9303         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9304
9305         switch (type) {
9306         case INTR_TYPE_NMI_INTR:
9307                 vcpu->arch.nmi_injected = true;
9308                 /*
9309                  * SDM 3: 27.7.1.2 (September 2008)
9310                  * Clear bit "block by NMI" before VM entry if a NMI
9311                  * delivery faulted.
9312                  */
9313                 vmx_set_nmi_mask(vcpu, false);
9314                 break;
9315         case INTR_TYPE_SOFT_EXCEPTION:
9316                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9317                 /* fall through */
9318         case INTR_TYPE_HARD_EXCEPTION:
9319                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9320                         u32 err = vmcs_read32(error_code_field);
9321                         kvm_requeue_exception_e(vcpu, vector, err);
9322                 } else
9323                         kvm_requeue_exception(vcpu, vector);
9324                 break;
9325         case INTR_TYPE_SOFT_INTR:
9326                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9327                 /* fall through */
9328         case INTR_TYPE_EXT_INTR:
9329                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9330                 break;
9331         default:
9332                 break;
9333         }
9334 }
9335
9336 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9337 {
9338         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9339                                   VM_EXIT_INSTRUCTION_LEN,
9340                                   IDT_VECTORING_ERROR_CODE);
9341 }
9342
9343 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9344 {
9345         __vmx_complete_interrupts(vcpu,
9346                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9347                                   VM_ENTRY_INSTRUCTION_LEN,
9348                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9349
9350         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9351 }
9352
9353 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9354 {
9355         int i, nr_msrs;
9356         struct perf_guest_switch_msr *msrs;
9357
9358         msrs = perf_guest_get_msrs(&nr_msrs);
9359
9360         if (!msrs)
9361                 return;
9362
9363         for (i = 0; i < nr_msrs; i++)
9364                 if (msrs[i].host == msrs[i].guest)
9365                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9366                 else
9367                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9368                                         msrs[i].host);
9369 }
9370
9371 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9372 {
9373         struct vcpu_vmx *vmx = to_vmx(vcpu);
9374         u64 tscl;
9375         u32 delta_tsc;
9376
9377         if (vmx->hv_deadline_tsc == -1)
9378                 return;
9379
9380         tscl = rdtsc();
9381         if (vmx->hv_deadline_tsc > tscl)
9382                 /* sure to be 32 bit only because checked on set_hv_timer */
9383                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9384                         cpu_preemption_timer_multi);
9385         else
9386                 delta_tsc = 0;
9387
9388         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9389 }
9390
9391 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9392 {
9393         struct vcpu_vmx *vmx = to_vmx(vcpu);
9394         unsigned long cr3, cr4;
9395
9396         /* Record the guest's net vcpu time for enforced NMI injections. */
9397         if (unlikely(!enable_vnmi &&
9398                      vmx->loaded_vmcs->soft_vnmi_blocked))
9399                 vmx->loaded_vmcs->entry_time = ktime_get();
9400
9401         /* Don't enter VMX if guest state is invalid, let the exit handler
9402            start emulation until we arrive back to a valid state */
9403         if (vmx->emulation_required)
9404                 return;
9405
9406         if (vmx->ple_window_dirty) {
9407                 vmx->ple_window_dirty = false;
9408                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9409         }
9410
9411         if (vmx->nested.sync_shadow_vmcs) {
9412                 copy_vmcs12_to_shadow(vmx);
9413                 vmx->nested.sync_shadow_vmcs = false;
9414         }
9415
9416         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9417                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9418         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9419                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9420
9421         cr3 = __get_current_cr3_fast();
9422         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9423                 vmcs_writel(HOST_CR3, cr3);
9424                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9425         }
9426
9427         cr4 = cr4_read_shadow();
9428         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9429                 vmcs_writel(HOST_CR4, cr4);
9430                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9431         }
9432
9433         /* When single-stepping over STI and MOV SS, we must clear the
9434          * corresponding interruptibility bits in the guest state. Otherwise
9435          * vmentry fails as it then expects bit 14 (BS) in pending debug
9436          * exceptions being set, but that's not correct for the guest debugging
9437          * case. */
9438         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9439                 vmx_set_interrupt_shadow(vcpu, 0);
9440
9441         if (static_cpu_has(X86_FEATURE_PKU) &&
9442             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9443             vcpu->arch.pkru != vmx->host_pkru)
9444                 __write_pkru(vcpu->arch.pkru);
9445
9446         atomic_switch_perf_msrs(vmx);
9447
9448         vmx_arm_hv_timer(vcpu);
9449
9450         /*
9451          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9452          * it's non-zero. Since vmentry is serialising on affected CPUs, there
9453          * is no need to worry about the conditional branch over the wrmsr
9454          * being speculatively taken.
9455          */
9456         if (vmx->spec_ctrl)
9457                 native_wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
9458
9459         vmx->__launched = vmx->loaded_vmcs->launched;
9460         asm(
9461                 /* Store host registers */
9462                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9463                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9464                 "push %%" _ASM_CX " \n\t"
9465                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9466                 "je 1f \n\t"
9467                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9468                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9469                 "1: \n\t"
9470                 /* Reload cr2 if changed */
9471                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9472                 "mov %%cr2, %%" _ASM_DX " \n\t"
9473                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9474                 "je 2f \n\t"
9475                 "mov %%" _ASM_AX", %%cr2 \n\t"
9476                 "2: \n\t"
9477                 /* Check if vmlaunch of vmresume is needed */
9478                 "cmpl $0, %c[launched](%0) \n\t"
9479                 /* Load guest registers.  Don't clobber flags. */
9480                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9481                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9482                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9483                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9484                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9485                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9486 #ifdef CONFIG_X86_64
9487                 "mov %c[r8](%0),  %%r8  \n\t"
9488                 "mov %c[r9](%0),  %%r9  \n\t"
9489                 "mov %c[r10](%0), %%r10 \n\t"
9490                 "mov %c[r11](%0), %%r11 \n\t"
9491                 "mov %c[r12](%0), %%r12 \n\t"
9492                 "mov %c[r13](%0), %%r13 \n\t"
9493                 "mov %c[r14](%0), %%r14 \n\t"
9494                 "mov %c[r15](%0), %%r15 \n\t"
9495 #endif
9496                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9497
9498                 /* Enter guest mode */
9499                 "jne 1f \n\t"
9500                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9501                 "jmp 2f \n\t"
9502                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9503                 "2: "
9504                 /* Save guest registers, load host registers, keep flags */
9505                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9506                 "pop %0 \n\t"
9507                 "setbe %c[fail](%0)\n\t"
9508                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9509                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9510                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9511                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9512                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9513                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9514                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9515 #ifdef CONFIG_X86_64
9516                 "mov %%r8,  %c[r8](%0) \n\t"
9517                 "mov %%r9,  %c[r9](%0) \n\t"
9518                 "mov %%r10, %c[r10](%0) \n\t"
9519                 "mov %%r11, %c[r11](%0) \n\t"
9520                 "mov %%r12, %c[r12](%0) \n\t"
9521                 "mov %%r13, %c[r13](%0) \n\t"
9522                 "mov %%r14, %c[r14](%0) \n\t"
9523                 "mov %%r15, %c[r15](%0) \n\t"
9524                 "xor %%r8d,  %%r8d \n\t"
9525                 "xor %%r9d,  %%r9d \n\t"
9526                 "xor %%r10d, %%r10d \n\t"
9527                 "xor %%r11d, %%r11d \n\t"
9528                 "xor %%r12d, %%r12d \n\t"
9529                 "xor %%r13d, %%r13d \n\t"
9530                 "xor %%r14d, %%r14d \n\t"
9531                 "xor %%r15d, %%r15d \n\t"
9532 #endif
9533                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9534                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9535
9536                 "xor %%eax, %%eax \n\t"
9537                 "xor %%ebx, %%ebx \n\t"
9538                 "xor %%esi, %%esi \n\t"
9539                 "xor %%edi, %%edi \n\t"
9540                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9541                 ".pushsection .rodata \n\t"
9542                 ".global vmx_return \n\t"
9543                 "vmx_return: " _ASM_PTR " 2b \n\t"
9544                 ".popsection"
9545               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9546                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9547                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9548                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9549                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9550                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9551                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9552                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9553                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9554                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9555                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9556 #ifdef CONFIG_X86_64
9557                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9558                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9559                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9560                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9561                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9562                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9563                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9564                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9565 #endif
9566                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9567                 [wordsize]"i"(sizeof(ulong))
9568               : "cc", "memory"
9569 #ifdef CONFIG_X86_64
9570                 , "rax", "rbx", "rdi", "rsi"
9571                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9572 #else
9573                 , "eax", "ebx", "edi", "esi"
9574 #endif
9575               );
9576
9577         /*
9578          * We do not use IBRS in the kernel. If this vCPU has used the
9579          * SPEC_CTRL MSR it may have left it on; save the value and
9580          * turn it off. This is much more efficient than blindly adding
9581          * it to the atomic save/restore list. Especially as the former
9582          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9583          *
9584          * For non-nested case:
9585          * If the L01 MSR bitmap does not intercept the MSR, then we need to
9586          * save it.
9587          *
9588          * For nested case:
9589          * If the L02 MSR bitmap does not intercept the MSR, then we need to
9590          * save it.
9591          */
9592         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
9593                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
9594
9595         if (vmx->spec_ctrl)
9596                 native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
9597
9598         /* Eliminate branch target predictions from guest mode */
9599         vmexit_fill_RSB();
9600
9601         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9602         if (vmx->host_debugctlmsr)
9603                 update_debugctlmsr(vmx->host_debugctlmsr);
9604
9605 #ifndef CONFIG_X86_64
9606         /*
9607          * The sysexit path does not restore ds/es, so we must set them to
9608          * a reasonable value ourselves.
9609          *
9610          * We can't defer this to vmx_load_host_state() since that function
9611          * may be executed in interrupt context, which saves and restore segments
9612          * around it, nullifying its effect.
9613          */
9614         loadsegment(ds, __USER_DS);
9615         loadsegment(es, __USER_DS);
9616 #endif
9617
9618         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9619                                   | (1 << VCPU_EXREG_RFLAGS)
9620                                   | (1 << VCPU_EXREG_PDPTR)
9621                                   | (1 << VCPU_EXREG_SEGMENTS)
9622                                   | (1 << VCPU_EXREG_CR3));
9623         vcpu->arch.regs_dirty = 0;
9624
9625         /*
9626          * eager fpu is enabled if PKEY is supported and CR4 is switched
9627          * back on host, so it is safe to read guest PKRU from current
9628          * XSAVE.
9629          */
9630         if (static_cpu_has(X86_FEATURE_PKU) &&
9631             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9632                 vcpu->arch.pkru = __read_pkru();
9633                 if (vcpu->arch.pkru != vmx->host_pkru)
9634                         __write_pkru(vmx->host_pkru);
9635         }
9636
9637         /*
9638          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9639          * we did not inject a still-pending event to L1 now because of
9640          * nested_run_pending, we need to re-enable this bit.
9641          */
9642         if (vmx->nested.nested_run_pending)
9643                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9644
9645         vmx->nested.nested_run_pending = 0;
9646         vmx->idt_vectoring_info = 0;
9647
9648         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9649         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9650                 return;
9651
9652         vmx->loaded_vmcs->launched = 1;
9653         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9654
9655         vmx_complete_atomic_exit(vmx);
9656         vmx_recover_nmi_blocking(vmx);
9657         vmx_complete_interrupts(vmx);
9658 }
9659 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9660
9661 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9662 {
9663         struct vcpu_vmx *vmx = to_vmx(vcpu);
9664         int cpu;
9665
9666         if (vmx->loaded_vmcs == vmcs)
9667                 return;
9668
9669         cpu = get_cpu();
9670         vmx->loaded_vmcs = vmcs;
9671         vmx_vcpu_put(vcpu);
9672         vmx_vcpu_load(vcpu, cpu);
9673         put_cpu();
9674 }
9675
9676 /*
9677  * Ensure that the current vmcs of the logical processor is the
9678  * vmcs01 of the vcpu before calling free_nested().
9679  */
9680 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9681 {
9682        struct vcpu_vmx *vmx = to_vmx(vcpu);
9683
9684        vcpu_load(vcpu);
9685        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9686        free_nested(vmx);
9687        vcpu_put(vcpu);
9688 }
9689
9690 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9691 {
9692         struct vcpu_vmx *vmx = to_vmx(vcpu);
9693
9694         if (enable_pml)
9695                 vmx_destroy_pml_buffer(vmx);
9696         free_vpid(vmx->vpid);
9697         leave_guest_mode(vcpu);
9698         vmx_free_vcpu_nested(vcpu);
9699         free_loaded_vmcs(vmx->loaded_vmcs);
9700         kfree(vmx->guest_msrs);
9701         kvm_vcpu_uninit(vcpu);
9702         kmem_cache_free(kvm_vcpu_cache, vmx);
9703 }
9704
9705 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9706 {
9707         int err;
9708         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9709         unsigned long *msr_bitmap;
9710         int cpu;
9711
9712         if (!vmx)
9713                 return ERR_PTR(-ENOMEM);
9714
9715         vmx->vpid = allocate_vpid();
9716
9717         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9718         if (err)
9719                 goto free_vcpu;
9720
9721         err = -ENOMEM;
9722
9723         /*
9724          * If PML is turned on, failure on enabling PML just results in failure
9725          * of creating the vcpu, therefore we can simplify PML logic (by
9726          * avoiding dealing with cases, such as enabling PML partially on vcpus
9727          * for the guest, etc.
9728          */
9729         if (enable_pml) {
9730                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9731                 if (!vmx->pml_pg)
9732                         goto uninit_vcpu;
9733         }
9734
9735         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9736         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9737                      > PAGE_SIZE);
9738
9739         if (!vmx->guest_msrs)
9740                 goto free_pml;
9741
9742         err = alloc_loaded_vmcs(&vmx->vmcs01);
9743         if (err < 0)
9744                 goto free_msrs;
9745
9746         msr_bitmap = vmx->vmcs01.msr_bitmap;
9747         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
9748         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
9749         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
9750         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
9751         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
9752         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
9753         vmx->msr_bitmap_mode = 0;
9754
9755         vmx->loaded_vmcs = &vmx->vmcs01;
9756         cpu = get_cpu();
9757         vmx_vcpu_load(&vmx->vcpu, cpu);
9758         vmx->vcpu.cpu = cpu;
9759         vmx_vcpu_setup(vmx);
9760         vmx_vcpu_put(&vmx->vcpu);
9761         put_cpu();
9762         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9763                 err = alloc_apic_access_page(kvm);
9764                 if (err)
9765                         goto free_vmcs;
9766         }
9767
9768         if (enable_ept) {
9769                 err = init_rmode_identity_map(kvm);
9770                 if (err)
9771                         goto free_vmcs;
9772         }
9773
9774         if (nested) {
9775                 nested_vmx_setup_ctls_msrs(vmx);
9776                 vmx->nested.vpid02 = allocate_vpid();
9777         }
9778
9779         vmx->nested.posted_intr_nv = -1;
9780         vmx->nested.current_vmptr = -1ull;
9781
9782         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9783
9784         /*
9785          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9786          * or POSTED_INTR_WAKEUP_VECTOR.
9787          */
9788         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9789         vmx->pi_desc.sn = 1;
9790
9791         return &vmx->vcpu;
9792
9793 free_vmcs:
9794         free_vpid(vmx->nested.vpid02);
9795         free_loaded_vmcs(vmx->loaded_vmcs);
9796 free_msrs:
9797         kfree(vmx->guest_msrs);
9798 free_pml:
9799         vmx_destroy_pml_buffer(vmx);
9800 uninit_vcpu:
9801         kvm_vcpu_uninit(&vmx->vcpu);
9802 free_vcpu:
9803         free_vpid(vmx->vpid);
9804         kmem_cache_free(kvm_vcpu_cache, vmx);
9805         return ERR_PTR(err);
9806 }
9807
9808 static void __init vmx_check_processor_compat(void *rtn)
9809 {
9810         struct vmcs_config vmcs_conf;
9811
9812         *(int *)rtn = 0;
9813         if (setup_vmcs_config(&vmcs_conf) < 0)
9814                 *(int *)rtn = -EIO;
9815         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9816                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9817                                 smp_processor_id());
9818                 *(int *)rtn = -EIO;
9819         }
9820 }
9821
9822 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9823 {
9824         u8 cache;
9825         u64 ipat = 0;
9826
9827         /* For VT-d and EPT combination
9828          * 1. MMIO: always map as UC
9829          * 2. EPT with VT-d:
9830          *   a. VT-d without snooping control feature: can't guarantee the
9831          *      result, try to trust guest.
9832          *   b. VT-d with snooping control feature: snooping control feature of
9833          *      VT-d engine can guarantee the cache correctness. Just set it
9834          *      to WB to keep consistent with host. So the same as item 3.
9835          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9836          *    consistent with host MTRR
9837          */
9838         if (is_mmio) {
9839                 cache = MTRR_TYPE_UNCACHABLE;
9840                 goto exit;
9841         }
9842
9843         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9844                 ipat = VMX_EPT_IPAT_BIT;
9845                 cache = MTRR_TYPE_WRBACK;
9846                 goto exit;
9847         }
9848
9849         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9850                 ipat = VMX_EPT_IPAT_BIT;
9851                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9852                         cache = MTRR_TYPE_WRBACK;
9853                 else
9854                         cache = MTRR_TYPE_UNCACHABLE;
9855                 goto exit;
9856         }
9857
9858         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9859
9860 exit:
9861         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9862 }
9863
9864 static int vmx_get_lpage_level(void)
9865 {
9866         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9867                 return PT_DIRECTORY_LEVEL;
9868         else
9869                 /* For shadow and EPT supported 1GB page */
9870                 return PT_PDPE_LEVEL;
9871 }
9872
9873 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9874 {
9875         /*
9876          * These bits in the secondary execution controls field
9877          * are dynamic, the others are mostly based on the hypervisor
9878          * architecture and the guest's CPUID.  Do not touch the
9879          * dynamic bits.
9880          */
9881         u32 mask =
9882                 SECONDARY_EXEC_SHADOW_VMCS |
9883                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9884                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9885                 SECONDARY_EXEC_DESC;
9886
9887         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9888
9889         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9890                      (new_ctl & ~mask) | (cur_ctl & mask));
9891 }
9892
9893 /*
9894  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9895  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9896  */
9897 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9898 {
9899         struct vcpu_vmx *vmx = to_vmx(vcpu);
9900         struct kvm_cpuid_entry2 *entry;
9901
9902         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9903         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9904
9905 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9906         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9907                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9908 } while (0)
9909
9910         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9911         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9912         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9913         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9914         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9915         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9916         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9917         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9918         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9919         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9920         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9921         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9922         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9923         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9924         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9925
9926         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9927         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9928         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9929         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9930         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9931         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
9932
9933 #undef cr4_fixed1_update
9934 }
9935
9936 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9937 {
9938         struct vcpu_vmx *vmx = to_vmx(vcpu);
9939
9940         if (cpu_has_secondary_exec_ctrls()) {
9941                 vmx_compute_secondary_exec_control(vmx);
9942                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9943         }
9944
9945         if (nested_vmx_allowed(vcpu))
9946                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9947                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9948         else
9949                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9950                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9951
9952         if (nested_vmx_allowed(vcpu))
9953                 nested_vmx_cr_fixed1_bits_update(vcpu);
9954 }
9955
9956 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9957 {
9958         if (func == 1 && nested)
9959                 entry->ecx |= bit(X86_FEATURE_VMX);
9960 }
9961
9962 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9963                 struct x86_exception *fault)
9964 {
9965         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9966         struct vcpu_vmx *vmx = to_vmx(vcpu);
9967         u32 exit_reason;
9968         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9969
9970         if (vmx->nested.pml_full) {
9971                 exit_reason = EXIT_REASON_PML_FULL;
9972                 vmx->nested.pml_full = false;
9973                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9974         } else if (fault->error_code & PFERR_RSVD_MASK)
9975                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9976         else
9977                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9978
9979         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9980         vmcs12->guest_physical_address = fault->address;
9981 }
9982
9983 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9984 {
9985         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9986 }
9987
9988 /* Callbacks for nested_ept_init_mmu_context: */
9989
9990 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9991 {
9992         /* return the page table to be shadowed - in our case, EPT12 */
9993         return get_vmcs12(vcpu)->ept_pointer;
9994 }
9995
9996 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9997 {
9998         WARN_ON(mmu_is_nested(vcpu));
9999         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10000                 return 1;
10001
10002         kvm_mmu_unload(vcpu);
10003         kvm_init_shadow_ept_mmu(vcpu,
10004                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
10005                         VMX_EPT_EXECUTE_ONLY_BIT,
10006                         nested_ept_ad_enabled(vcpu));
10007         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
10008         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
10009         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10010
10011         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
10012         return 0;
10013 }
10014
10015 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10016 {
10017         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10018 }
10019
10020 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10021                                             u16 error_code)
10022 {
10023         bool inequality, bit;
10024
10025         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10026         inequality =
10027                 (error_code & vmcs12->page_fault_error_code_mask) !=
10028                  vmcs12->page_fault_error_code_match;
10029         return inequality ^ bit;
10030 }
10031
10032 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10033                 struct x86_exception *fault)
10034 {
10035         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10036
10037         WARN_ON(!is_guest_mode(vcpu));
10038
10039         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10040                 !to_vmx(vcpu)->nested.nested_run_pending) {
10041                 vmcs12->vm_exit_intr_error_code = fault->error_code;
10042                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10043                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10044                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10045                                   fault->address);
10046         } else {
10047                 kvm_inject_page_fault(vcpu, fault);
10048         }
10049 }
10050
10051 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10052                                                  struct vmcs12 *vmcs12);
10053
10054 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10055                                         struct vmcs12 *vmcs12)
10056 {
10057         struct vcpu_vmx *vmx = to_vmx(vcpu);
10058         struct page *page;
10059         u64 hpa;
10060
10061         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10062                 /*
10063                  * Translate L1 physical address to host physical
10064                  * address for vmcs02. Keep the page pinned, so this
10065                  * physical address remains valid. We keep a reference
10066                  * to it so we can release it later.
10067                  */
10068                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10069                         kvm_release_page_dirty(vmx->nested.apic_access_page);
10070                         vmx->nested.apic_access_page = NULL;
10071                 }
10072                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10073                 /*
10074                  * If translation failed, no matter: This feature asks
10075                  * to exit when accessing the given address, and if it
10076                  * can never be accessed, this feature won't do
10077                  * anything anyway.
10078                  */
10079                 if (!is_error_page(page)) {
10080                         vmx->nested.apic_access_page = page;
10081                         hpa = page_to_phys(vmx->nested.apic_access_page);
10082                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
10083                 } else {
10084                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10085                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10086                 }
10087         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10088                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10089                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
10090                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10091                 kvm_vcpu_reload_apic_access_page(vcpu);
10092         }
10093
10094         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10095                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10096                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10097                         vmx->nested.virtual_apic_page = NULL;
10098                 }
10099                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10100
10101                 /*
10102                  * If translation failed, VM entry will fail because
10103                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10104                  * Failing the vm entry is _not_ what the processor
10105                  * does but it's basically the only possibility we
10106                  * have.  We could still enter the guest if CR8 load
10107                  * exits are enabled, CR8 store exits are enabled, and
10108                  * virtualize APIC access is disabled; in this case
10109                  * the processor would never use the TPR shadow and we
10110                  * could simply clear the bit from the execution
10111                  * control.  But such a configuration is useless, so
10112                  * let's keep the code simple.
10113                  */
10114                 if (!is_error_page(page)) {
10115                         vmx->nested.virtual_apic_page = page;
10116                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
10117                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10118                 }
10119         }
10120
10121         if (nested_cpu_has_posted_intr(vmcs12)) {
10122                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10123                         kunmap(vmx->nested.pi_desc_page);
10124                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
10125                         vmx->nested.pi_desc_page = NULL;
10126                 }
10127                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10128                 if (is_error_page(page))
10129                         return;
10130                 vmx->nested.pi_desc_page = page;
10131                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10132                 vmx->nested.pi_desc =
10133                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
10134                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10135                         (PAGE_SIZE - 1)));
10136                 vmcs_write64(POSTED_INTR_DESC_ADDR,
10137                         page_to_phys(vmx->nested.pi_desc_page) +
10138                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10139                         (PAGE_SIZE - 1)));
10140         }
10141         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10142                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10143                               CPU_BASED_USE_MSR_BITMAPS);
10144         else
10145                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10146                                 CPU_BASED_USE_MSR_BITMAPS);
10147 }
10148
10149 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10150 {
10151         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10152         struct vcpu_vmx *vmx = to_vmx(vcpu);
10153
10154         if (vcpu->arch.virtual_tsc_khz == 0)
10155                 return;
10156
10157         /* Make sure short timeouts reliably trigger an immediate vmexit.
10158          * hrtimer_start does not guarantee this. */
10159         if (preemption_timeout <= 1) {
10160                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10161                 return;
10162         }
10163
10164         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10165         preemption_timeout *= 1000000;
10166         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10167         hrtimer_start(&vmx->nested.preemption_timer,
10168                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10169 }
10170
10171 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10172                                                struct vmcs12 *vmcs12)
10173 {
10174         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10175                 return 0;
10176
10177         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10178             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10179                 return -EINVAL;
10180
10181         return 0;
10182 }
10183
10184 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10185                                                 struct vmcs12 *vmcs12)
10186 {
10187         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10188                 return 0;
10189
10190         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10191                 return -EINVAL;
10192
10193         return 0;
10194 }
10195
10196 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10197                                                 struct vmcs12 *vmcs12)
10198 {
10199         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10200                 return 0;
10201
10202         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10203                 return -EINVAL;
10204
10205         return 0;
10206 }
10207
10208 /*
10209  * Merge L0's and L1's MSR bitmap, return false to indicate that
10210  * we do not use the hardware.
10211  */
10212 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10213                                                  struct vmcs12 *vmcs12)
10214 {
10215         int msr;
10216         struct page *page;
10217         unsigned long *msr_bitmap_l1;
10218         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10219         /*
10220          * pred_cmd & spec_ctrl are trying to verify two things:
10221          *
10222          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10223          *    ensures that we do not accidentally generate an L02 MSR bitmap
10224          *    from the L12 MSR bitmap that is too permissive.
10225          * 2. That L1 or L2s have actually used the MSR. This avoids
10226          *    unnecessarily merging of the bitmap if the MSR is unused. This
10227          *    works properly because we only update the L01 MSR bitmap lazily.
10228          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10229          *    updated to reflect this when L1 (or its L2s) actually write to
10230          *    the MSR.
10231          */
10232         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10233         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10234
10235         /* Nothing to do if the MSR bitmap is not in use.  */
10236         if (!cpu_has_vmx_msr_bitmap() ||
10237             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10238                 return false;
10239
10240         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10241             !pred_cmd && !spec_ctrl)
10242                 return false;
10243
10244         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10245         if (is_error_page(page))
10246                 return false;
10247
10248         msr_bitmap_l1 = (unsigned long *)kmap(page);
10249         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10250                 /*
10251                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10252                  * just lets the processor take the value from the virtual-APIC page;
10253                  * take those 256 bits directly from the L1 bitmap.
10254                  */
10255                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10256                         unsigned word = msr / BITS_PER_LONG;
10257                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
10258                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10259                 }
10260         } else {
10261                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10262                         unsigned word = msr / BITS_PER_LONG;
10263                         msr_bitmap_l0[word] = ~0;
10264                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10265                 }
10266         }
10267
10268         nested_vmx_disable_intercept_for_msr(
10269                 msr_bitmap_l1, msr_bitmap_l0,
10270                 X2APIC_MSR(APIC_TASKPRI),
10271                 MSR_TYPE_W);
10272
10273         if (nested_cpu_has_vid(vmcs12)) {
10274                 nested_vmx_disable_intercept_for_msr(
10275                         msr_bitmap_l1, msr_bitmap_l0,
10276                         X2APIC_MSR(APIC_EOI),
10277                         MSR_TYPE_W);
10278                 nested_vmx_disable_intercept_for_msr(
10279                         msr_bitmap_l1, msr_bitmap_l0,
10280                         X2APIC_MSR(APIC_SELF_IPI),
10281                         MSR_TYPE_W);
10282         }
10283
10284         if (spec_ctrl)
10285                 nested_vmx_disable_intercept_for_msr(
10286                                         msr_bitmap_l1, msr_bitmap_l0,
10287                                         MSR_IA32_SPEC_CTRL,
10288                                         MSR_TYPE_R | MSR_TYPE_W);
10289
10290         if (pred_cmd)
10291                 nested_vmx_disable_intercept_for_msr(
10292                                         msr_bitmap_l1, msr_bitmap_l0,
10293                                         MSR_IA32_PRED_CMD,
10294                                         MSR_TYPE_W);
10295
10296         kunmap(page);
10297         kvm_release_page_clean(page);
10298
10299         return true;
10300 }
10301
10302 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10303                                            struct vmcs12 *vmcs12)
10304 {
10305         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10306             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10307             !nested_cpu_has_vid(vmcs12) &&
10308             !nested_cpu_has_posted_intr(vmcs12))
10309                 return 0;
10310
10311         /*
10312          * If virtualize x2apic mode is enabled,
10313          * virtualize apic access must be disabled.
10314          */
10315         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10316             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10317                 return -EINVAL;
10318
10319         /*
10320          * If virtual interrupt delivery is enabled,
10321          * we must exit on external interrupts.
10322          */
10323         if (nested_cpu_has_vid(vmcs12) &&
10324            !nested_exit_on_intr(vcpu))
10325                 return -EINVAL;
10326
10327         /*
10328          * bits 15:8 should be zero in posted_intr_nv,
10329          * the descriptor address has been already checked
10330          * in nested_get_vmcs12_pages.
10331          */
10332         if (nested_cpu_has_posted_intr(vmcs12) &&
10333            (!nested_cpu_has_vid(vmcs12) ||
10334             !nested_exit_intr_ack_set(vcpu) ||
10335             vmcs12->posted_intr_nv & 0xff00))
10336                 return -EINVAL;
10337
10338         /* tpr shadow is needed by all apicv features. */
10339         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10340                 return -EINVAL;
10341
10342         return 0;
10343 }
10344
10345 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10346                                        unsigned long count_field,
10347                                        unsigned long addr_field)
10348 {
10349         int maxphyaddr;
10350         u64 count, addr;
10351
10352         if (vmcs12_read_any(vcpu, count_field, &count) ||
10353             vmcs12_read_any(vcpu, addr_field, &addr)) {
10354                 WARN_ON(1);
10355                 return -EINVAL;
10356         }
10357         if (count == 0)
10358                 return 0;
10359         maxphyaddr = cpuid_maxphyaddr(vcpu);
10360         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10361             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10362                 pr_debug_ratelimited(
10363                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10364                         addr_field, maxphyaddr, count, addr);
10365                 return -EINVAL;
10366         }
10367         return 0;
10368 }
10369
10370 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10371                                                 struct vmcs12 *vmcs12)
10372 {
10373         if (vmcs12->vm_exit_msr_load_count == 0 &&
10374             vmcs12->vm_exit_msr_store_count == 0 &&
10375             vmcs12->vm_entry_msr_load_count == 0)
10376                 return 0; /* Fast path */
10377         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10378                                         VM_EXIT_MSR_LOAD_ADDR) ||
10379             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10380                                         VM_EXIT_MSR_STORE_ADDR) ||
10381             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10382                                         VM_ENTRY_MSR_LOAD_ADDR))
10383                 return -EINVAL;
10384         return 0;
10385 }
10386
10387 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10388                                          struct vmcs12 *vmcs12)
10389 {
10390         u64 address = vmcs12->pml_address;
10391         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10392
10393         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10394                 if (!nested_cpu_has_ept(vmcs12) ||
10395                     !IS_ALIGNED(address, 4096)  ||
10396                     address >> maxphyaddr)
10397                         return -EINVAL;
10398         }
10399
10400         return 0;
10401 }
10402
10403 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10404                                        struct vmx_msr_entry *e)
10405 {
10406         /* x2APIC MSR accesses are not allowed */
10407         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10408                 return -EINVAL;
10409         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10410             e->index == MSR_IA32_UCODE_REV)
10411                 return -EINVAL;
10412         if (e->reserved != 0)
10413                 return -EINVAL;
10414         return 0;
10415 }
10416
10417 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10418                                      struct vmx_msr_entry *e)
10419 {
10420         if (e->index == MSR_FS_BASE ||
10421             e->index == MSR_GS_BASE ||
10422             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10423             nested_vmx_msr_check_common(vcpu, e))
10424                 return -EINVAL;
10425         return 0;
10426 }
10427
10428 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10429                                       struct vmx_msr_entry *e)
10430 {
10431         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10432             nested_vmx_msr_check_common(vcpu, e))
10433                 return -EINVAL;
10434         return 0;
10435 }
10436
10437 /*
10438  * Load guest's/host's msr at nested entry/exit.
10439  * return 0 for success, entry index for failure.
10440  */
10441 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10442 {
10443         u32 i;
10444         struct vmx_msr_entry e;
10445         struct msr_data msr;
10446
10447         msr.host_initiated = false;
10448         for (i = 0; i < count; i++) {
10449                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10450                                         &e, sizeof(e))) {
10451                         pr_debug_ratelimited(
10452                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10453                                 __func__, i, gpa + i * sizeof(e));
10454                         goto fail;
10455                 }
10456                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10457                         pr_debug_ratelimited(
10458                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10459                                 __func__, i, e.index, e.reserved);
10460                         goto fail;
10461                 }
10462                 msr.index = e.index;
10463                 msr.data = e.value;
10464                 if (kvm_set_msr(vcpu, &msr)) {
10465                         pr_debug_ratelimited(
10466                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10467                                 __func__, i, e.index, e.value);
10468                         goto fail;
10469                 }
10470         }
10471         return 0;
10472 fail:
10473         return i + 1;
10474 }
10475
10476 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10477 {
10478         u32 i;
10479         struct vmx_msr_entry e;
10480
10481         for (i = 0; i < count; i++) {
10482                 struct msr_data msr_info;
10483                 if (kvm_vcpu_read_guest(vcpu,
10484                                         gpa + i * sizeof(e),
10485                                         &e, 2 * sizeof(u32))) {
10486                         pr_debug_ratelimited(
10487                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10488                                 __func__, i, gpa + i * sizeof(e));
10489                         return -EINVAL;
10490                 }
10491                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10492                         pr_debug_ratelimited(
10493                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10494                                 __func__, i, e.index, e.reserved);
10495                         return -EINVAL;
10496                 }
10497                 msr_info.host_initiated = false;
10498                 msr_info.index = e.index;
10499                 if (kvm_get_msr(vcpu, &msr_info)) {
10500                         pr_debug_ratelimited(
10501                                 "%s cannot read MSR (%u, 0x%x)\n",
10502                                 __func__, i, e.index);
10503                         return -EINVAL;
10504                 }
10505                 if (kvm_vcpu_write_guest(vcpu,
10506                                          gpa + i * sizeof(e) +
10507                                              offsetof(struct vmx_msr_entry, value),
10508                                          &msr_info.data, sizeof(msr_info.data))) {
10509                         pr_debug_ratelimited(
10510                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10511                                 __func__, i, e.index, msr_info.data);
10512                         return -EINVAL;
10513                 }
10514         }
10515         return 0;
10516 }
10517
10518 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10519 {
10520         unsigned long invalid_mask;
10521
10522         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10523         return (val & invalid_mask) == 0;
10524 }
10525
10526 /*
10527  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10528  * emulating VM entry into a guest with EPT enabled.
10529  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10530  * is assigned to entry_failure_code on failure.
10531  */
10532 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10533                                u32 *entry_failure_code)
10534 {
10535         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10536                 if (!nested_cr3_valid(vcpu, cr3)) {
10537                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10538                         return 1;
10539                 }
10540
10541                 /*
10542                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10543                  * must not be dereferenced.
10544                  */
10545                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10546                     !nested_ept) {
10547                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10548                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10549                                 return 1;
10550                         }
10551                 }
10552
10553                 vcpu->arch.cr3 = cr3;
10554                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10555         }
10556
10557         kvm_mmu_reset_context(vcpu);
10558         return 0;
10559 }
10560
10561 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10562                                bool from_vmentry)
10563 {
10564         struct vcpu_vmx *vmx = to_vmx(vcpu);
10565
10566         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10567         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10568         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10569         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10570         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10571         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10572         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10573         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10574         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10575         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10576         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10577         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10578         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10579         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10580         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10581         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10582         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10583         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10584         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10585         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10586         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10587         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10588         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10589         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10590         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10591         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10592         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10593         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10594         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10595         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10596         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10597
10598         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10599         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10600                 vmcs12->guest_pending_dbg_exceptions);
10601         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10602         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10603
10604         if (nested_cpu_has_xsaves(vmcs12))
10605                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10606         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10607
10608         if (cpu_has_vmx_posted_intr())
10609                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10610
10611         /*
10612          * Whether page-faults are trapped is determined by a combination of
10613          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10614          * If enable_ept, L0 doesn't care about page faults and we should
10615          * set all of these to L1's desires. However, if !enable_ept, L0 does
10616          * care about (at least some) page faults, and because it is not easy
10617          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10618          * to exit on each and every L2 page fault. This is done by setting
10619          * MASK=MATCH=0 and (see below) EB.PF=1.
10620          * Note that below we don't need special code to set EB.PF beyond the
10621          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10622          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10623          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10624          */
10625         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10626                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10627         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10628                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10629
10630         /* All VMFUNCs are currently emulated through L0 vmexits.  */
10631         if (cpu_has_vmx_vmfunc())
10632                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
10633
10634         if (cpu_has_vmx_apicv()) {
10635                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
10636                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
10637                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
10638                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
10639         }
10640
10641         /*
10642          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10643          * Some constant fields are set here by vmx_set_constant_host_state().
10644          * Other fields are different per CPU, and will be set later when
10645          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10646          */
10647         vmx_set_constant_host_state(vmx);
10648
10649         /*
10650          * Set the MSR load/store lists to match L0's settings.
10651          */
10652         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10653         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10654         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10655         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10656         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10657
10658         set_cr4_guest_host_mask(vmx);
10659
10660         if (vmx_mpx_supported())
10661                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10662
10663         if (enable_vpid) {
10664                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
10665                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10666                 else
10667                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10668         }
10669
10670         /*
10671          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10672          */
10673         if (enable_ept) {
10674                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10675                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10676                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10677                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10678         }
10679
10680         if (cpu_has_vmx_msr_bitmap())
10681                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
10682 }
10683
10684 /*
10685  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10686  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10687  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10688  * guest in a way that will both be appropriate to L1's requests, and our
10689  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10690  * function also has additional necessary side-effects, like setting various
10691  * vcpu->arch fields.
10692  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10693  * is assigned to entry_failure_code on failure.
10694  */
10695 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10696                           bool from_vmentry, u32 *entry_failure_code)
10697 {
10698         struct vcpu_vmx *vmx = to_vmx(vcpu);
10699         u32 exec_control, vmcs12_exec_ctrl;
10700
10701         /*
10702          * First, the fields that are shadowed.  This must be kept in sync
10703          * with vmx_shadow_fields.h.
10704          */
10705
10706         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10707         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10708         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10709         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10710         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10711
10712         /*
10713          * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
10714          * HOST_FS_BASE, HOST_GS_BASE.
10715          */
10716
10717         if (from_vmentry &&
10718             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10719                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10720                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10721         } else {
10722                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10723                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10724         }
10725         if (from_vmentry) {
10726                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10727                              vmcs12->vm_entry_intr_info_field);
10728                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10729                              vmcs12->vm_entry_exception_error_code);
10730                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10731                              vmcs12->vm_entry_instruction_len);
10732                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10733                              vmcs12->guest_interruptibility_info);
10734                 vmx->loaded_vmcs->nmi_known_unmasked =
10735                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10736         } else {
10737                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10738         }
10739         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10740
10741         exec_control = vmcs12->pin_based_vm_exec_control;
10742
10743         /* Preemption timer setting is only taken from vmcs01.  */
10744         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10745         exec_control |= vmcs_config.pin_based_exec_ctrl;
10746         if (vmx->hv_deadline_tsc == -1)
10747                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10748
10749         /* Posted interrupts setting is only taken from vmcs12.  */
10750         if (nested_cpu_has_posted_intr(vmcs12)) {
10751                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10752                 vmx->nested.pi_pending = false;
10753         } else {
10754                 exec_control &= ~PIN_BASED_POSTED_INTR;
10755         }
10756
10757         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10758
10759         vmx->nested.preemption_timer_expired = false;
10760         if (nested_cpu_has_preemption_timer(vmcs12))
10761                 vmx_start_preemption_timer(vcpu);
10762
10763         if (cpu_has_secondary_exec_ctrls()) {
10764                 exec_control = vmx->secondary_exec_control;
10765
10766                 /* Take the following fields only from vmcs12 */
10767                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10768                                   SECONDARY_EXEC_ENABLE_INVPCID |
10769                                   SECONDARY_EXEC_RDTSCP |
10770                                   SECONDARY_EXEC_XSAVES |
10771                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10772                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
10773                                   SECONDARY_EXEC_ENABLE_VMFUNC);
10774                 if (nested_cpu_has(vmcs12,
10775                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10776                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10777                                 ~SECONDARY_EXEC_ENABLE_PML;
10778                         exec_control |= vmcs12_exec_ctrl;
10779                 }
10780
10781                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
10782                         vmcs_write16(GUEST_INTR_STATUS,
10783                                 vmcs12->guest_intr_status);
10784
10785                 /*
10786                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10787                  * nested_get_vmcs12_pages will either fix it up or
10788                  * remove the VM execution control.
10789                  */
10790                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10791                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10792
10793                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10794         }
10795
10796         /*
10797          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10798          * entry, but only if the current (host) sp changed from the value
10799          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10800          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10801          * here we just force the write to happen on entry.
10802          */
10803         vmx->host_rsp = 0;
10804
10805         exec_control = vmx_exec_control(vmx); /* L0's desires */
10806         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10807         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10808         exec_control &= ~CPU_BASED_TPR_SHADOW;
10809         exec_control |= vmcs12->cpu_based_vm_exec_control;
10810
10811         /*
10812          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10813          * nested_get_vmcs12_pages can't fix it up, the illegal value
10814          * will result in a VM entry failure.
10815          */
10816         if (exec_control & CPU_BASED_TPR_SHADOW) {
10817                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10818                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10819         } else {
10820 #ifdef CONFIG_X86_64
10821                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10822                                 CPU_BASED_CR8_STORE_EXITING;
10823 #endif
10824         }
10825
10826         /*
10827          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
10828          * for I/O port accesses.
10829          */
10830         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10831         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10832
10833         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10834
10835         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10836          * bitwise-or of what L1 wants to trap for L2, and what we want to
10837          * trap. Note that CR0.TS also needs updating - we do this later.
10838          */
10839         update_exception_bitmap(vcpu);
10840         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10841         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10842
10843         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10844          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10845          * bits are further modified by vmx_set_efer() below.
10846          */
10847         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10848
10849         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10850          * emulated by vmx_set_efer(), below.
10851          */
10852         vm_entry_controls_init(vmx,
10853                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10854                         ~VM_ENTRY_IA32E_MODE) |
10855                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10856
10857         if (from_vmentry &&
10858             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10859                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10860                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10861         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10862                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10863         }
10864
10865         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10866                 vmcs_write64(TSC_OFFSET,
10867                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10868         else
10869                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10870         if (kvm_has_tsc_control)
10871                 decache_tsc_multiplier(vmx);
10872
10873         if (enable_vpid) {
10874                 /*
10875                  * There is no direct mapping between vpid02 and vpid12, the
10876                  * vpid02 is per-vCPU for L0 and reused while the value of
10877                  * vpid12 is changed w/ one invvpid during nested vmentry.
10878                  * The vpid12 is allocated by L1 for L2, so it will not
10879                  * influence global bitmap(for vpid01 and vpid02 allocation)
10880                  * even if spawn a lot of nested vCPUs.
10881                  */
10882                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10883                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10884                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10885                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true);
10886                         }
10887                 } else {
10888                         vmx_flush_tlb(vcpu, true);
10889                 }
10890         }
10891
10892         if (enable_pml) {
10893                 /*
10894                  * Conceptually we want to copy the PML address and index from
10895                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10896                  * since we always flush the log on each vmexit, this happens
10897                  * to be equivalent to simply resetting the fields in vmcs02.
10898                  */
10899                 ASSERT(vmx->pml_pg);
10900                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10901                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10902         }
10903
10904         if (nested_cpu_has_ept(vmcs12)) {
10905                 if (nested_ept_init_mmu_context(vcpu)) {
10906                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10907                         return 1;
10908                 }
10909         } else if (nested_cpu_has2(vmcs12,
10910                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10911                 vmx_flush_tlb_ept_only(vcpu);
10912         }
10913
10914         /*
10915          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10916          * bits which we consider mandatory enabled.
10917          * The CR0_READ_SHADOW is what L2 should have expected to read given
10918          * the specifications by L1; It's not enough to take
10919          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10920          * have more bits than L1 expected.
10921          */
10922         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10923         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10924
10925         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10926         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10927
10928         if (from_vmentry &&
10929             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10930                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10931         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10932                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10933         else
10934                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10935         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10936         vmx_set_efer(vcpu, vcpu->arch.efer);
10937
10938         if (vmx->nested.dirty_vmcs12) {
10939                 prepare_vmcs02_full(vcpu, vmcs12, from_vmentry);
10940                 vmx->nested.dirty_vmcs12 = false;
10941         }
10942
10943         /* Shadow page tables on either EPT or shadow page tables. */
10944         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10945                                 entry_failure_code))
10946                 return 1;
10947
10948         if (!enable_ept)
10949                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10950
10951         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10952         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10953         return 0;
10954 }
10955
10956 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10957 {
10958         struct vcpu_vmx *vmx = to_vmx(vcpu);
10959
10960         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10961             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10962                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10963
10964         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10965                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10966
10967         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10968                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10969
10970         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10971                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10972
10973         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10974                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10975
10976         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10977                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10978
10979         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10980                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10981
10982         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10983                                 vmx->nested.nested_vmx_procbased_ctls_low,
10984                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10985             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10986              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10987                                  vmx->nested.nested_vmx_secondary_ctls_low,
10988                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10989             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10990                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10991                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10992             !vmx_control_verify(vmcs12->vm_exit_controls,
10993                                 vmx->nested.nested_vmx_exit_ctls_low,
10994                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10995             !vmx_control_verify(vmcs12->vm_entry_controls,
10996                                 vmx->nested.nested_vmx_entry_ctls_low,
10997                                 vmx->nested.nested_vmx_entry_ctls_high))
10998                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10999
11000         if (nested_cpu_has_vmfunc(vmcs12)) {
11001                 if (vmcs12->vm_function_control &
11002                     ~vmx->nested.nested_vmx_vmfunc_controls)
11003                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11004
11005                 if (nested_cpu_has_eptp_switching(vmcs12)) {
11006                         if (!nested_cpu_has_ept(vmcs12) ||
11007                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
11008                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11009                 }
11010         }
11011
11012         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11013                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11014
11015         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11016             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11017             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11018                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11019
11020         return 0;
11021 }
11022
11023 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11024                                   u32 *exit_qual)
11025 {
11026         bool ia32e;
11027
11028         *exit_qual = ENTRY_FAIL_DEFAULT;
11029
11030         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11031             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11032                 return 1;
11033
11034         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11035             vmcs12->vmcs_link_pointer != -1ull) {
11036                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11037                 return 1;
11038         }
11039
11040         /*
11041          * If the load IA32_EFER VM-entry control is 1, the following checks
11042          * are performed on the field for the IA32_EFER MSR:
11043          * - Bits reserved in the IA32_EFER MSR must be 0.
11044          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11045          *   the IA-32e mode guest VM-exit control. It must also be identical
11046          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11047          *   CR0.PG) is 1.
11048          */
11049         if (to_vmx(vcpu)->nested.nested_run_pending &&
11050             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11051                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11052                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11053                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11054                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11055                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11056                         return 1;
11057         }
11058
11059         /*
11060          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11061          * IA32_EFER MSR must be 0 in the field for that register. In addition,
11062          * the values of the LMA and LME bits in the field must each be that of
11063          * the host address-space size VM-exit control.
11064          */
11065         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11066                 ia32e = (vmcs12->vm_exit_controls &
11067                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11068                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11069                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11070                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11071                         return 1;
11072         }
11073
11074         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11075                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11076                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11077                         return 1;
11078
11079         return 0;
11080 }
11081
11082 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
11083 {
11084         struct vcpu_vmx *vmx = to_vmx(vcpu);
11085         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11086         u32 msr_entry_idx;
11087         u32 exit_qual;
11088
11089         enter_guest_mode(vcpu);
11090
11091         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11092                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11093
11094         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11095         vmx_segment_cache_clear(vmx);
11096
11097         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
11098                 leave_guest_mode(vcpu);
11099                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11100                 nested_vmx_entry_failure(vcpu, vmcs12,
11101                                          EXIT_REASON_INVALID_STATE, exit_qual);
11102                 return 1;
11103         }
11104
11105         nested_get_vmcs12_pages(vcpu, vmcs12);
11106
11107         msr_entry_idx = nested_vmx_load_msr(vcpu,
11108                                             vmcs12->vm_entry_msr_load_addr,
11109                                             vmcs12->vm_entry_msr_load_count);
11110         if (msr_entry_idx) {
11111                 leave_guest_mode(vcpu);
11112                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11113                 nested_vmx_entry_failure(vcpu, vmcs12,
11114                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
11115                 return 1;
11116         }
11117
11118         /*
11119          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11120          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11121          * returned as far as L1 is concerned. It will only return (and set
11122          * the success flag) when L2 exits (see nested_vmx_vmexit()).
11123          */
11124         return 0;
11125 }
11126
11127 /*
11128  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11129  * for running an L2 nested guest.
11130  */
11131 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11132 {
11133         struct vmcs12 *vmcs12;
11134         struct vcpu_vmx *vmx = to_vmx(vcpu);
11135         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11136         u32 exit_qual;
11137         int ret;
11138
11139         if (!nested_vmx_check_permission(vcpu))
11140                 return 1;
11141
11142         if (!nested_vmx_check_vmcs12(vcpu))
11143                 goto out;
11144
11145         vmcs12 = get_vmcs12(vcpu);
11146
11147         if (enable_shadow_vmcs)
11148                 copy_shadow_to_vmcs12(vmx);
11149
11150         /*
11151          * The nested entry process starts with enforcing various prerequisites
11152          * on vmcs12 as required by the Intel SDM, and act appropriately when
11153          * they fail: As the SDM explains, some conditions should cause the
11154          * instruction to fail, while others will cause the instruction to seem
11155          * to succeed, but return an EXIT_REASON_INVALID_STATE.
11156          * To speed up the normal (success) code path, we should avoid checking
11157          * for misconfigurations which will anyway be caught by the processor
11158          * when using the merged vmcs02.
11159          */
11160         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11161                 nested_vmx_failValid(vcpu,
11162                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11163                 goto out;
11164         }
11165
11166         if (vmcs12->launch_state == launch) {
11167                 nested_vmx_failValid(vcpu,
11168                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11169                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11170                 goto out;
11171         }
11172
11173         ret = check_vmentry_prereqs(vcpu, vmcs12);
11174         if (ret) {
11175                 nested_vmx_failValid(vcpu, ret);
11176                 goto out;
11177         }
11178
11179         /*
11180          * After this point, the trap flag no longer triggers a singlestep trap
11181          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11182          * This is not 100% correct; for performance reasons, we delegate most
11183          * of the checks on host state to the processor.  If those fail,
11184          * the singlestep trap is missed.
11185          */
11186         skip_emulated_instruction(vcpu);
11187
11188         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11189         if (ret) {
11190                 nested_vmx_entry_failure(vcpu, vmcs12,
11191                                          EXIT_REASON_INVALID_STATE, exit_qual);
11192                 return 1;
11193         }
11194
11195         /*
11196          * We're finally done with prerequisite checking, and can start with
11197          * the nested entry.
11198          */
11199
11200         ret = enter_vmx_non_root_mode(vcpu, true);
11201         if (ret)
11202                 return ret;
11203
11204         /*
11205          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11206          * by event injection, halt vcpu.
11207          */
11208         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11209             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK))
11210                 return kvm_vcpu_halt(vcpu);
11211
11212         vmx->nested.nested_run_pending = 1;
11213
11214         return 1;
11215
11216 out:
11217         return kvm_skip_emulated_instruction(vcpu);
11218 }
11219
11220 /*
11221  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11222  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11223  * This function returns the new value we should put in vmcs12.guest_cr0.
11224  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11225  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11226  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11227  *     didn't trap the bit, because if L1 did, so would L0).
11228  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11229  *     been modified by L2, and L1 knows it. So just leave the old value of
11230  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11231  *     isn't relevant, because if L0 traps this bit it can set it to anything.
11232  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11233  *     changed these bits, and therefore they need to be updated, but L0
11234  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11235  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11236  */
11237 static inline unsigned long
11238 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11239 {
11240         return
11241         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11242         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11243         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11244                         vcpu->arch.cr0_guest_owned_bits));
11245 }
11246
11247 static inline unsigned long
11248 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11249 {
11250         return
11251         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11252         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11253         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11254                         vcpu->arch.cr4_guest_owned_bits));
11255 }
11256
11257 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11258                                        struct vmcs12 *vmcs12)
11259 {
11260         u32 idt_vectoring;
11261         unsigned int nr;
11262
11263         if (vcpu->arch.exception.injected) {
11264                 nr = vcpu->arch.exception.nr;
11265                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11266
11267                 if (kvm_exception_is_soft(nr)) {
11268                         vmcs12->vm_exit_instruction_len =
11269                                 vcpu->arch.event_exit_inst_len;
11270                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11271                 } else
11272                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11273
11274                 if (vcpu->arch.exception.has_error_code) {
11275                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11276                         vmcs12->idt_vectoring_error_code =
11277                                 vcpu->arch.exception.error_code;
11278                 }
11279
11280                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11281         } else if (vcpu->arch.nmi_injected) {
11282                 vmcs12->idt_vectoring_info_field =
11283                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11284         } else if (vcpu->arch.interrupt.pending) {
11285                 nr = vcpu->arch.interrupt.nr;
11286                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11287
11288                 if (vcpu->arch.interrupt.soft) {
11289                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11290                         vmcs12->vm_entry_instruction_len =
11291                                 vcpu->arch.event_exit_inst_len;
11292                 } else
11293                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11294
11295                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11296         }
11297 }
11298
11299 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11300 {
11301         struct vcpu_vmx *vmx = to_vmx(vcpu);
11302         unsigned long exit_qual;
11303         bool block_nested_events =
11304             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11305
11306         if (vcpu->arch.exception.pending &&
11307                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11308                 if (block_nested_events)
11309                         return -EBUSY;
11310                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11311                 return 0;
11312         }
11313
11314         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11315             vmx->nested.preemption_timer_expired) {
11316                 if (block_nested_events)
11317                         return -EBUSY;
11318                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11319                 return 0;
11320         }
11321
11322         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11323                 if (block_nested_events)
11324                         return -EBUSY;
11325                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11326                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11327                                   INTR_INFO_VALID_MASK, 0);
11328                 /*
11329                  * The NMI-triggered VM exit counts as injection:
11330                  * clear this one and block further NMIs.
11331                  */
11332                 vcpu->arch.nmi_pending = 0;
11333                 vmx_set_nmi_mask(vcpu, true);
11334                 return 0;
11335         }
11336
11337         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11338             nested_exit_on_intr(vcpu)) {
11339                 if (block_nested_events)
11340                         return -EBUSY;
11341                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11342                 return 0;
11343         }
11344
11345         vmx_complete_nested_posted_interrupt(vcpu);
11346         return 0;
11347 }
11348
11349 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11350 {
11351         ktime_t remaining =
11352                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11353         u64 value;
11354
11355         if (ktime_to_ns(remaining) <= 0)
11356                 return 0;
11357
11358         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11359         do_div(value, 1000000);
11360         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11361 }
11362
11363 /*
11364  * Update the guest state fields of vmcs12 to reflect changes that
11365  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11366  * VM-entry controls is also updated, since this is really a guest
11367  * state bit.)
11368  */
11369 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11370 {
11371         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11372         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11373
11374         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11375         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11376         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11377
11378         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11379         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11380         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11381         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11382         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11383         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11384         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11385         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11386         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11387         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11388         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11389         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11390         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11391         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11392         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11393         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11394         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11395         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11396         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11397         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11398         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11399         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11400         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11401         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11402         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11403         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11404         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11405         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11406         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11407         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11408         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11409         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11410         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11411         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11412         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11413         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11414
11415         vmcs12->guest_interruptibility_info =
11416                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11417         vmcs12->guest_pending_dbg_exceptions =
11418                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11419         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11420                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11421         else
11422                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11423
11424         if (nested_cpu_has_preemption_timer(vmcs12)) {
11425                 if (vmcs12->vm_exit_controls &
11426                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11427                         vmcs12->vmx_preemption_timer_value =
11428                                 vmx_get_preemption_timer_value(vcpu);
11429                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11430         }
11431
11432         /*
11433          * In some cases (usually, nested EPT), L2 is allowed to change its
11434          * own CR3 without exiting. If it has changed it, we must keep it.
11435          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11436          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11437          *
11438          * Additionally, restore L2's PDPTR to vmcs12.
11439          */
11440         if (enable_ept) {
11441                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11442                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11443                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11444                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11445                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11446         }
11447
11448         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11449
11450         if (nested_cpu_has_vid(vmcs12))
11451                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11452
11453         vmcs12->vm_entry_controls =
11454                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11455                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11456
11457         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11458                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11459                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11460         }
11461
11462         /* TODO: These cannot have changed unless we have MSR bitmaps and
11463          * the relevant bit asks not to trap the change */
11464         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11465                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11466         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11467                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11468         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11469         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11470         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11471         if (kvm_mpx_supported())
11472                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11473 }
11474
11475 /*
11476  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11477  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11478  * and this function updates it to reflect the changes to the guest state while
11479  * L2 was running (and perhaps made some exits which were handled directly by L0
11480  * without going back to L1), and to reflect the exit reason.
11481  * Note that we do not have to copy here all VMCS fields, just those that
11482  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11483  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11484  * which already writes to vmcs12 directly.
11485  */
11486 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11487                            u32 exit_reason, u32 exit_intr_info,
11488                            unsigned long exit_qualification)
11489 {
11490         /* update guest state fields: */
11491         sync_vmcs12(vcpu, vmcs12);
11492
11493         /* update exit information fields: */
11494
11495         vmcs12->vm_exit_reason = exit_reason;
11496         vmcs12->exit_qualification = exit_qualification;
11497         vmcs12->vm_exit_intr_info = exit_intr_info;
11498
11499         vmcs12->idt_vectoring_info_field = 0;
11500         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11501         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11502
11503         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11504                 vmcs12->launch_state = 1;
11505
11506                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11507                  * instead of reading the real value. */
11508                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11509
11510                 /*
11511                  * Transfer the event that L0 or L1 may wanted to inject into
11512                  * L2 to IDT_VECTORING_INFO_FIELD.
11513                  */
11514                 vmcs12_save_pending_event(vcpu, vmcs12);
11515         }
11516
11517         /*
11518          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11519          * preserved above and would only end up incorrectly in L1.
11520          */
11521         vcpu->arch.nmi_injected = false;
11522         kvm_clear_exception_queue(vcpu);
11523         kvm_clear_interrupt_queue(vcpu);
11524 }
11525
11526 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
11527                         struct vmcs12 *vmcs12)
11528 {
11529         u32 entry_failure_code;
11530
11531         nested_ept_uninit_mmu_context(vcpu);
11532
11533         /*
11534          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11535          * couldn't have changed.
11536          */
11537         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11538                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11539
11540         if (!enable_ept)
11541                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11542 }
11543
11544 /*
11545  * A part of what we need to when the nested L2 guest exits and we want to
11546  * run its L1 parent, is to reset L1's guest state to the host state specified
11547  * in vmcs12.
11548  * This function is to be called not only on normal nested exit, but also on
11549  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11550  * Failures During or After Loading Guest State").
11551  * This function should be called when the active VMCS is L1's (vmcs01).
11552  */
11553 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11554                                    struct vmcs12 *vmcs12)
11555 {
11556         struct kvm_segment seg;
11557
11558         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11559                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11560         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11561                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11562         else
11563                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11564         vmx_set_efer(vcpu, vcpu->arch.efer);
11565
11566         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11567         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11568         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11569         /*
11570          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11571          * actually changed, because vmx_set_cr0 refers to efer set above.
11572          *
11573          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11574          * (KVM doesn't change it);
11575          */
11576         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11577         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11578
11579         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11580         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11581         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11582
11583         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11584
11585         if (enable_vpid) {
11586                 /*
11587                  * Trivially support vpid by letting L2s share their parent
11588                  * L1's vpid. TODO: move to a more elaborate solution, giving
11589                  * each L2 its own vpid and exposing the vpid feature to L1.
11590                  */
11591                 vmx_flush_tlb(vcpu, true);
11592         }
11593
11594         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11595         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11596         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11597         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11598         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11599         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11600         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
11601
11602         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11603         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11604                 vmcs_write64(GUEST_BNDCFGS, 0);
11605
11606         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11607                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11608                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11609         }
11610         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11611                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11612                         vmcs12->host_ia32_perf_global_ctrl);
11613
11614         /* Set L1 segment info according to Intel SDM
11615             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11616         seg = (struct kvm_segment) {
11617                 .base = 0,
11618                 .limit = 0xFFFFFFFF,
11619                 .selector = vmcs12->host_cs_selector,
11620                 .type = 11,
11621                 .present = 1,
11622                 .s = 1,
11623                 .g = 1
11624         };
11625         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11626                 seg.l = 1;
11627         else
11628                 seg.db = 1;
11629         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11630         seg = (struct kvm_segment) {
11631                 .base = 0,
11632                 .limit = 0xFFFFFFFF,
11633                 .type = 3,
11634                 .present = 1,
11635                 .s = 1,
11636                 .db = 1,
11637                 .g = 1
11638         };
11639         seg.selector = vmcs12->host_ds_selector;
11640         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11641         seg.selector = vmcs12->host_es_selector;
11642         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11643         seg.selector = vmcs12->host_ss_selector;
11644         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11645         seg.selector = vmcs12->host_fs_selector;
11646         seg.base = vmcs12->host_fs_base;
11647         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11648         seg.selector = vmcs12->host_gs_selector;
11649         seg.base = vmcs12->host_gs_base;
11650         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11651         seg = (struct kvm_segment) {
11652                 .base = vmcs12->host_tr_base,
11653                 .limit = 0x67,
11654                 .selector = vmcs12->host_tr_selector,
11655                 .type = 11,
11656                 .present = 1
11657         };
11658         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11659
11660         kvm_set_dr(vcpu, 7, 0x400);
11661         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11662
11663         if (cpu_has_vmx_msr_bitmap())
11664                 vmx_update_msr_bitmap(vcpu);
11665
11666         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11667                                 vmcs12->vm_exit_msr_load_count))
11668                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11669 }
11670
11671 /*
11672  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11673  * and modify vmcs12 to make it see what it would expect to see there if
11674  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11675  */
11676 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11677                               u32 exit_intr_info,
11678                               unsigned long exit_qualification)
11679 {
11680         struct vcpu_vmx *vmx = to_vmx(vcpu);
11681         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11682
11683         /* trying to cancel vmlaunch/vmresume is a bug */
11684         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11685
11686         /*
11687          * The only expected VM-instruction error is "VM entry with
11688          * invalid control field(s)." Anything else indicates a
11689          * problem with L0.
11690          */
11691         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11692                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11693
11694         leave_guest_mode(vcpu);
11695
11696         if (likely(!vmx->fail)) {
11697                 if (exit_reason == -1)
11698                         sync_vmcs12(vcpu, vmcs12);
11699                 else
11700                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11701                                        exit_qualification);
11702
11703                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11704                                          vmcs12->vm_exit_msr_store_count))
11705                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11706         }
11707
11708         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11709         vm_entry_controls_reset_shadow(vmx);
11710         vm_exit_controls_reset_shadow(vmx);
11711         vmx_segment_cache_clear(vmx);
11712
11713         /* Update any VMCS fields that might have changed while L2 ran */
11714         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11715         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11716         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11717         if (vmx->hv_deadline_tsc == -1)
11718                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11719                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11720         else
11721                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11722                               PIN_BASED_VMX_PREEMPTION_TIMER);
11723         if (kvm_has_tsc_control)
11724                 decache_tsc_multiplier(vmx);
11725
11726         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11727                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11728                 vmx_set_virtual_x2apic_mode(vcpu,
11729                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11730         } else if (!nested_cpu_has_ept(vmcs12) &&
11731                    nested_cpu_has2(vmcs12,
11732                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11733                 vmx_flush_tlb_ept_only(vcpu);
11734         }
11735
11736         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11737         vmx->host_rsp = 0;
11738
11739         /* Unpin physical memory we referred to in vmcs02 */
11740         if (vmx->nested.apic_access_page) {
11741                 kvm_release_page_dirty(vmx->nested.apic_access_page);
11742                 vmx->nested.apic_access_page = NULL;
11743         }
11744         if (vmx->nested.virtual_apic_page) {
11745                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11746                 vmx->nested.virtual_apic_page = NULL;
11747         }
11748         if (vmx->nested.pi_desc_page) {
11749                 kunmap(vmx->nested.pi_desc_page);
11750                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11751                 vmx->nested.pi_desc_page = NULL;
11752                 vmx->nested.pi_desc = NULL;
11753         }
11754
11755         /*
11756          * We are now running in L2, mmu_notifier will force to reload the
11757          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11758          */
11759         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11760
11761         if (enable_shadow_vmcs && exit_reason != -1)
11762                 vmx->nested.sync_shadow_vmcs = true;
11763
11764         /* in case we halted in L2 */
11765         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11766
11767         if (likely(!vmx->fail)) {
11768                 /*
11769                  * TODO: SDM says that with acknowledge interrupt on
11770                  * exit, bit 31 of the VM-exit interrupt information
11771                  * (valid interrupt) is always set to 1 on
11772                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11773                  * need kvm_cpu_has_interrupt().  See the commit
11774                  * message for details.
11775                  */
11776                 if (nested_exit_intr_ack_set(vcpu) &&
11777                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11778                     kvm_cpu_has_interrupt(vcpu)) {
11779                         int irq = kvm_cpu_get_interrupt(vcpu);
11780                         WARN_ON(irq < 0);
11781                         vmcs12->vm_exit_intr_info = irq |
11782                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11783                 }
11784
11785                 if (exit_reason != -1)
11786                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11787                                                        vmcs12->exit_qualification,
11788                                                        vmcs12->idt_vectoring_info_field,
11789                                                        vmcs12->vm_exit_intr_info,
11790                                                        vmcs12->vm_exit_intr_error_code,
11791                                                        KVM_ISA_VMX);
11792
11793                 load_vmcs12_host_state(vcpu, vmcs12);
11794
11795                 return;
11796         }
11797
11798         /*
11799          * After an early L2 VM-entry failure, we're now back
11800          * in L1 which thinks it just finished a VMLAUNCH or
11801          * VMRESUME instruction, so we need to set the failure
11802          * flag and the VM-instruction error field of the VMCS
11803          * accordingly.
11804          */
11805         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11806
11807         load_vmcs12_mmu_host_state(vcpu, vmcs12);
11808
11809         /*
11810          * The emulated instruction was already skipped in
11811          * nested_vmx_run, but the updated RIP was never
11812          * written back to the vmcs01.
11813          */
11814         skip_emulated_instruction(vcpu);
11815         vmx->fail = 0;
11816 }
11817
11818 /*
11819  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11820  */
11821 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11822 {
11823         if (is_guest_mode(vcpu)) {
11824                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11825                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11826         }
11827         free_nested(to_vmx(vcpu));
11828 }
11829
11830 /*
11831  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11832  * 23.7 "VM-entry failures during or after loading guest state" (this also
11833  * lists the acceptable exit-reason and exit-qualification parameters).
11834  * It should only be called before L2 actually succeeded to run, and when
11835  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11836  */
11837 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11838                         struct vmcs12 *vmcs12,
11839                         u32 reason, unsigned long qualification)
11840 {
11841         load_vmcs12_host_state(vcpu, vmcs12);
11842         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11843         vmcs12->exit_qualification = qualification;
11844         nested_vmx_succeed(vcpu);
11845         if (enable_shadow_vmcs)
11846                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11847 }
11848
11849 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11850                                struct x86_instruction_info *info,
11851                                enum x86_intercept_stage stage)
11852 {
11853         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11854         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
11855
11856         /*
11857          * RDPID causes #UD if disabled through secondary execution controls.
11858          * Because it is marked as EmulateOnUD, we need to intercept it here.
11859          */
11860         if (info->intercept == x86_intercept_rdtscp &&
11861             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
11862                 ctxt->exception.vector = UD_VECTOR;
11863                 ctxt->exception.error_code_valid = false;
11864                 return X86EMUL_PROPAGATE_FAULT;
11865         }
11866
11867         /* TODO: check more intercepts... */
11868         return X86EMUL_CONTINUE;
11869 }
11870
11871 #ifdef CONFIG_X86_64
11872 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11873 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11874                                   u64 divisor, u64 *result)
11875 {
11876         u64 low = a << shift, high = a >> (64 - shift);
11877
11878         /* To avoid the overflow on divq */
11879         if (high >= divisor)
11880                 return 1;
11881
11882         /* Low hold the result, high hold rem which is discarded */
11883         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11884             "rm" (divisor), "0" (low), "1" (high));
11885         *result = low;
11886
11887         return 0;
11888 }
11889
11890 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11891 {
11892         struct vcpu_vmx *vmx = to_vmx(vcpu);
11893         u64 tscl = rdtsc();
11894         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11895         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11896
11897         /* Convert to host delta tsc if tsc scaling is enabled */
11898         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11899                         u64_shl_div_u64(delta_tsc,
11900                                 kvm_tsc_scaling_ratio_frac_bits,
11901                                 vcpu->arch.tsc_scaling_ratio,
11902                                 &delta_tsc))
11903                 return -ERANGE;
11904
11905         /*
11906          * If the delta tsc can't fit in the 32 bit after the multi shift,
11907          * we can't use the preemption timer.
11908          * It's possible that it fits on later vmentries, but checking
11909          * on every vmentry is costly so we just use an hrtimer.
11910          */
11911         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11912                 return -ERANGE;
11913
11914         vmx->hv_deadline_tsc = tscl + delta_tsc;
11915         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11916                         PIN_BASED_VMX_PREEMPTION_TIMER);
11917
11918         return delta_tsc == 0;
11919 }
11920
11921 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11922 {
11923         struct vcpu_vmx *vmx = to_vmx(vcpu);
11924         vmx->hv_deadline_tsc = -1;
11925         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11926                         PIN_BASED_VMX_PREEMPTION_TIMER);
11927 }
11928 #endif
11929
11930 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11931 {
11932         if (ple_gap)
11933                 shrink_ple_window(vcpu);
11934 }
11935
11936 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11937                                      struct kvm_memory_slot *slot)
11938 {
11939         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11940         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11941 }
11942
11943 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11944                                        struct kvm_memory_slot *slot)
11945 {
11946         kvm_mmu_slot_set_dirty(kvm, slot);
11947 }
11948
11949 static void vmx_flush_log_dirty(struct kvm *kvm)
11950 {
11951         kvm_flush_pml_buffers(kvm);
11952 }
11953
11954 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11955 {
11956         struct vmcs12 *vmcs12;
11957         struct vcpu_vmx *vmx = to_vmx(vcpu);
11958         gpa_t gpa;
11959         struct page *page = NULL;
11960         u64 *pml_address;
11961
11962         if (is_guest_mode(vcpu)) {
11963                 WARN_ON_ONCE(vmx->nested.pml_full);
11964
11965                 /*
11966                  * Check if PML is enabled for the nested guest.
11967                  * Whether eptp bit 6 is set is already checked
11968                  * as part of A/D emulation.
11969                  */
11970                 vmcs12 = get_vmcs12(vcpu);
11971                 if (!nested_cpu_has_pml(vmcs12))
11972                         return 0;
11973
11974                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11975                         vmx->nested.pml_full = true;
11976                         return 1;
11977                 }
11978
11979                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11980
11981                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11982                 if (is_error_page(page))
11983                         return 0;
11984
11985                 pml_address = kmap(page);
11986                 pml_address[vmcs12->guest_pml_index--] = gpa;
11987                 kunmap(page);
11988                 kvm_release_page_clean(page);
11989         }
11990
11991         return 0;
11992 }
11993
11994 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11995                                            struct kvm_memory_slot *memslot,
11996                                            gfn_t offset, unsigned long mask)
11997 {
11998         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11999 }
12000
12001 static void __pi_post_block(struct kvm_vcpu *vcpu)
12002 {
12003         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12004         struct pi_desc old, new;
12005         unsigned int dest;
12006
12007         do {
12008                 old.control = new.control = pi_desc->control;
12009                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12010                      "Wakeup handler not enabled while the VCPU is blocked\n");
12011
12012                 dest = cpu_physical_id(vcpu->cpu);
12013
12014                 if (x2apic_enabled())
12015                         new.ndst = dest;
12016                 else
12017                         new.ndst = (dest << 8) & 0xFF00;
12018
12019                 /* set 'NV' to 'notification vector' */
12020                 new.nv = POSTED_INTR_VECTOR;
12021         } while (cmpxchg64(&pi_desc->control, old.control,
12022                            new.control) != old.control);
12023
12024         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12025                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12026                 list_del(&vcpu->blocked_vcpu_list);
12027                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12028                 vcpu->pre_pcpu = -1;
12029         }
12030 }
12031
12032 /*
12033  * This routine does the following things for vCPU which is going
12034  * to be blocked if VT-d PI is enabled.
12035  * - Store the vCPU to the wakeup list, so when interrupts happen
12036  *   we can find the right vCPU to wake up.
12037  * - Change the Posted-interrupt descriptor as below:
12038  *      'NDST' <-- vcpu->pre_pcpu
12039  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12040  * - If 'ON' is set during this process, which means at least one
12041  *   interrupt is posted for this vCPU, we cannot block it, in
12042  *   this case, return 1, otherwise, return 0.
12043  *
12044  */
12045 static int pi_pre_block(struct kvm_vcpu *vcpu)
12046 {
12047         unsigned int dest;
12048         struct pi_desc old, new;
12049         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12050
12051         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12052                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
12053                 !kvm_vcpu_apicv_active(vcpu))
12054                 return 0;
12055
12056         WARN_ON(irqs_disabled());
12057         local_irq_disable();
12058         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12059                 vcpu->pre_pcpu = vcpu->cpu;
12060                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12061                 list_add_tail(&vcpu->blocked_vcpu_list,
12062                               &per_cpu(blocked_vcpu_on_cpu,
12063                                        vcpu->pre_pcpu));
12064                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12065         }
12066
12067         do {
12068                 old.control = new.control = pi_desc->control;
12069
12070                 WARN((pi_desc->sn == 1),
12071                      "Warning: SN field of posted-interrupts "
12072                      "is set before blocking\n");
12073
12074                 /*
12075                  * Since vCPU can be preempted during this process,
12076                  * vcpu->cpu could be different with pre_pcpu, we
12077                  * need to set pre_pcpu as the destination of wakeup
12078                  * notification event, then we can find the right vCPU
12079                  * to wakeup in wakeup handler if interrupts happen
12080                  * when the vCPU is in blocked state.
12081                  */
12082                 dest = cpu_physical_id(vcpu->pre_pcpu);
12083
12084                 if (x2apic_enabled())
12085                         new.ndst = dest;
12086                 else
12087                         new.ndst = (dest << 8) & 0xFF00;
12088
12089                 /* set 'NV' to 'wakeup vector' */
12090                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12091         } while (cmpxchg64(&pi_desc->control, old.control,
12092                            new.control) != old.control);
12093
12094         /* We should not block the vCPU if an interrupt is posted for it.  */
12095         if (pi_test_on(pi_desc) == 1)
12096                 __pi_post_block(vcpu);
12097
12098         local_irq_enable();
12099         return (vcpu->pre_pcpu == -1);
12100 }
12101
12102 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12103 {
12104         if (pi_pre_block(vcpu))
12105                 return 1;
12106
12107         if (kvm_lapic_hv_timer_in_use(vcpu))
12108                 kvm_lapic_switch_to_sw_timer(vcpu);
12109
12110         return 0;
12111 }
12112
12113 static void pi_post_block(struct kvm_vcpu *vcpu)
12114 {
12115         if (vcpu->pre_pcpu == -1)
12116                 return;
12117
12118         WARN_ON(irqs_disabled());
12119         local_irq_disable();
12120         __pi_post_block(vcpu);
12121         local_irq_enable();
12122 }
12123
12124 static void vmx_post_block(struct kvm_vcpu *vcpu)
12125 {
12126         if (kvm_x86_ops->set_hv_timer)
12127                 kvm_lapic_switch_to_hv_timer(vcpu);
12128
12129         pi_post_block(vcpu);
12130 }
12131
12132 /*
12133  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12134  *
12135  * @kvm: kvm
12136  * @host_irq: host irq of the interrupt
12137  * @guest_irq: gsi of the interrupt
12138  * @set: set or unset PI
12139  * returns 0 on success, < 0 on failure
12140  */
12141 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12142                               uint32_t guest_irq, bool set)
12143 {
12144         struct kvm_kernel_irq_routing_entry *e;
12145         struct kvm_irq_routing_table *irq_rt;
12146         struct kvm_lapic_irq irq;
12147         struct kvm_vcpu *vcpu;
12148         struct vcpu_data vcpu_info;
12149         int idx, ret = 0;
12150
12151         if (!kvm_arch_has_assigned_device(kvm) ||
12152                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12153                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12154                 return 0;
12155
12156         idx = srcu_read_lock(&kvm->irq_srcu);
12157         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12158         if (guest_irq >= irq_rt->nr_rt_entries ||
12159             hlist_empty(&irq_rt->map[guest_irq])) {
12160                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12161                              guest_irq, irq_rt->nr_rt_entries);
12162                 goto out;
12163         }
12164
12165         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12166                 if (e->type != KVM_IRQ_ROUTING_MSI)
12167                         continue;
12168                 /*
12169                  * VT-d PI cannot support posting multicast/broadcast
12170                  * interrupts to a vCPU, we still use interrupt remapping
12171                  * for these kind of interrupts.
12172                  *
12173                  * For lowest-priority interrupts, we only support
12174                  * those with single CPU as the destination, e.g. user
12175                  * configures the interrupts via /proc/irq or uses
12176                  * irqbalance to make the interrupts single-CPU.
12177                  *
12178                  * We will support full lowest-priority interrupt later.
12179                  */
12180
12181                 kvm_set_msi_irq(kvm, e, &irq);
12182                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12183                         /*
12184                          * Make sure the IRTE is in remapped mode if
12185                          * we don't handle it in posted mode.
12186                          */
12187                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12188                         if (ret < 0) {
12189                                 printk(KERN_INFO
12190                                    "failed to back to remapped mode, irq: %u\n",
12191                                    host_irq);
12192                                 goto out;
12193                         }
12194
12195                         continue;
12196                 }
12197
12198                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12199                 vcpu_info.vector = irq.vector;
12200
12201                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
12202                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12203
12204                 if (set)
12205                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12206                 else
12207                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12208
12209                 if (ret < 0) {
12210                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
12211                                         __func__);
12212                         goto out;
12213                 }
12214         }
12215
12216         ret = 0;
12217 out:
12218         srcu_read_unlock(&kvm->irq_srcu, idx);
12219         return ret;
12220 }
12221
12222 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12223 {
12224         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12225                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12226                         FEATURE_CONTROL_LMCE;
12227         else
12228                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12229                         ~FEATURE_CONTROL_LMCE;
12230 }
12231
12232 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12233 {
12234         /* we need a nested vmexit to enter SMM, postpone if run is pending */
12235         if (to_vmx(vcpu)->nested.nested_run_pending)
12236                 return 0;
12237         return 1;
12238 }
12239
12240 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12241 {
12242         struct vcpu_vmx *vmx = to_vmx(vcpu);
12243
12244         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12245         if (vmx->nested.smm.guest_mode)
12246                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12247
12248         vmx->nested.smm.vmxon = vmx->nested.vmxon;
12249         vmx->nested.vmxon = false;
12250         return 0;
12251 }
12252
12253 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12254 {
12255         struct vcpu_vmx *vmx = to_vmx(vcpu);
12256         int ret;
12257
12258         if (vmx->nested.smm.vmxon) {
12259                 vmx->nested.vmxon = true;
12260                 vmx->nested.smm.vmxon = false;
12261         }
12262
12263         if (vmx->nested.smm.guest_mode) {
12264                 vcpu->arch.hflags &= ~HF_SMM_MASK;
12265                 ret = enter_vmx_non_root_mode(vcpu, false);
12266                 vcpu->arch.hflags |= HF_SMM_MASK;
12267                 if (ret)
12268                         return ret;
12269
12270                 vmx->nested.smm.guest_mode = false;
12271         }
12272         return 0;
12273 }
12274
12275 static int enable_smi_window(struct kvm_vcpu *vcpu)
12276 {
12277         return 0;
12278 }
12279
12280 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12281         .cpu_has_kvm_support = cpu_has_kvm_support,
12282         .disabled_by_bios = vmx_disabled_by_bios,
12283         .hardware_setup = hardware_setup,
12284         .hardware_unsetup = hardware_unsetup,
12285         .check_processor_compatibility = vmx_check_processor_compat,
12286         .hardware_enable = hardware_enable,
12287         .hardware_disable = hardware_disable,
12288         .cpu_has_accelerated_tpr = report_flexpriority,
12289         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12290
12291         .vcpu_create = vmx_create_vcpu,
12292         .vcpu_free = vmx_free_vcpu,
12293         .vcpu_reset = vmx_vcpu_reset,
12294
12295         .prepare_guest_switch = vmx_save_host_state,
12296         .vcpu_load = vmx_vcpu_load,
12297         .vcpu_put = vmx_vcpu_put,
12298
12299         .update_bp_intercept = update_exception_bitmap,
12300         .get_msr = vmx_get_msr,
12301         .set_msr = vmx_set_msr,
12302         .get_segment_base = vmx_get_segment_base,
12303         .get_segment = vmx_get_segment,
12304         .set_segment = vmx_set_segment,
12305         .get_cpl = vmx_get_cpl,
12306         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12307         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12308         .decache_cr3 = vmx_decache_cr3,
12309         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12310         .set_cr0 = vmx_set_cr0,
12311         .set_cr3 = vmx_set_cr3,
12312         .set_cr4 = vmx_set_cr4,
12313         .set_efer = vmx_set_efer,
12314         .get_idt = vmx_get_idt,
12315         .set_idt = vmx_set_idt,
12316         .get_gdt = vmx_get_gdt,
12317         .set_gdt = vmx_set_gdt,
12318         .get_dr6 = vmx_get_dr6,
12319         .set_dr6 = vmx_set_dr6,
12320         .set_dr7 = vmx_set_dr7,
12321         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12322         .cache_reg = vmx_cache_reg,
12323         .get_rflags = vmx_get_rflags,
12324         .set_rflags = vmx_set_rflags,
12325
12326         .tlb_flush = vmx_flush_tlb,
12327
12328         .run = vmx_vcpu_run,
12329         .handle_exit = vmx_handle_exit,
12330         .skip_emulated_instruction = skip_emulated_instruction,
12331         .set_interrupt_shadow = vmx_set_interrupt_shadow,
12332         .get_interrupt_shadow = vmx_get_interrupt_shadow,
12333         .patch_hypercall = vmx_patch_hypercall,
12334         .set_irq = vmx_inject_irq,
12335         .set_nmi = vmx_inject_nmi,
12336         .queue_exception = vmx_queue_exception,
12337         .cancel_injection = vmx_cancel_injection,
12338         .interrupt_allowed = vmx_interrupt_allowed,
12339         .nmi_allowed = vmx_nmi_allowed,
12340         .get_nmi_mask = vmx_get_nmi_mask,
12341         .set_nmi_mask = vmx_set_nmi_mask,
12342         .enable_nmi_window = enable_nmi_window,
12343         .enable_irq_window = enable_irq_window,
12344         .update_cr8_intercept = update_cr8_intercept,
12345         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12346         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12347         .get_enable_apicv = vmx_get_enable_apicv,
12348         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12349         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12350         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12351         .hwapic_irr_update = vmx_hwapic_irr_update,
12352         .hwapic_isr_update = vmx_hwapic_isr_update,
12353         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12354         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12355
12356         .set_tss_addr = vmx_set_tss_addr,
12357         .get_tdp_level = get_ept_level,
12358         .get_mt_mask = vmx_get_mt_mask,
12359
12360         .get_exit_info = vmx_get_exit_info,
12361
12362         .get_lpage_level = vmx_get_lpage_level,
12363
12364         .cpuid_update = vmx_cpuid_update,
12365
12366         .rdtscp_supported = vmx_rdtscp_supported,
12367         .invpcid_supported = vmx_invpcid_supported,
12368
12369         .set_supported_cpuid = vmx_set_supported_cpuid,
12370
12371         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12372
12373         .write_tsc_offset = vmx_write_tsc_offset,
12374
12375         .set_tdp_cr3 = vmx_set_cr3,
12376
12377         .check_intercept = vmx_check_intercept,
12378         .handle_external_intr = vmx_handle_external_intr,
12379         .mpx_supported = vmx_mpx_supported,
12380         .xsaves_supported = vmx_xsaves_supported,
12381         .umip_emulated = vmx_umip_emulated,
12382
12383         .check_nested_events = vmx_check_nested_events,
12384
12385         .sched_in = vmx_sched_in,
12386
12387         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12388         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12389         .flush_log_dirty = vmx_flush_log_dirty,
12390         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12391         .write_log_dirty = vmx_write_pml_buffer,
12392
12393         .pre_block = vmx_pre_block,
12394         .post_block = vmx_post_block,
12395
12396         .pmu_ops = &intel_pmu_ops,
12397
12398         .update_pi_irte = vmx_update_pi_irte,
12399
12400 #ifdef CONFIG_X86_64
12401         .set_hv_timer = vmx_set_hv_timer,
12402         .cancel_hv_timer = vmx_cancel_hv_timer,
12403 #endif
12404
12405         .setup_mce = vmx_setup_mce,
12406
12407         .smi_allowed = vmx_smi_allowed,
12408         .pre_enter_smm = vmx_pre_enter_smm,
12409         .pre_leave_smm = vmx_pre_leave_smm,
12410         .enable_smi_window = enable_smi_window,
12411 };
12412
12413 static int __init vmx_init(void)
12414 {
12415         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12416                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12417         if (r)
12418                 return r;
12419
12420 #ifdef CONFIG_KEXEC_CORE
12421         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12422                            crash_vmclear_local_loaded_vmcss);
12423 #endif
12424
12425         return 0;
12426 }
12427
12428 static void __exit vmx_exit(void)
12429 {
12430 #ifdef CONFIG_KEXEC_CORE
12431         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12432         synchronize_rcu();
12433 #endif
12434
12435         kvm_exit();
12436 }
12437
12438 module_init(vmx_init)
12439 module_exit(vmx_exit)