2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX),
68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
70 static bool __read_mostly enable_vpid = 1;
71 module_param_named(vpid, enable_vpid, bool, 0444);
73 static bool __read_mostly flexpriority_enabled = 1;
74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
76 static bool __read_mostly enable_ept = 1;
77 module_param_named(ept, enable_ept, bool, S_IRUGO);
79 static bool __read_mostly enable_unrestricted_guest = 1;
80 module_param_named(unrestricted_guest,
81 enable_unrestricted_guest, bool, S_IRUGO);
83 static bool __read_mostly enable_ept_ad_bits = 1;
84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
86 static bool __read_mostly emulate_invalid_guest_state = true;
87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
89 static bool __read_mostly fasteoi = 1;
90 module_param(fasteoi, bool, S_IRUGO);
92 static bool __read_mostly enable_apicv = 1;
93 module_param(enable_apicv, bool, S_IRUGO);
95 static bool __read_mostly enable_shadow_vmcs = 1;
96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested = 0;
103 module_param(nested, bool, S_IRUGO);
105 static u64 __read_mostly host_xss;
107 static bool __read_mostly enable_pml = 1;
108 module_param_named(pml, enable_pml, bool, S_IRUGO);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi;
114 static bool __read_mostly enable_preemption_timer = 1;
116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
163 module_param(ple_gap, int, S_IRUGO);
165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
166 module_param(ple_window, int, S_IRUGO);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
170 module_param(ple_window_grow, int, S_IRUGO);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
174 module_param(ple_window_shrink, int, S_IRUGO);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, int, S_IRUGO);
181 extern const ulong vmx_return;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs *shadow_vmcs;
202 struct list_head loaded_vmcss_on_cpu_link;
205 struct shared_msr_entry {
212 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
213 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
214 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
215 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
216 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
217 * More than one of these structures may exist, if L1 runs multiple L2 guests.
218 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
219 * underlying hardware which will be used to run L2.
220 * This structure is packed to ensure that its layout is identical across
221 * machines (necessary for live migration).
222 * If there are changes in this struct, VMCS12_REVISION must be changed.
224 typedef u64 natural_width;
225 struct __packed vmcs12 {
226 /* According to the Intel spec, a VMCS region must start with the
227 * following two fields. Then follow implementation-specific data.
232 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
233 u32 padding[7]; /* room for future expansion */
238 u64 vm_exit_msr_store_addr;
239 u64 vm_exit_msr_load_addr;
240 u64 vm_entry_msr_load_addr;
242 u64 virtual_apic_page_addr;
243 u64 apic_access_addr;
244 u64 posted_intr_desc_addr;
246 u64 eoi_exit_bitmap0;
247 u64 eoi_exit_bitmap1;
248 u64 eoi_exit_bitmap2;
249 u64 eoi_exit_bitmap3;
251 u64 guest_physical_address;
252 u64 vmcs_link_pointer;
254 u64 guest_ia32_debugctl;
257 u64 guest_ia32_perf_global_ctrl;
265 u64 host_ia32_perf_global_ctrl;
266 u64 padding64[8]; /* room for future expansion */
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
273 natural_width cr0_guest_host_mask;
274 natural_width cr4_guest_host_mask;
275 natural_width cr0_read_shadow;
276 natural_width cr4_read_shadow;
277 natural_width cr3_target_value0;
278 natural_width cr3_target_value1;
279 natural_width cr3_target_value2;
280 natural_width cr3_target_value3;
281 natural_width exit_qualification;
282 natural_width guest_linear_address;
283 natural_width guest_cr0;
284 natural_width guest_cr3;
285 natural_width guest_cr4;
286 natural_width guest_es_base;
287 natural_width guest_cs_base;
288 natural_width guest_ss_base;
289 natural_width guest_ds_base;
290 natural_width guest_fs_base;
291 natural_width guest_gs_base;
292 natural_width guest_ldtr_base;
293 natural_width guest_tr_base;
294 natural_width guest_gdtr_base;
295 natural_width guest_idtr_base;
296 natural_width guest_dr7;
297 natural_width guest_rsp;
298 natural_width guest_rip;
299 natural_width guest_rflags;
300 natural_width guest_pending_dbg_exceptions;
301 natural_width guest_sysenter_esp;
302 natural_width guest_sysenter_eip;
303 natural_width host_cr0;
304 natural_width host_cr3;
305 natural_width host_cr4;
306 natural_width host_fs_base;
307 natural_width host_gs_base;
308 natural_width host_tr_base;
309 natural_width host_gdtr_base;
310 natural_width host_idtr_base;
311 natural_width host_ia32_sysenter_esp;
312 natural_width host_ia32_sysenter_eip;
313 natural_width host_rsp;
314 natural_width host_rip;
315 natural_width paddingl[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control;
317 u32 cpu_based_vm_exec_control;
318 u32 exception_bitmap;
319 u32 page_fault_error_code_mask;
320 u32 page_fault_error_code_match;
321 u32 cr3_target_count;
322 u32 vm_exit_controls;
323 u32 vm_exit_msr_store_count;
324 u32 vm_exit_msr_load_count;
325 u32 vm_entry_controls;
326 u32 vm_entry_msr_load_count;
327 u32 vm_entry_intr_info_field;
328 u32 vm_entry_exception_error_code;
329 u32 vm_entry_instruction_len;
331 u32 secondary_vm_exec_control;
332 u32 vm_instruction_error;
334 u32 vm_exit_intr_info;
335 u32 vm_exit_intr_error_code;
336 u32 idt_vectoring_info_field;
337 u32 idt_vectoring_error_code;
338 u32 vm_exit_instruction_len;
339 u32 vmx_instruction_info;
346 u32 guest_ldtr_limit;
348 u32 guest_gdtr_limit;
349 u32 guest_idtr_limit;
350 u32 guest_es_ar_bytes;
351 u32 guest_cs_ar_bytes;
352 u32 guest_ss_ar_bytes;
353 u32 guest_ds_ar_bytes;
354 u32 guest_fs_ar_bytes;
355 u32 guest_gs_ar_bytes;
356 u32 guest_ldtr_ar_bytes;
357 u32 guest_tr_ar_bytes;
358 u32 guest_interruptibility_info;
359 u32 guest_activity_state;
360 u32 guest_sysenter_cs;
361 u32 host_ia32_sysenter_cs;
362 u32 vmx_preemption_timer_value;
363 u32 padding32[7]; /* room for future expansion */
364 u16 virtual_processor_id;
366 u16 guest_es_selector;
367 u16 guest_cs_selector;
368 u16 guest_ss_selector;
369 u16 guest_ds_selector;
370 u16 guest_fs_selector;
371 u16 guest_gs_selector;
372 u16 guest_ldtr_selector;
373 u16 guest_tr_selector;
374 u16 guest_intr_status;
376 u16 host_es_selector;
377 u16 host_cs_selector;
378 u16 host_ss_selector;
379 u16 host_ds_selector;
380 u16 host_fs_selector;
381 u16 host_gs_selector;
382 u16 host_tr_selector;
386 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
387 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
388 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
390 #define VMCS12_REVISION 0x11e57ed0
393 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
394 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
395 * current implementation, 4K are reserved to avoid future complications.
397 #define VMCS12_SIZE 0x1000
399 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
401 struct list_head list;
403 struct loaded_vmcs vmcs02;
407 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
408 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
411 /* Has the level1 guest done vmxon? */
416 /* The guest-physical address of the current VMCS L1 keeps for L2 */
418 /* The host-usable pointer to the above */
419 struct page *current_vmcs12_page;
420 struct vmcs12 *current_vmcs12;
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMXOFF, VMCLEAR, VMPTRLD.
426 struct vmcs12 *cached_vmcs12;
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
431 bool sync_shadow_vmcs;
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool;
436 bool change_vmcs01_virtual_x2apic_mode;
437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending;
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
443 struct page *apic_access_page;
444 struct page *virtual_apic_page;
445 struct page *pi_desc_page;
446 struct pi_desc *pi_desc;
450 unsigned long *msr_bitmap;
452 struct hrtimer preemption_timer;
453 bool preemption_timer_expired;
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
466 u32 nested_vmx_procbased_ctls_low;
467 u32 nested_vmx_procbased_ctls_high;
468 u32 nested_vmx_secondary_ctls_low;
469 u32 nested_vmx_secondary_ctls_high;
470 u32 nested_vmx_pinbased_ctls_low;
471 u32 nested_vmx_pinbased_ctls_high;
472 u32 nested_vmx_exit_ctls_low;
473 u32 nested_vmx_exit_ctls_high;
474 u32 nested_vmx_entry_ctls_low;
475 u32 nested_vmx_entry_ctls_high;
476 u32 nested_vmx_misc_low;
477 u32 nested_vmx_misc_high;
478 u32 nested_vmx_ept_caps;
479 u32 nested_vmx_vpid_caps;
480 u64 nested_vmx_basic;
481 u64 nested_vmx_cr0_fixed0;
482 u64 nested_vmx_cr0_fixed1;
483 u64 nested_vmx_cr4_fixed0;
484 u64 nested_vmx_cr4_fixed1;
485 u64 nested_vmx_vmcs_enum;
488 #define POSTED_INTR_ON 0
489 #define POSTED_INTR_SN 1
491 /* Posted-Interrupt Descriptor */
493 u32 pir[8]; /* Posted interrupt requested */
496 /* bit 256 - Outstanding Notification */
498 /* bit 257 - Suppress Notification */
500 /* bit 271:258 - Reserved */
502 /* bit 279:272 - Notification Vector */
504 /* bit 287:280 - Reserved */
506 /* bit 319:288 - Notification Destination */
514 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
516 return test_and_set_bit(POSTED_INTR_ON,
517 (unsigned long *)&pi_desc->control);
520 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
522 return test_and_clear_bit(POSTED_INTR_ON,
523 (unsigned long *)&pi_desc->control);
526 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
528 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
531 static inline void pi_clear_sn(struct pi_desc *pi_desc)
533 return clear_bit(POSTED_INTR_SN,
534 (unsigned long *)&pi_desc->control);
537 static inline void pi_set_sn(struct pi_desc *pi_desc)
539 return set_bit(POSTED_INTR_SN,
540 (unsigned long *)&pi_desc->control);
543 static inline void pi_clear_on(struct pi_desc *pi_desc)
545 clear_bit(POSTED_INTR_ON,
546 (unsigned long *)&pi_desc->control);
549 static inline int pi_test_on(struct pi_desc *pi_desc)
551 return test_bit(POSTED_INTR_ON,
552 (unsigned long *)&pi_desc->control);
555 static inline int pi_test_sn(struct pi_desc *pi_desc)
557 return test_bit(POSTED_INTR_SN,
558 (unsigned long *)&pi_desc->control);
562 struct kvm_vcpu vcpu;
563 unsigned long host_rsp;
565 bool nmi_known_unmasked;
567 u32 idt_vectoring_info;
569 struct shared_msr_entry *guest_msrs;
572 unsigned long host_idt_base;
574 u64 msr_host_kernel_gs_base;
575 u64 msr_guest_kernel_gs_base;
577 u32 vm_entry_controls_shadow;
578 u32 vm_exit_controls_shadow;
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
584 struct loaded_vmcs vmcs01;
585 struct loaded_vmcs *loaded_vmcs;
586 bool __launched; /* temporary, used in vmx_vcpu_run */
587 struct msr_autoload {
589 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
590 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
594 u16 fs_sel, gs_sel, ldt_sel;
598 int gs_ldt_reload_needed;
599 int fs_reload_needed;
600 u64 msr_host_bndcfgs;
601 unsigned long vmcs_host_cr3; /* May not match real cr3 */
602 unsigned long vmcs_host_cr4; /* May not match real cr4 */
607 struct kvm_segment segs[8];
610 u32 bitmask; /* 4 bits per segment (1 bit per field) */
611 struct kvm_save_segment {
619 bool emulation_required;
623 /* Posted interrupt descriptor */
624 struct pi_desc pi_desc;
626 /* Support for a guest hypervisor (nested VMX) */
627 struct nested_vmx nested;
629 /* Dynamic PLE window. */
631 bool ple_window_dirty;
633 /* Support for PML */
634 #define PML_ENTITY_NUM 512
637 /* apic deadline value in host tsc */
640 u64 current_tsc_ratio;
642 bool guest_pkru_valid;
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
651 u64 msr_ia32_feature_control;
652 u64 msr_ia32_feature_control_valid_bits;
655 enum segment_cache_field {
664 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
666 return container_of(vcpu, struct vcpu_vmx, vcpu);
669 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
671 return &(to_vmx(vcpu)->pi_desc);
674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
680 static unsigned long shadow_read_only_fields[] = {
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
695 VM_EXIT_INSTRUCTION_LEN,
696 IDT_VECTORING_INFO_FIELD,
697 IDT_VECTORING_ERROR_CODE,
698 VM_EXIT_INTR_ERROR_CODE,
700 GUEST_LINEAR_ADDRESS,
701 GUEST_PHYSICAL_ADDRESS
703 static int max_shadow_read_only_fields =
704 ARRAY_SIZE(shadow_read_only_fields);
706 static unsigned long shadow_read_write_fields[] = {
713 GUEST_INTERRUPTIBILITY_INFO,
726 CPU_BASED_VM_EXEC_CONTROL,
727 VM_ENTRY_EXCEPTION_ERROR_CODE,
728 VM_ENTRY_INTR_INFO_FIELD,
729 VM_ENTRY_INSTRUCTION_LEN,
730 VM_ENTRY_EXCEPTION_ERROR_CODE,
736 static int max_shadow_read_write_fields =
737 ARRAY_SIZE(shadow_read_write_fields);
739 static const unsigned short vmcs_field_to_offset_table[] = {
740 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
741 FIELD(POSTED_INTR_NV, posted_intr_nv),
742 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
743 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
744 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
745 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
746 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
747 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
748 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
749 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
750 FIELD(GUEST_INTR_STATUS, guest_intr_status),
751 FIELD(GUEST_PML_INDEX, guest_pml_index),
752 FIELD(HOST_ES_SELECTOR, host_es_selector),
753 FIELD(HOST_CS_SELECTOR, host_cs_selector),
754 FIELD(HOST_SS_SELECTOR, host_ss_selector),
755 FIELD(HOST_DS_SELECTOR, host_ds_selector),
756 FIELD(HOST_FS_SELECTOR, host_fs_selector),
757 FIELD(HOST_GS_SELECTOR, host_gs_selector),
758 FIELD(HOST_TR_SELECTOR, host_tr_selector),
759 FIELD64(IO_BITMAP_A, io_bitmap_a),
760 FIELD64(IO_BITMAP_B, io_bitmap_b),
761 FIELD64(MSR_BITMAP, msr_bitmap),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
765 FIELD64(TSC_OFFSET, tsc_offset),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
767 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
768 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
769 FIELD64(EPT_POINTER, ept_pointer),
770 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
771 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
772 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
773 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
774 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
775 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
776 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
777 FIELD64(PML_ADDRESS, pml_address),
778 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
779 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
780 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
781 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
782 FIELD64(GUEST_PDPTR0, guest_pdptr0),
783 FIELD64(GUEST_PDPTR1, guest_pdptr1),
784 FIELD64(GUEST_PDPTR2, guest_pdptr2),
785 FIELD64(GUEST_PDPTR3, guest_pdptr3),
786 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
787 FIELD64(HOST_IA32_PAT, host_ia32_pat),
788 FIELD64(HOST_IA32_EFER, host_ia32_efer),
789 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
790 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
791 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
792 FIELD(EXCEPTION_BITMAP, exception_bitmap),
793 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
794 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
795 FIELD(CR3_TARGET_COUNT, cr3_target_count),
796 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
797 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
798 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
799 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
800 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
801 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
802 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
803 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
804 FIELD(TPR_THRESHOLD, tpr_threshold),
805 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
806 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
807 FIELD(VM_EXIT_REASON, vm_exit_reason),
808 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
809 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
810 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
811 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
812 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
813 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
814 FIELD(GUEST_ES_LIMIT, guest_es_limit),
815 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
816 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
817 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
818 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
819 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
820 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
821 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
822 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
823 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
824 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
825 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
826 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
827 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
828 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
829 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
830 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
831 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
832 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
833 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
834 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
835 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
836 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
837 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
838 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
839 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
840 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
841 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
842 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
843 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
844 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
845 FIELD(EXIT_QUALIFICATION, exit_qualification),
846 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
847 FIELD(GUEST_CR0, guest_cr0),
848 FIELD(GUEST_CR3, guest_cr3),
849 FIELD(GUEST_CR4, guest_cr4),
850 FIELD(GUEST_ES_BASE, guest_es_base),
851 FIELD(GUEST_CS_BASE, guest_cs_base),
852 FIELD(GUEST_SS_BASE, guest_ss_base),
853 FIELD(GUEST_DS_BASE, guest_ds_base),
854 FIELD(GUEST_FS_BASE, guest_fs_base),
855 FIELD(GUEST_GS_BASE, guest_gs_base),
856 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
857 FIELD(GUEST_TR_BASE, guest_tr_base),
858 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
859 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
860 FIELD(GUEST_DR7, guest_dr7),
861 FIELD(GUEST_RSP, guest_rsp),
862 FIELD(GUEST_RIP, guest_rip),
863 FIELD(GUEST_RFLAGS, guest_rflags),
864 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
865 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
866 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
867 FIELD(HOST_CR0, host_cr0),
868 FIELD(HOST_CR3, host_cr3),
869 FIELD(HOST_CR4, host_cr4),
870 FIELD(HOST_FS_BASE, host_fs_base),
871 FIELD(HOST_GS_BASE, host_gs_base),
872 FIELD(HOST_TR_BASE, host_tr_base),
873 FIELD(HOST_GDTR_BASE, host_gdtr_base),
874 FIELD(HOST_IDTR_BASE, host_idtr_base),
875 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
876 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
877 FIELD(HOST_RSP, host_rsp),
878 FIELD(HOST_RIP, host_rip),
881 static inline short vmcs_field_to_offset(unsigned long field)
883 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
885 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
886 vmcs_field_to_offset_table[field] == 0)
889 return vmcs_field_to_offset_table[field];
892 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
894 return to_vmx(vcpu)->nested.cached_vmcs12;
897 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
899 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
900 if (is_error_page(page))
906 static void nested_release_page(struct page *page)
908 kvm_release_page_dirty(page);
911 static void nested_release_page_clean(struct page *page)
913 kvm_release_page_clean(page);
916 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
917 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
918 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
919 static bool vmx_xsaves_supported(void);
920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
922 struct kvm_segment *var, int seg);
923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
924 struct kvm_segment *var, int seg);
925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
929 static int alloc_identity_pagetable(struct kvm *kvm);
931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
940 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
941 * can find which vCPU should be waken up.
943 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
944 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
949 VMX_MSR_BITMAP_LEGACY,
950 VMX_MSR_BITMAP_LONGMODE,
951 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
953 VMX_MSR_BITMAP_LEGACY_X2APIC,
954 VMX_MSR_BITMAP_LONGMODE_X2APIC,
960 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
962 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
965 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
966 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
968 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
969 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
970 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
971 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
973 static bool cpu_has_load_ia32_efer;
974 static bool cpu_has_load_perf_global_ctrl;
976 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
977 static DEFINE_SPINLOCK(vmx_vpid_lock);
979 static struct vmcs_config {
984 u32 pin_based_exec_ctrl;
985 u32 cpu_based_exec_ctrl;
986 u32 cpu_based_2nd_exec_ctrl;
991 static struct vmx_capability {
996 #define VMX_SEGMENT_FIELD(seg) \
997 [VCPU_SREG_##seg] = { \
998 .selector = GUEST_##seg##_SELECTOR, \
999 .base = GUEST_##seg##_BASE, \
1000 .limit = GUEST_##seg##_LIMIT, \
1001 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1004 static const struct kvm_vmx_segment_field {
1009 } kvm_vmx_segment_fields[] = {
1010 VMX_SEGMENT_FIELD(CS),
1011 VMX_SEGMENT_FIELD(DS),
1012 VMX_SEGMENT_FIELD(ES),
1013 VMX_SEGMENT_FIELD(FS),
1014 VMX_SEGMENT_FIELD(GS),
1015 VMX_SEGMENT_FIELD(SS),
1016 VMX_SEGMENT_FIELD(TR),
1017 VMX_SEGMENT_FIELD(LDTR),
1020 static u64 host_efer;
1022 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1025 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026 * away by decrementing the array size.
1028 static const u32 vmx_msr_index[] = {
1029 #ifdef CONFIG_X86_64
1030 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1035 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038 INTR_INFO_VALID_MASK)) ==
1039 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1042 static inline bool is_debug(u32 intr_info)
1044 return is_exception_n(intr_info, DB_VECTOR);
1047 static inline bool is_breakpoint(u32 intr_info)
1049 return is_exception_n(intr_info, BP_VECTOR);
1052 static inline bool is_page_fault(u32 intr_info)
1054 return is_exception_n(intr_info, PF_VECTOR);
1057 static inline bool is_no_device(u32 intr_info)
1059 return is_exception_n(intr_info, NM_VECTOR);
1062 static inline bool is_invalid_opcode(u32 intr_info)
1064 return is_exception_n(intr_info, UD_VECTOR);
1067 static inline bool is_external_interrupt(u32 intr_info)
1069 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1073 static inline bool is_machine_check(u32 intr_info)
1075 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076 INTR_INFO_VALID_MASK)) ==
1077 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 return vmcs_config.cpu_based_exec_ctrl &
1098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 return vmcs_config.cpu_based_2nd_exec_ctrl &
1104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 return vmcs_config.cpu_based_2nd_exec_ctrl &
1110 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 return vmcs_config.cpu_based_2nd_exec_ctrl &
1116 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 return vmcs_config.cpu_based_2nd_exec_ctrl &
1122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1126 * Comment's format: document - errata name - stepping - processor name.
1128 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130 static u32 vmx_preemption_cpu_tfms[] = {
1131 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1133 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1142 * 320767.pdf - AAP86 - B1 -
1143 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 u32 eax = cpuid_eax(0x00000001), i;
1162 /* Clear the reserved bits */
1163 eax &= ~(0x3U << 14 | 0xfU << 28);
1164 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1165 if (eax == vmx_preemption_cpu_tfms[i])
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1173 return vmcs_config.pin_based_exec_ctrl &
1174 PIN_BASED_VMX_PREEMPTION_TIMER;
1177 static inline bool cpu_has_vmx_posted_intr(void)
1179 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1183 static inline bool cpu_has_vmx_apicv(void)
1185 return cpu_has_vmx_apic_register_virt() &&
1186 cpu_has_vmx_virtual_intr_delivery() &&
1187 cpu_has_vmx_posted_intr();
1190 static inline bool cpu_has_vmx_flexpriority(void)
1192 return cpu_has_vmx_tpr_shadow() &&
1193 cpu_has_vmx_virtualize_apic_accesses();
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1213 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1216 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 return vmx_capability.ept & VMX_EPT_AD_BIT;
1221 static inline bool cpu_has_vmx_invept_context(void)
1223 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1226 static inline bool cpu_has_vmx_invept_global(void)
1228 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1231 static inline bool cpu_has_vmx_invvpid_single(void)
1233 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1236 static inline bool cpu_has_vmx_invvpid_global(void)
1238 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1241 static inline bool cpu_has_vmx_invvpid(void)
1243 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1246 static inline bool cpu_has_vmx_ept(void)
1248 return vmcs_config.cpu_based_2nd_exec_ctrl &
1249 SECONDARY_EXEC_ENABLE_EPT;
1252 static inline bool cpu_has_vmx_unrestricted_guest(void)
1254 return vmcs_config.cpu_based_2nd_exec_ctrl &
1255 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1258 static inline bool cpu_has_vmx_ple(void)
1260 return vmcs_config.cpu_based_2nd_exec_ctrl &
1261 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1264 static inline bool cpu_has_vmx_basic_inout(void)
1266 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1269 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1271 return flexpriority_enabled && lapic_in_kernel(vcpu);
1274 static inline bool cpu_has_vmx_vpid(void)
1276 return vmcs_config.cpu_based_2nd_exec_ctrl &
1277 SECONDARY_EXEC_ENABLE_VPID;
1280 static inline bool cpu_has_vmx_rdtscp(void)
1282 return vmcs_config.cpu_based_2nd_exec_ctrl &
1283 SECONDARY_EXEC_RDTSCP;
1286 static inline bool cpu_has_vmx_invpcid(void)
1288 return vmcs_config.cpu_based_2nd_exec_ctrl &
1289 SECONDARY_EXEC_ENABLE_INVPCID;
1292 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 return vmcs_config.cpu_based_2nd_exec_ctrl &
1295 SECONDARY_EXEC_WBINVD_EXITING;
1298 static inline bool cpu_has_vmx_shadow_vmcs(void)
1301 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1302 /* check if the cpu supports writing r/o exit information fields */
1303 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1306 return vmcs_config.cpu_based_2nd_exec_ctrl &
1307 SECONDARY_EXEC_SHADOW_VMCS;
1310 static inline bool cpu_has_vmx_pml(void)
1312 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1315 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 return vmcs_config.cpu_based_2nd_exec_ctrl &
1318 SECONDARY_EXEC_TSC_SCALING;
1321 static inline bool report_flexpriority(void)
1323 return flexpriority_enabled;
1326 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1328 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1331 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1333 return vmcs12->cpu_based_vm_exec_control & bit;
1336 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1338 return (vmcs12->cpu_based_vm_exec_control &
1339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340 (vmcs12->secondary_vm_exec_control & bit);
1343 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1345 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1348 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1350 return vmcs12->pin_based_vm_exec_control &
1351 PIN_BASED_VMX_PREEMPTION_TIMER;
1354 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1356 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1359 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1361 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362 vmx_xsaves_supported();
1365 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1367 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1370 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1372 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1375 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1377 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1380 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1382 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1385 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1387 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1390 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1392 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1395 static inline bool is_nmi(u32 intr_info)
1397 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1398 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1401 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1403 unsigned long exit_qualification);
1404 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1405 struct vmcs12 *vmcs12,
1406 u32 reason, unsigned long qualification);
1408 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1412 for (i = 0; i < vmx->nmsrs; ++i)
1413 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1418 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1424 } operand = { vpid, 0, gva };
1426 asm volatile (__ex(ASM_VMX_INVVPID)
1427 /* CF==1 or ZF==1 --> rc = -1 */
1428 "; ja 1f ; ud2 ; 1:"
1429 : : "a"(&operand), "c"(ext) : "cc", "memory");
1432 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1436 } operand = {eptp, gpa};
1438 asm volatile (__ex(ASM_VMX_INVEPT)
1439 /* CF==1 or ZF==1 --> rc = -1 */
1440 "; ja 1f ; ud2 ; 1:\n"
1441 : : "a" (&operand), "c" (ext) : "cc", "memory");
1444 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1448 i = __find_msr_index(vmx, msr);
1450 return &vmx->guest_msrs[i];
1454 static void vmcs_clear(struct vmcs *vmcs)
1456 u64 phys_addr = __pa(vmcs);
1459 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1460 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1463 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1467 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1469 vmcs_clear(loaded_vmcs->vmcs);
1470 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1471 vmcs_clear(loaded_vmcs->shadow_vmcs);
1472 loaded_vmcs->cpu = -1;
1473 loaded_vmcs->launched = 0;
1476 static void vmcs_load(struct vmcs *vmcs)
1478 u64 phys_addr = __pa(vmcs);
1481 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1482 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1485 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1489 #ifdef CONFIG_KEXEC_CORE
1491 * This bitmap is used to indicate whether the vmclear
1492 * operation is enabled on all cpus. All disabled by
1495 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1497 static inline void crash_enable_local_vmclear(int cpu)
1499 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1502 static inline void crash_disable_local_vmclear(int cpu)
1504 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1507 static inline int crash_local_vmclear_enabled(int cpu)
1509 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1512 static void crash_vmclear_local_loaded_vmcss(void)
1514 int cpu = raw_smp_processor_id();
1515 struct loaded_vmcs *v;
1517 if (!crash_local_vmclear_enabled(cpu))
1520 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1521 loaded_vmcss_on_cpu_link)
1522 vmcs_clear(v->vmcs);
1525 static inline void crash_enable_local_vmclear(int cpu) { }
1526 static inline void crash_disable_local_vmclear(int cpu) { }
1527 #endif /* CONFIG_KEXEC_CORE */
1529 static void __loaded_vmcs_clear(void *arg)
1531 struct loaded_vmcs *loaded_vmcs = arg;
1532 int cpu = raw_smp_processor_id();
1534 if (loaded_vmcs->cpu != cpu)
1535 return; /* vcpu migration can race with cpu offline */
1536 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1537 per_cpu(current_vmcs, cpu) = NULL;
1538 crash_disable_local_vmclear(cpu);
1539 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1542 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543 * is before setting loaded_vmcs->vcpu to -1 which is done in
1544 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545 * then adds the vmcs into percpu list before it is deleted.
1549 loaded_vmcs_init(loaded_vmcs);
1550 crash_enable_local_vmclear(cpu);
1553 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1555 int cpu = loaded_vmcs->cpu;
1558 smp_call_function_single(cpu,
1559 __loaded_vmcs_clear, loaded_vmcs, 1);
1562 static inline void vpid_sync_vcpu_single(int vpid)
1567 if (cpu_has_vmx_invvpid_single())
1568 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1571 static inline void vpid_sync_vcpu_global(void)
1573 if (cpu_has_vmx_invvpid_global())
1574 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1577 static inline void vpid_sync_context(int vpid)
1579 if (cpu_has_vmx_invvpid_single())
1580 vpid_sync_vcpu_single(vpid);
1582 vpid_sync_vcpu_global();
1585 static inline void ept_sync_global(void)
1587 if (cpu_has_vmx_invept_global())
1588 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1591 static inline void ept_sync_context(u64 eptp)
1594 if (cpu_has_vmx_invept_context())
1595 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1601 static __always_inline void vmcs_check16(unsigned long field)
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1604 "16-bit accessor invalid for 64-bit field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1606 "16-bit accessor invalid for 64-bit high field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1608 "16-bit accessor invalid for 32-bit high field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610 "16-bit accessor invalid for natural width field");
1613 static __always_inline void vmcs_check32(unsigned long field)
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616 "32-bit accessor invalid for 16-bit field");
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1618 "32-bit accessor invalid for natural width field");
1621 static __always_inline void vmcs_check64(unsigned long field)
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1624 "64-bit accessor invalid for 16-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1626 "64-bit accessor invalid for 64-bit high field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1628 "64-bit accessor invalid for 32-bit field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630 "64-bit accessor invalid for natural width field");
1633 static __always_inline void vmcs_checkl(unsigned long field)
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636 "Natural width accessor invalid for 16-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1638 "Natural width accessor invalid for 64-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640 "Natural width accessor invalid for 64-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642 "Natural width accessor invalid for 32-bit field");
1645 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1647 unsigned long value;
1649 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1650 : "=a"(value) : "d"(field) : "cc");
1654 static __always_inline u16 vmcs_read16(unsigned long field)
1656 vmcs_check16(field);
1657 return __vmcs_readl(field);
1660 static __always_inline u32 vmcs_read32(unsigned long field)
1662 vmcs_check32(field);
1663 return __vmcs_readl(field);
1666 static __always_inline u64 vmcs_read64(unsigned long field)
1668 vmcs_check64(field);
1669 #ifdef CONFIG_X86_64
1670 return __vmcs_readl(field);
1672 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1676 static __always_inline unsigned long vmcs_readl(unsigned long field)
1679 return __vmcs_readl(field);
1682 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1684 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1685 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1689 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1693 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1694 : "=q"(error) : "a"(value), "d"(field) : "cc");
1695 if (unlikely(error))
1696 vmwrite_error(field, value);
1699 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1701 vmcs_check16(field);
1702 __vmcs_writel(field, value);
1705 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1707 vmcs_check32(field);
1708 __vmcs_writel(field, value);
1711 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1713 vmcs_check64(field);
1714 __vmcs_writel(field, value);
1715 #ifndef CONFIG_X86_64
1717 __vmcs_writel(field+1, value >> 32);
1721 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1724 __vmcs_writel(field, value);
1727 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1729 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1730 "vmcs_clear_bits does not support 64-bit fields");
1731 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1734 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1736 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1737 "vmcs_set_bits does not support 64-bit fields");
1738 __vmcs_writel(field, __vmcs_readl(field) | mask);
1741 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1743 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1746 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1748 vmcs_write32(VM_ENTRY_CONTROLS, val);
1749 vmx->vm_entry_controls_shadow = val;
1752 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1754 if (vmx->vm_entry_controls_shadow != val)
1755 vm_entry_controls_init(vmx, val);
1758 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1760 return vmx->vm_entry_controls_shadow;
1764 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1766 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1769 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1771 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1774 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1776 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1779 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1781 vmcs_write32(VM_EXIT_CONTROLS, val);
1782 vmx->vm_exit_controls_shadow = val;
1785 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1787 if (vmx->vm_exit_controls_shadow != val)
1788 vm_exit_controls_init(vmx, val);
1791 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1793 return vmx->vm_exit_controls_shadow;
1797 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1799 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1802 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1804 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1807 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1809 vmx->segment_cache.bitmask = 0;
1812 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1816 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1818 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1819 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1820 vmx->segment_cache.bitmask = 0;
1822 ret = vmx->segment_cache.bitmask & mask;
1823 vmx->segment_cache.bitmask |= mask;
1827 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1829 u16 *p = &vmx->segment_cache.seg[seg].selector;
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1832 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1836 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1838 ulong *p = &vmx->segment_cache.seg[seg].base;
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1841 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1845 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1847 u32 *p = &vmx->segment_cache.seg[seg].limit;
1849 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1850 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1854 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1856 u32 *p = &vmx->segment_cache.seg[seg].ar;
1858 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1859 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1863 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1867 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1868 (1u << DB_VECTOR) | (1u << AC_VECTOR);
1869 if ((vcpu->guest_debug &
1870 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1871 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1872 eb |= 1u << BP_VECTOR;
1873 if (to_vmx(vcpu)->rmode.vm86_active)
1876 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1878 /* When we are running a nested L2 guest and L1 specified for it a
1879 * certain exception bitmap, we must trap the same exceptions and pass
1880 * them to L1. When running L2, we will only handle the exceptions
1881 * specified above if L1 did not want them.
1883 if (is_guest_mode(vcpu))
1884 eb |= get_vmcs12(vcpu)->exception_bitmap;
1886 vmcs_write32(EXCEPTION_BITMAP, eb);
1889 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1890 unsigned long entry, unsigned long exit)
1892 vm_entry_controls_clearbit(vmx, entry);
1893 vm_exit_controls_clearbit(vmx, exit);
1896 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1899 struct msr_autoload *m = &vmx->msr_autoload;
1903 if (cpu_has_load_ia32_efer) {
1904 clear_atomic_switch_msr_special(vmx,
1905 VM_ENTRY_LOAD_IA32_EFER,
1906 VM_EXIT_LOAD_IA32_EFER);
1910 case MSR_CORE_PERF_GLOBAL_CTRL:
1911 if (cpu_has_load_perf_global_ctrl) {
1912 clear_atomic_switch_msr_special(vmx,
1913 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1914 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1920 for (i = 0; i < m->nr; ++i)
1921 if (m->guest[i].index == msr)
1927 m->guest[i] = m->guest[m->nr];
1928 m->host[i] = m->host[m->nr];
1929 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1930 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1933 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1934 unsigned long entry, unsigned long exit,
1935 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1936 u64 guest_val, u64 host_val)
1938 vmcs_write64(guest_val_vmcs, guest_val);
1939 vmcs_write64(host_val_vmcs, host_val);
1940 vm_entry_controls_setbit(vmx, entry);
1941 vm_exit_controls_setbit(vmx, exit);
1944 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1945 u64 guest_val, u64 host_val)
1948 struct msr_autoload *m = &vmx->msr_autoload;
1952 if (cpu_has_load_ia32_efer) {
1953 add_atomic_switch_msr_special(vmx,
1954 VM_ENTRY_LOAD_IA32_EFER,
1955 VM_EXIT_LOAD_IA32_EFER,
1958 guest_val, host_val);
1962 case MSR_CORE_PERF_GLOBAL_CTRL:
1963 if (cpu_has_load_perf_global_ctrl) {
1964 add_atomic_switch_msr_special(vmx,
1965 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1966 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1967 GUEST_IA32_PERF_GLOBAL_CTRL,
1968 HOST_IA32_PERF_GLOBAL_CTRL,
1969 guest_val, host_val);
1973 case MSR_IA32_PEBS_ENABLE:
1974 /* PEBS needs a quiescent period after being disabled (to write
1975 * a record). Disabling PEBS through VMX MSR swapping doesn't
1976 * provide that period, so a CPU could write host's record into
1979 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1982 for (i = 0; i < m->nr; ++i)
1983 if (m->guest[i].index == msr)
1986 if (i == NR_AUTOLOAD_MSRS) {
1987 printk_once(KERN_WARNING "Not enough msr switch entries. "
1988 "Can't add msr %x\n", msr);
1990 } else if (i == m->nr) {
1992 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1993 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1996 m->guest[i].index = msr;
1997 m->guest[i].value = guest_val;
1998 m->host[i].index = msr;
1999 m->host[i].value = host_val;
2002 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2004 u64 guest_efer = vmx->vcpu.arch.efer;
2005 u64 ignore_bits = 0;
2009 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2010 * host CPUID is more efficient than testing guest CPUID
2011 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2013 if (boot_cpu_has(X86_FEATURE_SMEP))
2014 guest_efer |= EFER_NX;
2015 else if (!(guest_efer & EFER_NX))
2016 ignore_bits |= EFER_NX;
2020 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2022 ignore_bits |= EFER_SCE;
2023 #ifdef CONFIG_X86_64
2024 ignore_bits |= EFER_LMA | EFER_LME;
2025 /* SCE is meaningful only in long mode on Intel */
2026 if (guest_efer & EFER_LMA)
2027 ignore_bits &= ~(u64)EFER_SCE;
2030 clear_atomic_switch_msr(vmx, MSR_EFER);
2033 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034 * On CPUs that support "load IA32_EFER", always switch EFER
2035 * atomically, since it's faster than switching it manually.
2037 if (cpu_has_load_ia32_efer ||
2038 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2039 if (!(guest_efer & EFER_LMA))
2040 guest_efer &= ~EFER_LME;
2041 if (guest_efer != host_efer)
2042 add_atomic_switch_msr(vmx, MSR_EFER,
2043 guest_efer, host_efer);
2046 guest_efer &= ~ignore_bits;
2047 guest_efer |= host_efer & ignore_bits;
2049 vmx->guest_msrs[efer_offset].data = guest_efer;
2050 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2056 #ifdef CONFIG_X86_32
2058 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059 * VMCS rather than the segment table. KVM uses this helper to figure
2060 * out the current bases to poke them into the VMCS before entry.
2062 static unsigned long segment_base(u16 selector)
2064 struct desc_struct *table;
2067 if (!(selector & ~SEGMENT_RPL_MASK))
2070 table = get_current_gdt_ro();
2072 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2073 u16 ldt_selector = kvm_read_ldt();
2075 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2078 table = (struct desc_struct *)segment_base(ldt_selector);
2080 v = get_desc_base(&table[selector >> 3]);
2085 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2087 struct vcpu_vmx *vmx = to_vmx(vcpu);
2090 if (vmx->host_state.loaded)
2093 vmx->host_state.loaded = 1;
2095 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2096 * allow segment selectors with cpl > 0 or ti == 1.
2098 vmx->host_state.ldt_sel = kvm_read_ldt();
2099 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2100 savesegment(fs, vmx->host_state.fs_sel);
2101 if (!(vmx->host_state.fs_sel & 7)) {
2102 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2103 vmx->host_state.fs_reload_needed = 0;
2105 vmcs_write16(HOST_FS_SELECTOR, 0);
2106 vmx->host_state.fs_reload_needed = 1;
2108 savesegment(gs, vmx->host_state.gs_sel);
2109 if (!(vmx->host_state.gs_sel & 7))
2110 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2112 vmcs_write16(HOST_GS_SELECTOR, 0);
2113 vmx->host_state.gs_ldt_reload_needed = 1;
2116 #ifdef CONFIG_X86_64
2117 savesegment(ds, vmx->host_state.ds_sel);
2118 savesegment(es, vmx->host_state.es_sel);
2121 #ifdef CONFIG_X86_64
2122 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2123 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2125 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2126 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2129 #ifdef CONFIG_X86_64
2130 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2131 if (is_long_mode(&vmx->vcpu))
2132 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2134 if (boot_cpu_has(X86_FEATURE_MPX))
2135 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2136 for (i = 0; i < vmx->save_nmsrs; ++i)
2137 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2138 vmx->guest_msrs[i].data,
2139 vmx->guest_msrs[i].mask);
2142 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2144 if (!vmx->host_state.loaded)
2147 ++vmx->vcpu.stat.host_state_reload;
2148 vmx->host_state.loaded = 0;
2149 #ifdef CONFIG_X86_64
2150 if (is_long_mode(&vmx->vcpu))
2151 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2153 if (vmx->host_state.gs_ldt_reload_needed) {
2154 kvm_load_ldt(vmx->host_state.ldt_sel);
2155 #ifdef CONFIG_X86_64
2156 load_gs_index(vmx->host_state.gs_sel);
2158 loadsegment(gs, vmx->host_state.gs_sel);
2161 if (vmx->host_state.fs_reload_needed)
2162 loadsegment(fs, vmx->host_state.fs_sel);
2163 #ifdef CONFIG_X86_64
2164 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2165 loadsegment(ds, vmx->host_state.ds_sel);
2166 loadsegment(es, vmx->host_state.es_sel);
2169 invalidate_tss_limit();
2170 #ifdef CONFIG_X86_64
2171 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2173 if (vmx->host_state.msr_host_bndcfgs)
2174 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2175 load_fixmap_gdt(raw_smp_processor_id());
2178 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2181 __vmx_load_host_state(vmx);
2185 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2187 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2188 struct pi_desc old, new;
2191 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2192 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2193 !kvm_vcpu_apicv_active(vcpu))
2197 old.control = new.control = pi_desc->control;
2200 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2201 * are two possible cases:
2202 * 1. After running 'pre_block', context switch
2203 * happened. For this case, 'sn' was set in
2204 * vmx_vcpu_put(), so we need to clear it here.
2205 * 2. After running 'pre_block', we were blocked,
2206 * and woken up by some other guy. For this case,
2207 * we don't need to do anything, 'pi_post_block'
2208 * will do everything for us. However, we cannot
2209 * check whether it is case #1 or case #2 here
2210 * (maybe, not needed), so we also clear sn here,
2211 * I think it is not a big deal.
2213 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2214 if (vcpu->cpu != cpu) {
2215 dest = cpu_physical_id(cpu);
2217 if (x2apic_enabled())
2220 new.ndst = (dest << 8) & 0xFF00;
2223 /* set 'NV' to 'notification vector' */
2224 new.nv = POSTED_INTR_VECTOR;
2227 /* Allow posting non-urgent interrupts */
2229 } while (cmpxchg(&pi_desc->control, old.control,
2230 new.control) != old.control);
2233 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2235 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2236 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2240 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241 * vcpu mutex is already taken.
2243 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2245 struct vcpu_vmx *vmx = to_vmx(vcpu);
2246 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2248 if (!already_loaded) {
2249 loaded_vmcs_clear(vmx->loaded_vmcs);
2250 local_irq_disable();
2251 crash_disable_local_vmclear(cpu);
2254 * Read loaded_vmcs->cpu should be before fetching
2255 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256 * See the comments in __loaded_vmcs_clear().
2260 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261 &per_cpu(loaded_vmcss_on_cpu, cpu));
2262 crash_enable_local_vmclear(cpu);
2266 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268 vmcs_load(vmx->loaded_vmcs->vmcs);
2271 if (!already_loaded) {
2272 void *gdt = get_current_gdt_ro();
2273 unsigned long sysenter_esp;
2275 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2278 * Linux uses per-cpu TSS and GDT, so set these when switching
2279 * processors. See 22.2.4.
2281 vmcs_writel(HOST_TR_BASE,
2282 (unsigned long)this_cpu_ptr(&cpu_tss));
2283 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2286 * VM exits change the host TR limit to 0x67 after a VM
2287 * exit. This is okay, since 0x67 covers everything except
2288 * the IO bitmap and have have code to handle the IO bitmap
2289 * being lost after a VM exit.
2291 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2293 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2296 vmx->loaded_vmcs->cpu = cpu;
2299 /* Setup TSC multiplier */
2300 if (kvm_has_tsc_control &&
2301 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302 decache_tsc_multiplier(vmx);
2304 vmx_vcpu_pi_load(vcpu, cpu);
2305 vmx->host_pkru = read_pkru();
2308 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2310 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2312 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2313 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2314 !kvm_vcpu_apicv_active(vcpu))
2317 /* Set SN when the vCPU is preempted */
2318 if (vcpu->preempted)
2322 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2324 vmx_vcpu_pi_put(vcpu);
2326 __vmx_load_host_state(to_vmx(vcpu));
2329 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2332 * Return the cr0 value that a nested guest would read. This is a combination
2333 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2334 * its hypervisor (cr0_read_shadow).
2336 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2338 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2339 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2341 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2343 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2344 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2347 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2349 unsigned long rflags, save_rflags;
2351 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2352 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2353 rflags = vmcs_readl(GUEST_RFLAGS);
2354 if (to_vmx(vcpu)->rmode.vm86_active) {
2355 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2356 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2357 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2359 to_vmx(vcpu)->rflags = rflags;
2361 return to_vmx(vcpu)->rflags;
2364 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2366 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2367 to_vmx(vcpu)->rflags = rflags;
2368 if (to_vmx(vcpu)->rmode.vm86_active) {
2369 to_vmx(vcpu)->rmode.save_rflags = rflags;
2370 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2372 vmcs_writel(GUEST_RFLAGS, rflags);
2375 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2377 return to_vmx(vcpu)->guest_pkru;
2380 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2382 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2385 if (interruptibility & GUEST_INTR_STATE_STI)
2386 ret |= KVM_X86_SHADOW_INT_STI;
2387 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2388 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2393 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2395 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2396 u32 interruptibility = interruptibility_old;
2398 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2400 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2401 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2402 else if (mask & KVM_X86_SHADOW_INT_STI)
2403 interruptibility |= GUEST_INTR_STATE_STI;
2405 if ((interruptibility != interruptibility_old))
2406 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2409 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2413 rip = kvm_rip_read(vcpu);
2414 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2415 kvm_rip_write(vcpu, rip);
2417 /* skipping an emulated instruction also counts */
2418 vmx_set_interrupt_shadow(vcpu, 0);
2422 * KVM wants to inject page-faults which it got to the guest. This function
2423 * checks whether in a nested guest, we need to inject them to L1 or L2.
2425 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
2427 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2428 unsigned int nr = vcpu->arch.exception.nr;
2430 if (!((vmcs12->exception_bitmap & (1u << nr)) ||
2431 (nr == PF_VECTOR && vcpu->arch.exception.nested_apf)))
2434 if (vcpu->arch.exception.nested_apf) {
2435 vmcs_write32(VM_EXIT_INTR_ERROR_CODE, vcpu->arch.exception.error_code);
2436 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2437 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
2438 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
2439 vcpu->arch.apf.nested_apf_token);
2443 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2444 vmcs_read32(VM_EXIT_INTR_INFO),
2445 vmcs_readl(EXIT_QUALIFICATION));
2449 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2451 struct vcpu_vmx *vmx = to_vmx(vcpu);
2452 unsigned nr = vcpu->arch.exception.nr;
2453 bool has_error_code = vcpu->arch.exception.has_error_code;
2454 bool reinject = vcpu->arch.exception.reinject;
2455 u32 error_code = vcpu->arch.exception.error_code;
2456 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2458 if (!reinject && is_guest_mode(vcpu) &&
2459 nested_vmx_check_exception(vcpu))
2462 if (has_error_code) {
2463 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2464 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2467 if (vmx->rmode.vm86_active) {
2469 if (kvm_exception_is_soft(nr))
2470 inc_eip = vcpu->arch.event_exit_inst_len;
2471 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2472 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2476 if (kvm_exception_is_soft(nr)) {
2477 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2478 vmx->vcpu.arch.event_exit_inst_len);
2479 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2481 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2483 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2486 static bool vmx_rdtscp_supported(void)
2488 return cpu_has_vmx_rdtscp();
2491 static bool vmx_invpcid_supported(void)
2493 return cpu_has_vmx_invpcid() && enable_ept;
2497 * Swap MSR entry in host/guest MSR entry array.
2499 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2501 struct shared_msr_entry tmp;
2503 tmp = vmx->guest_msrs[to];
2504 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2505 vmx->guest_msrs[from] = tmp;
2508 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2510 unsigned long *msr_bitmap;
2512 if (is_guest_mode(vcpu))
2513 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2514 else if (cpu_has_secondary_exec_ctrls() &&
2515 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2516 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2517 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2518 if (is_long_mode(vcpu))
2519 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2521 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2523 if (is_long_mode(vcpu))
2524 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2526 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2529 if (is_long_mode(vcpu))
2530 msr_bitmap = vmx_msr_bitmap_longmode;
2532 msr_bitmap = vmx_msr_bitmap_legacy;
2535 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2539 * Set up the vmcs to automatically save and restore system
2540 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2541 * mode, as fiddling with msrs is very expensive.
2543 static void setup_msrs(struct vcpu_vmx *vmx)
2545 int save_nmsrs, index;
2548 #ifdef CONFIG_X86_64
2549 if (is_long_mode(&vmx->vcpu)) {
2550 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2552 move_msr_up(vmx, index, save_nmsrs++);
2553 index = __find_msr_index(vmx, MSR_LSTAR);
2555 move_msr_up(vmx, index, save_nmsrs++);
2556 index = __find_msr_index(vmx, MSR_CSTAR);
2558 move_msr_up(vmx, index, save_nmsrs++);
2559 index = __find_msr_index(vmx, MSR_TSC_AUX);
2560 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2561 move_msr_up(vmx, index, save_nmsrs++);
2563 * MSR_STAR is only needed on long mode guests, and only
2564 * if efer.sce is enabled.
2566 index = __find_msr_index(vmx, MSR_STAR);
2567 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2568 move_msr_up(vmx, index, save_nmsrs++);
2571 index = __find_msr_index(vmx, MSR_EFER);
2572 if (index >= 0 && update_transition_efer(vmx, index))
2573 move_msr_up(vmx, index, save_nmsrs++);
2575 vmx->save_nmsrs = save_nmsrs;
2577 if (cpu_has_vmx_msr_bitmap())
2578 vmx_set_msr_bitmap(&vmx->vcpu);
2582 * reads and returns guest's timestamp counter "register"
2583 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2584 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2586 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2588 u64 host_tsc, tsc_offset;
2591 tsc_offset = vmcs_read64(TSC_OFFSET);
2592 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2596 * writes 'offset' into guest's timestamp counter offset register
2598 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2600 if (is_guest_mode(vcpu)) {
2602 * We're here if L1 chose not to trap WRMSR to TSC. According
2603 * to the spec, this should set L1's TSC; The offset that L1
2604 * set for L2 remains unchanged, and still needs to be added
2605 * to the newly set TSC to get L2's TSC.
2607 struct vmcs12 *vmcs12;
2608 /* recalculate vmcs02.TSC_OFFSET: */
2609 vmcs12 = get_vmcs12(vcpu);
2610 vmcs_write64(TSC_OFFSET, offset +
2611 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2612 vmcs12->tsc_offset : 0));
2614 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2615 vmcs_read64(TSC_OFFSET), offset);
2616 vmcs_write64(TSC_OFFSET, offset);
2620 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2622 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2623 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2627 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2628 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2629 * all guests if the "nested" module option is off, and can also be disabled
2630 * for a single guest by disabling its VMX cpuid bit.
2632 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2634 return nested && guest_cpuid_has_vmx(vcpu);
2638 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2639 * returned for the various VMX controls MSRs when nested VMX is enabled.
2640 * The same values should also be used to verify that vmcs12 control fields are
2641 * valid during nested entry from L1 to L2.
2642 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2643 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2644 * bit in the high half is on if the corresponding bit in the control field
2645 * may be on. See also vmx_control_verify().
2647 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2650 * Note that as a general rule, the high half of the MSRs (bits in
2651 * the control fields which may be 1) should be initialized by the
2652 * intersection of the underlying hardware's MSR (i.e., features which
2653 * can be supported) and the list of features we want to expose -
2654 * because they are known to be properly supported in our code.
2655 * Also, usually, the low half of the MSRs (bits which must be 1) can
2656 * be set to 0, meaning that L1 may turn off any of these bits. The
2657 * reason is that if one of these bits is necessary, it will appear
2658 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2659 * fields of vmcs01 and vmcs02, will turn these bits off - and
2660 * nested_vmx_exit_handled() will not pass related exits to L1.
2661 * These rules have exceptions below.
2664 /* pin-based controls */
2665 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2666 vmx->nested.nested_vmx_pinbased_ctls_low,
2667 vmx->nested.nested_vmx_pinbased_ctls_high);
2668 vmx->nested.nested_vmx_pinbased_ctls_low |=
2669 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2670 vmx->nested.nested_vmx_pinbased_ctls_high &=
2671 PIN_BASED_EXT_INTR_MASK |
2672 PIN_BASED_NMI_EXITING |
2673 PIN_BASED_VIRTUAL_NMIS;
2674 vmx->nested.nested_vmx_pinbased_ctls_high |=
2675 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2676 PIN_BASED_VMX_PREEMPTION_TIMER;
2677 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2678 vmx->nested.nested_vmx_pinbased_ctls_high |=
2679 PIN_BASED_POSTED_INTR;
2682 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2683 vmx->nested.nested_vmx_exit_ctls_low,
2684 vmx->nested.nested_vmx_exit_ctls_high);
2685 vmx->nested.nested_vmx_exit_ctls_low =
2686 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2688 vmx->nested.nested_vmx_exit_ctls_high &=
2689 #ifdef CONFIG_X86_64
2690 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2692 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2693 vmx->nested.nested_vmx_exit_ctls_high |=
2694 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2695 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2696 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2698 if (kvm_mpx_supported())
2699 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2701 /* We support free control of debug control saving. */
2702 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2704 /* entry controls */
2705 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2706 vmx->nested.nested_vmx_entry_ctls_low,
2707 vmx->nested.nested_vmx_entry_ctls_high);
2708 vmx->nested.nested_vmx_entry_ctls_low =
2709 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2710 vmx->nested.nested_vmx_entry_ctls_high &=
2711 #ifdef CONFIG_X86_64
2712 VM_ENTRY_IA32E_MODE |
2714 VM_ENTRY_LOAD_IA32_PAT;
2715 vmx->nested.nested_vmx_entry_ctls_high |=
2716 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2717 if (kvm_mpx_supported())
2718 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2720 /* We support free control of debug control loading. */
2721 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2723 /* cpu-based controls */
2724 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2725 vmx->nested.nested_vmx_procbased_ctls_low,
2726 vmx->nested.nested_vmx_procbased_ctls_high);
2727 vmx->nested.nested_vmx_procbased_ctls_low =
2728 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2729 vmx->nested.nested_vmx_procbased_ctls_high &=
2730 CPU_BASED_VIRTUAL_INTR_PENDING |
2731 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2732 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2733 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2734 CPU_BASED_CR3_STORE_EXITING |
2735 #ifdef CONFIG_X86_64
2736 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2738 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2739 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2740 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2741 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2742 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2744 * We can allow some features even when not supported by the
2745 * hardware. For example, L1 can specify an MSR bitmap - and we
2746 * can use it to avoid exits to L1 - even when L0 runs L2
2747 * without MSR bitmaps.
2749 vmx->nested.nested_vmx_procbased_ctls_high |=
2750 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2751 CPU_BASED_USE_MSR_BITMAPS;
2753 /* We support free control of CR3 access interception. */
2754 vmx->nested.nested_vmx_procbased_ctls_low &=
2755 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2757 /* secondary cpu-based controls */
2758 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2759 vmx->nested.nested_vmx_secondary_ctls_low,
2760 vmx->nested.nested_vmx_secondary_ctls_high);
2761 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2762 vmx->nested.nested_vmx_secondary_ctls_high &=
2763 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2765 SECONDARY_EXEC_RDTSCP |
2766 SECONDARY_EXEC_DESC |
2767 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2768 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2769 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2770 SECONDARY_EXEC_WBINVD_EXITING |
2771 SECONDARY_EXEC_XSAVES;
2774 /* nested EPT: emulate EPT also to L1 */
2775 vmx->nested.nested_vmx_secondary_ctls_high |=
2776 SECONDARY_EXEC_ENABLE_EPT;
2777 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2778 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2779 if (cpu_has_vmx_ept_execute_only())
2780 vmx->nested.nested_vmx_ept_caps |=
2781 VMX_EPT_EXECUTE_ONLY_BIT;
2782 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2783 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2784 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2785 VMX_EPT_1GB_PAGE_BIT;
2786 if (enable_ept_ad_bits) {
2787 vmx->nested.nested_vmx_secondary_ctls_high |=
2788 SECONDARY_EXEC_ENABLE_PML;
2789 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2792 vmx->nested.nested_vmx_ept_caps = 0;
2795 * Old versions of KVM use the single-context version without
2796 * checking for support, so declare that it is supported even
2797 * though it is treated as global context. The alternative is
2798 * not failing the single-context invvpid, and it is worse.
2801 vmx->nested.nested_vmx_secondary_ctls_high |=
2802 SECONDARY_EXEC_ENABLE_VPID;
2803 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2804 VMX_VPID_EXTENT_SUPPORTED_MASK;
2806 vmx->nested.nested_vmx_vpid_caps = 0;
2808 if (enable_unrestricted_guest)
2809 vmx->nested.nested_vmx_secondary_ctls_high |=
2810 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2812 /* miscellaneous data */
2813 rdmsr(MSR_IA32_VMX_MISC,
2814 vmx->nested.nested_vmx_misc_low,
2815 vmx->nested.nested_vmx_misc_high);
2816 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2817 vmx->nested.nested_vmx_misc_low |=
2818 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2819 VMX_MISC_ACTIVITY_HLT;
2820 vmx->nested.nested_vmx_misc_high = 0;
2823 * This MSR reports some information about VMX support. We
2824 * should return information about the VMX we emulate for the
2825 * guest, and the VMCS structure we give it - not about the
2826 * VMX support of the underlying hardware.
2828 vmx->nested.nested_vmx_basic =
2830 VMX_BASIC_TRUE_CTLS |
2831 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2832 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2834 if (cpu_has_vmx_basic_inout())
2835 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2838 * These MSRs specify bits which the guest must keep fixed on
2839 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2840 * We picked the standard core2 setting.
2842 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2843 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2844 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2845 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2847 /* These MSRs specify bits which the guest must keep fixed off. */
2848 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2849 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2851 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2852 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2856 * if fixed0[i] == 1: val[i] must be 1
2857 * if fixed1[i] == 0: val[i] must be 0
2859 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2861 return ((val & fixed1) | fixed0) == val;
2864 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2866 return fixed_bits_valid(control, low, high);
2869 static inline u64 vmx_control_msr(u32 low, u32 high)
2871 return low | ((u64)high << 32);
2874 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2879 return (superset | subset) == superset;
2882 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2884 const u64 feature_and_reserved =
2885 /* feature (except bit 48; see below) */
2886 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2888 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2889 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2891 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2895 * KVM does not emulate a version of VMX that constrains physical
2896 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2898 if (data & BIT_ULL(48))
2901 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2902 vmx_basic_vmcs_revision_id(data))
2905 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2908 vmx->nested.nested_vmx_basic = data;
2913 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2918 switch (msr_index) {
2919 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2920 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2921 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2923 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2924 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2925 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2927 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2928 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2929 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2931 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2932 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2933 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2935 case MSR_IA32_VMX_PROCBASED_CTLS2:
2936 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2937 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2943 supported = vmx_control_msr(*lowp, *highp);
2945 /* Check must-be-1 bits are still 1. */
2946 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2949 /* Check must-be-0 bits are still 0. */
2950 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2954 *highp = data >> 32;
2958 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2960 const u64 feature_and_reserved_bits =
2962 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2963 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2965 GENMASK_ULL(13, 9) | BIT_ULL(31);
2968 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2969 vmx->nested.nested_vmx_misc_high);
2971 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2974 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2975 PIN_BASED_VMX_PREEMPTION_TIMER) &&
2976 vmx_misc_preemption_timer_rate(data) !=
2977 vmx_misc_preemption_timer_rate(vmx_misc))
2980 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2983 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2986 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2989 vmx->nested.nested_vmx_misc_low = data;
2990 vmx->nested.nested_vmx_misc_high = data >> 32;
2994 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2996 u64 vmx_ept_vpid_cap;
2998 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2999 vmx->nested.nested_vmx_vpid_caps);
3001 /* Every bit is either reserved or a feature bit. */
3002 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3005 vmx->nested.nested_vmx_ept_caps = data;
3006 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3010 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3014 switch (msr_index) {
3015 case MSR_IA32_VMX_CR0_FIXED0:
3016 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3018 case MSR_IA32_VMX_CR4_FIXED0:
3019 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3026 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3027 * must be 1 in the restored value.
3029 if (!is_bitwise_subset(data, *msr, -1ULL))
3037 * Called when userspace is restoring VMX MSRs.
3039 * Returns 0 on success, non-0 otherwise.
3041 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3043 struct vcpu_vmx *vmx = to_vmx(vcpu);
3045 switch (msr_index) {
3046 case MSR_IA32_VMX_BASIC:
3047 return vmx_restore_vmx_basic(vmx, data);
3048 case MSR_IA32_VMX_PINBASED_CTLS:
3049 case MSR_IA32_VMX_PROCBASED_CTLS:
3050 case MSR_IA32_VMX_EXIT_CTLS:
3051 case MSR_IA32_VMX_ENTRY_CTLS:
3053 * The "non-true" VMX capability MSRs are generated from the
3054 * "true" MSRs, so we do not support restoring them directly.
3056 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3057 * should restore the "true" MSRs with the must-be-1 bits
3058 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3059 * DEFAULT SETTINGS".
3062 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3063 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3064 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3065 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3066 case MSR_IA32_VMX_PROCBASED_CTLS2:
3067 return vmx_restore_control_msr(vmx, msr_index, data);
3068 case MSR_IA32_VMX_MISC:
3069 return vmx_restore_vmx_misc(vmx, data);
3070 case MSR_IA32_VMX_CR0_FIXED0:
3071 case MSR_IA32_VMX_CR4_FIXED0:
3072 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3073 case MSR_IA32_VMX_CR0_FIXED1:
3074 case MSR_IA32_VMX_CR4_FIXED1:
3076 * These MSRs are generated based on the vCPU's CPUID, so we
3077 * do not support restoring them directly.
3080 case MSR_IA32_VMX_EPT_VPID_CAP:
3081 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3082 case MSR_IA32_VMX_VMCS_ENUM:
3083 vmx->nested.nested_vmx_vmcs_enum = data;
3087 * The rest of the VMX capability MSRs do not support restore.
3093 /* Returns 0 on success, non-0 otherwise. */
3094 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3096 struct vcpu_vmx *vmx = to_vmx(vcpu);
3098 switch (msr_index) {
3099 case MSR_IA32_VMX_BASIC:
3100 *pdata = vmx->nested.nested_vmx_basic;
3102 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3103 case MSR_IA32_VMX_PINBASED_CTLS:
3104 *pdata = vmx_control_msr(
3105 vmx->nested.nested_vmx_pinbased_ctls_low,
3106 vmx->nested.nested_vmx_pinbased_ctls_high);
3107 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3108 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3110 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3111 case MSR_IA32_VMX_PROCBASED_CTLS:
3112 *pdata = vmx_control_msr(
3113 vmx->nested.nested_vmx_procbased_ctls_low,
3114 vmx->nested.nested_vmx_procbased_ctls_high);
3115 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3116 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3118 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3119 case MSR_IA32_VMX_EXIT_CTLS:
3120 *pdata = vmx_control_msr(
3121 vmx->nested.nested_vmx_exit_ctls_low,
3122 vmx->nested.nested_vmx_exit_ctls_high);
3123 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3124 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3126 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3127 case MSR_IA32_VMX_ENTRY_CTLS:
3128 *pdata = vmx_control_msr(
3129 vmx->nested.nested_vmx_entry_ctls_low,
3130 vmx->nested.nested_vmx_entry_ctls_high);
3131 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3132 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3134 case MSR_IA32_VMX_MISC:
3135 *pdata = vmx_control_msr(
3136 vmx->nested.nested_vmx_misc_low,
3137 vmx->nested.nested_vmx_misc_high);
3139 case MSR_IA32_VMX_CR0_FIXED0:
3140 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3142 case MSR_IA32_VMX_CR0_FIXED1:
3143 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3145 case MSR_IA32_VMX_CR4_FIXED0:
3146 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3148 case MSR_IA32_VMX_CR4_FIXED1:
3149 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3151 case MSR_IA32_VMX_VMCS_ENUM:
3152 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3154 case MSR_IA32_VMX_PROCBASED_CTLS2:
3155 *pdata = vmx_control_msr(
3156 vmx->nested.nested_vmx_secondary_ctls_low,
3157 vmx->nested.nested_vmx_secondary_ctls_high);
3159 case MSR_IA32_VMX_EPT_VPID_CAP:
3160 *pdata = vmx->nested.nested_vmx_ept_caps |
3161 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3170 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3173 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3175 return !(val & ~valid_bits);
3179 * Reads an msr value (of 'msr_index') into 'pdata'.
3180 * Returns 0 on success, non-0 otherwise.
3181 * Assumes vcpu_load() was already called.
3183 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3185 struct shared_msr_entry *msr;
3187 switch (msr_info->index) {
3188 #ifdef CONFIG_X86_64
3190 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3193 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3195 case MSR_KERNEL_GS_BASE:
3196 vmx_load_host_state(to_vmx(vcpu));
3197 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3201 return kvm_get_msr_common(vcpu, msr_info);
3203 msr_info->data = guest_read_tsc(vcpu);
3205 case MSR_IA32_SYSENTER_CS:
3206 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3208 case MSR_IA32_SYSENTER_EIP:
3209 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3211 case MSR_IA32_SYSENTER_ESP:
3212 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3214 case MSR_IA32_BNDCFGS:
3215 if (!kvm_mpx_supported() ||
3216 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3218 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3220 case MSR_IA32_MCG_EXT_CTL:
3221 if (!msr_info->host_initiated &&
3222 !(to_vmx(vcpu)->msr_ia32_feature_control &
3223 FEATURE_CONTROL_LMCE))
3225 msr_info->data = vcpu->arch.mcg_ext_ctl;
3227 case MSR_IA32_FEATURE_CONTROL:
3228 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3230 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3231 if (!nested_vmx_allowed(vcpu))
3233 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3235 if (!vmx_xsaves_supported())
3237 msr_info->data = vcpu->arch.ia32_xss;
3240 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3242 /* Otherwise falls through */
3244 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3246 msr_info->data = msr->data;
3249 return kvm_get_msr_common(vcpu, msr_info);
3255 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3258 * Writes msr value into into the appropriate "register".
3259 * Returns 0 on success, non-0 otherwise.
3260 * Assumes vcpu_load() was already called.
3262 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3264 struct vcpu_vmx *vmx = to_vmx(vcpu);
3265 struct shared_msr_entry *msr;
3267 u32 msr_index = msr_info->index;
3268 u64 data = msr_info->data;
3270 switch (msr_index) {
3272 ret = kvm_set_msr_common(vcpu, msr_info);
3274 #ifdef CONFIG_X86_64
3276 vmx_segment_cache_clear(vmx);
3277 vmcs_writel(GUEST_FS_BASE, data);
3280 vmx_segment_cache_clear(vmx);
3281 vmcs_writel(GUEST_GS_BASE, data);
3283 case MSR_KERNEL_GS_BASE:
3284 vmx_load_host_state(vmx);
3285 vmx->msr_guest_kernel_gs_base = data;
3288 case MSR_IA32_SYSENTER_CS:
3289 vmcs_write32(GUEST_SYSENTER_CS, data);
3291 case MSR_IA32_SYSENTER_EIP:
3292 vmcs_writel(GUEST_SYSENTER_EIP, data);
3294 case MSR_IA32_SYSENTER_ESP:
3295 vmcs_writel(GUEST_SYSENTER_ESP, data);
3297 case MSR_IA32_BNDCFGS:
3298 if (!kvm_mpx_supported() ||
3299 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3301 if (is_noncanonical_address(data & PAGE_MASK) ||
3302 (data & MSR_IA32_BNDCFGS_RSVD))
3304 vmcs_write64(GUEST_BNDCFGS, data);
3307 kvm_write_tsc(vcpu, msr_info);
3309 case MSR_IA32_CR_PAT:
3310 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3311 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3313 vmcs_write64(GUEST_IA32_PAT, data);
3314 vcpu->arch.pat = data;
3317 ret = kvm_set_msr_common(vcpu, msr_info);
3319 case MSR_IA32_TSC_ADJUST:
3320 ret = kvm_set_msr_common(vcpu, msr_info);
3322 case MSR_IA32_MCG_EXT_CTL:
3323 if ((!msr_info->host_initiated &&
3324 !(to_vmx(vcpu)->msr_ia32_feature_control &
3325 FEATURE_CONTROL_LMCE)) ||
3326 (data & ~MCG_EXT_CTL_LMCE_EN))
3328 vcpu->arch.mcg_ext_ctl = data;
3330 case MSR_IA32_FEATURE_CONTROL:
3331 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3332 (to_vmx(vcpu)->msr_ia32_feature_control &
3333 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3335 vmx->msr_ia32_feature_control = data;
3336 if (msr_info->host_initiated && data == 0)
3337 vmx_leave_nested(vcpu);
3339 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3340 if (!msr_info->host_initiated)
3341 return 1; /* they are read-only */
3342 if (!nested_vmx_allowed(vcpu))
3344 return vmx_set_vmx_msr(vcpu, msr_index, data);
3346 if (!vmx_xsaves_supported())
3349 * The only supported bit as of Skylake is bit 8, but
3350 * it is not supported on KVM.
3354 vcpu->arch.ia32_xss = data;
3355 if (vcpu->arch.ia32_xss != host_xss)
3356 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3357 vcpu->arch.ia32_xss, host_xss);
3359 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3362 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3364 /* Check reserved bit, higher 32 bits should be zero */
3365 if ((data >> 32) != 0)
3367 /* Otherwise falls through */
3369 msr = find_msr_entry(vmx, msr_index);
3371 u64 old_msr_data = msr->data;
3373 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3375 ret = kvm_set_shared_msr(msr->index, msr->data,
3379 msr->data = old_msr_data;
3383 ret = kvm_set_msr_common(vcpu, msr_info);
3389 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3391 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3394 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3397 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3399 case VCPU_EXREG_PDPTR:
3401 ept_save_pdptrs(vcpu);
3408 static __init int cpu_has_kvm_support(void)
3410 return cpu_has_vmx();
3413 static __init int vmx_disabled_by_bios(void)
3417 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3418 if (msr & FEATURE_CONTROL_LOCKED) {
3419 /* launched w/ TXT and VMX disabled */
3420 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3423 /* launched w/o TXT and VMX only enabled w/ TXT */
3424 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3425 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3426 && !tboot_enabled()) {
3427 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3428 "activate TXT before enabling KVM\n");
3431 /* launched w/o TXT and VMX disabled */
3432 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3433 && !tboot_enabled())
3440 static void kvm_cpu_vmxon(u64 addr)
3442 cr4_set_bits(X86_CR4_VMXE);
3443 intel_pt_handle_vmx(1);
3445 asm volatile (ASM_VMX_VMXON_RAX
3446 : : "a"(&addr), "m"(addr)
3450 static int hardware_enable(void)
3452 int cpu = raw_smp_processor_id();
3453 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3456 if (cr4_read_shadow() & X86_CR4_VMXE)
3459 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3460 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3461 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3464 * Now we can enable the vmclear operation in kdump
3465 * since the loaded_vmcss_on_cpu list on this cpu
3466 * has been initialized.
3468 * Though the cpu is not in VMX operation now, there
3469 * is no problem to enable the vmclear operation
3470 * for the loaded_vmcss_on_cpu list is empty!
3472 crash_enable_local_vmclear(cpu);
3474 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3476 test_bits = FEATURE_CONTROL_LOCKED;
3477 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3478 if (tboot_enabled())
3479 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3481 if ((old & test_bits) != test_bits) {
3482 /* enable and lock */
3483 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3485 kvm_cpu_vmxon(phys_addr);
3491 static void vmclear_local_loaded_vmcss(void)
3493 int cpu = raw_smp_processor_id();
3494 struct loaded_vmcs *v, *n;
3496 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3497 loaded_vmcss_on_cpu_link)
3498 __loaded_vmcs_clear(v);
3502 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3505 static void kvm_cpu_vmxoff(void)
3507 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3509 intel_pt_handle_vmx(0);
3510 cr4_clear_bits(X86_CR4_VMXE);
3513 static void hardware_disable(void)
3515 vmclear_local_loaded_vmcss();
3519 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3520 u32 msr, u32 *result)
3522 u32 vmx_msr_low, vmx_msr_high;
3523 u32 ctl = ctl_min | ctl_opt;
3525 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3527 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3528 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3530 /* Ensure minimum (required) set of control bits are supported. */
3538 static __init bool allow_1_setting(u32 msr, u32 ctl)
3540 u32 vmx_msr_low, vmx_msr_high;
3542 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3543 return vmx_msr_high & ctl;
3546 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3548 u32 vmx_msr_low, vmx_msr_high;
3549 u32 min, opt, min2, opt2;
3550 u32 _pin_based_exec_control = 0;
3551 u32 _cpu_based_exec_control = 0;
3552 u32 _cpu_based_2nd_exec_control = 0;
3553 u32 _vmexit_control = 0;
3554 u32 _vmentry_control = 0;
3556 min = CPU_BASED_HLT_EXITING |
3557 #ifdef CONFIG_X86_64
3558 CPU_BASED_CR8_LOAD_EXITING |
3559 CPU_BASED_CR8_STORE_EXITING |
3561 CPU_BASED_CR3_LOAD_EXITING |
3562 CPU_BASED_CR3_STORE_EXITING |
3563 CPU_BASED_USE_IO_BITMAPS |
3564 CPU_BASED_MOV_DR_EXITING |
3565 CPU_BASED_USE_TSC_OFFSETING |
3566 CPU_BASED_INVLPG_EXITING |
3567 CPU_BASED_RDPMC_EXITING;
3569 if (!kvm_mwait_in_guest())
3570 min |= CPU_BASED_MWAIT_EXITING |
3571 CPU_BASED_MONITOR_EXITING;
3573 opt = CPU_BASED_TPR_SHADOW |
3574 CPU_BASED_USE_MSR_BITMAPS |
3575 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3576 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3577 &_cpu_based_exec_control) < 0)
3579 #ifdef CONFIG_X86_64
3580 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3581 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3582 ~CPU_BASED_CR8_STORE_EXITING;
3584 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3586 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3587 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3588 SECONDARY_EXEC_WBINVD_EXITING |
3589 SECONDARY_EXEC_ENABLE_VPID |
3590 SECONDARY_EXEC_ENABLE_EPT |
3591 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3592 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3593 SECONDARY_EXEC_RDTSCP |
3594 SECONDARY_EXEC_ENABLE_INVPCID |
3595 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3596 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3597 SECONDARY_EXEC_SHADOW_VMCS |
3598 SECONDARY_EXEC_XSAVES |
3599 SECONDARY_EXEC_ENABLE_PML |
3600 SECONDARY_EXEC_TSC_SCALING;
3601 if (adjust_vmx_controls(min2, opt2,
3602 MSR_IA32_VMX_PROCBASED_CTLS2,
3603 &_cpu_based_2nd_exec_control) < 0)
3606 #ifndef CONFIG_X86_64
3607 if (!(_cpu_based_2nd_exec_control &
3608 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3609 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3612 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3613 _cpu_based_2nd_exec_control &= ~(
3614 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3615 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3616 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3618 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3619 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3621 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3622 CPU_BASED_CR3_STORE_EXITING |
3623 CPU_BASED_INVLPG_EXITING);
3624 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3625 vmx_capability.ept, vmx_capability.vpid);
3628 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3629 #ifdef CONFIG_X86_64
3630 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3632 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3633 VM_EXIT_CLEAR_BNDCFGS;
3634 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3635 &_vmexit_control) < 0)
3638 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3639 PIN_BASED_VIRTUAL_NMIS;
3640 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3641 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3642 &_pin_based_exec_control) < 0)
3645 if (cpu_has_broken_vmx_preemption_timer())
3646 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3647 if (!(_cpu_based_2nd_exec_control &
3648 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3649 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3651 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3652 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3653 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3654 &_vmentry_control) < 0)
3657 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3659 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3660 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3663 #ifdef CONFIG_X86_64
3664 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3665 if (vmx_msr_high & (1u<<16))
3669 /* Require Write-Back (WB) memory type for VMCS accesses. */
3670 if (((vmx_msr_high >> 18) & 15) != 6)
3673 vmcs_conf->size = vmx_msr_high & 0x1fff;
3674 vmcs_conf->order = get_order(vmcs_conf->size);
3675 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3676 vmcs_conf->revision_id = vmx_msr_low;
3678 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3679 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3680 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3681 vmcs_conf->vmexit_ctrl = _vmexit_control;
3682 vmcs_conf->vmentry_ctrl = _vmentry_control;
3684 cpu_has_load_ia32_efer =
3685 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3686 VM_ENTRY_LOAD_IA32_EFER)
3687 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3688 VM_EXIT_LOAD_IA32_EFER);
3690 cpu_has_load_perf_global_ctrl =
3691 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3692 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3693 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3694 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3697 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3698 * but due to errata below it can't be used. Workaround is to use
3699 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3701 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3706 * BC86,AAY89,BD102 (model 44)
3710 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3711 switch (boot_cpu_data.x86_model) {
3717 cpu_has_load_perf_global_ctrl = false;
3718 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3719 "does not work properly. Using workaround\n");
3726 if (boot_cpu_has(X86_FEATURE_XSAVES))
3727 rdmsrl(MSR_IA32_XSS, host_xss);
3732 static struct vmcs *alloc_vmcs_cpu(int cpu)
3734 int node = cpu_to_node(cpu);
3738 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3741 vmcs = page_address(pages);
3742 memset(vmcs, 0, vmcs_config.size);
3743 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3747 static struct vmcs *alloc_vmcs(void)
3749 return alloc_vmcs_cpu(raw_smp_processor_id());
3752 static void free_vmcs(struct vmcs *vmcs)
3754 free_pages((unsigned long)vmcs, vmcs_config.order);
3758 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3760 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3762 if (!loaded_vmcs->vmcs)
3764 loaded_vmcs_clear(loaded_vmcs);
3765 free_vmcs(loaded_vmcs->vmcs);
3766 loaded_vmcs->vmcs = NULL;
3767 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3770 static void free_kvm_area(void)
3774 for_each_possible_cpu(cpu) {
3775 free_vmcs(per_cpu(vmxarea, cpu));
3776 per_cpu(vmxarea, cpu) = NULL;
3780 enum vmcs_field_type {
3781 VMCS_FIELD_TYPE_U16 = 0,
3782 VMCS_FIELD_TYPE_U64 = 1,
3783 VMCS_FIELD_TYPE_U32 = 2,
3784 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3787 static inline int vmcs_field_type(unsigned long field)
3789 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3790 return VMCS_FIELD_TYPE_U32;
3791 return (field >> 13) & 0x3 ;
3794 static inline int vmcs_field_readonly(unsigned long field)
3796 return (((field >> 10) & 0x3) == 1);
3799 static void init_vmcs_shadow_fields(void)
3803 /* No checks for read only fields yet */
3805 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3806 switch (shadow_read_write_fields[i]) {
3808 if (!kvm_mpx_supported())
3816 shadow_read_write_fields[j] =
3817 shadow_read_write_fields[i];
3820 max_shadow_read_write_fields = j;
3822 /* shadowed fields guest access without vmexit */
3823 for (i = 0; i < max_shadow_read_write_fields; i++) {
3824 unsigned long field = shadow_read_write_fields[i];
3826 clear_bit(field, vmx_vmwrite_bitmap);
3827 clear_bit(field, vmx_vmread_bitmap);
3828 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3829 clear_bit(field + 1, vmx_vmwrite_bitmap);
3830 clear_bit(field + 1, vmx_vmread_bitmap);
3833 for (i = 0; i < max_shadow_read_only_fields; i++) {
3834 unsigned long field = shadow_read_only_fields[i];
3836 clear_bit(field, vmx_vmread_bitmap);
3837 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3838 clear_bit(field + 1, vmx_vmread_bitmap);
3842 static __init int alloc_kvm_area(void)
3846 for_each_possible_cpu(cpu) {
3849 vmcs = alloc_vmcs_cpu(cpu);
3855 per_cpu(vmxarea, cpu) = vmcs;
3860 static bool emulation_required(struct kvm_vcpu *vcpu)
3862 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3865 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3866 struct kvm_segment *save)
3868 if (!emulate_invalid_guest_state) {
3870 * CS and SS RPL should be equal during guest entry according
3871 * to VMX spec, but in reality it is not always so. Since vcpu
3872 * is in the middle of the transition from real mode to
3873 * protected mode it is safe to assume that RPL 0 is a good
3876 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3877 save->selector &= ~SEGMENT_RPL_MASK;
3878 save->dpl = save->selector & SEGMENT_RPL_MASK;
3881 vmx_set_segment(vcpu, save, seg);
3884 static void enter_pmode(struct kvm_vcpu *vcpu)
3886 unsigned long flags;
3887 struct vcpu_vmx *vmx = to_vmx(vcpu);
3890 * Update real mode segment cache. It may be not up-to-date if sement
3891 * register was written while vcpu was in a guest mode.
3893 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3894 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3895 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3896 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3897 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3898 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3900 vmx->rmode.vm86_active = 0;
3902 vmx_segment_cache_clear(vmx);
3904 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3906 flags = vmcs_readl(GUEST_RFLAGS);
3907 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3908 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3909 vmcs_writel(GUEST_RFLAGS, flags);
3911 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3912 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3914 update_exception_bitmap(vcpu);
3916 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3917 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3918 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3919 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3920 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3921 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3924 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3926 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3927 struct kvm_segment var = *save;
3930 if (seg == VCPU_SREG_CS)
3933 if (!emulate_invalid_guest_state) {
3934 var.selector = var.base >> 4;
3935 var.base = var.base & 0xffff0;
3945 if (save->base & 0xf)
3946 printk_once(KERN_WARNING "kvm: segment base is not "
3947 "paragraph aligned when entering "
3948 "protected mode (seg=%d)", seg);
3951 vmcs_write16(sf->selector, var.selector);
3952 vmcs_writel(sf->base, var.base);
3953 vmcs_write32(sf->limit, var.limit);
3954 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3957 static void enter_rmode(struct kvm_vcpu *vcpu)
3959 unsigned long flags;
3960 struct vcpu_vmx *vmx = to_vmx(vcpu);
3962 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3963 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3964 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3965 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3966 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3967 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3968 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3970 vmx->rmode.vm86_active = 1;
3973 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3974 * vcpu. Warn the user that an update is overdue.
3976 if (!vcpu->kvm->arch.tss_addr)
3977 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3978 "called before entering vcpu\n");
3980 vmx_segment_cache_clear(vmx);
3982 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3983 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3984 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3986 flags = vmcs_readl(GUEST_RFLAGS);
3987 vmx->rmode.save_rflags = flags;
3989 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3991 vmcs_writel(GUEST_RFLAGS, flags);
3992 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3993 update_exception_bitmap(vcpu);
3995 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3996 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3997 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3998 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3999 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4000 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4002 kvm_mmu_reset_context(vcpu);
4005 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4007 struct vcpu_vmx *vmx = to_vmx(vcpu);
4008 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4014 * Force kernel_gs_base reloading before EFER changes, as control
4015 * of this msr depends on is_long_mode().
4017 vmx_load_host_state(to_vmx(vcpu));
4018 vcpu->arch.efer = efer;
4019 if (efer & EFER_LMA) {
4020 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4023 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4025 msr->data = efer & ~EFER_LME;
4030 #ifdef CONFIG_X86_64
4032 static void enter_lmode(struct kvm_vcpu *vcpu)
4036 vmx_segment_cache_clear(to_vmx(vcpu));
4038 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4039 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4040 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4042 vmcs_write32(GUEST_TR_AR_BYTES,
4043 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4044 | VMX_AR_TYPE_BUSY_64_TSS);
4046 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4049 static void exit_lmode(struct kvm_vcpu *vcpu)
4051 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4052 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4057 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4060 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4062 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4064 vpid_sync_context(vpid);
4068 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4070 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4073 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4076 vmx_flush_tlb(vcpu);
4079 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4081 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4083 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4084 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4087 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4089 if (enable_ept && is_paging(vcpu))
4090 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4091 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4094 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4096 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4098 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4099 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4102 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4104 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4106 if (!test_bit(VCPU_EXREG_PDPTR,
4107 (unsigned long *)&vcpu->arch.regs_dirty))
4110 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4111 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4112 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4113 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4114 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4118 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4120 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4122 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4123 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4124 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4125 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4126 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4129 __set_bit(VCPU_EXREG_PDPTR,
4130 (unsigned long *)&vcpu->arch.regs_avail);
4131 __set_bit(VCPU_EXREG_PDPTR,
4132 (unsigned long *)&vcpu->arch.regs_dirty);
4135 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4137 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4138 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4139 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4141 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4142 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4143 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4144 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4146 return fixed_bits_valid(val, fixed0, fixed1);
4149 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4151 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4152 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4154 return fixed_bits_valid(val, fixed0, fixed1);
4157 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4159 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4160 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4162 return fixed_bits_valid(val, fixed0, fixed1);
4165 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4166 #define nested_guest_cr4_valid nested_cr4_valid
4167 #define nested_host_cr4_valid nested_cr4_valid
4169 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4171 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4173 struct kvm_vcpu *vcpu)
4175 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4176 vmx_decache_cr3(vcpu);
4177 if (!(cr0 & X86_CR0_PG)) {
4178 /* From paging/starting to nonpaging */
4179 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4180 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4181 (CPU_BASED_CR3_LOAD_EXITING |
4182 CPU_BASED_CR3_STORE_EXITING));
4183 vcpu->arch.cr0 = cr0;
4184 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4185 } else if (!is_paging(vcpu)) {
4186 /* From nonpaging to paging */
4187 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4188 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4189 ~(CPU_BASED_CR3_LOAD_EXITING |
4190 CPU_BASED_CR3_STORE_EXITING));
4191 vcpu->arch.cr0 = cr0;
4192 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4195 if (!(cr0 & X86_CR0_WP))
4196 *hw_cr0 &= ~X86_CR0_WP;
4199 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4201 struct vcpu_vmx *vmx = to_vmx(vcpu);
4202 unsigned long hw_cr0;
4204 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4205 if (enable_unrestricted_guest)
4206 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4208 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4210 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4213 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4217 #ifdef CONFIG_X86_64
4218 if (vcpu->arch.efer & EFER_LME) {
4219 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4221 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4227 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4229 vmcs_writel(CR0_READ_SHADOW, cr0);
4230 vmcs_writel(GUEST_CR0, hw_cr0);
4231 vcpu->arch.cr0 = cr0;
4233 /* depends on vcpu->arch.cr0 to be set to a new value */
4234 vmx->emulation_required = emulation_required(vcpu);
4237 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4241 /* TODO write the value reading from MSR */
4242 eptp = VMX_EPT_DEFAULT_MT |
4243 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4244 if (enable_ept_ad_bits &&
4245 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4246 eptp |= VMX_EPT_AD_ENABLE_BIT;
4247 eptp |= (root_hpa & PAGE_MASK);
4252 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4254 unsigned long guest_cr3;
4259 eptp = construct_eptp(vcpu, cr3);
4260 vmcs_write64(EPT_POINTER, eptp);
4261 if (is_paging(vcpu) || is_guest_mode(vcpu))
4262 guest_cr3 = kvm_read_cr3(vcpu);
4264 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4265 ept_load_pdptrs(vcpu);
4268 vmx_flush_tlb(vcpu);
4269 vmcs_writel(GUEST_CR3, guest_cr3);
4272 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4275 * Pass through host's Machine Check Enable value to hw_cr4, which
4276 * is in force while we are in guest mode. Do not let guests control
4277 * this bit, even if host CR4.MCE == 0.
4279 unsigned long hw_cr4 =
4280 (cr4_read_shadow() & X86_CR4_MCE) |
4281 (cr4 & ~X86_CR4_MCE) |
4282 (to_vmx(vcpu)->rmode.vm86_active ?
4283 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4285 if (cr4 & X86_CR4_VMXE) {
4287 * To use VMXON (and later other VMX instructions), a guest
4288 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4289 * So basically the check on whether to allow nested VMX
4292 if (!nested_vmx_allowed(vcpu))
4296 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4299 vcpu->arch.cr4 = cr4;
4301 if (!is_paging(vcpu)) {
4302 hw_cr4 &= ~X86_CR4_PAE;
4303 hw_cr4 |= X86_CR4_PSE;
4304 } else if (!(cr4 & X86_CR4_PAE)) {
4305 hw_cr4 &= ~X86_CR4_PAE;
4309 if (!enable_unrestricted_guest && !is_paging(vcpu))
4311 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4312 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4313 * to be manually disabled when guest switches to non-paging
4316 * If !enable_unrestricted_guest, the CPU is always running
4317 * with CR0.PG=1 and CR4 needs to be modified.
4318 * If enable_unrestricted_guest, the CPU automatically
4319 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4321 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4323 vmcs_writel(CR4_READ_SHADOW, cr4);
4324 vmcs_writel(GUEST_CR4, hw_cr4);
4328 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4329 struct kvm_segment *var, int seg)
4331 struct vcpu_vmx *vmx = to_vmx(vcpu);
4334 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4335 *var = vmx->rmode.segs[seg];
4336 if (seg == VCPU_SREG_TR
4337 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4339 var->base = vmx_read_guest_seg_base(vmx, seg);
4340 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4343 var->base = vmx_read_guest_seg_base(vmx, seg);
4344 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4345 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4346 ar = vmx_read_guest_seg_ar(vmx, seg);
4347 var->unusable = (ar >> 16) & 1;
4348 var->type = ar & 15;
4349 var->s = (ar >> 4) & 1;
4350 var->dpl = (ar >> 5) & 3;
4352 * Some userspaces do not preserve unusable property. Since usable
4353 * segment has to be present according to VMX spec we can use present
4354 * property to amend userspace bug by making unusable segment always
4355 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4356 * segment as unusable.
4358 var->present = !var->unusable;
4359 var->avl = (ar >> 12) & 1;
4360 var->l = (ar >> 13) & 1;
4361 var->db = (ar >> 14) & 1;
4362 var->g = (ar >> 15) & 1;
4365 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4367 struct kvm_segment s;
4369 if (to_vmx(vcpu)->rmode.vm86_active) {
4370 vmx_get_segment(vcpu, &s, seg);
4373 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4376 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4378 struct vcpu_vmx *vmx = to_vmx(vcpu);
4380 if (unlikely(vmx->rmode.vm86_active))
4383 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4384 return VMX_AR_DPL(ar);
4388 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4392 if (var->unusable || !var->present)
4395 ar = var->type & 15;
4396 ar |= (var->s & 1) << 4;
4397 ar |= (var->dpl & 3) << 5;
4398 ar |= (var->present & 1) << 7;
4399 ar |= (var->avl & 1) << 12;
4400 ar |= (var->l & 1) << 13;
4401 ar |= (var->db & 1) << 14;
4402 ar |= (var->g & 1) << 15;
4408 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4409 struct kvm_segment *var, int seg)
4411 struct vcpu_vmx *vmx = to_vmx(vcpu);
4412 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4414 vmx_segment_cache_clear(vmx);
4416 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4417 vmx->rmode.segs[seg] = *var;
4418 if (seg == VCPU_SREG_TR)
4419 vmcs_write16(sf->selector, var->selector);
4421 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4425 vmcs_writel(sf->base, var->base);
4426 vmcs_write32(sf->limit, var->limit);
4427 vmcs_write16(sf->selector, var->selector);
4430 * Fix the "Accessed" bit in AR field of segment registers for older
4432 * IA32 arch specifies that at the time of processor reset the
4433 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4434 * is setting it to 0 in the userland code. This causes invalid guest
4435 * state vmexit when "unrestricted guest" mode is turned on.
4436 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4437 * tree. Newer qemu binaries with that qemu fix would not need this
4440 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4441 var->type |= 0x1; /* Accessed */
4443 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4446 vmx->emulation_required = emulation_required(vcpu);
4449 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4451 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4453 *db = (ar >> 14) & 1;
4454 *l = (ar >> 13) & 1;
4457 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4459 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4460 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4463 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4465 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4466 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4469 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4471 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4472 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4475 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4477 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4478 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4481 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4483 struct kvm_segment var;
4486 vmx_get_segment(vcpu, &var, seg);
4488 if (seg == VCPU_SREG_CS)
4490 ar = vmx_segment_access_rights(&var);
4492 if (var.base != (var.selector << 4))
4494 if (var.limit != 0xffff)
4502 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4504 struct kvm_segment cs;
4505 unsigned int cs_rpl;
4507 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4508 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4512 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4516 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4517 if (cs.dpl > cs_rpl)
4520 if (cs.dpl != cs_rpl)
4526 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4530 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4532 struct kvm_segment ss;
4533 unsigned int ss_rpl;
4535 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4536 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4540 if (ss.type != 3 && ss.type != 7)
4544 if (ss.dpl != ss_rpl) /* DPL != RPL */
4552 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4554 struct kvm_segment var;
4557 vmx_get_segment(vcpu, &var, seg);
4558 rpl = var.selector & SEGMENT_RPL_MASK;
4566 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4567 if (var.dpl < rpl) /* DPL < RPL */
4571 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4577 static bool tr_valid(struct kvm_vcpu *vcpu)
4579 struct kvm_segment tr;
4581 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4585 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4587 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4595 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4597 struct kvm_segment ldtr;
4599 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4603 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4613 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4615 struct kvm_segment cs, ss;
4617 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4618 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4620 return ((cs.selector & SEGMENT_RPL_MASK) ==
4621 (ss.selector & SEGMENT_RPL_MASK));
4625 * Check if guest state is valid. Returns true if valid, false if
4627 * We assume that registers are always usable
4629 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4631 if (enable_unrestricted_guest)
4634 /* real mode guest state checks */
4635 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4636 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4638 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4640 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4642 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4644 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4646 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4649 /* protected mode guest state checks */
4650 if (!cs_ss_rpl_check(vcpu))
4652 if (!code_segment_valid(vcpu))
4654 if (!stack_segment_valid(vcpu))
4656 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4658 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4660 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4662 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4664 if (!tr_valid(vcpu))
4666 if (!ldtr_valid(vcpu))
4670 * - Add checks on RIP
4671 * - Add checks on RFLAGS
4677 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4679 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4682 static int init_rmode_tss(struct kvm *kvm)
4688 idx = srcu_read_lock(&kvm->srcu);
4689 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4690 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4693 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4694 r = kvm_write_guest_page(kvm, fn++, &data,
4695 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4698 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4701 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4705 r = kvm_write_guest_page(kvm, fn, &data,
4706 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4709 srcu_read_unlock(&kvm->srcu, idx);
4713 static int init_rmode_identity_map(struct kvm *kvm)
4716 kvm_pfn_t identity_map_pfn;
4722 /* Protect kvm->arch.ept_identity_pagetable_done. */
4723 mutex_lock(&kvm->slots_lock);
4725 if (likely(kvm->arch.ept_identity_pagetable_done))
4728 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4730 r = alloc_identity_pagetable(kvm);
4734 idx = srcu_read_lock(&kvm->srcu);
4735 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4738 /* Set up identity-mapping pagetable for EPT in real mode */
4739 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4740 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4741 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4742 r = kvm_write_guest_page(kvm, identity_map_pfn,
4743 &tmp, i * sizeof(tmp), sizeof(tmp));
4747 kvm->arch.ept_identity_pagetable_done = true;
4750 srcu_read_unlock(&kvm->srcu, idx);
4753 mutex_unlock(&kvm->slots_lock);
4757 static void seg_setup(int seg)
4759 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4762 vmcs_write16(sf->selector, 0);
4763 vmcs_writel(sf->base, 0);
4764 vmcs_write32(sf->limit, 0xffff);
4766 if (seg == VCPU_SREG_CS)
4767 ar |= 0x08; /* code segment */
4769 vmcs_write32(sf->ar_bytes, ar);
4772 static int alloc_apic_access_page(struct kvm *kvm)
4777 mutex_lock(&kvm->slots_lock);
4778 if (kvm->arch.apic_access_page_done)
4780 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4781 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4785 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4786 if (is_error_page(page)) {
4792 * Do not pin the page in memory, so that memory hot-unplug
4793 * is able to migrate it.
4796 kvm->arch.apic_access_page_done = true;
4798 mutex_unlock(&kvm->slots_lock);
4802 static int alloc_identity_pagetable(struct kvm *kvm)
4804 /* Called with kvm->slots_lock held. */
4808 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4810 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4811 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4816 static int allocate_vpid(void)
4822 spin_lock(&vmx_vpid_lock);
4823 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4824 if (vpid < VMX_NR_VPIDS)
4825 __set_bit(vpid, vmx_vpid_bitmap);
4828 spin_unlock(&vmx_vpid_lock);
4832 static void free_vpid(int vpid)
4834 if (!enable_vpid || vpid == 0)
4836 spin_lock(&vmx_vpid_lock);
4837 __clear_bit(vpid, vmx_vpid_bitmap);
4838 spin_unlock(&vmx_vpid_lock);
4841 #define MSR_TYPE_R 1
4842 #define MSR_TYPE_W 2
4843 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4846 int f = sizeof(unsigned long);
4848 if (!cpu_has_vmx_msr_bitmap())
4852 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4853 * have the write-low and read-high bitmap offsets the wrong way round.
4854 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4856 if (msr <= 0x1fff) {
4857 if (type & MSR_TYPE_R)
4859 __clear_bit(msr, msr_bitmap + 0x000 / f);
4861 if (type & MSR_TYPE_W)
4863 __clear_bit(msr, msr_bitmap + 0x800 / f);
4865 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4867 if (type & MSR_TYPE_R)
4869 __clear_bit(msr, msr_bitmap + 0x400 / f);
4871 if (type & MSR_TYPE_W)
4873 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4879 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4880 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4882 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4883 unsigned long *msr_bitmap_nested,
4886 int f = sizeof(unsigned long);
4888 if (!cpu_has_vmx_msr_bitmap()) {
4894 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4895 * have the write-low and read-high bitmap offsets the wrong way round.
4896 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4898 if (msr <= 0x1fff) {
4899 if (type & MSR_TYPE_R &&
4900 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4902 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4904 if (type & MSR_TYPE_W &&
4905 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4907 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4909 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4911 if (type & MSR_TYPE_R &&
4912 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4914 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4916 if (type & MSR_TYPE_W &&
4917 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4919 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4924 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4927 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4928 msr, MSR_TYPE_R | MSR_TYPE_W);
4929 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4930 msr, MSR_TYPE_R | MSR_TYPE_W);
4933 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4936 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4938 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4941 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4943 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4948 static bool vmx_get_enable_apicv(void)
4950 return enable_apicv;
4953 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4955 struct vcpu_vmx *vmx = to_vmx(vcpu);
4960 if (vmx->nested.pi_desc &&
4961 vmx->nested.pi_pending) {
4962 vmx->nested.pi_pending = false;
4963 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4966 max_irr = find_last_bit(
4967 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4972 vapic_page = kmap(vmx->nested.virtual_apic_page);
4973 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4974 kunmap(vmx->nested.virtual_apic_page);
4976 status = vmcs_read16(GUEST_INTR_STATUS);
4977 if ((u8)max_irr > ((u8)status & 0xff)) {
4979 status |= (u8)max_irr;
4980 vmcs_write16(GUEST_INTR_STATUS, status);
4985 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4988 if (vcpu->mode == IN_GUEST_MODE) {
4989 struct vcpu_vmx *vmx = to_vmx(vcpu);
4992 * Currently, we don't support urgent interrupt,
4993 * all interrupts are recognized as non-urgent
4994 * interrupt, so we cannot post interrupts when
4997 * If the vcpu is in guest mode, it means it is
4998 * running instead of being scheduled out and
4999 * waiting in the run queue, and that's the only
5000 * case when 'SN' is set currently, warning if
5003 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5005 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
5006 POSTED_INTR_VECTOR);
5013 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5016 struct vcpu_vmx *vmx = to_vmx(vcpu);
5018 if (is_guest_mode(vcpu) &&
5019 vector == vmx->nested.posted_intr_nv) {
5020 /* the PIR and ON have been set by L1. */
5021 kvm_vcpu_trigger_posted_interrupt(vcpu);
5023 * If a posted intr is not recognized by hardware,
5024 * we will accomplish it in the next vmentry.
5026 vmx->nested.pi_pending = true;
5027 kvm_make_request(KVM_REQ_EVENT, vcpu);
5033 * Send interrupt to vcpu via posted interrupt way.
5034 * 1. If target vcpu is running(non-root mode), send posted interrupt
5035 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5036 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5037 * interrupt from PIR in next vmentry.
5039 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5041 struct vcpu_vmx *vmx = to_vmx(vcpu);
5044 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5048 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5051 /* If a previous notification has sent the IPI, nothing to do. */
5052 if (pi_test_and_set_on(&vmx->pi_desc))
5055 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5056 kvm_vcpu_kick(vcpu);
5060 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5061 * will not change in the lifetime of the guest.
5062 * Note that host-state that does change is set elsewhere. E.g., host-state
5063 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5065 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5070 unsigned long cr0, cr3, cr4;
5073 WARN_ON(cr0 & X86_CR0_TS);
5074 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5077 * Save the most likely value for this task's CR3 in the VMCS.
5078 * We can't use __get_current_cr3_fast() because we're not atomic.
5081 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5082 vmx->host_state.vmcs_host_cr3 = cr3;
5084 /* Save the most likely value for this task's CR4 in the VMCS. */
5085 cr4 = cr4_read_shadow();
5086 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5087 vmx->host_state.vmcs_host_cr4 = cr4;
5089 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5090 #ifdef CONFIG_X86_64
5092 * Load null selectors, so we can avoid reloading them in
5093 * __vmx_load_host_state(), in case userspace uses the null selectors
5094 * too (the expected case).
5096 vmcs_write16(HOST_DS_SELECTOR, 0);
5097 vmcs_write16(HOST_ES_SELECTOR, 0);
5099 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5100 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5102 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5103 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5105 native_store_idt(&dt);
5106 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5107 vmx->host_idt_base = dt.address;
5109 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5111 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5112 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5113 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5114 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5116 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5117 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5118 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5122 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5124 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5126 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5127 if (is_guest_mode(&vmx->vcpu))
5128 vmx->vcpu.arch.cr4_guest_owned_bits &=
5129 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5130 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5133 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5135 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5137 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5138 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5139 /* Enable the preemption timer dynamically */
5140 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5141 return pin_based_exec_ctrl;
5144 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5146 struct vcpu_vmx *vmx = to_vmx(vcpu);
5148 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5149 if (cpu_has_secondary_exec_ctrls()) {
5150 if (kvm_vcpu_apicv_active(vcpu))
5151 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5152 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5153 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5155 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5156 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5157 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5160 if (cpu_has_vmx_msr_bitmap())
5161 vmx_set_msr_bitmap(vcpu);
5164 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5166 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5168 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5169 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5171 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5172 exec_control &= ~CPU_BASED_TPR_SHADOW;
5173 #ifdef CONFIG_X86_64
5174 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5175 CPU_BASED_CR8_LOAD_EXITING;
5179 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5180 CPU_BASED_CR3_LOAD_EXITING |
5181 CPU_BASED_INVLPG_EXITING;
5182 return exec_control;
5185 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5187 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5188 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5189 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5191 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5193 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5194 enable_unrestricted_guest = 0;
5195 /* Enable INVPCID for non-ept guests may cause performance regression. */
5196 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5198 if (!enable_unrestricted_guest)
5199 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5201 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5202 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5203 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5204 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5205 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5206 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5208 We can NOT enable shadow_vmcs here because we don't have yet
5211 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5214 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5216 return exec_control;
5219 static void ept_set_mmio_spte_mask(void)
5222 * EPT Misconfigurations can be generated if the value of bits 2:0
5223 * of an EPT paging-structure entry is 110b (write/execute).
5225 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5226 VMX_EPT_MISCONFIG_WX_VALUE);
5229 #define VMX_XSS_EXIT_BITMAP 0
5231 * Sets up the vmcs for emulated real mode.
5233 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5235 #ifdef CONFIG_X86_64
5241 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5242 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5244 if (enable_shadow_vmcs) {
5245 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5246 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5248 if (cpu_has_vmx_msr_bitmap())
5249 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5251 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5254 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5255 vmx->hv_deadline_tsc = -1;
5257 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5259 if (cpu_has_secondary_exec_ctrls()) {
5260 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5261 vmx_secondary_exec_control(vmx));
5264 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5265 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5266 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5267 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5268 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5270 vmcs_write16(GUEST_INTR_STATUS, 0);
5272 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5273 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5277 vmcs_write32(PLE_GAP, ple_gap);
5278 vmx->ple_window = ple_window;
5279 vmx->ple_window_dirty = true;
5282 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5283 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5284 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5286 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5287 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5288 vmx_set_constant_host_state(vmx);
5289 #ifdef CONFIG_X86_64
5290 rdmsrl(MSR_FS_BASE, a);
5291 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5292 rdmsrl(MSR_GS_BASE, a);
5293 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5295 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5296 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5299 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5300 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5301 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5302 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5303 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5305 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5306 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5308 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5309 u32 index = vmx_msr_index[i];
5310 u32 data_low, data_high;
5313 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5315 if (wrmsr_safe(index, data_low, data_high) < 0)
5317 vmx->guest_msrs[j].index = i;
5318 vmx->guest_msrs[j].data = 0;
5319 vmx->guest_msrs[j].mask = -1ull;
5324 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5326 /* 22.2.1, 20.8.1 */
5327 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5329 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5330 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5332 set_cr4_guest_host_mask(vmx);
5334 if (vmx_xsaves_supported())
5335 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5338 ASSERT(vmx->pml_pg);
5339 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5340 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5346 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5348 struct vcpu_vmx *vmx = to_vmx(vcpu);
5349 struct msr_data apic_base_msr;
5352 vmx->rmode.vm86_active = 0;
5354 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5355 kvm_set_cr8(vcpu, 0);
5358 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5359 MSR_IA32_APICBASE_ENABLE;
5360 if (kvm_vcpu_is_reset_bsp(vcpu))
5361 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5362 apic_base_msr.host_initiated = true;
5363 kvm_set_apic_base(vcpu, &apic_base_msr);
5366 vmx_segment_cache_clear(vmx);
5368 seg_setup(VCPU_SREG_CS);
5369 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5370 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5372 seg_setup(VCPU_SREG_DS);
5373 seg_setup(VCPU_SREG_ES);
5374 seg_setup(VCPU_SREG_FS);
5375 seg_setup(VCPU_SREG_GS);
5376 seg_setup(VCPU_SREG_SS);
5378 vmcs_write16(GUEST_TR_SELECTOR, 0);
5379 vmcs_writel(GUEST_TR_BASE, 0);
5380 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5381 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5383 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5384 vmcs_writel(GUEST_LDTR_BASE, 0);
5385 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5386 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5389 vmcs_write32(GUEST_SYSENTER_CS, 0);
5390 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5391 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5392 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5395 vmcs_writel(GUEST_RFLAGS, 0x02);
5396 kvm_rip_write(vcpu, 0xfff0);
5398 vmcs_writel(GUEST_GDTR_BASE, 0);
5399 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5401 vmcs_writel(GUEST_IDTR_BASE, 0);
5402 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5404 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5405 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5406 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5410 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5412 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5413 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5414 if (cpu_need_tpr_shadow(vcpu))
5415 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5416 __pa(vcpu->arch.apic->regs));
5417 vmcs_write32(TPR_THRESHOLD, 0);
5420 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5422 if (kvm_vcpu_apicv_active(vcpu))
5423 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5426 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5428 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5429 vmx->vcpu.arch.cr0 = cr0;
5430 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5431 vmx_set_cr4(vcpu, 0);
5432 vmx_set_efer(vcpu, 0);
5434 update_exception_bitmap(vcpu);
5436 vpid_sync_context(vmx->vpid);
5440 * In nested virtualization, check if L1 asked to exit on external interrupts.
5441 * For most existing hypervisors, this will always return true.
5443 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5445 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5446 PIN_BASED_EXT_INTR_MASK;
5450 * In nested virtualization, check if L1 has set
5451 * VM_EXIT_ACK_INTR_ON_EXIT
5453 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5455 return get_vmcs12(vcpu)->vm_exit_controls &
5456 VM_EXIT_ACK_INTR_ON_EXIT;
5459 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5461 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5462 PIN_BASED_NMI_EXITING;
5465 static void enable_irq_window(struct kvm_vcpu *vcpu)
5467 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5468 CPU_BASED_VIRTUAL_INTR_PENDING);
5471 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5473 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5474 enable_irq_window(vcpu);
5478 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5479 CPU_BASED_VIRTUAL_NMI_PENDING);
5482 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5484 struct vcpu_vmx *vmx = to_vmx(vcpu);
5486 int irq = vcpu->arch.interrupt.nr;
5488 trace_kvm_inj_virq(irq);
5490 ++vcpu->stat.irq_injections;
5491 if (vmx->rmode.vm86_active) {
5493 if (vcpu->arch.interrupt.soft)
5494 inc_eip = vcpu->arch.event_exit_inst_len;
5495 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5496 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5499 intr = irq | INTR_INFO_VALID_MASK;
5500 if (vcpu->arch.interrupt.soft) {
5501 intr |= INTR_TYPE_SOFT_INTR;
5502 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5503 vmx->vcpu.arch.event_exit_inst_len);
5505 intr |= INTR_TYPE_EXT_INTR;
5506 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5509 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5511 struct vcpu_vmx *vmx = to_vmx(vcpu);
5513 if (!is_guest_mode(vcpu)) {
5514 ++vcpu->stat.nmi_injections;
5515 vmx->nmi_known_unmasked = false;
5518 if (vmx->rmode.vm86_active) {
5519 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5520 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5524 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5525 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5528 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5530 if (to_vmx(vcpu)->nmi_known_unmasked)
5532 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5535 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5537 struct vcpu_vmx *vmx = to_vmx(vcpu);
5539 vmx->nmi_known_unmasked = !masked;
5541 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5542 GUEST_INTR_STATE_NMI);
5544 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5545 GUEST_INTR_STATE_NMI);
5548 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5550 if (to_vmx(vcpu)->nested.nested_run_pending)
5553 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5554 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5555 | GUEST_INTR_STATE_NMI));
5558 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5560 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5561 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5562 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5563 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5566 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5570 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5574 kvm->arch.tss_addr = addr;
5575 return init_rmode_tss(kvm);
5578 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5583 * Update instruction length as we may reinject the exception
5584 * from user space while in guest debugging mode.
5586 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5587 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5588 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5592 if (vcpu->guest_debug &
5593 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5610 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5611 int vec, u32 err_code)
5614 * Instruction with address size override prefix opcode 0x67
5615 * Cause the #SS fault with 0 error code in VM86 mode.
5617 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5618 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5619 if (vcpu->arch.halt_request) {
5620 vcpu->arch.halt_request = 0;
5621 return kvm_vcpu_halt(vcpu);
5629 * Forward all other exceptions that are valid in real mode.
5630 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5631 * the required debugging infrastructure rework.
5633 kvm_queue_exception(vcpu, vec);
5638 * Trigger machine check on the host. We assume all the MSRs are already set up
5639 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5640 * We pass a fake environment to the machine check handler because we want
5641 * the guest to be always treated like user space, no matter what context
5642 * it used internally.
5644 static void kvm_machine_check(void)
5646 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5647 struct pt_regs regs = {
5648 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5649 .flags = X86_EFLAGS_IF,
5652 do_machine_check(®s, 0);
5656 static int handle_machine_check(struct kvm_vcpu *vcpu)
5658 /* already handled by vcpu_run */
5662 static int handle_exception(struct kvm_vcpu *vcpu)
5664 struct vcpu_vmx *vmx = to_vmx(vcpu);
5665 struct kvm_run *kvm_run = vcpu->run;
5666 u32 intr_info, ex_no, error_code;
5667 unsigned long cr2, rip, dr6;
5669 enum emulation_result er;
5671 vect_info = vmx->idt_vectoring_info;
5672 intr_info = vmx->exit_intr_info;
5674 if (is_machine_check(intr_info))
5675 return handle_machine_check(vcpu);
5677 if (is_nmi(intr_info))
5678 return 1; /* already handled by vmx_vcpu_run() */
5680 if (is_invalid_opcode(intr_info)) {
5681 if (is_guest_mode(vcpu)) {
5682 kvm_queue_exception(vcpu, UD_VECTOR);
5685 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5686 if (er != EMULATE_DONE)
5687 kvm_queue_exception(vcpu, UD_VECTOR);
5692 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5693 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5696 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5697 * MMIO, it is better to report an internal error.
5698 * See the comments in vmx_handle_exit.
5700 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5701 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5702 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5703 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5704 vcpu->run->internal.ndata = 3;
5705 vcpu->run->internal.data[0] = vect_info;
5706 vcpu->run->internal.data[1] = intr_info;
5707 vcpu->run->internal.data[2] = error_code;
5711 if (is_page_fault(intr_info)) {
5712 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5713 /* EPT won't cause page fault directly */
5714 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5715 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5719 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5721 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5722 return handle_rmode_exception(vcpu, ex_no, error_code);
5726 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5729 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5730 if (!(vcpu->guest_debug &
5731 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5732 vcpu->arch.dr6 &= ~15;
5733 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5734 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5735 skip_emulated_instruction(vcpu);
5737 kvm_queue_exception(vcpu, DB_VECTOR);
5740 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5741 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5745 * Update instruction length as we may reinject #BP from
5746 * user space while in guest debugging mode. Reading it for
5747 * #DB as well causes no harm, it is not used in that case.
5749 vmx->vcpu.arch.event_exit_inst_len =
5750 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5751 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5752 rip = kvm_rip_read(vcpu);
5753 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5754 kvm_run->debug.arch.exception = ex_no;
5757 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5758 kvm_run->ex.exception = ex_no;
5759 kvm_run->ex.error_code = error_code;
5765 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5767 ++vcpu->stat.irq_exits;
5771 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5773 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5777 static int handle_io(struct kvm_vcpu *vcpu)
5779 unsigned long exit_qualification;
5780 int size, in, string, ret;
5783 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5784 string = (exit_qualification & 16) != 0;
5785 in = (exit_qualification & 8) != 0;
5787 ++vcpu->stat.io_exits;
5790 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5792 port = exit_qualification >> 16;
5793 size = (exit_qualification & 7) + 1;
5795 ret = kvm_skip_emulated_instruction(vcpu);
5798 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5799 * KVM_EXIT_DEBUG here.
5801 return kvm_fast_pio_out(vcpu, size, port) && ret;
5805 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5808 * Patch in the VMCALL instruction:
5810 hypercall[0] = 0x0f;
5811 hypercall[1] = 0x01;
5812 hypercall[2] = 0xc1;
5815 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5816 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5818 if (is_guest_mode(vcpu)) {
5819 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5820 unsigned long orig_val = val;
5823 * We get here when L2 changed cr0 in a way that did not change
5824 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5825 * but did change L0 shadowed bits. So we first calculate the
5826 * effective cr0 value that L1 would like to write into the
5827 * hardware. It consists of the L2-owned bits from the new
5828 * value combined with the L1-owned bits from L1's guest_cr0.
5830 val = (val & ~vmcs12->cr0_guest_host_mask) |
5831 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5833 if (!nested_guest_cr0_valid(vcpu, val))
5836 if (kvm_set_cr0(vcpu, val))
5838 vmcs_writel(CR0_READ_SHADOW, orig_val);
5841 if (to_vmx(vcpu)->nested.vmxon &&
5842 !nested_host_cr0_valid(vcpu, val))
5845 return kvm_set_cr0(vcpu, val);
5849 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5851 if (is_guest_mode(vcpu)) {
5852 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5853 unsigned long orig_val = val;
5855 /* analogously to handle_set_cr0 */
5856 val = (val & ~vmcs12->cr4_guest_host_mask) |
5857 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5858 if (kvm_set_cr4(vcpu, val))
5860 vmcs_writel(CR4_READ_SHADOW, orig_val);
5863 return kvm_set_cr4(vcpu, val);
5866 static int handle_cr(struct kvm_vcpu *vcpu)
5868 unsigned long exit_qualification, val;
5874 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5875 cr = exit_qualification & 15;
5876 reg = (exit_qualification >> 8) & 15;
5877 switch ((exit_qualification >> 4) & 3) {
5878 case 0: /* mov to cr */
5879 val = kvm_register_readl(vcpu, reg);
5880 trace_kvm_cr_write(cr, val);
5883 err = handle_set_cr0(vcpu, val);
5884 return kvm_complete_insn_gp(vcpu, err);
5886 err = kvm_set_cr3(vcpu, val);
5887 return kvm_complete_insn_gp(vcpu, err);
5889 err = handle_set_cr4(vcpu, val);
5890 return kvm_complete_insn_gp(vcpu, err);
5892 u8 cr8_prev = kvm_get_cr8(vcpu);
5894 err = kvm_set_cr8(vcpu, cr8);
5895 ret = kvm_complete_insn_gp(vcpu, err);
5896 if (lapic_in_kernel(vcpu))
5898 if (cr8_prev <= cr8)
5901 * TODO: we might be squashing a
5902 * KVM_GUESTDBG_SINGLESTEP-triggered
5903 * KVM_EXIT_DEBUG here.
5905 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5911 WARN_ONCE(1, "Guest should always own CR0.TS");
5912 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5913 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5914 return kvm_skip_emulated_instruction(vcpu);
5915 case 1: /*mov from cr*/
5918 val = kvm_read_cr3(vcpu);
5919 kvm_register_write(vcpu, reg, val);
5920 trace_kvm_cr_read(cr, val);
5921 return kvm_skip_emulated_instruction(vcpu);
5923 val = kvm_get_cr8(vcpu);
5924 kvm_register_write(vcpu, reg, val);
5925 trace_kvm_cr_read(cr, val);
5926 return kvm_skip_emulated_instruction(vcpu);
5930 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5931 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5932 kvm_lmsw(vcpu, val);
5934 return kvm_skip_emulated_instruction(vcpu);
5938 vcpu->run->exit_reason = 0;
5939 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5940 (int)(exit_qualification >> 4) & 3, cr);
5944 static int handle_dr(struct kvm_vcpu *vcpu)
5946 unsigned long exit_qualification;
5949 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5950 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5952 /* First, if DR does not exist, trigger UD */
5953 if (!kvm_require_dr(vcpu, dr))
5956 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5957 if (!kvm_require_cpl(vcpu, 0))
5959 dr7 = vmcs_readl(GUEST_DR7);
5962 * As the vm-exit takes precedence over the debug trap, we
5963 * need to emulate the latter, either for the host or the
5964 * guest debugging itself.
5966 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5967 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5968 vcpu->run->debug.arch.dr7 = dr7;
5969 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5970 vcpu->run->debug.arch.exception = DB_VECTOR;
5971 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5974 vcpu->arch.dr6 &= ~15;
5975 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5976 kvm_queue_exception(vcpu, DB_VECTOR);
5981 if (vcpu->guest_debug == 0) {
5982 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5983 CPU_BASED_MOV_DR_EXITING);
5986 * No more DR vmexits; force a reload of the debug registers
5987 * and reenter on this instruction. The next vmexit will
5988 * retrieve the full state of the debug registers.
5990 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5994 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5995 if (exit_qualification & TYPE_MOV_FROM_DR) {
5998 if (kvm_get_dr(vcpu, dr, &val))
6000 kvm_register_write(vcpu, reg, val);
6002 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6005 return kvm_skip_emulated_instruction(vcpu);
6008 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6010 return vcpu->arch.dr6;
6013 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6017 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6019 get_debugreg(vcpu->arch.db[0], 0);
6020 get_debugreg(vcpu->arch.db[1], 1);
6021 get_debugreg(vcpu->arch.db[2], 2);
6022 get_debugreg(vcpu->arch.db[3], 3);
6023 get_debugreg(vcpu->arch.dr6, 6);
6024 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6026 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6027 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6030 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6032 vmcs_writel(GUEST_DR7, val);
6035 static int handle_cpuid(struct kvm_vcpu *vcpu)
6037 return kvm_emulate_cpuid(vcpu);
6040 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6042 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6043 struct msr_data msr_info;
6045 msr_info.index = ecx;
6046 msr_info.host_initiated = false;
6047 if (vmx_get_msr(vcpu, &msr_info)) {
6048 trace_kvm_msr_read_ex(ecx);
6049 kvm_inject_gp(vcpu, 0);
6053 trace_kvm_msr_read(ecx, msr_info.data);
6055 /* FIXME: handling of bits 32:63 of rax, rdx */
6056 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6057 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6058 return kvm_skip_emulated_instruction(vcpu);
6061 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6063 struct msr_data msr;
6064 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6065 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6066 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6070 msr.host_initiated = false;
6071 if (kvm_set_msr(vcpu, &msr) != 0) {
6072 trace_kvm_msr_write_ex(ecx, data);
6073 kvm_inject_gp(vcpu, 0);
6077 trace_kvm_msr_write(ecx, data);
6078 return kvm_skip_emulated_instruction(vcpu);
6081 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6083 kvm_apic_update_ppr(vcpu);
6087 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6089 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6090 CPU_BASED_VIRTUAL_INTR_PENDING);
6092 kvm_make_request(KVM_REQ_EVENT, vcpu);
6094 ++vcpu->stat.irq_window_exits;
6098 static int handle_halt(struct kvm_vcpu *vcpu)
6100 return kvm_emulate_halt(vcpu);
6103 static int handle_vmcall(struct kvm_vcpu *vcpu)
6105 return kvm_emulate_hypercall(vcpu);
6108 static int handle_invd(struct kvm_vcpu *vcpu)
6110 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6113 static int handle_invlpg(struct kvm_vcpu *vcpu)
6115 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6117 kvm_mmu_invlpg(vcpu, exit_qualification);
6118 return kvm_skip_emulated_instruction(vcpu);
6121 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6125 err = kvm_rdpmc(vcpu);
6126 return kvm_complete_insn_gp(vcpu, err);
6129 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6131 return kvm_emulate_wbinvd(vcpu);
6134 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6136 u64 new_bv = kvm_read_edx_eax(vcpu);
6137 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6139 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6140 return kvm_skip_emulated_instruction(vcpu);
6144 static int handle_xsaves(struct kvm_vcpu *vcpu)
6146 kvm_skip_emulated_instruction(vcpu);
6147 WARN(1, "this should never happen\n");
6151 static int handle_xrstors(struct kvm_vcpu *vcpu)
6153 kvm_skip_emulated_instruction(vcpu);
6154 WARN(1, "this should never happen\n");
6158 static int handle_apic_access(struct kvm_vcpu *vcpu)
6160 if (likely(fasteoi)) {
6161 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6162 int access_type, offset;
6164 access_type = exit_qualification & APIC_ACCESS_TYPE;
6165 offset = exit_qualification & APIC_ACCESS_OFFSET;
6167 * Sane guest uses MOV to write EOI, with written value
6168 * not cared. So make a short-circuit here by avoiding
6169 * heavy instruction emulation.
6171 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6172 (offset == APIC_EOI)) {
6173 kvm_lapic_set_eoi(vcpu);
6174 return kvm_skip_emulated_instruction(vcpu);
6177 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6180 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6182 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6183 int vector = exit_qualification & 0xff;
6185 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6186 kvm_apic_set_eoi_accelerated(vcpu, vector);
6190 static int handle_apic_write(struct kvm_vcpu *vcpu)
6192 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6193 u32 offset = exit_qualification & 0xfff;
6195 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6196 kvm_apic_write_nodecode(vcpu, offset);
6200 static int handle_task_switch(struct kvm_vcpu *vcpu)
6202 struct vcpu_vmx *vmx = to_vmx(vcpu);
6203 unsigned long exit_qualification;
6204 bool has_error_code = false;
6207 int reason, type, idt_v, idt_index;
6209 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6210 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6211 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6213 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6215 reason = (u32)exit_qualification >> 30;
6216 if (reason == TASK_SWITCH_GATE && idt_v) {
6218 case INTR_TYPE_NMI_INTR:
6219 vcpu->arch.nmi_injected = false;
6220 vmx_set_nmi_mask(vcpu, true);
6222 case INTR_TYPE_EXT_INTR:
6223 case INTR_TYPE_SOFT_INTR:
6224 kvm_clear_interrupt_queue(vcpu);
6226 case INTR_TYPE_HARD_EXCEPTION:
6227 if (vmx->idt_vectoring_info &
6228 VECTORING_INFO_DELIVER_CODE_MASK) {
6229 has_error_code = true;
6231 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6234 case INTR_TYPE_SOFT_EXCEPTION:
6235 kvm_clear_exception_queue(vcpu);
6241 tss_selector = exit_qualification;
6243 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6244 type != INTR_TYPE_EXT_INTR &&
6245 type != INTR_TYPE_NMI_INTR))
6246 skip_emulated_instruction(vcpu);
6248 if (kvm_task_switch(vcpu, tss_selector,
6249 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6250 has_error_code, error_code) == EMULATE_FAIL) {
6251 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6252 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6253 vcpu->run->internal.ndata = 0;
6258 * TODO: What about debug traps on tss switch?
6259 * Are we supposed to inject them and update dr6?
6265 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6267 unsigned long exit_qualification;
6271 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6274 * EPT violation happened while executing iret from NMI,
6275 * "blocked by NMI" bit has to be set before next VM entry.
6276 * There are errata that may cause this bit to not be set:
6279 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6280 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6281 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6283 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6284 trace_kvm_page_fault(gpa, exit_qualification);
6286 /* Is it a read fault? */
6287 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6288 ? PFERR_USER_MASK : 0;
6289 /* Is it a write fault? */
6290 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6291 ? PFERR_WRITE_MASK : 0;
6292 /* Is it a fetch fault? */
6293 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6294 ? PFERR_FETCH_MASK : 0;
6295 /* ept page table entry is present? */
6296 error_code |= (exit_qualification &
6297 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6298 EPT_VIOLATION_EXECUTABLE))
6299 ? PFERR_PRESENT_MASK : 0;
6301 vcpu->arch.gpa_available = true;
6302 vcpu->arch.exit_qualification = exit_qualification;
6304 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6307 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6312 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6313 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6314 trace_kvm_fast_mmio(gpa);
6315 return kvm_skip_emulated_instruction(vcpu);
6318 ret = handle_mmio_page_fault(vcpu, gpa, true);
6319 vcpu->arch.gpa_available = true;
6320 if (likely(ret == RET_MMIO_PF_EMULATE))
6321 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6324 if (unlikely(ret == RET_MMIO_PF_INVALID))
6325 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6327 if (unlikely(ret == RET_MMIO_PF_RETRY))
6330 /* It is the real ept misconfig */
6333 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6334 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6339 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6341 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6342 CPU_BASED_VIRTUAL_NMI_PENDING);
6343 ++vcpu->stat.nmi_window_exits;
6344 kvm_make_request(KVM_REQ_EVENT, vcpu);
6349 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6351 struct vcpu_vmx *vmx = to_vmx(vcpu);
6352 enum emulation_result err = EMULATE_DONE;
6355 bool intr_window_requested;
6356 unsigned count = 130;
6358 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6359 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6361 while (vmx->emulation_required && count-- != 0) {
6362 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6363 return handle_interrupt_window(&vmx->vcpu);
6365 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6368 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6370 if (err == EMULATE_USER_EXIT) {
6371 ++vcpu->stat.mmio_exits;
6376 if (err != EMULATE_DONE) {
6377 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6378 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6379 vcpu->run->internal.ndata = 0;
6383 if (vcpu->arch.halt_request) {
6384 vcpu->arch.halt_request = 0;
6385 ret = kvm_vcpu_halt(vcpu);
6389 if (signal_pending(current))
6399 static int __grow_ple_window(int val)
6401 if (ple_window_grow < 1)
6404 val = min(val, ple_window_actual_max);
6406 if (ple_window_grow < ple_window)
6407 val *= ple_window_grow;
6409 val += ple_window_grow;
6414 static int __shrink_ple_window(int val, int modifier, int minimum)
6419 if (modifier < ple_window)
6424 return max(val, minimum);
6427 static void grow_ple_window(struct kvm_vcpu *vcpu)
6429 struct vcpu_vmx *vmx = to_vmx(vcpu);
6430 int old = vmx->ple_window;
6432 vmx->ple_window = __grow_ple_window(old);
6434 if (vmx->ple_window != old)
6435 vmx->ple_window_dirty = true;
6437 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6440 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6442 struct vcpu_vmx *vmx = to_vmx(vcpu);
6443 int old = vmx->ple_window;
6445 vmx->ple_window = __shrink_ple_window(old,
6446 ple_window_shrink, ple_window);
6448 if (vmx->ple_window != old)
6449 vmx->ple_window_dirty = true;
6451 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6455 * ple_window_actual_max is computed to be one grow_ple_window() below
6456 * ple_window_max. (See __grow_ple_window for the reason.)
6457 * This prevents overflows, because ple_window_max is int.
6458 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6460 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6462 static void update_ple_window_actual_max(void)
6464 ple_window_actual_max =
6465 __shrink_ple_window(max(ple_window_max, ple_window),
6466 ple_window_grow, INT_MIN);
6470 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6472 static void wakeup_handler(void)
6474 struct kvm_vcpu *vcpu;
6475 int cpu = smp_processor_id();
6477 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6478 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6479 blocked_vcpu_list) {
6480 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6482 if (pi_test_on(pi_desc) == 1)
6483 kvm_vcpu_kick(vcpu);
6485 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6488 void vmx_enable_tdp(void)
6490 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6491 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6492 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6493 0ull, VMX_EPT_EXECUTABLE_MASK,
6494 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6497 ept_set_mmio_spte_mask();
6501 static __init int hardware_setup(void)
6503 int r = -ENOMEM, i, msr;
6505 rdmsrl_safe(MSR_EFER, &host_efer);
6507 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6508 kvm_define_shared_msr(i, vmx_msr_index[i]);
6510 for (i = 0; i < VMX_BITMAP_NR; i++) {
6511 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6516 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6517 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6518 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6521 * Allow direct access to the PC debug port (it is often used for I/O
6522 * delays, but the vmexits simply slow things down).
6524 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6525 clear_bit(0x80, vmx_io_bitmap_a);
6527 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6529 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6530 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6532 if (setup_vmcs_config(&vmcs_config) < 0) {
6537 if (boot_cpu_has(X86_FEATURE_NX))
6538 kvm_enable_efer_bits(EFER_NX);
6540 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6541 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6544 if (!cpu_has_vmx_shadow_vmcs())
6545 enable_shadow_vmcs = 0;
6546 if (enable_shadow_vmcs)
6547 init_vmcs_shadow_fields();
6549 if (!cpu_has_vmx_ept() ||
6550 !cpu_has_vmx_ept_4levels()) {
6552 enable_unrestricted_guest = 0;
6553 enable_ept_ad_bits = 0;
6556 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6557 enable_ept_ad_bits = 0;
6559 if (!cpu_has_vmx_unrestricted_guest())
6560 enable_unrestricted_guest = 0;
6562 if (!cpu_has_vmx_flexpriority())
6563 flexpriority_enabled = 0;
6566 * set_apic_access_page_addr() is used to reload apic access
6567 * page upon invalidation. No need to do anything if not
6568 * using the APIC_ACCESS_ADDR VMCS field.
6570 if (!flexpriority_enabled)
6571 kvm_x86_ops->set_apic_access_page_addr = NULL;
6573 if (!cpu_has_vmx_tpr_shadow())
6574 kvm_x86_ops->update_cr8_intercept = NULL;
6576 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6577 kvm_disable_largepages();
6579 if (!cpu_has_vmx_ple())
6582 if (!cpu_has_vmx_apicv()) {
6584 kvm_x86_ops->sync_pir_to_irr = NULL;
6587 if (cpu_has_vmx_tsc_scaling()) {
6588 kvm_has_tsc_control = true;
6589 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6590 kvm_tsc_scaling_ratio_frac_bits = 48;
6593 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6594 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6595 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6596 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6597 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6598 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6600 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6601 vmx_msr_bitmap_legacy, PAGE_SIZE);
6602 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6603 vmx_msr_bitmap_longmode, PAGE_SIZE);
6604 memcpy(vmx_msr_bitmap_legacy_x2apic,
6605 vmx_msr_bitmap_legacy, PAGE_SIZE);
6606 memcpy(vmx_msr_bitmap_longmode_x2apic,
6607 vmx_msr_bitmap_longmode, PAGE_SIZE);
6609 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6611 for (msr = 0x800; msr <= 0x8ff; msr++) {
6612 if (msr == 0x839 /* TMCCT */)
6614 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6618 * TPR reads and writes can be virtualized even if virtual interrupt
6619 * delivery is not in use.
6621 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6622 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6625 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6627 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6634 update_ple_window_actual_max();
6637 * Only enable PML when hardware supports PML feature, and both EPT
6638 * and EPT A/D bit features are enabled -- PML depends on them to work.
6640 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6644 kvm_x86_ops->slot_enable_log_dirty = NULL;
6645 kvm_x86_ops->slot_disable_log_dirty = NULL;
6646 kvm_x86_ops->flush_log_dirty = NULL;
6647 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6650 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6653 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6654 cpu_preemption_timer_multi =
6655 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6657 kvm_x86_ops->set_hv_timer = NULL;
6658 kvm_x86_ops->cancel_hv_timer = NULL;
6661 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6663 kvm_mce_cap_supported |= MCG_LMCE_P;
6665 return alloc_kvm_area();
6668 for (i = 0; i < VMX_BITMAP_NR; i++)
6669 free_page((unsigned long)vmx_bitmap[i]);
6674 static __exit void hardware_unsetup(void)
6678 for (i = 0; i < VMX_BITMAP_NR; i++)
6679 free_page((unsigned long)vmx_bitmap[i]);
6685 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6686 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6688 static int handle_pause(struct kvm_vcpu *vcpu)
6691 grow_ple_window(vcpu);
6693 kvm_vcpu_on_spin(vcpu);
6694 return kvm_skip_emulated_instruction(vcpu);
6697 static int handle_nop(struct kvm_vcpu *vcpu)
6699 return kvm_skip_emulated_instruction(vcpu);
6702 static int handle_mwait(struct kvm_vcpu *vcpu)
6704 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6705 return handle_nop(vcpu);
6708 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6713 static int handle_monitor(struct kvm_vcpu *vcpu)
6715 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6716 return handle_nop(vcpu);
6720 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6721 * We could reuse a single VMCS for all the L2 guests, but we also want the
6722 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6723 * allows keeping them loaded on the processor, and in the future will allow
6724 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6725 * every entry if they never change.
6726 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6727 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6729 * The following functions allocate and free a vmcs02 in this pool.
6732 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6733 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6735 struct vmcs02_list *item;
6736 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6737 if (item->vmptr == vmx->nested.current_vmptr) {
6738 list_move(&item->list, &vmx->nested.vmcs02_pool);
6739 return &item->vmcs02;
6742 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6743 /* Recycle the least recently used VMCS. */
6744 item = list_last_entry(&vmx->nested.vmcs02_pool,
6745 struct vmcs02_list, list);
6746 item->vmptr = vmx->nested.current_vmptr;
6747 list_move(&item->list, &vmx->nested.vmcs02_pool);
6748 return &item->vmcs02;
6751 /* Create a new VMCS */
6752 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6755 item->vmcs02.vmcs = alloc_vmcs();
6756 item->vmcs02.shadow_vmcs = NULL;
6757 if (!item->vmcs02.vmcs) {
6761 loaded_vmcs_init(&item->vmcs02);
6762 item->vmptr = vmx->nested.current_vmptr;
6763 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6764 vmx->nested.vmcs02_num++;
6765 return &item->vmcs02;
6768 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6769 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6771 struct vmcs02_list *item;
6772 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6773 if (item->vmptr == vmptr) {
6774 free_loaded_vmcs(&item->vmcs02);
6775 list_del(&item->list);
6777 vmx->nested.vmcs02_num--;
6783 * Free all VMCSs saved for this vcpu, except the one pointed by
6784 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6785 * must be &vmx->vmcs01.
6787 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6789 struct vmcs02_list *item, *n;
6791 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6792 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6794 * Something will leak if the above WARN triggers. Better than
6797 if (vmx->loaded_vmcs == &item->vmcs02)
6800 free_loaded_vmcs(&item->vmcs02);
6801 list_del(&item->list);
6803 vmx->nested.vmcs02_num--;
6808 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6809 * set the success or error code of an emulated VMX instruction, as specified
6810 * by Vol 2B, VMX Instruction Reference, "Conventions".
6812 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6814 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6815 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6816 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6819 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6821 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6822 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6823 X86_EFLAGS_SF | X86_EFLAGS_OF))
6827 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6828 u32 vm_instruction_error)
6830 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6832 * failValid writes the error number to the current VMCS, which
6833 * can't be done there isn't a current VMCS.
6835 nested_vmx_failInvalid(vcpu);
6838 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6839 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6840 X86_EFLAGS_SF | X86_EFLAGS_OF))
6842 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6844 * We don't need to force a shadow sync because
6845 * VM_INSTRUCTION_ERROR is not shadowed
6849 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6851 /* TODO: not to reset guest simply here. */
6852 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6853 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6856 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6858 struct vcpu_vmx *vmx =
6859 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6861 vmx->nested.preemption_timer_expired = true;
6862 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6863 kvm_vcpu_kick(&vmx->vcpu);
6865 return HRTIMER_NORESTART;
6869 * Decode the memory-address operand of a vmx instruction, as recorded on an
6870 * exit caused by such an instruction (run by a guest hypervisor).
6871 * On success, returns 0. When the operand is invalid, returns 1 and throws
6874 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6875 unsigned long exit_qualification,
6876 u32 vmx_instruction_info, bool wr, gva_t *ret)
6880 struct kvm_segment s;
6883 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6884 * Execution", on an exit, vmx_instruction_info holds most of the
6885 * addressing components of the operand. Only the displacement part
6886 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6887 * For how an actual address is calculated from all these components,
6888 * refer to Vol. 1, "Operand Addressing".
6890 int scaling = vmx_instruction_info & 3;
6891 int addr_size = (vmx_instruction_info >> 7) & 7;
6892 bool is_reg = vmx_instruction_info & (1u << 10);
6893 int seg_reg = (vmx_instruction_info >> 15) & 7;
6894 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6895 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6896 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6897 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6900 kvm_queue_exception(vcpu, UD_VECTOR);
6904 /* Addr = segment_base + offset */
6905 /* offset = base + [index * scale] + displacement */
6906 off = exit_qualification; /* holds the displacement */
6908 off += kvm_register_read(vcpu, base_reg);
6910 off += kvm_register_read(vcpu, index_reg)<<scaling;
6911 vmx_get_segment(vcpu, &s, seg_reg);
6912 *ret = s.base + off;
6914 if (addr_size == 1) /* 32 bit */
6917 /* Checks for #GP/#SS exceptions. */
6919 if (is_long_mode(vcpu)) {
6920 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6921 * non-canonical form. This is the only check on the memory
6922 * destination for long mode!
6924 exn = is_noncanonical_address(*ret);
6925 } else if (is_protmode(vcpu)) {
6926 /* Protected mode: apply checks for segment validity in the
6928 * - segment type check (#GP(0) may be thrown)
6929 * - usability check (#GP(0)/#SS(0))
6930 * - limit check (#GP(0)/#SS(0))
6933 /* #GP(0) if the destination operand is located in a
6934 * read-only data segment or any code segment.
6936 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6938 /* #GP(0) if the source operand is located in an
6939 * execute-only code segment
6941 exn = ((s.type & 0xa) == 8);
6943 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6946 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6948 exn = (s.unusable != 0);
6949 /* Protected mode: #GP(0)/#SS(0) if the memory
6950 * operand is outside the segment limit.
6952 exn = exn || (off + sizeof(u64) > s.limit);
6955 kvm_queue_exception_e(vcpu,
6956 seg_reg == VCPU_SREG_SS ?
6957 SS_VECTOR : GP_VECTOR,
6965 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
6968 struct x86_exception e;
6970 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6971 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6974 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6975 sizeof(*vmpointer), &e)) {
6976 kvm_inject_page_fault(vcpu, &e);
6983 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6985 struct vcpu_vmx *vmx = to_vmx(vcpu);
6986 struct vmcs *shadow_vmcs;
6988 if (cpu_has_vmx_msr_bitmap()) {
6989 vmx->nested.msr_bitmap =
6990 (unsigned long *)__get_free_page(GFP_KERNEL);
6991 if (!vmx->nested.msr_bitmap)
6992 goto out_msr_bitmap;
6995 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6996 if (!vmx->nested.cached_vmcs12)
6997 goto out_cached_vmcs12;
6999 if (enable_shadow_vmcs) {
7000 shadow_vmcs = alloc_vmcs();
7002 goto out_shadow_vmcs;
7003 /* mark vmcs as shadow */
7004 shadow_vmcs->revision_id |= (1u << 31);
7005 /* init shadow vmcs */
7006 vmcs_clear(shadow_vmcs);
7007 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7010 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7011 vmx->nested.vmcs02_num = 0;
7013 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7014 HRTIMER_MODE_REL_PINNED);
7015 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7017 vmx->nested.vmxon = true;
7021 kfree(vmx->nested.cached_vmcs12);
7024 free_page((unsigned long)vmx->nested.msr_bitmap);
7031 * Emulate the VMXON instruction.
7032 * Currently, we just remember that VMX is active, and do not save or even
7033 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7034 * do not currently need to store anything in that guest-allocated memory
7035 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7036 * argument is different from the VMXON pointer (which the spec says they do).
7038 static int handle_vmon(struct kvm_vcpu *vcpu)
7043 struct vcpu_vmx *vmx = to_vmx(vcpu);
7044 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7045 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7048 * The Intel VMX Instruction Reference lists a bunch of bits that are
7049 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7050 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7051 * Otherwise, we should fail with #UD. But most faulting conditions
7052 * have already been checked by hardware, prior to the VM-exit for
7053 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7054 * that bit set to 1 in non-root mode.
7056 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7057 kvm_queue_exception(vcpu, UD_VECTOR);
7061 if (vmx->nested.vmxon) {
7062 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7063 return kvm_skip_emulated_instruction(vcpu);
7066 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7067 != VMXON_NEEDED_FEATURES) {
7068 kvm_inject_gp(vcpu, 0);
7072 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7077 * The first 4 bytes of VMXON region contain the supported
7078 * VMCS revision identifier
7080 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7081 * which replaces physical address width with 32
7083 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7084 nested_vmx_failInvalid(vcpu);
7085 return kvm_skip_emulated_instruction(vcpu);
7088 page = nested_get_page(vcpu, vmptr);
7090 nested_vmx_failInvalid(vcpu);
7091 return kvm_skip_emulated_instruction(vcpu);
7093 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7095 nested_release_page_clean(page);
7096 nested_vmx_failInvalid(vcpu);
7097 return kvm_skip_emulated_instruction(vcpu);
7100 nested_release_page_clean(page);
7102 vmx->nested.vmxon_ptr = vmptr;
7103 ret = enter_vmx_operation(vcpu);
7107 nested_vmx_succeed(vcpu);
7108 return kvm_skip_emulated_instruction(vcpu);
7112 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7113 * for running VMX instructions (except VMXON, whose prerequisites are
7114 * slightly different). It also specifies what exception to inject otherwise.
7115 * Note that many of these exceptions have priority over VM exits, so they
7116 * don't have to be checked again here.
7118 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7120 if (!to_vmx(vcpu)->nested.vmxon) {
7121 kvm_queue_exception(vcpu, UD_VECTOR);
7127 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7129 if (vmx->nested.current_vmptr == -1ull)
7132 /* current_vmptr and current_vmcs12 are always set/reset together */
7133 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7136 if (enable_shadow_vmcs) {
7137 /* copy to memory all shadowed fields in case
7138 they were modified */
7139 copy_shadow_to_vmcs12(vmx);
7140 vmx->nested.sync_shadow_vmcs = false;
7141 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7142 SECONDARY_EXEC_SHADOW_VMCS);
7143 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7145 vmx->nested.posted_intr_nv = -1;
7147 /* Flush VMCS12 to guest memory */
7148 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7151 kunmap(vmx->nested.current_vmcs12_page);
7152 nested_release_page(vmx->nested.current_vmcs12_page);
7153 vmx->nested.current_vmptr = -1ull;
7154 vmx->nested.current_vmcs12 = NULL;
7158 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7159 * just stops using VMX.
7161 static void free_nested(struct vcpu_vmx *vmx)
7163 if (!vmx->nested.vmxon)
7166 vmx->nested.vmxon = false;
7167 free_vpid(vmx->nested.vpid02);
7168 nested_release_vmcs12(vmx);
7169 if (vmx->nested.msr_bitmap) {
7170 free_page((unsigned long)vmx->nested.msr_bitmap);
7171 vmx->nested.msr_bitmap = NULL;
7173 if (enable_shadow_vmcs) {
7174 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7175 free_vmcs(vmx->vmcs01.shadow_vmcs);
7176 vmx->vmcs01.shadow_vmcs = NULL;
7178 kfree(vmx->nested.cached_vmcs12);
7179 /* Unpin physical memory we referred to in current vmcs02 */
7180 if (vmx->nested.apic_access_page) {
7181 nested_release_page(vmx->nested.apic_access_page);
7182 vmx->nested.apic_access_page = NULL;
7184 if (vmx->nested.virtual_apic_page) {
7185 nested_release_page(vmx->nested.virtual_apic_page);
7186 vmx->nested.virtual_apic_page = NULL;
7188 if (vmx->nested.pi_desc_page) {
7189 kunmap(vmx->nested.pi_desc_page);
7190 nested_release_page(vmx->nested.pi_desc_page);
7191 vmx->nested.pi_desc_page = NULL;
7192 vmx->nested.pi_desc = NULL;
7195 nested_free_all_saved_vmcss(vmx);
7198 /* Emulate the VMXOFF instruction */
7199 static int handle_vmoff(struct kvm_vcpu *vcpu)
7201 if (!nested_vmx_check_permission(vcpu))
7203 free_nested(to_vmx(vcpu));
7204 nested_vmx_succeed(vcpu);
7205 return kvm_skip_emulated_instruction(vcpu);
7208 /* Emulate the VMCLEAR instruction */
7209 static int handle_vmclear(struct kvm_vcpu *vcpu)
7211 struct vcpu_vmx *vmx = to_vmx(vcpu);
7215 if (!nested_vmx_check_permission(vcpu))
7218 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7221 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7222 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7223 return kvm_skip_emulated_instruction(vcpu);
7226 if (vmptr == vmx->nested.vmxon_ptr) {
7227 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7228 return kvm_skip_emulated_instruction(vcpu);
7231 if (vmptr == vmx->nested.current_vmptr)
7232 nested_release_vmcs12(vmx);
7234 kvm_vcpu_write_guest(vcpu,
7235 vmptr + offsetof(struct vmcs12, launch_state),
7236 &zero, sizeof(zero));
7238 nested_free_vmcs02(vmx, vmptr);
7240 nested_vmx_succeed(vcpu);
7241 return kvm_skip_emulated_instruction(vcpu);
7244 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7246 /* Emulate the VMLAUNCH instruction */
7247 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7249 return nested_vmx_run(vcpu, true);
7252 /* Emulate the VMRESUME instruction */
7253 static int handle_vmresume(struct kvm_vcpu *vcpu)
7256 return nested_vmx_run(vcpu, false);
7260 * Read a vmcs12 field. Since these can have varying lengths and we return
7261 * one type, we chose the biggest type (u64) and zero-extend the return value
7262 * to that size. Note that the caller, handle_vmread, might need to use only
7263 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7264 * 64-bit fields are to be returned).
7266 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7267 unsigned long field, u64 *ret)
7269 short offset = vmcs_field_to_offset(field);
7275 p = ((char *)(get_vmcs12(vcpu))) + offset;
7277 switch (vmcs_field_type(field)) {
7278 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7279 *ret = *((natural_width *)p);
7281 case VMCS_FIELD_TYPE_U16:
7284 case VMCS_FIELD_TYPE_U32:
7287 case VMCS_FIELD_TYPE_U64:
7297 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7298 unsigned long field, u64 field_value){
7299 short offset = vmcs_field_to_offset(field);
7300 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7304 switch (vmcs_field_type(field)) {
7305 case VMCS_FIELD_TYPE_U16:
7306 *(u16 *)p = field_value;
7308 case VMCS_FIELD_TYPE_U32:
7309 *(u32 *)p = field_value;
7311 case VMCS_FIELD_TYPE_U64:
7312 *(u64 *)p = field_value;
7314 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7315 *(natural_width *)p = field_value;
7324 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7327 unsigned long field;
7329 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7330 const unsigned long *fields = shadow_read_write_fields;
7331 const int num_fields = max_shadow_read_write_fields;
7335 vmcs_load(shadow_vmcs);
7337 for (i = 0; i < num_fields; i++) {
7339 switch (vmcs_field_type(field)) {
7340 case VMCS_FIELD_TYPE_U16:
7341 field_value = vmcs_read16(field);
7343 case VMCS_FIELD_TYPE_U32:
7344 field_value = vmcs_read32(field);
7346 case VMCS_FIELD_TYPE_U64:
7347 field_value = vmcs_read64(field);
7349 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7350 field_value = vmcs_readl(field);
7356 vmcs12_write_any(&vmx->vcpu, field, field_value);
7359 vmcs_clear(shadow_vmcs);
7360 vmcs_load(vmx->loaded_vmcs->vmcs);
7365 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7367 const unsigned long *fields[] = {
7368 shadow_read_write_fields,
7369 shadow_read_only_fields
7371 const int max_fields[] = {
7372 max_shadow_read_write_fields,
7373 max_shadow_read_only_fields
7376 unsigned long field;
7377 u64 field_value = 0;
7378 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7380 vmcs_load(shadow_vmcs);
7382 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7383 for (i = 0; i < max_fields[q]; i++) {
7384 field = fields[q][i];
7385 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7387 switch (vmcs_field_type(field)) {
7388 case VMCS_FIELD_TYPE_U16:
7389 vmcs_write16(field, (u16)field_value);
7391 case VMCS_FIELD_TYPE_U32:
7392 vmcs_write32(field, (u32)field_value);
7394 case VMCS_FIELD_TYPE_U64:
7395 vmcs_write64(field, (u64)field_value);
7397 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7398 vmcs_writel(field, (long)field_value);
7407 vmcs_clear(shadow_vmcs);
7408 vmcs_load(vmx->loaded_vmcs->vmcs);
7412 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7413 * used before) all generate the same failure when it is missing.
7415 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7417 struct vcpu_vmx *vmx = to_vmx(vcpu);
7418 if (vmx->nested.current_vmptr == -1ull) {
7419 nested_vmx_failInvalid(vcpu);
7425 static int handle_vmread(struct kvm_vcpu *vcpu)
7427 unsigned long field;
7429 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7430 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7433 if (!nested_vmx_check_permission(vcpu))
7436 if (!nested_vmx_check_vmcs12(vcpu))
7437 return kvm_skip_emulated_instruction(vcpu);
7439 /* Decode instruction info and find the field to read */
7440 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7441 /* Read the field, zero-extended to a u64 field_value */
7442 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7443 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7444 return kvm_skip_emulated_instruction(vcpu);
7447 * Now copy part of this value to register or memory, as requested.
7448 * Note that the number of bits actually copied is 32 or 64 depending
7449 * on the guest's mode (32 or 64 bit), not on the given field's length.
7451 if (vmx_instruction_info & (1u << 10)) {
7452 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7455 if (get_vmx_mem_address(vcpu, exit_qualification,
7456 vmx_instruction_info, true, &gva))
7458 /* _system ok, as hardware has verified cpl=0 */
7459 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7460 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7463 nested_vmx_succeed(vcpu);
7464 return kvm_skip_emulated_instruction(vcpu);
7468 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7470 unsigned long field;
7472 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7473 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7474 /* The value to write might be 32 or 64 bits, depending on L1's long
7475 * mode, and eventually we need to write that into a field of several
7476 * possible lengths. The code below first zero-extends the value to 64
7477 * bit (field_value), and then copies only the appropriate number of
7478 * bits into the vmcs12 field.
7480 u64 field_value = 0;
7481 struct x86_exception e;
7483 if (!nested_vmx_check_permission(vcpu))
7486 if (!nested_vmx_check_vmcs12(vcpu))
7487 return kvm_skip_emulated_instruction(vcpu);
7489 if (vmx_instruction_info & (1u << 10))
7490 field_value = kvm_register_readl(vcpu,
7491 (((vmx_instruction_info) >> 3) & 0xf));
7493 if (get_vmx_mem_address(vcpu, exit_qualification,
7494 vmx_instruction_info, false, &gva))
7496 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7497 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7498 kvm_inject_page_fault(vcpu, &e);
7504 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7505 if (vmcs_field_readonly(field)) {
7506 nested_vmx_failValid(vcpu,
7507 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7508 return kvm_skip_emulated_instruction(vcpu);
7511 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7512 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7513 return kvm_skip_emulated_instruction(vcpu);
7516 nested_vmx_succeed(vcpu);
7517 return kvm_skip_emulated_instruction(vcpu);
7520 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7522 vmx->nested.current_vmptr = vmptr;
7523 if (enable_shadow_vmcs) {
7524 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7525 SECONDARY_EXEC_SHADOW_VMCS);
7526 vmcs_write64(VMCS_LINK_POINTER,
7527 __pa(vmx->vmcs01.shadow_vmcs));
7528 vmx->nested.sync_shadow_vmcs = true;
7532 /* Emulate the VMPTRLD instruction */
7533 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7535 struct vcpu_vmx *vmx = to_vmx(vcpu);
7538 if (!nested_vmx_check_permission(vcpu))
7541 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7544 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7545 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7546 return kvm_skip_emulated_instruction(vcpu);
7549 if (vmptr == vmx->nested.vmxon_ptr) {
7550 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7551 return kvm_skip_emulated_instruction(vcpu);
7554 if (vmx->nested.current_vmptr != vmptr) {
7555 struct vmcs12 *new_vmcs12;
7557 page = nested_get_page(vcpu, vmptr);
7559 nested_vmx_failInvalid(vcpu);
7560 return kvm_skip_emulated_instruction(vcpu);
7562 new_vmcs12 = kmap(page);
7563 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7565 nested_release_page_clean(page);
7566 nested_vmx_failValid(vcpu,
7567 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7568 return kvm_skip_emulated_instruction(vcpu);
7571 nested_release_vmcs12(vmx);
7572 vmx->nested.current_vmcs12 = new_vmcs12;
7573 vmx->nested.current_vmcs12_page = page;
7575 * Load VMCS12 from guest memory since it is not already
7578 memcpy(vmx->nested.cached_vmcs12,
7579 vmx->nested.current_vmcs12, VMCS12_SIZE);
7580 set_current_vmptr(vmx, vmptr);
7583 nested_vmx_succeed(vcpu);
7584 return kvm_skip_emulated_instruction(vcpu);
7587 /* Emulate the VMPTRST instruction */
7588 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7590 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7591 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7593 struct x86_exception e;
7595 if (!nested_vmx_check_permission(vcpu))
7598 if (get_vmx_mem_address(vcpu, exit_qualification,
7599 vmx_instruction_info, true, &vmcs_gva))
7601 /* ok to use *_system, as hardware has verified cpl=0 */
7602 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7603 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7605 kvm_inject_page_fault(vcpu, &e);
7608 nested_vmx_succeed(vcpu);
7609 return kvm_skip_emulated_instruction(vcpu);
7612 /* Emulate the INVEPT instruction */
7613 static int handle_invept(struct kvm_vcpu *vcpu)
7615 struct vcpu_vmx *vmx = to_vmx(vcpu);
7616 u32 vmx_instruction_info, types;
7619 struct x86_exception e;
7624 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7625 SECONDARY_EXEC_ENABLE_EPT) ||
7626 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7627 kvm_queue_exception(vcpu, UD_VECTOR);
7631 if (!nested_vmx_check_permission(vcpu))
7634 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7635 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7637 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7639 if (type >= 32 || !(types & (1 << type))) {
7640 nested_vmx_failValid(vcpu,
7641 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7642 return kvm_skip_emulated_instruction(vcpu);
7645 /* According to the Intel VMX instruction reference, the memory
7646 * operand is read even if it isn't needed (e.g., for type==global)
7648 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7649 vmx_instruction_info, false, &gva))
7651 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7652 sizeof(operand), &e)) {
7653 kvm_inject_page_fault(vcpu, &e);
7658 case VMX_EPT_EXTENT_GLOBAL:
7660 * TODO: track mappings and invalidate
7661 * single context requests appropriately
7663 case VMX_EPT_EXTENT_CONTEXT:
7664 kvm_mmu_sync_roots(vcpu);
7665 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7666 nested_vmx_succeed(vcpu);
7673 return kvm_skip_emulated_instruction(vcpu);
7676 static int handle_invvpid(struct kvm_vcpu *vcpu)
7678 struct vcpu_vmx *vmx = to_vmx(vcpu);
7679 u32 vmx_instruction_info;
7680 unsigned long type, types;
7682 struct x86_exception e;
7688 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7689 SECONDARY_EXEC_ENABLE_VPID) ||
7690 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7691 kvm_queue_exception(vcpu, UD_VECTOR);
7695 if (!nested_vmx_check_permission(vcpu))
7698 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7699 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7701 types = (vmx->nested.nested_vmx_vpid_caps &
7702 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7704 if (type >= 32 || !(types & (1 << type))) {
7705 nested_vmx_failValid(vcpu,
7706 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7707 return kvm_skip_emulated_instruction(vcpu);
7710 /* according to the intel vmx instruction reference, the memory
7711 * operand is read even if it isn't needed (e.g., for type==global)
7713 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7714 vmx_instruction_info, false, &gva))
7716 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7717 sizeof(operand), &e)) {
7718 kvm_inject_page_fault(vcpu, &e);
7721 if (operand.vpid >> 16) {
7722 nested_vmx_failValid(vcpu,
7723 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7724 return kvm_skip_emulated_instruction(vcpu);
7728 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7729 if (is_noncanonical_address(operand.gla)) {
7730 nested_vmx_failValid(vcpu,
7731 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7732 return kvm_skip_emulated_instruction(vcpu);
7735 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7736 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7737 if (!operand.vpid) {
7738 nested_vmx_failValid(vcpu,
7739 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7740 return kvm_skip_emulated_instruction(vcpu);
7743 case VMX_VPID_EXTENT_ALL_CONTEXT:
7747 return kvm_skip_emulated_instruction(vcpu);
7750 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7751 nested_vmx_succeed(vcpu);
7753 return kvm_skip_emulated_instruction(vcpu);
7756 static int handle_pml_full(struct kvm_vcpu *vcpu)
7758 unsigned long exit_qualification;
7760 trace_kvm_pml_full(vcpu->vcpu_id);
7762 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7765 * PML buffer FULL happened while executing iret from NMI,
7766 * "blocked by NMI" bit has to be set before next VM entry.
7768 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7769 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7770 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7771 GUEST_INTR_STATE_NMI);
7774 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7775 * here.., and there's no userspace involvement needed for PML.
7780 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7782 kvm_lapic_expired_hv_timer(vcpu);
7787 * The exit handlers return 1 if the exit was handled fully and guest execution
7788 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7789 * to be done to userspace and return 0.
7791 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7792 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7793 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7794 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7795 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7796 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7797 [EXIT_REASON_CR_ACCESS] = handle_cr,
7798 [EXIT_REASON_DR_ACCESS] = handle_dr,
7799 [EXIT_REASON_CPUID] = handle_cpuid,
7800 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7801 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7802 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7803 [EXIT_REASON_HLT] = handle_halt,
7804 [EXIT_REASON_INVD] = handle_invd,
7805 [EXIT_REASON_INVLPG] = handle_invlpg,
7806 [EXIT_REASON_RDPMC] = handle_rdpmc,
7807 [EXIT_REASON_VMCALL] = handle_vmcall,
7808 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7809 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7810 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7811 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7812 [EXIT_REASON_VMREAD] = handle_vmread,
7813 [EXIT_REASON_VMRESUME] = handle_vmresume,
7814 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7815 [EXIT_REASON_VMOFF] = handle_vmoff,
7816 [EXIT_REASON_VMON] = handle_vmon,
7817 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7818 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7819 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7820 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7821 [EXIT_REASON_WBINVD] = handle_wbinvd,
7822 [EXIT_REASON_XSETBV] = handle_xsetbv,
7823 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7824 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7825 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7826 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7827 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7828 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7829 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7830 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7831 [EXIT_REASON_INVEPT] = handle_invept,
7832 [EXIT_REASON_INVVPID] = handle_invvpid,
7833 [EXIT_REASON_XSAVES] = handle_xsaves,
7834 [EXIT_REASON_XRSTORS] = handle_xrstors,
7835 [EXIT_REASON_PML_FULL] = handle_pml_full,
7836 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7839 static const int kvm_vmx_max_exit_handlers =
7840 ARRAY_SIZE(kvm_vmx_exit_handlers);
7842 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7843 struct vmcs12 *vmcs12)
7845 unsigned long exit_qualification;
7846 gpa_t bitmap, last_bitmap;
7851 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7852 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7854 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7856 port = exit_qualification >> 16;
7857 size = (exit_qualification & 7) + 1;
7859 last_bitmap = (gpa_t)-1;
7864 bitmap = vmcs12->io_bitmap_a;
7865 else if (port < 0x10000)
7866 bitmap = vmcs12->io_bitmap_b;
7869 bitmap += (port & 0x7fff) / 8;
7871 if (last_bitmap != bitmap)
7872 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7874 if (b & (1 << (port & 7)))
7879 last_bitmap = bitmap;
7886 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7887 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7888 * disinterest in the current event (read or write a specific MSR) by using an
7889 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7891 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7892 struct vmcs12 *vmcs12, u32 exit_reason)
7894 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7897 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7901 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7902 * for the four combinations of read/write and low/high MSR numbers.
7903 * First we need to figure out which of the four to use:
7905 bitmap = vmcs12->msr_bitmap;
7906 if (exit_reason == EXIT_REASON_MSR_WRITE)
7908 if (msr_index >= 0xc0000000) {
7909 msr_index -= 0xc0000000;
7913 /* Then read the msr_index'th bit from this bitmap: */
7914 if (msr_index < 1024*8) {
7916 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7918 return 1 & (b >> (msr_index & 7));
7920 return true; /* let L1 handle the wrong parameter */
7924 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7925 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7926 * intercept (via guest_host_mask etc.) the current event.
7928 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7929 struct vmcs12 *vmcs12)
7931 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7932 int cr = exit_qualification & 15;
7936 switch ((exit_qualification >> 4) & 3) {
7937 case 0: /* mov to cr */
7938 reg = (exit_qualification >> 8) & 15;
7939 val = kvm_register_readl(vcpu, reg);
7942 if (vmcs12->cr0_guest_host_mask &
7943 (val ^ vmcs12->cr0_read_shadow))
7947 if ((vmcs12->cr3_target_count >= 1 &&
7948 vmcs12->cr3_target_value0 == val) ||
7949 (vmcs12->cr3_target_count >= 2 &&
7950 vmcs12->cr3_target_value1 == val) ||
7951 (vmcs12->cr3_target_count >= 3 &&
7952 vmcs12->cr3_target_value2 == val) ||
7953 (vmcs12->cr3_target_count >= 4 &&
7954 vmcs12->cr3_target_value3 == val))
7956 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7960 if (vmcs12->cr4_guest_host_mask &
7961 (vmcs12->cr4_read_shadow ^ val))
7965 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7971 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7972 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7975 case 1: /* mov from cr */
7978 if (vmcs12->cpu_based_vm_exec_control &
7979 CPU_BASED_CR3_STORE_EXITING)
7983 if (vmcs12->cpu_based_vm_exec_control &
7984 CPU_BASED_CR8_STORE_EXITING)
7991 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7992 * cr0. Other attempted changes are ignored, with no exit.
7994 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
7995 if (vmcs12->cr0_guest_host_mask & 0xe &
7996 (val ^ vmcs12->cr0_read_shadow))
7998 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7999 !(vmcs12->cr0_read_shadow & 0x1) &&
8008 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8009 * should handle it ourselves in L0 (and then continue L2). Only call this
8010 * when in is_guest_mode (L2).
8012 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8014 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8015 struct vcpu_vmx *vmx = to_vmx(vcpu);
8016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8017 u32 exit_reason = vmx->exit_reason;
8019 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8020 vmcs_readl(EXIT_QUALIFICATION),
8021 vmx->idt_vectoring_info,
8023 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8026 if (vmx->nested.nested_run_pending)
8029 if (unlikely(vmx->fail)) {
8030 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8031 vmcs_read32(VM_INSTRUCTION_ERROR));
8035 switch (exit_reason) {
8036 case EXIT_REASON_EXCEPTION_NMI:
8037 if (is_nmi(intr_info))
8039 else if (is_page_fault(intr_info))
8041 else if (is_no_device(intr_info) &&
8042 !(vmcs12->guest_cr0 & X86_CR0_TS))
8044 else if (is_debug(intr_info) &&
8046 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8048 else if (is_breakpoint(intr_info) &&
8049 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8051 return vmcs12->exception_bitmap &
8052 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8053 case EXIT_REASON_EXTERNAL_INTERRUPT:
8055 case EXIT_REASON_TRIPLE_FAULT:
8057 case EXIT_REASON_PENDING_INTERRUPT:
8058 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8059 case EXIT_REASON_NMI_WINDOW:
8060 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8061 case EXIT_REASON_TASK_SWITCH:
8063 case EXIT_REASON_CPUID:
8065 case EXIT_REASON_HLT:
8066 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8067 case EXIT_REASON_INVD:
8069 case EXIT_REASON_INVLPG:
8070 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8071 case EXIT_REASON_RDPMC:
8072 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8073 case EXIT_REASON_RDRAND:
8074 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8075 case EXIT_REASON_RDSEED:
8076 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8077 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8078 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8079 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8080 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8081 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8082 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8083 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8084 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8086 * VMX instructions trap unconditionally. This allows L1 to
8087 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8090 case EXIT_REASON_CR_ACCESS:
8091 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8092 case EXIT_REASON_DR_ACCESS:
8093 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8094 case EXIT_REASON_IO_INSTRUCTION:
8095 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8096 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8097 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8098 case EXIT_REASON_MSR_READ:
8099 case EXIT_REASON_MSR_WRITE:
8100 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8101 case EXIT_REASON_INVALID_STATE:
8103 case EXIT_REASON_MWAIT_INSTRUCTION:
8104 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8105 case EXIT_REASON_MONITOR_TRAP_FLAG:
8106 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8107 case EXIT_REASON_MONITOR_INSTRUCTION:
8108 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8109 case EXIT_REASON_PAUSE_INSTRUCTION:
8110 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8111 nested_cpu_has2(vmcs12,
8112 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8113 case EXIT_REASON_MCE_DURING_VMENTRY:
8115 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8116 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8117 case EXIT_REASON_APIC_ACCESS:
8118 return nested_cpu_has2(vmcs12,
8119 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8120 case EXIT_REASON_APIC_WRITE:
8121 case EXIT_REASON_EOI_INDUCED:
8122 /* apic_write and eoi_induced should exit unconditionally. */
8124 case EXIT_REASON_EPT_VIOLATION:
8126 * L0 always deals with the EPT violation. If nested EPT is
8127 * used, and the nested mmu code discovers that the address is
8128 * missing in the guest EPT table (EPT12), the EPT violation
8129 * will be injected with nested_ept_inject_page_fault()
8132 case EXIT_REASON_EPT_MISCONFIG:
8134 * L2 never uses directly L1's EPT, but rather L0's own EPT
8135 * table (shadow on EPT) or a merged EPT table that L0 built
8136 * (EPT on EPT). So any problems with the structure of the
8137 * table is L0's fault.
8140 case EXIT_REASON_WBINVD:
8141 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8142 case EXIT_REASON_XSETBV:
8144 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8146 * This should never happen, since it is not possible to
8147 * set XSS to a non-zero value---neither in L1 nor in L2.
8148 * If if it were, XSS would have to be checked against
8149 * the XSS exit bitmap in vmcs12.
8151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8152 case EXIT_REASON_PREEMPTION_TIMER:
8154 case EXIT_REASON_PML_FULL:
8155 /* We emulate PML support to L1. */
8162 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8164 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8165 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8168 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8171 __free_page(vmx->pml_pg);
8176 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8178 struct vcpu_vmx *vmx = to_vmx(vcpu);
8182 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8184 /* Do nothing if PML buffer is empty */
8185 if (pml_idx == (PML_ENTITY_NUM - 1))
8188 /* PML index always points to next available PML buffer entity */
8189 if (pml_idx >= PML_ENTITY_NUM)
8194 pml_buf = page_address(vmx->pml_pg);
8195 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8198 gpa = pml_buf[pml_idx];
8199 WARN_ON(gpa & (PAGE_SIZE - 1));
8200 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8203 /* reset PML index */
8204 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8208 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8209 * Called before reporting dirty_bitmap to userspace.
8211 static void kvm_flush_pml_buffers(struct kvm *kvm)
8214 struct kvm_vcpu *vcpu;
8216 * We only need to kick vcpu out of guest mode here, as PML buffer
8217 * is flushed at beginning of all VMEXITs, and it's obvious that only
8218 * vcpus running in guest are possible to have unflushed GPAs in PML
8221 kvm_for_each_vcpu(i, vcpu, kvm)
8222 kvm_vcpu_kick(vcpu);
8225 static void vmx_dump_sel(char *name, uint32_t sel)
8227 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8228 name, vmcs_read16(sel),
8229 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8230 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8231 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8234 static void vmx_dump_dtsel(char *name, uint32_t limit)
8236 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8237 name, vmcs_read32(limit),
8238 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8241 static void dump_vmcs(void)
8243 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8244 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8245 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8246 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8247 u32 secondary_exec_control = 0;
8248 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8249 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8252 if (cpu_has_secondary_exec_ctrls())
8253 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8255 pr_err("*** Guest State ***\n");
8256 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8257 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8258 vmcs_readl(CR0_GUEST_HOST_MASK));
8259 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8260 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8261 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8262 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8263 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8265 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8266 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8267 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8268 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8270 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8271 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8272 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8273 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8274 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8275 vmcs_readl(GUEST_SYSENTER_ESP),
8276 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8277 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8278 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8279 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8280 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8281 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8282 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8283 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8284 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8285 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8286 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8287 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8288 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8289 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8290 efer, vmcs_read64(GUEST_IA32_PAT));
8291 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8292 vmcs_read64(GUEST_IA32_DEBUGCTL),
8293 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8294 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8295 pr_err("PerfGlobCtl = 0x%016llx\n",
8296 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8297 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8298 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8299 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8300 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8301 vmcs_read32(GUEST_ACTIVITY_STATE));
8302 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8303 pr_err("InterruptStatus = %04x\n",
8304 vmcs_read16(GUEST_INTR_STATUS));
8306 pr_err("*** Host State ***\n");
8307 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8308 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8309 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8310 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8311 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8312 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8313 vmcs_read16(HOST_TR_SELECTOR));
8314 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8315 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8316 vmcs_readl(HOST_TR_BASE));
8317 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8318 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8319 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8320 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8321 vmcs_readl(HOST_CR4));
8322 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8323 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8324 vmcs_read32(HOST_IA32_SYSENTER_CS),
8325 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8326 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8327 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8328 vmcs_read64(HOST_IA32_EFER),
8329 vmcs_read64(HOST_IA32_PAT));
8330 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8331 pr_err("PerfGlobCtl = 0x%016llx\n",
8332 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8334 pr_err("*** Control State ***\n");
8335 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8336 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8337 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8338 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8339 vmcs_read32(EXCEPTION_BITMAP),
8340 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8341 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8342 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8343 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8344 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8345 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8346 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8347 vmcs_read32(VM_EXIT_INTR_INFO),
8348 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8349 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8350 pr_err(" reason=%08x qualification=%016lx\n",
8351 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8352 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8353 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8354 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8355 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8356 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8357 pr_err("TSC Multiplier = 0x%016llx\n",
8358 vmcs_read64(TSC_MULTIPLIER));
8359 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8360 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8361 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8362 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8363 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8364 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8365 n = vmcs_read32(CR3_TARGET_COUNT);
8366 for (i = 0; i + 1 < n; i += 4)
8367 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8368 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8369 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8371 pr_err("CR3 target%u=%016lx\n",
8372 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8373 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8374 pr_err("PLE Gap=%08x Window=%08x\n",
8375 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8376 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8377 pr_err("Virtual processor ID = 0x%04x\n",
8378 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8382 * The guest has exited. See if we can fix it or if we need userspace
8385 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8387 struct vcpu_vmx *vmx = to_vmx(vcpu);
8388 u32 exit_reason = vmx->exit_reason;
8389 u32 vectoring_info = vmx->idt_vectoring_info;
8391 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8392 vcpu->arch.gpa_available = false;
8395 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8396 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8397 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8398 * mode as if vcpus is in root mode, the PML buffer must has been
8402 vmx_flush_pml_buffer(vcpu);
8404 /* If guest state is invalid, start emulating */
8405 if (vmx->emulation_required)
8406 return handle_invalid_guest_state(vcpu);
8408 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8409 nested_vmx_vmexit(vcpu, exit_reason,
8410 vmcs_read32(VM_EXIT_INTR_INFO),
8411 vmcs_readl(EXIT_QUALIFICATION));
8415 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8417 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8418 vcpu->run->fail_entry.hardware_entry_failure_reason
8423 if (unlikely(vmx->fail)) {
8424 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8425 vcpu->run->fail_entry.hardware_entry_failure_reason
8426 = vmcs_read32(VM_INSTRUCTION_ERROR);
8432 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8433 * delivery event since it indicates guest is accessing MMIO.
8434 * The vm-exit can be triggered again after return to guest that
8435 * will cause infinite loop.
8437 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8438 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8439 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8440 exit_reason != EXIT_REASON_PML_FULL &&
8441 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8442 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8443 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8444 vcpu->run->internal.ndata = 3;
8445 vcpu->run->internal.data[0] = vectoring_info;
8446 vcpu->run->internal.data[1] = exit_reason;
8447 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8448 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8449 vcpu->run->internal.ndata++;
8450 vcpu->run->internal.data[3] =
8451 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8456 if (exit_reason < kvm_vmx_max_exit_handlers
8457 && kvm_vmx_exit_handlers[exit_reason])
8458 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8460 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8462 kvm_queue_exception(vcpu, UD_VECTOR);
8467 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8469 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8471 if (is_guest_mode(vcpu) &&
8472 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8475 if (irr == -1 || tpr < irr) {
8476 vmcs_write32(TPR_THRESHOLD, 0);
8480 vmcs_write32(TPR_THRESHOLD, irr);
8483 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8485 u32 sec_exec_control;
8487 /* Postpone execution until vmcs01 is the current VMCS. */
8488 if (is_guest_mode(vcpu)) {
8489 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8493 if (!cpu_has_vmx_virtualize_x2apic_mode())
8496 if (!cpu_need_tpr_shadow(vcpu))
8499 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8502 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8503 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8505 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8506 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8507 vmx_flush_tlb_ept_only(vcpu);
8509 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8511 vmx_set_msr_bitmap(vcpu);
8514 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8516 struct vcpu_vmx *vmx = to_vmx(vcpu);
8519 * Currently we do not handle the nested case where L2 has an
8520 * APIC access page of its own; that page is still pinned.
8521 * Hence, we skip the case where the VCPU is in guest mode _and_
8522 * L1 prepared an APIC access page for L2.
8524 * For the case where L1 and L2 share the same APIC access page
8525 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8526 * in the vmcs12), this function will only update either the vmcs01
8527 * or the vmcs02. If the former, the vmcs02 will be updated by
8528 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8529 * the next L2->L1 exit.
8531 if (!is_guest_mode(vcpu) ||
8532 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8533 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8534 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8535 vmx_flush_tlb_ept_only(vcpu);
8539 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8547 status = vmcs_read16(GUEST_INTR_STATUS);
8549 if (max_isr != old) {
8551 status |= max_isr << 8;
8552 vmcs_write16(GUEST_INTR_STATUS, status);
8556 static void vmx_set_rvi(int vector)
8564 status = vmcs_read16(GUEST_INTR_STATUS);
8565 old = (u8)status & 0xff;
8566 if ((u8)vector != old) {
8568 status |= (u8)vector;
8569 vmcs_write16(GUEST_INTR_STATUS, status);
8573 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8575 if (!is_guest_mode(vcpu)) {
8576 vmx_set_rvi(max_irr);
8584 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8587 if (nested_exit_on_intr(vcpu))
8591 * Else, fall back to pre-APICv interrupt injection since L2
8592 * is run without virtual interrupt delivery.
8594 if (!kvm_event_needs_reinjection(vcpu) &&
8595 vmx_interrupt_allowed(vcpu)) {
8596 kvm_queue_interrupt(vcpu, max_irr, false);
8597 vmx_inject_irq(vcpu);
8601 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8603 struct vcpu_vmx *vmx = to_vmx(vcpu);
8606 WARN_ON(!vcpu->arch.apicv_active);
8607 if (pi_test_on(&vmx->pi_desc)) {
8608 pi_clear_on(&vmx->pi_desc);
8610 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8611 * But on x86 this is just a compiler barrier anyway.
8613 smp_mb__after_atomic();
8614 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8616 max_irr = kvm_lapic_find_highest_irr(vcpu);
8618 vmx_hwapic_irr_update(vcpu, max_irr);
8622 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8624 if (!kvm_vcpu_apicv_active(vcpu))
8627 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8628 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8629 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8630 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8633 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8635 struct vcpu_vmx *vmx = to_vmx(vcpu);
8637 pi_clear_on(&vmx->pi_desc);
8638 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8641 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8643 u32 exit_intr_info = 0;
8644 u16 basic_exit_reason = (u16)vmx->exit_reason;
8646 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8647 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
8650 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8651 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8652 vmx->exit_intr_info = exit_intr_info;
8654 /* if exit due to PF check for async PF */
8655 if (is_page_fault(exit_intr_info))
8656 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8658 /* Handle machine checks before interrupts are enabled */
8659 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8660 is_machine_check(exit_intr_info))
8661 kvm_machine_check();
8663 /* We need to handle NMIs before interrupts are enabled */
8664 if (is_nmi(exit_intr_info)) {
8665 kvm_before_handle_nmi(&vmx->vcpu);
8667 kvm_after_handle_nmi(&vmx->vcpu);
8671 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8673 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8674 register void *__sp asm(_ASM_SP);
8676 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8677 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8678 unsigned int vector;
8679 unsigned long entry;
8681 struct vcpu_vmx *vmx = to_vmx(vcpu);
8682 #ifdef CONFIG_X86_64
8686 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8687 desc = (gate_desc *)vmx->host_idt_base + vector;
8688 entry = gate_offset(*desc);
8690 #ifdef CONFIG_X86_64
8691 "mov %%" _ASM_SP ", %[sp]\n\t"
8692 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8697 __ASM_SIZE(push) " $%c[cs]\n\t"
8698 "call *%[entry]\n\t"
8700 #ifdef CONFIG_X86_64
8706 [ss]"i"(__KERNEL_DS),
8707 [cs]"i"(__KERNEL_CS)
8711 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8713 static bool vmx_has_high_real_mode_segbase(void)
8715 return enable_unrestricted_guest || emulate_invalid_guest_state;
8718 static bool vmx_mpx_supported(void)
8720 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8721 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8724 static bool vmx_xsaves_supported(void)
8726 return vmcs_config.cpu_based_2nd_exec_ctrl &
8727 SECONDARY_EXEC_XSAVES;
8730 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8735 bool idtv_info_valid;
8737 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8739 if (vmx->nmi_known_unmasked)
8742 * Can't use vmx->exit_intr_info since we're not sure what
8743 * the exit reason is.
8745 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8746 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8747 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8749 * SDM 3: 27.7.1.2 (September 2008)
8750 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8751 * a guest IRET fault.
8752 * SDM 3: 23.2.2 (September 2008)
8753 * Bit 12 is undefined in any of the following cases:
8754 * If the VM exit sets the valid bit in the IDT-vectoring
8755 * information field.
8756 * If the VM exit is due to a double fault.
8758 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8759 vector != DF_VECTOR && !idtv_info_valid)
8760 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8761 GUEST_INTR_STATE_NMI);
8763 vmx->nmi_known_unmasked =
8764 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8765 & GUEST_INTR_STATE_NMI);
8768 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8769 u32 idt_vectoring_info,
8770 int instr_len_field,
8771 int error_code_field)
8775 bool idtv_info_valid;
8777 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8779 vcpu->arch.nmi_injected = false;
8780 kvm_clear_exception_queue(vcpu);
8781 kvm_clear_interrupt_queue(vcpu);
8783 if (!idtv_info_valid)
8786 kvm_make_request(KVM_REQ_EVENT, vcpu);
8788 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8789 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8792 case INTR_TYPE_NMI_INTR:
8793 vcpu->arch.nmi_injected = true;
8795 * SDM 3: 27.7.1.2 (September 2008)
8796 * Clear bit "block by NMI" before VM entry if a NMI
8799 vmx_set_nmi_mask(vcpu, false);
8801 case INTR_TYPE_SOFT_EXCEPTION:
8802 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8804 case INTR_TYPE_HARD_EXCEPTION:
8805 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8806 u32 err = vmcs_read32(error_code_field);
8807 kvm_requeue_exception_e(vcpu, vector, err);
8809 kvm_requeue_exception(vcpu, vector);
8811 case INTR_TYPE_SOFT_INTR:
8812 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8814 case INTR_TYPE_EXT_INTR:
8815 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8822 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8824 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8825 VM_EXIT_INSTRUCTION_LEN,
8826 IDT_VECTORING_ERROR_CODE);
8829 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8831 __vmx_complete_interrupts(vcpu,
8832 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8833 VM_ENTRY_INSTRUCTION_LEN,
8834 VM_ENTRY_EXCEPTION_ERROR_CODE);
8836 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8839 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8842 struct perf_guest_switch_msr *msrs;
8844 msrs = perf_guest_get_msrs(&nr_msrs);
8849 for (i = 0; i < nr_msrs; i++)
8850 if (msrs[i].host == msrs[i].guest)
8851 clear_atomic_switch_msr(vmx, msrs[i].msr);
8853 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8857 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8859 struct vcpu_vmx *vmx = to_vmx(vcpu);
8863 if (vmx->hv_deadline_tsc == -1)
8867 if (vmx->hv_deadline_tsc > tscl)
8868 /* sure to be 32 bit only because checked on set_hv_timer */
8869 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8870 cpu_preemption_timer_multi);
8874 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8877 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8879 struct vcpu_vmx *vmx = to_vmx(vcpu);
8880 unsigned long debugctlmsr, cr3, cr4;
8882 /* Don't enter VMX if guest state is invalid, let the exit handler
8883 start emulation until we arrive back to a valid state */
8884 if (vmx->emulation_required)
8887 if (vmx->ple_window_dirty) {
8888 vmx->ple_window_dirty = false;
8889 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8892 if (vmx->nested.sync_shadow_vmcs) {
8893 copy_vmcs12_to_shadow(vmx);
8894 vmx->nested.sync_shadow_vmcs = false;
8897 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8898 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8899 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8900 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8902 cr3 = __get_current_cr3_fast();
8903 if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8904 vmcs_writel(HOST_CR3, cr3);
8905 vmx->host_state.vmcs_host_cr3 = cr3;
8908 cr4 = cr4_read_shadow();
8909 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8910 vmcs_writel(HOST_CR4, cr4);
8911 vmx->host_state.vmcs_host_cr4 = cr4;
8914 /* When single-stepping over STI and MOV SS, we must clear the
8915 * corresponding interruptibility bits in the guest state. Otherwise
8916 * vmentry fails as it then expects bit 14 (BS) in pending debug
8917 * exceptions being set, but that's not correct for the guest debugging
8919 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8920 vmx_set_interrupt_shadow(vcpu, 0);
8922 if (vmx->guest_pkru_valid)
8923 __write_pkru(vmx->guest_pkru);
8925 atomic_switch_perf_msrs(vmx);
8926 debugctlmsr = get_debugctlmsr();
8928 vmx_arm_hv_timer(vcpu);
8930 vmx->__launched = vmx->loaded_vmcs->launched;
8932 /* Store host registers */
8933 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8934 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8935 "push %%" _ASM_CX " \n\t"
8936 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8938 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8939 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8941 /* Reload cr2 if changed */
8942 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8943 "mov %%cr2, %%" _ASM_DX " \n\t"
8944 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8946 "mov %%" _ASM_AX", %%cr2 \n\t"
8948 /* Check if vmlaunch of vmresume is needed */
8949 "cmpl $0, %c[launched](%0) \n\t"
8950 /* Load guest registers. Don't clobber flags. */
8951 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8952 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8953 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8954 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8955 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8956 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8957 #ifdef CONFIG_X86_64
8958 "mov %c[r8](%0), %%r8 \n\t"
8959 "mov %c[r9](%0), %%r9 \n\t"
8960 "mov %c[r10](%0), %%r10 \n\t"
8961 "mov %c[r11](%0), %%r11 \n\t"
8962 "mov %c[r12](%0), %%r12 \n\t"
8963 "mov %c[r13](%0), %%r13 \n\t"
8964 "mov %c[r14](%0), %%r14 \n\t"
8965 "mov %c[r15](%0), %%r15 \n\t"
8967 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8969 /* Enter guest mode */
8971 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8973 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8975 /* Save guest registers, load host registers, keep flags */
8976 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8978 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8979 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8980 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8981 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8982 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8983 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8984 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8985 #ifdef CONFIG_X86_64
8986 "mov %%r8, %c[r8](%0) \n\t"
8987 "mov %%r9, %c[r9](%0) \n\t"
8988 "mov %%r10, %c[r10](%0) \n\t"
8989 "mov %%r11, %c[r11](%0) \n\t"
8990 "mov %%r12, %c[r12](%0) \n\t"
8991 "mov %%r13, %c[r13](%0) \n\t"
8992 "mov %%r14, %c[r14](%0) \n\t"
8993 "mov %%r15, %c[r15](%0) \n\t"
8995 "mov %%cr2, %%" _ASM_AX " \n\t"
8996 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8998 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8999 "setbe %c[fail](%0) \n\t"
9000 ".pushsection .rodata \n\t"
9001 ".global vmx_return \n\t"
9002 "vmx_return: " _ASM_PTR " 2b \n\t"
9004 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9005 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9006 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9007 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9008 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9009 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9010 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9011 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9012 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9013 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9014 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9015 #ifdef CONFIG_X86_64
9016 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9017 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9018 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9019 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9020 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9021 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9022 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9023 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9025 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9026 [wordsize]"i"(sizeof(ulong))
9028 #ifdef CONFIG_X86_64
9029 , "rax", "rbx", "rdi", "rsi"
9030 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9032 , "eax", "ebx", "edi", "esi"
9036 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9038 update_debugctlmsr(debugctlmsr);
9040 #ifndef CONFIG_X86_64
9042 * The sysexit path does not restore ds/es, so we must set them to
9043 * a reasonable value ourselves.
9045 * We can't defer this to vmx_load_host_state() since that function
9046 * may be executed in interrupt context, which saves and restore segments
9047 * around it, nullifying its effect.
9049 loadsegment(ds, __USER_DS);
9050 loadsegment(es, __USER_DS);
9053 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9054 | (1 << VCPU_EXREG_RFLAGS)
9055 | (1 << VCPU_EXREG_PDPTR)
9056 | (1 << VCPU_EXREG_SEGMENTS)
9057 | (1 << VCPU_EXREG_CR3));
9058 vcpu->arch.regs_dirty = 0;
9060 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9062 vmx->loaded_vmcs->launched = 1;
9064 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9067 * eager fpu is enabled if PKEY is supported and CR4 is switched
9068 * back on host, so it is safe to read guest PKRU from current
9071 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9072 vmx->guest_pkru = __read_pkru();
9073 if (vmx->guest_pkru != vmx->host_pkru) {
9074 vmx->guest_pkru_valid = true;
9075 __write_pkru(vmx->host_pkru);
9077 vmx->guest_pkru_valid = false;
9081 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9082 * we did not inject a still-pending event to L1 now because of
9083 * nested_run_pending, we need to re-enable this bit.
9085 if (vmx->nested.nested_run_pending)
9086 kvm_make_request(KVM_REQ_EVENT, vcpu);
9088 vmx->nested.nested_run_pending = 0;
9090 vmx_complete_atomic_exit(vmx);
9091 vmx_recover_nmi_blocking(vmx);
9092 vmx_complete_interrupts(vmx);
9094 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9096 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9098 struct vcpu_vmx *vmx = to_vmx(vcpu);
9101 if (vmx->loaded_vmcs == vmcs)
9105 vmx->loaded_vmcs = vmcs;
9107 vmx_vcpu_load(vcpu, cpu);
9113 * Ensure that the current vmcs of the logical processor is the
9114 * vmcs01 of the vcpu before calling free_nested().
9116 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9118 struct vcpu_vmx *vmx = to_vmx(vcpu);
9121 r = vcpu_load(vcpu);
9123 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9128 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9130 struct vcpu_vmx *vmx = to_vmx(vcpu);
9133 vmx_destroy_pml_buffer(vmx);
9134 free_vpid(vmx->vpid);
9135 leave_guest_mode(vcpu);
9136 vmx_free_vcpu_nested(vcpu);
9137 free_loaded_vmcs(vmx->loaded_vmcs);
9138 kfree(vmx->guest_msrs);
9139 kvm_vcpu_uninit(vcpu);
9140 kmem_cache_free(kvm_vcpu_cache, vmx);
9143 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9146 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9150 return ERR_PTR(-ENOMEM);
9152 vmx->vpid = allocate_vpid();
9154 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9161 * If PML is turned on, failure on enabling PML just results in failure
9162 * of creating the vcpu, therefore we can simplify PML logic (by
9163 * avoiding dealing with cases, such as enabling PML partially on vcpus
9164 * for the guest, etc.
9167 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9172 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9173 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9176 if (!vmx->guest_msrs)
9179 vmx->loaded_vmcs = &vmx->vmcs01;
9180 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9181 vmx->loaded_vmcs->shadow_vmcs = NULL;
9182 if (!vmx->loaded_vmcs->vmcs)
9184 loaded_vmcs_init(vmx->loaded_vmcs);
9187 vmx_vcpu_load(&vmx->vcpu, cpu);
9188 vmx->vcpu.cpu = cpu;
9189 err = vmx_vcpu_setup(vmx);
9190 vmx_vcpu_put(&vmx->vcpu);
9194 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9195 err = alloc_apic_access_page(kvm);
9201 if (!kvm->arch.ept_identity_map_addr)
9202 kvm->arch.ept_identity_map_addr =
9203 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9204 err = init_rmode_identity_map(kvm);
9210 nested_vmx_setup_ctls_msrs(vmx);
9211 vmx->nested.vpid02 = allocate_vpid();
9214 vmx->nested.posted_intr_nv = -1;
9215 vmx->nested.current_vmptr = -1ull;
9216 vmx->nested.current_vmcs12 = NULL;
9218 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9223 free_vpid(vmx->nested.vpid02);
9224 free_loaded_vmcs(vmx->loaded_vmcs);
9226 kfree(vmx->guest_msrs);
9228 vmx_destroy_pml_buffer(vmx);
9230 kvm_vcpu_uninit(&vmx->vcpu);
9232 free_vpid(vmx->vpid);
9233 kmem_cache_free(kvm_vcpu_cache, vmx);
9234 return ERR_PTR(err);
9237 static void __init vmx_check_processor_compat(void *rtn)
9239 struct vmcs_config vmcs_conf;
9242 if (setup_vmcs_config(&vmcs_conf) < 0)
9244 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9245 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9246 smp_processor_id());
9251 static int get_ept_level(void)
9253 return VMX_EPT_DEFAULT_GAW + 1;
9256 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9261 /* For VT-d and EPT combination
9262 * 1. MMIO: always map as UC
9264 * a. VT-d without snooping control feature: can't guarantee the
9265 * result, try to trust guest.
9266 * b. VT-d with snooping control feature: snooping control feature of
9267 * VT-d engine can guarantee the cache correctness. Just set it
9268 * to WB to keep consistent with host. So the same as item 3.
9269 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9270 * consistent with host MTRR
9273 cache = MTRR_TYPE_UNCACHABLE;
9277 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9278 ipat = VMX_EPT_IPAT_BIT;
9279 cache = MTRR_TYPE_WRBACK;
9283 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9284 ipat = VMX_EPT_IPAT_BIT;
9285 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9286 cache = MTRR_TYPE_WRBACK;
9288 cache = MTRR_TYPE_UNCACHABLE;
9292 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9295 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9298 static int vmx_get_lpage_level(void)
9300 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9301 return PT_DIRECTORY_LEVEL;
9303 /* For shadow and EPT supported 1GB page */
9304 return PT_PDPE_LEVEL;
9307 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9310 * These bits in the secondary execution controls field
9311 * are dynamic, the others are mostly based on the hypervisor
9312 * architecture and the guest's CPUID. Do not touch the
9316 SECONDARY_EXEC_SHADOW_VMCS |
9317 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9318 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9320 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9322 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9323 (new_ctl & ~mask) | (cur_ctl & mask));
9327 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9328 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9330 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9332 struct vcpu_vmx *vmx = to_vmx(vcpu);
9333 struct kvm_cpuid_entry2 *entry;
9335 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9336 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9338 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9339 if (entry && (entry->_reg & (_cpuid_mask))) \
9340 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9343 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9344 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9345 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9346 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9347 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9348 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9349 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9350 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9351 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9352 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9353 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9354 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9355 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9356 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9357 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9359 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9360 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9361 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9362 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9363 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9364 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9365 cr4_fixed1_update(bit(11), ecx, bit(2));
9367 #undef cr4_fixed1_update
9370 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9372 struct kvm_cpuid_entry2 *best;
9373 struct vcpu_vmx *vmx = to_vmx(vcpu);
9374 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9376 if (vmx_rdtscp_supported()) {
9377 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9378 if (!rdtscp_enabled)
9379 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9383 vmx->nested.nested_vmx_secondary_ctls_high |=
9384 SECONDARY_EXEC_RDTSCP;
9386 vmx->nested.nested_vmx_secondary_ctls_high &=
9387 ~SECONDARY_EXEC_RDTSCP;
9391 /* Exposing INVPCID only when PCID is exposed */
9392 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9393 if (vmx_invpcid_supported() &&
9394 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9395 !guest_cpuid_has_pcid(vcpu))) {
9396 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9399 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9402 if (cpu_has_secondary_exec_ctrls())
9403 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9405 if (nested_vmx_allowed(vcpu))
9406 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9407 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9409 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9410 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9412 if (nested_vmx_allowed(vcpu))
9413 nested_vmx_cr_fixed1_bits_update(vcpu);
9416 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9418 if (func == 1 && nested)
9419 entry->ecx |= bit(X86_FEATURE_VMX);
9422 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9423 struct x86_exception *fault)
9425 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9426 struct vcpu_vmx *vmx = to_vmx(vcpu);
9428 unsigned long exit_qualification = vcpu->arch.exit_qualification;
9430 if (vmx->nested.pml_full) {
9431 exit_reason = EXIT_REASON_PML_FULL;
9432 vmx->nested.pml_full = false;
9433 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9434 } else if (fault->error_code & PFERR_RSVD_MASK)
9435 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9437 exit_reason = EXIT_REASON_EPT_VIOLATION;
9439 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9440 vmcs12->guest_physical_address = fault->address;
9443 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9445 return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9448 /* Callbacks for nested_ept_init_mmu_context: */
9450 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9452 /* return the page table to be shadowed - in our case, EPT12 */
9453 return get_vmcs12(vcpu)->ept_pointer;
9456 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9460 WARN_ON(mmu_is_nested(vcpu));
9461 wants_ad = nested_ept_ad_enabled(vcpu);
9462 if (wants_ad && !enable_ept_ad_bits)
9465 kvm_mmu_unload(vcpu);
9466 kvm_init_shadow_ept_mmu(vcpu,
9467 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9468 VMX_EPT_EXECUTE_ONLY_BIT,
9470 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9471 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9472 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9474 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9478 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9480 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9483 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9486 bool inequality, bit;
9488 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9490 (error_code & vmcs12->page_fault_error_code_mask) !=
9491 vmcs12->page_fault_error_code_match;
9492 return inequality ^ bit;
9495 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9496 struct x86_exception *fault)
9498 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9500 WARN_ON(!is_guest_mode(vcpu));
9502 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9503 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9504 vmcs_read32(VM_EXIT_INTR_INFO),
9505 vmcs_readl(EXIT_QUALIFICATION));
9507 kvm_inject_page_fault(vcpu, fault);
9510 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9511 struct vmcs12 *vmcs12);
9513 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9514 struct vmcs12 *vmcs12)
9516 struct vcpu_vmx *vmx = to_vmx(vcpu);
9519 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9521 * Translate L1 physical address to host physical
9522 * address for vmcs02. Keep the page pinned, so this
9523 * physical address remains valid. We keep a reference
9524 * to it so we can release it later.
9526 if (vmx->nested.apic_access_page) /* shouldn't happen */
9527 nested_release_page(vmx->nested.apic_access_page);
9528 vmx->nested.apic_access_page =
9529 nested_get_page(vcpu, vmcs12->apic_access_addr);
9531 * If translation failed, no matter: This feature asks
9532 * to exit when accessing the given address, and if it
9533 * can never be accessed, this feature won't do
9536 if (vmx->nested.apic_access_page) {
9537 hpa = page_to_phys(vmx->nested.apic_access_page);
9538 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9540 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9541 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9543 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9544 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9545 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9546 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9547 kvm_vcpu_reload_apic_access_page(vcpu);
9550 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9551 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9552 nested_release_page(vmx->nested.virtual_apic_page);
9553 vmx->nested.virtual_apic_page =
9554 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9557 * If translation failed, VM entry will fail because
9558 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9559 * Failing the vm entry is _not_ what the processor
9560 * does but it's basically the only possibility we
9561 * have. We could still enter the guest if CR8 load
9562 * exits are enabled, CR8 store exits are enabled, and
9563 * virtualize APIC access is disabled; in this case
9564 * the processor would never use the TPR shadow and we
9565 * could simply clear the bit from the execution
9566 * control. But such a configuration is useless, so
9567 * let's keep the code simple.
9569 if (vmx->nested.virtual_apic_page) {
9570 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9571 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9575 if (nested_cpu_has_posted_intr(vmcs12)) {
9576 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9577 kunmap(vmx->nested.pi_desc_page);
9578 nested_release_page(vmx->nested.pi_desc_page);
9580 vmx->nested.pi_desc_page =
9581 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9582 vmx->nested.pi_desc =
9583 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9584 if (!vmx->nested.pi_desc) {
9585 nested_release_page_clean(vmx->nested.pi_desc_page);
9588 vmx->nested.pi_desc =
9589 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9590 (unsigned long)(vmcs12->posted_intr_desc_addr &
9592 vmcs_write64(POSTED_INTR_DESC_ADDR,
9593 page_to_phys(vmx->nested.pi_desc_page) +
9594 (unsigned long)(vmcs12->posted_intr_desc_addr &
9597 if (cpu_has_vmx_msr_bitmap() &&
9598 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9599 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9602 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9603 CPU_BASED_USE_MSR_BITMAPS);
9606 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9608 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9609 struct vcpu_vmx *vmx = to_vmx(vcpu);
9611 if (vcpu->arch.virtual_tsc_khz == 0)
9614 /* Make sure short timeouts reliably trigger an immediate vmexit.
9615 * hrtimer_start does not guarantee this. */
9616 if (preemption_timeout <= 1) {
9617 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9621 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9622 preemption_timeout *= 1000000;
9623 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9624 hrtimer_start(&vmx->nested.preemption_timer,
9625 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9628 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9629 struct vmcs12 *vmcs12)
9631 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9634 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9635 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9641 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9642 struct vmcs12 *vmcs12)
9644 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9647 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
9654 * Merge L0's and L1's MSR bitmap, return false to indicate that
9655 * we do not use the hardware.
9657 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9658 struct vmcs12 *vmcs12)
9662 unsigned long *msr_bitmap_l1;
9663 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9665 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9666 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9669 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9672 msr_bitmap_l1 = (unsigned long *)kmap(page);
9674 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9676 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9677 if (nested_cpu_has_apic_reg_virt(vmcs12))
9678 for (msr = 0x800; msr <= 0x8ff; msr++)
9679 nested_vmx_disable_intercept_for_msr(
9680 msr_bitmap_l1, msr_bitmap_l0,
9683 nested_vmx_disable_intercept_for_msr(
9684 msr_bitmap_l1, msr_bitmap_l0,
9685 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9686 MSR_TYPE_R | MSR_TYPE_W);
9688 if (nested_cpu_has_vid(vmcs12)) {
9689 nested_vmx_disable_intercept_for_msr(
9690 msr_bitmap_l1, msr_bitmap_l0,
9691 APIC_BASE_MSR + (APIC_EOI >> 4),
9693 nested_vmx_disable_intercept_for_msr(
9694 msr_bitmap_l1, msr_bitmap_l0,
9695 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9700 nested_release_page_clean(page);
9705 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9706 struct vmcs12 *vmcs12)
9708 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9709 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9710 !nested_cpu_has_vid(vmcs12) &&
9711 !nested_cpu_has_posted_intr(vmcs12))
9715 * If virtualize x2apic mode is enabled,
9716 * virtualize apic access must be disabled.
9718 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9719 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9723 * If virtual interrupt delivery is enabled,
9724 * we must exit on external interrupts.
9726 if (nested_cpu_has_vid(vmcs12) &&
9727 !nested_exit_on_intr(vcpu))
9731 * bits 15:8 should be zero in posted_intr_nv,
9732 * the descriptor address has been already checked
9733 * in nested_get_vmcs12_pages.
9735 if (nested_cpu_has_posted_intr(vmcs12) &&
9736 (!nested_cpu_has_vid(vmcs12) ||
9737 !nested_exit_intr_ack_set(vcpu) ||
9738 vmcs12->posted_intr_nv & 0xff00))
9741 /* tpr shadow is needed by all apicv features. */
9742 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9748 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9749 unsigned long count_field,
9750 unsigned long addr_field)
9755 if (vmcs12_read_any(vcpu, count_field, &count) ||
9756 vmcs12_read_any(vcpu, addr_field, &addr)) {
9762 maxphyaddr = cpuid_maxphyaddr(vcpu);
9763 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9764 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9765 pr_debug_ratelimited(
9766 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9767 addr_field, maxphyaddr, count, addr);
9773 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9774 struct vmcs12 *vmcs12)
9776 if (vmcs12->vm_exit_msr_load_count == 0 &&
9777 vmcs12->vm_exit_msr_store_count == 0 &&
9778 vmcs12->vm_entry_msr_load_count == 0)
9779 return 0; /* Fast path */
9780 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9781 VM_EXIT_MSR_LOAD_ADDR) ||
9782 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9783 VM_EXIT_MSR_STORE_ADDR) ||
9784 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9785 VM_ENTRY_MSR_LOAD_ADDR))
9790 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9791 struct vmcs12 *vmcs12)
9793 u64 address = vmcs12->pml_address;
9794 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9796 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9797 if (!nested_cpu_has_ept(vmcs12) ||
9798 !IS_ALIGNED(address, 4096) ||
9799 address >> maxphyaddr)
9806 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9807 struct vmx_msr_entry *e)
9809 /* x2APIC MSR accesses are not allowed */
9810 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9812 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9813 e->index == MSR_IA32_UCODE_REV)
9815 if (e->reserved != 0)
9820 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9821 struct vmx_msr_entry *e)
9823 if (e->index == MSR_FS_BASE ||
9824 e->index == MSR_GS_BASE ||
9825 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9826 nested_vmx_msr_check_common(vcpu, e))
9831 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9832 struct vmx_msr_entry *e)
9834 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9835 nested_vmx_msr_check_common(vcpu, e))
9841 * Load guest's/host's msr at nested entry/exit.
9842 * return 0 for success, entry index for failure.
9844 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9847 struct vmx_msr_entry e;
9848 struct msr_data msr;
9850 msr.host_initiated = false;
9851 for (i = 0; i < count; i++) {
9852 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9854 pr_debug_ratelimited(
9855 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9856 __func__, i, gpa + i * sizeof(e));
9859 if (nested_vmx_load_msr_check(vcpu, &e)) {
9860 pr_debug_ratelimited(
9861 "%s check failed (%u, 0x%x, 0x%x)\n",
9862 __func__, i, e.index, e.reserved);
9865 msr.index = e.index;
9867 if (kvm_set_msr(vcpu, &msr)) {
9868 pr_debug_ratelimited(
9869 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9870 __func__, i, e.index, e.value);
9879 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9882 struct vmx_msr_entry e;
9884 for (i = 0; i < count; i++) {
9885 struct msr_data msr_info;
9886 if (kvm_vcpu_read_guest(vcpu,
9887 gpa + i * sizeof(e),
9888 &e, 2 * sizeof(u32))) {
9889 pr_debug_ratelimited(
9890 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9891 __func__, i, gpa + i * sizeof(e));
9894 if (nested_vmx_store_msr_check(vcpu, &e)) {
9895 pr_debug_ratelimited(
9896 "%s check failed (%u, 0x%x, 0x%x)\n",
9897 __func__, i, e.index, e.reserved);
9900 msr_info.host_initiated = false;
9901 msr_info.index = e.index;
9902 if (kvm_get_msr(vcpu, &msr_info)) {
9903 pr_debug_ratelimited(
9904 "%s cannot read MSR (%u, 0x%x)\n",
9905 __func__, i, e.index);
9908 if (kvm_vcpu_write_guest(vcpu,
9909 gpa + i * sizeof(e) +
9910 offsetof(struct vmx_msr_entry, value),
9911 &msr_info.data, sizeof(msr_info.data))) {
9912 pr_debug_ratelimited(
9913 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9914 __func__, i, e.index, msr_info.data);
9921 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9923 unsigned long invalid_mask;
9925 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9926 return (val & invalid_mask) == 0;
9930 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9931 * emulating VM entry into a guest with EPT enabled.
9932 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9933 * is assigned to entry_failure_code on failure.
9935 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9936 u32 *entry_failure_code)
9938 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9939 if (!nested_cr3_valid(vcpu, cr3)) {
9940 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9945 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9946 * must not be dereferenced.
9948 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9950 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9951 *entry_failure_code = ENTRY_FAIL_PDPTE;
9956 vcpu->arch.cr3 = cr3;
9957 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9960 kvm_mmu_reset_context(vcpu);
9965 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9966 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9967 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9968 * guest in a way that will both be appropriate to L1's requests, and our
9969 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9970 * function also has additional necessary side-effects, like setting various
9971 * vcpu->arch fields.
9972 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9973 * is assigned to entry_failure_code on failure.
9975 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9976 bool from_vmentry, u32 *entry_failure_code)
9978 struct vcpu_vmx *vmx = to_vmx(vcpu);
9979 u32 exec_control, vmcs12_exec_ctrl;
9981 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9982 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9983 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9984 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9985 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9986 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9987 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9988 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9989 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9990 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9991 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9992 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9993 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9994 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9995 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9996 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9997 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9998 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9999 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10000 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10001 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10002 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10003 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10004 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10005 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10006 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10007 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10008 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10009 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10010 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10011 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10012 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10013 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10014 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10015 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10016 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10018 if (from_vmentry &&
10019 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10020 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10021 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10023 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10024 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10026 if (from_vmentry) {
10027 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10028 vmcs12->vm_entry_intr_info_field);
10029 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10030 vmcs12->vm_entry_exception_error_code);
10031 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10032 vmcs12->vm_entry_instruction_len);
10033 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10034 vmcs12->guest_interruptibility_info);
10036 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10038 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10039 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10040 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10041 vmcs12->guest_pending_dbg_exceptions);
10042 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10043 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10045 if (nested_cpu_has_xsaves(vmcs12))
10046 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10047 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10049 exec_control = vmcs12->pin_based_vm_exec_control;
10051 /* Preemption timer setting is only taken from vmcs01. */
10052 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10053 exec_control |= vmcs_config.pin_based_exec_ctrl;
10054 if (vmx->hv_deadline_tsc == -1)
10055 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10057 /* Posted interrupts setting is only taken from vmcs12. */
10058 if (nested_cpu_has_posted_intr(vmcs12)) {
10060 * Note that we use L0's vector here and in
10061 * vmx_deliver_nested_posted_interrupt.
10063 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10064 vmx->nested.pi_pending = false;
10065 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10067 exec_control &= ~PIN_BASED_POSTED_INTR;
10070 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10072 vmx->nested.preemption_timer_expired = false;
10073 if (nested_cpu_has_preemption_timer(vmcs12))
10074 vmx_start_preemption_timer(vcpu);
10077 * Whether page-faults are trapped is determined by a combination of
10078 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10079 * If enable_ept, L0 doesn't care about page faults and we should
10080 * set all of these to L1's desires. However, if !enable_ept, L0 does
10081 * care about (at least some) page faults, and because it is not easy
10082 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10083 * to exit on each and every L2 page fault. This is done by setting
10084 * MASK=MATCH=0 and (see below) EB.PF=1.
10085 * Note that below we don't need special code to set EB.PF beyond the
10086 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10087 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10088 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10090 * A problem with this approach (when !enable_ept) is that L1 may be
10091 * injected with more page faults than it asked for. This could have
10092 * caused problems, but in practice existing hypervisors don't care.
10093 * To fix this, we will need to emulate the PFEC checking (on the L1
10094 * page tables), using walk_addr(), when injecting PFs to L1.
10096 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10097 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10098 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10099 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10101 if (cpu_has_secondary_exec_ctrls()) {
10102 exec_control = vmx_secondary_exec_control(vmx);
10104 /* Take the following fields only from vmcs12 */
10105 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10106 SECONDARY_EXEC_RDTSCP |
10107 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10108 SECONDARY_EXEC_APIC_REGISTER_VIRT);
10109 if (nested_cpu_has(vmcs12,
10110 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10111 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10112 ~SECONDARY_EXEC_ENABLE_PML;
10113 exec_control |= vmcs12_exec_ctrl;
10116 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10117 vmcs_write64(EOI_EXIT_BITMAP0,
10118 vmcs12->eoi_exit_bitmap0);
10119 vmcs_write64(EOI_EXIT_BITMAP1,
10120 vmcs12->eoi_exit_bitmap1);
10121 vmcs_write64(EOI_EXIT_BITMAP2,
10122 vmcs12->eoi_exit_bitmap2);
10123 vmcs_write64(EOI_EXIT_BITMAP3,
10124 vmcs12->eoi_exit_bitmap3);
10125 vmcs_write16(GUEST_INTR_STATUS,
10126 vmcs12->guest_intr_status);
10130 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10131 * nested_get_vmcs12_pages will either fix it up or
10132 * remove the VM execution control.
10134 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10135 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10137 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10142 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10143 * Some constant fields are set here by vmx_set_constant_host_state().
10144 * Other fields are different per CPU, and will be set later when
10145 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10147 vmx_set_constant_host_state(vmx);
10150 * Set the MSR load/store lists to match L0's settings.
10152 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10153 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10154 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10155 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10156 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10159 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10160 * entry, but only if the current (host) sp changed from the value
10161 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10162 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10163 * here we just force the write to happen on entry.
10167 exec_control = vmx_exec_control(vmx); /* L0's desires */
10168 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10169 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10170 exec_control &= ~CPU_BASED_TPR_SHADOW;
10171 exec_control |= vmcs12->cpu_based_vm_exec_control;
10174 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10175 * nested_get_vmcs12_pages can't fix it up, the illegal value
10176 * will result in a VM entry failure.
10178 if (exec_control & CPU_BASED_TPR_SHADOW) {
10179 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10180 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10184 * Merging of IO bitmap not currently supported.
10185 * Rather, exit every time.
10187 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10188 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10190 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10192 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10193 * bitwise-or of what L1 wants to trap for L2, and what we want to
10194 * trap. Note that CR0.TS also needs updating - we do this later.
10196 update_exception_bitmap(vcpu);
10197 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10198 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10200 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10201 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10202 * bits are further modified by vmx_set_efer() below.
10204 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10206 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10207 * emulated by vmx_set_efer(), below.
10209 vm_entry_controls_init(vmx,
10210 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10211 ~VM_ENTRY_IA32E_MODE) |
10212 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10214 if (from_vmentry &&
10215 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10216 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10217 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10218 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10219 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10222 set_cr4_guest_host_mask(vmx);
10224 if (from_vmentry &&
10225 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10226 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10228 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10229 vmcs_write64(TSC_OFFSET,
10230 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10232 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10233 if (kvm_has_tsc_control)
10234 decache_tsc_multiplier(vmx);
10238 * There is no direct mapping between vpid02 and vpid12, the
10239 * vpid02 is per-vCPU for L0 and reused while the value of
10240 * vpid12 is changed w/ one invvpid during nested vmentry.
10241 * The vpid12 is allocated by L1 for L2, so it will not
10242 * influence global bitmap(for vpid01 and vpid02 allocation)
10243 * even if spawn a lot of nested vCPUs.
10245 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10246 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10247 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10248 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10249 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10252 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10253 vmx_flush_tlb(vcpu);
10260 * Conceptually we want to copy the PML address and index from
10261 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10262 * since we always flush the log on each vmexit, this happens
10263 * to be equivalent to simply resetting the fields in vmcs02.
10265 ASSERT(vmx->pml_pg);
10266 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10267 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10270 if (nested_cpu_has_ept(vmcs12)) {
10271 if (nested_ept_init_mmu_context(vcpu)) {
10272 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10275 } else if (nested_cpu_has2(vmcs12,
10276 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10277 vmx_flush_tlb_ept_only(vcpu);
10281 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10282 * bits which we consider mandatory enabled.
10283 * The CR0_READ_SHADOW is what L2 should have expected to read given
10284 * the specifications by L1; It's not enough to take
10285 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10286 * have more bits than L1 expected.
10288 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10289 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10291 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10292 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10294 if (from_vmentry &&
10295 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10296 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10297 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10298 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10300 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10301 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10302 vmx_set_efer(vcpu, vcpu->arch.efer);
10304 /* Shadow page tables on either EPT or shadow page tables. */
10305 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10306 entry_failure_code))
10310 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10313 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10316 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10317 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10318 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10319 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10322 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10323 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10327 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10329 struct vcpu_vmx *vmx = to_vmx(vcpu);
10331 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10332 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10333 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10335 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10336 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10338 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10339 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10341 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10342 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10344 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10345 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10347 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10348 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10350 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10351 vmx->nested.nested_vmx_procbased_ctls_low,
10352 vmx->nested.nested_vmx_procbased_ctls_high) ||
10353 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10354 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10355 vmx->nested.nested_vmx_secondary_ctls_low,
10356 vmx->nested.nested_vmx_secondary_ctls_high)) ||
10357 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10358 vmx->nested.nested_vmx_pinbased_ctls_low,
10359 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10360 !vmx_control_verify(vmcs12->vm_exit_controls,
10361 vmx->nested.nested_vmx_exit_ctls_low,
10362 vmx->nested.nested_vmx_exit_ctls_high) ||
10363 !vmx_control_verify(vmcs12->vm_entry_controls,
10364 vmx->nested.nested_vmx_entry_ctls_low,
10365 vmx->nested.nested_vmx_entry_ctls_high))
10366 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10368 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10369 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10371 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10372 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10373 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10374 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10379 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10384 *exit_qual = ENTRY_FAIL_DEFAULT;
10386 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10387 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10390 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10391 vmcs12->vmcs_link_pointer != -1ull) {
10392 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10397 * If the load IA32_EFER VM-entry control is 1, the following checks
10398 * are performed on the field for the IA32_EFER MSR:
10399 * - Bits reserved in the IA32_EFER MSR must be 0.
10400 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10401 * the IA-32e mode guest VM-exit control. It must also be identical
10402 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10405 if (to_vmx(vcpu)->nested.nested_run_pending &&
10406 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10407 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10408 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10409 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10410 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10411 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10416 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10417 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10418 * the values of the LMA and LME bits in the field must each be that of
10419 * the host address-space size VM-exit control.
10421 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10422 ia32e = (vmcs12->vm_exit_controls &
10423 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10424 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10425 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10426 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10433 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10435 struct vcpu_vmx *vmx = to_vmx(vcpu);
10436 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10437 struct loaded_vmcs *vmcs02;
10441 vmcs02 = nested_get_current_vmcs02(vmx);
10445 enter_guest_mode(vcpu);
10447 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10448 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10450 vmx_switch_vmcs(vcpu, vmcs02);
10451 vmx_segment_cache_clear(vmx);
10453 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10454 leave_guest_mode(vcpu);
10455 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10456 nested_vmx_entry_failure(vcpu, vmcs12,
10457 EXIT_REASON_INVALID_STATE, exit_qual);
10461 nested_get_vmcs12_pages(vcpu, vmcs12);
10463 msr_entry_idx = nested_vmx_load_msr(vcpu,
10464 vmcs12->vm_entry_msr_load_addr,
10465 vmcs12->vm_entry_msr_load_count);
10466 if (msr_entry_idx) {
10467 leave_guest_mode(vcpu);
10468 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10469 nested_vmx_entry_failure(vcpu, vmcs12,
10470 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10475 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10476 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10477 * returned as far as L1 is concerned. It will only return (and set
10478 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10484 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10485 * for running an L2 nested guest.
10487 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10489 struct vmcs12 *vmcs12;
10490 struct vcpu_vmx *vmx = to_vmx(vcpu);
10494 if (!nested_vmx_check_permission(vcpu))
10497 if (!nested_vmx_check_vmcs12(vcpu))
10500 vmcs12 = get_vmcs12(vcpu);
10502 if (enable_shadow_vmcs)
10503 copy_shadow_to_vmcs12(vmx);
10506 * The nested entry process starts with enforcing various prerequisites
10507 * on vmcs12 as required by the Intel SDM, and act appropriately when
10508 * they fail: As the SDM explains, some conditions should cause the
10509 * instruction to fail, while others will cause the instruction to seem
10510 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10511 * To speed up the normal (success) code path, we should avoid checking
10512 * for misconfigurations which will anyway be caught by the processor
10513 * when using the merged vmcs02.
10515 if (vmcs12->launch_state == launch) {
10516 nested_vmx_failValid(vcpu,
10517 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10518 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10522 ret = check_vmentry_prereqs(vcpu, vmcs12);
10524 nested_vmx_failValid(vcpu, ret);
10529 * After this point, the trap flag no longer triggers a singlestep trap
10530 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10531 * This is not 100% correct; for performance reasons, we delegate most
10532 * of the checks on host state to the processor. If those fail,
10533 * the singlestep trap is missed.
10535 skip_emulated_instruction(vcpu);
10537 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10539 nested_vmx_entry_failure(vcpu, vmcs12,
10540 EXIT_REASON_INVALID_STATE, exit_qual);
10545 * We're finally done with prerequisite checking, and can start with
10546 * the nested entry.
10549 ret = enter_vmx_non_root_mode(vcpu, true);
10553 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10554 return kvm_vcpu_halt(vcpu);
10556 vmx->nested.nested_run_pending = 1;
10561 return kvm_skip_emulated_instruction(vcpu);
10565 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10566 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10567 * This function returns the new value we should put in vmcs12.guest_cr0.
10568 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10569 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10570 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10571 * didn't trap the bit, because if L1 did, so would L0).
10572 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10573 * been modified by L2, and L1 knows it. So just leave the old value of
10574 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10575 * isn't relevant, because if L0 traps this bit it can set it to anything.
10576 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10577 * changed these bits, and therefore they need to be updated, but L0
10578 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10579 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10581 static inline unsigned long
10582 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10585 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10586 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10587 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10588 vcpu->arch.cr0_guest_owned_bits));
10591 static inline unsigned long
10592 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10595 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10596 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10597 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10598 vcpu->arch.cr4_guest_owned_bits));
10601 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10602 struct vmcs12 *vmcs12)
10607 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10608 nr = vcpu->arch.exception.nr;
10609 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10611 if (kvm_exception_is_soft(nr)) {
10612 vmcs12->vm_exit_instruction_len =
10613 vcpu->arch.event_exit_inst_len;
10614 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10616 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10618 if (vcpu->arch.exception.has_error_code) {
10619 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10620 vmcs12->idt_vectoring_error_code =
10621 vcpu->arch.exception.error_code;
10624 vmcs12->idt_vectoring_info_field = idt_vectoring;
10625 } else if (vcpu->arch.nmi_injected) {
10626 vmcs12->idt_vectoring_info_field =
10627 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10628 } else if (vcpu->arch.interrupt.pending) {
10629 nr = vcpu->arch.interrupt.nr;
10630 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10632 if (vcpu->arch.interrupt.soft) {
10633 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10634 vmcs12->vm_entry_instruction_len =
10635 vcpu->arch.event_exit_inst_len;
10637 idt_vectoring |= INTR_TYPE_EXT_INTR;
10639 vmcs12->idt_vectoring_info_field = idt_vectoring;
10643 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10645 struct vcpu_vmx *vmx = to_vmx(vcpu);
10647 if (vcpu->arch.exception.pending ||
10648 vcpu->arch.nmi_injected ||
10649 vcpu->arch.interrupt.pending)
10652 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10653 vmx->nested.preemption_timer_expired) {
10654 if (vmx->nested.nested_run_pending)
10656 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10660 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10661 if (vmx->nested.nested_run_pending)
10663 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10664 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10665 INTR_INFO_VALID_MASK, 0);
10667 * The NMI-triggered VM exit counts as injection:
10668 * clear this one and block further NMIs.
10670 vcpu->arch.nmi_pending = 0;
10671 vmx_set_nmi_mask(vcpu, true);
10675 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10676 nested_exit_on_intr(vcpu)) {
10677 if (vmx->nested.nested_run_pending)
10679 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10683 vmx_complete_nested_posted_interrupt(vcpu);
10687 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10689 ktime_t remaining =
10690 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10693 if (ktime_to_ns(remaining) <= 0)
10696 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10697 do_div(value, 1000000);
10698 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10702 * Update the guest state fields of vmcs12 to reflect changes that
10703 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10704 * VM-entry controls is also updated, since this is really a guest
10707 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10709 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10710 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10712 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10713 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10714 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10716 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10717 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10718 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10719 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10720 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10721 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10722 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10723 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10724 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10725 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10726 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10727 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10728 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10729 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10730 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10731 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10732 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10733 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10734 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10735 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10736 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10737 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10738 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10739 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10740 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10741 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10742 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10743 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10744 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10745 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10746 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10747 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10748 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10749 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10750 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10751 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10753 vmcs12->guest_interruptibility_info =
10754 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10755 vmcs12->guest_pending_dbg_exceptions =
10756 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10757 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10758 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10760 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10762 if (nested_cpu_has_preemption_timer(vmcs12)) {
10763 if (vmcs12->vm_exit_controls &
10764 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10765 vmcs12->vmx_preemption_timer_value =
10766 vmx_get_preemption_timer_value(vcpu);
10767 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10771 * In some cases (usually, nested EPT), L2 is allowed to change its
10772 * own CR3 without exiting. If it has changed it, we must keep it.
10773 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10774 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10776 * Additionally, restore L2's PDPTR to vmcs12.
10779 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10780 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10781 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10782 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10783 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10786 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10788 if (nested_cpu_has_vid(vmcs12))
10789 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10791 vmcs12->vm_entry_controls =
10792 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10793 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10795 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10796 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10797 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10800 /* TODO: These cannot have changed unless we have MSR bitmaps and
10801 * the relevant bit asks not to trap the change */
10802 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10803 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10804 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10805 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10806 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10807 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10808 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10809 if (kvm_mpx_supported())
10810 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10814 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10815 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10816 * and this function updates it to reflect the changes to the guest state while
10817 * L2 was running (and perhaps made some exits which were handled directly by L0
10818 * without going back to L1), and to reflect the exit reason.
10819 * Note that we do not have to copy here all VMCS fields, just those that
10820 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10821 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10822 * which already writes to vmcs12 directly.
10824 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10825 u32 exit_reason, u32 exit_intr_info,
10826 unsigned long exit_qualification)
10828 /* update guest state fields: */
10829 sync_vmcs12(vcpu, vmcs12);
10831 /* update exit information fields: */
10833 vmcs12->vm_exit_reason = exit_reason;
10834 vmcs12->exit_qualification = exit_qualification;
10836 vmcs12->vm_exit_intr_info = exit_intr_info;
10837 if ((vmcs12->vm_exit_intr_info &
10838 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10839 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10840 vmcs12->vm_exit_intr_error_code =
10841 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10842 vmcs12->idt_vectoring_info_field = 0;
10843 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10844 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10846 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10847 vmcs12->launch_state = 1;
10849 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10850 * instead of reading the real value. */
10851 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10854 * Transfer the event that L0 or L1 may wanted to inject into
10855 * L2 to IDT_VECTORING_INFO_FIELD.
10857 vmcs12_save_pending_event(vcpu, vmcs12);
10861 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10862 * preserved above and would only end up incorrectly in L1.
10864 vcpu->arch.nmi_injected = false;
10865 kvm_clear_exception_queue(vcpu);
10866 kvm_clear_interrupt_queue(vcpu);
10870 * A part of what we need to when the nested L2 guest exits and we want to
10871 * run its L1 parent, is to reset L1's guest state to the host state specified
10873 * This function is to be called not only on normal nested exit, but also on
10874 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10875 * Failures During or After Loading Guest State").
10876 * This function should be called when the active VMCS is L1's (vmcs01).
10878 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10879 struct vmcs12 *vmcs12)
10881 struct kvm_segment seg;
10882 u32 entry_failure_code;
10884 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10885 vcpu->arch.efer = vmcs12->host_ia32_efer;
10886 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10887 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10889 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10890 vmx_set_efer(vcpu, vcpu->arch.efer);
10892 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10893 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10894 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10896 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10897 * actually changed, because vmx_set_cr0 refers to efer set above.
10899 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10900 * (KVM doesn't change it);
10902 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10903 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10905 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10906 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10907 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10909 nested_ept_uninit_mmu_context(vcpu);
10912 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10913 * couldn't have changed.
10915 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10916 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10919 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10923 * Trivially support vpid by letting L2s share their parent
10924 * L1's vpid. TODO: move to a more elaborate solution, giving
10925 * each L2 its own vpid and exposing the vpid feature to L1.
10927 vmx_flush_tlb(vcpu);
10931 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10932 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10933 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10934 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10935 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10937 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10938 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10939 vmcs_write64(GUEST_BNDCFGS, 0);
10941 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10942 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10943 vcpu->arch.pat = vmcs12->host_ia32_pat;
10945 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10946 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10947 vmcs12->host_ia32_perf_global_ctrl);
10949 /* Set L1 segment info according to Intel SDM
10950 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10951 seg = (struct kvm_segment) {
10953 .limit = 0xFFFFFFFF,
10954 .selector = vmcs12->host_cs_selector,
10960 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10964 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10965 seg = (struct kvm_segment) {
10967 .limit = 0xFFFFFFFF,
10974 seg.selector = vmcs12->host_ds_selector;
10975 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10976 seg.selector = vmcs12->host_es_selector;
10977 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10978 seg.selector = vmcs12->host_ss_selector;
10979 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10980 seg.selector = vmcs12->host_fs_selector;
10981 seg.base = vmcs12->host_fs_base;
10982 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10983 seg.selector = vmcs12->host_gs_selector;
10984 seg.base = vmcs12->host_gs_base;
10985 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10986 seg = (struct kvm_segment) {
10987 .base = vmcs12->host_tr_base,
10989 .selector = vmcs12->host_tr_selector,
10993 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10995 kvm_set_dr(vcpu, 7, 0x400);
10996 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10998 if (cpu_has_vmx_msr_bitmap())
10999 vmx_set_msr_bitmap(vcpu);
11001 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11002 vmcs12->vm_exit_msr_load_count))
11003 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11007 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11008 * and modify vmcs12 to make it see what it would expect to see there if
11009 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11011 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11012 u32 exit_intr_info,
11013 unsigned long exit_qualification)
11015 struct vcpu_vmx *vmx = to_vmx(vcpu);
11016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11017 u32 vm_inst_error = 0;
11019 /* trying to cancel vmlaunch/vmresume is a bug */
11020 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11022 leave_guest_mode(vcpu);
11023 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11024 exit_qualification);
11026 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11027 vmcs12->vm_exit_msr_store_count))
11028 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11030 if (unlikely(vmx->fail))
11031 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11033 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11035 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11036 && nested_exit_intr_ack_set(vcpu)) {
11037 int irq = kvm_cpu_get_interrupt(vcpu);
11039 vmcs12->vm_exit_intr_info = irq |
11040 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11043 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11044 vmcs12->exit_qualification,
11045 vmcs12->idt_vectoring_info_field,
11046 vmcs12->vm_exit_intr_info,
11047 vmcs12->vm_exit_intr_error_code,
11050 vm_entry_controls_reset_shadow(vmx);
11051 vm_exit_controls_reset_shadow(vmx);
11052 vmx_segment_cache_clear(vmx);
11054 /* if no vmcs02 cache requested, remove the one we used */
11055 if (VMCS02_POOL_SIZE == 0)
11056 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11058 load_vmcs12_host_state(vcpu, vmcs12);
11060 /* Update any VMCS fields that might have changed while L2 ran */
11061 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11062 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11063 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11064 if (vmx->hv_deadline_tsc == -1)
11065 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11066 PIN_BASED_VMX_PREEMPTION_TIMER);
11068 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11069 PIN_BASED_VMX_PREEMPTION_TIMER);
11070 if (kvm_has_tsc_control)
11071 decache_tsc_multiplier(vmx);
11073 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11074 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11075 vmx_set_virtual_x2apic_mode(vcpu,
11076 vcpu->arch.apic_base & X2APIC_ENABLE);
11077 } else if (!nested_cpu_has_ept(vmcs12) &&
11078 nested_cpu_has2(vmcs12,
11079 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11080 vmx_flush_tlb_ept_only(vcpu);
11083 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11086 /* Unpin physical memory we referred to in vmcs02 */
11087 if (vmx->nested.apic_access_page) {
11088 nested_release_page(vmx->nested.apic_access_page);
11089 vmx->nested.apic_access_page = NULL;
11091 if (vmx->nested.virtual_apic_page) {
11092 nested_release_page(vmx->nested.virtual_apic_page);
11093 vmx->nested.virtual_apic_page = NULL;
11095 if (vmx->nested.pi_desc_page) {
11096 kunmap(vmx->nested.pi_desc_page);
11097 nested_release_page(vmx->nested.pi_desc_page);
11098 vmx->nested.pi_desc_page = NULL;
11099 vmx->nested.pi_desc = NULL;
11103 * We are now running in L2, mmu_notifier will force to reload the
11104 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11106 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11109 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11110 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11111 * success or failure flag accordingly.
11113 if (unlikely(vmx->fail)) {
11115 nested_vmx_failValid(vcpu, vm_inst_error);
11117 nested_vmx_succeed(vcpu);
11118 if (enable_shadow_vmcs)
11119 vmx->nested.sync_shadow_vmcs = true;
11121 /* in case we halted in L2 */
11122 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11126 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11128 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11130 if (is_guest_mode(vcpu)) {
11131 to_vmx(vcpu)->nested.nested_run_pending = 0;
11132 nested_vmx_vmexit(vcpu, -1, 0, 0);
11134 free_nested(to_vmx(vcpu));
11138 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11139 * 23.7 "VM-entry failures during or after loading guest state" (this also
11140 * lists the acceptable exit-reason and exit-qualification parameters).
11141 * It should only be called before L2 actually succeeded to run, and when
11142 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11144 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11145 struct vmcs12 *vmcs12,
11146 u32 reason, unsigned long qualification)
11148 load_vmcs12_host_state(vcpu, vmcs12);
11149 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11150 vmcs12->exit_qualification = qualification;
11151 nested_vmx_succeed(vcpu);
11152 if (enable_shadow_vmcs)
11153 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11156 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11157 struct x86_instruction_info *info,
11158 enum x86_intercept_stage stage)
11160 return X86EMUL_CONTINUE;
11163 #ifdef CONFIG_X86_64
11164 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11165 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11166 u64 divisor, u64 *result)
11168 u64 low = a << shift, high = a >> (64 - shift);
11170 /* To avoid the overflow on divq */
11171 if (high >= divisor)
11174 /* Low hold the result, high hold rem which is discarded */
11175 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11176 "rm" (divisor), "0" (low), "1" (high));
11182 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11184 struct vcpu_vmx *vmx = to_vmx(vcpu);
11185 u64 tscl = rdtsc();
11186 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11187 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11189 /* Convert to host delta tsc if tsc scaling is enabled */
11190 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11191 u64_shl_div_u64(delta_tsc,
11192 kvm_tsc_scaling_ratio_frac_bits,
11193 vcpu->arch.tsc_scaling_ratio,
11198 * If the delta tsc can't fit in the 32 bit after the multi shift,
11199 * we can't use the preemption timer.
11200 * It's possible that it fits on later vmentries, but checking
11201 * on every vmentry is costly so we just use an hrtimer.
11203 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11206 vmx->hv_deadline_tsc = tscl + delta_tsc;
11207 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11208 PIN_BASED_VMX_PREEMPTION_TIMER);
11210 return delta_tsc == 0;
11213 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11215 struct vcpu_vmx *vmx = to_vmx(vcpu);
11216 vmx->hv_deadline_tsc = -1;
11217 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11218 PIN_BASED_VMX_PREEMPTION_TIMER);
11222 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11225 shrink_ple_window(vcpu);
11228 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11229 struct kvm_memory_slot *slot)
11231 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11232 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11235 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11236 struct kvm_memory_slot *slot)
11238 kvm_mmu_slot_set_dirty(kvm, slot);
11241 static void vmx_flush_log_dirty(struct kvm *kvm)
11243 kvm_flush_pml_buffers(kvm);
11246 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11248 struct vmcs12 *vmcs12;
11249 struct vcpu_vmx *vmx = to_vmx(vcpu);
11251 struct page *page = NULL;
11254 if (is_guest_mode(vcpu)) {
11255 WARN_ON_ONCE(vmx->nested.pml_full);
11258 * Check if PML is enabled for the nested guest.
11259 * Whether eptp bit 6 is set is already checked
11260 * as part of A/D emulation.
11262 vmcs12 = get_vmcs12(vcpu);
11263 if (!nested_cpu_has_pml(vmcs12))
11266 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11267 vmx->nested.pml_full = true;
11271 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11273 page = nested_get_page(vcpu, vmcs12->pml_address);
11277 pml_address = kmap(page);
11278 pml_address[vmcs12->guest_pml_index--] = gpa;
11280 nested_release_page_clean(page);
11286 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11287 struct kvm_memory_slot *memslot,
11288 gfn_t offset, unsigned long mask)
11290 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11294 * This routine does the following things for vCPU which is going
11295 * to be blocked if VT-d PI is enabled.
11296 * - Store the vCPU to the wakeup list, so when interrupts happen
11297 * we can find the right vCPU to wake up.
11298 * - Change the Posted-interrupt descriptor as below:
11299 * 'NDST' <-- vcpu->pre_pcpu
11300 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11301 * - If 'ON' is set during this process, which means at least one
11302 * interrupt is posted for this vCPU, we cannot block it, in
11303 * this case, return 1, otherwise, return 0.
11306 static int pi_pre_block(struct kvm_vcpu *vcpu)
11308 unsigned long flags;
11310 struct pi_desc old, new;
11311 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11313 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11314 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11315 !kvm_vcpu_apicv_active(vcpu))
11318 vcpu->pre_pcpu = vcpu->cpu;
11319 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11320 vcpu->pre_pcpu), flags);
11321 list_add_tail(&vcpu->blocked_vcpu_list,
11322 &per_cpu(blocked_vcpu_on_cpu,
11324 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11325 vcpu->pre_pcpu), flags);
11328 old.control = new.control = pi_desc->control;
11331 * We should not block the vCPU if
11332 * an interrupt is posted for it.
11334 if (pi_test_on(pi_desc) == 1) {
11335 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11336 vcpu->pre_pcpu), flags);
11337 list_del(&vcpu->blocked_vcpu_list);
11338 spin_unlock_irqrestore(
11339 &per_cpu(blocked_vcpu_on_cpu_lock,
11340 vcpu->pre_pcpu), flags);
11341 vcpu->pre_pcpu = -1;
11346 WARN((pi_desc->sn == 1),
11347 "Warning: SN field of posted-interrupts "
11348 "is set before blocking\n");
11351 * Since vCPU can be preempted during this process,
11352 * vcpu->cpu could be different with pre_pcpu, we
11353 * need to set pre_pcpu as the destination of wakeup
11354 * notification event, then we can find the right vCPU
11355 * to wakeup in wakeup handler if interrupts happen
11356 * when the vCPU is in blocked state.
11358 dest = cpu_physical_id(vcpu->pre_pcpu);
11360 if (x2apic_enabled())
11363 new.ndst = (dest << 8) & 0xFF00;
11365 /* set 'NV' to 'wakeup vector' */
11366 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11367 } while (cmpxchg(&pi_desc->control, old.control,
11368 new.control) != old.control);
11373 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11375 if (pi_pre_block(vcpu))
11378 if (kvm_lapic_hv_timer_in_use(vcpu))
11379 kvm_lapic_switch_to_sw_timer(vcpu);
11384 static void pi_post_block(struct kvm_vcpu *vcpu)
11386 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11387 struct pi_desc old, new;
11389 unsigned long flags;
11391 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11392 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11393 !kvm_vcpu_apicv_active(vcpu))
11397 old.control = new.control = pi_desc->control;
11399 dest = cpu_physical_id(vcpu->cpu);
11401 if (x2apic_enabled())
11404 new.ndst = (dest << 8) & 0xFF00;
11406 /* Allow posting non-urgent interrupts */
11409 /* set 'NV' to 'notification vector' */
11410 new.nv = POSTED_INTR_VECTOR;
11411 } while (cmpxchg(&pi_desc->control, old.control,
11412 new.control) != old.control);
11414 if(vcpu->pre_pcpu != -1) {
11416 &per_cpu(blocked_vcpu_on_cpu_lock,
11417 vcpu->pre_pcpu), flags);
11418 list_del(&vcpu->blocked_vcpu_list);
11419 spin_unlock_irqrestore(
11420 &per_cpu(blocked_vcpu_on_cpu_lock,
11421 vcpu->pre_pcpu), flags);
11422 vcpu->pre_pcpu = -1;
11426 static void vmx_post_block(struct kvm_vcpu *vcpu)
11428 if (kvm_x86_ops->set_hv_timer)
11429 kvm_lapic_switch_to_hv_timer(vcpu);
11431 pi_post_block(vcpu);
11435 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11438 * @host_irq: host irq of the interrupt
11439 * @guest_irq: gsi of the interrupt
11440 * @set: set or unset PI
11441 * returns 0 on success, < 0 on failure
11443 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11444 uint32_t guest_irq, bool set)
11446 struct kvm_kernel_irq_routing_entry *e;
11447 struct kvm_irq_routing_table *irq_rt;
11448 struct kvm_lapic_irq irq;
11449 struct kvm_vcpu *vcpu;
11450 struct vcpu_data vcpu_info;
11451 int idx, ret = -EINVAL;
11453 if (!kvm_arch_has_assigned_device(kvm) ||
11454 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11455 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11458 idx = srcu_read_lock(&kvm->irq_srcu);
11459 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11460 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11462 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11463 if (e->type != KVM_IRQ_ROUTING_MSI)
11466 * VT-d PI cannot support posting multicast/broadcast
11467 * interrupts to a vCPU, we still use interrupt remapping
11468 * for these kind of interrupts.
11470 * For lowest-priority interrupts, we only support
11471 * those with single CPU as the destination, e.g. user
11472 * configures the interrupts via /proc/irq or uses
11473 * irqbalance to make the interrupts single-CPU.
11475 * We will support full lowest-priority interrupt later.
11478 kvm_set_msi_irq(kvm, e, &irq);
11479 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11481 * Make sure the IRTE is in remapped mode if
11482 * we don't handle it in posted mode.
11484 ret = irq_set_vcpu_affinity(host_irq, NULL);
11487 "failed to back to remapped mode, irq: %u\n",
11495 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11496 vcpu_info.vector = irq.vector;
11498 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11499 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11502 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11504 /* suppress notification event before unposting */
11505 pi_set_sn(vcpu_to_pi_desc(vcpu));
11506 ret = irq_set_vcpu_affinity(host_irq, NULL);
11507 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11511 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11519 srcu_read_unlock(&kvm->irq_srcu, idx);
11523 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11525 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11526 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11527 FEATURE_CONTROL_LMCE;
11529 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11530 ~FEATURE_CONTROL_LMCE;
11533 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11534 .cpu_has_kvm_support = cpu_has_kvm_support,
11535 .disabled_by_bios = vmx_disabled_by_bios,
11536 .hardware_setup = hardware_setup,
11537 .hardware_unsetup = hardware_unsetup,
11538 .check_processor_compatibility = vmx_check_processor_compat,
11539 .hardware_enable = hardware_enable,
11540 .hardware_disable = hardware_disable,
11541 .cpu_has_accelerated_tpr = report_flexpriority,
11542 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11544 .vcpu_create = vmx_create_vcpu,
11545 .vcpu_free = vmx_free_vcpu,
11546 .vcpu_reset = vmx_vcpu_reset,
11548 .prepare_guest_switch = vmx_save_host_state,
11549 .vcpu_load = vmx_vcpu_load,
11550 .vcpu_put = vmx_vcpu_put,
11552 .update_bp_intercept = update_exception_bitmap,
11553 .get_msr = vmx_get_msr,
11554 .set_msr = vmx_set_msr,
11555 .get_segment_base = vmx_get_segment_base,
11556 .get_segment = vmx_get_segment,
11557 .set_segment = vmx_set_segment,
11558 .get_cpl = vmx_get_cpl,
11559 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11560 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11561 .decache_cr3 = vmx_decache_cr3,
11562 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11563 .set_cr0 = vmx_set_cr0,
11564 .set_cr3 = vmx_set_cr3,
11565 .set_cr4 = vmx_set_cr4,
11566 .set_efer = vmx_set_efer,
11567 .get_idt = vmx_get_idt,
11568 .set_idt = vmx_set_idt,
11569 .get_gdt = vmx_get_gdt,
11570 .set_gdt = vmx_set_gdt,
11571 .get_dr6 = vmx_get_dr6,
11572 .set_dr6 = vmx_set_dr6,
11573 .set_dr7 = vmx_set_dr7,
11574 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11575 .cache_reg = vmx_cache_reg,
11576 .get_rflags = vmx_get_rflags,
11577 .set_rflags = vmx_set_rflags,
11579 .get_pkru = vmx_get_pkru,
11581 .tlb_flush = vmx_flush_tlb,
11583 .run = vmx_vcpu_run,
11584 .handle_exit = vmx_handle_exit,
11585 .skip_emulated_instruction = skip_emulated_instruction,
11586 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11587 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11588 .patch_hypercall = vmx_patch_hypercall,
11589 .set_irq = vmx_inject_irq,
11590 .set_nmi = vmx_inject_nmi,
11591 .queue_exception = vmx_queue_exception,
11592 .cancel_injection = vmx_cancel_injection,
11593 .interrupt_allowed = vmx_interrupt_allowed,
11594 .nmi_allowed = vmx_nmi_allowed,
11595 .get_nmi_mask = vmx_get_nmi_mask,
11596 .set_nmi_mask = vmx_set_nmi_mask,
11597 .enable_nmi_window = enable_nmi_window,
11598 .enable_irq_window = enable_irq_window,
11599 .update_cr8_intercept = update_cr8_intercept,
11600 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11601 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11602 .get_enable_apicv = vmx_get_enable_apicv,
11603 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11604 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11605 .apicv_post_state_restore = vmx_apicv_post_state_restore,
11606 .hwapic_irr_update = vmx_hwapic_irr_update,
11607 .hwapic_isr_update = vmx_hwapic_isr_update,
11608 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11609 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11611 .set_tss_addr = vmx_set_tss_addr,
11612 .get_tdp_level = get_ept_level,
11613 .get_mt_mask = vmx_get_mt_mask,
11615 .get_exit_info = vmx_get_exit_info,
11617 .get_lpage_level = vmx_get_lpage_level,
11619 .cpuid_update = vmx_cpuid_update,
11621 .rdtscp_supported = vmx_rdtscp_supported,
11622 .invpcid_supported = vmx_invpcid_supported,
11624 .set_supported_cpuid = vmx_set_supported_cpuid,
11626 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11628 .write_tsc_offset = vmx_write_tsc_offset,
11630 .set_tdp_cr3 = vmx_set_cr3,
11632 .check_intercept = vmx_check_intercept,
11633 .handle_external_intr = vmx_handle_external_intr,
11634 .mpx_supported = vmx_mpx_supported,
11635 .xsaves_supported = vmx_xsaves_supported,
11637 .check_nested_events = vmx_check_nested_events,
11639 .sched_in = vmx_sched_in,
11641 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11642 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11643 .flush_log_dirty = vmx_flush_log_dirty,
11644 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11645 .write_log_dirty = vmx_write_pml_buffer,
11647 .pre_block = vmx_pre_block,
11648 .post_block = vmx_post_block,
11650 .pmu_ops = &intel_pmu_ops,
11652 .update_pi_irte = vmx_update_pi_irte,
11654 #ifdef CONFIG_X86_64
11655 .set_hv_timer = vmx_set_hv_timer,
11656 .cancel_hv_timer = vmx_cancel_hv_timer,
11659 .setup_mce = vmx_setup_mce,
11662 static int __init vmx_init(void)
11664 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11665 __alignof__(struct vcpu_vmx), THIS_MODULE);
11669 #ifdef CONFIG_KEXEC_CORE
11670 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11671 crash_vmclear_local_loaded_vmcss);
11677 static void __exit vmx_exit(void)
11679 #ifdef CONFIG_KEXEC_CORE
11680 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11687 module_init(vmx_init)
11688 module_exit(vmx_exit)