arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly flexpriority_enabled = 1;
  74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_ept = 1;
  77 module_param_named(ept, enable_ept, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_unrestricted_guest = 1;
  80 module_param_named(unrestricted_guest,
  81                         enable_unrestricted_guest, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept_ad_bits = 1;
  84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  85
  86 static bool __read_mostly emulate_invalid_guest_state = true;
  87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 113 static int __read_mostly cpu_preemption_timer_multi;
 114 static bool __read_mostly enable_preemption_timer = 1;
 115 #ifdef CONFIG_X86_64
 116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 117 #endif
 118
 119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 121 #define KVM_VM_CR0_ALWAYS_ON                                            \
 122         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 123 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 124         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 125          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 126
 127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 129
 130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 131
 132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 133
 134 /*
 135  * Hyper-V requires all of these, so mark them as supported even though
 136  * they are just treated the same as all-context.
 137  */
 138 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 139         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 140         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 141         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 143
 144 /*
 145  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 146  * ple_gap:    upper bound on the amount of time between two successive
 147  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 148  *             According to test, this time is usually smaller than 128 cycles.
 149  * ple_window: upper bound on the amount of time a guest is allowed to execute
 150  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 151  *             less than 2^12 cycles
 152  * Time is measured based on a counter that runs at the same rate as the TSC,
 153  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 154  */
 155 #define KVM_VMX_DEFAULT_PLE_GAP           128
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 160                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 161
 162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 163 module_param(ple_gap, int, S_IRUGO);
 164
 165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 166 module_param(ple_window, int, S_IRUGO);
 167
 168 /* Default doubles per-vcpu window every exit. */
 169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 170 module_param(ple_window_grow, int, S_IRUGO);
 171
 172 /* Default resets per-vcpu window every exit to ple_window. */
 173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 174 module_param(ple_window_shrink, int, S_IRUGO);
 175
 176 /* Default is to compute the maximum so we can never overflow. */
 177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 178 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, int, S_IRUGO);
 180
 181 extern const ulong vmx_return;
 182
 183 #define NR_AUTOLOAD_MSRS 8
 184 #define VMCS02_POOL_SIZE 1
 185
 186 struct vmcs {
 187         u32 revision_id;
 188         u32 abort;
 189         char data[0];
 190 };
 191
 192 /*
 193  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 194  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 195  * loaded on this CPU (so we can clear them if the CPU goes down).
 196  */
 197 struct loaded_vmcs {
 198         struct vmcs *vmcs;
 199         struct vmcs *shadow_vmcs;
 200         int cpu;
 201         bool launched;
 202         bool nmi_known_unmasked;
 203         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 204         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 205         struct list_head loaded_vmcss_on_cpu_link;
 206 };
 207
 208 struct shared_msr_entry {
 209         unsigned index;
 210         u64 data;
 211         u64 mask;
 212 };
 213
 214 /*
 215  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 216  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 217  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 218  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 219  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 220  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 221  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 222  * underlying hardware which will be used to run L2.
 223  * This structure is packed to ensure that its layout is identical across
 224  * machines (necessary for live migration).
 225  * If there are changes in this struct, VMCS12_REVISION must be changed.
 226  */
 227 typedef u64 natural_width;
 228 struct __packed vmcs12 {
 229         /* According to the Intel spec, a VMCS region must start with the
 230          * following two fields. Then follow implementation-specific data.
 231          */
 232         u32 revision_id;
 233         u32 abort;
 234
 235         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 236         u32 padding[7]; /* room for future expansion */
 237
 238         u64 io_bitmap_a;
 239         u64 io_bitmap_b;
 240         u64 msr_bitmap;
 241         u64 vm_exit_msr_store_addr;
 242         u64 vm_exit_msr_load_addr;
 243         u64 vm_entry_msr_load_addr;
 244         u64 tsc_offset;
 245         u64 virtual_apic_page_addr;
 246         u64 apic_access_addr;
 247         u64 posted_intr_desc_addr;
 248         u64 vm_function_control;
 249         u64 ept_pointer;
 250         u64 eoi_exit_bitmap0;
 251         u64 eoi_exit_bitmap1;
 252         u64 eoi_exit_bitmap2;
 253         u64 eoi_exit_bitmap3;
 254         u64 eptp_list_address;
 255         u64 xss_exit_bitmap;
 256         u64 guest_physical_address;
 257         u64 vmcs_link_pointer;
 258         u64 pml_address;
 259         u64 guest_ia32_debugctl;
 260         u64 guest_ia32_pat;
 261         u64 guest_ia32_efer;
 262         u64 guest_ia32_perf_global_ctrl;
 263         u64 guest_pdptr0;
 264         u64 guest_pdptr1;
 265         u64 guest_pdptr2;
 266         u64 guest_pdptr3;
 267         u64 guest_bndcfgs;
 268         u64 host_ia32_pat;
 269         u64 host_ia32_efer;
 270         u64 host_ia32_perf_global_ctrl;
 271         u64 padding64[8]; /* room for future expansion */
 272         /*
 273          * To allow migration of L1 (complete with its L2 guests) between
 274          * machines of different natural widths (32 or 64 bit), we cannot have
 275          * unsigned long fields with no explict size. We use u64 (aliased
 276          * natural_width) instead. Luckily, x86 is little-endian.
 277          */
 278         natural_width cr0_guest_host_mask;
 279         natural_width cr4_guest_host_mask;
 280         natural_width cr0_read_shadow;
 281         natural_width cr4_read_shadow;
 282         natural_width cr3_target_value0;
 283         natural_width cr3_target_value1;
 284         natural_width cr3_target_value2;
 285         natural_width cr3_target_value3;
 286         natural_width exit_qualification;
 287         natural_width guest_linear_address;
 288         natural_width guest_cr0;
 289         natural_width guest_cr3;
 290         natural_width guest_cr4;
 291         natural_width guest_es_base;
 292         natural_width guest_cs_base;
 293         natural_width guest_ss_base;
 294         natural_width guest_ds_base;
 295         natural_width guest_fs_base;
 296         natural_width guest_gs_base;
 297         natural_width guest_ldtr_base;
 298         natural_width guest_tr_base;
 299         natural_width guest_gdtr_base;
 300         natural_width guest_idtr_base;
 301         natural_width guest_dr7;
 302         natural_width guest_rsp;
 303         natural_width guest_rip;
 304         natural_width guest_rflags;
 305         natural_width guest_pending_dbg_exceptions;
 306         natural_width guest_sysenter_esp;
 307         natural_width guest_sysenter_eip;
 308         natural_width host_cr0;
 309         natural_width host_cr3;
 310         natural_width host_cr4;
 311         natural_width host_fs_base;
 312         natural_width host_gs_base;
 313         natural_width host_tr_base;
 314         natural_width host_gdtr_base;
 315         natural_width host_idtr_base;
 316         natural_width host_ia32_sysenter_esp;
 317         natural_width host_ia32_sysenter_eip;
 318         natural_width host_rsp;
 319         natural_width host_rip;
 320         natural_width paddingl[8]; /* room for future expansion */
 321         u32 pin_based_vm_exec_control;
 322         u32 cpu_based_vm_exec_control;
 323         u32 exception_bitmap;
 324         u32 page_fault_error_code_mask;
 325         u32 page_fault_error_code_match;
 326         u32 cr3_target_count;
 327         u32 vm_exit_controls;
 328         u32 vm_exit_msr_store_count;
 329         u32 vm_exit_msr_load_count;
 330         u32 vm_entry_controls;
 331         u32 vm_entry_msr_load_count;
 332         u32 vm_entry_intr_info_field;
 333         u32 vm_entry_exception_error_code;
 334         u32 vm_entry_instruction_len;
 335         u32 tpr_threshold;
 336         u32 secondary_vm_exec_control;
 337         u32 vm_instruction_error;
 338         u32 vm_exit_reason;
 339         u32 vm_exit_intr_info;
 340         u32 vm_exit_intr_error_code;
 341         u32 idt_vectoring_info_field;
 342         u32 idt_vectoring_error_code;
 343         u32 vm_exit_instruction_len;
 344         u32 vmx_instruction_info;
 345         u32 guest_es_limit;
 346         u32 guest_cs_limit;
 347         u32 guest_ss_limit;
 348         u32 guest_ds_limit;
 349         u32 guest_fs_limit;
 350         u32 guest_gs_limit;
 351         u32 guest_ldtr_limit;
 352         u32 guest_tr_limit;
 353         u32 guest_gdtr_limit;
 354         u32 guest_idtr_limit;
 355         u32 guest_es_ar_bytes;
 356         u32 guest_cs_ar_bytes;
 357         u32 guest_ss_ar_bytes;
 358         u32 guest_ds_ar_bytes;
 359         u32 guest_fs_ar_bytes;
 360         u32 guest_gs_ar_bytes;
 361         u32 guest_ldtr_ar_bytes;
 362         u32 guest_tr_ar_bytes;
 363         u32 guest_interruptibility_info;
 364         u32 guest_activity_state;
 365         u32 guest_sysenter_cs;
 366         u32 host_ia32_sysenter_cs;
 367         u32 vmx_preemption_timer_value;
 368         u32 padding32[7]; /* room for future expansion */
 369         u16 virtual_processor_id;
 370         u16 posted_intr_nv;
 371         u16 guest_es_selector;
 372         u16 guest_cs_selector;
 373         u16 guest_ss_selector;
 374         u16 guest_ds_selector;
 375         u16 guest_fs_selector;
 376         u16 guest_gs_selector;
 377         u16 guest_ldtr_selector;
 378         u16 guest_tr_selector;
 379         u16 guest_intr_status;
 380         u16 guest_pml_index;
 381         u16 host_es_selector;
 382         u16 host_cs_selector;
 383         u16 host_ss_selector;
 384         u16 host_ds_selector;
 385         u16 host_fs_selector;
 386         u16 host_gs_selector;
 387         u16 host_tr_selector;
 388 };
 389
 390 /*
 391  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 392  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 393  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 394  */
 395 #define VMCS12_REVISION 0x11e57ed0
 396
 397 /*
 398  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 399  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 400  * current implementation, 4K are reserved to avoid future complications.
 401  */
 402 #define VMCS12_SIZE 0x1000
 403
 404 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 405 struct vmcs02_list {
 406         struct list_head list;
 407         gpa_t vmptr;
 408         struct loaded_vmcs vmcs02;
 409 };
 410
 411 /*
 412  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 413  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 414  */
 415 struct nested_vmx {
 416         /* Has the level1 guest done vmxon? */
 417         bool vmxon;
 418         gpa_t vmxon_ptr;
 419         bool pml_full;
 420
 421         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 422         gpa_t current_vmptr;
 423         /*
 424          * Cache of the guest's VMCS, existing outside of guest memory.
 425          * Loaded from guest memory during VMPTRLD. Flushed to guest
 426          * memory during VMCLEAR and VMPTRLD.
 427          */
 428         struct vmcs12 *cached_vmcs12;
 429         /*
 430          * Indicates if the shadow vmcs must be updated with the
 431          * data hold by vmcs12
 432          */
 433         bool sync_shadow_vmcs;
 434
 435         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 436         struct list_head vmcs02_pool;
 437         int vmcs02_num;
 438         bool change_vmcs01_virtual_x2apic_mode;
 439         /* L2 must run next, and mustn't decide to exit to L1. */
 440         bool nested_run_pending;
 441         /*
 442          * Guest pages referred to in vmcs02 with host-physical pointers, so
 443          * we must keep them pinned while L2 runs.
 444          */
 445         struct page *apic_access_page;
 446         struct page *virtual_apic_page;
 447         struct page *pi_desc_page;
 448         struct pi_desc *pi_desc;
 449         bool pi_pending;
 450         u16 posted_intr_nv;
 451
 452         unsigned long *msr_bitmap;
 453
 454         struct hrtimer preemption_timer;
 455         bool preemption_timer_expired;
 456
 457         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 458         u64 vmcs01_debugctl;
 459
 460         u16 vpid02;
 461         u16 last_vpid;
 462
 463         /*
 464          * We only store the "true" versions of the VMX capability MSRs. We
 465          * generate the "non-true" versions by setting the must-be-1 bits
 466          * according to the SDM.
 467          */
 468         u32 nested_vmx_procbased_ctls_low;
 469         u32 nested_vmx_procbased_ctls_high;
 470         u32 nested_vmx_secondary_ctls_low;
 471         u32 nested_vmx_secondary_ctls_high;
 472         u32 nested_vmx_pinbased_ctls_low;
 473         u32 nested_vmx_pinbased_ctls_high;
 474         u32 nested_vmx_exit_ctls_low;
 475         u32 nested_vmx_exit_ctls_high;
 476         u32 nested_vmx_entry_ctls_low;
 477         u32 nested_vmx_entry_ctls_high;
 478         u32 nested_vmx_misc_low;
 479         u32 nested_vmx_misc_high;
 480         u32 nested_vmx_ept_caps;
 481         u32 nested_vmx_vpid_caps;
 482         u64 nested_vmx_basic;
 483         u64 nested_vmx_cr0_fixed0;
 484         u64 nested_vmx_cr0_fixed1;
 485         u64 nested_vmx_cr4_fixed0;
 486         u64 nested_vmx_cr4_fixed1;
 487         u64 nested_vmx_vmcs_enum;
 488         u64 nested_vmx_vmfunc_controls;
 489 };
 490
 491 #define POSTED_INTR_ON  0
 492 #define POSTED_INTR_SN  1
 493
 494 /* Posted-Interrupt Descriptor */
 495 struct pi_desc {
 496         u32 pir[8];     /* Posted interrupt requested */
 497         union {
 498                 struct {
 499                                 /* bit 256 - Outstanding Notification */
 500                         u16     on      : 1,
 501                                 /* bit 257 - Suppress Notification */
 502                                 sn      : 1,
 503                                 /* bit 271:258 - Reserved */
 504                                 rsvd_1  : 14;
 505                                 /* bit 279:272 - Notification Vector */
 506                         u8      nv;
 507                                 /* bit 287:280 - Reserved */
 508                         u8      rsvd_2;
 509                                 /* bit 319:288 - Notification Destination */
 510                         u32     ndst;
 511                 };
 512                 u64 control;
 513         };
 514         u32 rsvd[6];
 515 } __aligned(64);
 516
 517 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 518 {
 519         return test_and_set_bit(POSTED_INTR_ON,
 520                         (unsigned long *)&pi_desc->control);
 521 }
 522
 523 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 524 {
 525         return test_and_clear_bit(POSTED_INTR_ON,
 526                         (unsigned long *)&pi_desc->control);
 527 }
 528
 529 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 530 {
 531         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 532 }
 533
 534 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 535 {
 536         return clear_bit(POSTED_INTR_SN,
 537                         (unsigned long *)&pi_desc->control);
 538 }
 539
 540 static inline void pi_set_sn(struct pi_desc *pi_desc)
 541 {
 542         return set_bit(POSTED_INTR_SN,
 543                         (unsigned long *)&pi_desc->control);
 544 }
 545
 546 static inline void pi_clear_on(struct pi_desc *pi_desc)
 547 {
 548         clear_bit(POSTED_INTR_ON,
 549                   (unsigned long *)&pi_desc->control);
 550 }
 551
 552 static inline int pi_test_on(struct pi_desc *pi_desc)
 553 {
 554         return test_bit(POSTED_INTR_ON,
 555                         (unsigned long *)&pi_desc->control);
 556 }
 557
 558 static inline int pi_test_sn(struct pi_desc *pi_desc)
 559 {
 560         return test_bit(POSTED_INTR_SN,
 561                         (unsigned long *)&pi_desc->control);
 562 }
 563
 564 struct vcpu_vmx {
 565         struct kvm_vcpu       vcpu;
 566         unsigned long         host_rsp;
 567         u8                    fail;
 568         u32                   exit_intr_info;
 569         u32                   idt_vectoring_info;
 570         ulong                 rflags;
 571         struct shared_msr_entry *guest_msrs;
 572         int                   nmsrs;
 573         int                   save_nmsrs;
 574         unsigned long         host_idt_base;
 575 #ifdef CONFIG_X86_64
 576         u64                   msr_host_kernel_gs_base;
 577         u64                   msr_guest_kernel_gs_base;
 578 #endif
 579         u32 vm_entry_controls_shadow;
 580         u32 vm_exit_controls_shadow;
 581         u32 secondary_exec_control;
 582
 583         /*
 584          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 585          * non-nested (L1) guest, it always points to vmcs01. For a nested
 586          * guest (L2), it points to a different VMCS.
 587          */
 588         struct loaded_vmcs    vmcs01;
 589         struct loaded_vmcs   *loaded_vmcs;
 590         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 591         struct msr_autoload {
 592                 unsigned nr;
 593                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 594                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 595         } msr_autoload;
 596         struct {
 597                 int           loaded;
 598                 u16           fs_sel, gs_sel, ldt_sel;
 599 #ifdef CONFIG_X86_64
 600                 u16           ds_sel, es_sel;
 601 #endif
 602                 int           gs_ldt_reload_needed;
 603                 int           fs_reload_needed;
 604                 u64           msr_host_bndcfgs;
 605         } host_state;
 606         struct {
 607                 int vm86_active;
 608                 ulong save_rflags;
 609                 struct kvm_segment segs[8];
 610         } rmode;
 611         struct {
 612                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 613                 struct kvm_save_segment {
 614                         u16 selector;
 615                         unsigned long base;
 616                         u32 limit;
 617                         u32 ar;
 618                 } seg[8];
 619         } segment_cache;
 620         int vpid;
 621         bool emulation_required;
 622
 623         u32 exit_reason;
 624
 625         /* Posted interrupt descriptor */
 626         struct pi_desc pi_desc;
 627
 628         /* Support for a guest hypervisor (nested VMX) */
 629         struct nested_vmx nested;
 630
 631         /* Dynamic PLE window. */
 632         int ple_window;
 633         bool ple_window_dirty;
 634
 635         /* Support for PML */
 636 #define PML_ENTITY_NUM          512
 637         struct page *pml_pg;
 638
 639         /* apic deadline value in host tsc */
 640         u64 hv_deadline_tsc;
 641
 642         u64 current_tsc_ratio;
 643
 644         u32 host_pkru;
 645
 646         /*
 647          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 648          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 649          * in msr_ia32_feature_control_valid_bits.
 650          */
 651         u64 msr_ia32_feature_control;
 652         u64 msr_ia32_feature_control_valid_bits;
 653 };
 654
 655 enum segment_cache_field {
 656         SEG_FIELD_SEL = 0,
 657         SEG_FIELD_BASE = 1,
 658         SEG_FIELD_LIMIT = 2,
 659         SEG_FIELD_AR = 3,
 660
 661         SEG_FIELD_NR = 4
 662 };
 663
 664 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 665 {
 666         return container_of(vcpu, struct vcpu_vmx, vcpu);
 667 }
 668
 669 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 670 {
 671         return &(to_vmx(vcpu)->pi_desc);
 672 }
 673
 674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 675 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 676 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 677                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 678
 679
 680 static unsigned long shadow_read_only_fields[] = {
 681         /*
 682          * We do NOT shadow fields that are modified when L0
 683          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 684          * VMXON...) executed by L1.
 685          * For example, VM_INSTRUCTION_ERROR is read
 686          * by L1 if a vmx instruction fails (part of the error path).
 687          * Note the code assumes this logic. If for some reason
 688          * we start shadowing these fields then we need to
 689          * force a shadow sync when L0 emulates vmx instructions
 690          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 691          * by nested_vmx_failValid)
 692          */
 693         VM_EXIT_REASON,
 694         VM_EXIT_INTR_INFO,
 695         VM_EXIT_INSTRUCTION_LEN,
 696         IDT_VECTORING_INFO_FIELD,
 697         IDT_VECTORING_ERROR_CODE,
 698         VM_EXIT_INTR_ERROR_CODE,
 699         EXIT_QUALIFICATION,
 700         GUEST_LINEAR_ADDRESS,
 701         GUEST_PHYSICAL_ADDRESS
 702 };
 703 static int max_shadow_read_only_fields =
 704         ARRAY_SIZE(shadow_read_only_fields);
 705
 706 static unsigned long shadow_read_write_fields[] = {
 707         TPR_THRESHOLD,
 708         GUEST_RIP,
 709         GUEST_RSP,
 710         GUEST_CR0,
 711         GUEST_CR3,
 712         GUEST_CR4,
 713         GUEST_INTERRUPTIBILITY_INFO,
 714         GUEST_RFLAGS,
 715         GUEST_CS_SELECTOR,
 716         GUEST_CS_AR_BYTES,
 717         GUEST_CS_LIMIT,
 718         GUEST_CS_BASE,
 719         GUEST_ES_BASE,
 720         GUEST_BNDCFGS,
 721         CR0_GUEST_HOST_MASK,
 722         CR0_READ_SHADOW,
 723         CR4_READ_SHADOW,
 724         TSC_OFFSET,
 725         EXCEPTION_BITMAP,
 726         CPU_BASED_VM_EXEC_CONTROL,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         VM_ENTRY_INTR_INFO_FIELD,
 729         VM_ENTRY_INSTRUCTION_LEN,
 730         VM_ENTRY_EXCEPTION_ERROR_CODE,
 731         HOST_FS_BASE,
 732         HOST_GS_BASE,
 733         HOST_FS_SELECTOR,
 734         HOST_GS_SELECTOR
 735 };
 736 static int max_shadow_read_write_fields =
 737         ARRAY_SIZE(shadow_read_write_fields);
 738
 739 static const unsigned short vmcs_field_to_offset_table[] = {
 740         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 741         FIELD(POSTED_INTR_NV, posted_intr_nv),
 742         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 743         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 744         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 745         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 746         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 747         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 748         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 749         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 750         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 751         FIELD(GUEST_PML_INDEX, guest_pml_index),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 770         FIELD64(EPT_POINTER, ept_pointer),
 771         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 772         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 773         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 774         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 775         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 776         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 777         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 778         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 779         FIELD64(PML_ADDRESS, pml_address),
 780         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 781         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 782         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 783         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 784         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 785         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 786         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 787         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 788         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 789         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 790         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 791         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 792         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 793         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 794         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 795         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 796         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 797         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 798         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 799         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 800         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 801         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 802         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 803         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 804         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 805         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 806         FIELD(TPR_THRESHOLD, tpr_threshold),
 807         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 808         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 809         FIELD(VM_EXIT_REASON, vm_exit_reason),
 810         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 811         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 812         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 813         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 814         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 815         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 816         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 817         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 818         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 819         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 820         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 821         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 822         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 823         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 824         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 825         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 826         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 827         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 828         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 829         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 830         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 831         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 832         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 833         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 834         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 835         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 836         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 837         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 838         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 839         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 840         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 841         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 842         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 843         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 844         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 845         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 846         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 847         FIELD(EXIT_QUALIFICATION, exit_qualification),
 848         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 849         FIELD(GUEST_CR0, guest_cr0),
 850         FIELD(GUEST_CR3, guest_cr3),
 851         FIELD(GUEST_CR4, guest_cr4),
 852         FIELD(GUEST_ES_BASE, guest_es_base),
 853         FIELD(GUEST_CS_BASE, guest_cs_base),
 854         FIELD(GUEST_SS_BASE, guest_ss_base),
 855         FIELD(GUEST_DS_BASE, guest_ds_base),
 856         FIELD(GUEST_FS_BASE, guest_fs_base),
 857         FIELD(GUEST_GS_BASE, guest_gs_base),
 858         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 859         FIELD(GUEST_TR_BASE, guest_tr_base),
 860         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 861         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 862         FIELD(GUEST_DR7, guest_dr7),
 863         FIELD(GUEST_RSP, guest_rsp),
 864         FIELD(GUEST_RIP, guest_rip),
 865         FIELD(GUEST_RFLAGS, guest_rflags),
 866         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 867         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 868         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 869         FIELD(HOST_CR0, host_cr0),
 870         FIELD(HOST_CR3, host_cr3),
 871         FIELD(HOST_CR4, host_cr4),
 872         FIELD(HOST_FS_BASE, host_fs_base),
 873         FIELD(HOST_GS_BASE, host_gs_base),
 874         FIELD(HOST_TR_BASE, host_tr_base),
 875         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 876         FIELD(HOST_IDTR_BASE, host_idtr_base),
 877         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 878         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 879         FIELD(HOST_RSP, host_rsp),
 880         FIELD(HOST_RIP, host_rip),
 881 };
 882
 883 static inline short vmcs_field_to_offset(unsigned long field)
 884 {
 885         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 886
 887         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 888             vmcs_field_to_offset_table[field] == 0)
 889                 return -ENOENT;
 890
 891         return vmcs_field_to_offset_table[field];
 892 }
 893
 894 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 895 {
 896         return to_vmx(vcpu)->nested.cached_vmcs12;
 897 }
 898
 899 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 900 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 901 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 902 static bool vmx_xsaves_supported(void);
 903 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 904 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 905                             struct kvm_segment *var, int seg);
 906 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 907                             struct kvm_segment *var, int seg);
 908 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 909 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 910 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 911 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 912 static int alloc_identity_pagetable(struct kvm *kvm);
 913 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 914 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 915 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 916                                             u16 error_code);
 917
 918 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 919 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 920 /*
 921  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 922  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 923  */
 924 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 925
 926 /*
 927  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 928  * can find which vCPU should be waken up.
 929  */
 930 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 931 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 932
 933 enum {
 934         VMX_IO_BITMAP_A,
 935         VMX_IO_BITMAP_B,
 936         VMX_MSR_BITMAP_LEGACY,
 937         VMX_MSR_BITMAP_LONGMODE,
 938         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 939         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 940         VMX_MSR_BITMAP_LEGACY_X2APIC,
 941         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 942         VMX_VMREAD_BITMAP,
 943         VMX_VMWRITE_BITMAP,
 944         VMX_BITMAP_NR
 945 };
 946
 947 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 948
 949 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 950 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 951 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 952 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 953 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 954 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 955 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 956 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 957 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 958 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 959
 960 static bool cpu_has_load_ia32_efer;
 961 static bool cpu_has_load_perf_global_ctrl;
 962
 963 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 964 static DEFINE_SPINLOCK(vmx_vpid_lock);
 965
 966 static struct vmcs_config {
 967         int size;
 968         int order;
 969         u32 basic_cap;
 970         u32 revision_id;
 971         u32 pin_based_exec_ctrl;
 972         u32 cpu_based_exec_ctrl;
 973         u32 cpu_based_2nd_exec_ctrl;
 974         u32 vmexit_ctrl;
 975         u32 vmentry_ctrl;
 976 } vmcs_config;
 977
 978 static struct vmx_capability {
 979         u32 ept;
 980         u32 vpid;
 981 } vmx_capability;
 982
 983 #define VMX_SEGMENT_FIELD(seg)                                  \
 984         [VCPU_SREG_##seg] = {                                   \
 985                 .selector = GUEST_##seg##_SELECTOR,             \
 986                 .base = GUEST_##seg##_BASE,                     \
 987                 .limit = GUEST_##seg##_LIMIT,                   \
 988                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 989         }
 990
 991 static const struct kvm_vmx_segment_field {
 992         unsigned selector;
 993         unsigned base;
 994         unsigned limit;
 995         unsigned ar_bytes;
 996 } kvm_vmx_segment_fields[] = {
 997         VMX_SEGMENT_FIELD(CS),
 998         VMX_SEGMENT_FIELD(DS),
 999         VMX_SEGMENT_FIELD(ES),
1000         VMX_SEGMENT_FIELD(FS),
1001         VMX_SEGMENT_FIELD(GS),
1002         VMX_SEGMENT_FIELD(SS),
1003         VMX_SEGMENT_FIELD(TR),
1004         VMX_SEGMENT_FIELD(LDTR),
1005 };
1006
1007 static u64 host_efer;
1008
1009 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1010
1011 /*
1012  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1013  * away by decrementing the array size.
1014  */
1015 static const u32 vmx_msr_index[] = {
1016 #ifdef CONFIG_X86_64
1017         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1018 #endif
1019         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1020 };
1021
1022 static inline bool is_exception_n(u32 intr_info, u8 vector)
1023 {
1024         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1025                              INTR_INFO_VALID_MASK)) ==
1026                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1027 }
1028
1029 static inline bool is_debug(u32 intr_info)
1030 {
1031         return is_exception_n(intr_info, DB_VECTOR);
1032 }
1033
1034 static inline bool is_breakpoint(u32 intr_info)
1035 {
1036         return is_exception_n(intr_info, BP_VECTOR);
1037 }
1038
1039 static inline bool is_page_fault(u32 intr_info)
1040 {
1041         return is_exception_n(intr_info, PF_VECTOR);
1042 }
1043
1044 static inline bool is_no_device(u32 intr_info)
1045 {
1046         return is_exception_n(intr_info, NM_VECTOR);
1047 }
1048
1049 static inline bool is_invalid_opcode(u32 intr_info)
1050 {
1051         return is_exception_n(intr_info, UD_VECTOR);
1052 }
1053
1054 static inline bool is_external_interrupt(u32 intr_info)
1055 {
1056         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1057                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1058 }
1059
1060 static inline bool is_machine_check(u32 intr_info)
1061 {
1062         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1063                              INTR_INFO_VALID_MASK)) ==
1064                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1065 }
1066
1067 static inline bool cpu_has_vmx_msr_bitmap(void)
1068 {
1069         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1070 }
1071
1072 static inline bool cpu_has_vmx_tpr_shadow(void)
1073 {
1074         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1075 }
1076
1077 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1078 {
1079         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1080 }
1081
1082 static inline bool cpu_has_secondary_exec_ctrls(void)
1083 {
1084         return vmcs_config.cpu_based_exec_ctrl &
1085                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1086 }
1087
1088 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1089 {
1090         return vmcs_config.cpu_based_2nd_exec_ctrl &
1091                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1092 }
1093
1094 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1095 {
1096         return vmcs_config.cpu_based_2nd_exec_ctrl &
1097                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1098 }
1099
1100 static inline bool cpu_has_vmx_apic_register_virt(void)
1101 {
1102         return vmcs_config.cpu_based_2nd_exec_ctrl &
1103                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1104 }
1105
1106 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1107 {
1108         return vmcs_config.cpu_based_2nd_exec_ctrl &
1109                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1110 }
1111
1112 /*
1113  * Comment's format: document - errata name - stepping - processor name.
1114  * Refer from
1115  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1116  */
1117 static u32 vmx_preemption_cpu_tfms[] = {
1118 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1119 0x000206E6,
1120 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1121 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1122 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1123 0x00020652,
1124 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1125 0x00020655,
1126 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1127 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1128 /*
1129  * 320767.pdf - AAP86  - B1 -
1130  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1131  */
1132 0x000106E5,
1133 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1134 0x000106A0,
1135 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1136 0x000106A1,
1137 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1138 0x000106A4,
1139  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1140  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1141  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1142 0x000106A5,
1143 };
1144
1145 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1146 {
1147         u32 eax = cpuid_eax(0x00000001), i;
1148
1149         /* Clear the reserved bits */
1150         eax &= ~(0x3U << 14 | 0xfU << 28);
1151         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1152                 if (eax == vmx_preemption_cpu_tfms[i])
1153                         return true;
1154
1155         return false;
1156 }
1157
1158 static inline bool cpu_has_vmx_preemption_timer(void)
1159 {
1160         return vmcs_config.pin_based_exec_ctrl &
1161                 PIN_BASED_VMX_PREEMPTION_TIMER;
1162 }
1163
1164 static inline bool cpu_has_vmx_posted_intr(void)
1165 {
1166         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1167                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1168 }
1169
1170 static inline bool cpu_has_vmx_apicv(void)
1171 {
1172         return cpu_has_vmx_apic_register_virt() &&
1173                 cpu_has_vmx_virtual_intr_delivery() &&
1174                 cpu_has_vmx_posted_intr();
1175 }
1176
1177 static inline bool cpu_has_vmx_flexpriority(void)
1178 {
1179         return cpu_has_vmx_tpr_shadow() &&
1180                 cpu_has_vmx_virtualize_apic_accesses();
1181 }
1182
1183 static inline bool cpu_has_vmx_ept_execute_only(void)
1184 {
1185         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1186 }
1187
1188 static inline bool cpu_has_vmx_ept_2m_page(void)
1189 {
1190         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1191 }
1192
1193 static inline bool cpu_has_vmx_ept_1g_page(void)
1194 {
1195         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept_4levels(void)
1199 {
1200         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1201 }
1202
1203 static inline bool cpu_has_vmx_ept_mt_wb(void)
1204 {
1205         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_ept_5levels(void)
1209 {
1210         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_ept_ad_bits(void)
1214 {
1215         return vmx_capability.ept & VMX_EPT_AD_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_invept_context(void)
1219 {
1220         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_invept_global(void)
1224 {
1225         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1226 }
1227
1228 static inline bool cpu_has_vmx_invvpid_single(void)
1229 {
1230         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1231 }
1232
1233 static inline bool cpu_has_vmx_invvpid_global(void)
1234 {
1235         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1236 }
1237
1238 static inline bool cpu_has_vmx_invvpid(void)
1239 {
1240         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1241 }
1242
1243 static inline bool cpu_has_vmx_ept(void)
1244 {
1245         return vmcs_config.cpu_based_2nd_exec_ctrl &
1246                 SECONDARY_EXEC_ENABLE_EPT;
1247 }
1248
1249 static inline bool cpu_has_vmx_unrestricted_guest(void)
1250 {
1251         return vmcs_config.cpu_based_2nd_exec_ctrl &
1252                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1253 }
1254
1255 static inline bool cpu_has_vmx_ple(void)
1256 {
1257         return vmcs_config.cpu_based_2nd_exec_ctrl &
1258                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1259 }
1260
1261 static inline bool cpu_has_vmx_basic_inout(void)
1262 {
1263         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1264 }
1265
1266 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1267 {
1268         return flexpriority_enabled && lapic_in_kernel(vcpu);
1269 }
1270
1271 static inline bool cpu_has_vmx_vpid(void)
1272 {
1273         return vmcs_config.cpu_based_2nd_exec_ctrl &
1274                 SECONDARY_EXEC_ENABLE_VPID;
1275 }
1276
1277 static inline bool cpu_has_vmx_rdtscp(void)
1278 {
1279         return vmcs_config.cpu_based_2nd_exec_ctrl &
1280                 SECONDARY_EXEC_RDTSCP;
1281 }
1282
1283 static inline bool cpu_has_vmx_invpcid(void)
1284 {
1285         return vmcs_config.cpu_based_2nd_exec_ctrl &
1286                 SECONDARY_EXEC_ENABLE_INVPCID;
1287 }
1288
1289 static inline bool cpu_has_vmx_wbinvd_exit(void)
1290 {
1291         return vmcs_config.cpu_based_2nd_exec_ctrl &
1292                 SECONDARY_EXEC_WBINVD_EXITING;
1293 }
1294
1295 static inline bool cpu_has_vmx_shadow_vmcs(void)
1296 {
1297         u64 vmx_msr;
1298         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1299         /* check if the cpu supports writing r/o exit information fields */
1300         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1301                 return false;
1302
1303         return vmcs_config.cpu_based_2nd_exec_ctrl &
1304                 SECONDARY_EXEC_SHADOW_VMCS;
1305 }
1306
1307 static inline bool cpu_has_vmx_pml(void)
1308 {
1309         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1310 }
1311
1312 static inline bool cpu_has_vmx_tsc_scaling(void)
1313 {
1314         return vmcs_config.cpu_based_2nd_exec_ctrl &
1315                 SECONDARY_EXEC_TSC_SCALING;
1316 }
1317
1318 static inline bool cpu_has_vmx_vmfunc(void)
1319 {
1320         return vmcs_config.cpu_based_2nd_exec_ctrl &
1321                 SECONDARY_EXEC_ENABLE_VMFUNC;
1322 }
1323
1324 static inline bool report_flexpriority(void)
1325 {
1326         return flexpriority_enabled;
1327 }
1328
1329 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1330 {
1331         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1332 }
1333
1334 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1335 {
1336         return vmcs12->cpu_based_vm_exec_control & bit;
1337 }
1338
1339 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1340 {
1341         return (vmcs12->cpu_based_vm_exec_control &
1342                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1343                 (vmcs12->secondary_vm_exec_control & bit);
1344 }
1345
1346 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1347 {
1348         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1349 }
1350
1351 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1352 {
1353         return vmcs12->pin_based_vm_exec_control &
1354                 PIN_BASED_VMX_PREEMPTION_TIMER;
1355 }
1356
1357 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1358 {
1359         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1360 }
1361
1362 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1363 {
1364         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1365 }
1366
1367 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1368 {
1369         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1370 }
1371
1372 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1373 {
1374         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1375 }
1376
1377 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1378 {
1379         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1380 }
1381
1382 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1383 {
1384         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1385 }
1386
1387 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1388 {
1389         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1390 }
1391
1392 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1393 {
1394         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1395 }
1396
1397 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1398 {
1399         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1400 }
1401
1402 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1403 {
1404         return nested_cpu_has_vmfunc(vmcs12) &&
1405                 (vmcs12->vm_function_control &
1406                  VMX_VMFUNC_EPTP_SWITCHING);
1407 }
1408
1409 static inline bool is_nmi(u32 intr_info)
1410 {
1411         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1412                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1413 }
1414
1415 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1416                               u32 exit_intr_info,
1417                               unsigned long exit_qualification);
1418 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1419                         struct vmcs12 *vmcs12,
1420                         u32 reason, unsigned long qualification);
1421
1422 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1423 {
1424         int i;
1425
1426         for (i = 0; i < vmx->nmsrs; ++i)
1427                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1428                         return i;
1429         return -1;
1430 }
1431
1432 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1433 {
1434     struct {
1435         u64 vpid : 16;
1436         u64 rsvd : 48;
1437         u64 gva;
1438     } operand = { vpid, 0, gva };
1439
1440     asm volatile (__ex(ASM_VMX_INVVPID)
1441                   /* CF==1 or ZF==1 --> rc = -1 */
1442                   "; ja 1f ; ud2 ; 1:"
1443                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1444 }
1445
1446 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1447 {
1448         struct {
1449                 u64 eptp, gpa;
1450         } operand = {eptp, gpa};
1451
1452         asm volatile (__ex(ASM_VMX_INVEPT)
1453                         /* CF==1 or ZF==1 --> rc = -1 */
1454                         "; ja 1f ; ud2 ; 1:\n"
1455                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1456 }
1457
1458 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1459 {
1460         int i;
1461
1462         i = __find_msr_index(vmx, msr);
1463         if (i >= 0)
1464                 return &vmx->guest_msrs[i];
1465         return NULL;
1466 }
1467
1468 static void vmcs_clear(struct vmcs *vmcs)
1469 {
1470         u64 phys_addr = __pa(vmcs);
1471         u8 error;
1472
1473         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1474                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1475                       : "cc", "memory");
1476         if (error)
1477                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1478                        vmcs, phys_addr);
1479 }
1480
1481 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1482 {
1483         vmcs_clear(loaded_vmcs->vmcs);
1484         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1485                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1486         loaded_vmcs->cpu = -1;
1487         loaded_vmcs->launched = 0;
1488 }
1489
1490 static void vmcs_load(struct vmcs *vmcs)
1491 {
1492         u64 phys_addr = __pa(vmcs);
1493         u8 error;
1494
1495         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1496                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1497                         : "cc", "memory");
1498         if (error)
1499                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1500                        vmcs, phys_addr);
1501 }
1502
1503 #ifdef CONFIG_KEXEC_CORE
1504 /*
1505  * This bitmap is used to indicate whether the vmclear
1506  * operation is enabled on all cpus. All disabled by
1507  * default.
1508  */
1509 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1510
1511 static inline void crash_enable_local_vmclear(int cpu)
1512 {
1513         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1514 }
1515
1516 static inline void crash_disable_local_vmclear(int cpu)
1517 {
1518         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1519 }
1520
1521 static inline int crash_local_vmclear_enabled(int cpu)
1522 {
1523         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1524 }
1525
1526 static void crash_vmclear_local_loaded_vmcss(void)
1527 {
1528         int cpu = raw_smp_processor_id();
1529         struct loaded_vmcs *v;
1530
1531         if (!crash_local_vmclear_enabled(cpu))
1532                 return;
1533
1534         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1535                             loaded_vmcss_on_cpu_link)
1536                 vmcs_clear(v->vmcs);
1537 }
1538 #else
1539 static inline void crash_enable_local_vmclear(int cpu) { }
1540 static inline void crash_disable_local_vmclear(int cpu) { }
1541 #endif /* CONFIG_KEXEC_CORE */
1542
1543 static void __loaded_vmcs_clear(void *arg)
1544 {
1545         struct loaded_vmcs *loaded_vmcs = arg;
1546         int cpu = raw_smp_processor_id();
1547
1548         if (loaded_vmcs->cpu != cpu)
1549                 return; /* vcpu migration can race with cpu offline */
1550         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1551                 per_cpu(current_vmcs, cpu) = NULL;
1552         crash_disable_local_vmclear(cpu);
1553         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1554
1555         /*
1556          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1557          * is before setting loaded_vmcs->vcpu to -1 which is done in
1558          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1559          * then adds the vmcs into percpu list before it is deleted.
1560          */
1561         smp_wmb();
1562
1563         loaded_vmcs_init(loaded_vmcs);
1564         crash_enable_local_vmclear(cpu);
1565 }
1566
1567 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1568 {
1569         int cpu = loaded_vmcs->cpu;
1570
1571         if (cpu != -1)
1572                 smp_call_function_single(cpu,
1573                          __loaded_vmcs_clear, loaded_vmcs, 1);
1574 }
1575
1576 static inline void vpid_sync_vcpu_single(int vpid)
1577 {
1578         if (vpid == 0)
1579                 return;
1580
1581         if (cpu_has_vmx_invvpid_single())
1582                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1583 }
1584
1585 static inline void vpid_sync_vcpu_global(void)
1586 {
1587         if (cpu_has_vmx_invvpid_global())
1588                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1589 }
1590
1591 static inline void vpid_sync_context(int vpid)
1592 {
1593         if (cpu_has_vmx_invvpid_single())
1594                 vpid_sync_vcpu_single(vpid);
1595         else
1596                 vpid_sync_vcpu_global();
1597 }
1598
1599 static inline void ept_sync_global(void)
1600 {
1601         if (cpu_has_vmx_invept_global())
1602                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1603 }
1604
1605 static inline void ept_sync_context(u64 eptp)
1606 {
1607         if (cpu_has_vmx_invept_context())
1608                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1609         else
1610                 ept_sync_global();
1611 }
1612
1613 static __always_inline void vmcs_check16(unsigned long field)
1614 {
1615         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1616                          "16-bit accessor invalid for 64-bit field");
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1618                          "16-bit accessor invalid for 64-bit high field");
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1620                          "16-bit accessor invalid for 32-bit high field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1622                          "16-bit accessor invalid for natural width field");
1623 }
1624
1625 static __always_inline void vmcs_check32(unsigned long field)
1626 {
1627         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1628                          "32-bit accessor invalid for 16-bit field");
1629         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630                          "32-bit accessor invalid for natural width field");
1631 }
1632
1633 static __always_inline void vmcs_check64(unsigned long field)
1634 {
1635         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636                          "64-bit accessor invalid for 16-bit field");
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1638                          "64-bit accessor invalid for 64-bit high field");
1639         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1640                          "64-bit accessor invalid for 32-bit field");
1641         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1642                          "64-bit accessor invalid for natural width field");
1643 }
1644
1645 static __always_inline void vmcs_checkl(unsigned long field)
1646 {
1647         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1648                          "Natural width accessor invalid for 16-bit field");
1649         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1650                          "Natural width accessor invalid for 64-bit field");
1651         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1652                          "Natural width accessor invalid for 64-bit high field");
1653         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1654                          "Natural width accessor invalid for 32-bit field");
1655 }
1656
1657 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1658 {
1659         unsigned long value;
1660
1661         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1662                       : "=a"(value) : "d"(field) : "cc");
1663         return value;
1664 }
1665
1666 static __always_inline u16 vmcs_read16(unsigned long field)
1667 {
1668         vmcs_check16(field);
1669         return __vmcs_readl(field);
1670 }
1671
1672 static __always_inline u32 vmcs_read32(unsigned long field)
1673 {
1674         vmcs_check32(field);
1675         return __vmcs_readl(field);
1676 }
1677
1678 static __always_inline u64 vmcs_read64(unsigned long field)
1679 {
1680         vmcs_check64(field);
1681 #ifdef CONFIG_X86_64
1682         return __vmcs_readl(field);
1683 #else
1684         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1685 #endif
1686 }
1687
1688 static __always_inline unsigned long vmcs_readl(unsigned long field)
1689 {
1690         vmcs_checkl(field);
1691         return __vmcs_readl(field);
1692 }
1693
1694 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1695 {
1696         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1697                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1698         dump_stack();
1699 }
1700
1701 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1702 {
1703         u8 error;
1704
1705         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1706                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1707         if (unlikely(error))
1708                 vmwrite_error(field, value);
1709 }
1710
1711 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1712 {
1713         vmcs_check16(field);
1714         __vmcs_writel(field, value);
1715 }
1716
1717 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1718 {
1719         vmcs_check32(field);
1720         __vmcs_writel(field, value);
1721 }
1722
1723 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1724 {
1725         vmcs_check64(field);
1726         __vmcs_writel(field, value);
1727 #ifndef CONFIG_X86_64
1728         asm volatile ("");
1729         __vmcs_writel(field+1, value >> 32);
1730 #endif
1731 }
1732
1733 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1734 {
1735         vmcs_checkl(field);
1736         __vmcs_writel(field, value);
1737 }
1738
1739 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1740 {
1741         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1742                          "vmcs_clear_bits does not support 64-bit fields");
1743         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1744 }
1745
1746 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1747 {
1748         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1749                          "vmcs_set_bits does not support 64-bit fields");
1750         __vmcs_writel(field, __vmcs_readl(field) | mask);
1751 }
1752
1753 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1754 {
1755         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1756 }
1757
1758 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1759 {
1760         vmcs_write32(VM_ENTRY_CONTROLS, val);
1761         vmx->vm_entry_controls_shadow = val;
1762 }
1763
1764 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1765 {
1766         if (vmx->vm_entry_controls_shadow != val)
1767                 vm_entry_controls_init(vmx, val);
1768 }
1769
1770 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1771 {
1772         return vmx->vm_entry_controls_shadow;
1773 }
1774
1775
1776 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1777 {
1778         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1779 }
1780
1781 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1782 {
1783         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1784 }
1785
1786 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1787 {
1788         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1789 }
1790
1791 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1792 {
1793         vmcs_write32(VM_EXIT_CONTROLS, val);
1794         vmx->vm_exit_controls_shadow = val;
1795 }
1796
1797 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1798 {
1799         if (vmx->vm_exit_controls_shadow != val)
1800                 vm_exit_controls_init(vmx, val);
1801 }
1802
1803 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1804 {
1805         return vmx->vm_exit_controls_shadow;
1806 }
1807
1808
1809 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1810 {
1811         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1812 }
1813
1814 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1815 {
1816         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1817 }
1818
1819 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1820 {
1821         vmx->segment_cache.bitmask = 0;
1822 }
1823
1824 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1825                                        unsigned field)
1826 {
1827         bool ret;
1828         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1829
1830         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1831                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1832                 vmx->segment_cache.bitmask = 0;
1833         }
1834         ret = vmx->segment_cache.bitmask & mask;
1835         vmx->segment_cache.bitmask |= mask;
1836         return ret;
1837 }
1838
1839 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1840 {
1841         u16 *p = &vmx->segment_cache.seg[seg].selector;
1842
1843         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1844                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1845         return *p;
1846 }
1847
1848 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1849 {
1850         ulong *p = &vmx->segment_cache.seg[seg].base;
1851
1852         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1853                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1854         return *p;
1855 }
1856
1857 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1858 {
1859         u32 *p = &vmx->segment_cache.seg[seg].limit;
1860
1861         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1862                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1863         return *p;
1864 }
1865
1866 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1867 {
1868         u32 *p = &vmx->segment_cache.seg[seg].ar;
1869
1870         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1871                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1872         return *p;
1873 }
1874
1875 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1876 {
1877         u32 eb;
1878
1879         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1880              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1881         if ((vcpu->guest_debug &
1882              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1883             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1884                 eb |= 1u << BP_VECTOR;
1885         if (to_vmx(vcpu)->rmode.vm86_active)
1886                 eb = ~0;
1887         if (enable_ept)
1888                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1889
1890         /* When we are running a nested L2 guest and L1 specified for it a
1891          * certain exception bitmap, we must trap the same exceptions and pass
1892          * them to L1. When running L2, we will only handle the exceptions
1893          * specified above if L1 did not want them.
1894          */
1895         if (is_guest_mode(vcpu))
1896                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1897
1898         vmcs_write32(EXCEPTION_BITMAP, eb);
1899 }
1900
1901 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1902                 unsigned long entry, unsigned long exit)
1903 {
1904         vm_entry_controls_clearbit(vmx, entry);
1905         vm_exit_controls_clearbit(vmx, exit);
1906 }
1907
1908 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1909 {
1910         unsigned i;
1911         struct msr_autoload *m = &vmx->msr_autoload;
1912
1913         switch (msr) {
1914         case MSR_EFER:
1915                 if (cpu_has_load_ia32_efer) {
1916                         clear_atomic_switch_msr_special(vmx,
1917                                         VM_ENTRY_LOAD_IA32_EFER,
1918                                         VM_EXIT_LOAD_IA32_EFER);
1919                         return;
1920                 }
1921                 break;
1922         case MSR_CORE_PERF_GLOBAL_CTRL:
1923                 if (cpu_has_load_perf_global_ctrl) {
1924                         clear_atomic_switch_msr_special(vmx,
1925                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1926                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1927                         return;
1928                 }
1929                 break;
1930         }
1931
1932         for (i = 0; i < m->nr; ++i)
1933                 if (m->guest[i].index == msr)
1934                         break;
1935
1936         if (i == m->nr)
1937                 return;
1938         --m->nr;
1939         m->guest[i] = m->guest[m->nr];
1940         m->host[i] = m->host[m->nr];
1941         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1942         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1943 }
1944
1945 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1946                 unsigned long entry, unsigned long exit,
1947                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1948                 u64 guest_val, u64 host_val)
1949 {
1950         vmcs_write64(guest_val_vmcs, guest_val);
1951         vmcs_write64(host_val_vmcs, host_val);
1952         vm_entry_controls_setbit(vmx, entry);
1953         vm_exit_controls_setbit(vmx, exit);
1954 }
1955
1956 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1957                                   u64 guest_val, u64 host_val)
1958 {
1959         unsigned i;
1960         struct msr_autoload *m = &vmx->msr_autoload;
1961
1962         switch (msr) {
1963         case MSR_EFER:
1964                 if (cpu_has_load_ia32_efer) {
1965                         add_atomic_switch_msr_special(vmx,
1966                                         VM_ENTRY_LOAD_IA32_EFER,
1967                                         VM_EXIT_LOAD_IA32_EFER,
1968                                         GUEST_IA32_EFER,
1969                                         HOST_IA32_EFER,
1970                                         guest_val, host_val);
1971                         return;
1972                 }
1973                 break;
1974         case MSR_CORE_PERF_GLOBAL_CTRL:
1975                 if (cpu_has_load_perf_global_ctrl) {
1976                         add_atomic_switch_msr_special(vmx,
1977                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1978                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1979                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1980                                         HOST_IA32_PERF_GLOBAL_CTRL,
1981                                         guest_val, host_val);
1982                         return;
1983                 }
1984                 break;
1985         case MSR_IA32_PEBS_ENABLE:
1986                 /* PEBS needs a quiescent period after being disabled (to write
1987                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1988                  * provide that period, so a CPU could write host's record into
1989                  * guest's memory.
1990                  */
1991                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1992         }
1993
1994         for (i = 0; i < m->nr; ++i)
1995                 if (m->guest[i].index == msr)
1996                         break;
1997
1998         if (i == NR_AUTOLOAD_MSRS) {
1999                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2000                                 "Can't add msr %x\n", msr);
2001                 return;
2002         } else if (i == m->nr) {
2003                 ++m->nr;
2004                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2005                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2006         }
2007
2008         m->guest[i].index = msr;
2009         m->guest[i].value = guest_val;
2010         m->host[i].index = msr;
2011         m->host[i].value = host_val;
2012 }
2013
2014 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2015 {
2016         u64 guest_efer = vmx->vcpu.arch.efer;
2017         u64 ignore_bits = 0;
2018
2019         if (!enable_ept) {
2020                 /*
2021                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2022                  * host CPUID is more efficient than testing guest CPUID
2023                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2024                  */
2025                 if (boot_cpu_has(X86_FEATURE_SMEP))
2026                         guest_efer |= EFER_NX;
2027                 else if (!(guest_efer & EFER_NX))
2028                         ignore_bits |= EFER_NX;
2029         }
2030
2031         /*
2032          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2033          */
2034         ignore_bits |= EFER_SCE;
2035 #ifdef CONFIG_X86_64
2036         ignore_bits |= EFER_LMA | EFER_LME;
2037         /* SCE is meaningful only in long mode on Intel */
2038         if (guest_efer & EFER_LMA)
2039                 ignore_bits &= ~(u64)EFER_SCE;
2040 #endif
2041
2042         clear_atomic_switch_msr(vmx, MSR_EFER);
2043
2044         /*
2045          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2046          * On CPUs that support "load IA32_EFER", always switch EFER
2047          * atomically, since it's faster than switching it manually.
2048          */
2049         if (cpu_has_load_ia32_efer ||
2050             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2051                 if (!(guest_efer & EFER_LMA))
2052                         guest_efer &= ~EFER_LME;
2053                 if (guest_efer != host_efer)
2054                         add_atomic_switch_msr(vmx, MSR_EFER,
2055                                               guest_efer, host_efer);
2056                 return false;
2057         } else {
2058                 guest_efer &= ~ignore_bits;
2059                 guest_efer |= host_efer & ignore_bits;
2060
2061                 vmx->guest_msrs[efer_offset].data = guest_efer;
2062                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2063
2064                 return true;
2065         }
2066 }
2067
2068 #ifdef CONFIG_X86_32
2069 /*
2070  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2071  * VMCS rather than the segment table.  KVM uses this helper to figure
2072  * out the current bases to poke them into the VMCS before entry.
2073  */
2074 static unsigned long segment_base(u16 selector)
2075 {
2076         struct desc_struct *table;
2077         unsigned long v;
2078
2079         if (!(selector & ~SEGMENT_RPL_MASK))
2080                 return 0;
2081
2082         table = get_current_gdt_ro();
2083
2084         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2085                 u16 ldt_selector = kvm_read_ldt();
2086
2087                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2088                         return 0;
2089
2090                 table = (struct desc_struct *)segment_base(ldt_selector);
2091         }
2092         v = get_desc_base(&table[selector >> 3]);
2093         return v;
2094 }
2095 #endif
2096
2097 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2098 {
2099         struct vcpu_vmx *vmx = to_vmx(vcpu);
2100         int i;
2101
2102         if (vmx->host_state.loaded)
2103                 return;
2104
2105         vmx->host_state.loaded = 1;
2106         /*
2107          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2108          * allow segment selectors with cpl > 0 or ti == 1.
2109          */
2110         vmx->host_state.ldt_sel = kvm_read_ldt();
2111         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2112         savesegment(fs, vmx->host_state.fs_sel);
2113         if (!(vmx->host_state.fs_sel & 7)) {
2114                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2115                 vmx->host_state.fs_reload_needed = 0;
2116         } else {
2117                 vmcs_write16(HOST_FS_SELECTOR, 0);
2118                 vmx->host_state.fs_reload_needed = 1;
2119         }
2120         savesegment(gs, vmx->host_state.gs_sel);
2121         if (!(vmx->host_state.gs_sel & 7))
2122                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2123         else {
2124                 vmcs_write16(HOST_GS_SELECTOR, 0);
2125                 vmx->host_state.gs_ldt_reload_needed = 1;
2126         }
2127
2128 #ifdef CONFIG_X86_64
2129         savesegment(ds, vmx->host_state.ds_sel);
2130         savesegment(es, vmx->host_state.es_sel);
2131 #endif
2132
2133 #ifdef CONFIG_X86_64
2134         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2135         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2136 #else
2137         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2138         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2139 #endif
2140
2141 #ifdef CONFIG_X86_64
2142         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2143         if (is_long_mode(&vmx->vcpu))
2144                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2145 #endif
2146         if (boot_cpu_has(X86_FEATURE_MPX))
2147                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2148         for (i = 0; i < vmx->save_nmsrs; ++i)
2149                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2150                                    vmx->guest_msrs[i].data,
2151                                    vmx->guest_msrs[i].mask);
2152 }
2153
2154 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2155 {
2156         if (!vmx->host_state.loaded)
2157                 return;
2158
2159         ++vmx->vcpu.stat.host_state_reload;
2160         vmx->host_state.loaded = 0;
2161 #ifdef CONFIG_X86_64
2162         if (is_long_mode(&vmx->vcpu))
2163                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2164 #endif
2165         if (vmx->host_state.gs_ldt_reload_needed) {
2166                 kvm_load_ldt(vmx->host_state.ldt_sel);
2167 #ifdef CONFIG_X86_64
2168                 load_gs_index(vmx->host_state.gs_sel);
2169 #else
2170                 loadsegment(gs, vmx->host_state.gs_sel);
2171 #endif
2172         }
2173         if (vmx->host_state.fs_reload_needed)
2174                 loadsegment(fs, vmx->host_state.fs_sel);
2175 #ifdef CONFIG_X86_64
2176         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2177                 loadsegment(ds, vmx->host_state.ds_sel);
2178                 loadsegment(es, vmx->host_state.es_sel);
2179         }
2180 #endif
2181         invalidate_tss_limit();
2182 #ifdef CONFIG_X86_64
2183         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2184 #endif
2185         if (vmx->host_state.msr_host_bndcfgs)
2186                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2187         load_fixmap_gdt(raw_smp_processor_id());
2188 }
2189
2190 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2191 {
2192         preempt_disable();
2193         __vmx_load_host_state(vmx);
2194         preempt_enable();
2195 }
2196
2197 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2198 {
2199         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2200         struct pi_desc old, new;
2201         unsigned int dest;
2202
2203         /*
2204          * In case of hot-plug or hot-unplug, we may have to undo
2205          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2206          * always keep PI.NDST up to date for simplicity: it makes the
2207          * code easier, and CPU migration is not a fast path.
2208          */
2209         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2210                 return;
2211
2212         /*
2213          * First handle the simple case where no cmpxchg is necessary; just
2214          * allow posting non-urgent interrupts.
2215          *
2216          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2217          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2218          * expects the VCPU to be on the blocked_vcpu_list that matches
2219          * PI.NDST.
2220          */
2221         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2222             vcpu->cpu == cpu) {
2223                 pi_clear_sn(pi_desc);
2224                 return;
2225         }
2226
2227         /* The full case.  */
2228         do {
2229                 old.control = new.control = pi_desc->control;
2230
2231                 dest = cpu_physical_id(cpu);
2232
2233                 if (x2apic_enabled())
2234                         new.ndst = dest;
2235                 else
2236                         new.ndst = (dest << 8) & 0xFF00;
2237
2238                 new.sn = 0;
2239         } while (cmpxchg64(&pi_desc->control, old.control,
2240                            new.control) != old.control);
2241 }
2242
2243 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2244 {
2245         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2246         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2247 }
2248
2249 /*
2250  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2251  * vcpu mutex is already taken.
2252  */
2253 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2254 {
2255         struct vcpu_vmx *vmx = to_vmx(vcpu);
2256         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2257
2258         if (!already_loaded) {
2259                 loaded_vmcs_clear(vmx->loaded_vmcs);
2260                 local_irq_disable();
2261                 crash_disable_local_vmclear(cpu);
2262
2263                 /*
2264                  * Read loaded_vmcs->cpu should be before fetching
2265                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2266                  * See the comments in __loaded_vmcs_clear().
2267                  */
2268                 smp_rmb();
2269
2270                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2271                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2272                 crash_enable_local_vmclear(cpu);
2273                 local_irq_enable();
2274         }
2275
2276         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2277                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2278                 vmcs_load(vmx->loaded_vmcs->vmcs);
2279         }
2280
2281         if (!already_loaded) {
2282                 void *gdt = get_current_gdt_ro();
2283                 unsigned long sysenter_esp;
2284
2285                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2286
2287                 /*
2288                  * Linux uses per-cpu TSS and GDT, so set these when switching
2289                  * processors.  See 22.2.4.
2290                  */
2291                 vmcs_writel(HOST_TR_BASE,
2292                             (unsigned long)this_cpu_ptr(&cpu_tss));
2293                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2294
2295                 /*
2296                  * VM exits change the host TR limit to 0x67 after a VM
2297                  * exit.  This is okay, since 0x67 covers everything except
2298                  * the IO bitmap and have have code to handle the IO bitmap
2299                  * being lost after a VM exit.
2300                  */
2301                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2302
2303                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2304                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2305
2306                 vmx->loaded_vmcs->cpu = cpu;
2307         }
2308
2309         /* Setup TSC multiplier */
2310         if (kvm_has_tsc_control &&
2311             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2312                 decache_tsc_multiplier(vmx);
2313
2314         vmx_vcpu_pi_load(vcpu, cpu);
2315         vmx->host_pkru = read_pkru();
2316 }
2317
2318 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2319 {
2320         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2321
2322         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2323                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2324                 !kvm_vcpu_apicv_active(vcpu))
2325                 return;
2326
2327         /* Set SN when the vCPU is preempted */
2328         if (vcpu->preempted)
2329                 pi_set_sn(pi_desc);
2330 }
2331
2332 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2333 {
2334         vmx_vcpu_pi_put(vcpu);
2335
2336         __vmx_load_host_state(to_vmx(vcpu));
2337 }
2338
2339 static bool emulation_required(struct kvm_vcpu *vcpu)
2340 {
2341         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2342 }
2343
2344 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2345
2346 /*
2347  * Return the cr0 value that a nested guest would read. This is a combination
2348  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2349  * its hypervisor (cr0_read_shadow).
2350  */
2351 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2352 {
2353         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2354                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2355 }
2356 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2357 {
2358         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2359                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2360 }
2361
2362 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2363 {
2364         unsigned long rflags, save_rflags;
2365
2366         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2367                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2368                 rflags = vmcs_readl(GUEST_RFLAGS);
2369                 if (to_vmx(vcpu)->rmode.vm86_active) {
2370                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2371                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2372                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2373                 }
2374                 to_vmx(vcpu)->rflags = rflags;
2375         }
2376         return to_vmx(vcpu)->rflags;
2377 }
2378
2379 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2380 {
2381         unsigned long old_rflags = vmx_get_rflags(vcpu);
2382
2383         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2384         to_vmx(vcpu)->rflags = rflags;
2385         if (to_vmx(vcpu)->rmode.vm86_active) {
2386                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2387                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2388         }
2389         vmcs_writel(GUEST_RFLAGS, rflags);
2390
2391         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2392                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2393 }
2394
2395 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2396 {
2397         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2398         int ret = 0;
2399
2400         if (interruptibility & GUEST_INTR_STATE_STI)
2401                 ret |= KVM_X86_SHADOW_INT_STI;
2402         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2403                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2404
2405         return ret;
2406 }
2407
2408 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2409 {
2410         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2411         u32 interruptibility = interruptibility_old;
2412
2413         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2414
2415         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2416                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2417         else if (mask & KVM_X86_SHADOW_INT_STI)
2418                 interruptibility |= GUEST_INTR_STATE_STI;
2419
2420         if ((interruptibility != interruptibility_old))
2421                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2422 }
2423
2424 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2425 {
2426         unsigned long rip;
2427
2428         rip = kvm_rip_read(vcpu);
2429         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2430         kvm_rip_write(vcpu, rip);
2431
2432         /* skipping an emulated instruction also counts */
2433         vmx_set_interrupt_shadow(vcpu, 0);
2434 }
2435
2436 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2437                                                unsigned long exit_qual)
2438 {
2439         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2440         unsigned int nr = vcpu->arch.exception.nr;
2441         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2442
2443         if (vcpu->arch.exception.has_error_code) {
2444                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2445                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2446         }
2447
2448         if (kvm_exception_is_soft(nr))
2449                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2450         else
2451                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2452
2453         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2454             vmx_get_nmi_mask(vcpu))
2455                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2456
2457         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2458 }
2459
2460 /*
2461  * KVM wants to inject page-faults which it got to the guest. This function
2462  * checks whether in a nested guest, we need to inject them to L1 or L2.
2463  */
2464 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2465 {
2466         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2467         unsigned int nr = vcpu->arch.exception.nr;
2468
2469         if (nr == PF_VECTOR) {
2470                 if (vcpu->arch.exception.nested_apf) {
2471                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2472                         return 1;
2473                 }
2474                 /*
2475                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2476                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2477                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2478                  * can be written only when inject_pending_event runs.  This should be
2479                  * conditional on a new capability---if the capability is disabled,
2480                  * kvm_multiple_exception would write the ancillary information to
2481                  * CR2 or DR6, for backwards ABI-compatibility.
2482                  */
2483                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2484                                                     vcpu->arch.exception.error_code)) {
2485                         *exit_qual = vcpu->arch.cr2;
2486                         return 1;
2487                 }
2488         } else {
2489                 if (vmcs12->exception_bitmap & (1u << nr)) {
2490                         if (nr == DB_VECTOR)
2491                                 *exit_qual = vcpu->arch.dr6;
2492                         else
2493                                 *exit_qual = 0;
2494                         return 1;
2495                 }
2496         }
2497
2498         return 0;
2499 }
2500
2501 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2502 {
2503         struct vcpu_vmx *vmx = to_vmx(vcpu);
2504         unsigned nr = vcpu->arch.exception.nr;
2505         bool has_error_code = vcpu->arch.exception.has_error_code;
2506         u32 error_code = vcpu->arch.exception.error_code;
2507         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2508
2509         if (has_error_code) {
2510                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2511                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2512         }
2513
2514         if (vmx->rmode.vm86_active) {
2515                 int inc_eip = 0;
2516                 if (kvm_exception_is_soft(nr))
2517                         inc_eip = vcpu->arch.event_exit_inst_len;
2518                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2519                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2520                 return;
2521         }
2522
2523         if (kvm_exception_is_soft(nr)) {
2524                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2525                              vmx->vcpu.arch.event_exit_inst_len);
2526                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2527         } else
2528                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2529
2530         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2531 }
2532
2533 static bool vmx_rdtscp_supported(void)
2534 {
2535         return cpu_has_vmx_rdtscp();
2536 }
2537
2538 static bool vmx_invpcid_supported(void)
2539 {
2540         return cpu_has_vmx_invpcid() && enable_ept;
2541 }
2542
2543 /*
2544  * Swap MSR entry in host/guest MSR entry array.
2545  */
2546 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2547 {
2548         struct shared_msr_entry tmp;
2549
2550         tmp = vmx->guest_msrs[to];
2551         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2552         vmx->guest_msrs[from] = tmp;
2553 }
2554
2555 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2556 {
2557         unsigned long *msr_bitmap;
2558
2559         if (is_guest_mode(vcpu))
2560                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2561         else if (cpu_has_secondary_exec_ctrls() &&
2562                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2563                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2564                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2565                         if (is_long_mode(vcpu))
2566                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2567                         else
2568                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2569                 } else {
2570                         if (is_long_mode(vcpu))
2571                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2572                         else
2573                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2574                 }
2575         } else {
2576                 if (is_long_mode(vcpu))
2577                         msr_bitmap = vmx_msr_bitmap_longmode;
2578                 else
2579                         msr_bitmap = vmx_msr_bitmap_legacy;
2580         }
2581
2582         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2583 }
2584
2585 /*
2586  * Set up the vmcs to automatically save and restore system
2587  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2588  * mode, as fiddling with msrs is very expensive.
2589  */
2590 static void setup_msrs(struct vcpu_vmx *vmx)
2591 {
2592         int save_nmsrs, index;
2593
2594         save_nmsrs = 0;
2595 #ifdef CONFIG_X86_64
2596         if (is_long_mode(&vmx->vcpu)) {
2597                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2598                 if (index >= 0)
2599                         move_msr_up(vmx, index, save_nmsrs++);
2600                 index = __find_msr_index(vmx, MSR_LSTAR);
2601                 if (index >= 0)
2602                         move_msr_up(vmx, index, save_nmsrs++);
2603                 index = __find_msr_index(vmx, MSR_CSTAR);
2604                 if (index >= 0)
2605                         move_msr_up(vmx, index, save_nmsrs++);
2606                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2607                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2608                         move_msr_up(vmx, index, save_nmsrs++);
2609                 /*
2610                  * MSR_STAR is only needed on long mode guests, and only
2611                  * if efer.sce is enabled.
2612                  */
2613                 index = __find_msr_index(vmx, MSR_STAR);
2614                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2615                         move_msr_up(vmx, index, save_nmsrs++);
2616         }
2617 #endif
2618         index = __find_msr_index(vmx, MSR_EFER);
2619         if (index >= 0 && update_transition_efer(vmx, index))
2620                 move_msr_up(vmx, index, save_nmsrs++);
2621
2622         vmx->save_nmsrs = save_nmsrs;
2623
2624         if (cpu_has_vmx_msr_bitmap())
2625                 vmx_set_msr_bitmap(&vmx->vcpu);
2626 }
2627
2628 /*
2629  * reads and returns guest's timestamp counter "register"
2630  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2631  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2632  */
2633 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2634 {
2635         u64 host_tsc, tsc_offset;
2636
2637         host_tsc = rdtsc();
2638         tsc_offset = vmcs_read64(TSC_OFFSET);
2639         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2640 }
2641
2642 /*
2643  * writes 'offset' into guest's timestamp counter offset register
2644  */
2645 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2646 {
2647         if (is_guest_mode(vcpu)) {
2648                 /*
2649                  * We're here if L1 chose not to trap WRMSR to TSC. According
2650                  * to the spec, this should set L1's TSC; The offset that L1
2651                  * set for L2 remains unchanged, and still needs to be added
2652                  * to the newly set TSC to get L2's TSC.
2653                  */
2654                 struct vmcs12 *vmcs12;
2655                 /* recalculate vmcs02.TSC_OFFSET: */
2656                 vmcs12 = get_vmcs12(vcpu);
2657                 vmcs_write64(TSC_OFFSET, offset +
2658                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2659                          vmcs12->tsc_offset : 0));
2660         } else {
2661                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2662                                            vmcs_read64(TSC_OFFSET), offset);
2663                 vmcs_write64(TSC_OFFSET, offset);
2664         }
2665 }
2666
2667 /*
2668  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2669  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2670  * all guests if the "nested" module option is off, and can also be disabled
2671  * for a single guest by disabling its VMX cpuid bit.
2672  */
2673 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2674 {
2675         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2676 }
2677
2678 /*
2679  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2680  * returned for the various VMX controls MSRs when nested VMX is enabled.
2681  * The same values should also be used to verify that vmcs12 control fields are
2682  * valid during nested entry from L1 to L2.
2683  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2684  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2685  * bit in the high half is on if the corresponding bit in the control field
2686  * may be on. See also vmx_control_verify().
2687  */
2688 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2689 {
2690         /*
2691          * Note that as a general rule, the high half of the MSRs (bits in
2692          * the control fields which may be 1) should be initialized by the
2693          * intersection of the underlying hardware's MSR (i.e., features which
2694          * can be supported) and the list of features we want to expose -
2695          * because they are known to be properly supported in our code.
2696          * Also, usually, the low half of the MSRs (bits which must be 1) can
2697          * be set to 0, meaning that L1 may turn off any of these bits. The
2698          * reason is that if one of these bits is necessary, it will appear
2699          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2700          * fields of vmcs01 and vmcs02, will turn these bits off - and
2701          * nested_vmx_exit_reflected() will not pass related exits to L1.
2702          * These rules have exceptions below.
2703          */
2704
2705         /* pin-based controls */
2706         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2707                 vmx->nested.nested_vmx_pinbased_ctls_low,
2708                 vmx->nested.nested_vmx_pinbased_ctls_high);
2709         vmx->nested.nested_vmx_pinbased_ctls_low |=
2710                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2711         vmx->nested.nested_vmx_pinbased_ctls_high &=
2712                 PIN_BASED_EXT_INTR_MASK |
2713                 PIN_BASED_NMI_EXITING |
2714                 PIN_BASED_VIRTUAL_NMIS;
2715         vmx->nested.nested_vmx_pinbased_ctls_high |=
2716                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2717                 PIN_BASED_VMX_PREEMPTION_TIMER;
2718         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2719                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2720                         PIN_BASED_POSTED_INTR;
2721
2722         /* exit controls */
2723         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2724                 vmx->nested.nested_vmx_exit_ctls_low,
2725                 vmx->nested.nested_vmx_exit_ctls_high);
2726         vmx->nested.nested_vmx_exit_ctls_low =
2727                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2728
2729         vmx->nested.nested_vmx_exit_ctls_high &=
2730 #ifdef CONFIG_X86_64
2731                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2732 #endif
2733                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2734         vmx->nested.nested_vmx_exit_ctls_high |=
2735                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2736                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2737                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2738
2739         if (kvm_mpx_supported())
2740                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2741
2742         /* We support free control of debug control saving. */
2743         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2744
2745         /* entry controls */
2746         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2747                 vmx->nested.nested_vmx_entry_ctls_low,
2748                 vmx->nested.nested_vmx_entry_ctls_high);
2749         vmx->nested.nested_vmx_entry_ctls_low =
2750                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2751         vmx->nested.nested_vmx_entry_ctls_high &=
2752 #ifdef CONFIG_X86_64
2753                 VM_ENTRY_IA32E_MODE |
2754 #endif
2755                 VM_ENTRY_LOAD_IA32_PAT;
2756         vmx->nested.nested_vmx_entry_ctls_high |=
2757                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2758         if (kvm_mpx_supported())
2759                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2760
2761         /* We support free control of debug control loading. */
2762         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2763
2764         /* cpu-based controls */
2765         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2766                 vmx->nested.nested_vmx_procbased_ctls_low,
2767                 vmx->nested.nested_vmx_procbased_ctls_high);
2768         vmx->nested.nested_vmx_procbased_ctls_low =
2769                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2770         vmx->nested.nested_vmx_procbased_ctls_high &=
2771                 CPU_BASED_VIRTUAL_INTR_PENDING |
2772                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2773                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2774                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2775                 CPU_BASED_CR3_STORE_EXITING |
2776 #ifdef CONFIG_X86_64
2777                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2778 #endif
2779                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2780                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2781                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2782                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2783                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2784         /*
2785          * We can allow some features even when not supported by the
2786          * hardware. For example, L1 can specify an MSR bitmap - and we
2787          * can use it to avoid exits to L1 - even when L0 runs L2
2788          * without MSR bitmaps.
2789          */
2790         vmx->nested.nested_vmx_procbased_ctls_high |=
2791                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2792                 CPU_BASED_USE_MSR_BITMAPS;
2793
2794         /* We support free control of CR3 access interception. */
2795         vmx->nested.nested_vmx_procbased_ctls_low &=
2796                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2797
2798         /*
2799          * secondary cpu-based controls.  Do not include those that
2800          * depend on CPUID bits, they are added later by vmx_cpuid_update.
2801          */
2802         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2803                 vmx->nested.nested_vmx_secondary_ctls_low,
2804                 vmx->nested.nested_vmx_secondary_ctls_high);
2805         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2806         vmx->nested.nested_vmx_secondary_ctls_high &=
2807                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2808                 SECONDARY_EXEC_DESC |
2809                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2810                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2811                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2812                 SECONDARY_EXEC_WBINVD_EXITING;
2813
2814         if (enable_ept) {
2815                 /* nested EPT: emulate EPT also to L1 */
2816                 vmx->nested.nested_vmx_secondary_ctls_high |=
2817                         SECONDARY_EXEC_ENABLE_EPT;
2818                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2819                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2820                 if (cpu_has_vmx_ept_execute_only())
2821                         vmx->nested.nested_vmx_ept_caps |=
2822                                 VMX_EPT_EXECUTE_ONLY_BIT;
2823                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2824                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2825                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2826                         VMX_EPT_1GB_PAGE_BIT;
2827                 if (enable_ept_ad_bits) {
2828                         vmx->nested.nested_vmx_secondary_ctls_high |=
2829                                 SECONDARY_EXEC_ENABLE_PML;
2830                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2831                 }
2832         } else
2833                 vmx->nested.nested_vmx_ept_caps = 0;
2834
2835         if (cpu_has_vmx_vmfunc()) {
2836                 vmx->nested.nested_vmx_secondary_ctls_high |=
2837                         SECONDARY_EXEC_ENABLE_VMFUNC;
2838                 /*
2839                  * Advertise EPTP switching unconditionally
2840                  * since we emulate it
2841                  */
2842                 vmx->nested.nested_vmx_vmfunc_controls =
2843                         VMX_VMFUNC_EPTP_SWITCHING;
2844         }
2845
2846         /*
2847          * Old versions of KVM use the single-context version without
2848          * checking for support, so declare that it is supported even
2849          * though it is treated as global context.  The alternative is
2850          * not failing the single-context invvpid, and it is worse.
2851          */
2852         if (enable_vpid) {
2853                 vmx->nested.nested_vmx_secondary_ctls_high |=
2854                         SECONDARY_EXEC_ENABLE_VPID;
2855                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2856                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2857         } else
2858                 vmx->nested.nested_vmx_vpid_caps = 0;
2859
2860         if (enable_unrestricted_guest)
2861                 vmx->nested.nested_vmx_secondary_ctls_high |=
2862                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2863
2864         /* miscellaneous data */
2865         rdmsr(MSR_IA32_VMX_MISC,
2866                 vmx->nested.nested_vmx_misc_low,
2867                 vmx->nested.nested_vmx_misc_high);
2868         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2869         vmx->nested.nested_vmx_misc_low |=
2870                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2871                 VMX_MISC_ACTIVITY_HLT;
2872         vmx->nested.nested_vmx_misc_high = 0;
2873
2874         /*
2875          * This MSR reports some information about VMX support. We
2876          * should return information about the VMX we emulate for the
2877          * guest, and the VMCS structure we give it - not about the
2878          * VMX support of the underlying hardware.
2879          */
2880         vmx->nested.nested_vmx_basic =
2881                 VMCS12_REVISION |
2882                 VMX_BASIC_TRUE_CTLS |
2883                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2884                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2885
2886         if (cpu_has_vmx_basic_inout())
2887                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2888
2889         /*
2890          * These MSRs specify bits which the guest must keep fixed on
2891          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2892          * We picked the standard core2 setting.
2893          */
2894 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2895 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2896         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2897         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2898
2899         /* These MSRs specify bits which the guest must keep fixed off. */
2900         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2901         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2902
2903         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2904         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2905 }
2906
2907 /*
2908  * if fixed0[i] == 1: val[i] must be 1
2909  * if fixed1[i] == 0: val[i] must be 0
2910  */
2911 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2912 {
2913         return ((val & fixed1) | fixed0) == val;
2914 }
2915
2916 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2917 {
2918         return fixed_bits_valid(control, low, high);
2919 }
2920
2921 static inline u64 vmx_control_msr(u32 low, u32 high)
2922 {
2923         return low | ((u64)high << 32);
2924 }
2925
2926 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2927 {
2928         superset &= mask;
2929         subset &= mask;
2930
2931         return (superset | subset) == superset;
2932 }
2933
2934 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2935 {
2936         const u64 feature_and_reserved =
2937                 /* feature (except bit 48; see below) */
2938                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2939                 /* reserved */
2940                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2941         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2942
2943         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2944                 return -EINVAL;
2945
2946         /*
2947          * KVM does not emulate a version of VMX that constrains physical
2948          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2949          */
2950         if (data & BIT_ULL(48))
2951                 return -EINVAL;
2952
2953         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2954             vmx_basic_vmcs_revision_id(data))
2955                 return -EINVAL;
2956
2957         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2958                 return -EINVAL;
2959
2960         vmx->nested.nested_vmx_basic = data;
2961         return 0;
2962 }
2963
2964 static int
2965 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2966 {
2967         u64 supported;
2968         u32 *lowp, *highp;
2969
2970         switch (msr_index) {
2971         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2972                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2973                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2974                 break;
2975         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2976                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2977                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2978                 break;
2979         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2980                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2981                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2982                 break;
2983         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2984                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2985                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2986                 break;
2987         case MSR_IA32_VMX_PROCBASED_CTLS2:
2988                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2989                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2990                 break;
2991         default:
2992                 BUG();
2993         }
2994
2995         supported = vmx_control_msr(*lowp, *highp);
2996
2997         /* Check must-be-1 bits are still 1. */
2998         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2999                 return -EINVAL;
3000
3001         /* Check must-be-0 bits are still 0. */
3002         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3003                 return -EINVAL;
3004
3005         *lowp = data;
3006         *highp = data >> 32;
3007         return 0;
3008 }
3009
3010 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3011 {
3012         const u64 feature_and_reserved_bits =
3013                 /* feature */
3014                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3015                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3016                 /* reserved */
3017                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3018         u64 vmx_misc;
3019
3020         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3021                                    vmx->nested.nested_vmx_misc_high);
3022
3023         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3024                 return -EINVAL;
3025
3026         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3027              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3028             vmx_misc_preemption_timer_rate(data) !=
3029             vmx_misc_preemption_timer_rate(vmx_misc))
3030                 return -EINVAL;
3031
3032         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3033                 return -EINVAL;
3034
3035         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3036                 return -EINVAL;
3037
3038         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3039                 return -EINVAL;
3040
3041         vmx->nested.nested_vmx_misc_low = data;
3042         vmx->nested.nested_vmx_misc_high = data >> 32;
3043         return 0;
3044 }
3045
3046 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3047 {
3048         u64 vmx_ept_vpid_cap;
3049
3050         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3051                                            vmx->nested.nested_vmx_vpid_caps);
3052
3053         /* Every bit is either reserved or a feature bit. */
3054         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3055                 return -EINVAL;
3056
3057         vmx->nested.nested_vmx_ept_caps = data;
3058         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3059         return 0;
3060 }
3061
3062 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3063 {
3064         u64 *msr;
3065
3066         switch (msr_index) {
3067         case MSR_IA32_VMX_CR0_FIXED0:
3068                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3069                 break;
3070         case MSR_IA32_VMX_CR4_FIXED0:
3071                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3072                 break;
3073         default:
3074                 BUG();
3075         }
3076
3077         /*
3078          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3079          * must be 1 in the restored value.
3080          */
3081         if (!is_bitwise_subset(data, *msr, -1ULL))
3082                 return -EINVAL;
3083
3084         *msr = data;
3085         return 0;
3086 }
3087
3088 /*
3089  * Called when userspace is restoring VMX MSRs.
3090  *
3091  * Returns 0 on success, non-0 otherwise.
3092  */
3093 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3094 {
3095         struct vcpu_vmx *vmx = to_vmx(vcpu);
3096
3097         switch (msr_index) {
3098         case MSR_IA32_VMX_BASIC:
3099                 return vmx_restore_vmx_basic(vmx, data);
3100         case MSR_IA32_VMX_PINBASED_CTLS:
3101         case MSR_IA32_VMX_PROCBASED_CTLS:
3102         case MSR_IA32_VMX_EXIT_CTLS:
3103         case MSR_IA32_VMX_ENTRY_CTLS:
3104                 /*
3105                  * The "non-true" VMX capability MSRs are generated from the
3106                  * "true" MSRs, so we do not support restoring them directly.
3107                  *
3108                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3109                  * should restore the "true" MSRs with the must-be-1 bits
3110                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3111                  * DEFAULT SETTINGS".
3112                  */
3113                 return -EINVAL;
3114         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3115         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3116         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3117         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3118         case MSR_IA32_VMX_PROCBASED_CTLS2:
3119                 return vmx_restore_control_msr(vmx, msr_index, data);
3120         case MSR_IA32_VMX_MISC:
3121                 return vmx_restore_vmx_misc(vmx, data);
3122         case MSR_IA32_VMX_CR0_FIXED0:
3123         case MSR_IA32_VMX_CR4_FIXED0:
3124                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3125         case MSR_IA32_VMX_CR0_FIXED1:
3126         case MSR_IA32_VMX_CR4_FIXED1:
3127                 /*
3128                  * These MSRs are generated based on the vCPU's CPUID, so we
3129                  * do not support restoring them directly.
3130                  */
3131                 return -EINVAL;
3132         case MSR_IA32_VMX_EPT_VPID_CAP:
3133                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3134         case MSR_IA32_VMX_VMCS_ENUM:
3135                 vmx->nested.nested_vmx_vmcs_enum = data;
3136                 return 0;
3137         default:
3138                 /*
3139                  * The rest of the VMX capability MSRs do not support restore.
3140                  */
3141                 return -EINVAL;
3142         }
3143 }
3144
3145 /* Returns 0 on success, non-0 otherwise. */
3146 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3147 {
3148         struct vcpu_vmx *vmx = to_vmx(vcpu);
3149
3150         switch (msr_index) {
3151         case MSR_IA32_VMX_BASIC:
3152                 *pdata = vmx->nested.nested_vmx_basic;
3153                 break;
3154         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3155         case MSR_IA32_VMX_PINBASED_CTLS:
3156                 *pdata = vmx_control_msr(
3157                         vmx->nested.nested_vmx_pinbased_ctls_low,
3158                         vmx->nested.nested_vmx_pinbased_ctls_high);
3159                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3160                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3161                 break;
3162         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3163         case MSR_IA32_VMX_PROCBASED_CTLS:
3164                 *pdata = vmx_control_msr(
3165                         vmx->nested.nested_vmx_procbased_ctls_low,
3166                         vmx->nested.nested_vmx_procbased_ctls_high);
3167                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3168                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3169                 break;
3170         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3171         case MSR_IA32_VMX_EXIT_CTLS:
3172                 *pdata = vmx_control_msr(
3173                         vmx->nested.nested_vmx_exit_ctls_low,
3174                         vmx->nested.nested_vmx_exit_ctls_high);
3175                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3176                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3177                 break;
3178         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3179         case MSR_IA32_VMX_ENTRY_CTLS:
3180                 *pdata = vmx_control_msr(
3181                         vmx->nested.nested_vmx_entry_ctls_low,
3182                         vmx->nested.nested_vmx_entry_ctls_high);
3183                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3184                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3185                 break;
3186         case MSR_IA32_VMX_MISC:
3187                 *pdata = vmx_control_msr(
3188                         vmx->nested.nested_vmx_misc_low,
3189                         vmx->nested.nested_vmx_misc_high);
3190                 break;
3191         case MSR_IA32_VMX_CR0_FIXED0:
3192                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3193                 break;
3194         case MSR_IA32_VMX_CR0_FIXED1:
3195                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3196                 break;
3197         case MSR_IA32_VMX_CR4_FIXED0:
3198                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3199                 break;
3200         case MSR_IA32_VMX_CR4_FIXED1:
3201                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3202                 break;
3203         case MSR_IA32_VMX_VMCS_ENUM:
3204                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3205                 break;
3206         case MSR_IA32_VMX_PROCBASED_CTLS2:
3207                 *pdata = vmx_control_msr(
3208                         vmx->nested.nested_vmx_secondary_ctls_low,
3209                         vmx->nested.nested_vmx_secondary_ctls_high);
3210                 break;
3211         case MSR_IA32_VMX_EPT_VPID_CAP:
3212                 *pdata = vmx->nested.nested_vmx_ept_caps |
3213                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3214                 break;
3215         case MSR_IA32_VMX_VMFUNC:
3216                 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3217                 break;
3218         default:
3219                 return 1;
3220         }
3221
3222         return 0;
3223 }
3224
3225 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3226                                                  uint64_t val)
3227 {
3228         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3229
3230         return !(val & ~valid_bits);
3231 }
3232
3233 /*
3234  * Reads an msr value (of 'msr_index') into 'pdata'.
3235  * Returns 0 on success, non-0 otherwise.
3236  * Assumes vcpu_load() was already called.
3237  */
3238 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3239 {
3240         struct shared_msr_entry *msr;
3241
3242         switch (msr_info->index) {
3243 #ifdef CONFIG_X86_64
3244         case MSR_FS_BASE:
3245                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3246                 break;
3247         case MSR_GS_BASE:
3248                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3249                 break;
3250         case MSR_KERNEL_GS_BASE:
3251                 vmx_load_host_state(to_vmx(vcpu));
3252                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3253                 break;
3254 #endif
3255         case MSR_EFER:
3256                 return kvm_get_msr_common(vcpu, msr_info);
3257         case MSR_IA32_TSC:
3258                 msr_info->data = guest_read_tsc(vcpu);
3259                 break;
3260         case MSR_IA32_SYSENTER_CS:
3261                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3262                 break;
3263         case MSR_IA32_SYSENTER_EIP:
3264                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3265                 break;
3266         case MSR_IA32_SYSENTER_ESP:
3267                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3268                 break;
3269         case MSR_IA32_BNDCFGS:
3270                 if (!kvm_mpx_supported() ||
3271                     (!msr_info->host_initiated &&
3272                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3273                         return 1;
3274                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3275                 break;
3276         case MSR_IA32_MCG_EXT_CTL:
3277                 if (!msr_info->host_initiated &&
3278                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3279                       FEATURE_CONTROL_LMCE))
3280                         return 1;
3281                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3282                 break;
3283         case MSR_IA32_FEATURE_CONTROL:
3284                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3285                 break;
3286         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3287                 if (!nested_vmx_allowed(vcpu))
3288                         return 1;
3289                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3290         case MSR_IA32_XSS:
3291                 if (!vmx_xsaves_supported())
3292                         return 1;
3293                 msr_info->data = vcpu->arch.ia32_xss;
3294                 break;
3295         case MSR_TSC_AUX:
3296                 if (!msr_info->host_initiated &&
3297                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3298                         return 1;
3299                 /* Otherwise falls through */
3300         default:
3301                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3302                 if (msr) {
3303                         msr_info->data = msr->data;
3304                         break;
3305                 }
3306                 return kvm_get_msr_common(vcpu, msr_info);
3307         }
3308
3309         return 0;
3310 }
3311
3312 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3313
3314 /*
3315  * Writes msr value into into the appropriate "register".
3316  * Returns 0 on success, non-0 otherwise.
3317  * Assumes vcpu_load() was already called.
3318  */
3319 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3320 {
3321         struct vcpu_vmx *vmx = to_vmx(vcpu);
3322         struct shared_msr_entry *msr;
3323         int ret = 0;
3324         u32 msr_index = msr_info->index;
3325         u64 data = msr_info->data;
3326
3327         switch (msr_index) {
3328         case MSR_EFER:
3329                 ret = kvm_set_msr_common(vcpu, msr_info);
3330                 break;
3331 #ifdef CONFIG_X86_64
3332         case MSR_FS_BASE:
3333                 vmx_segment_cache_clear(vmx);
3334                 vmcs_writel(GUEST_FS_BASE, data);
3335                 break;
3336         case MSR_GS_BASE:
3337                 vmx_segment_cache_clear(vmx);
3338                 vmcs_writel(GUEST_GS_BASE, data);
3339                 break;
3340         case MSR_KERNEL_GS_BASE:
3341                 vmx_load_host_state(vmx);
3342                 vmx->msr_guest_kernel_gs_base = data;
3343                 break;
3344 #endif
3345         case MSR_IA32_SYSENTER_CS:
3346                 vmcs_write32(GUEST_SYSENTER_CS, data);
3347                 break;
3348         case MSR_IA32_SYSENTER_EIP:
3349                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3350                 break;
3351         case MSR_IA32_SYSENTER_ESP:
3352                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3353                 break;
3354         case MSR_IA32_BNDCFGS:
3355                 if (!kvm_mpx_supported() ||
3356                     (!msr_info->host_initiated &&
3357                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3358                         return 1;
3359                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3360                     (data & MSR_IA32_BNDCFGS_RSVD))
3361                         return 1;
3362                 vmcs_write64(GUEST_BNDCFGS, data);
3363                 break;
3364         case MSR_IA32_TSC:
3365                 kvm_write_tsc(vcpu, msr_info);
3366                 break;
3367         case MSR_IA32_CR_PAT:
3368                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3369                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3370                                 return 1;
3371                         vmcs_write64(GUEST_IA32_PAT, data);
3372                         vcpu->arch.pat = data;
3373                         break;
3374                 }
3375                 ret = kvm_set_msr_common(vcpu, msr_info);
3376                 break;
3377         case MSR_IA32_TSC_ADJUST:
3378                 ret = kvm_set_msr_common(vcpu, msr_info);
3379                 break;
3380         case MSR_IA32_MCG_EXT_CTL:
3381                 if ((!msr_info->host_initiated &&
3382                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3383                        FEATURE_CONTROL_LMCE)) ||
3384                     (data & ~MCG_EXT_CTL_LMCE_EN))
3385                         return 1;
3386                 vcpu->arch.mcg_ext_ctl = data;
3387                 break;
3388         case MSR_IA32_FEATURE_CONTROL:
3389                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3390                     (to_vmx(vcpu)->msr_ia32_feature_control &
3391                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3392                         return 1;
3393                 vmx->msr_ia32_feature_control = data;
3394                 if (msr_info->host_initiated && data == 0)
3395                         vmx_leave_nested(vcpu);
3396                 break;
3397         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3398                 if (!msr_info->host_initiated)
3399                         return 1; /* they are read-only */
3400                 if (!nested_vmx_allowed(vcpu))
3401                         return 1;
3402                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3403         case MSR_IA32_XSS:
3404                 if (!vmx_xsaves_supported())
3405                         return 1;
3406                 /*
3407                  * The only supported bit as of Skylake is bit 8, but
3408                  * it is not supported on KVM.
3409                  */
3410                 if (data != 0)
3411                         return 1;
3412                 vcpu->arch.ia32_xss = data;
3413                 if (vcpu->arch.ia32_xss != host_xss)
3414                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3415                                 vcpu->arch.ia32_xss, host_xss);
3416                 else
3417                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3418                 break;
3419         case MSR_TSC_AUX:
3420                 if (!msr_info->host_initiated &&
3421                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3422                         return 1;
3423                 /* Check reserved bit, higher 32 bits should be zero */
3424                 if ((data >> 32) != 0)
3425                         return 1;
3426                 /* Otherwise falls through */
3427         default:
3428                 msr = find_msr_entry(vmx, msr_index);
3429                 if (msr) {
3430                         u64 old_msr_data = msr->data;
3431                         msr->data = data;
3432                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3433                                 preempt_disable();
3434                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3435                                                          msr->mask);
3436                                 preempt_enable();
3437                                 if (ret)
3438                                         msr->data = old_msr_data;
3439                         }
3440                         break;
3441                 }
3442                 ret = kvm_set_msr_common(vcpu, msr_info);
3443         }
3444
3445         return ret;
3446 }
3447
3448 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3449 {
3450         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3451         switch (reg) {
3452         case VCPU_REGS_RSP:
3453                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3454                 break;
3455         case VCPU_REGS_RIP:
3456                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3457                 break;
3458         case VCPU_EXREG_PDPTR:
3459                 if (enable_ept)
3460                         ept_save_pdptrs(vcpu);
3461                 break;
3462         default:
3463                 break;
3464         }
3465 }
3466
3467 static __init int cpu_has_kvm_support(void)
3468 {
3469         return cpu_has_vmx();
3470 }
3471
3472 static __init int vmx_disabled_by_bios(void)
3473 {
3474         u64 msr;
3475
3476         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3477         if (msr & FEATURE_CONTROL_LOCKED) {
3478                 /* launched w/ TXT and VMX disabled */
3479                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3480                         && tboot_enabled())
3481                         return 1;
3482                 /* launched w/o TXT and VMX only enabled w/ TXT */
3483                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3484                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3485                         && !tboot_enabled()) {
3486                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3487                                 "activate TXT before enabling KVM\n");
3488                         return 1;
3489                 }
3490                 /* launched w/o TXT and VMX disabled */
3491                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3492                         && !tboot_enabled())
3493                         return 1;
3494         }
3495
3496         return 0;
3497 }
3498
3499 static void kvm_cpu_vmxon(u64 addr)
3500 {
3501         cr4_set_bits(X86_CR4_VMXE);
3502         intel_pt_handle_vmx(1);
3503
3504         asm volatile (ASM_VMX_VMXON_RAX
3505                         : : "a"(&addr), "m"(addr)
3506                         : "memory", "cc");
3507 }
3508
3509 static int hardware_enable(void)
3510 {
3511         int cpu = raw_smp_processor_id();
3512         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3513         u64 old, test_bits;
3514
3515         if (cr4_read_shadow() & X86_CR4_VMXE)
3516                 return -EBUSY;
3517
3518         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3519         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3520         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3521
3522         /*
3523          * Now we can enable the vmclear operation in kdump
3524          * since the loaded_vmcss_on_cpu list on this cpu
3525          * has been initialized.
3526          *
3527          * Though the cpu is not in VMX operation now, there
3528          * is no problem to enable the vmclear operation
3529          * for the loaded_vmcss_on_cpu list is empty!
3530          */
3531         crash_enable_local_vmclear(cpu);
3532
3533         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3534
3535         test_bits = FEATURE_CONTROL_LOCKED;
3536         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3537         if (tboot_enabled())
3538                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3539
3540         if ((old & test_bits) != test_bits) {
3541                 /* enable and lock */
3542                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3543         }
3544         kvm_cpu_vmxon(phys_addr);
3545         if (enable_ept)
3546                 ept_sync_global();
3547
3548         return 0;
3549 }
3550
3551 static void vmclear_local_loaded_vmcss(void)
3552 {
3553         int cpu = raw_smp_processor_id();
3554         struct loaded_vmcs *v, *n;
3555
3556         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3557                                  loaded_vmcss_on_cpu_link)
3558                 __loaded_vmcs_clear(v);
3559 }
3560
3561
3562 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3563  * tricks.
3564  */
3565 static void kvm_cpu_vmxoff(void)
3566 {
3567         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3568
3569         intel_pt_handle_vmx(0);
3570         cr4_clear_bits(X86_CR4_VMXE);
3571 }
3572
3573 static void hardware_disable(void)
3574 {
3575         vmclear_local_loaded_vmcss();
3576         kvm_cpu_vmxoff();
3577 }
3578
3579 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3580                                       u32 msr, u32 *result)
3581 {
3582         u32 vmx_msr_low, vmx_msr_high;
3583         u32 ctl = ctl_min | ctl_opt;
3584
3585         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3586
3587         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3588         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3589
3590         /* Ensure minimum (required) set of control bits are supported. */
3591         if (ctl_min & ~ctl)
3592                 return -EIO;
3593
3594         *result = ctl;
3595         return 0;
3596 }
3597
3598 static __init bool allow_1_setting(u32 msr, u32 ctl)
3599 {
3600         u32 vmx_msr_low, vmx_msr_high;
3601
3602         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3603         return vmx_msr_high & ctl;
3604 }
3605
3606 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3607 {
3608         u32 vmx_msr_low, vmx_msr_high;
3609         u32 min, opt, min2, opt2;
3610         u32 _pin_based_exec_control = 0;
3611         u32 _cpu_based_exec_control = 0;
3612         u32 _cpu_based_2nd_exec_control = 0;
3613         u32 _vmexit_control = 0;
3614         u32 _vmentry_control = 0;
3615
3616         min = CPU_BASED_HLT_EXITING |
3617 #ifdef CONFIG_X86_64
3618               CPU_BASED_CR8_LOAD_EXITING |
3619               CPU_BASED_CR8_STORE_EXITING |
3620 #endif
3621               CPU_BASED_CR3_LOAD_EXITING |
3622               CPU_BASED_CR3_STORE_EXITING |
3623               CPU_BASED_USE_IO_BITMAPS |
3624               CPU_BASED_MOV_DR_EXITING |
3625               CPU_BASED_USE_TSC_OFFSETING |
3626               CPU_BASED_INVLPG_EXITING |
3627               CPU_BASED_RDPMC_EXITING;
3628
3629         if (!kvm_mwait_in_guest())
3630                 min |= CPU_BASED_MWAIT_EXITING |
3631                         CPU_BASED_MONITOR_EXITING;
3632
3633         opt = CPU_BASED_TPR_SHADOW |
3634               CPU_BASED_USE_MSR_BITMAPS |
3635               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3636         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3637                                 &_cpu_based_exec_control) < 0)
3638                 return -EIO;
3639 #ifdef CONFIG_X86_64
3640         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3641                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3642                                            ~CPU_BASED_CR8_STORE_EXITING;
3643 #endif
3644         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3645                 min2 = 0;
3646                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3647                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3648                         SECONDARY_EXEC_WBINVD_EXITING |
3649                         SECONDARY_EXEC_ENABLE_VPID |
3650                         SECONDARY_EXEC_ENABLE_EPT |
3651                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3652                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3653                         SECONDARY_EXEC_RDTSCP |
3654                         SECONDARY_EXEC_ENABLE_INVPCID |
3655                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3656                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3657                         SECONDARY_EXEC_SHADOW_VMCS |
3658                         SECONDARY_EXEC_XSAVES |
3659                         SECONDARY_EXEC_RDSEED |
3660                         SECONDARY_EXEC_RDRAND |
3661                         SECONDARY_EXEC_ENABLE_PML |
3662                         SECONDARY_EXEC_TSC_SCALING |
3663                         SECONDARY_EXEC_ENABLE_VMFUNC;
3664                 if (adjust_vmx_controls(min2, opt2,
3665                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3666                                         &_cpu_based_2nd_exec_control) < 0)
3667                         return -EIO;
3668         }
3669 #ifndef CONFIG_X86_64
3670         if (!(_cpu_based_2nd_exec_control &
3671                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3672                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3673 #endif
3674
3675         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3676                 _cpu_based_2nd_exec_control &= ~(
3677                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3678                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3679                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3680
3681         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3682                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3683                    enabled */
3684                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3685                                              CPU_BASED_CR3_STORE_EXITING |
3686                                              CPU_BASED_INVLPG_EXITING);
3687                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3688                       vmx_capability.ept, vmx_capability.vpid);
3689         }
3690
3691         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3692 #ifdef CONFIG_X86_64
3693         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3694 #endif
3695         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3696                 VM_EXIT_CLEAR_BNDCFGS;
3697         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3698                                 &_vmexit_control) < 0)
3699                 return -EIO;
3700
3701         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3702                 PIN_BASED_VIRTUAL_NMIS;
3703         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3704         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3705                                 &_pin_based_exec_control) < 0)
3706                 return -EIO;
3707
3708         if (cpu_has_broken_vmx_preemption_timer())
3709                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3710         if (!(_cpu_based_2nd_exec_control &
3711                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3712                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3713
3714         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3715         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3716         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3717                                 &_vmentry_control) < 0)
3718                 return -EIO;
3719
3720         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3721
3722         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3723         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3724                 return -EIO;
3725
3726 #ifdef CONFIG_X86_64
3727         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3728         if (vmx_msr_high & (1u<<16))
3729                 return -EIO;
3730 #endif
3731
3732         /* Require Write-Back (WB) memory type for VMCS accesses. */
3733         if (((vmx_msr_high >> 18) & 15) != 6)
3734                 return -EIO;
3735
3736         vmcs_conf->size = vmx_msr_high & 0x1fff;
3737         vmcs_conf->order = get_order(vmcs_conf->size);
3738         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3739         vmcs_conf->revision_id = vmx_msr_low;
3740
3741         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3742         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3743         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3744         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3745         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3746
3747         cpu_has_load_ia32_efer =
3748                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3749                                 VM_ENTRY_LOAD_IA32_EFER)
3750                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3751                                    VM_EXIT_LOAD_IA32_EFER);
3752
3753         cpu_has_load_perf_global_ctrl =
3754                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3755                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3756                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3757                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3758
3759         /*
3760          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3761          * but due to errata below it can't be used. Workaround is to use
3762          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3763          *
3764          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3765          *
3766          * AAK155             (model 26)
3767          * AAP115             (model 30)
3768          * AAT100             (model 37)
3769          * BC86,AAY89,BD102   (model 44)
3770          * BA97               (model 46)
3771          *
3772          */
3773         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3774                 switch (boot_cpu_data.x86_model) {
3775                 case 26:
3776                 case 30:
3777                 case 37:
3778                 case 44:
3779                 case 46:
3780                         cpu_has_load_perf_global_ctrl = false;
3781                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3782                                         "does not work properly. Using workaround\n");
3783                         break;
3784                 default:
3785                         break;
3786                 }
3787         }
3788
3789         if (boot_cpu_has(X86_FEATURE_XSAVES))
3790                 rdmsrl(MSR_IA32_XSS, host_xss);
3791
3792         return 0;
3793 }
3794
3795 static struct vmcs *alloc_vmcs_cpu(int cpu)
3796 {
3797         int node = cpu_to_node(cpu);
3798         struct page *pages;
3799         struct vmcs *vmcs;
3800
3801         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3802         if (!pages)
3803                 return NULL;
3804         vmcs = page_address(pages);
3805         memset(vmcs, 0, vmcs_config.size);
3806         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3807         return vmcs;
3808 }
3809
3810 static struct vmcs *alloc_vmcs(void)
3811 {
3812         return alloc_vmcs_cpu(raw_smp_processor_id());
3813 }
3814
3815 static void free_vmcs(struct vmcs *vmcs)
3816 {
3817         free_pages((unsigned long)vmcs, vmcs_config.order);
3818 }
3819
3820 /*
3821  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3822  */
3823 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3824 {
3825         if (!loaded_vmcs->vmcs)
3826                 return;
3827         loaded_vmcs_clear(loaded_vmcs);
3828         free_vmcs(loaded_vmcs->vmcs);
3829         loaded_vmcs->vmcs = NULL;
3830         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3831 }
3832
3833 static void free_kvm_area(void)
3834 {
3835         int cpu;
3836
3837         for_each_possible_cpu(cpu) {
3838                 free_vmcs(per_cpu(vmxarea, cpu));
3839                 per_cpu(vmxarea, cpu) = NULL;
3840         }
3841 }
3842
3843 enum vmcs_field_type {
3844         VMCS_FIELD_TYPE_U16 = 0,
3845         VMCS_FIELD_TYPE_U64 = 1,
3846         VMCS_FIELD_TYPE_U32 = 2,
3847         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3848 };
3849
3850 static inline int vmcs_field_type(unsigned long field)
3851 {
3852         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3853                 return VMCS_FIELD_TYPE_U32;
3854         return (field >> 13) & 0x3 ;
3855 }
3856
3857 static inline int vmcs_field_readonly(unsigned long field)
3858 {
3859         return (((field >> 10) & 0x3) == 1);
3860 }
3861
3862 static void init_vmcs_shadow_fields(void)
3863 {
3864         int i, j;
3865
3866         /* No checks for read only fields yet */
3867
3868         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3869                 switch (shadow_read_write_fields[i]) {
3870                 case GUEST_BNDCFGS:
3871                         if (!kvm_mpx_supported())
3872                                 continue;
3873                         break;
3874                 default:
3875                         break;
3876                 }
3877
3878                 if (j < i)
3879                         shadow_read_write_fields[j] =
3880                                 shadow_read_write_fields[i];
3881                 j++;
3882         }
3883         max_shadow_read_write_fields = j;
3884
3885         /* shadowed fields guest access without vmexit */
3886         for (i = 0; i < max_shadow_read_write_fields; i++) {
3887                 unsigned long field = shadow_read_write_fields[i];
3888
3889                 clear_bit(field, vmx_vmwrite_bitmap);
3890                 clear_bit(field, vmx_vmread_bitmap);
3891                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3892                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3893                         clear_bit(field + 1, vmx_vmread_bitmap);
3894                 }
3895         }
3896         for (i = 0; i < max_shadow_read_only_fields; i++) {
3897                 unsigned long field = shadow_read_only_fields[i];
3898
3899                 clear_bit(field, vmx_vmread_bitmap);
3900                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3901                         clear_bit(field + 1, vmx_vmread_bitmap);
3902         }
3903 }
3904
3905 static __init int alloc_kvm_area(void)
3906 {
3907         int cpu;
3908
3909         for_each_possible_cpu(cpu) {
3910                 struct vmcs *vmcs;
3911
3912                 vmcs = alloc_vmcs_cpu(cpu);
3913                 if (!vmcs) {
3914                         free_kvm_area();
3915                         return -ENOMEM;
3916                 }
3917
3918                 per_cpu(vmxarea, cpu) = vmcs;
3919         }
3920         return 0;
3921 }
3922
3923 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3924                 struct kvm_segment *save)
3925 {
3926         if (!emulate_invalid_guest_state) {
3927                 /*
3928                  * CS and SS RPL should be equal during guest entry according
3929                  * to VMX spec, but in reality it is not always so. Since vcpu
3930                  * is in the middle of the transition from real mode to
3931                  * protected mode it is safe to assume that RPL 0 is a good
3932                  * default value.
3933                  */
3934                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3935                         save->selector &= ~SEGMENT_RPL_MASK;
3936                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3937                 save->s = 1;
3938         }
3939         vmx_set_segment(vcpu, save, seg);
3940 }
3941
3942 static void enter_pmode(struct kvm_vcpu *vcpu)
3943 {
3944         unsigned long flags;
3945         struct vcpu_vmx *vmx = to_vmx(vcpu);
3946
3947         /*
3948          * Update real mode segment cache. It may be not up-to-date if sement
3949          * register was written while vcpu was in a guest mode.
3950          */
3951         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3952         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3953         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3954         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3955         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3956         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3957
3958         vmx->rmode.vm86_active = 0;
3959
3960         vmx_segment_cache_clear(vmx);
3961
3962         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3963
3964         flags = vmcs_readl(GUEST_RFLAGS);
3965         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3966         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3967         vmcs_writel(GUEST_RFLAGS, flags);
3968
3969         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3970                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3971
3972         update_exception_bitmap(vcpu);
3973
3974         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3975         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3976         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3977         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3978         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3979         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3980 }
3981
3982 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3983 {
3984         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3985         struct kvm_segment var = *save;
3986
3987         var.dpl = 0x3;
3988         if (seg == VCPU_SREG_CS)
3989                 var.type = 0x3;
3990
3991         if (!emulate_invalid_guest_state) {
3992                 var.selector = var.base >> 4;
3993                 var.base = var.base & 0xffff0;
3994                 var.limit = 0xffff;
3995                 var.g = 0;
3996                 var.db = 0;
3997                 var.present = 1;
3998                 var.s = 1;
3999                 var.l = 0;
4000                 var.unusable = 0;
4001                 var.type = 0x3;
4002                 var.avl = 0;
4003                 if (save->base & 0xf)
4004                         printk_once(KERN_WARNING "kvm: segment base is not "
4005                                         "paragraph aligned when entering "
4006                                         "protected mode (seg=%d)", seg);
4007         }
4008
4009         vmcs_write16(sf->selector, var.selector);
4010         vmcs_writel(sf->base, var.base);
4011         vmcs_write32(sf->limit, var.limit);
4012         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4013 }
4014
4015 static void enter_rmode(struct kvm_vcpu *vcpu)
4016 {
4017         unsigned long flags;
4018         struct vcpu_vmx *vmx = to_vmx(vcpu);
4019
4020         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4021         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4022         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4023         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4024         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4027
4028         vmx->rmode.vm86_active = 1;
4029
4030         /*
4031          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4032          * vcpu. Warn the user that an update is overdue.
4033          */
4034         if (!vcpu->kvm->arch.tss_addr)
4035                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4036                              "called before entering vcpu\n");
4037
4038         vmx_segment_cache_clear(vmx);
4039
4040         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4041         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4042         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4043
4044         flags = vmcs_readl(GUEST_RFLAGS);
4045         vmx->rmode.save_rflags = flags;
4046
4047         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4048
4049         vmcs_writel(GUEST_RFLAGS, flags);
4050         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4051         update_exception_bitmap(vcpu);
4052
4053         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4054         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4055         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4056         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4057         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4058         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4059
4060         kvm_mmu_reset_context(vcpu);
4061 }
4062
4063 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4064 {
4065         struct vcpu_vmx *vmx = to_vmx(vcpu);
4066         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4067
4068         if (!msr)
4069                 return;
4070
4071         /*
4072          * Force kernel_gs_base reloading before EFER changes, as control
4073          * of this msr depends on is_long_mode().
4074          */
4075         vmx_load_host_state(to_vmx(vcpu));
4076         vcpu->arch.efer = efer;
4077         if (efer & EFER_LMA) {
4078                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4079                 msr->data = efer;
4080         } else {
4081                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4082
4083                 msr->data = efer & ~EFER_LME;
4084         }
4085         setup_msrs(vmx);
4086 }
4087
4088 #ifdef CONFIG_X86_64
4089
4090 static void enter_lmode(struct kvm_vcpu *vcpu)
4091 {
4092         u32 guest_tr_ar;
4093
4094         vmx_segment_cache_clear(to_vmx(vcpu));
4095
4096         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4097         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4098                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4099                                      __func__);
4100                 vmcs_write32(GUEST_TR_AR_BYTES,
4101                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4102                              | VMX_AR_TYPE_BUSY_64_TSS);
4103         }
4104         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4105 }
4106
4107 static void exit_lmode(struct kvm_vcpu *vcpu)
4108 {
4109         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4110         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4111 }
4112
4113 #endif
4114
4115 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4116 {
4117         if (enable_ept) {
4118                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4119                         return;
4120                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4121         } else {
4122                 vpid_sync_context(vpid);
4123         }
4124 }
4125
4126 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4127 {
4128         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4129 }
4130
4131 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4132 {
4133         if (enable_ept)
4134                 vmx_flush_tlb(vcpu);
4135 }
4136
4137 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4138 {
4139         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4140
4141         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4142         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4143 }
4144
4145 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4146 {
4147         if (enable_ept && is_paging(vcpu))
4148                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4149         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4150 }
4151
4152 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4153 {
4154         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4155
4156         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4157         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4158 }
4159
4160 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4161 {
4162         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4163
4164         if (!test_bit(VCPU_EXREG_PDPTR,
4165                       (unsigned long *)&vcpu->arch.regs_dirty))
4166                 return;
4167
4168         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4169                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4170                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4171                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4172                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4173         }
4174 }
4175
4176 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4177 {
4178         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4179
4180         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4181                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4182                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4183                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4184                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4185         }
4186
4187         __set_bit(VCPU_EXREG_PDPTR,
4188                   (unsigned long *)&vcpu->arch.regs_avail);
4189         __set_bit(VCPU_EXREG_PDPTR,
4190                   (unsigned long *)&vcpu->arch.regs_dirty);
4191 }
4192
4193 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4194 {
4195         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4196         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4197         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4198
4199         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4200                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4201             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4202                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4203
4204         return fixed_bits_valid(val, fixed0, fixed1);
4205 }
4206
4207 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4208 {
4209         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4210         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4211
4212         return fixed_bits_valid(val, fixed0, fixed1);
4213 }
4214
4215 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4216 {
4217         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4218         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4219
4220         return fixed_bits_valid(val, fixed0, fixed1);
4221 }
4222
4223 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4224 #define nested_guest_cr4_valid  nested_cr4_valid
4225 #define nested_host_cr4_valid   nested_cr4_valid
4226
4227 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4228
4229 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4230                                         unsigned long cr0,
4231                                         struct kvm_vcpu *vcpu)
4232 {
4233         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4234                 vmx_decache_cr3(vcpu);
4235         if (!(cr0 & X86_CR0_PG)) {
4236                 /* From paging/starting to nonpaging */
4237                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4238                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4239                              (CPU_BASED_CR3_LOAD_EXITING |
4240                               CPU_BASED_CR3_STORE_EXITING));
4241                 vcpu->arch.cr0 = cr0;
4242                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4243         } else if (!is_paging(vcpu)) {
4244                 /* From nonpaging to paging */
4245                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4246                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4247                              ~(CPU_BASED_CR3_LOAD_EXITING |
4248                                CPU_BASED_CR3_STORE_EXITING));
4249                 vcpu->arch.cr0 = cr0;
4250                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4251         }
4252
4253         if (!(cr0 & X86_CR0_WP))
4254                 *hw_cr0 &= ~X86_CR0_WP;
4255 }
4256
4257 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4258 {
4259         struct vcpu_vmx *vmx = to_vmx(vcpu);
4260         unsigned long hw_cr0;
4261
4262         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4263         if (enable_unrestricted_guest)
4264                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4265         else {
4266                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4267
4268                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4269                         enter_pmode(vcpu);
4270
4271                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4272                         enter_rmode(vcpu);
4273         }
4274
4275 #ifdef CONFIG_X86_64
4276         if (vcpu->arch.efer & EFER_LME) {
4277                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4278                         enter_lmode(vcpu);
4279                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4280                         exit_lmode(vcpu);
4281         }
4282 #endif
4283
4284         if (enable_ept)
4285                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4286
4287         vmcs_writel(CR0_READ_SHADOW, cr0);
4288         vmcs_writel(GUEST_CR0, hw_cr0);
4289         vcpu->arch.cr0 = cr0;
4290
4291         /* depends on vcpu->arch.cr0 to be set to a new value */
4292         vmx->emulation_required = emulation_required(vcpu);
4293 }
4294
4295 static int get_ept_level(struct kvm_vcpu *vcpu)
4296 {
4297         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4298                 return 5;
4299         return 4;
4300 }
4301
4302 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4303 {
4304         u64 eptp = VMX_EPTP_MT_WB;
4305
4306         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4307
4308         if (enable_ept_ad_bits &&
4309             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4310                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4311         eptp |= (root_hpa & PAGE_MASK);
4312
4313         return eptp;
4314 }
4315
4316 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4317 {
4318         unsigned long guest_cr3;
4319         u64 eptp;
4320
4321         guest_cr3 = cr3;
4322         if (enable_ept) {
4323                 eptp = construct_eptp(vcpu, cr3);
4324                 vmcs_write64(EPT_POINTER, eptp);
4325                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4326                         guest_cr3 = kvm_read_cr3(vcpu);
4327                 else
4328                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4329                 ept_load_pdptrs(vcpu);
4330         }
4331
4332         vmx_flush_tlb(vcpu);
4333         vmcs_writel(GUEST_CR3, guest_cr3);
4334 }
4335
4336 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4337 {
4338         /*
4339          * Pass through host's Machine Check Enable value to hw_cr4, which
4340          * is in force while we are in guest mode.  Do not let guests control
4341          * this bit, even if host CR4.MCE == 0.
4342          */
4343         unsigned long hw_cr4 =
4344                 (cr4_read_shadow() & X86_CR4_MCE) |
4345                 (cr4 & ~X86_CR4_MCE) |
4346                 (to_vmx(vcpu)->rmode.vm86_active ?
4347                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4348
4349         if (cr4 & X86_CR4_VMXE) {
4350                 /*
4351                  * To use VMXON (and later other VMX instructions), a guest
4352                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4353                  * So basically the check on whether to allow nested VMX
4354                  * is here.
4355                  */
4356                 if (!nested_vmx_allowed(vcpu))
4357                         return 1;
4358         }
4359
4360         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4361                 return 1;
4362
4363         vcpu->arch.cr4 = cr4;
4364         if (enable_ept) {
4365                 if (!is_paging(vcpu)) {
4366                         hw_cr4 &= ~X86_CR4_PAE;
4367                         hw_cr4 |= X86_CR4_PSE;
4368                 } else if (!(cr4 & X86_CR4_PAE)) {
4369                         hw_cr4 &= ~X86_CR4_PAE;
4370                 }
4371         }
4372
4373         if (!enable_unrestricted_guest && !is_paging(vcpu))
4374                 /*
4375                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4376                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4377                  * to be manually disabled when guest switches to non-paging
4378                  * mode.
4379                  *
4380                  * If !enable_unrestricted_guest, the CPU is always running
4381                  * with CR0.PG=1 and CR4 needs to be modified.
4382                  * If enable_unrestricted_guest, the CPU automatically
4383                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4384                  */
4385                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4386
4387         vmcs_writel(CR4_READ_SHADOW, cr4);
4388         vmcs_writel(GUEST_CR4, hw_cr4);
4389         return 0;
4390 }
4391
4392 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4393                             struct kvm_segment *var, int seg)
4394 {
4395         struct vcpu_vmx *vmx = to_vmx(vcpu);
4396         u32 ar;
4397
4398         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4399                 *var = vmx->rmode.segs[seg];
4400                 if (seg == VCPU_SREG_TR
4401                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4402                         return;
4403                 var->base = vmx_read_guest_seg_base(vmx, seg);
4404                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4405                 return;
4406         }
4407         var->base = vmx_read_guest_seg_base(vmx, seg);
4408         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4409         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4410         ar = vmx_read_guest_seg_ar(vmx, seg);
4411         var->unusable = (ar >> 16) & 1;
4412         var->type = ar & 15;
4413         var->s = (ar >> 4) & 1;
4414         var->dpl = (ar >> 5) & 3;
4415         /*
4416          * Some userspaces do not preserve unusable property. Since usable
4417          * segment has to be present according to VMX spec we can use present
4418          * property to amend userspace bug by making unusable segment always
4419          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4420          * segment as unusable.
4421          */
4422         var->present = !var->unusable;
4423         var->avl = (ar >> 12) & 1;
4424         var->l = (ar >> 13) & 1;
4425         var->db = (ar >> 14) & 1;
4426         var->g = (ar >> 15) & 1;
4427 }
4428
4429 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4430 {
4431         struct kvm_segment s;
4432
4433         if (to_vmx(vcpu)->rmode.vm86_active) {
4434                 vmx_get_segment(vcpu, &s, seg);
4435                 return s.base;
4436         }
4437         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4438 }
4439
4440 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4441 {
4442         struct vcpu_vmx *vmx = to_vmx(vcpu);
4443
4444         if (unlikely(vmx->rmode.vm86_active))
4445                 return 0;
4446         else {
4447                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4448                 return VMX_AR_DPL(ar);
4449         }
4450 }
4451
4452 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4453 {
4454         u32 ar;
4455
4456         if (var->unusable || !var->present)
4457                 ar = 1 << 16;
4458         else {
4459                 ar = var->type & 15;
4460                 ar |= (var->s & 1) << 4;
4461                 ar |= (var->dpl & 3) << 5;
4462                 ar |= (var->present & 1) << 7;
4463                 ar |= (var->avl & 1) << 12;
4464                 ar |= (var->l & 1) << 13;
4465                 ar |= (var->db & 1) << 14;
4466                 ar |= (var->g & 1) << 15;
4467         }
4468
4469         return ar;
4470 }
4471
4472 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4473                             struct kvm_segment *var, int seg)
4474 {
4475         struct vcpu_vmx *vmx = to_vmx(vcpu);
4476         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4477
4478         vmx_segment_cache_clear(vmx);
4479
4480         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4481                 vmx->rmode.segs[seg] = *var;
4482                 if (seg == VCPU_SREG_TR)
4483                         vmcs_write16(sf->selector, var->selector);
4484                 else if (var->s)
4485                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4486                 goto out;
4487         }
4488
4489         vmcs_writel(sf->base, var->base);
4490         vmcs_write32(sf->limit, var->limit);
4491         vmcs_write16(sf->selector, var->selector);
4492
4493         /*
4494          *   Fix the "Accessed" bit in AR field of segment registers for older
4495          * qemu binaries.
4496          *   IA32 arch specifies that at the time of processor reset the
4497          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4498          * is setting it to 0 in the userland code. This causes invalid guest
4499          * state vmexit when "unrestricted guest" mode is turned on.
4500          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4501          * tree. Newer qemu binaries with that qemu fix would not need this
4502          * kvm hack.
4503          */
4504         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4505                 var->type |= 0x1; /* Accessed */
4506
4507         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4508
4509 out:
4510         vmx->emulation_required = emulation_required(vcpu);
4511 }
4512
4513 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4514 {
4515         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4516
4517         *db = (ar >> 14) & 1;
4518         *l = (ar >> 13) & 1;
4519 }
4520
4521 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4522 {
4523         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4524         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4525 }
4526
4527 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4528 {
4529         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4530         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4531 }
4532
4533 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4534 {
4535         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4536         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4537 }
4538
4539 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4540 {
4541         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4542         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4543 }
4544
4545 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4546 {
4547         struct kvm_segment var;
4548         u32 ar;
4549
4550         vmx_get_segment(vcpu, &var, seg);
4551         var.dpl = 0x3;
4552         if (seg == VCPU_SREG_CS)
4553                 var.type = 0x3;
4554         ar = vmx_segment_access_rights(&var);
4555
4556         if (var.base != (var.selector << 4))
4557                 return false;
4558         if (var.limit != 0xffff)
4559                 return false;
4560         if (ar != 0xf3)
4561                 return false;
4562
4563         return true;
4564 }
4565
4566 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4567 {
4568         struct kvm_segment cs;
4569         unsigned int cs_rpl;
4570
4571         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4572         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4573
4574         if (cs.unusable)
4575                 return false;
4576         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4577                 return false;
4578         if (!cs.s)
4579                 return false;
4580         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4581                 if (cs.dpl > cs_rpl)
4582                         return false;
4583         } else {
4584                 if (cs.dpl != cs_rpl)
4585                         return false;
4586         }
4587         if (!cs.present)
4588                 return false;
4589
4590         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4591         return true;
4592 }
4593
4594 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4595 {
4596         struct kvm_segment ss;
4597         unsigned int ss_rpl;
4598
4599         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4600         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4601
4602         if (ss.unusable)
4603                 return true;
4604         if (ss.type != 3 && ss.type != 7)
4605                 return false;
4606         if (!ss.s)
4607                 return false;
4608         if (ss.dpl != ss_rpl) /* DPL != RPL */
4609                 return false;
4610         if (!ss.present)
4611                 return false;
4612
4613         return true;
4614 }
4615
4616 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4617 {
4618         struct kvm_segment var;
4619         unsigned int rpl;
4620
4621         vmx_get_segment(vcpu, &var, seg);
4622         rpl = var.selector & SEGMENT_RPL_MASK;
4623
4624         if (var.unusable)
4625                 return true;
4626         if (!var.s)
4627                 return false;
4628         if (!var.present)
4629                 return false;
4630         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4631                 if (var.dpl < rpl) /* DPL < RPL */
4632                         return false;
4633         }
4634
4635         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4636          * rights flags
4637          */
4638         return true;
4639 }
4640
4641 static bool tr_valid(struct kvm_vcpu *vcpu)
4642 {
4643         struct kvm_segment tr;
4644
4645         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4646
4647         if (tr.unusable)
4648                 return false;
4649         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4650                 return false;
4651         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4652                 return false;
4653         if (!tr.present)
4654                 return false;
4655
4656         return true;
4657 }
4658
4659 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4660 {
4661         struct kvm_segment ldtr;
4662
4663         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4664
4665         if (ldtr.unusable)
4666                 return true;
4667         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4668                 return false;
4669         if (ldtr.type != 2)
4670                 return false;
4671         if (!ldtr.present)
4672                 return false;
4673
4674         return true;
4675 }
4676
4677 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4678 {
4679         struct kvm_segment cs, ss;
4680
4681         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4682         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4683
4684         return ((cs.selector & SEGMENT_RPL_MASK) ==
4685                  (ss.selector & SEGMENT_RPL_MASK));
4686 }
4687
4688 /*
4689  * Check if guest state is valid. Returns true if valid, false if
4690  * not.
4691  * We assume that registers are always usable
4692  */
4693 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4694 {
4695         if (enable_unrestricted_guest)
4696                 return true;
4697
4698         /* real mode guest state checks */
4699         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4700                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4701                         return false;
4702                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4703                         return false;
4704                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4705                         return false;
4706                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4707                         return false;
4708                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4709                         return false;
4710                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4711                         return false;
4712         } else {
4713         /* protected mode guest state checks */
4714                 if (!cs_ss_rpl_check(vcpu))
4715                         return false;
4716                 if (!code_segment_valid(vcpu))
4717                         return false;
4718                 if (!stack_segment_valid(vcpu))
4719                         return false;
4720                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4721                         return false;
4722                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4723                         return false;
4724                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4725                         return false;
4726                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4727                         return false;
4728                 if (!tr_valid(vcpu))
4729                         return false;
4730                 if (!ldtr_valid(vcpu))
4731                         return false;
4732         }
4733         /* TODO:
4734          * - Add checks on RIP
4735          * - Add checks on RFLAGS
4736          */
4737
4738         return true;
4739 }
4740
4741 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4742 {
4743         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4744 }
4745
4746 static int init_rmode_tss(struct kvm *kvm)
4747 {
4748         gfn_t fn;
4749         u16 data = 0;
4750         int idx, r;
4751
4752         idx = srcu_read_lock(&kvm->srcu);
4753         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4754         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4755         if (r < 0)
4756                 goto out;
4757         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4758         r = kvm_write_guest_page(kvm, fn++, &data,
4759                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4760         if (r < 0)
4761                 goto out;
4762         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4763         if (r < 0)
4764                 goto out;
4765         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4766         if (r < 0)
4767                 goto out;
4768         data = ~0;
4769         r = kvm_write_guest_page(kvm, fn, &data,
4770                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4771                                  sizeof(u8));
4772 out:
4773         srcu_read_unlock(&kvm->srcu, idx);
4774         return r;
4775 }
4776
4777 static int init_rmode_identity_map(struct kvm *kvm)
4778 {
4779         int i, idx, r = 0;
4780         kvm_pfn_t identity_map_pfn;
4781         u32 tmp;
4782
4783         if (!enable_ept)
4784                 return 0;
4785
4786         /* Protect kvm->arch.ept_identity_pagetable_done. */
4787         mutex_lock(&kvm->slots_lock);
4788
4789         if (likely(kvm->arch.ept_identity_pagetable_done))
4790                 goto out2;
4791
4792         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4793
4794         r = alloc_identity_pagetable(kvm);
4795         if (r < 0)
4796                 goto out2;
4797
4798         idx = srcu_read_lock(&kvm->srcu);
4799         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4800         if (r < 0)
4801                 goto out;
4802         /* Set up identity-mapping pagetable for EPT in real mode */
4803         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4804                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4805                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4806                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4807                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4808                 if (r < 0)
4809                         goto out;
4810         }
4811         kvm->arch.ept_identity_pagetable_done = true;
4812
4813 out:
4814         srcu_read_unlock(&kvm->srcu, idx);
4815
4816 out2:
4817         mutex_unlock(&kvm->slots_lock);
4818         return r;
4819 }
4820
4821 static void seg_setup(int seg)
4822 {
4823         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4824         unsigned int ar;
4825
4826         vmcs_write16(sf->selector, 0);
4827         vmcs_writel(sf->base, 0);
4828         vmcs_write32(sf->limit, 0xffff);
4829         ar = 0x93;
4830         if (seg == VCPU_SREG_CS)
4831                 ar |= 0x08; /* code segment */
4832
4833         vmcs_write32(sf->ar_bytes, ar);
4834 }
4835
4836 static int alloc_apic_access_page(struct kvm *kvm)
4837 {
4838         struct page *page;
4839         int r = 0;
4840
4841         mutex_lock(&kvm->slots_lock);
4842         if (kvm->arch.apic_access_page_done)
4843                 goto out;
4844         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4845                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4846         if (r)
4847                 goto out;
4848
4849         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4850         if (is_error_page(page)) {
4851                 r = -EFAULT;
4852                 goto out;
4853         }
4854
4855         /*
4856          * Do not pin the page in memory, so that memory hot-unplug
4857          * is able to migrate it.
4858          */
4859         put_page(page);
4860         kvm->arch.apic_access_page_done = true;
4861 out:
4862         mutex_unlock(&kvm->slots_lock);
4863         return r;
4864 }
4865
4866 static int alloc_identity_pagetable(struct kvm *kvm)
4867 {
4868         /* Called with kvm->slots_lock held. */
4869
4870         int r = 0;
4871
4872         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4873
4874         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4875                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4876
4877         return r;
4878 }
4879
4880 static int allocate_vpid(void)
4881 {
4882         int vpid;
4883
4884         if (!enable_vpid)
4885                 return 0;
4886         spin_lock(&vmx_vpid_lock);
4887         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4888         if (vpid < VMX_NR_VPIDS)
4889                 __set_bit(vpid, vmx_vpid_bitmap);
4890         else
4891                 vpid = 0;
4892         spin_unlock(&vmx_vpid_lock);
4893         return vpid;
4894 }
4895
4896 static void free_vpid(int vpid)
4897 {
4898         if (!enable_vpid || vpid == 0)
4899                 return;
4900         spin_lock(&vmx_vpid_lock);
4901         __clear_bit(vpid, vmx_vpid_bitmap);
4902         spin_unlock(&vmx_vpid_lock);
4903 }
4904
4905 #define MSR_TYPE_R      1
4906 #define MSR_TYPE_W      2
4907 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4908                                                 u32 msr, int type)
4909 {
4910         int f = sizeof(unsigned long);
4911
4912         if (!cpu_has_vmx_msr_bitmap())
4913                 return;
4914
4915         /*
4916          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4917          * have the write-low and read-high bitmap offsets the wrong way round.
4918          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4919          */
4920         if (msr <= 0x1fff) {
4921                 if (type & MSR_TYPE_R)
4922                         /* read-low */
4923                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4924
4925                 if (type & MSR_TYPE_W)
4926                         /* write-low */
4927                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4928
4929         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4930                 msr &= 0x1fff;
4931                 if (type & MSR_TYPE_R)
4932                         /* read-high */
4933                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4934
4935                 if (type & MSR_TYPE_W)
4936                         /* write-high */
4937                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4938
4939         }
4940 }
4941
4942 /*
4943  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4944  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4945  */
4946 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4947                                                unsigned long *msr_bitmap_nested,
4948                                                u32 msr, int type)
4949 {
4950         int f = sizeof(unsigned long);
4951
4952         if (!cpu_has_vmx_msr_bitmap()) {
4953                 WARN_ON(1);
4954                 return;
4955         }
4956
4957         /*
4958          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4959          * have the write-low and read-high bitmap offsets the wrong way round.
4960          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4961          */
4962         if (msr <= 0x1fff) {
4963                 if (type & MSR_TYPE_R &&
4964                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4965                         /* read-low */
4966                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4967
4968                 if (type & MSR_TYPE_W &&
4969                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4970                         /* write-low */
4971                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4972
4973         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4974                 msr &= 0x1fff;
4975                 if (type & MSR_TYPE_R &&
4976                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4977                         /* read-high */
4978                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4979
4980                 if (type & MSR_TYPE_W &&
4981                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4982                         /* write-high */
4983                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4984
4985         }
4986 }
4987
4988 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4989 {
4990         if (!longmode_only)
4991                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4992                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4993         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4994                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4995 }
4996
4997 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4998 {
4999         if (apicv_active) {
5000                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
5001                                 msr, type);
5002                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
5003                                 msr, type);
5004         } else {
5005                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
5006                                 msr, type);
5007                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
5008                                 msr, type);
5009         }
5010 }
5011
5012 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5013 {
5014         return enable_apicv;
5015 }
5016
5017 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5018 {
5019         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5020         gfn_t gfn;
5021
5022         /*
5023          * Don't need to mark the APIC access page dirty; it is never
5024          * written to by the CPU during APIC virtualization.
5025          */
5026
5027         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5028                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5029                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5030         }
5031
5032         if (nested_cpu_has_posted_intr(vmcs12)) {
5033                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5034                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5035         }
5036 }
5037
5038
5039 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5040 {
5041         struct vcpu_vmx *vmx = to_vmx(vcpu);
5042         int max_irr;
5043         void *vapic_page;
5044         u16 status;
5045
5046         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5047                 return;
5048
5049         vmx->nested.pi_pending = false;
5050         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5051                 return;
5052
5053         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5054         if (max_irr != 256) {
5055                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5056                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5057                 kunmap(vmx->nested.virtual_apic_page);
5058
5059                 status = vmcs_read16(GUEST_INTR_STATUS);
5060                 if ((u8)max_irr > ((u8)status & 0xff)) {
5061                         status &= ~0xff;
5062                         status |= (u8)max_irr;
5063                         vmcs_write16(GUEST_INTR_STATUS, status);
5064                 }
5065         }
5066
5067         nested_mark_vmcs12_pages_dirty(vcpu);
5068 }
5069
5070 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5071                                                      bool nested)
5072 {
5073 #ifdef CONFIG_SMP
5074         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5075
5076         if (vcpu->mode == IN_GUEST_MODE) {
5077                 /*
5078                  * The vector of interrupt to be delivered to vcpu had
5079                  * been set in PIR before this function.
5080                  *
5081                  * Following cases will be reached in this block, and
5082                  * we always send a notification event in all cases as
5083                  * explained below.
5084                  *
5085                  * Case 1: vcpu keeps in non-root mode. Sending a
5086                  * notification event posts the interrupt to vcpu.
5087                  *
5088                  * Case 2: vcpu exits to root mode and is still
5089                  * runnable. PIR will be synced to vIRR before the
5090                  * next vcpu entry. Sending a notification event in
5091                  * this case has no effect, as vcpu is not in root
5092                  * mode.
5093                  *
5094                  * Case 3: vcpu exits to root mode and is blocked.
5095                  * vcpu_block() has already synced PIR to vIRR and
5096                  * never blocks vcpu if vIRR is not cleared. Therefore,
5097                  * a blocked vcpu here does not wait for any requested
5098                  * interrupts in PIR, and sending a notification event
5099                  * which has no effect is safe here.
5100                  */
5101
5102                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5103                 return true;
5104         }
5105 #endif
5106         return false;
5107 }
5108
5109 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5110                                                 int vector)
5111 {
5112         struct vcpu_vmx *vmx = to_vmx(vcpu);
5113
5114         if (is_guest_mode(vcpu) &&
5115             vector == vmx->nested.posted_intr_nv) {
5116                 /* the PIR and ON have been set by L1. */
5117                 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5118                 /*
5119                  * If a posted intr is not recognized by hardware,
5120                  * we will accomplish it in the next vmentry.
5121                  */
5122                 vmx->nested.pi_pending = true;
5123                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5124                 return 0;
5125         }
5126         return -1;
5127 }
5128 /*
5129  * Send interrupt to vcpu via posted interrupt way.
5130  * 1. If target vcpu is running(non-root mode), send posted interrupt
5131  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5132  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5133  * interrupt from PIR in next vmentry.
5134  */
5135 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5136 {
5137         struct vcpu_vmx *vmx = to_vmx(vcpu);
5138         int r;
5139
5140         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5141         if (!r)
5142                 return;
5143
5144         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5145                 return;
5146
5147         /* If a previous notification has sent the IPI, nothing to do.  */
5148         if (pi_test_and_set_on(&vmx->pi_desc))
5149                 return;
5150
5151         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5152                 kvm_vcpu_kick(vcpu);
5153 }
5154
5155 /*
5156  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5157  * will not change in the lifetime of the guest.
5158  * Note that host-state that does change is set elsewhere. E.g., host-state
5159  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5160  */
5161 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5162 {
5163         u32 low32, high32;
5164         unsigned long tmpl;
5165         struct desc_ptr dt;
5166         unsigned long cr0, cr3, cr4;
5167
5168         cr0 = read_cr0();
5169         WARN_ON(cr0 & X86_CR0_TS);
5170         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5171
5172         /*
5173          * Save the most likely value for this task's CR3 in the VMCS.
5174          * We can't use __get_current_cr3_fast() because we're not atomic.
5175          */
5176         cr3 = __read_cr3();
5177         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5178         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5179
5180         /* Save the most likely value for this task's CR4 in the VMCS. */
5181         cr4 = cr4_read_shadow();
5182         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5183         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5184
5185         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5186 #ifdef CONFIG_X86_64
5187         /*
5188          * Load null selectors, so we can avoid reloading them in
5189          * __vmx_load_host_state(), in case userspace uses the null selectors
5190          * too (the expected case).
5191          */
5192         vmcs_write16(HOST_DS_SELECTOR, 0);
5193         vmcs_write16(HOST_ES_SELECTOR, 0);
5194 #else
5195         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5196         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5197 #endif
5198         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5199         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5200
5201         store_idt(&dt);
5202         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5203         vmx->host_idt_base = dt.address;
5204
5205         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5206
5207         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5208         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5209         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5210         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5211
5212         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5213                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5214                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5215         }
5216 }
5217
5218 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5219 {
5220         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5221         if (enable_ept)
5222                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5223         if (is_guest_mode(&vmx->vcpu))
5224                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5225                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5226         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5227 }
5228
5229 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5230 {
5231         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5232
5233         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5234                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5235         /* Enable the preemption timer dynamically */
5236         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5237         return pin_based_exec_ctrl;
5238 }
5239
5240 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5241 {
5242         struct vcpu_vmx *vmx = to_vmx(vcpu);
5243
5244         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5245         if (cpu_has_secondary_exec_ctrls()) {
5246                 if (kvm_vcpu_apicv_active(vcpu))
5247                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5248                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5249                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5250                 else
5251                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5252                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5253                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5254         }
5255
5256         if (cpu_has_vmx_msr_bitmap())
5257                 vmx_set_msr_bitmap(vcpu);
5258 }
5259
5260 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5261 {
5262         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5263
5264         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5265                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5266
5267         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5268                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5269 #ifdef CONFIG_X86_64
5270                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5271                                 CPU_BASED_CR8_LOAD_EXITING;
5272 #endif
5273         }
5274         if (!enable_ept)
5275                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5276                                 CPU_BASED_CR3_LOAD_EXITING  |
5277                                 CPU_BASED_INVLPG_EXITING;
5278         return exec_control;
5279 }
5280
5281 static bool vmx_rdrand_supported(void)
5282 {
5283         return vmcs_config.cpu_based_2nd_exec_ctrl &
5284                 SECONDARY_EXEC_RDRAND;
5285 }
5286
5287 static bool vmx_rdseed_supported(void)
5288 {
5289         return vmcs_config.cpu_based_2nd_exec_ctrl &
5290                 SECONDARY_EXEC_RDSEED;
5291 }
5292
5293 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5294 {
5295         struct kvm_vcpu *vcpu = &vmx->vcpu;
5296
5297         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5298         if (!cpu_need_virtualize_apic_accesses(vcpu))
5299                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5300         if (vmx->vpid == 0)
5301                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5302         if (!enable_ept) {
5303                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5304                 enable_unrestricted_guest = 0;
5305                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5306                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5307         }
5308         if (!enable_unrestricted_guest)
5309                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5310         if (!ple_gap)
5311                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5312         if (!kvm_vcpu_apicv_active(vcpu))
5313                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5314                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5315         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5316         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5317            (handle_vmptrld).
5318            We can NOT enable shadow_vmcs here because we don't have yet
5319            a current VMCS12
5320         */
5321         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5322
5323         if (!enable_pml)
5324                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5325
5326         if (vmx_xsaves_supported()) {
5327                 /* Exposing XSAVES only when XSAVE is exposed */
5328                 bool xsaves_enabled =
5329                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5330                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5331
5332                 if (!xsaves_enabled)
5333                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5334
5335                 if (nested) {
5336                         if (xsaves_enabled)
5337                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5338                                         SECONDARY_EXEC_XSAVES;
5339                         else
5340                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5341                                         ~SECONDARY_EXEC_XSAVES;
5342                 }
5343         }
5344
5345         if (vmx_rdtscp_supported()) {
5346                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5347                 if (!rdtscp_enabled)
5348                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5349
5350                 if (nested) {
5351                         if (rdtscp_enabled)
5352                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5353                                         SECONDARY_EXEC_RDTSCP;
5354                         else
5355                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5356                                         ~SECONDARY_EXEC_RDTSCP;
5357                 }
5358         }
5359
5360         if (vmx_invpcid_supported()) {
5361                 /* Exposing INVPCID only when PCID is exposed */
5362                 bool invpcid_enabled =
5363                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5364                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5365
5366                 if (!invpcid_enabled) {
5367                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5368                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5369                 }
5370
5371                 if (nested) {
5372                         if (invpcid_enabled)
5373                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5374                                         SECONDARY_EXEC_ENABLE_INVPCID;
5375                         else
5376                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5377                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5378                 }
5379         }
5380
5381         if (vmx_rdrand_supported()) {
5382                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5383                 if (rdrand_enabled)
5384                         exec_control &= ~SECONDARY_EXEC_RDRAND;
5385
5386                 if (nested) {
5387                         if (rdrand_enabled)
5388                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5389                                         SECONDARY_EXEC_RDRAND;
5390                         else
5391                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5392                                         ~SECONDARY_EXEC_RDRAND;
5393                 }
5394         }
5395
5396         if (vmx_rdseed_supported()) {
5397                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5398                 if (rdseed_enabled)
5399                         exec_control &= ~SECONDARY_EXEC_RDSEED;
5400
5401                 if (nested) {
5402                         if (rdseed_enabled)
5403                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5404                                         SECONDARY_EXEC_RDSEED;
5405                         else
5406                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5407                                         ~SECONDARY_EXEC_RDSEED;
5408                 }
5409         }
5410
5411         vmx->secondary_exec_control = exec_control;
5412 }
5413
5414 static void ept_set_mmio_spte_mask(void)
5415 {
5416         /*
5417          * EPT Misconfigurations can be generated if the value of bits 2:0
5418          * of an EPT paging-structure entry is 110b (write/execute).
5419          */
5420         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5421                                    VMX_EPT_MISCONFIG_WX_VALUE);
5422 }
5423
5424 #define VMX_XSS_EXIT_BITMAP 0
5425 /*
5426  * Sets up the vmcs for emulated real mode.
5427  */
5428 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
5429 {
5430 #ifdef CONFIG_X86_64
5431         unsigned long a;
5432 #endif
5433         int i;
5434
5435         /* I/O */
5436         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5437         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5438
5439         if (enable_shadow_vmcs) {
5440                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5441                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5442         }
5443         if (cpu_has_vmx_msr_bitmap())
5444                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5445
5446         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5447
5448         /* Control */
5449         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5450         vmx->hv_deadline_tsc = -1;
5451
5452         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5453
5454         if (cpu_has_secondary_exec_ctrls()) {
5455                 vmx_compute_secondary_exec_control(vmx);
5456                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5457                              vmx->secondary_exec_control);
5458         }
5459
5460         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5461                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5462                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5463                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5464                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5465
5466                 vmcs_write16(GUEST_INTR_STATUS, 0);
5467
5468                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5469                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5470         }
5471
5472         if (ple_gap) {
5473                 vmcs_write32(PLE_GAP, ple_gap);
5474                 vmx->ple_window = ple_window;
5475                 vmx->ple_window_dirty = true;
5476         }
5477
5478         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5479         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5480         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5481
5482         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5483         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5484         vmx_set_constant_host_state(vmx);
5485 #ifdef CONFIG_X86_64
5486         rdmsrl(MSR_FS_BASE, a);
5487         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5488         rdmsrl(MSR_GS_BASE, a);
5489         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5490 #else
5491         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5492         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5493 #endif
5494
5495         if (cpu_has_vmx_vmfunc())
5496                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5497
5498         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5499         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5500         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5501         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5502         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5503
5504         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5505                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5506
5507         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5508                 u32 index = vmx_msr_index[i];
5509                 u32 data_low, data_high;
5510                 int j = vmx->nmsrs;
5511
5512                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5513                         continue;
5514                 if (wrmsr_safe(index, data_low, data_high) < 0)
5515                         continue;
5516                 vmx->guest_msrs[j].index = i;
5517                 vmx->guest_msrs[j].data = 0;
5518                 vmx->guest_msrs[j].mask = -1ull;
5519                 ++vmx->nmsrs;
5520         }
5521
5522
5523         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5524
5525         /* 22.2.1, 20.8.1 */
5526         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5527
5528         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5529         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5530
5531         set_cr4_guest_host_mask(vmx);
5532
5533         if (vmx_xsaves_supported())
5534                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5535
5536         if (enable_pml) {
5537                 ASSERT(vmx->pml_pg);
5538                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5539                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5540         }
5541 }
5542
5543 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5544 {
5545         struct vcpu_vmx *vmx = to_vmx(vcpu);
5546         struct msr_data apic_base_msr;
5547         u64 cr0;
5548
5549         vmx->rmode.vm86_active = 0;
5550
5551         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5552         kvm_set_cr8(vcpu, 0);
5553
5554         if (!init_event) {
5555                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5556                                      MSR_IA32_APICBASE_ENABLE;
5557                 if (kvm_vcpu_is_reset_bsp(vcpu))
5558                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5559                 apic_base_msr.host_initiated = true;
5560                 kvm_set_apic_base(vcpu, &apic_base_msr);
5561         }
5562
5563         vmx_segment_cache_clear(vmx);
5564
5565         seg_setup(VCPU_SREG_CS);
5566         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5567         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5568
5569         seg_setup(VCPU_SREG_DS);
5570         seg_setup(VCPU_SREG_ES);
5571         seg_setup(VCPU_SREG_FS);
5572         seg_setup(VCPU_SREG_GS);
5573         seg_setup(VCPU_SREG_SS);
5574
5575         vmcs_write16(GUEST_TR_SELECTOR, 0);
5576         vmcs_writel(GUEST_TR_BASE, 0);
5577         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5578         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5579
5580         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5581         vmcs_writel(GUEST_LDTR_BASE, 0);
5582         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5583         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5584
5585         if (!init_event) {
5586                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5587                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5588                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5589                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5590         }
5591
5592         vmcs_writel(GUEST_RFLAGS, 0x02);
5593         kvm_rip_write(vcpu, 0xfff0);
5594
5595         vmcs_writel(GUEST_GDTR_BASE, 0);
5596         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5597
5598         vmcs_writel(GUEST_IDTR_BASE, 0);
5599         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5600
5601         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5602         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5603         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5604
5605         setup_msrs(vmx);
5606
5607         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5608
5609         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5610                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5611                 if (cpu_need_tpr_shadow(vcpu))
5612                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5613                                      __pa(vcpu->arch.apic->regs));
5614                 vmcs_write32(TPR_THRESHOLD, 0);
5615         }
5616
5617         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5618
5619         if (kvm_vcpu_apicv_active(vcpu))
5620                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5621
5622         if (vmx->vpid != 0)
5623                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5624
5625         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5626         vmx->vcpu.arch.cr0 = cr0;
5627         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5628         vmx_set_cr4(vcpu, 0);
5629         vmx_set_efer(vcpu, 0);
5630
5631         update_exception_bitmap(vcpu);
5632
5633         vpid_sync_context(vmx->vpid);
5634 }
5635
5636 /*
5637  * In nested virtualization, check if L1 asked to exit on external interrupts.
5638  * For most existing hypervisors, this will always return true.
5639  */
5640 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5641 {
5642         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5643                 PIN_BASED_EXT_INTR_MASK;
5644 }
5645
5646 /*
5647  * In nested virtualization, check if L1 has set
5648  * VM_EXIT_ACK_INTR_ON_EXIT
5649  */
5650 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5651 {
5652         return get_vmcs12(vcpu)->vm_exit_controls &
5653                 VM_EXIT_ACK_INTR_ON_EXIT;
5654 }
5655
5656 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5657 {
5658         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5659                 PIN_BASED_NMI_EXITING;
5660 }
5661
5662 static void enable_irq_window(struct kvm_vcpu *vcpu)
5663 {
5664         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5665                       CPU_BASED_VIRTUAL_INTR_PENDING);
5666 }
5667
5668 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5669 {
5670         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5671                 enable_irq_window(vcpu);
5672                 return;
5673         }
5674
5675         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5676                       CPU_BASED_VIRTUAL_NMI_PENDING);
5677 }
5678
5679 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5680 {
5681         struct vcpu_vmx *vmx = to_vmx(vcpu);
5682         uint32_t intr;
5683         int irq = vcpu->arch.interrupt.nr;
5684
5685         trace_kvm_inj_virq(irq);
5686
5687         ++vcpu->stat.irq_injections;
5688         if (vmx->rmode.vm86_active) {
5689                 int inc_eip = 0;
5690                 if (vcpu->arch.interrupt.soft)
5691                         inc_eip = vcpu->arch.event_exit_inst_len;
5692                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5693                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5694                 return;
5695         }
5696         intr = irq | INTR_INFO_VALID_MASK;
5697         if (vcpu->arch.interrupt.soft) {
5698                 intr |= INTR_TYPE_SOFT_INTR;
5699                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5700                              vmx->vcpu.arch.event_exit_inst_len);
5701         } else
5702                 intr |= INTR_TYPE_EXT_INTR;
5703         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5704 }
5705
5706 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5707 {
5708         struct vcpu_vmx *vmx = to_vmx(vcpu);
5709
5710         ++vcpu->stat.nmi_injections;
5711         vmx->loaded_vmcs->nmi_known_unmasked = false;
5712
5713         if (vmx->rmode.vm86_active) {
5714                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5715                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5716                 return;
5717         }
5718
5719         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5720                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5721 }
5722
5723 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5724 {
5725         struct vcpu_vmx *vmx = to_vmx(vcpu);
5726         bool masked;
5727
5728         if (vmx->loaded_vmcs->nmi_known_unmasked)
5729                 return false;
5730         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5731         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5732         return masked;
5733 }
5734
5735 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5736 {
5737         struct vcpu_vmx *vmx = to_vmx(vcpu);
5738
5739         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5740         if (masked)
5741                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5742                               GUEST_INTR_STATE_NMI);
5743         else
5744                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5745                                 GUEST_INTR_STATE_NMI);
5746 }
5747
5748 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5749 {
5750         if (to_vmx(vcpu)->nested.nested_run_pending)
5751                 return 0;
5752
5753         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5754                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5755                    | GUEST_INTR_STATE_NMI));
5756 }
5757
5758 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5759 {
5760         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5761                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5762                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5763                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5764 }
5765
5766 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5767 {
5768         int ret;
5769
5770         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5771                                     PAGE_SIZE * 3);
5772         if (ret)
5773                 return ret;
5774         kvm->arch.tss_addr = addr;
5775         return init_rmode_tss(kvm);
5776 }
5777
5778 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5779 {
5780         switch (vec) {
5781         case BP_VECTOR:
5782                 /*
5783                  * Update instruction length as we may reinject the exception
5784                  * from user space while in guest debugging mode.
5785                  */
5786                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5787                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5788                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5789                         return false;
5790                 /* fall through */
5791         case DB_VECTOR:
5792                 if (vcpu->guest_debug &
5793                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5794                         return false;
5795                 /* fall through */
5796         case DE_VECTOR:
5797         case OF_VECTOR:
5798         case BR_VECTOR:
5799         case UD_VECTOR:
5800         case DF_VECTOR:
5801         case SS_VECTOR:
5802         case GP_VECTOR:
5803         case MF_VECTOR:
5804                 return true;
5805         break;
5806         }
5807         return false;
5808 }
5809
5810 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5811                                   int vec, u32 err_code)
5812 {
5813         /*
5814          * Instruction with address size override prefix opcode 0x67
5815          * Cause the #SS fault with 0 error code in VM86 mode.
5816          */
5817         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5818                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5819                         if (vcpu->arch.halt_request) {
5820                                 vcpu->arch.halt_request = 0;
5821                                 return kvm_vcpu_halt(vcpu);
5822                         }
5823                         return 1;
5824                 }
5825                 return 0;
5826         }
5827
5828         /*
5829          * Forward all other exceptions that are valid in real mode.
5830          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5831          *        the required debugging infrastructure rework.
5832          */
5833         kvm_queue_exception(vcpu, vec);
5834         return 1;
5835 }
5836
5837 /*
5838  * Trigger machine check on the host. We assume all the MSRs are already set up
5839  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5840  * We pass a fake environment to the machine check handler because we want
5841  * the guest to be always treated like user space, no matter what context
5842  * it used internally.
5843  */
5844 static void kvm_machine_check(void)
5845 {
5846 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5847         struct pt_regs regs = {
5848                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5849                 .flags = X86_EFLAGS_IF,
5850         };
5851
5852         do_machine_check(&regs, 0);
5853 #endif
5854 }
5855
5856 static int handle_machine_check(struct kvm_vcpu *vcpu)
5857 {
5858         /* already handled by vcpu_run */
5859         return 1;
5860 }
5861
5862 static int handle_exception(struct kvm_vcpu *vcpu)
5863 {
5864         struct vcpu_vmx *vmx = to_vmx(vcpu);
5865         struct kvm_run *kvm_run = vcpu->run;
5866         u32 intr_info, ex_no, error_code;
5867         unsigned long cr2, rip, dr6;
5868         u32 vect_info;
5869         enum emulation_result er;
5870
5871         vect_info = vmx->idt_vectoring_info;
5872         intr_info = vmx->exit_intr_info;
5873
5874         if (is_machine_check(intr_info))
5875                 return handle_machine_check(vcpu);
5876
5877         if (is_nmi(intr_info))
5878                 return 1;  /* already handled by vmx_vcpu_run() */
5879
5880         if (is_invalid_opcode(intr_info)) {
5881                 if (is_guest_mode(vcpu)) {
5882                         kvm_queue_exception(vcpu, UD_VECTOR);
5883                         return 1;
5884                 }
5885                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5886                 if (er != EMULATE_DONE)
5887                         kvm_queue_exception(vcpu, UD_VECTOR);
5888                 return 1;
5889         }
5890
5891         error_code = 0;
5892         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5893                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5894
5895         /*
5896          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5897          * MMIO, it is better to report an internal error.
5898          * See the comments in vmx_handle_exit.
5899          */
5900         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5901             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5902                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5903                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5904                 vcpu->run->internal.ndata = 3;
5905                 vcpu->run->internal.data[0] = vect_info;
5906                 vcpu->run->internal.data[1] = intr_info;
5907                 vcpu->run->internal.data[2] = error_code;
5908                 return 0;
5909         }
5910
5911         if (is_page_fault(intr_info)) {
5912                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5913                 /* EPT won't cause page fault directly */
5914                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5915                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5916                                 true);
5917         }
5918
5919         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5920
5921         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5922                 return handle_rmode_exception(vcpu, ex_no, error_code);
5923
5924         switch (ex_no) {
5925         case AC_VECTOR:
5926                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5927                 return 1;
5928         case DB_VECTOR:
5929                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5930                 if (!(vcpu->guest_debug &
5931                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5932                         vcpu->arch.dr6 &= ~15;
5933                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5934                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5935                                 skip_emulated_instruction(vcpu);
5936
5937                         kvm_queue_exception(vcpu, DB_VECTOR);
5938                         return 1;
5939                 }
5940                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5941                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5942                 /* fall through */
5943         case BP_VECTOR:
5944                 /*
5945                  * Update instruction length as we may reinject #BP from
5946                  * user space while in guest debugging mode. Reading it for
5947                  * #DB as well causes no harm, it is not used in that case.
5948                  */
5949                 vmx->vcpu.arch.event_exit_inst_len =
5950                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5951                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5952                 rip = kvm_rip_read(vcpu);
5953                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5954                 kvm_run->debug.arch.exception = ex_no;
5955                 break;
5956         default:
5957                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5958                 kvm_run->ex.exception = ex_no;
5959                 kvm_run->ex.error_code = error_code;
5960                 break;
5961         }
5962         return 0;
5963 }
5964
5965 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5966 {
5967         ++vcpu->stat.irq_exits;
5968         return 1;
5969 }
5970
5971 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5972 {
5973         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5974         vcpu->mmio_needed = 0;
5975         return 0;
5976 }
5977
5978 static int handle_io(struct kvm_vcpu *vcpu)
5979 {
5980         unsigned long exit_qualification;
5981         int size, in, string, ret;
5982         unsigned port;
5983
5984         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5985         string = (exit_qualification & 16) != 0;
5986         in = (exit_qualification & 8) != 0;
5987
5988         ++vcpu->stat.io_exits;
5989
5990         if (string || in)
5991                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5992
5993         port = exit_qualification >> 16;
5994         size = (exit_qualification & 7) + 1;
5995
5996         ret = kvm_skip_emulated_instruction(vcpu);
5997
5998         /*
5999          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6000          * KVM_EXIT_DEBUG here.
6001          */
6002         return kvm_fast_pio_out(vcpu, size, port) && ret;
6003 }
6004
6005 static void
6006 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6007 {
6008         /*
6009          * Patch in the VMCALL instruction:
6010          */
6011         hypercall[0] = 0x0f;
6012         hypercall[1] = 0x01;
6013         hypercall[2] = 0xc1;
6014 }
6015
6016 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6017 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6018 {
6019         if (is_guest_mode(vcpu)) {
6020                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6021                 unsigned long orig_val = val;
6022
6023                 /*
6024                  * We get here when L2 changed cr0 in a way that did not change
6025                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6026                  * but did change L0 shadowed bits. So we first calculate the
6027                  * effective cr0 value that L1 would like to write into the
6028                  * hardware. It consists of the L2-owned bits from the new
6029                  * value combined with the L1-owned bits from L1's guest_cr0.
6030                  */
6031                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6032                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6033
6034                 if (!nested_guest_cr0_valid(vcpu, val))
6035                         return 1;
6036
6037                 if (kvm_set_cr0(vcpu, val))
6038                         return 1;
6039                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6040                 return 0;
6041         } else {
6042                 if (to_vmx(vcpu)->nested.vmxon &&
6043                     !nested_host_cr0_valid(vcpu, val))
6044                         return 1;
6045
6046                 return kvm_set_cr0(vcpu, val);
6047         }
6048 }
6049
6050 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6051 {
6052         if (is_guest_mode(vcpu)) {
6053                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6054                 unsigned long orig_val = val;
6055
6056                 /* analogously to handle_set_cr0 */
6057                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6058                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6059                 if (kvm_set_cr4(vcpu, val))
6060                         return 1;
6061                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6062                 return 0;
6063         } else
6064                 return kvm_set_cr4(vcpu, val);
6065 }
6066
6067 static int handle_cr(struct kvm_vcpu *vcpu)
6068 {
6069         unsigned long exit_qualification, val;
6070         int cr;
6071         int reg;
6072         int err;
6073         int ret;
6074
6075         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6076         cr = exit_qualification & 15;
6077         reg = (exit_qualification >> 8) & 15;
6078         switch ((exit_qualification >> 4) & 3) {
6079         case 0: /* mov to cr */
6080                 val = kvm_register_readl(vcpu, reg);
6081                 trace_kvm_cr_write(cr, val);
6082                 switch (cr) {
6083                 case 0:
6084                         err = handle_set_cr0(vcpu, val);
6085                         return kvm_complete_insn_gp(vcpu, err);
6086                 case 3:
6087                         err = kvm_set_cr3(vcpu, val);
6088                         return kvm_complete_insn_gp(vcpu, err);
6089                 case 4:
6090                         err = handle_set_cr4(vcpu, val);
6091                         return kvm_complete_insn_gp(vcpu, err);
6092                 case 8: {
6093                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6094                                 u8 cr8 = (u8)val;
6095                                 err = kvm_set_cr8(vcpu, cr8);
6096                                 ret = kvm_complete_insn_gp(vcpu, err);
6097                                 if (lapic_in_kernel(vcpu))
6098                                         return ret;
6099                                 if (cr8_prev <= cr8)
6100                                         return ret;
6101                                 /*
6102                                  * TODO: we might be squashing a
6103                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6104                                  * KVM_EXIT_DEBUG here.
6105                                  */
6106                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6107                                 return 0;
6108                         }
6109                 }
6110                 break;
6111         case 2: /* clts */
6112                 WARN_ONCE(1, "Guest should always own CR0.TS");
6113                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6114                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6115                 return kvm_skip_emulated_instruction(vcpu);
6116         case 1: /*mov from cr*/
6117                 switch (cr) {
6118                 case 3:
6119                         val = kvm_read_cr3(vcpu);
6120                         kvm_register_write(vcpu, reg, val);
6121                         trace_kvm_cr_read(cr, val);
6122                         return kvm_skip_emulated_instruction(vcpu);
6123                 case 8:
6124                         val = kvm_get_cr8(vcpu);
6125                         kvm_register_write(vcpu, reg, val);
6126                         trace_kvm_cr_read(cr, val);
6127                         return kvm_skip_emulated_instruction(vcpu);
6128                 }
6129                 break;
6130         case 3: /* lmsw */
6131                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6132                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6133                 kvm_lmsw(vcpu, val);
6134
6135                 return kvm_skip_emulated_instruction(vcpu);
6136         default:
6137                 break;
6138         }
6139         vcpu->run->exit_reason = 0;
6140         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6141                (int)(exit_qualification >> 4) & 3, cr);
6142         return 0;
6143 }
6144
6145 static int handle_dr(struct kvm_vcpu *vcpu)
6146 {
6147         unsigned long exit_qualification;
6148         int dr, dr7, reg;
6149
6150         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6151         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6152
6153         /* First, if DR does not exist, trigger UD */
6154         if (!kvm_require_dr(vcpu, dr))
6155                 return 1;
6156
6157         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6158         if (!kvm_require_cpl(vcpu, 0))
6159                 return 1;
6160         dr7 = vmcs_readl(GUEST_DR7);
6161         if (dr7 & DR7_GD) {
6162                 /*
6163                  * As the vm-exit takes precedence over the debug trap, we
6164                  * need to emulate the latter, either for the host or the
6165                  * guest debugging itself.
6166                  */
6167                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6168                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6169                         vcpu->run->debug.arch.dr7 = dr7;
6170                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6171                         vcpu->run->debug.arch.exception = DB_VECTOR;
6172                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6173                         return 0;
6174                 } else {
6175                         vcpu->arch.dr6 &= ~15;
6176                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6177                         kvm_queue_exception(vcpu, DB_VECTOR);
6178                         return 1;
6179                 }
6180         }
6181
6182         if (vcpu->guest_debug == 0) {
6183                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6184                                 CPU_BASED_MOV_DR_EXITING);
6185
6186                 /*
6187                  * No more DR vmexits; force a reload of the debug registers
6188                  * and reenter on this instruction.  The next vmexit will
6189                  * retrieve the full state of the debug registers.
6190                  */
6191                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6192                 return 1;
6193         }
6194
6195         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6196         if (exit_qualification & TYPE_MOV_FROM_DR) {
6197                 unsigned long val;
6198
6199                 if (kvm_get_dr(vcpu, dr, &val))
6200                         return 1;
6201                 kvm_register_write(vcpu, reg, val);
6202         } else
6203                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6204                         return 1;
6205
6206         return kvm_skip_emulated_instruction(vcpu);
6207 }
6208
6209 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6210 {
6211         return vcpu->arch.dr6;
6212 }
6213
6214 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6215 {
6216 }
6217
6218 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6219 {
6220         get_debugreg(vcpu->arch.db[0], 0);
6221         get_debugreg(vcpu->arch.db[1], 1);
6222         get_debugreg(vcpu->arch.db[2], 2);
6223         get_debugreg(vcpu->arch.db[3], 3);
6224         get_debugreg(vcpu->arch.dr6, 6);
6225         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6226
6227         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6228         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6229 }
6230
6231 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6232 {
6233         vmcs_writel(GUEST_DR7, val);
6234 }
6235
6236 static int handle_cpuid(struct kvm_vcpu *vcpu)
6237 {
6238         return kvm_emulate_cpuid(vcpu);
6239 }
6240
6241 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6242 {
6243         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6244         struct msr_data msr_info;
6245
6246         msr_info.index = ecx;
6247         msr_info.host_initiated = false;
6248         if (vmx_get_msr(vcpu, &msr_info)) {
6249                 trace_kvm_msr_read_ex(ecx);
6250                 kvm_inject_gp(vcpu, 0);
6251                 return 1;
6252         }
6253
6254         trace_kvm_msr_read(ecx, msr_info.data);
6255
6256         /* FIXME: handling of bits 32:63 of rax, rdx */
6257         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6258         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6259         return kvm_skip_emulated_instruction(vcpu);
6260 }
6261
6262 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6263 {
6264         struct msr_data msr;
6265         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6266         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6267                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6268
6269         msr.data = data;
6270         msr.index = ecx;
6271         msr.host_initiated = false;
6272         if (kvm_set_msr(vcpu, &msr) != 0) {
6273                 trace_kvm_msr_write_ex(ecx, data);
6274                 kvm_inject_gp(vcpu, 0);
6275                 return 1;
6276         }
6277
6278         trace_kvm_msr_write(ecx, data);
6279         return kvm_skip_emulated_instruction(vcpu);
6280 }
6281
6282 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6283 {
6284         kvm_apic_update_ppr(vcpu);
6285         return 1;
6286 }
6287
6288 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6289 {
6290         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6291                         CPU_BASED_VIRTUAL_INTR_PENDING);
6292
6293         kvm_make_request(KVM_REQ_EVENT, vcpu);
6294
6295         ++vcpu->stat.irq_window_exits;
6296         return 1;
6297 }
6298
6299 static int handle_halt(struct kvm_vcpu *vcpu)
6300 {
6301         return kvm_emulate_halt(vcpu);
6302 }
6303
6304 static int handle_vmcall(struct kvm_vcpu *vcpu)
6305 {
6306         return kvm_emulate_hypercall(vcpu);
6307 }
6308
6309 static int handle_invd(struct kvm_vcpu *vcpu)
6310 {
6311         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6312 }
6313
6314 static int handle_invlpg(struct kvm_vcpu *vcpu)
6315 {
6316         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6317
6318         kvm_mmu_invlpg(vcpu, exit_qualification);
6319         return kvm_skip_emulated_instruction(vcpu);
6320 }
6321
6322 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6323 {
6324         int err;
6325
6326         err = kvm_rdpmc(vcpu);
6327         return kvm_complete_insn_gp(vcpu, err);
6328 }
6329
6330 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6331 {
6332         return kvm_emulate_wbinvd(vcpu);
6333 }
6334
6335 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6336 {
6337         u64 new_bv = kvm_read_edx_eax(vcpu);
6338         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6339
6340         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6341                 return kvm_skip_emulated_instruction(vcpu);
6342         return 1;
6343 }
6344
6345 static int handle_xsaves(struct kvm_vcpu *vcpu)
6346 {
6347         kvm_skip_emulated_instruction(vcpu);
6348         WARN(1, "this should never happen\n");
6349         return 1;
6350 }
6351
6352 static int handle_xrstors(struct kvm_vcpu *vcpu)
6353 {
6354         kvm_skip_emulated_instruction(vcpu);
6355         WARN(1, "this should never happen\n");
6356         return 1;
6357 }
6358
6359 static int handle_apic_access(struct kvm_vcpu *vcpu)
6360 {
6361         if (likely(fasteoi)) {
6362                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6363                 int access_type, offset;
6364
6365                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6366                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6367                 /*
6368                  * Sane guest uses MOV to write EOI, with written value
6369                  * not cared. So make a short-circuit here by avoiding
6370                  * heavy instruction emulation.
6371                  */
6372                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6373                     (offset == APIC_EOI)) {
6374                         kvm_lapic_set_eoi(vcpu);
6375                         return kvm_skip_emulated_instruction(vcpu);
6376                 }
6377         }
6378         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6379 }
6380
6381 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6382 {
6383         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6384         int vector = exit_qualification & 0xff;
6385
6386         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6387         kvm_apic_set_eoi_accelerated(vcpu, vector);
6388         return 1;
6389 }
6390
6391 static int handle_apic_write(struct kvm_vcpu *vcpu)
6392 {
6393         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6394         u32 offset = exit_qualification & 0xfff;
6395
6396         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6397         kvm_apic_write_nodecode(vcpu, offset);
6398         return 1;
6399 }
6400
6401 static int handle_task_switch(struct kvm_vcpu *vcpu)
6402 {
6403         struct vcpu_vmx *vmx = to_vmx(vcpu);
6404         unsigned long exit_qualification;
6405         bool has_error_code = false;
6406         u32 error_code = 0;
6407         u16 tss_selector;
6408         int reason, type, idt_v, idt_index;
6409
6410         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6411         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6412         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6413
6414         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6415
6416         reason = (u32)exit_qualification >> 30;
6417         if (reason == TASK_SWITCH_GATE && idt_v) {
6418                 switch (type) {
6419                 case INTR_TYPE_NMI_INTR:
6420                         vcpu->arch.nmi_injected = false;
6421                         vmx_set_nmi_mask(vcpu, true);
6422                         break;
6423                 case INTR_TYPE_EXT_INTR:
6424                 case INTR_TYPE_SOFT_INTR:
6425                         kvm_clear_interrupt_queue(vcpu);
6426                         break;
6427                 case INTR_TYPE_HARD_EXCEPTION:
6428                         if (vmx->idt_vectoring_info &
6429                             VECTORING_INFO_DELIVER_CODE_MASK) {
6430                                 has_error_code = true;
6431                                 error_code =
6432                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6433                         }
6434                         /* fall through */
6435                 case INTR_TYPE_SOFT_EXCEPTION:
6436                         kvm_clear_exception_queue(vcpu);
6437                         break;
6438                 default:
6439                         break;
6440                 }
6441         }
6442         tss_selector = exit_qualification;
6443
6444         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6445                        type != INTR_TYPE_EXT_INTR &&
6446                        type != INTR_TYPE_NMI_INTR))
6447                 skip_emulated_instruction(vcpu);
6448
6449         if (kvm_task_switch(vcpu, tss_selector,
6450                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6451                             has_error_code, error_code) == EMULATE_FAIL) {
6452                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6453                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6454                 vcpu->run->internal.ndata = 0;
6455                 return 0;
6456         }
6457
6458         /*
6459          * TODO: What about debug traps on tss switch?
6460          *       Are we supposed to inject them and update dr6?
6461          */
6462
6463         return 1;
6464 }
6465
6466 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6467 {
6468         unsigned long exit_qualification;
6469         gpa_t gpa;
6470         u64 error_code;
6471
6472         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6473
6474         /*
6475          * EPT violation happened while executing iret from NMI,
6476          * "blocked by NMI" bit has to be set before next VM entry.
6477          * There are errata that may cause this bit to not be set:
6478          * AAK134, BY25.
6479          */
6480         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6481                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6482                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6483
6484         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6485         trace_kvm_page_fault(gpa, exit_qualification);
6486
6487         /* Is it a read fault? */
6488         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6489                      ? PFERR_USER_MASK : 0;
6490         /* Is it a write fault? */
6491         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6492                       ? PFERR_WRITE_MASK : 0;
6493         /* Is it a fetch fault? */
6494         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6495                       ? PFERR_FETCH_MASK : 0;
6496         /* ept page table entry is present? */
6497         error_code |= (exit_qualification &
6498                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6499                         EPT_VIOLATION_EXECUTABLE))
6500                       ? PFERR_PRESENT_MASK : 0;
6501
6502         error_code |= (exit_qualification & 0x100) != 0 ?
6503                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6504
6505         vcpu->arch.exit_qualification = exit_qualification;
6506         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6507 }
6508
6509 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6510 {
6511         int ret;
6512         gpa_t gpa;
6513
6514         /*
6515          * A nested guest cannot optimize MMIO vmexits, because we have an
6516          * nGPA here instead of the required GPA.
6517          */
6518         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6519         if (!is_guest_mode(vcpu) &&
6520             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6521                 trace_kvm_fast_mmio(gpa);
6522                 return kvm_skip_emulated_instruction(vcpu);
6523         }
6524
6525         ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6526         if (ret >= 0)
6527                 return ret;
6528
6529         /* It is the real ept misconfig */
6530         WARN_ON(1);
6531
6532         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6533         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6534
6535         return 0;
6536 }
6537
6538 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6539 {
6540         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6541                         CPU_BASED_VIRTUAL_NMI_PENDING);
6542         ++vcpu->stat.nmi_window_exits;
6543         kvm_make_request(KVM_REQ_EVENT, vcpu);
6544
6545         return 1;
6546 }
6547
6548 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6549 {
6550         struct vcpu_vmx *vmx = to_vmx(vcpu);
6551         enum emulation_result err = EMULATE_DONE;
6552         int ret = 1;
6553         u32 cpu_exec_ctrl;
6554         bool intr_window_requested;
6555         unsigned count = 130;
6556
6557         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6558         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6559
6560         while (vmx->emulation_required && count-- != 0) {
6561                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6562                         return handle_interrupt_window(&vmx->vcpu);
6563
6564                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6565                         return 1;
6566
6567                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6568
6569                 if (err == EMULATE_USER_EXIT) {
6570                         ++vcpu->stat.mmio_exits;
6571                         ret = 0;
6572                         goto out;
6573                 }
6574
6575                 if (err != EMULATE_DONE) {
6576                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6577                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6578                         vcpu->run->internal.ndata = 0;
6579                         return 0;
6580                 }
6581
6582                 if (vcpu->arch.halt_request) {
6583                         vcpu->arch.halt_request = 0;
6584                         ret = kvm_vcpu_halt(vcpu);
6585                         goto out;
6586                 }
6587
6588                 if (signal_pending(current))
6589                         goto out;
6590                 if (need_resched())
6591                         schedule();
6592         }
6593
6594 out:
6595         return ret;
6596 }
6597
6598 static int __grow_ple_window(int val)
6599 {
6600         if (ple_window_grow < 1)
6601                 return ple_window;
6602
6603         val = min(val, ple_window_actual_max);
6604
6605         if (ple_window_grow < ple_window)
6606                 val *= ple_window_grow;
6607         else
6608                 val += ple_window_grow;
6609
6610         return val;
6611 }
6612
6613 static int __shrink_ple_window(int val, int modifier, int minimum)
6614 {
6615         if (modifier < 1)
6616                 return ple_window;
6617
6618         if (modifier < ple_window)
6619                 val /= modifier;
6620         else
6621                 val -= modifier;
6622
6623         return max(val, minimum);
6624 }
6625
6626 static void grow_ple_window(struct kvm_vcpu *vcpu)
6627 {
6628         struct vcpu_vmx *vmx = to_vmx(vcpu);
6629         int old = vmx->ple_window;
6630
6631         vmx->ple_window = __grow_ple_window(old);
6632
6633         if (vmx->ple_window != old)
6634                 vmx->ple_window_dirty = true;
6635
6636         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6637 }
6638
6639 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6640 {
6641         struct vcpu_vmx *vmx = to_vmx(vcpu);
6642         int old = vmx->ple_window;
6643
6644         vmx->ple_window = __shrink_ple_window(old,
6645                                               ple_window_shrink, ple_window);
6646
6647         if (vmx->ple_window != old)
6648                 vmx->ple_window_dirty = true;
6649
6650         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6651 }
6652
6653 /*
6654  * ple_window_actual_max is computed to be one grow_ple_window() below
6655  * ple_window_max. (See __grow_ple_window for the reason.)
6656  * This prevents overflows, because ple_window_max is int.
6657  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6658  * this process.
6659  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6660  */
6661 static void update_ple_window_actual_max(void)
6662 {
6663         ple_window_actual_max =
6664                         __shrink_ple_window(max(ple_window_max, ple_window),
6665                                             ple_window_grow, INT_MIN);
6666 }
6667
6668 /*
6669  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6670  */
6671 static void wakeup_handler(void)
6672 {
6673         struct kvm_vcpu *vcpu;
6674         int cpu = smp_processor_id();
6675
6676         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6677         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6678                         blocked_vcpu_list) {
6679                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6680
6681                 if (pi_test_on(pi_desc) == 1)
6682                         kvm_vcpu_kick(vcpu);
6683         }
6684         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6685 }
6686
6687 void vmx_enable_tdp(void)
6688 {
6689         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6690                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6691                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6692                 0ull, VMX_EPT_EXECUTABLE_MASK,
6693                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6694                 VMX_EPT_RWX_MASK, 0ull);
6695
6696         ept_set_mmio_spte_mask();
6697         kvm_enable_tdp();
6698 }
6699
6700 static __init int hardware_setup(void)
6701 {
6702         int r = -ENOMEM, i, msr;
6703
6704         rdmsrl_safe(MSR_EFER, &host_efer);
6705
6706         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6707                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6708
6709         for (i = 0; i < VMX_BITMAP_NR; i++) {
6710                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6711                 if (!vmx_bitmap[i])
6712                         goto out;
6713         }
6714
6715         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6716         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6717         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6718
6719         /*
6720          * Allow direct access to the PC debug port (it is often used for I/O
6721          * delays, but the vmexits simply slow things down).
6722          */
6723         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6724         clear_bit(0x80, vmx_io_bitmap_a);
6725
6726         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6727
6728         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6729         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6730
6731         if (setup_vmcs_config(&vmcs_config) < 0) {
6732                 r = -EIO;
6733                 goto out;
6734         }
6735
6736         if (boot_cpu_has(X86_FEATURE_NX))
6737                 kvm_enable_efer_bits(EFER_NX);
6738
6739         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6740                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6741                 enable_vpid = 0;
6742
6743         if (!cpu_has_vmx_shadow_vmcs())
6744                 enable_shadow_vmcs = 0;
6745         if (enable_shadow_vmcs)
6746                 init_vmcs_shadow_fields();
6747
6748         if (!cpu_has_vmx_ept() ||
6749             !cpu_has_vmx_ept_4levels() ||
6750             !cpu_has_vmx_ept_mt_wb()) {
6751                 enable_ept = 0;
6752                 enable_unrestricted_guest = 0;
6753                 enable_ept_ad_bits = 0;
6754         }
6755
6756         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6757                 enable_ept_ad_bits = 0;
6758
6759         if (!cpu_has_vmx_unrestricted_guest())
6760                 enable_unrestricted_guest = 0;
6761
6762         if (!cpu_has_vmx_flexpriority())
6763                 flexpriority_enabled = 0;
6764
6765         /*
6766          * set_apic_access_page_addr() is used to reload apic access
6767          * page upon invalidation.  No need to do anything if not
6768          * using the APIC_ACCESS_ADDR VMCS field.
6769          */
6770         if (!flexpriority_enabled)
6771                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6772
6773         if (!cpu_has_vmx_tpr_shadow())
6774                 kvm_x86_ops->update_cr8_intercept = NULL;
6775
6776         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6777                 kvm_disable_largepages();
6778
6779         if (!cpu_has_vmx_ple()) {
6780                 ple_gap = 0;
6781                 ple_window = 0;
6782                 ple_window_grow = 0;
6783                 ple_window_max = 0;
6784                 ple_window_shrink = 0;
6785         }
6786
6787         if (!cpu_has_vmx_apicv()) {
6788                 enable_apicv = 0;
6789                 kvm_x86_ops->sync_pir_to_irr = NULL;
6790         }
6791
6792         if (cpu_has_vmx_tsc_scaling()) {
6793                 kvm_has_tsc_control = true;
6794                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6795                 kvm_tsc_scaling_ratio_frac_bits = 48;
6796         }
6797
6798         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6799         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6800         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6801         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6802         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6803         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6804
6805         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6806                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6807         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6808                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6809         memcpy(vmx_msr_bitmap_legacy_x2apic,
6810                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6811         memcpy(vmx_msr_bitmap_longmode_x2apic,
6812                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6813
6814         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6815
6816         for (msr = 0x800; msr <= 0x8ff; msr++) {
6817                 if (msr == 0x839 /* TMCCT */)
6818                         continue;
6819                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6820         }
6821
6822         /*
6823          * TPR reads and writes can be virtualized even if virtual interrupt
6824          * delivery is not in use.
6825          */
6826         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6827         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6828
6829         /* EOI */
6830         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6831         /* SELF-IPI */
6832         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6833
6834         if (enable_ept)
6835                 vmx_enable_tdp();
6836         else
6837                 kvm_disable_tdp();
6838
6839         update_ple_window_actual_max();
6840
6841         /*
6842          * Only enable PML when hardware supports PML feature, and both EPT
6843          * and EPT A/D bit features are enabled -- PML depends on them to work.
6844          */
6845         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6846                 enable_pml = 0;
6847
6848         if (!enable_pml) {
6849                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6850                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6851                 kvm_x86_ops->flush_log_dirty = NULL;
6852                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6853         }
6854
6855         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6856                 u64 vmx_msr;
6857
6858                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6859                 cpu_preemption_timer_multi =
6860                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6861         } else {
6862                 kvm_x86_ops->set_hv_timer = NULL;
6863                 kvm_x86_ops->cancel_hv_timer = NULL;
6864         }
6865
6866         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6867
6868         kvm_mce_cap_supported |= MCG_LMCE_P;
6869
6870         return alloc_kvm_area();
6871
6872 out:
6873         for (i = 0; i < VMX_BITMAP_NR; i++)
6874                 free_page((unsigned long)vmx_bitmap[i]);
6875
6876     return r;
6877 }
6878
6879 static __exit void hardware_unsetup(void)
6880 {
6881         int i;
6882
6883         for (i = 0; i < VMX_BITMAP_NR; i++)
6884                 free_page((unsigned long)vmx_bitmap[i]);
6885
6886         free_kvm_area();
6887 }
6888
6889 /*
6890  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6891  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6892  */
6893 static int handle_pause(struct kvm_vcpu *vcpu)
6894 {
6895         if (ple_gap)
6896                 grow_ple_window(vcpu);
6897
6898         /*
6899          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6900          * VM-execution control is ignored if CPL > 0. OTOH, KVM
6901          * never set PAUSE_EXITING and just set PLE if supported,
6902          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6903          */
6904         kvm_vcpu_on_spin(vcpu, true);
6905         return kvm_skip_emulated_instruction(vcpu);
6906 }
6907
6908 static int handle_nop(struct kvm_vcpu *vcpu)
6909 {
6910         return kvm_skip_emulated_instruction(vcpu);
6911 }
6912
6913 static int handle_mwait(struct kvm_vcpu *vcpu)
6914 {
6915         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6916         return handle_nop(vcpu);
6917 }
6918
6919 static int handle_invalid_op(struct kvm_vcpu *vcpu)
6920 {
6921         kvm_queue_exception(vcpu, UD_VECTOR);
6922         return 1;
6923 }
6924
6925 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6926 {
6927         return 1;
6928 }
6929
6930 static int handle_monitor(struct kvm_vcpu *vcpu)
6931 {
6932         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6933         return handle_nop(vcpu);
6934 }
6935
6936 /*
6937  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6938  * We could reuse a single VMCS for all the L2 guests, but we also want the
6939  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6940  * allows keeping them loaded on the processor, and in the future will allow
6941  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6942  * every entry if they never change.
6943  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6944  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6945  *
6946  * The following functions allocate and free a vmcs02 in this pool.
6947  */
6948
6949 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6950 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6951 {
6952         struct vmcs02_list *item;
6953         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6954                 if (item->vmptr == vmx->nested.current_vmptr) {
6955                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6956                         return &item->vmcs02;
6957                 }
6958
6959         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6960                 /* Recycle the least recently used VMCS. */
6961                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6962                                        struct vmcs02_list, list);
6963                 item->vmptr = vmx->nested.current_vmptr;
6964                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6965                 return &item->vmcs02;
6966         }
6967
6968         /* Create a new VMCS */
6969         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6970         if (!item)
6971                 return NULL;
6972         item->vmcs02.vmcs = alloc_vmcs();
6973         item->vmcs02.shadow_vmcs = NULL;
6974         if (!item->vmcs02.vmcs) {
6975                 kfree(item);
6976                 return NULL;
6977         }
6978         loaded_vmcs_init(&item->vmcs02);
6979         item->vmptr = vmx->nested.current_vmptr;
6980         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6981         vmx->nested.vmcs02_num++;
6982         return &item->vmcs02;
6983 }
6984
6985 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6986 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6987 {
6988         struct vmcs02_list *item;
6989         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6990                 if (item->vmptr == vmptr) {
6991                         free_loaded_vmcs(&item->vmcs02);
6992                         list_del(&item->list);
6993                         kfree(item);
6994                         vmx->nested.vmcs02_num--;
6995                         return;
6996                 }
6997 }
6998
6999 /*
7000  * Free all VMCSs saved for this vcpu, except the one pointed by
7001  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
7002  * must be &vmx->vmcs01.
7003  */
7004 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
7005 {
7006         struct vmcs02_list *item, *n;
7007
7008         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
7009         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
7010                 /*
7011                  * Something will leak if the above WARN triggers.  Better than
7012                  * a use-after-free.
7013                  */
7014                 if (vmx->loaded_vmcs == &item->vmcs02)
7015                         continue;
7016
7017                 free_loaded_vmcs(&item->vmcs02);
7018                 list_del(&item->list);
7019                 kfree(item);
7020                 vmx->nested.vmcs02_num--;
7021         }
7022 }
7023
7024 /*
7025  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7026  * set the success or error code of an emulated VMX instruction, as specified
7027  * by Vol 2B, VMX Instruction Reference, "Conventions".
7028  */
7029 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7030 {
7031         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7032                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7033                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7034 }
7035
7036 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7037 {
7038         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7039                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7040                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7041                         | X86_EFLAGS_CF);
7042 }
7043
7044 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7045                                         u32 vm_instruction_error)
7046 {
7047         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7048                 /*
7049                  * failValid writes the error number to the current VMCS, which
7050                  * can't be done there isn't a current VMCS.
7051                  */
7052                 nested_vmx_failInvalid(vcpu);
7053                 return;
7054         }
7055         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7056                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7057                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7058                         | X86_EFLAGS_ZF);
7059         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7060         /*
7061          * We don't need to force a shadow sync because
7062          * VM_INSTRUCTION_ERROR is not shadowed
7063          */
7064 }
7065
7066 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7067 {
7068         /* TODO: not to reset guest simply here. */
7069         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7070         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7071 }
7072
7073 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7074 {
7075         struct vcpu_vmx *vmx =
7076                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7077
7078         vmx->nested.preemption_timer_expired = true;
7079         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7080         kvm_vcpu_kick(&vmx->vcpu);
7081
7082         return HRTIMER_NORESTART;
7083 }
7084
7085 /*
7086  * Decode the memory-address operand of a vmx instruction, as recorded on an
7087  * exit caused by such an instruction (run by a guest hypervisor).
7088  * On success, returns 0. When the operand is invalid, returns 1 and throws
7089  * #UD or #GP.
7090  */
7091 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7092                                  unsigned long exit_qualification,
7093                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7094 {
7095         gva_t off;
7096         bool exn;
7097         struct kvm_segment s;
7098
7099         /*
7100          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7101          * Execution", on an exit, vmx_instruction_info holds most of the
7102          * addressing components of the operand. Only the displacement part
7103          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7104          * For how an actual address is calculated from all these components,
7105          * refer to Vol. 1, "Operand Addressing".
7106          */
7107         int  scaling = vmx_instruction_info & 3;
7108         int  addr_size = (vmx_instruction_info >> 7) & 7;
7109         bool is_reg = vmx_instruction_info & (1u << 10);
7110         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7111         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7112         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7113         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7114         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7115
7116         if (is_reg) {
7117                 kvm_queue_exception(vcpu, UD_VECTOR);
7118                 return 1;
7119         }
7120
7121         /* Addr = segment_base + offset */
7122         /* offset = base + [index * scale] + displacement */
7123         off = exit_qualification; /* holds the displacement */
7124         if (base_is_valid)
7125                 off += kvm_register_read(vcpu, base_reg);
7126         if (index_is_valid)
7127                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7128         vmx_get_segment(vcpu, &s, seg_reg);
7129         *ret = s.base + off;
7130
7131         if (addr_size == 1) /* 32 bit */
7132                 *ret &= 0xffffffff;
7133
7134         /* Checks for #GP/#SS exceptions. */
7135         exn = false;
7136         if (is_long_mode(vcpu)) {
7137                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7138                  * non-canonical form. This is the only check on the memory
7139                  * destination for long mode!
7140                  */
7141                 exn = is_noncanonical_address(*ret, vcpu);
7142         } else if (is_protmode(vcpu)) {
7143                 /* Protected mode: apply checks for segment validity in the
7144                  * following order:
7145                  * - segment type check (#GP(0) may be thrown)
7146                  * - usability check (#GP(0)/#SS(0))
7147                  * - limit check (#GP(0)/#SS(0))
7148                  */
7149                 if (wr)
7150                         /* #GP(0) if the destination operand is located in a
7151                          * read-only data segment or any code segment.
7152                          */
7153                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7154                 else
7155                         /* #GP(0) if the source operand is located in an
7156                          * execute-only code segment
7157                          */
7158                         exn = ((s.type & 0xa) == 8);
7159                 if (exn) {
7160                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7161                         return 1;
7162                 }
7163                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7164                  */
7165                 exn = (s.unusable != 0);
7166                 /* Protected mode: #GP(0)/#SS(0) if the memory
7167                  * operand is outside the segment limit.
7168                  */
7169                 exn = exn || (off + sizeof(u64) > s.limit);
7170         }
7171         if (exn) {
7172                 kvm_queue_exception_e(vcpu,
7173                                       seg_reg == VCPU_SREG_SS ?
7174                                                 SS_VECTOR : GP_VECTOR,
7175                                       0);
7176                 return 1;
7177         }
7178
7179         return 0;
7180 }
7181
7182 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7183 {
7184         gva_t gva;
7185         struct x86_exception e;
7186
7187         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7188                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7189                 return 1;
7190
7191         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7192                                 sizeof(*vmpointer), &e)) {
7193                 kvm_inject_page_fault(vcpu, &e);
7194                 return 1;
7195         }
7196
7197         return 0;
7198 }
7199
7200 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7201 {
7202         struct vcpu_vmx *vmx = to_vmx(vcpu);
7203         struct vmcs *shadow_vmcs;
7204
7205         if (cpu_has_vmx_msr_bitmap()) {
7206                 vmx->nested.msr_bitmap =
7207                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7208                 if (!vmx->nested.msr_bitmap)
7209                         goto out_msr_bitmap;
7210         }
7211
7212         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7213         if (!vmx->nested.cached_vmcs12)
7214                 goto out_cached_vmcs12;
7215
7216         if (enable_shadow_vmcs) {
7217                 shadow_vmcs = alloc_vmcs();
7218                 if (!shadow_vmcs)
7219                         goto out_shadow_vmcs;
7220                 /* mark vmcs as shadow */
7221                 shadow_vmcs->revision_id |= (1u << 31);
7222                 /* init shadow vmcs */
7223                 vmcs_clear(shadow_vmcs);
7224                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7225         }
7226
7227         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7228         vmx->nested.vmcs02_num = 0;
7229
7230         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7231                      HRTIMER_MODE_REL_PINNED);
7232         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7233
7234         vmx->nested.vmxon = true;
7235         return 0;
7236
7237 out_shadow_vmcs:
7238         kfree(vmx->nested.cached_vmcs12);
7239
7240 out_cached_vmcs12:
7241         free_page((unsigned long)vmx->nested.msr_bitmap);
7242
7243 out_msr_bitmap:
7244         return -ENOMEM;
7245 }
7246
7247 /*
7248  * Emulate the VMXON instruction.
7249  * Currently, we just remember that VMX is active, and do not save or even
7250  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7251  * do not currently need to store anything in that guest-allocated memory
7252  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7253  * argument is different from the VMXON pointer (which the spec says they do).
7254  */
7255 static int handle_vmon(struct kvm_vcpu *vcpu)
7256 {
7257         int ret;
7258         gpa_t vmptr;
7259         struct page *page;
7260         struct vcpu_vmx *vmx = to_vmx(vcpu);
7261         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7262                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7263
7264         /*
7265          * The Intel VMX Instruction Reference lists a bunch of bits that are
7266          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7267          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7268          * Otherwise, we should fail with #UD.  But most faulting conditions
7269          * have already been checked by hardware, prior to the VM-exit for
7270          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7271          * that bit set to 1 in non-root mode.
7272          */
7273         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7274                 kvm_queue_exception(vcpu, UD_VECTOR);
7275                 return 1;
7276         }
7277
7278         if (vmx->nested.vmxon) {
7279                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7280                 return kvm_skip_emulated_instruction(vcpu);
7281         }
7282
7283         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7284                         != VMXON_NEEDED_FEATURES) {
7285                 kvm_inject_gp(vcpu, 0);
7286                 return 1;
7287         }
7288
7289         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7290                 return 1;
7291
7292         /*
7293          * SDM 3: 24.11.5
7294          * The first 4 bytes of VMXON region contain the supported
7295          * VMCS revision identifier
7296          *
7297          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7298          * which replaces physical address width with 32
7299          */
7300         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7301                 nested_vmx_failInvalid(vcpu);
7302                 return kvm_skip_emulated_instruction(vcpu);
7303         }
7304
7305         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7306         if (is_error_page(page)) {
7307                 nested_vmx_failInvalid(vcpu);
7308                 return kvm_skip_emulated_instruction(vcpu);
7309         }
7310         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7311                 kunmap(page);
7312                 kvm_release_page_clean(page);
7313                 nested_vmx_failInvalid(vcpu);
7314                 return kvm_skip_emulated_instruction(vcpu);
7315         }
7316         kunmap(page);
7317         kvm_release_page_clean(page);
7318
7319         vmx->nested.vmxon_ptr = vmptr;
7320         ret = enter_vmx_operation(vcpu);
7321         if (ret)
7322                 return ret;
7323
7324         nested_vmx_succeed(vcpu);
7325         return kvm_skip_emulated_instruction(vcpu);
7326 }
7327
7328 /*
7329  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7330  * for running VMX instructions (except VMXON, whose prerequisites are
7331  * slightly different). It also specifies what exception to inject otherwise.
7332  * Note that many of these exceptions have priority over VM exits, so they
7333  * don't have to be checked again here.
7334  */
7335 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7336 {
7337         if (!to_vmx(vcpu)->nested.vmxon) {
7338                 kvm_queue_exception(vcpu, UD_VECTOR);
7339                 return 0;
7340         }
7341         return 1;
7342 }
7343
7344 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7345 {
7346         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7347         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7348 }
7349
7350 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7351 {
7352         if (vmx->nested.current_vmptr == -1ull)
7353                 return;
7354
7355         if (enable_shadow_vmcs) {
7356                 /* copy to memory all shadowed fields in case
7357                    they were modified */
7358                 copy_shadow_to_vmcs12(vmx);
7359                 vmx->nested.sync_shadow_vmcs = false;
7360                 vmx_disable_shadow_vmcs(vmx);
7361         }
7362         vmx->nested.posted_intr_nv = -1;
7363
7364         /* Flush VMCS12 to guest memory */
7365         kvm_vcpu_write_guest_page(&vmx->vcpu,
7366                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7367                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7368
7369         vmx->nested.current_vmptr = -1ull;
7370 }
7371
7372 /*
7373  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7374  * just stops using VMX.
7375  */
7376 static void free_nested(struct vcpu_vmx *vmx)
7377 {
7378         if (!vmx->nested.vmxon)
7379                 return;
7380
7381         vmx->nested.vmxon = false;
7382         free_vpid(vmx->nested.vpid02);
7383         vmx->nested.posted_intr_nv = -1;
7384         vmx->nested.current_vmptr = -1ull;
7385         if (vmx->nested.msr_bitmap) {
7386                 free_page((unsigned long)vmx->nested.msr_bitmap);
7387                 vmx->nested.msr_bitmap = NULL;
7388         }
7389         if (enable_shadow_vmcs) {
7390                 vmx_disable_shadow_vmcs(vmx);
7391                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7392                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7393                 vmx->vmcs01.shadow_vmcs = NULL;
7394         }
7395         kfree(vmx->nested.cached_vmcs12);
7396         /* Unpin physical memory we referred to in current vmcs02 */
7397         if (vmx->nested.apic_access_page) {
7398                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7399                 vmx->nested.apic_access_page = NULL;
7400         }
7401         if (vmx->nested.virtual_apic_page) {
7402                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7403                 vmx->nested.virtual_apic_page = NULL;
7404         }
7405         if (vmx->nested.pi_desc_page) {
7406                 kunmap(vmx->nested.pi_desc_page);
7407                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7408                 vmx->nested.pi_desc_page = NULL;
7409                 vmx->nested.pi_desc = NULL;
7410         }
7411
7412         nested_free_all_saved_vmcss(vmx);
7413 }
7414
7415 /* Emulate the VMXOFF instruction */
7416 static int handle_vmoff(struct kvm_vcpu *vcpu)
7417 {
7418         if (!nested_vmx_check_permission(vcpu))
7419                 return 1;
7420         free_nested(to_vmx(vcpu));
7421         nested_vmx_succeed(vcpu);
7422         return kvm_skip_emulated_instruction(vcpu);
7423 }
7424
7425 /* Emulate the VMCLEAR instruction */
7426 static int handle_vmclear(struct kvm_vcpu *vcpu)
7427 {
7428         struct vcpu_vmx *vmx = to_vmx(vcpu);
7429         u32 zero = 0;
7430         gpa_t vmptr;
7431
7432         if (!nested_vmx_check_permission(vcpu))
7433                 return 1;
7434
7435         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7436                 return 1;
7437
7438         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7439                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7440                 return kvm_skip_emulated_instruction(vcpu);
7441         }
7442
7443         if (vmptr == vmx->nested.vmxon_ptr) {
7444                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7445                 return kvm_skip_emulated_instruction(vcpu);
7446         }
7447
7448         if (vmptr == vmx->nested.current_vmptr)
7449                 nested_release_vmcs12(vmx);
7450
7451         kvm_vcpu_write_guest(vcpu,
7452                         vmptr + offsetof(struct vmcs12, launch_state),
7453                         &zero, sizeof(zero));
7454
7455         nested_free_vmcs02(vmx, vmptr);
7456
7457         nested_vmx_succeed(vcpu);
7458         return kvm_skip_emulated_instruction(vcpu);
7459 }
7460
7461 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7462
7463 /* Emulate the VMLAUNCH instruction */
7464 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7465 {
7466         return nested_vmx_run(vcpu, true);
7467 }
7468
7469 /* Emulate the VMRESUME instruction */
7470 static int handle_vmresume(struct kvm_vcpu *vcpu)
7471 {
7472
7473         return nested_vmx_run(vcpu, false);
7474 }
7475
7476 /*
7477  * Read a vmcs12 field. Since these can have varying lengths and we return
7478  * one type, we chose the biggest type (u64) and zero-extend the return value
7479  * to that size. Note that the caller, handle_vmread, might need to use only
7480  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7481  * 64-bit fields are to be returned).
7482  */
7483 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7484                                   unsigned long field, u64 *ret)
7485 {
7486         short offset = vmcs_field_to_offset(field);
7487         char *p;
7488
7489         if (offset < 0)
7490                 return offset;
7491
7492         p = ((char *)(get_vmcs12(vcpu))) + offset;
7493
7494         switch (vmcs_field_type(field)) {
7495         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7496                 *ret = *((natural_width *)p);
7497                 return 0;
7498         case VMCS_FIELD_TYPE_U16:
7499                 *ret = *((u16 *)p);
7500                 return 0;
7501         case VMCS_FIELD_TYPE_U32:
7502                 *ret = *((u32 *)p);
7503                 return 0;
7504         case VMCS_FIELD_TYPE_U64:
7505                 *ret = *((u64 *)p);
7506                 return 0;
7507         default:
7508                 WARN_ON(1);
7509                 return -ENOENT;
7510         }
7511 }
7512
7513
7514 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7515                                    unsigned long field, u64 field_value){
7516         short offset = vmcs_field_to_offset(field);
7517         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7518         if (offset < 0)
7519                 return offset;
7520
7521         switch (vmcs_field_type(field)) {
7522         case VMCS_FIELD_TYPE_U16:
7523                 *(u16 *)p = field_value;
7524                 return 0;
7525         case VMCS_FIELD_TYPE_U32:
7526                 *(u32 *)p = field_value;
7527                 return 0;
7528         case VMCS_FIELD_TYPE_U64:
7529                 *(u64 *)p = field_value;
7530                 return 0;
7531         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7532                 *(natural_width *)p = field_value;
7533                 return 0;
7534         default:
7535                 WARN_ON(1);
7536                 return -ENOENT;
7537         }
7538
7539 }
7540
7541 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7542 {
7543         int i;
7544         unsigned long field;
7545         u64 field_value;
7546         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7547         const unsigned long *fields = shadow_read_write_fields;
7548         const int num_fields = max_shadow_read_write_fields;
7549
7550         preempt_disable();
7551
7552         vmcs_load(shadow_vmcs);
7553
7554         for (i = 0; i < num_fields; i++) {
7555                 field = fields[i];
7556                 switch (vmcs_field_type(field)) {
7557                 case VMCS_FIELD_TYPE_U16:
7558                         field_value = vmcs_read16(field);
7559                         break;
7560                 case VMCS_FIELD_TYPE_U32:
7561                         field_value = vmcs_read32(field);
7562                         break;
7563                 case VMCS_FIELD_TYPE_U64:
7564                         field_value = vmcs_read64(field);
7565                         break;
7566                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7567                         field_value = vmcs_readl(field);
7568                         break;
7569                 default:
7570                         WARN_ON(1);
7571                         continue;
7572                 }
7573                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7574         }
7575
7576         vmcs_clear(shadow_vmcs);
7577         vmcs_load(vmx->loaded_vmcs->vmcs);
7578
7579         preempt_enable();
7580 }
7581
7582 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7583 {
7584         const unsigned long *fields[] = {
7585                 shadow_read_write_fields,
7586                 shadow_read_only_fields
7587         };
7588         const int max_fields[] = {
7589                 max_shadow_read_write_fields,
7590                 max_shadow_read_only_fields
7591         };
7592         int i, q;
7593         unsigned long field;
7594         u64 field_value = 0;
7595         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7596
7597         vmcs_load(shadow_vmcs);
7598
7599         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7600                 for (i = 0; i < max_fields[q]; i++) {
7601                         field = fields[q][i];
7602                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7603
7604                         switch (vmcs_field_type(field)) {
7605                         case VMCS_FIELD_TYPE_U16:
7606                                 vmcs_write16(field, (u16)field_value);
7607                                 break;
7608                         case VMCS_FIELD_TYPE_U32:
7609                                 vmcs_write32(field, (u32)field_value);
7610                                 break;
7611                         case VMCS_FIELD_TYPE_U64:
7612                                 vmcs_write64(field, (u64)field_value);
7613                                 break;
7614                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7615                                 vmcs_writel(field, (long)field_value);
7616                                 break;
7617                         default:
7618                                 WARN_ON(1);
7619                                 break;
7620                         }
7621                 }
7622         }
7623
7624         vmcs_clear(shadow_vmcs);
7625         vmcs_load(vmx->loaded_vmcs->vmcs);
7626 }
7627
7628 /*
7629  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7630  * used before) all generate the same failure when it is missing.
7631  */
7632 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7633 {
7634         struct vcpu_vmx *vmx = to_vmx(vcpu);
7635         if (vmx->nested.current_vmptr == -1ull) {
7636                 nested_vmx_failInvalid(vcpu);
7637                 return 0;
7638         }
7639         return 1;
7640 }
7641
7642 static int handle_vmread(struct kvm_vcpu *vcpu)
7643 {
7644         unsigned long field;
7645         u64 field_value;
7646         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7647         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7648         gva_t gva = 0;
7649
7650         if (!nested_vmx_check_permission(vcpu))
7651                 return 1;
7652
7653         if (!nested_vmx_check_vmcs12(vcpu))
7654                 return kvm_skip_emulated_instruction(vcpu);
7655
7656         /* Decode instruction info and find the field to read */
7657         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7658         /* Read the field, zero-extended to a u64 field_value */
7659         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7660                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7661                 return kvm_skip_emulated_instruction(vcpu);
7662         }
7663         /*
7664          * Now copy part of this value to register or memory, as requested.
7665          * Note that the number of bits actually copied is 32 or 64 depending
7666          * on the guest's mode (32 or 64 bit), not on the given field's length.
7667          */
7668         if (vmx_instruction_info & (1u << 10)) {
7669                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7670                         field_value);
7671         } else {
7672                 if (get_vmx_mem_address(vcpu, exit_qualification,
7673                                 vmx_instruction_info, true, &gva))
7674                         return 1;
7675                 /* _system ok, as hardware has verified cpl=0 */
7676                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7677                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7678         }
7679
7680         nested_vmx_succeed(vcpu);
7681         return kvm_skip_emulated_instruction(vcpu);
7682 }
7683
7684
7685 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7686 {
7687         unsigned long field;
7688         gva_t gva;
7689         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7690         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7691         /* The value to write might be 32 or 64 bits, depending on L1's long
7692          * mode, and eventually we need to write that into a field of several
7693          * possible lengths. The code below first zero-extends the value to 64
7694          * bit (field_value), and then copies only the appropriate number of
7695          * bits into the vmcs12 field.
7696          */
7697         u64 field_value = 0;
7698         struct x86_exception e;
7699
7700         if (!nested_vmx_check_permission(vcpu))
7701                 return 1;
7702
7703         if (!nested_vmx_check_vmcs12(vcpu))
7704                 return kvm_skip_emulated_instruction(vcpu);
7705
7706         if (vmx_instruction_info & (1u << 10))
7707                 field_value = kvm_register_readl(vcpu,
7708                         (((vmx_instruction_info) >> 3) & 0xf));
7709         else {
7710                 if (get_vmx_mem_address(vcpu, exit_qualification,
7711                                 vmx_instruction_info, false, &gva))
7712                         return 1;
7713                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7714                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7715                         kvm_inject_page_fault(vcpu, &e);
7716                         return 1;
7717                 }
7718         }
7719
7720
7721         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7722         if (vmcs_field_readonly(field)) {
7723                 nested_vmx_failValid(vcpu,
7724                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7725                 return kvm_skip_emulated_instruction(vcpu);
7726         }
7727
7728         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7729                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7730                 return kvm_skip_emulated_instruction(vcpu);
7731         }
7732
7733         nested_vmx_succeed(vcpu);
7734         return kvm_skip_emulated_instruction(vcpu);
7735 }
7736
7737 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7738 {
7739         vmx->nested.current_vmptr = vmptr;
7740         if (enable_shadow_vmcs) {
7741                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7742                               SECONDARY_EXEC_SHADOW_VMCS);
7743                 vmcs_write64(VMCS_LINK_POINTER,
7744                              __pa(vmx->vmcs01.shadow_vmcs));
7745                 vmx->nested.sync_shadow_vmcs = true;
7746         }
7747 }
7748
7749 /* Emulate the VMPTRLD instruction */
7750 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7751 {
7752         struct vcpu_vmx *vmx = to_vmx(vcpu);
7753         gpa_t vmptr;
7754
7755         if (!nested_vmx_check_permission(vcpu))
7756                 return 1;
7757
7758         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7759                 return 1;
7760
7761         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7762                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7763                 return kvm_skip_emulated_instruction(vcpu);
7764         }
7765
7766         if (vmptr == vmx->nested.vmxon_ptr) {
7767                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7768                 return kvm_skip_emulated_instruction(vcpu);
7769         }
7770
7771         if (vmx->nested.current_vmptr != vmptr) {
7772                 struct vmcs12 *new_vmcs12;
7773                 struct page *page;
7774                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7775                 if (is_error_page(page)) {
7776                         nested_vmx_failInvalid(vcpu);
7777                         return kvm_skip_emulated_instruction(vcpu);
7778                 }
7779                 new_vmcs12 = kmap(page);
7780                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7781                         kunmap(page);
7782                         kvm_release_page_clean(page);
7783                         nested_vmx_failValid(vcpu,
7784                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7785                         return kvm_skip_emulated_instruction(vcpu);
7786                 }
7787
7788                 nested_release_vmcs12(vmx);
7789                 /*
7790                  * Load VMCS12 from guest memory since it is not already
7791                  * cached.
7792                  */
7793                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7794                 kunmap(page);
7795                 kvm_release_page_clean(page);
7796
7797                 set_current_vmptr(vmx, vmptr);
7798         }
7799
7800         nested_vmx_succeed(vcpu);
7801         return kvm_skip_emulated_instruction(vcpu);
7802 }
7803
7804 /* Emulate the VMPTRST instruction */
7805 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7806 {
7807         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7808         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7809         gva_t vmcs_gva;
7810         struct x86_exception e;
7811
7812         if (!nested_vmx_check_permission(vcpu))
7813                 return 1;
7814
7815         if (get_vmx_mem_address(vcpu, exit_qualification,
7816                         vmx_instruction_info, true, &vmcs_gva))
7817                 return 1;
7818         /* ok to use *_system, as hardware has verified cpl=0 */
7819         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7820                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7821                                  sizeof(u64), &e)) {
7822                 kvm_inject_page_fault(vcpu, &e);
7823                 return 1;
7824         }
7825         nested_vmx_succeed(vcpu);
7826         return kvm_skip_emulated_instruction(vcpu);
7827 }
7828
7829 /* Emulate the INVEPT instruction */
7830 static int handle_invept(struct kvm_vcpu *vcpu)
7831 {
7832         struct vcpu_vmx *vmx = to_vmx(vcpu);
7833         u32 vmx_instruction_info, types;
7834         unsigned long type;
7835         gva_t gva;
7836         struct x86_exception e;
7837         struct {
7838                 u64 eptp, gpa;
7839         } operand;
7840
7841         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7842               SECONDARY_EXEC_ENABLE_EPT) ||
7843             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7844                 kvm_queue_exception(vcpu, UD_VECTOR);
7845                 return 1;
7846         }
7847
7848         if (!nested_vmx_check_permission(vcpu))
7849                 return 1;
7850
7851         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7852         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7853
7854         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7855
7856         if (type >= 32 || !(types & (1 << type))) {
7857                 nested_vmx_failValid(vcpu,
7858                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7859                 return kvm_skip_emulated_instruction(vcpu);
7860         }
7861
7862         /* According to the Intel VMX instruction reference, the memory
7863          * operand is read even if it isn't needed (e.g., for type==global)
7864          */
7865         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7866                         vmx_instruction_info, false, &gva))
7867                 return 1;
7868         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7869                                 sizeof(operand), &e)) {
7870                 kvm_inject_page_fault(vcpu, &e);
7871                 return 1;
7872         }
7873
7874         switch (type) {
7875         case VMX_EPT_EXTENT_GLOBAL:
7876         /*
7877          * TODO: track mappings and invalidate
7878          * single context requests appropriately
7879          */
7880         case VMX_EPT_EXTENT_CONTEXT:
7881                 kvm_mmu_sync_roots(vcpu);
7882                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7883                 nested_vmx_succeed(vcpu);
7884                 break;
7885         default:
7886                 BUG_ON(1);
7887                 break;
7888         }
7889
7890         return kvm_skip_emulated_instruction(vcpu);
7891 }
7892
7893 static int handle_invvpid(struct kvm_vcpu *vcpu)
7894 {
7895         struct vcpu_vmx *vmx = to_vmx(vcpu);
7896         u32 vmx_instruction_info;
7897         unsigned long type, types;
7898         gva_t gva;
7899         struct x86_exception e;
7900         struct {
7901                 u64 vpid;
7902                 u64 gla;
7903         } operand;
7904
7905         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7906               SECONDARY_EXEC_ENABLE_VPID) ||
7907                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7908                 kvm_queue_exception(vcpu, UD_VECTOR);
7909                 return 1;
7910         }
7911
7912         if (!nested_vmx_check_permission(vcpu))
7913                 return 1;
7914
7915         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7916         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7917
7918         types = (vmx->nested.nested_vmx_vpid_caps &
7919                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7920
7921         if (type >= 32 || !(types & (1 << type))) {
7922                 nested_vmx_failValid(vcpu,
7923                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7924                 return kvm_skip_emulated_instruction(vcpu);
7925         }
7926
7927         /* according to the intel vmx instruction reference, the memory
7928          * operand is read even if it isn't needed (e.g., for type==global)
7929          */
7930         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7931                         vmx_instruction_info, false, &gva))
7932                 return 1;
7933         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7934                                 sizeof(operand), &e)) {
7935                 kvm_inject_page_fault(vcpu, &e);
7936                 return 1;
7937         }
7938         if (operand.vpid >> 16) {
7939                 nested_vmx_failValid(vcpu,
7940                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7941                 return kvm_skip_emulated_instruction(vcpu);
7942         }
7943
7944         switch (type) {
7945         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7946                 if (is_noncanonical_address(operand.gla, vcpu)) {
7947                         nested_vmx_failValid(vcpu,
7948                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7949                         return kvm_skip_emulated_instruction(vcpu);
7950                 }
7951                 /* fall through */
7952         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7953         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7954                 if (!operand.vpid) {
7955                         nested_vmx_failValid(vcpu,
7956                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7957                         return kvm_skip_emulated_instruction(vcpu);
7958                 }
7959                 break;
7960         case VMX_VPID_EXTENT_ALL_CONTEXT:
7961                 break;
7962         default:
7963                 WARN_ON_ONCE(1);
7964                 return kvm_skip_emulated_instruction(vcpu);
7965         }
7966
7967         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7968         nested_vmx_succeed(vcpu);
7969
7970         return kvm_skip_emulated_instruction(vcpu);
7971 }
7972
7973 static int handle_pml_full(struct kvm_vcpu *vcpu)
7974 {
7975         unsigned long exit_qualification;
7976
7977         trace_kvm_pml_full(vcpu->vcpu_id);
7978
7979         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7980
7981         /*
7982          * PML buffer FULL happened while executing iret from NMI,
7983          * "blocked by NMI" bit has to be set before next VM entry.
7984          */
7985         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7986                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7987                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7988                                 GUEST_INTR_STATE_NMI);
7989
7990         /*
7991          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7992          * here.., and there's no userspace involvement needed for PML.
7993          */
7994         return 1;
7995 }
7996
7997 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7998 {
7999         kvm_lapic_expired_hv_timer(vcpu);
8000         return 1;
8001 }
8002
8003 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8004 {
8005         struct vcpu_vmx *vmx = to_vmx(vcpu);
8006         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8007
8008         /* Check for memory type validity */
8009         switch (address & VMX_EPTP_MT_MASK) {
8010         case VMX_EPTP_MT_UC:
8011                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8012                         return false;
8013                 break;
8014         case VMX_EPTP_MT_WB:
8015                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8016                         return false;
8017                 break;
8018         default:
8019                 return false;
8020         }
8021
8022         /* only 4 levels page-walk length are valid */
8023         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8024                 return false;
8025
8026         /* Reserved bits should not be set */
8027         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8028                 return false;
8029
8030         /* AD, if set, should be supported */
8031         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8032                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8033                         return false;
8034         }
8035
8036         return true;
8037 }
8038
8039 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8040                                      struct vmcs12 *vmcs12)
8041 {
8042         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8043         u64 address;
8044         bool accessed_dirty;
8045         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8046
8047         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8048             !nested_cpu_has_ept(vmcs12))
8049                 return 1;
8050
8051         if (index >= VMFUNC_EPTP_ENTRIES)
8052                 return 1;
8053
8054
8055         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8056                                      &address, index * 8, 8))
8057                 return 1;
8058
8059         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8060
8061         /*
8062          * If the (L2) guest does a vmfunc to the currently
8063          * active ept pointer, we don't have to do anything else
8064          */
8065         if (vmcs12->ept_pointer != address) {
8066                 if (!valid_ept_address(vcpu, address))
8067                         return 1;
8068
8069                 kvm_mmu_unload(vcpu);
8070                 mmu->ept_ad = accessed_dirty;
8071                 mmu->base_role.ad_disabled = !accessed_dirty;
8072                 vmcs12->ept_pointer = address;
8073                 /*
8074                  * TODO: Check what's the correct approach in case
8075                  * mmu reload fails. Currently, we just let the next
8076                  * reload potentially fail
8077                  */
8078                 kvm_mmu_reload(vcpu);
8079         }
8080
8081         return 0;
8082 }
8083
8084 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8085 {
8086         struct vcpu_vmx *vmx = to_vmx(vcpu);
8087         struct vmcs12 *vmcs12;
8088         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8089
8090         /*
8091          * VMFUNC is only supported for nested guests, but we always enable the
8092          * secondary control for simplicity; for non-nested mode, fake that we
8093          * didn't by injecting #UD.
8094          */
8095         if (!is_guest_mode(vcpu)) {
8096                 kvm_queue_exception(vcpu, UD_VECTOR);
8097                 return 1;
8098         }
8099
8100         vmcs12 = get_vmcs12(vcpu);
8101         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8102                 goto fail;
8103
8104         switch (function) {
8105         case 0:
8106                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8107                         goto fail;
8108                 break;
8109         default:
8110                 goto fail;
8111         }
8112         return kvm_skip_emulated_instruction(vcpu);
8113
8114 fail:
8115         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8116                           vmcs_read32(VM_EXIT_INTR_INFO),
8117                           vmcs_readl(EXIT_QUALIFICATION));
8118         return 1;
8119 }
8120
8121 /*
8122  * The exit handlers return 1 if the exit was handled fully and guest execution
8123  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8124  * to be done to userspace and return 0.
8125  */
8126 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8127         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8128         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8129         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8130         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8131         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8132         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8133         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8134         [EXIT_REASON_CPUID]                   = handle_cpuid,
8135         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8136         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8137         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8138         [EXIT_REASON_HLT]                     = handle_halt,
8139         [EXIT_REASON_INVD]                    = handle_invd,
8140         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8141         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8142         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8143         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8144         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8145         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8146         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8147         [EXIT_REASON_VMREAD]                  = handle_vmread,
8148         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8149         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8150         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8151         [EXIT_REASON_VMON]                    = handle_vmon,
8152         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8153         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8154         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8155         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8156         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8157         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8158         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8159         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8160         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8161         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8162         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8163         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8164         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8165         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8166         [EXIT_REASON_INVEPT]                  = handle_invept,
8167         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8168         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8169         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8170         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8171         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8172         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8173         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8174         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8175 };
8176
8177 static const int kvm_vmx_max_exit_handlers =
8178         ARRAY_SIZE(kvm_vmx_exit_handlers);
8179
8180 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8181                                        struct vmcs12 *vmcs12)
8182 {
8183         unsigned long exit_qualification;
8184         gpa_t bitmap, last_bitmap;
8185         unsigned int port;
8186         int size;
8187         u8 b;
8188
8189         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8190                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8191
8192         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8193
8194         port = exit_qualification >> 16;
8195         size = (exit_qualification & 7) + 1;
8196
8197         last_bitmap = (gpa_t)-1;
8198         b = -1;
8199
8200         while (size > 0) {
8201                 if (port < 0x8000)
8202                         bitmap = vmcs12->io_bitmap_a;
8203                 else if (port < 0x10000)
8204                         bitmap = vmcs12->io_bitmap_b;
8205                 else
8206                         return true;
8207                 bitmap += (port & 0x7fff) / 8;
8208
8209                 if (last_bitmap != bitmap)
8210                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8211                                 return true;
8212                 if (b & (1 << (port & 7)))
8213                         return true;
8214
8215                 port++;
8216                 size--;
8217                 last_bitmap = bitmap;
8218         }
8219
8220         return false;
8221 }
8222
8223 /*
8224  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8225  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8226  * disinterest in the current event (read or write a specific MSR) by using an
8227  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8228  */
8229 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8230         struct vmcs12 *vmcs12, u32 exit_reason)
8231 {
8232         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8233         gpa_t bitmap;
8234
8235         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8236                 return true;
8237
8238         /*
8239          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8240          * for the four combinations of read/write and low/high MSR numbers.
8241          * First we need to figure out which of the four to use:
8242          */
8243         bitmap = vmcs12->msr_bitmap;
8244         if (exit_reason == EXIT_REASON_MSR_WRITE)
8245                 bitmap += 2048;
8246         if (msr_index >= 0xc0000000) {
8247                 msr_index -= 0xc0000000;
8248                 bitmap += 1024;
8249         }
8250
8251         /* Then read the msr_index'th bit from this bitmap: */
8252         if (msr_index < 1024*8) {
8253                 unsigned char b;
8254                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8255                         return true;
8256                 return 1 & (b >> (msr_index & 7));
8257         } else
8258                 return true; /* let L1 handle the wrong parameter */
8259 }
8260
8261 /*
8262  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8263  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8264  * intercept (via guest_host_mask etc.) the current event.
8265  */
8266 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8267         struct vmcs12 *vmcs12)
8268 {
8269         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8270         int cr = exit_qualification & 15;
8271         int reg;
8272         unsigned long val;
8273
8274         switch ((exit_qualification >> 4) & 3) {
8275         case 0: /* mov to cr */
8276                 reg = (exit_qualification >> 8) & 15;
8277                 val = kvm_register_readl(vcpu, reg);
8278                 switch (cr) {
8279                 case 0:
8280                         if (vmcs12->cr0_guest_host_mask &
8281                             (val ^ vmcs12->cr0_read_shadow))
8282                                 return true;
8283                         break;
8284                 case 3:
8285                         if ((vmcs12->cr3_target_count >= 1 &&
8286                                         vmcs12->cr3_target_value0 == val) ||
8287                                 (vmcs12->cr3_target_count >= 2 &&
8288                                         vmcs12->cr3_target_value1 == val) ||
8289                                 (vmcs12->cr3_target_count >= 3 &&
8290                                         vmcs12->cr3_target_value2 == val) ||
8291                                 (vmcs12->cr3_target_count >= 4 &&
8292                                         vmcs12->cr3_target_value3 == val))
8293                                 return false;
8294                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8295                                 return true;
8296                         break;
8297                 case 4:
8298                         if (vmcs12->cr4_guest_host_mask &
8299                             (vmcs12->cr4_read_shadow ^ val))
8300                                 return true;
8301                         break;
8302                 case 8:
8303                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8304                                 return true;
8305                         break;
8306                 }
8307                 break;
8308         case 2: /* clts */
8309                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8310                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8311                         return true;
8312                 break;
8313         case 1: /* mov from cr */
8314                 switch (cr) {
8315                 case 3:
8316                         if (vmcs12->cpu_based_vm_exec_control &
8317                             CPU_BASED_CR3_STORE_EXITING)
8318                                 return true;
8319                         break;
8320                 case 8:
8321                         if (vmcs12->cpu_based_vm_exec_control &
8322                             CPU_BASED_CR8_STORE_EXITING)
8323                                 return true;
8324                         break;
8325                 }
8326                 break;
8327         case 3: /* lmsw */
8328                 /*
8329                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8330                  * cr0. Other attempted changes are ignored, with no exit.
8331                  */
8332                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8333                 if (vmcs12->cr0_guest_host_mask & 0xe &
8334                     (val ^ vmcs12->cr0_read_shadow))
8335                         return true;
8336                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8337                     !(vmcs12->cr0_read_shadow & 0x1) &&
8338                     (val & 0x1))
8339                         return true;
8340                 break;
8341         }
8342         return false;
8343 }
8344
8345 /*
8346  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8347  * should handle it ourselves in L0 (and then continue L2). Only call this
8348  * when in is_guest_mode (L2).
8349  */
8350 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8351 {
8352         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8353         struct vcpu_vmx *vmx = to_vmx(vcpu);
8354         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8355
8356         if (vmx->nested.nested_run_pending)
8357                 return false;
8358
8359         if (unlikely(vmx->fail)) {
8360                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8361                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8362                 return true;
8363         }
8364
8365         /*
8366          * The host physical addresses of some pages of guest memory
8367          * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8368          * may write to these pages via their host physical address while
8369          * L2 is running, bypassing any address-translation-based dirty
8370          * tracking (e.g. EPT write protection).
8371          *
8372          * Mark them dirty on every exit from L2 to prevent them from
8373          * getting out of sync with dirty tracking.
8374          */
8375         nested_mark_vmcs12_pages_dirty(vcpu);
8376
8377         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8378                                 vmcs_readl(EXIT_QUALIFICATION),
8379                                 vmx->idt_vectoring_info,
8380                                 intr_info,
8381                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8382                                 KVM_ISA_VMX);
8383
8384         switch (exit_reason) {
8385         case EXIT_REASON_EXCEPTION_NMI:
8386                 if (is_nmi(intr_info))
8387                         return false;
8388                 else if (is_page_fault(intr_info))
8389                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8390                 else if (is_no_device(intr_info) &&
8391                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8392                         return false;
8393                 else if (is_debug(intr_info) &&
8394                          vcpu->guest_debug &
8395                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8396                         return false;
8397                 else if (is_breakpoint(intr_info) &&
8398                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8399                         return false;
8400                 return vmcs12->exception_bitmap &
8401                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8402         case EXIT_REASON_EXTERNAL_INTERRUPT:
8403                 return false;
8404         case EXIT_REASON_TRIPLE_FAULT:
8405                 return true;
8406         case EXIT_REASON_PENDING_INTERRUPT:
8407                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8408         case EXIT_REASON_NMI_WINDOW:
8409                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8410         case EXIT_REASON_TASK_SWITCH:
8411                 return true;
8412         case EXIT_REASON_CPUID:
8413                 return true;
8414         case EXIT_REASON_HLT:
8415                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8416         case EXIT_REASON_INVD:
8417                 return true;
8418         case EXIT_REASON_INVLPG:
8419                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8420         case EXIT_REASON_RDPMC:
8421                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8422         case EXIT_REASON_RDRAND:
8423                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8424         case EXIT_REASON_RDSEED:
8425                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8426         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8427                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8428         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8429         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8430         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8431         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8432         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8433         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8434                 /*
8435                  * VMX instructions trap unconditionally. This allows L1 to
8436                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8437                  */
8438                 return true;
8439         case EXIT_REASON_CR_ACCESS:
8440                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8441         case EXIT_REASON_DR_ACCESS:
8442                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8443         case EXIT_REASON_IO_INSTRUCTION:
8444                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8445         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8446                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8447         case EXIT_REASON_MSR_READ:
8448         case EXIT_REASON_MSR_WRITE:
8449                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8450         case EXIT_REASON_INVALID_STATE:
8451                 return true;
8452         case EXIT_REASON_MWAIT_INSTRUCTION:
8453                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8454         case EXIT_REASON_MONITOR_TRAP_FLAG:
8455                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8456         case EXIT_REASON_MONITOR_INSTRUCTION:
8457                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8458         case EXIT_REASON_PAUSE_INSTRUCTION:
8459                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8460                         nested_cpu_has2(vmcs12,
8461                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8462         case EXIT_REASON_MCE_DURING_VMENTRY:
8463                 return false;
8464         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8465                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8466         case EXIT_REASON_APIC_ACCESS:
8467                 return nested_cpu_has2(vmcs12,
8468                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8469         case EXIT_REASON_APIC_WRITE:
8470         case EXIT_REASON_EOI_INDUCED:
8471                 /* apic_write and eoi_induced should exit unconditionally. */
8472                 return true;
8473         case EXIT_REASON_EPT_VIOLATION:
8474                 /*
8475                  * L0 always deals with the EPT violation. If nested EPT is
8476                  * used, and the nested mmu code discovers that the address is
8477                  * missing in the guest EPT table (EPT12), the EPT violation
8478                  * will be injected with nested_ept_inject_page_fault()
8479                  */
8480                 return false;
8481         case EXIT_REASON_EPT_MISCONFIG:
8482                 /*
8483                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8484                  * table (shadow on EPT) or a merged EPT table that L0 built
8485                  * (EPT on EPT). So any problems with the structure of the
8486                  * table is L0's fault.
8487                  */
8488                 return false;
8489         case EXIT_REASON_INVPCID:
8490                 return
8491                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8492                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8493         case EXIT_REASON_WBINVD:
8494                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8495         case EXIT_REASON_XSETBV:
8496                 return true;
8497         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8498                 /*
8499                  * This should never happen, since it is not possible to
8500                  * set XSS to a non-zero value---neither in L1 nor in L2.
8501                  * If if it were, XSS would have to be checked against
8502                  * the XSS exit bitmap in vmcs12.
8503                  */
8504                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8505         case EXIT_REASON_PREEMPTION_TIMER:
8506                 return false;
8507         case EXIT_REASON_PML_FULL:
8508                 /* We emulate PML support to L1. */
8509                 return false;
8510         case EXIT_REASON_VMFUNC:
8511                 /* VM functions are emulated through L2->L0 vmexits. */
8512                 return false;
8513         default:
8514                 return true;
8515         }
8516 }
8517
8518 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8519 {
8520         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8521
8522         /*
8523          * At this point, the exit interruption info in exit_intr_info
8524          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8525          * we need to query the in-kernel LAPIC.
8526          */
8527         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8528         if ((exit_intr_info &
8529              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8530             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8531                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8532                 vmcs12->vm_exit_intr_error_code =
8533                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8534         }
8535
8536         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8537                           vmcs_readl(EXIT_QUALIFICATION));
8538         return 1;
8539 }
8540
8541 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8542 {
8543         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8544         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8545 }
8546
8547 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8548 {
8549         if (vmx->pml_pg) {
8550                 __free_page(vmx->pml_pg);
8551                 vmx->pml_pg = NULL;
8552         }
8553 }
8554
8555 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8556 {
8557         struct vcpu_vmx *vmx = to_vmx(vcpu);
8558         u64 *pml_buf;
8559         u16 pml_idx;
8560
8561         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8562
8563         /* Do nothing if PML buffer is empty */
8564         if (pml_idx == (PML_ENTITY_NUM - 1))
8565                 return;
8566
8567         /* PML index always points to next available PML buffer entity */
8568         if (pml_idx >= PML_ENTITY_NUM)
8569                 pml_idx = 0;
8570         else
8571                 pml_idx++;
8572
8573         pml_buf = page_address(vmx->pml_pg);
8574         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8575                 u64 gpa;
8576
8577                 gpa = pml_buf[pml_idx];
8578                 WARN_ON(gpa & (PAGE_SIZE - 1));
8579                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8580         }
8581
8582         /* reset PML index */
8583         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8584 }
8585
8586 /*
8587  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8588  * Called before reporting dirty_bitmap to userspace.
8589  */
8590 static void kvm_flush_pml_buffers(struct kvm *kvm)
8591 {
8592         int i;
8593         struct kvm_vcpu *vcpu;
8594         /*
8595          * We only need to kick vcpu out of guest mode here, as PML buffer
8596          * is flushed at beginning of all VMEXITs, and it's obvious that only
8597          * vcpus running in guest are possible to have unflushed GPAs in PML
8598          * buffer.
8599          */
8600         kvm_for_each_vcpu(i, vcpu, kvm)
8601                 kvm_vcpu_kick(vcpu);
8602 }
8603
8604 static void vmx_dump_sel(char *name, uint32_t sel)
8605 {
8606         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8607                name, vmcs_read16(sel),
8608                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8609                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8610                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8611 }
8612
8613 static void vmx_dump_dtsel(char *name, uint32_t limit)
8614 {
8615         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8616                name, vmcs_read32(limit),
8617                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8618 }
8619
8620 static void dump_vmcs(void)
8621 {
8622         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8623         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8624         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8625         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8626         u32 secondary_exec_control = 0;
8627         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8628         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8629         int i, n;
8630
8631         if (cpu_has_secondary_exec_ctrls())
8632                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8633
8634         pr_err("*** Guest State ***\n");
8635         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8636                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8637                vmcs_readl(CR0_GUEST_HOST_MASK));
8638         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8639                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8640         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8641         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8642             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8643         {
8644                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8645                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8646                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8647                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8648         }
8649         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8650                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8651         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8652                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8653         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8654                vmcs_readl(GUEST_SYSENTER_ESP),
8655                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8656         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8657         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8658         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8659         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8660         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8661         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8662         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8663         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8664         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8665         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8666         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8667             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8668                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8669                        efer, vmcs_read64(GUEST_IA32_PAT));
8670         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8671                vmcs_read64(GUEST_IA32_DEBUGCTL),
8672                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8673         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8674                 pr_err("PerfGlobCtl = 0x%016llx\n",
8675                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8676         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8677                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8678         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8679                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8680                vmcs_read32(GUEST_ACTIVITY_STATE));
8681         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8682                 pr_err("InterruptStatus = %04x\n",
8683                        vmcs_read16(GUEST_INTR_STATUS));
8684
8685         pr_err("*** Host State ***\n");
8686         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8687                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8688         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8689                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8690                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8691                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8692                vmcs_read16(HOST_TR_SELECTOR));
8693         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8694                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8695                vmcs_readl(HOST_TR_BASE));
8696         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8697                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8698         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8699                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8700                vmcs_readl(HOST_CR4));
8701         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8702                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8703                vmcs_read32(HOST_IA32_SYSENTER_CS),
8704                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8705         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8706                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8707                        vmcs_read64(HOST_IA32_EFER),
8708                        vmcs_read64(HOST_IA32_PAT));
8709         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8710                 pr_err("PerfGlobCtl = 0x%016llx\n",
8711                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8712
8713         pr_err("*** Control State ***\n");
8714         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8715                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8716         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8717         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8718                vmcs_read32(EXCEPTION_BITMAP),
8719                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8720                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8721         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8722                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8723                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8724                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8725         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8726                vmcs_read32(VM_EXIT_INTR_INFO),
8727                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8728                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8729         pr_err("        reason=%08x qualification=%016lx\n",
8730                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8731         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8732                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8733                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8734         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8735         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8736                 pr_err("TSC Multiplier = 0x%016llx\n",
8737                        vmcs_read64(TSC_MULTIPLIER));
8738         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8739                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8740         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8741                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8742         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8743                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8744         n = vmcs_read32(CR3_TARGET_COUNT);
8745         for (i = 0; i + 1 < n; i += 4)
8746                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8747                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8748                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8749         if (i < n)
8750                 pr_err("CR3 target%u=%016lx\n",
8751                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8752         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8753                 pr_err("PLE Gap=%08x Window=%08x\n",
8754                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8755         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8756                 pr_err("Virtual processor ID = 0x%04x\n",
8757                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8758 }
8759
8760 /*
8761  * The guest has exited.  See if we can fix it or if we need userspace
8762  * assistance.
8763  */
8764 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8765 {
8766         struct vcpu_vmx *vmx = to_vmx(vcpu);
8767         u32 exit_reason = vmx->exit_reason;
8768         u32 vectoring_info = vmx->idt_vectoring_info;
8769
8770         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8771
8772         /*
8773          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8774          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8775          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8776          * mode as if vcpus is in root mode, the PML buffer must has been
8777          * flushed already.
8778          */
8779         if (enable_pml)
8780                 vmx_flush_pml_buffer(vcpu);
8781
8782         /* If guest state is invalid, start emulating */
8783         if (vmx->emulation_required)
8784                 return handle_invalid_guest_state(vcpu);
8785
8786         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8787                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8788
8789         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8790                 dump_vmcs();
8791                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8792                 vcpu->run->fail_entry.hardware_entry_failure_reason
8793                         = exit_reason;
8794                 return 0;
8795         }
8796
8797         if (unlikely(vmx->fail)) {
8798                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8799                 vcpu->run->fail_entry.hardware_entry_failure_reason
8800                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8801                 return 0;
8802         }
8803
8804         /*
8805          * Note:
8806          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8807          * delivery event since it indicates guest is accessing MMIO.
8808          * The vm-exit can be triggered again after return to guest that
8809          * will cause infinite loop.
8810          */
8811         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8812                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8813                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8814                         exit_reason != EXIT_REASON_PML_FULL &&
8815                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8816                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8817                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8818                 vcpu->run->internal.ndata = 3;
8819                 vcpu->run->internal.data[0] = vectoring_info;
8820                 vcpu->run->internal.data[1] = exit_reason;
8821                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8822                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8823                         vcpu->run->internal.ndata++;
8824                         vcpu->run->internal.data[3] =
8825                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8826                 }
8827                 return 0;
8828         }
8829
8830         if (exit_reason < kvm_vmx_max_exit_handlers
8831             && kvm_vmx_exit_handlers[exit_reason])
8832                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8833         else {
8834                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8835                                 exit_reason);
8836                 kvm_queue_exception(vcpu, UD_VECTOR);
8837                 return 1;
8838         }
8839 }
8840
8841 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8842 {
8843         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8844
8845         if (is_guest_mode(vcpu) &&
8846                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8847                 return;
8848
8849         if (irr == -1 || tpr < irr) {
8850                 vmcs_write32(TPR_THRESHOLD, 0);
8851                 return;
8852         }
8853
8854         vmcs_write32(TPR_THRESHOLD, irr);
8855 }
8856
8857 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8858 {
8859         u32 sec_exec_control;
8860
8861         /* Postpone execution until vmcs01 is the current VMCS. */
8862         if (is_guest_mode(vcpu)) {
8863                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8864                 return;
8865         }
8866
8867         if (!cpu_has_vmx_virtualize_x2apic_mode())
8868                 return;
8869
8870         if (!cpu_need_tpr_shadow(vcpu))
8871                 return;
8872
8873         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8874
8875         if (set) {
8876                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8877                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8878         } else {
8879                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8880                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8881                 vmx_flush_tlb_ept_only(vcpu);
8882         }
8883         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8884
8885         vmx_set_msr_bitmap(vcpu);
8886 }
8887
8888 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8889 {
8890         struct vcpu_vmx *vmx = to_vmx(vcpu);
8891
8892         /*
8893          * Currently we do not handle the nested case where L2 has an
8894          * APIC access page of its own; that page is still pinned.
8895          * Hence, we skip the case where the VCPU is in guest mode _and_
8896          * L1 prepared an APIC access page for L2.
8897          *
8898          * For the case where L1 and L2 share the same APIC access page
8899          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8900          * in the vmcs12), this function will only update either the vmcs01
8901          * or the vmcs02.  If the former, the vmcs02 will be updated by
8902          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8903          * the next L2->L1 exit.
8904          */
8905         if (!is_guest_mode(vcpu) ||
8906             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8907                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8908                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8909                 vmx_flush_tlb_ept_only(vcpu);
8910         }
8911 }
8912
8913 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8914 {
8915         u16 status;
8916         u8 old;
8917
8918         if (max_isr == -1)
8919                 max_isr = 0;
8920
8921         status = vmcs_read16(GUEST_INTR_STATUS);
8922         old = status >> 8;
8923         if (max_isr != old) {
8924                 status &= 0xff;
8925                 status |= max_isr << 8;
8926                 vmcs_write16(GUEST_INTR_STATUS, status);
8927         }
8928 }
8929
8930 static void vmx_set_rvi(int vector)
8931 {
8932         u16 status;
8933         u8 old;
8934
8935         if (vector == -1)
8936                 vector = 0;
8937
8938         status = vmcs_read16(GUEST_INTR_STATUS);
8939         old = (u8)status & 0xff;
8940         if ((u8)vector != old) {
8941                 status &= ~0xff;
8942                 status |= (u8)vector;
8943                 vmcs_write16(GUEST_INTR_STATUS, status);
8944         }
8945 }
8946
8947 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8948 {
8949         if (!is_guest_mode(vcpu)) {
8950                 vmx_set_rvi(max_irr);
8951                 return;
8952         }
8953
8954         if (max_irr == -1)
8955                 return;
8956
8957         /*
8958          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8959          * handles it.
8960          */
8961         if (nested_exit_on_intr(vcpu))
8962                 return;
8963
8964         /*
8965          * Else, fall back to pre-APICv interrupt injection since L2
8966          * is run without virtual interrupt delivery.
8967          */
8968         if (!kvm_event_needs_reinjection(vcpu) &&
8969             vmx_interrupt_allowed(vcpu)) {
8970                 kvm_queue_interrupt(vcpu, max_irr, false);
8971                 vmx_inject_irq(vcpu);
8972         }
8973 }
8974
8975 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8976 {
8977         struct vcpu_vmx *vmx = to_vmx(vcpu);
8978         int max_irr;
8979
8980         WARN_ON(!vcpu->arch.apicv_active);
8981         if (pi_test_on(&vmx->pi_desc)) {
8982                 pi_clear_on(&vmx->pi_desc);
8983                 /*
8984                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8985                  * But on x86 this is just a compiler barrier anyway.
8986                  */
8987                 smp_mb__after_atomic();
8988                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8989         } else {
8990                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8991         }
8992         vmx_hwapic_irr_update(vcpu, max_irr);
8993         return max_irr;
8994 }
8995
8996 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8997 {
8998         if (!kvm_vcpu_apicv_active(vcpu))
8999                 return;
9000
9001         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9002         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9003         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9004         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9005 }
9006
9007 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9008 {
9009         struct vcpu_vmx *vmx = to_vmx(vcpu);
9010
9011         pi_clear_on(&vmx->pi_desc);
9012         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9013 }
9014
9015 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9016 {
9017         u32 exit_intr_info = 0;
9018         u16 basic_exit_reason = (u16)vmx->exit_reason;
9019
9020         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9021               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9022                 return;
9023
9024         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9025                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9026         vmx->exit_intr_info = exit_intr_info;
9027
9028         /* if exit due to PF check for async PF */
9029         if (is_page_fault(exit_intr_info))
9030                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9031
9032         /* Handle machine checks before interrupts are enabled */
9033         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9034             is_machine_check(exit_intr_info))
9035                 kvm_machine_check();
9036
9037         /* We need to handle NMIs before interrupts are enabled */
9038         if (is_nmi(exit_intr_info)) {
9039                 kvm_before_handle_nmi(&vmx->vcpu);
9040                 asm("int $2");
9041                 kvm_after_handle_nmi(&vmx->vcpu);
9042         }
9043 }
9044
9045 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9046 {
9047         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9048
9049         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9050                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9051                 unsigned int vector;
9052                 unsigned long entry;
9053                 gate_desc *desc;
9054                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9055 #ifdef CONFIG_X86_64
9056                 unsigned long tmp;
9057 #endif
9058
9059                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9060                 desc = (gate_desc *)vmx->host_idt_base + vector;
9061                 entry = gate_offset(desc);
9062                 asm volatile(
9063 #ifdef CONFIG_X86_64
9064                         "mov %%" _ASM_SP ", %[sp]\n\t"
9065                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9066                         "push $%c[ss]\n\t"
9067                         "push %[sp]\n\t"
9068 #endif
9069                         "pushf\n\t"
9070                         __ASM_SIZE(push) " $%c[cs]\n\t"
9071                         "call *%[entry]\n\t"
9072                         :
9073 #ifdef CONFIG_X86_64
9074                         [sp]"=&r"(tmp),
9075 #endif
9076                         ASM_CALL_CONSTRAINT
9077                         :
9078                         [entry]"r"(entry),
9079                         [ss]"i"(__KERNEL_DS),
9080                         [cs]"i"(__KERNEL_CS)
9081                         );
9082         }
9083 }
9084 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9085
9086 static bool vmx_has_high_real_mode_segbase(void)
9087 {
9088         return enable_unrestricted_guest || emulate_invalid_guest_state;
9089 }
9090
9091 static bool vmx_mpx_supported(void)
9092 {
9093         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9094                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9095 }
9096
9097 static bool vmx_xsaves_supported(void)
9098 {
9099         return vmcs_config.cpu_based_2nd_exec_ctrl &
9100                 SECONDARY_EXEC_XSAVES;
9101 }
9102
9103 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9104 {
9105         u32 exit_intr_info;
9106         bool unblock_nmi;
9107         u8 vector;
9108         bool idtv_info_valid;
9109
9110         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9111
9112         if (vmx->loaded_vmcs->nmi_known_unmasked)
9113                 return;
9114         /*
9115          * Can't use vmx->exit_intr_info since we're not sure what
9116          * the exit reason is.
9117          */
9118         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9119         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9120         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9121         /*
9122          * SDM 3: 27.7.1.2 (September 2008)
9123          * Re-set bit "block by NMI" before VM entry if vmexit caused by
9124          * a guest IRET fault.
9125          * SDM 3: 23.2.2 (September 2008)
9126          * Bit 12 is undefined in any of the following cases:
9127          *  If the VM exit sets the valid bit in the IDT-vectoring
9128          *   information field.
9129          *  If the VM exit is due to a double fault.
9130          */
9131         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9132             vector != DF_VECTOR && !idtv_info_valid)
9133                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9134                               GUEST_INTR_STATE_NMI);
9135         else
9136                 vmx->loaded_vmcs->nmi_known_unmasked =
9137                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9138                           & GUEST_INTR_STATE_NMI);
9139 }
9140
9141 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9142                                       u32 idt_vectoring_info,
9143                                       int instr_len_field,
9144                                       int error_code_field)
9145 {
9146         u8 vector;
9147         int type;
9148         bool idtv_info_valid;
9149
9150         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9151
9152         vcpu->arch.nmi_injected = false;
9153         kvm_clear_exception_queue(vcpu);
9154         kvm_clear_interrupt_queue(vcpu);
9155
9156         if (!idtv_info_valid)
9157                 return;
9158
9159         kvm_make_request(KVM_REQ_EVENT, vcpu);
9160
9161         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9162         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9163
9164         switch (type) {
9165         case INTR_TYPE_NMI_INTR:
9166                 vcpu->arch.nmi_injected = true;
9167                 /*
9168                  * SDM 3: 27.7.1.2 (September 2008)
9169                  * Clear bit "block by NMI" before VM entry if a NMI
9170                  * delivery faulted.
9171                  */
9172                 vmx_set_nmi_mask(vcpu, false);
9173                 break;
9174         case INTR_TYPE_SOFT_EXCEPTION:
9175                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9176                 /* fall through */
9177         case INTR_TYPE_HARD_EXCEPTION:
9178                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9179                         u32 err = vmcs_read32(error_code_field);
9180                         kvm_requeue_exception_e(vcpu, vector, err);
9181                 } else
9182                         kvm_requeue_exception(vcpu, vector);
9183                 break;
9184         case INTR_TYPE_SOFT_INTR:
9185                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9186                 /* fall through */
9187         case INTR_TYPE_EXT_INTR:
9188                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9189                 break;
9190         default:
9191                 break;
9192         }
9193 }
9194
9195 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9196 {
9197         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9198                                   VM_EXIT_INSTRUCTION_LEN,
9199                                   IDT_VECTORING_ERROR_CODE);
9200 }
9201
9202 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9203 {
9204         __vmx_complete_interrupts(vcpu,
9205                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9206                                   VM_ENTRY_INSTRUCTION_LEN,
9207                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9208
9209         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9210 }
9211
9212 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9213 {
9214         int i, nr_msrs;
9215         struct perf_guest_switch_msr *msrs;
9216
9217         msrs = perf_guest_get_msrs(&nr_msrs);
9218
9219         if (!msrs)
9220                 return;
9221
9222         for (i = 0; i < nr_msrs; i++)
9223                 if (msrs[i].host == msrs[i].guest)
9224                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9225                 else
9226                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9227                                         msrs[i].host);
9228 }
9229
9230 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9231 {
9232         struct vcpu_vmx *vmx = to_vmx(vcpu);
9233         u64 tscl;
9234         u32 delta_tsc;
9235
9236         if (vmx->hv_deadline_tsc == -1)
9237                 return;
9238
9239         tscl = rdtsc();
9240         if (vmx->hv_deadline_tsc > tscl)
9241                 /* sure to be 32 bit only because checked on set_hv_timer */
9242                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9243                         cpu_preemption_timer_multi);
9244         else
9245                 delta_tsc = 0;
9246
9247         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9248 }
9249
9250 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9251 {
9252         struct vcpu_vmx *vmx = to_vmx(vcpu);
9253         unsigned long debugctlmsr, cr3, cr4;
9254
9255         /* Don't enter VMX if guest state is invalid, let the exit handler
9256            start emulation until we arrive back to a valid state */
9257         if (vmx->emulation_required)
9258                 return;
9259
9260         if (vmx->ple_window_dirty) {
9261                 vmx->ple_window_dirty = false;
9262                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9263         }
9264
9265         if (vmx->nested.sync_shadow_vmcs) {
9266                 copy_vmcs12_to_shadow(vmx);
9267                 vmx->nested.sync_shadow_vmcs = false;
9268         }
9269
9270         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9271                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9272         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9273                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9274
9275         cr3 = __get_current_cr3_fast();
9276         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9277                 vmcs_writel(HOST_CR3, cr3);
9278                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9279         }
9280
9281         cr4 = cr4_read_shadow();
9282         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9283                 vmcs_writel(HOST_CR4, cr4);
9284                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9285         }
9286
9287         /* When single-stepping over STI and MOV SS, we must clear the
9288          * corresponding interruptibility bits in the guest state. Otherwise
9289          * vmentry fails as it then expects bit 14 (BS) in pending debug
9290          * exceptions being set, but that's not correct for the guest debugging
9291          * case. */
9292         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9293                 vmx_set_interrupt_shadow(vcpu, 0);
9294
9295         if (static_cpu_has(X86_FEATURE_PKU) &&
9296             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9297             vcpu->arch.pkru != vmx->host_pkru)
9298                 __write_pkru(vcpu->arch.pkru);
9299
9300         atomic_switch_perf_msrs(vmx);
9301         debugctlmsr = get_debugctlmsr();
9302
9303         vmx_arm_hv_timer(vcpu);
9304
9305         vmx->__launched = vmx->loaded_vmcs->launched;
9306         asm(
9307                 /* Store host registers */
9308                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9309                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9310                 "push %%" _ASM_CX " \n\t"
9311                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9312                 "je 1f \n\t"
9313                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9314                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9315                 "1: \n\t"
9316                 /* Reload cr2 if changed */
9317                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9318                 "mov %%cr2, %%" _ASM_DX " \n\t"
9319                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9320                 "je 2f \n\t"
9321                 "mov %%" _ASM_AX", %%cr2 \n\t"
9322                 "2: \n\t"
9323                 /* Check if vmlaunch of vmresume is needed */
9324                 "cmpl $0, %c[launched](%0) \n\t"
9325                 /* Load guest registers.  Don't clobber flags. */
9326                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9327                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9328                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9329                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9330                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9331                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9332 #ifdef CONFIG_X86_64
9333                 "mov %c[r8](%0),  %%r8  \n\t"
9334                 "mov %c[r9](%0),  %%r9  \n\t"
9335                 "mov %c[r10](%0), %%r10 \n\t"
9336                 "mov %c[r11](%0), %%r11 \n\t"
9337                 "mov %c[r12](%0), %%r12 \n\t"
9338                 "mov %c[r13](%0), %%r13 \n\t"
9339                 "mov %c[r14](%0), %%r14 \n\t"
9340                 "mov %c[r15](%0), %%r15 \n\t"
9341 #endif
9342                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9343
9344                 /* Enter guest mode */
9345                 "jne 1f \n\t"
9346                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9347                 "jmp 2f \n\t"
9348                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9349                 "2: "
9350                 /* Save guest registers, load host registers, keep flags */
9351                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9352                 "pop %0 \n\t"
9353                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9354                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9355                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9356                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9357                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9358                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9359                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9360 #ifdef CONFIG_X86_64
9361                 "mov %%r8,  %c[r8](%0) \n\t"
9362                 "mov %%r9,  %c[r9](%0) \n\t"
9363                 "mov %%r10, %c[r10](%0) \n\t"
9364                 "mov %%r11, %c[r11](%0) \n\t"
9365                 "mov %%r12, %c[r12](%0) \n\t"
9366                 "mov %%r13, %c[r13](%0) \n\t"
9367                 "mov %%r14, %c[r14](%0) \n\t"
9368                 "mov %%r15, %c[r15](%0) \n\t"
9369 #endif
9370                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9371                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9372
9373                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9374                 "setbe %c[fail](%0) \n\t"
9375                 ".pushsection .rodata \n\t"
9376                 ".global vmx_return \n\t"
9377                 "vmx_return: " _ASM_PTR " 2b \n\t"
9378                 ".popsection"
9379               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9380                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9381                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9382                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9383                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9384                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9385                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9386                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9387                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9388                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9389                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9390 #ifdef CONFIG_X86_64
9391                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9392                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9393                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9394                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9395                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9396                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9397                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9398                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9399 #endif
9400                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9401                 [wordsize]"i"(sizeof(ulong))
9402               : "cc", "memory"
9403 #ifdef CONFIG_X86_64
9404                 , "rax", "rbx", "rdi", "rsi"
9405                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9406 #else
9407                 , "eax", "ebx", "edi", "esi"
9408 #endif
9409               );
9410
9411         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9412         if (debugctlmsr)
9413                 update_debugctlmsr(debugctlmsr);
9414
9415 #ifndef CONFIG_X86_64
9416         /*
9417          * The sysexit path does not restore ds/es, so we must set them to
9418          * a reasonable value ourselves.
9419          *
9420          * We can't defer this to vmx_load_host_state() since that function
9421          * may be executed in interrupt context, which saves and restore segments
9422          * around it, nullifying its effect.
9423          */
9424         loadsegment(ds, __USER_DS);
9425         loadsegment(es, __USER_DS);
9426 #endif
9427
9428         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9429                                   | (1 << VCPU_EXREG_RFLAGS)
9430                                   | (1 << VCPU_EXREG_PDPTR)
9431                                   | (1 << VCPU_EXREG_SEGMENTS)
9432                                   | (1 << VCPU_EXREG_CR3));
9433         vcpu->arch.regs_dirty = 0;
9434
9435         /*
9436          * eager fpu is enabled if PKEY is supported and CR4 is switched
9437          * back on host, so it is safe to read guest PKRU from current
9438          * XSAVE.
9439          */
9440         if (static_cpu_has(X86_FEATURE_PKU) &&
9441             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9442                 vcpu->arch.pkru = __read_pkru();
9443                 if (vcpu->arch.pkru != vmx->host_pkru)
9444                         __write_pkru(vmx->host_pkru);
9445         }
9446
9447         /*
9448          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9449          * we did not inject a still-pending event to L1 now because of
9450          * nested_run_pending, we need to re-enable this bit.
9451          */
9452         if (vmx->nested.nested_run_pending)
9453                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9454
9455         vmx->nested.nested_run_pending = 0;
9456         vmx->idt_vectoring_info = 0;
9457
9458         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9459         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9460                 return;
9461
9462         vmx->loaded_vmcs->launched = 1;
9463         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9464
9465         vmx_complete_atomic_exit(vmx);
9466         vmx_recover_nmi_blocking(vmx);
9467         vmx_complete_interrupts(vmx);
9468 }
9469 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9470
9471 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9472 {
9473         struct vcpu_vmx *vmx = to_vmx(vcpu);
9474         int cpu;
9475
9476         if (vmx->loaded_vmcs == vmcs)
9477                 return;
9478
9479         cpu = get_cpu();
9480         vmx->loaded_vmcs = vmcs;
9481         vmx_vcpu_put(vcpu);
9482         vmx_vcpu_load(vcpu, cpu);
9483         vcpu->cpu = cpu;
9484         put_cpu();
9485 }
9486
9487 /*
9488  * Ensure that the current vmcs of the logical processor is the
9489  * vmcs01 of the vcpu before calling free_nested().
9490  */
9491 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9492 {
9493        struct vcpu_vmx *vmx = to_vmx(vcpu);
9494        int r;
9495
9496        r = vcpu_load(vcpu);
9497        BUG_ON(r);
9498        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9499        free_nested(vmx);
9500        vcpu_put(vcpu);
9501 }
9502
9503 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9504 {
9505         struct vcpu_vmx *vmx = to_vmx(vcpu);
9506
9507         if (enable_pml)
9508                 vmx_destroy_pml_buffer(vmx);
9509         free_vpid(vmx->vpid);
9510         leave_guest_mode(vcpu);
9511         vmx_free_vcpu_nested(vcpu);
9512         free_loaded_vmcs(vmx->loaded_vmcs);
9513         kfree(vmx->guest_msrs);
9514         kvm_vcpu_uninit(vcpu);
9515         kmem_cache_free(kvm_vcpu_cache, vmx);
9516 }
9517
9518 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9519 {
9520         int err;
9521         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9522         int cpu;
9523
9524         if (!vmx)
9525                 return ERR_PTR(-ENOMEM);
9526
9527         vmx->vpid = allocate_vpid();
9528
9529         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9530         if (err)
9531                 goto free_vcpu;
9532
9533         err = -ENOMEM;
9534
9535         /*
9536          * If PML is turned on, failure on enabling PML just results in failure
9537          * of creating the vcpu, therefore we can simplify PML logic (by
9538          * avoiding dealing with cases, such as enabling PML partially on vcpus
9539          * for the guest, etc.
9540          */
9541         if (enable_pml) {
9542                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9543                 if (!vmx->pml_pg)
9544                         goto uninit_vcpu;
9545         }
9546
9547         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9548         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9549                      > PAGE_SIZE);
9550
9551         if (!vmx->guest_msrs)
9552                 goto free_pml;
9553
9554         vmx->loaded_vmcs = &vmx->vmcs01;
9555         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9556         vmx->loaded_vmcs->shadow_vmcs = NULL;
9557         if (!vmx->loaded_vmcs->vmcs)
9558                 goto free_msrs;
9559         loaded_vmcs_init(vmx->loaded_vmcs);
9560
9561         cpu = get_cpu();
9562         vmx_vcpu_load(&vmx->vcpu, cpu);
9563         vmx->vcpu.cpu = cpu;
9564         vmx_vcpu_setup(vmx);
9565         vmx_vcpu_put(&vmx->vcpu);
9566         put_cpu();
9567         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9568                 err = alloc_apic_access_page(kvm);
9569                 if (err)
9570                         goto free_vmcs;
9571         }
9572
9573         if (enable_ept) {
9574                 if (!kvm->arch.ept_identity_map_addr)
9575                         kvm->arch.ept_identity_map_addr =
9576                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9577                 err = init_rmode_identity_map(kvm);
9578                 if (err)
9579                         goto free_vmcs;
9580         }
9581
9582         if (nested) {
9583                 nested_vmx_setup_ctls_msrs(vmx);
9584                 vmx->nested.vpid02 = allocate_vpid();
9585         }
9586
9587         vmx->nested.posted_intr_nv = -1;
9588         vmx->nested.current_vmptr = -1ull;
9589
9590         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9591
9592         /*
9593          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9594          * or POSTED_INTR_WAKEUP_VECTOR.
9595          */
9596         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9597         vmx->pi_desc.sn = 1;
9598
9599         return &vmx->vcpu;
9600
9601 free_vmcs:
9602         free_vpid(vmx->nested.vpid02);
9603         free_loaded_vmcs(vmx->loaded_vmcs);
9604 free_msrs:
9605         kfree(vmx->guest_msrs);
9606 free_pml:
9607         vmx_destroy_pml_buffer(vmx);
9608 uninit_vcpu:
9609         kvm_vcpu_uninit(&vmx->vcpu);
9610 free_vcpu:
9611         free_vpid(vmx->vpid);
9612         kmem_cache_free(kvm_vcpu_cache, vmx);
9613         return ERR_PTR(err);
9614 }
9615
9616 static void __init vmx_check_processor_compat(void *rtn)
9617 {
9618         struct vmcs_config vmcs_conf;
9619
9620         *(int *)rtn = 0;
9621         if (setup_vmcs_config(&vmcs_conf) < 0)
9622                 *(int *)rtn = -EIO;
9623         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9624                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9625                                 smp_processor_id());
9626                 *(int *)rtn = -EIO;
9627         }
9628 }
9629
9630 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9631 {
9632         u8 cache;
9633         u64 ipat = 0;
9634
9635         /* For VT-d and EPT combination
9636          * 1. MMIO: always map as UC
9637          * 2. EPT with VT-d:
9638          *   a. VT-d without snooping control feature: can't guarantee the
9639          *      result, try to trust guest.
9640          *   b. VT-d with snooping control feature: snooping control feature of
9641          *      VT-d engine can guarantee the cache correctness. Just set it
9642          *      to WB to keep consistent with host. So the same as item 3.
9643          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9644          *    consistent with host MTRR
9645          */
9646         if (is_mmio) {
9647                 cache = MTRR_TYPE_UNCACHABLE;
9648                 goto exit;
9649         }
9650
9651         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9652                 ipat = VMX_EPT_IPAT_BIT;
9653                 cache = MTRR_TYPE_WRBACK;
9654                 goto exit;
9655         }
9656
9657         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9658                 ipat = VMX_EPT_IPAT_BIT;
9659                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9660                         cache = MTRR_TYPE_WRBACK;
9661                 else
9662                         cache = MTRR_TYPE_UNCACHABLE;
9663                 goto exit;
9664         }
9665
9666         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9667
9668 exit:
9669         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9670 }
9671
9672 static int vmx_get_lpage_level(void)
9673 {
9674         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9675                 return PT_DIRECTORY_LEVEL;
9676         else
9677                 /* For shadow and EPT supported 1GB page */
9678                 return PT_PDPE_LEVEL;
9679 }
9680
9681 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9682 {
9683         /*
9684          * These bits in the secondary execution controls field
9685          * are dynamic, the others are mostly based on the hypervisor
9686          * architecture and the guest's CPUID.  Do not touch the
9687          * dynamic bits.
9688          */
9689         u32 mask =
9690                 SECONDARY_EXEC_SHADOW_VMCS |
9691                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9692                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9693
9694         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9695
9696         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9697                      (new_ctl & ~mask) | (cur_ctl & mask));
9698 }
9699
9700 /*
9701  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9702  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9703  */
9704 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9705 {
9706         struct vcpu_vmx *vmx = to_vmx(vcpu);
9707         struct kvm_cpuid_entry2 *entry;
9708
9709         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9710         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9711
9712 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9713         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9714                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9715 } while (0)
9716
9717         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9718         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9719         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9720         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9721         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9722         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9723         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9724         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9725         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9726         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9727         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9728         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9729         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9730         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9731         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9732
9733         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9734         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9735         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9736         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9737         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9738         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9739         cr4_fixed1_update(bit(11),            ecx, bit(2));
9740
9741 #undef cr4_fixed1_update
9742 }
9743
9744 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9745 {
9746         struct vcpu_vmx *vmx = to_vmx(vcpu);
9747
9748         if (cpu_has_secondary_exec_ctrls()) {
9749                 vmx_compute_secondary_exec_control(vmx);
9750                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9751         }
9752
9753         if (nested_vmx_allowed(vcpu))
9754                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9755                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9756         else
9757                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9758                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9759
9760         if (nested_vmx_allowed(vcpu))
9761                 nested_vmx_cr_fixed1_bits_update(vcpu);
9762 }
9763
9764 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9765 {
9766         if (func == 1 && nested)
9767                 entry->ecx |= bit(X86_FEATURE_VMX);
9768 }
9769
9770 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9771                 struct x86_exception *fault)
9772 {
9773         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9774         struct vcpu_vmx *vmx = to_vmx(vcpu);
9775         u32 exit_reason;
9776         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9777
9778         if (vmx->nested.pml_full) {
9779                 exit_reason = EXIT_REASON_PML_FULL;
9780                 vmx->nested.pml_full = false;
9781                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9782         } else if (fault->error_code & PFERR_RSVD_MASK)
9783                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9784         else
9785                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9786
9787         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9788         vmcs12->guest_physical_address = fault->address;
9789 }
9790
9791 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9792 {
9793         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9794 }
9795
9796 /* Callbacks for nested_ept_init_mmu_context: */
9797
9798 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9799 {
9800         /* return the page table to be shadowed - in our case, EPT12 */
9801         return get_vmcs12(vcpu)->ept_pointer;
9802 }
9803
9804 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9805 {
9806         WARN_ON(mmu_is_nested(vcpu));
9807         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
9808                 return 1;
9809
9810         kvm_mmu_unload(vcpu);
9811         kvm_init_shadow_ept_mmu(vcpu,
9812                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9813                         VMX_EPT_EXECUTE_ONLY_BIT,
9814                         nested_ept_ad_enabled(vcpu));
9815         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9816         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9817         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9818
9819         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9820         return 0;
9821 }
9822
9823 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9824 {
9825         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9826 }
9827
9828 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9829                                             u16 error_code)
9830 {
9831         bool inequality, bit;
9832
9833         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9834         inequality =
9835                 (error_code & vmcs12->page_fault_error_code_mask) !=
9836                  vmcs12->page_fault_error_code_match;
9837         return inequality ^ bit;
9838 }
9839
9840 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9841                 struct x86_exception *fault)
9842 {
9843         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9844
9845         WARN_ON(!is_guest_mode(vcpu));
9846
9847         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
9848                 !to_vmx(vcpu)->nested.nested_run_pending) {
9849                 vmcs12->vm_exit_intr_error_code = fault->error_code;
9850                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9851                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9852                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9853                                   fault->address);
9854         } else {
9855                 kvm_inject_page_fault(vcpu, fault);
9856         }
9857 }
9858
9859 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9860                                                struct vmcs12 *vmcs12);
9861
9862 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9863                                         struct vmcs12 *vmcs12)
9864 {
9865         struct vcpu_vmx *vmx = to_vmx(vcpu);
9866         struct page *page;
9867         u64 hpa;
9868
9869         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9870                 /*
9871                  * Translate L1 physical address to host physical
9872                  * address for vmcs02. Keep the page pinned, so this
9873                  * physical address remains valid. We keep a reference
9874                  * to it so we can release it later.
9875                  */
9876                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
9877                         kvm_release_page_dirty(vmx->nested.apic_access_page);
9878                         vmx->nested.apic_access_page = NULL;
9879                 }
9880                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
9881                 /*
9882                  * If translation failed, no matter: This feature asks
9883                  * to exit when accessing the given address, and if it
9884                  * can never be accessed, this feature won't do
9885                  * anything anyway.
9886                  */
9887                 if (!is_error_page(page)) {
9888                         vmx->nested.apic_access_page = page;
9889                         hpa = page_to_phys(vmx->nested.apic_access_page);
9890                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9891                 } else {
9892                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9893                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9894                 }
9895         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9896                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9897                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9898                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9899                 kvm_vcpu_reload_apic_access_page(vcpu);
9900         }
9901
9902         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9903                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
9904                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
9905                         vmx->nested.virtual_apic_page = NULL;
9906                 }
9907                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
9908
9909                 /*
9910                  * If translation failed, VM entry will fail because
9911                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9912                  * Failing the vm entry is _not_ what the processor
9913                  * does but it's basically the only possibility we
9914                  * have.  We could still enter the guest if CR8 load
9915                  * exits are enabled, CR8 store exits are enabled, and
9916                  * virtualize APIC access is disabled; in this case
9917                  * the processor would never use the TPR shadow and we
9918                  * could simply clear the bit from the execution
9919                  * control.  But such a configuration is useless, so
9920                  * let's keep the code simple.
9921                  */
9922                 if (!is_error_page(page)) {
9923                         vmx->nested.virtual_apic_page = page;
9924                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9925                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9926                 }
9927         }
9928
9929         if (nested_cpu_has_posted_intr(vmcs12)) {
9930                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9931                         kunmap(vmx->nested.pi_desc_page);
9932                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
9933                         vmx->nested.pi_desc_page = NULL;
9934                 }
9935                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
9936                 if (is_error_page(page))
9937                         return;
9938                 vmx->nested.pi_desc_page = page;
9939                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
9940                 vmx->nested.pi_desc =
9941                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9942                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9943                         (PAGE_SIZE - 1)));
9944                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9945                         page_to_phys(vmx->nested.pi_desc_page) +
9946                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9947                         (PAGE_SIZE - 1)));
9948         }
9949         if (cpu_has_vmx_msr_bitmap() &&
9950             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9951             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9952                 ;
9953         else
9954                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9955                                 CPU_BASED_USE_MSR_BITMAPS);
9956 }
9957
9958 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9959 {
9960         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9961         struct vcpu_vmx *vmx = to_vmx(vcpu);
9962
9963         if (vcpu->arch.virtual_tsc_khz == 0)
9964                 return;
9965
9966         /* Make sure short timeouts reliably trigger an immediate vmexit.
9967          * hrtimer_start does not guarantee this. */
9968         if (preemption_timeout <= 1) {
9969                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9970                 return;
9971         }
9972
9973         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9974         preemption_timeout *= 1000000;
9975         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9976         hrtimer_start(&vmx->nested.preemption_timer,
9977                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9978 }
9979
9980 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9981                                                struct vmcs12 *vmcs12)
9982 {
9983         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9984                 return 0;
9985
9986         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9987             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9988                 return -EINVAL;
9989
9990         return 0;
9991 }
9992
9993 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9994                                                 struct vmcs12 *vmcs12)
9995 {
9996         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9997                 return 0;
9998
9999         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10000                 return -EINVAL;
10001
10002         return 0;
10003 }
10004
10005 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10006                                                 struct vmcs12 *vmcs12)
10007 {
10008         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10009                 return 0;
10010
10011         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10012                 return -EINVAL;
10013
10014         return 0;
10015 }
10016
10017 /*
10018  * Merge L0's and L1's MSR bitmap, return false to indicate that
10019  * we do not use the hardware.
10020  */
10021 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10022                                                struct vmcs12 *vmcs12)
10023 {
10024         int msr;
10025         struct page *page;
10026         unsigned long *msr_bitmap_l1;
10027         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
10028
10029         /* This shortcut is ok because we support only x2APIC MSRs so far. */
10030         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
10031                 return false;
10032
10033         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10034         if (is_error_page(page))
10035                 return false;
10036         msr_bitmap_l1 = (unsigned long *)kmap(page);
10037
10038         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
10039
10040         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
10041                 if (nested_cpu_has_apic_reg_virt(vmcs12))
10042                         for (msr = 0x800; msr <= 0x8ff; msr++)
10043                                 nested_vmx_disable_intercept_for_msr(
10044                                         msr_bitmap_l1, msr_bitmap_l0,
10045                                         msr, MSR_TYPE_R);
10046
10047                 nested_vmx_disable_intercept_for_msr(
10048                                 msr_bitmap_l1, msr_bitmap_l0,
10049                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
10050                                 MSR_TYPE_R | MSR_TYPE_W);
10051
10052                 if (nested_cpu_has_vid(vmcs12)) {
10053                         nested_vmx_disable_intercept_for_msr(
10054                                 msr_bitmap_l1, msr_bitmap_l0,
10055                                 APIC_BASE_MSR + (APIC_EOI >> 4),
10056                                 MSR_TYPE_W);
10057                         nested_vmx_disable_intercept_for_msr(
10058                                 msr_bitmap_l1, msr_bitmap_l0,
10059                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
10060                                 MSR_TYPE_W);
10061                 }
10062         }
10063         kunmap(page);
10064         kvm_release_page_clean(page);
10065
10066         return true;
10067 }
10068
10069 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10070                                            struct vmcs12 *vmcs12)
10071 {
10072         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10073             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10074             !nested_cpu_has_vid(vmcs12) &&
10075             !nested_cpu_has_posted_intr(vmcs12))
10076                 return 0;
10077
10078         /*
10079          * If virtualize x2apic mode is enabled,
10080          * virtualize apic access must be disabled.
10081          */
10082         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10083             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10084                 return -EINVAL;
10085
10086         /*
10087          * If virtual interrupt delivery is enabled,
10088          * we must exit on external interrupts.
10089          */
10090         if (nested_cpu_has_vid(vmcs12) &&
10091            !nested_exit_on_intr(vcpu))
10092                 return -EINVAL;
10093
10094         /*
10095          * bits 15:8 should be zero in posted_intr_nv,
10096          * the descriptor address has been already checked
10097          * in nested_get_vmcs12_pages.
10098          */
10099         if (nested_cpu_has_posted_intr(vmcs12) &&
10100            (!nested_cpu_has_vid(vmcs12) ||
10101             !nested_exit_intr_ack_set(vcpu) ||
10102             vmcs12->posted_intr_nv & 0xff00))
10103                 return -EINVAL;
10104
10105         /* tpr shadow is needed by all apicv features. */
10106         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10107                 return -EINVAL;
10108
10109         return 0;
10110 }
10111
10112 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10113                                        unsigned long count_field,
10114                                        unsigned long addr_field)
10115 {
10116         int maxphyaddr;
10117         u64 count, addr;
10118
10119         if (vmcs12_read_any(vcpu, count_field, &count) ||
10120             vmcs12_read_any(vcpu, addr_field, &addr)) {
10121                 WARN_ON(1);
10122                 return -EINVAL;
10123         }
10124         if (count == 0)
10125                 return 0;
10126         maxphyaddr = cpuid_maxphyaddr(vcpu);
10127         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10128             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10129                 pr_debug_ratelimited(
10130                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10131                         addr_field, maxphyaddr, count, addr);
10132                 return -EINVAL;
10133         }
10134         return 0;
10135 }
10136
10137 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10138                                                 struct vmcs12 *vmcs12)
10139 {
10140         if (vmcs12->vm_exit_msr_load_count == 0 &&
10141             vmcs12->vm_exit_msr_store_count == 0 &&
10142             vmcs12->vm_entry_msr_load_count == 0)
10143                 return 0; /* Fast path */
10144         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10145                                         VM_EXIT_MSR_LOAD_ADDR) ||
10146             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10147                                         VM_EXIT_MSR_STORE_ADDR) ||
10148             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10149                                         VM_ENTRY_MSR_LOAD_ADDR))
10150                 return -EINVAL;
10151         return 0;
10152 }
10153
10154 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10155                                          struct vmcs12 *vmcs12)
10156 {
10157         u64 address = vmcs12->pml_address;
10158         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10159
10160         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10161                 if (!nested_cpu_has_ept(vmcs12) ||
10162                     !IS_ALIGNED(address, 4096)  ||
10163                     address >> maxphyaddr)
10164                         return -EINVAL;
10165         }
10166
10167         return 0;
10168 }
10169
10170 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10171                                        struct vmx_msr_entry *e)
10172 {
10173         /* x2APIC MSR accesses are not allowed */
10174         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10175                 return -EINVAL;
10176         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10177             e->index == MSR_IA32_UCODE_REV)
10178                 return -EINVAL;
10179         if (e->reserved != 0)
10180                 return -EINVAL;
10181         return 0;
10182 }
10183
10184 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10185                                      struct vmx_msr_entry *e)
10186 {
10187         if (e->index == MSR_FS_BASE ||
10188             e->index == MSR_GS_BASE ||
10189             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10190             nested_vmx_msr_check_common(vcpu, e))
10191                 return -EINVAL;
10192         return 0;
10193 }
10194
10195 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10196                                       struct vmx_msr_entry *e)
10197 {
10198         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10199             nested_vmx_msr_check_common(vcpu, e))
10200                 return -EINVAL;
10201         return 0;
10202 }
10203
10204 /*
10205  * Load guest's/host's msr at nested entry/exit.
10206  * return 0 for success, entry index for failure.
10207  */
10208 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10209 {
10210         u32 i;
10211         struct vmx_msr_entry e;
10212         struct msr_data msr;
10213
10214         msr.host_initiated = false;
10215         for (i = 0; i < count; i++) {
10216                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10217                                         &e, sizeof(e))) {
10218                         pr_debug_ratelimited(
10219                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10220                                 __func__, i, gpa + i * sizeof(e));
10221                         goto fail;
10222                 }
10223                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10224                         pr_debug_ratelimited(
10225                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10226                                 __func__, i, e.index, e.reserved);
10227                         goto fail;
10228                 }
10229                 msr.index = e.index;
10230                 msr.data = e.value;
10231                 if (kvm_set_msr(vcpu, &msr)) {
10232                         pr_debug_ratelimited(
10233                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10234                                 __func__, i, e.index, e.value);
10235                         goto fail;
10236                 }
10237         }
10238         return 0;
10239 fail:
10240         return i + 1;
10241 }
10242
10243 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10244 {
10245         u32 i;
10246         struct vmx_msr_entry e;
10247
10248         for (i = 0; i < count; i++) {
10249                 struct msr_data msr_info;
10250                 if (kvm_vcpu_read_guest(vcpu,
10251                                         gpa + i * sizeof(e),
10252                                         &e, 2 * sizeof(u32))) {
10253                         pr_debug_ratelimited(
10254                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10255                                 __func__, i, gpa + i * sizeof(e));
10256                         return -EINVAL;
10257                 }
10258                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10259                         pr_debug_ratelimited(
10260                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10261                                 __func__, i, e.index, e.reserved);
10262                         return -EINVAL;
10263                 }
10264                 msr_info.host_initiated = false;
10265                 msr_info.index = e.index;
10266                 if (kvm_get_msr(vcpu, &msr_info)) {
10267                         pr_debug_ratelimited(
10268                                 "%s cannot read MSR (%u, 0x%x)\n",
10269                                 __func__, i, e.index);
10270                         return -EINVAL;
10271                 }
10272                 if (kvm_vcpu_write_guest(vcpu,
10273                                          gpa + i * sizeof(e) +
10274                                              offsetof(struct vmx_msr_entry, value),
10275                                          &msr_info.data, sizeof(msr_info.data))) {
10276                         pr_debug_ratelimited(
10277                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10278                                 __func__, i, e.index, msr_info.data);
10279                         return -EINVAL;
10280                 }
10281         }
10282         return 0;
10283 }
10284
10285 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10286 {
10287         unsigned long invalid_mask;
10288
10289         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10290         return (val & invalid_mask) == 0;
10291 }
10292
10293 /*
10294  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10295  * emulating VM entry into a guest with EPT enabled.
10296  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10297  * is assigned to entry_failure_code on failure.
10298  */
10299 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10300                                u32 *entry_failure_code)
10301 {
10302         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10303                 if (!nested_cr3_valid(vcpu, cr3)) {
10304                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10305                         return 1;
10306                 }
10307
10308                 /*
10309                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10310                  * must not be dereferenced.
10311                  */
10312                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10313                     !nested_ept) {
10314                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10315                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10316                                 return 1;
10317                         }
10318                 }
10319
10320                 vcpu->arch.cr3 = cr3;
10321                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10322         }
10323
10324         kvm_mmu_reset_context(vcpu);
10325         return 0;
10326 }
10327
10328 /*
10329  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10330  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10331  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10332  * guest in a way that will both be appropriate to L1's requests, and our
10333  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10334  * function also has additional necessary side-effects, like setting various
10335  * vcpu->arch fields.
10336  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10337  * is assigned to entry_failure_code on failure.
10338  */
10339 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10340                           bool from_vmentry, u32 *entry_failure_code)
10341 {
10342         struct vcpu_vmx *vmx = to_vmx(vcpu);
10343         u32 exec_control, vmcs12_exec_ctrl;
10344
10345         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10346         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10347         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10348         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10349         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10350         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10351         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10352         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10353         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10354         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10355         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10356         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10357         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10358         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10359         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10360         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10361         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10362         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10363         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10364         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10365         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10366         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10367         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10368         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10369         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10370         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10371         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10372         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10373         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10374         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10375         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10376         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10377         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10378         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10379         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10380         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10381
10382         if (from_vmentry &&
10383             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10384                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10385                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10386         } else {
10387                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10388                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10389         }
10390         if (from_vmentry) {
10391                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10392                              vmcs12->vm_entry_intr_info_field);
10393                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10394                              vmcs12->vm_entry_exception_error_code);
10395                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10396                              vmcs12->vm_entry_instruction_len);
10397                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10398                              vmcs12->guest_interruptibility_info);
10399                 vmx->loaded_vmcs->nmi_known_unmasked =
10400                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10401         } else {
10402                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10403         }
10404         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10405         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10406         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10407                 vmcs12->guest_pending_dbg_exceptions);
10408         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10409         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10410
10411         if (nested_cpu_has_xsaves(vmcs12))
10412                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10413         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10414
10415         exec_control = vmcs12->pin_based_vm_exec_control;
10416
10417         /* Preemption timer setting is only taken from vmcs01.  */
10418         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10419         exec_control |= vmcs_config.pin_based_exec_ctrl;
10420         if (vmx->hv_deadline_tsc == -1)
10421                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10422
10423         /* Posted interrupts setting is only taken from vmcs12.  */
10424         if (nested_cpu_has_posted_intr(vmcs12)) {
10425                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10426                 vmx->nested.pi_pending = false;
10427                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10428         } else {
10429                 exec_control &= ~PIN_BASED_POSTED_INTR;
10430         }
10431
10432         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10433
10434         vmx->nested.preemption_timer_expired = false;
10435         if (nested_cpu_has_preemption_timer(vmcs12))
10436                 vmx_start_preemption_timer(vcpu);
10437
10438         /*
10439          * Whether page-faults are trapped is determined by a combination of
10440          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10441          * If enable_ept, L0 doesn't care about page faults and we should
10442          * set all of these to L1's desires. However, if !enable_ept, L0 does
10443          * care about (at least some) page faults, and because it is not easy
10444          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10445          * to exit on each and every L2 page fault. This is done by setting
10446          * MASK=MATCH=0 and (see below) EB.PF=1.
10447          * Note that below we don't need special code to set EB.PF beyond the
10448          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10449          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10450          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10451          */
10452         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10453                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10454         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10455                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10456
10457         if (cpu_has_secondary_exec_ctrls()) {
10458                 exec_control = vmx->secondary_exec_control;
10459
10460                 /* Take the following fields only from vmcs12 */
10461                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10462                                   SECONDARY_EXEC_ENABLE_INVPCID |
10463                                   SECONDARY_EXEC_RDTSCP |
10464                                   SECONDARY_EXEC_XSAVES |
10465                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10466                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
10467                                   SECONDARY_EXEC_ENABLE_VMFUNC);
10468                 if (nested_cpu_has(vmcs12,
10469                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10470                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10471                                 ~SECONDARY_EXEC_ENABLE_PML;
10472                         exec_control |= vmcs12_exec_ctrl;
10473                 }
10474
10475                 /* All VMFUNCs are currently emulated through L0 vmexits.  */
10476                 if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC)
10477                         vmcs_write64(VM_FUNCTION_CONTROL, 0);
10478
10479                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10480                         vmcs_write64(EOI_EXIT_BITMAP0,
10481                                 vmcs12->eoi_exit_bitmap0);
10482                         vmcs_write64(EOI_EXIT_BITMAP1,
10483                                 vmcs12->eoi_exit_bitmap1);
10484                         vmcs_write64(EOI_EXIT_BITMAP2,
10485                                 vmcs12->eoi_exit_bitmap2);
10486                         vmcs_write64(EOI_EXIT_BITMAP3,
10487                                 vmcs12->eoi_exit_bitmap3);
10488                         vmcs_write16(GUEST_INTR_STATUS,
10489                                 vmcs12->guest_intr_status);
10490                 }
10491
10492                 /*
10493                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10494                  * nested_get_vmcs12_pages will either fix it up or
10495                  * remove the VM execution control.
10496                  */
10497                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10498                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10499
10500                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10501         }
10502
10503
10504         /*
10505          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10506          * Some constant fields are set here by vmx_set_constant_host_state().
10507          * Other fields are different per CPU, and will be set later when
10508          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10509          */
10510         vmx_set_constant_host_state(vmx);
10511
10512         /*
10513          * Set the MSR load/store lists to match L0's settings.
10514          */
10515         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10516         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10517         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10518         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10519         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10520
10521         /*
10522          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10523          * entry, but only if the current (host) sp changed from the value
10524          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10525          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10526          * here we just force the write to happen on entry.
10527          */
10528         vmx->host_rsp = 0;
10529
10530         exec_control = vmx_exec_control(vmx); /* L0's desires */
10531         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10532         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10533         exec_control &= ~CPU_BASED_TPR_SHADOW;
10534         exec_control |= vmcs12->cpu_based_vm_exec_control;
10535
10536         /*
10537          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10538          * nested_get_vmcs12_pages can't fix it up, the illegal value
10539          * will result in a VM entry failure.
10540          */
10541         if (exec_control & CPU_BASED_TPR_SHADOW) {
10542                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10543                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10544         } else {
10545 #ifdef CONFIG_X86_64
10546                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10547                                 CPU_BASED_CR8_STORE_EXITING;
10548 #endif
10549         }
10550
10551         /*
10552          * Merging of IO bitmap not currently supported.
10553          * Rather, exit every time.
10554          */
10555         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10556         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10557
10558         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10559
10560         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10561          * bitwise-or of what L1 wants to trap for L2, and what we want to
10562          * trap. Note that CR0.TS also needs updating - we do this later.
10563          */
10564         update_exception_bitmap(vcpu);
10565         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10566         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10567
10568         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10569          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10570          * bits are further modified by vmx_set_efer() below.
10571          */
10572         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10573
10574         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10575          * emulated by vmx_set_efer(), below.
10576          */
10577         vm_entry_controls_init(vmx,
10578                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10579                         ~VM_ENTRY_IA32E_MODE) |
10580                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10581
10582         if (from_vmentry &&
10583             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10584                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10585                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10586         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10587                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10588         }
10589
10590         set_cr4_guest_host_mask(vmx);
10591
10592         if (from_vmentry &&
10593             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10594                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10595
10596         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10597                 vmcs_write64(TSC_OFFSET,
10598                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10599         else
10600                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10601         if (kvm_has_tsc_control)
10602                 decache_tsc_multiplier(vmx);
10603
10604         if (enable_vpid) {
10605                 /*
10606                  * There is no direct mapping between vpid02 and vpid12, the
10607                  * vpid02 is per-vCPU for L0 and reused while the value of
10608                  * vpid12 is changed w/ one invvpid during nested vmentry.
10609                  * The vpid12 is allocated by L1 for L2, so it will not
10610                  * influence global bitmap(for vpid01 and vpid02 allocation)
10611                  * even if spawn a lot of nested vCPUs.
10612                  */
10613                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10614                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10615                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10616                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10617                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10618                         }
10619                 } else {
10620                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10621                         vmx_flush_tlb(vcpu);
10622                 }
10623
10624         }
10625
10626         if (enable_pml) {
10627                 /*
10628                  * Conceptually we want to copy the PML address and index from
10629                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10630                  * since we always flush the log on each vmexit, this happens
10631                  * to be equivalent to simply resetting the fields in vmcs02.
10632                  */
10633                 ASSERT(vmx->pml_pg);
10634                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10635                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10636         }
10637
10638         if (nested_cpu_has_ept(vmcs12)) {
10639                 if (nested_ept_init_mmu_context(vcpu)) {
10640                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10641                         return 1;
10642                 }
10643         } else if (nested_cpu_has2(vmcs12,
10644                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10645                 vmx_flush_tlb_ept_only(vcpu);
10646         }
10647
10648         /*
10649          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10650          * bits which we consider mandatory enabled.
10651          * The CR0_READ_SHADOW is what L2 should have expected to read given
10652          * the specifications by L1; It's not enough to take
10653          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10654          * have more bits than L1 expected.
10655          */
10656         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10657         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10658
10659         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10660         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10661
10662         if (from_vmentry &&
10663             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10664                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10665         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10666                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10667         else
10668                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10669         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10670         vmx_set_efer(vcpu, vcpu->arch.efer);
10671
10672         /* Shadow page tables on either EPT or shadow page tables. */
10673         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10674                                 entry_failure_code))
10675                 return 1;
10676
10677         if (!enable_ept)
10678                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10679
10680         /*
10681          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10682          */
10683         if (enable_ept) {
10684                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10685                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10686                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10687                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10688         }
10689
10690         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10691         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10692         return 0;
10693 }
10694
10695 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10696 {
10697         struct vcpu_vmx *vmx = to_vmx(vcpu);
10698
10699         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10700             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10701                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10702
10703         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10704                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10705
10706         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10707                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10708
10709         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10710                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10711
10712         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10713                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10714
10715         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10716                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10717
10718         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10719                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10720
10721         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10722                                 vmx->nested.nested_vmx_procbased_ctls_low,
10723                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10724             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10725              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10726                                  vmx->nested.nested_vmx_secondary_ctls_low,
10727                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10728             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10729                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10730                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10731             !vmx_control_verify(vmcs12->vm_exit_controls,
10732                                 vmx->nested.nested_vmx_exit_ctls_low,
10733                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10734             !vmx_control_verify(vmcs12->vm_entry_controls,
10735                                 vmx->nested.nested_vmx_entry_ctls_low,
10736                                 vmx->nested.nested_vmx_entry_ctls_high))
10737                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10738
10739         if (nested_cpu_has_vmfunc(vmcs12)) {
10740                 if (vmcs12->vm_function_control &
10741                     ~vmx->nested.nested_vmx_vmfunc_controls)
10742                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10743
10744                 if (nested_cpu_has_eptp_switching(vmcs12)) {
10745                         if (!nested_cpu_has_ept(vmcs12) ||
10746                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
10747                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10748                 }
10749         }
10750
10751         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10752                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10753
10754         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10755             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10756             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10757                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10758
10759         return 0;
10760 }
10761
10762 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10763                                   u32 *exit_qual)
10764 {
10765         bool ia32e;
10766
10767         *exit_qual = ENTRY_FAIL_DEFAULT;
10768
10769         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10770             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10771                 return 1;
10772
10773         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10774             vmcs12->vmcs_link_pointer != -1ull) {
10775                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10776                 return 1;
10777         }
10778
10779         /*
10780          * If the load IA32_EFER VM-entry control is 1, the following checks
10781          * are performed on the field for the IA32_EFER MSR:
10782          * - Bits reserved in the IA32_EFER MSR must be 0.
10783          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10784          *   the IA-32e mode guest VM-exit control. It must also be identical
10785          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10786          *   CR0.PG) is 1.
10787          */
10788         if (to_vmx(vcpu)->nested.nested_run_pending &&
10789             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10790                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10791                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10792                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10793                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10794                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10795                         return 1;
10796         }
10797
10798         /*
10799          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10800          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10801          * the values of the LMA and LME bits in the field must each be that of
10802          * the host address-space size VM-exit control.
10803          */
10804         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10805                 ia32e = (vmcs12->vm_exit_controls &
10806                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10807                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10808                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10809                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10810                         return 1;
10811         }
10812
10813         return 0;
10814 }
10815
10816 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10817 {
10818         struct vcpu_vmx *vmx = to_vmx(vcpu);
10819         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10820         struct loaded_vmcs *vmcs02;
10821         u32 msr_entry_idx;
10822         u32 exit_qual;
10823
10824         vmcs02 = nested_get_current_vmcs02(vmx);
10825         if (!vmcs02)
10826                 return -ENOMEM;
10827
10828         enter_guest_mode(vcpu);
10829
10830         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10831                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10832
10833         vmx_switch_vmcs(vcpu, vmcs02);
10834         vmx_segment_cache_clear(vmx);
10835
10836         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10837                 leave_guest_mode(vcpu);
10838                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10839                 nested_vmx_entry_failure(vcpu, vmcs12,
10840                                          EXIT_REASON_INVALID_STATE, exit_qual);
10841                 return 1;
10842         }
10843
10844         nested_get_vmcs12_pages(vcpu, vmcs12);
10845
10846         msr_entry_idx = nested_vmx_load_msr(vcpu,
10847                                             vmcs12->vm_entry_msr_load_addr,
10848                                             vmcs12->vm_entry_msr_load_count);
10849         if (msr_entry_idx) {
10850                 leave_guest_mode(vcpu);
10851                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10852                 nested_vmx_entry_failure(vcpu, vmcs12,
10853                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10854                 return 1;
10855         }
10856
10857         /*
10858          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10859          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10860          * returned as far as L1 is concerned. It will only return (and set
10861          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10862          */
10863         return 0;
10864 }
10865
10866 /*
10867  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10868  * for running an L2 nested guest.
10869  */
10870 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10871 {
10872         struct vmcs12 *vmcs12;
10873         struct vcpu_vmx *vmx = to_vmx(vcpu);
10874         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10875         u32 exit_qual;
10876         int ret;
10877
10878         if (!nested_vmx_check_permission(vcpu))
10879                 return 1;
10880
10881         if (!nested_vmx_check_vmcs12(vcpu))
10882                 goto out;
10883
10884         vmcs12 = get_vmcs12(vcpu);
10885
10886         if (enable_shadow_vmcs)
10887                 copy_shadow_to_vmcs12(vmx);
10888
10889         /*
10890          * The nested entry process starts with enforcing various prerequisites
10891          * on vmcs12 as required by the Intel SDM, and act appropriately when
10892          * they fail: As the SDM explains, some conditions should cause the
10893          * instruction to fail, while others will cause the instruction to seem
10894          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10895          * To speed up the normal (success) code path, we should avoid checking
10896          * for misconfigurations which will anyway be caught by the processor
10897          * when using the merged vmcs02.
10898          */
10899         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10900                 nested_vmx_failValid(vcpu,
10901                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10902                 goto out;
10903         }
10904
10905         if (vmcs12->launch_state == launch) {
10906                 nested_vmx_failValid(vcpu,
10907                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10908                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10909                 goto out;
10910         }
10911
10912         ret = check_vmentry_prereqs(vcpu, vmcs12);
10913         if (ret) {
10914                 nested_vmx_failValid(vcpu, ret);
10915                 goto out;
10916         }
10917
10918         /*
10919          * After this point, the trap flag no longer triggers a singlestep trap
10920          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10921          * This is not 100% correct; for performance reasons, we delegate most
10922          * of the checks on host state to the processor.  If those fail,
10923          * the singlestep trap is missed.
10924          */
10925         skip_emulated_instruction(vcpu);
10926
10927         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10928         if (ret) {
10929                 nested_vmx_entry_failure(vcpu, vmcs12,
10930                                          EXIT_REASON_INVALID_STATE, exit_qual);
10931                 return 1;
10932         }
10933
10934         /*
10935          * We're finally done with prerequisite checking, and can start with
10936          * the nested entry.
10937          */
10938
10939         ret = enter_vmx_non_root_mode(vcpu, true);
10940         if (ret)
10941                 return ret;
10942
10943         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10944                 return kvm_vcpu_halt(vcpu);
10945
10946         vmx->nested.nested_run_pending = 1;
10947
10948         return 1;
10949
10950 out:
10951         return kvm_skip_emulated_instruction(vcpu);
10952 }
10953
10954 /*
10955  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10956  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10957  * This function returns the new value we should put in vmcs12.guest_cr0.
10958  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10959  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10960  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10961  *     didn't trap the bit, because if L1 did, so would L0).
10962  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10963  *     been modified by L2, and L1 knows it. So just leave the old value of
10964  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10965  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10966  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10967  *     changed these bits, and therefore they need to be updated, but L0
10968  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10969  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10970  */
10971 static inline unsigned long
10972 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10973 {
10974         return
10975         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10976         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10977         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10978                         vcpu->arch.cr0_guest_owned_bits));
10979 }
10980
10981 static inline unsigned long
10982 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10983 {
10984         return
10985         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10986         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10987         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10988                         vcpu->arch.cr4_guest_owned_bits));
10989 }
10990
10991 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10992                                        struct vmcs12 *vmcs12)
10993 {
10994         u32 idt_vectoring;
10995         unsigned int nr;
10996
10997         if (vcpu->arch.exception.injected) {
10998                 nr = vcpu->arch.exception.nr;
10999                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11000
11001                 if (kvm_exception_is_soft(nr)) {
11002                         vmcs12->vm_exit_instruction_len =
11003                                 vcpu->arch.event_exit_inst_len;
11004                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11005                 } else
11006                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11007
11008                 if (vcpu->arch.exception.has_error_code) {
11009                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11010                         vmcs12->idt_vectoring_error_code =
11011                                 vcpu->arch.exception.error_code;
11012                 }
11013
11014                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11015         } else if (vcpu->arch.nmi_injected) {
11016                 vmcs12->idt_vectoring_info_field =
11017                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11018         } else if (vcpu->arch.interrupt.pending) {
11019                 nr = vcpu->arch.interrupt.nr;
11020                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11021
11022                 if (vcpu->arch.interrupt.soft) {
11023                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11024                         vmcs12->vm_entry_instruction_len =
11025                                 vcpu->arch.event_exit_inst_len;
11026                 } else
11027                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11028
11029                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11030         }
11031 }
11032
11033 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11034 {
11035         struct vcpu_vmx *vmx = to_vmx(vcpu);
11036         unsigned long exit_qual;
11037
11038         if (kvm_event_needs_reinjection(vcpu))
11039                 return -EBUSY;
11040
11041         if (vcpu->arch.exception.pending &&
11042                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11043                 if (vmx->nested.nested_run_pending)
11044                         return -EBUSY;
11045                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11046                 vcpu->arch.exception.pending = false;
11047                 return 0;
11048         }
11049
11050         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11051             vmx->nested.preemption_timer_expired) {
11052                 if (vmx->nested.nested_run_pending)
11053                         return -EBUSY;
11054                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11055                 return 0;
11056         }
11057
11058         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11059                 if (vmx->nested.nested_run_pending)
11060                         return -EBUSY;
11061                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11062                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11063                                   INTR_INFO_VALID_MASK, 0);
11064                 /*
11065                  * The NMI-triggered VM exit counts as injection:
11066                  * clear this one and block further NMIs.
11067                  */
11068                 vcpu->arch.nmi_pending = 0;
11069                 vmx_set_nmi_mask(vcpu, true);
11070                 return 0;
11071         }
11072
11073         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11074             nested_exit_on_intr(vcpu)) {
11075                 if (vmx->nested.nested_run_pending)
11076                         return -EBUSY;
11077                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11078                 return 0;
11079         }
11080
11081         vmx_complete_nested_posted_interrupt(vcpu);
11082         return 0;
11083 }
11084
11085 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11086 {
11087         ktime_t remaining =
11088                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11089         u64 value;
11090
11091         if (ktime_to_ns(remaining) <= 0)
11092                 return 0;
11093
11094         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11095         do_div(value, 1000000);
11096         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11097 }
11098
11099 /*
11100  * Update the guest state fields of vmcs12 to reflect changes that
11101  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11102  * VM-entry controls is also updated, since this is really a guest
11103  * state bit.)
11104  */
11105 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11106 {
11107         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11108         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11109
11110         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11111         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11112         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11113
11114         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11115         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11116         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11117         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11118         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11119         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11120         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11121         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11122         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11123         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11124         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11125         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11126         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11127         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11128         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11129         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11130         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11131         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11132         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11133         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11134         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11135         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11136         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11137         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11138         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11139         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11140         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11141         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11142         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11143         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11144         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11145         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11146         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11147         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11148         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11149         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11150
11151         vmcs12->guest_interruptibility_info =
11152                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11153         vmcs12->guest_pending_dbg_exceptions =
11154                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11155         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11156                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11157         else
11158                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11159
11160         if (nested_cpu_has_preemption_timer(vmcs12)) {
11161                 if (vmcs12->vm_exit_controls &
11162                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11163                         vmcs12->vmx_preemption_timer_value =
11164                                 vmx_get_preemption_timer_value(vcpu);
11165                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11166         }
11167
11168         /*
11169          * In some cases (usually, nested EPT), L2 is allowed to change its
11170          * own CR3 without exiting. If it has changed it, we must keep it.
11171          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11172          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11173          *
11174          * Additionally, restore L2's PDPTR to vmcs12.
11175          */
11176         if (enable_ept) {
11177                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11178                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11179                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11180                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11181                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11182         }
11183
11184         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11185
11186         if (nested_cpu_has_vid(vmcs12))
11187                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11188
11189         vmcs12->vm_entry_controls =
11190                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11191                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11192
11193         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11194                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11195                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11196         }
11197
11198         /* TODO: These cannot have changed unless we have MSR bitmaps and
11199          * the relevant bit asks not to trap the change */
11200         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11201                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11202         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11203                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11204         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11205         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11206         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11207         if (kvm_mpx_supported())
11208                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11209 }
11210
11211 /*
11212  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11213  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11214  * and this function updates it to reflect the changes to the guest state while
11215  * L2 was running (and perhaps made some exits which were handled directly by L0
11216  * without going back to L1), and to reflect the exit reason.
11217  * Note that we do not have to copy here all VMCS fields, just those that
11218  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11219  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11220  * which already writes to vmcs12 directly.
11221  */
11222 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11223                            u32 exit_reason, u32 exit_intr_info,
11224                            unsigned long exit_qualification)
11225 {
11226         /* update guest state fields: */
11227         sync_vmcs12(vcpu, vmcs12);
11228
11229         /* update exit information fields: */
11230
11231         vmcs12->vm_exit_reason = exit_reason;
11232         vmcs12->exit_qualification = exit_qualification;
11233         vmcs12->vm_exit_intr_info = exit_intr_info;
11234
11235         vmcs12->idt_vectoring_info_field = 0;
11236         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11237         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11238
11239         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11240                 vmcs12->launch_state = 1;
11241
11242                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11243                  * instead of reading the real value. */
11244                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11245
11246                 /*
11247                  * Transfer the event that L0 or L1 may wanted to inject into
11248                  * L2 to IDT_VECTORING_INFO_FIELD.
11249                  */
11250                 vmcs12_save_pending_event(vcpu, vmcs12);
11251         }
11252
11253         /*
11254          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11255          * preserved above and would only end up incorrectly in L1.
11256          */
11257         vcpu->arch.nmi_injected = false;
11258         kvm_clear_exception_queue(vcpu);
11259         kvm_clear_interrupt_queue(vcpu);
11260 }
11261
11262 /*
11263  * A part of what we need to when the nested L2 guest exits and we want to
11264  * run its L1 parent, is to reset L1's guest state to the host state specified
11265  * in vmcs12.
11266  * This function is to be called not only on normal nested exit, but also on
11267  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11268  * Failures During or After Loading Guest State").
11269  * This function should be called when the active VMCS is L1's (vmcs01).
11270  */
11271 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11272                                    struct vmcs12 *vmcs12)
11273 {
11274         struct kvm_segment seg;
11275         u32 entry_failure_code;
11276
11277         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11278                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11279         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11280                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11281         else
11282                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11283         vmx_set_efer(vcpu, vcpu->arch.efer);
11284
11285         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11286         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11287         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11288         /*
11289          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11290          * actually changed, because vmx_set_cr0 refers to efer set above.
11291          *
11292          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11293          * (KVM doesn't change it);
11294          */
11295         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11296         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11297
11298         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11299         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11300         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11301
11302         nested_ept_uninit_mmu_context(vcpu);
11303
11304         /*
11305          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11306          * couldn't have changed.
11307          */
11308         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11309                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11310
11311         if (!enable_ept)
11312                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11313
11314         if (enable_vpid) {
11315                 /*
11316                  * Trivially support vpid by letting L2s share their parent
11317                  * L1's vpid. TODO: move to a more elaborate solution, giving
11318                  * each L2 its own vpid and exposing the vpid feature to L1.
11319                  */
11320                 vmx_flush_tlb(vcpu);
11321         }
11322         /* Restore posted intr vector. */
11323         if (nested_cpu_has_posted_intr(vmcs12))
11324                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11325
11326         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11327         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11328         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11329         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11330         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11331
11332         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11333         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11334                 vmcs_write64(GUEST_BNDCFGS, 0);
11335
11336         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11337                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11338                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11339         }
11340         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11341                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11342                         vmcs12->host_ia32_perf_global_ctrl);
11343
11344         /* Set L1 segment info according to Intel SDM
11345             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11346         seg = (struct kvm_segment) {
11347                 .base = 0,
11348                 .limit = 0xFFFFFFFF,
11349                 .selector = vmcs12->host_cs_selector,
11350                 .type = 11,
11351                 .present = 1,
11352                 .s = 1,
11353                 .g = 1
11354         };
11355         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11356                 seg.l = 1;
11357         else
11358                 seg.db = 1;
11359         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11360         seg = (struct kvm_segment) {
11361                 .base = 0,
11362                 .limit = 0xFFFFFFFF,
11363                 .type = 3,
11364                 .present = 1,
11365                 .s = 1,
11366                 .db = 1,
11367                 .g = 1
11368         };
11369         seg.selector = vmcs12->host_ds_selector;
11370         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11371         seg.selector = vmcs12->host_es_selector;
11372         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11373         seg.selector = vmcs12->host_ss_selector;
11374         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11375         seg.selector = vmcs12->host_fs_selector;
11376         seg.base = vmcs12->host_fs_base;
11377         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11378         seg.selector = vmcs12->host_gs_selector;
11379         seg.base = vmcs12->host_gs_base;
11380         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11381         seg = (struct kvm_segment) {
11382                 .base = vmcs12->host_tr_base,
11383                 .limit = 0x67,
11384                 .selector = vmcs12->host_tr_selector,
11385                 .type = 11,
11386                 .present = 1
11387         };
11388         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11389
11390         kvm_set_dr(vcpu, 7, 0x400);
11391         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11392
11393         if (cpu_has_vmx_msr_bitmap())
11394                 vmx_set_msr_bitmap(vcpu);
11395
11396         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11397                                 vmcs12->vm_exit_msr_load_count))
11398                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11399 }
11400
11401 /*
11402  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11403  * and modify vmcs12 to make it see what it would expect to see there if
11404  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11405  */
11406 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11407                               u32 exit_intr_info,
11408                               unsigned long exit_qualification)
11409 {
11410         struct vcpu_vmx *vmx = to_vmx(vcpu);
11411         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11412
11413         /* trying to cancel vmlaunch/vmresume is a bug */
11414         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11415
11416         /*
11417          * The only expected VM-instruction error is "VM entry with
11418          * invalid control field(s)." Anything else indicates a
11419          * problem with L0.
11420          */
11421         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11422                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11423
11424         leave_guest_mode(vcpu);
11425
11426         if (likely(!vmx->fail)) {
11427                 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11428                                exit_qualification);
11429
11430                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11431                                          vmcs12->vm_exit_msr_store_count))
11432                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11433         }
11434
11435         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11436         vm_entry_controls_reset_shadow(vmx);
11437         vm_exit_controls_reset_shadow(vmx);
11438         vmx_segment_cache_clear(vmx);
11439
11440         /* if no vmcs02 cache requested, remove the one we used */
11441         if (VMCS02_POOL_SIZE == 0)
11442                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11443
11444         /* Update any VMCS fields that might have changed while L2 ran */
11445         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11446         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11447         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11448         if (vmx->hv_deadline_tsc == -1)
11449                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11450                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11451         else
11452                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11453                               PIN_BASED_VMX_PREEMPTION_TIMER);
11454         if (kvm_has_tsc_control)
11455                 decache_tsc_multiplier(vmx);
11456
11457         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11458                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11459                 vmx_set_virtual_x2apic_mode(vcpu,
11460                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11461         } else if (!nested_cpu_has_ept(vmcs12) &&
11462                    nested_cpu_has2(vmcs12,
11463                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11464                 vmx_flush_tlb_ept_only(vcpu);
11465         }
11466
11467         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11468         vmx->host_rsp = 0;
11469
11470         /* Unpin physical memory we referred to in vmcs02 */
11471         if (vmx->nested.apic_access_page) {
11472                 kvm_release_page_dirty(vmx->nested.apic_access_page);
11473                 vmx->nested.apic_access_page = NULL;
11474         }
11475         if (vmx->nested.virtual_apic_page) {
11476                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11477                 vmx->nested.virtual_apic_page = NULL;
11478         }
11479         if (vmx->nested.pi_desc_page) {
11480                 kunmap(vmx->nested.pi_desc_page);
11481                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11482                 vmx->nested.pi_desc_page = NULL;
11483                 vmx->nested.pi_desc = NULL;
11484         }
11485
11486         /*
11487          * We are now running in L2, mmu_notifier will force to reload the
11488          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11489          */
11490         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11491
11492         if (enable_shadow_vmcs)
11493                 vmx->nested.sync_shadow_vmcs = true;
11494
11495         /* in case we halted in L2 */
11496         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11497
11498         if (likely(!vmx->fail)) {
11499                 /*
11500                  * TODO: SDM says that with acknowledge interrupt on
11501                  * exit, bit 31 of the VM-exit interrupt information
11502                  * (valid interrupt) is always set to 1 on
11503                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11504                  * need kvm_cpu_has_interrupt().  See the commit
11505                  * message for details.
11506                  */
11507                 if (nested_exit_intr_ack_set(vcpu) &&
11508                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11509                     kvm_cpu_has_interrupt(vcpu)) {
11510                         int irq = kvm_cpu_get_interrupt(vcpu);
11511                         WARN_ON(irq < 0);
11512                         vmcs12->vm_exit_intr_info = irq |
11513                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11514                 }
11515
11516                 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11517                                                vmcs12->exit_qualification,
11518                                                vmcs12->idt_vectoring_info_field,
11519                                                vmcs12->vm_exit_intr_info,
11520                                                vmcs12->vm_exit_intr_error_code,
11521                                                KVM_ISA_VMX);
11522
11523                 load_vmcs12_host_state(vcpu, vmcs12);
11524
11525                 return;
11526         }
11527
11528         /*
11529          * After an early L2 VM-entry failure, we're now back
11530          * in L1 which thinks it just finished a VMLAUNCH or
11531          * VMRESUME instruction, so we need to set the failure
11532          * flag and the VM-instruction error field of the VMCS
11533          * accordingly.
11534          */
11535         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11536         /*
11537          * The emulated instruction was already skipped in
11538          * nested_vmx_run, but the updated RIP was never
11539          * written back to the vmcs01.
11540          */
11541         skip_emulated_instruction(vcpu);
11542         vmx->fail = 0;
11543 }
11544
11545 /*
11546  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11547  */
11548 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11549 {
11550         if (is_guest_mode(vcpu)) {
11551                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11552                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11553         }
11554         free_nested(to_vmx(vcpu));
11555 }
11556
11557 /*
11558  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11559  * 23.7 "VM-entry failures during or after loading guest state" (this also
11560  * lists the acceptable exit-reason and exit-qualification parameters).
11561  * It should only be called before L2 actually succeeded to run, and when
11562  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11563  */
11564 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11565                         struct vmcs12 *vmcs12,
11566                         u32 reason, unsigned long qualification)
11567 {
11568         load_vmcs12_host_state(vcpu, vmcs12);
11569         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11570         vmcs12->exit_qualification = qualification;
11571         nested_vmx_succeed(vcpu);
11572         if (enable_shadow_vmcs)
11573                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11574 }
11575
11576 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11577                                struct x86_instruction_info *info,
11578                                enum x86_intercept_stage stage)
11579 {
11580         return X86EMUL_CONTINUE;
11581 }
11582
11583 #ifdef CONFIG_X86_64
11584 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11585 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11586                                   u64 divisor, u64 *result)
11587 {
11588         u64 low = a << shift, high = a >> (64 - shift);
11589
11590         /* To avoid the overflow on divq */
11591         if (high >= divisor)
11592                 return 1;
11593
11594         /* Low hold the result, high hold rem which is discarded */
11595         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11596             "rm" (divisor), "0" (low), "1" (high));
11597         *result = low;
11598
11599         return 0;
11600 }
11601
11602 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11603 {
11604         struct vcpu_vmx *vmx = to_vmx(vcpu);
11605         u64 tscl = rdtsc();
11606         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11607         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11608
11609         /* Convert to host delta tsc if tsc scaling is enabled */
11610         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11611                         u64_shl_div_u64(delta_tsc,
11612                                 kvm_tsc_scaling_ratio_frac_bits,
11613                                 vcpu->arch.tsc_scaling_ratio,
11614                                 &delta_tsc))
11615                 return -ERANGE;
11616
11617         /*
11618          * If the delta tsc can't fit in the 32 bit after the multi shift,
11619          * we can't use the preemption timer.
11620          * It's possible that it fits on later vmentries, but checking
11621          * on every vmentry is costly so we just use an hrtimer.
11622          */
11623         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11624                 return -ERANGE;
11625
11626         vmx->hv_deadline_tsc = tscl + delta_tsc;
11627         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11628                         PIN_BASED_VMX_PREEMPTION_TIMER);
11629
11630         return delta_tsc == 0;
11631 }
11632
11633 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11634 {
11635         struct vcpu_vmx *vmx = to_vmx(vcpu);
11636         vmx->hv_deadline_tsc = -1;
11637         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11638                         PIN_BASED_VMX_PREEMPTION_TIMER);
11639 }
11640 #endif
11641
11642 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11643 {
11644         if (ple_gap)
11645                 shrink_ple_window(vcpu);
11646 }
11647
11648 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11649                                      struct kvm_memory_slot *slot)
11650 {
11651         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11652         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11653 }
11654
11655 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11656                                        struct kvm_memory_slot *slot)
11657 {
11658         kvm_mmu_slot_set_dirty(kvm, slot);
11659 }
11660
11661 static void vmx_flush_log_dirty(struct kvm *kvm)
11662 {
11663         kvm_flush_pml_buffers(kvm);
11664 }
11665
11666 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11667 {
11668         struct vmcs12 *vmcs12;
11669         struct vcpu_vmx *vmx = to_vmx(vcpu);
11670         gpa_t gpa;
11671         struct page *page = NULL;
11672         u64 *pml_address;
11673
11674         if (is_guest_mode(vcpu)) {
11675                 WARN_ON_ONCE(vmx->nested.pml_full);
11676
11677                 /*
11678                  * Check if PML is enabled for the nested guest.
11679                  * Whether eptp bit 6 is set is already checked
11680                  * as part of A/D emulation.
11681                  */
11682                 vmcs12 = get_vmcs12(vcpu);
11683                 if (!nested_cpu_has_pml(vmcs12))
11684                         return 0;
11685
11686                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11687                         vmx->nested.pml_full = true;
11688                         return 1;
11689                 }
11690
11691                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11692
11693                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11694                 if (is_error_page(page))
11695                         return 0;
11696
11697                 pml_address = kmap(page);
11698                 pml_address[vmcs12->guest_pml_index--] = gpa;
11699                 kunmap(page);
11700                 kvm_release_page_clean(page);
11701         }
11702
11703         return 0;
11704 }
11705
11706 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11707                                            struct kvm_memory_slot *memslot,
11708                                            gfn_t offset, unsigned long mask)
11709 {
11710         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11711 }
11712
11713 static void __pi_post_block(struct kvm_vcpu *vcpu)
11714 {
11715         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11716         struct pi_desc old, new;
11717         unsigned int dest;
11718
11719         do {
11720                 old.control = new.control = pi_desc->control;
11721                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
11722                      "Wakeup handler not enabled while the VCPU is blocked\n");
11723
11724                 dest = cpu_physical_id(vcpu->cpu);
11725
11726                 if (x2apic_enabled())
11727                         new.ndst = dest;
11728                 else
11729                         new.ndst = (dest << 8) & 0xFF00;
11730
11731                 /* set 'NV' to 'notification vector' */
11732                 new.nv = POSTED_INTR_VECTOR;
11733         } while (cmpxchg64(&pi_desc->control, old.control,
11734                            new.control) != old.control);
11735
11736         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
11737                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11738                 list_del(&vcpu->blocked_vcpu_list);
11739                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11740                 vcpu->pre_pcpu = -1;
11741         }
11742 }
11743
11744 /*
11745  * This routine does the following things for vCPU which is going
11746  * to be blocked if VT-d PI is enabled.
11747  * - Store the vCPU to the wakeup list, so when interrupts happen
11748  *   we can find the right vCPU to wake up.
11749  * - Change the Posted-interrupt descriptor as below:
11750  *      'NDST' <-- vcpu->pre_pcpu
11751  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11752  * - If 'ON' is set during this process, which means at least one
11753  *   interrupt is posted for this vCPU, we cannot block it, in
11754  *   this case, return 1, otherwise, return 0.
11755  *
11756  */
11757 static int pi_pre_block(struct kvm_vcpu *vcpu)
11758 {
11759         unsigned int dest;
11760         struct pi_desc old, new;
11761         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11762
11763         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11764                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11765                 !kvm_vcpu_apicv_active(vcpu))
11766                 return 0;
11767
11768         WARN_ON(irqs_disabled());
11769         local_irq_disable();
11770         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
11771                 vcpu->pre_pcpu = vcpu->cpu;
11772                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11773                 list_add_tail(&vcpu->blocked_vcpu_list,
11774                               &per_cpu(blocked_vcpu_on_cpu,
11775                                        vcpu->pre_pcpu));
11776                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11777         }
11778
11779         do {
11780                 old.control = new.control = pi_desc->control;
11781
11782                 WARN((pi_desc->sn == 1),
11783                      "Warning: SN field of posted-interrupts "
11784                      "is set before blocking\n");
11785
11786                 /*
11787                  * Since vCPU can be preempted during this process,
11788                  * vcpu->cpu could be different with pre_pcpu, we
11789                  * need to set pre_pcpu as the destination of wakeup
11790                  * notification event, then we can find the right vCPU
11791                  * to wakeup in wakeup handler if interrupts happen
11792                  * when the vCPU is in blocked state.
11793                  */
11794                 dest = cpu_physical_id(vcpu->pre_pcpu);
11795
11796                 if (x2apic_enabled())
11797                         new.ndst = dest;
11798                 else
11799                         new.ndst = (dest << 8) & 0xFF00;
11800
11801                 /* set 'NV' to 'wakeup vector' */
11802                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11803         } while (cmpxchg64(&pi_desc->control, old.control,
11804                            new.control) != old.control);
11805
11806         /* We should not block the vCPU if an interrupt is posted for it.  */
11807         if (pi_test_on(pi_desc) == 1)
11808                 __pi_post_block(vcpu);
11809
11810         local_irq_enable();
11811         return (vcpu->pre_pcpu == -1);
11812 }
11813
11814 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11815 {
11816         if (pi_pre_block(vcpu))
11817                 return 1;
11818
11819         if (kvm_lapic_hv_timer_in_use(vcpu))
11820                 kvm_lapic_switch_to_sw_timer(vcpu);
11821
11822         return 0;
11823 }
11824
11825 static void pi_post_block(struct kvm_vcpu *vcpu)
11826 {
11827         if (vcpu->pre_pcpu == -1)
11828                 return;
11829
11830         WARN_ON(irqs_disabled());
11831         local_irq_disable();
11832         __pi_post_block(vcpu);
11833         local_irq_enable();
11834 }
11835
11836 static void vmx_post_block(struct kvm_vcpu *vcpu)
11837 {
11838         if (kvm_x86_ops->set_hv_timer)
11839                 kvm_lapic_switch_to_hv_timer(vcpu);
11840
11841         pi_post_block(vcpu);
11842 }
11843
11844 /*
11845  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11846  *
11847  * @kvm: kvm
11848  * @host_irq: host irq of the interrupt
11849  * @guest_irq: gsi of the interrupt
11850  * @set: set or unset PI
11851  * returns 0 on success, < 0 on failure
11852  */
11853 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11854                               uint32_t guest_irq, bool set)
11855 {
11856         struct kvm_kernel_irq_routing_entry *e;
11857         struct kvm_irq_routing_table *irq_rt;
11858         struct kvm_lapic_irq irq;
11859         struct kvm_vcpu *vcpu;
11860         struct vcpu_data vcpu_info;
11861         int idx, ret = 0;
11862
11863         if (!kvm_arch_has_assigned_device(kvm) ||
11864                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11865                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11866                 return 0;
11867
11868         idx = srcu_read_lock(&kvm->irq_srcu);
11869         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11870         if (guest_irq >= irq_rt->nr_rt_entries ||
11871             hlist_empty(&irq_rt->map[guest_irq])) {
11872                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11873                              guest_irq, irq_rt->nr_rt_entries);
11874                 goto out;
11875         }
11876
11877         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11878                 if (e->type != KVM_IRQ_ROUTING_MSI)
11879                         continue;
11880                 /*
11881                  * VT-d PI cannot support posting multicast/broadcast
11882                  * interrupts to a vCPU, we still use interrupt remapping
11883                  * for these kind of interrupts.
11884                  *
11885                  * For lowest-priority interrupts, we only support
11886                  * those with single CPU as the destination, e.g. user
11887                  * configures the interrupts via /proc/irq or uses
11888                  * irqbalance to make the interrupts single-CPU.
11889                  *
11890                  * We will support full lowest-priority interrupt later.
11891                  */
11892
11893                 kvm_set_msi_irq(kvm, e, &irq);
11894                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11895                         /*
11896                          * Make sure the IRTE is in remapped mode if
11897                          * we don't handle it in posted mode.
11898                          */
11899                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11900                         if (ret < 0) {
11901                                 printk(KERN_INFO
11902                                    "failed to back to remapped mode, irq: %u\n",
11903                                    host_irq);
11904                                 goto out;
11905                         }
11906
11907                         continue;
11908                 }
11909
11910                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11911                 vcpu_info.vector = irq.vector;
11912
11913                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11914                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11915
11916                 if (set)
11917                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11918                 else
11919                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11920
11921                 if (ret < 0) {
11922                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11923                                         __func__);
11924                         goto out;
11925                 }
11926         }
11927
11928         ret = 0;
11929 out:
11930         srcu_read_unlock(&kvm->irq_srcu, idx);
11931         return ret;
11932 }
11933
11934 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11935 {
11936         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11937                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11938                         FEATURE_CONTROL_LMCE;
11939         else
11940                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11941                         ~FEATURE_CONTROL_LMCE;
11942 }
11943
11944 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11945         .cpu_has_kvm_support = cpu_has_kvm_support,
11946         .disabled_by_bios = vmx_disabled_by_bios,
11947         .hardware_setup = hardware_setup,
11948         .hardware_unsetup = hardware_unsetup,
11949         .check_processor_compatibility = vmx_check_processor_compat,
11950         .hardware_enable = hardware_enable,
11951         .hardware_disable = hardware_disable,
11952         .cpu_has_accelerated_tpr = report_flexpriority,
11953         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11954
11955         .vcpu_create = vmx_create_vcpu,
11956         .vcpu_free = vmx_free_vcpu,
11957         .vcpu_reset = vmx_vcpu_reset,
11958
11959         .prepare_guest_switch = vmx_save_host_state,
11960         .vcpu_load = vmx_vcpu_load,
11961         .vcpu_put = vmx_vcpu_put,
11962
11963         .update_bp_intercept = update_exception_bitmap,
11964         .get_msr = vmx_get_msr,
11965         .set_msr = vmx_set_msr,
11966         .get_segment_base = vmx_get_segment_base,
11967         .get_segment = vmx_get_segment,
11968         .set_segment = vmx_set_segment,
11969         .get_cpl = vmx_get_cpl,
11970         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11971         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11972         .decache_cr3 = vmx_decache_cr3,
11973         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11974         .set_cr0 = vmx_set_cr0,
11975         .set_cr3 = vmx_set_cr3,
11976         .set_cr4 = vmx_set_cr4,
11977         .set_efer = vmx_set_efer,
11978         .get_idt = vmx_get_idt,
11979         .set_idt = vmx_set_idt,
11980         .get_gdt = vmx_get_gdt,
11981         .set_gdt = vmx_set_gdt,
11982         .get_dr6 = vmx_get_dr6,
11983         .set_dr6 = vmx_set_dr6,
11984         .set_dr7 = vmx_set_dr7,
11985         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11986         .cache_reg = vmx_cache_reg,
11987         .get_rflags = vmx_get_rflags,
11988         .set_rflags = vmx_set_rflags,
11989
11990         .tlb_flush = vmx_flush_tlb,
11991
11992         .run = vmx_vcpu_run,
11993         .handle_exit = vmx_handle_exit,
11994         .skip_emulated_instruction = skip_emulated_instruction,
11995         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11996         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11997         .patch_hypercall = vmx_patch_hypercall,
11998         .set_irq = vmx_inject_irq,
11999         .set_nmi = vmx_inject_nmi,
12000         .queue_exception = vmx_queue_exception,
12001         .cancel_injection = vmx_cancel_injection,
12002         .interrupt_allowed = vmx_interrupt_allowed,
12003         .nmi_allowed = vmx_nmi_allowed,
12004         .get_nmi_mask = vmx_get_nmi_mask,
12005         .set_nmi_mask = vmx_set_nmi_mask,
12006         .enable_nmi_window = enable_nmi_window,
12007         .enable_irq_window = enable_irq_window,
12008         .update_cr8_intercept = update_cr8_intercept,
12009         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12010         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12011         .get_enable_apicv = vmx_get_enable_apicv,
12012         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12013         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12014         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12015         .hwapic_irr_update = vmx_hwapic_irr_update,
12016         .hwapic_isr_update = vmx_hwapic_isr_update,
12017         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12018         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12019
12020         .set_tss_addr = vmx_set_tss_addr,
12021         .get_tdp_level = get_ept_level,
12022         .get_mt_mask = vmx_get_mt_mask,
12023
12024         .get_exit_info = vmx_get_exit_info,
12025
12026         .get_lpage_level = vmx_get_lpage_level,
12027
12028         .cpuid_update = vmx_cpuid_update,
12029
12030         .rdtscp_supported = vmx_rdtscp_supported,
12031         .invpcid_supported = vmx_invpcid_supported,
12032
12033         .set_supported_cpuid = vmx_set_supported_cpuid,
12034
12035         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12036
12037         .write_tsc_offset = vmx_write_tsc_offset,
12038
12039         .set_tdp_cr3 = vmx_set_cr3,
12040
12041         .check_intercept = vmx_check_intercept,
12042         .handle_external_intr = vmx_handle_external_intr,
12043         .mpx_supported = vmx_mpx_supported,
12044         .xsaves_supported = vmx_xsaves_supported,
12045
12046         .check_nested_events = vmx_check_nested_events,
12047
12048         .sched_in = vmx_sched_in,
12049
12050         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12051         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12052         .flush_log_dirty = vmx_flush_log_dirty,
12053         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12054         .write_log_dirty = vmx_write_pml_buffer,
12055
12056         .pre_block = vmx_pre_block,
12057         .post_block = vmx_post_block,
12058
12059         .pmu_ops = &intel_pmu_ops,
12060
12061         .update_pi_irte = vmx_update_pi_irte,
12062
12063 #ifdef CONFIG_X86_64
12064         .set_hv_timer = vmx_set_hv_timer,
12065         .cancel_hv_timer = vmx_cancel_hv_timer,
12066 #endif
12067
12068         .setup_mce = vmx_setup_mce,
12069 };
12070
12071 static int __init vmx_init(void)
12072 {
12073         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12074                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12075         if (r)
12076                 return r;
12077
12078 #ifdef CONFIG_KEXEC_CORE
12079         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12080                            crash_vmclear_local_loaded_vmcss);
12081 #endif
12082
12083         return 0;
12084 }
12085
12086 static void __exit vmx_exit(void)
12087 {
12088 #ifdef CONFIG_KEXEC_CORE
12089         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12090         synchronize_rcu();
12091 #endif
12092
12093         kvm_exit();
12094 }
12095
12096 module_init(vmx_init)
12097 module_exit(vmx_exit)