2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72 #include <asm/intel_pt.h>
74 #define CREATE_TRACE_POINTS
77 #define MAX_IO_MSRS 256
78 #define KVM_MAX_MCE_BANKS 32
79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
82 #define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
102 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
103 static void process_nmi(struct kvm_vcpu *vcpu);
104 static void enter_smm(struct kvm_vcpu *vcpu);
105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
106 static void store_regs(struct kvm_vcpu *vcpu);
107 static int sync_regs(struct kvm_vcpu *vcpu);
109 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
110 EXPORT_SYMBOL_GPL(kvm_x86_ops);
112 static bool __read_mostly ignore_msrs = 0;
113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
115 static bool __read_mostly report_ignored_msrs = true;
116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
118 unsigned int min_timer_period_us = 200;
119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
121 static bool __read_mostly kvmclock_periodic_sync = true;
122 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
124 bool __read_mostly kvm_has_tsc_control;
125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
126 u32 __read_mostly kvm_max_guest_tsc_khz;
127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
128 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130 u64 __read_mostly kvm_max_tsc_scaling_ratio;
131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
132 u64 __read_mostly kvm_default_tsc_scaling_ratio;
133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
136 static u32 __read_mostly tsc_tolerance_ppm = 250;
137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
140 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
141 * adaptive tuning starting from default advancment of 1000ns. '0' disables
142 * advancement entirely. Any other value is used as-is and disables adaptive
143 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
145 static int __read_mostly lapic_timer_advance_ns = -1;
146 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
148 static bool __read_mostly vector_hashing = true;
149 module_param(vector_hashing, bool, S_IRUGO);
151 bool __read_mostly enable_vmware_backdoor = false;
152 module_param(enable_vmware_backdoor, bool, S_IRUGO);
153 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
155 static bool __read_mostly force_emulation_prefix = false;
156 module_param(force_emulation_prefix, bool, S_IRUGO);
158 #define KVM_NR_SHARED_MSRS 16
160 struct kvm_shared_msrs_global {
162 u32 msrs[KVM_NR_SHARED_MSRS];
165 struct kvm_shared_msrs {
166 struct user_return_notifier urn;
168 struct kvm_shared_msr_values {
171 } values[KVM_NR_SHARED_MSRS];
174 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
175 static struct kvm_shared_msrs __percpu *shared_msrs;
177 struct kvm_stats_debugfs_item debugfs_entries[] = {
178 { "pf_fixed", VCPU_STAT(pf_fixed) },
179 { "pf_guest", VCPU_STAT(pf_guest) },
180 { "tlb_flush", VCPU_STAT(tlb_flush) },
181 { "invlpg", VCPU_STAT(invlpg) },
182 { "exits", VCPU_STAT(exits) },
183 { "io_exits", VCPU_STAT(io_exits) },
184 { "mmio_exits", VCPU_STAT(mmio_exits) },
185 { "signal_exits", VCPU_STAT(signal_exits) },
186 { "irq_window", VCPU_STAT(irq_window_exits) },
187 { "nmi_window", VCPU_STAT(nmi_window_exits) },
188 { "halt_exits", VCPU_STAT(halt_exits) },
189 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
190 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
191 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
192 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
193 { "hypercalls", VCPU_STAT(hypercalls) },
194 { "request_irq", VCPU_STAT(request_irq_exits) },
195 { "irq_exits", VCPU_STAT(irq_exits) },
196 { "host_state_reload", VCPU_STAT(host_state_reload) },
197 { "fpu_reload", VCPU_STAT(fpu_reload) },
198 { "insn_emulation", VCPU_STAT(insn_emulation) },
199 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
200 { "irq_injections", VCPU_STAT(irq_injections) },
201 { "nmi_injections", VCPU_STAT(nmi_injections) },
202 { "req_event", VCPU_STAT(req_event) },
203 { "l1d_flush", VCPU_STAT(l1d_flush) },
204 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
205 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
206 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
207 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
208 { "mmu_flooded", VM_STAT(mmu_flooded) },
209 { "mmu_recycled", VM_STAT(mmu_recycled) },
210 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
211 { "mmu_unsync", VM_STAT(mmu_unsync) },
212 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
213 { "largepages", VM_STAT(lpages) },
214 { "max_mmu_page_hash_collisions",
215 VM_STAT(max_mmu_page_hash_collisions) },
219 u64 __read_mostly host_xcr0;
221 struct kmem_cache *x86_fpu_cache;
222 EXPORT_SYMBOL_GPL(x86_fpu_cache);
224 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
226 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
230 vcpu->arch.apf.gfns[i] = ~0;
233 static void kvm_on_user_return(struct user_return_notifier *urn)
236 struct kvm_shared_msrs *locals
237 = container_of(urn, struct kvm_shared_msrs, urn);
238 struct kvm_shared_msr_values *values;
242 * Disabling irqs at this point since the following code could be
243 * interrupted and executed through kvm_arch_hardware_disable()
245 local_irq_save(flags);
246 if (locals->registered) {
247 locals->registered = false;
248 user_return_notifier_unregister(urn);
250 local_irq_restore(flags);
251 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
252 values = &locals->values[slot];
253 if (values->host != values->curr) {
254 wrmsrl(shared_msrs_global.msrs[slot], values->host);
255 values->curr = values->host;
260 static void shared_msr_update(unsigned slot, u32 msr)
263 unsigned int cpu = smp_processor_id();
264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
266 /* only read, and nobody should modify it at this time,
267 * so don't need lock */
268 if (slot >= shared_msrs_global.nr) {
269 printk(KERN_ERR "kvm: invalid MSR slot!");
272 rdmsrl_safe(msr, &value);
273 smsr->values[slot].host = value;
274 smsr->values[slot].curr = value;
277 void kvm_define_shared_msr(unsigned slot, u32 msr)
279 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
280 shared_msrs_global.msrs[slot] = msr;
281 if (slot >= shared_msrs_global.nr)
282 shared_msrs_global.nr = slot + 1;
284 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
286 static void kvm_shared_msr_cpu_online(void)
290 for (i = 0; i < shared_msrs_global.nr; ++i)
291 shared_msr_update(i, shared_msrs_global.msrs[i]);
294 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
300 if (((value ^ smsr->values[slot].curr) & mask) == 0)
302 smsr->values[slot].curr = value;
303 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
307 if (!smsr->registered) {
308 smsr->urn.on_user_return = kvm_on_user_return;
309 user_return_notifier_register(&smsr->urn);
310 smsr->registered = true;
314 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
316 static void drop_user_return_notifiers(void)
318 unsigned int cpu = smp_processor_id();
319 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
321 if (smsr->registered)
322 kvm_on_user_return(&smsr->urn);
325 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
327 return vcpu->arch.apic_base;
329 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
331 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
333 return kvm_apic_mode(kvm_get_apic_base(vcpu));
335 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
337 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
339 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
340 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
341 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
342 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
344 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
346 if (!msr_info->host_initiated) {
347 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
349 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
353 kvm_lapic_set_base(vcpu, msr_info->data);
356 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
358 asmlinkage __visible void kvm_spurious_fault(void)
360 /* Fault while not rebooting. We want the trace. */
363 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
365 #define EXCPT_BENIGN 0
366 #define EXCPT_CONTRIBUTORY 1
369 static int exception_class(int vector)
379 return EXCPT_CONTRIBUTORY;
386 #define EXCPT_FAULT 0
388 #define EXCPT_ABORT 2
389 #define EXCPT_INTERRUPT 3
391 static int exception_type(int vector)
395 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
396 return EXCPT_INTERRUPT;
400 /* #DB is trap, as instruction watchpoints are handled elsewhere */
401 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 /* Reserved exceptions will result in fault */
411 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
413 unsigned nr = vcpu->arch.exception.nr;
414 bool has_payload = vcpu->arch.exception.has_payload;
415 unsigned long payload = vcpu->arch.exception.payload;
423 * "Certain debug exceptions may clear bit 0-3. The
424 * remaining contents of the DR6 register are never
425 * cleared by the processor".
427 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
429 * DR6.RTM is set by all #DB exceptions that don't clear it.
431 vcpu->arch.dr6 |= DR6_RTM;
432 vcpu->arch.dr6 |= payload;
434 * Bit 16 should be set in the payload whenever the #DB
435 * exception should clear DR6.RTM. This makes the payload
436 * compatible with the pending debug exceptions under VMX.
437 * Though not currently documented in the SDM, this also
438 * makes the payload compatible with the exit qualification
439 * for #DB exceptions under VMX.
441 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 vcpu->arch.cr2 = payload;
448 vcpu->arch.exception.has_payload = false;
449 vcpu->arch.exception.payload = 0;
451 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
453 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
454 unsigned nr, bool has_error, u32 error_code,
455 bool has_payload, unsigned long payload, bool reinject)
460 kvm_make_request(KVM_REQ_EVENT, vcpu);
462 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
464 if (has_error && !is_protmode(vcpu))
468 * On vmentry, vcpu->arch.exception.pending is only
469 * true if an event injection was blocked by
470 * nested_run_pending. In that case, however,
471 * vcpu_enter_guest requests an immediate exit,
472 * and the guest shouldn't proceed far enough to
475 WARN_ON_ONCE(vcpu->arch.exception.pending);
476 vcpu->arch.exception.injected = true;
477 if (WARN_ON_ONCE(has_payload)) {
479 * A reinjected event has already
480 * delivered its payload.
486 vcpu->arch.exception.pending = true;
487 vcpu->arch.exception.injected = false;
489 vcpu->arch.exception.has_error_code = has_error;
490 vcpu->arch.exception.nr = nr;
491 vcpu->arch.exception.error_code = error_code;
492 vcpu->arch.exception.has_payload = has_payload;
493 vcpu->arch.exception.payload = payload;
495 * In guest mode, payload delivery should be deferred,
496 * so that the L1 hypervisor can intercept #PF before
497 * CR2 is modified (or intercept #DB before DR6 is
498 * modified under nVMX). However, for ABI
499 * compatibility with KVM_GET_VCPU_EVENTS and
500 * KVM_SET_VCPU_EVENTS, we can't delay payload
501 * delivery unless userspace has enabled this
502 * functionality via the per-VM capability,
503 * KVM_CAP_EXCEPTION_PAYLOAD.
505 if (!vcpu->kvm->arch.exception_payload_enabled ||
506 !is_guest_mode(vcpu))
507 kvm_deliver_exception_payload(vcpu);
511 /* to check exception */
512 prev_nr = vcpu->arch.exception.nr;
513 if (prev_nr == DF_VECTOR) {
514 /* triple fault -> shutdown */
515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
518 class1 = exception_class(prev_nr);
519 class2 = exception_class(nr);
520 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
521 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
523 * Generate double fault per SDM Table 5-5. Set
524 * exception.pending = true so that the double fault
525 * can trigger a nested vmexit.
527 vcpu->arch.exception.pending = true;
528 vcpu->arch.exception.injected = false;
529 vcpu->arch.exception.has_error_code = true;
530 vcpu->arch.exception.nr = DF_VECTOR;
531 vcpu->arch.exception.error_code = 0;
532 vcpu->arch.exception.has_payload = false;
533 vcpu->arch.exception.payload = 0;
535 /* replace previous exception with a new one in a hope
536 that instruction re-execution will regenerate lost
541 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
543 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
545 EXPORT_SYMBOL_GPL(kvm_queue_exception);
547 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
549 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
551 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
553 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
554 unsigned long payload)
556 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
560 u32 error_code, unsigned long payload)
562 kvm_multiple_exception(vcpu, nr, true, error_code,
563 true, payload, false);
566 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
569 kvm_inject_gp(vcpu, 0);
571 return kvm_skip_emulated_instruction(vcpu);
575 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
577 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
579 ++vcpu->stat.pf_guest;
580 vcpu->arch.exception.nested_apf =
581 is_guest_mode(vcpu) && fault->async_page_fault;
582 if (vcpu->arch.exception.nested_apf) {
583 vcpu->arch.apf.nested_apf_token = fault->address;
584 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
586 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
590 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
592 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
594 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
595 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
597 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
599 return fault->nested_page_fault;
602 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
604 atomic_inc(&vcpu->arch.nmi_queued);
605 kvm_make_request(KVM_REQ_NMI, vcpu);
607 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
609 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
611 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
613 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
615 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
617 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
619 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
623 * a #GP and return false.
625 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
627 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
629 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 EXPORT_SYMBOL_GPL(kvm_require_cpl);
634 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
636 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 kvm_queue_exception(vcpu, UD_VECTOR);
642 EXPORT_SYMBOL_GPL(kvm_require_dr);
645 * This function will be used to read from the physical memory of the currently
646 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
647 * can read from guest physical or from the guest's guest physical memory.
649 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
650 gfn_t ngfn, void *data, int offset, int len,
653 struct x86_exception exception;
657 ngpa = gfn_to_gpa(ngfn);
658 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
659 if (real_gfn == UNMAPPED_GVA)
662 real_gfn = gpa_to_gfn(real_gfn);
664 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
666 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
668 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
669 void *data, int offset, int len, u32 access)
671 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
672 data, offset, len, access);
676 * Load the pae pdptrs. Return true is they are all valid.
678 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
680 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
681 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
684 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
686 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
687 offset * sizeof(u64), sizeof(pdpte),
688 PFERR_USER_MASK|PFERR_WRITE_MASK);
693 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
694 if ((pdpte[i] & PT_PRESENT_MASK) &&
696 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
704 __set_bit(VCPU_EXREG_PDPTR,
705 (unsigned long *)&vcpu->arch.regs_avail);
706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_dirty);
712 EXPORT_SYMBOL_GPL(load_pdptrs);
714 bool pdptrs_changed(struct kvm_vcpu *vcpu)
716 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
722 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
725 if (!test_bit(VCPU_EXREG_PDPTR,
726 (unsigned long *)&vcpu->arch.regs_avail))
729 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
730 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
731 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
732 PFERR_USER_MASK | PFERR_WRITE_MASK);
735 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
740 EXPORT_SYMBOL_GPL(pdptrs_changed);
742 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
744 unsigned long old_cr0 = kvm_read_cr0(vcpu);
745 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
750 if (cr0 & 0xffffffff00000000UL)
754 cr0 &= ~CR0_RESERVED_BITS;
756 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
759 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
762 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
764 if ((vcpu->arch.efer & EFER_LME)) {
769 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
774 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
779 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
782 kvm_x86_ops->set_cr0(vcpu, cr0);
784 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
785 kvm_clear_async_pf_completion_queue(vcpu);
786 kvm_async_pf_hash_reset(vcpu);
789 if ((cr0 ^ old_cr0) & update_bits)
790 kvm_mmu_reset_context(vcpu);
792 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
793 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
794 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
795 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
799 EXPORT_SYMBOL_GPL(kvm_set_cr0);
801 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
803 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
805 EXPORT_SYMBOL_GPL(kvm_lmsw);
807 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
809 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
810 !vcpu->guest_xcr0_loaded) {
811 /* kvm_set_xcr() also depends on this */
812 if (vcpu->arch.xcr0 != host_xcr0)
813 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
814 vcpu->guest_xcr0_loaded = 1;
817 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
819 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
821 if (vcpu->guest_xcr0_loaded) {
822 if (vcpu->arch.xcr0 != host_xcr0)
823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
824 vcpu->guest_xcr0_loaded = 0;
827 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
829 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
832 u64 old_xcr0 = vcpu->arch.xcr0;
835 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
836 if (index != XCR_XFEATURE_ENABLED_MASK)
838 if (!(xcr0 & XFEATURE_MASK_FP))
840 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
844 * Do not allow the guest to set bits that we do not support
845 * saving. However, xcr0 bit 0 is always set, even if the
846 * emulated CPU does not support XSAVE (see fx_init).
848 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
849 if (xcr0 & ~valid_bits)
852 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
853 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
856 if (xcr0 & XFEATURE_MASK_AVX512) {
857 if (!(xcr0 & XFEATURE_MASK_YMM))
859 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
862 vcpu->arch.xcr0 = xcr0;
864 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
865 kvm_update_cpuid(vcpu);
869 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
871 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
872 __kvm_set_xcr(vcpu, index, xcr)) {
873 kvm_inject_gp(vcpu, 0);
878 EXPORT_SYMBOL_GPL(kvm_set_xcr);
880 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
882 unsigned long old_cr4 = kvm_read_cr4(vcpu);
883 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
884 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
886 if (cr4 & CR4_RESERVED_BITS)
889 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
892 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
895 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
898 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
901 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
904 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
907 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
910 if (is_long_mode(vcpu)) {
911 if (!(cr4 & X86_CR4_PAE))
913 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
914 && ((cr4 ^ old_cr4) & pdptr_bits)
915 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
919 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
920 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
923 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
924 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
928 if (kvm_x86_ops->set_cr4(vcpu, cr4))
931 if (((cr4 ^ old_cr4) & pdptr_bits) ||
932 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
933 kvm_mmu_reset_context(vcpu);
935 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
936 kvm_update_cpuid(vcpu);
940 EXPORT_SYMBOL_GPL(kvm_set_cr4);
942 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
944 bool skip_tlb_flush = false;
946 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
949 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
950 cr3 &= ~X86_CR3_PCID_NOFLUSH;
954 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
955 if (!skip_tlb_flush) {
956 kvm_mmu_sync_roots(vcpu);
957 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
962 if (is_long_mode(vcpu) &&
963 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
965 else if (is_pae(vcpu) && is_paging(vcpu) &&
966 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
969 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
970 vcpu->arch.cr3 = cr3;
971 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
975 EXPORT_SYMBOL_GPL(kvm_set_cr3);
977 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
979 if (cr8 & CR8_RESERVED_BITS)
981 if (lapic_in_kernel(vcpu))
982 kvm_lapic_set_tpr(vcpu, cr8);
984 vcpu->arch.cr8 = cr8;
987 EXPORT_SYMBOL_GPL(kvm_set_cr8);
989 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
991 if (lapic_in_kernel(vcpu))
992 return kvm_lapic_get_cr8(vcpu);
994 return vcpu->arch.cr8;
996 EXPORT_SYMBOL_GPL(kvm_get_cr8);
998 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1002 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1003 for (i = 0; i < KVM_NR_DB_REGS; i++)
1004 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1005 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1009 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1011 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1012 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1015 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1020 dr7 = vcpu->arch.guest_debug_dr7;
1022 dr7 = vcpu->arch.dr7;
1023 kvm_x86_ops->set_dr7(vcpu, dr7);
1024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1025 if (dr7 & DR7_BP_EN_MASK)
1026 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1029 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1031 u64 fixed = DR6_FIXED_1;
1033 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1038 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1042 vcpu->arch.db[dr] = val;
1043 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1044 vcpu->arch.eff_db[dr] = val;
1049 if (val & 0xffffffff00000000ULL)
1050 return -1; /* #GP */
1051 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1052 kvm_update_dr6(vcpu);
1057 if (val & 0xffffffff00000000ULL)
1058 return -1; /* #GP */
1059 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1060 kvm_update_dr7(vcpu);
1067 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1069 if (__kvm_set_dr(vcpu, dr, val)) {
1070 kvm_inject_gp(vcpu, 0);
1075 EXPORT_SYMBOL_GPL(kvm_set_dr);
1077 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1081 *val = vcpu->arch.db[dr];
1086 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1087 *val = vcpu->arch.dr6;
1089 *val = kvm_x86_ops->get_dr6(vcpu);
1094 *val = vcpu->arch.dr7;
1099 EXPORT_SYMBOL_GPL(kvm_get_dr);
1101 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1103 u32 ecx = kvm_rcx_read(vcpu);
1107 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1110 kvm_rax_write(vcpu, (u32)data);
1111 kvm_rdx_write(vcpu, data >> 32);
1114 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1117 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1118 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1120 * This list is modified at module load time to reflect the
1121 * capabilities of the host cpu. This capabilities test skips MSRs that are
1122 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1123 * may depend on host virtualization features rather than host cpu features.
1126 static u32 msrs_to_save[] = {
1127 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1129 #ifdef CONFIG_X86_64
1130 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1132 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1133 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1135 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1136 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1137 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1138 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1139 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1140 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1143 static unsigned num_msrs_to_save;
1145 static u32 emulated_msrs[] = {
1146 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1147 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1148 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1149 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1150 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1151 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1152 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1154 HV_X64_MSR_VP_INDEX,
1155 HV_X64_MSR_VP_RUNTIME,
1156 HV_X64_MSR_SCONTROL,
1157 HV_X64_MSR_STIMER0_CONFIG,
1158 HV_X64_MSR_VP_ASSIST_PAGE,
1159 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1160 HV_X64_MSR_TSC_EMULATION_STATUS,
1162 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1165 MSR_IA32_TSC_ADJUST,
1166 MSR_IA32_TSCDEADLINE,
1167 MSR_IA32_ARCH_CAPABILITIES,
1168 MSR_IA32_MISC_ENABLE,
1169 MSR_IA32_MCG_STATUS,
1171 MSR_IA32_MCG_EXT_CTL,
1175 MSR_MISC_FEATURES_ENABLES,
1176 MSR_AMD64_VIRT_SPEC_CTRL,
1182 static unsigned num_emulated_msrs;
1185 * List of msr numbers which are used to expose MSR-based features that
1186 * can be used by a hypervisor to validate requested CPU features.
1188 static u32 msr_based_features[] = {
1190 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1191 MSR_IA32_VMX_PINBASED_CTLS,
1192 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1193 MSR_IA32_VMX_PROCBASED_CTLS,
1194 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1195 MSR_IA32_VMX_EXIT_CTLS,
1196 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1197 MSR_IA32_VMX_ENTRY_CTLS,
1199 MSR_IA32_VMX_CR0_FIXED0,
1200 MSR_IA32_VMX_CR0_FIXED1,
1201 MSR_IA32_VMX_CR4_FIXED0,
1202 MSR_IA32_VMX_CR4_FIXED1,
1203 MSR_IA32_VMX_VMCS_ENUM,
1204 MSR_IA32_VMX_PROCBASED_CTLS2,
1205 MSR_IA32_VMX_EPT_VPID_CAP,
1206 MSR_IA32_VMX_VMFUNC,
1210 MSR_IA32_ARCH_CAPABILITIES,
1213 static unsigned int num_msr_based_features;
1215 static u64 kvm_get_arch_capabilities(void)
1219 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1223 * If we're doing cache flushes (either "always" or "cond")
1224 * we will do one whenever the guest does a vmlaunch/vmresume.
1225 * If an outer hypervisor is doing the cache flush for us
1226 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1227 * capability to the guest too, and if EPT is disabled we're not
1228 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1229 * require a nested hypervisor to do a flush of its own.
1231 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1232 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1237 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1239 switch (msr->index) {
1240 case MSR_IA32_ARCH_CAPABILITIES:
1241 msr->data = kvm_get_arch_capabilities();
1243 case MSR_IA32_UCODE_REV:
1244 rdmsrl_safe(msr->index, &msr->data);
1247 if (kvm_x86_ops->get_msr_feature(msr))
1253 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1255 struct kvm_msr_entry msr;
1259 r = kvm_get_msr_feature(&msr);
1268 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1270 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1273 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1276 if (efer & (EFER_LME | EFER_LMA) &&
1277 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1280 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1286 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1288 if (efer & efer_reserved_bits)
1291 return __kvm_valid_efer(vcpu, efer);
1293 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1295 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1297 u64 old_efer = vcpu->arch.efer;
1298 u64 efer = msr_info->data;
1300 if (efer & efer_reserved_bits)
1303 if (!msr_info->host_initiated) {
1304 if (!__kvm_valid_efer(vcpu, efer))
1307 if (is_paging(vcpu) &&
1308 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1313 efer |= vcpu->arch.efer & EFER_LMA;
1315 kvm_x86_ops->set_efer(vcpu, efer);
1317 /* Update reserved bits */
1318 if ((efer ^ old_efer) & EFER_NX)
1319 kvm_mmu_reset_context(vcpu);
1324 void kvm_enable_efer_bits(u64 mask)
1326 efer_reserved_bits &= ~mask;
1328 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1331 * Writes msr value into into the appropriate "register".
1332 * Returns 0 on success, non-0 otherwise.
1333 * Assumes vcpu_load() was already called.
1335 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1337 switch (msr->index) {
1340 case MSR_KERNEL_GS_BASE:
1343 if (is_noncanonical_address(msr->data, vcpu))
1346 case MSR_IA32_SYSENTER_EIP:
1347 case MSR_IA32_SYSENTER_ESP:
1349 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1350 * non-canonical address is written on Intel but not on
1351 * AMD (which ignores the top 32-bits, because it does
1352 * not implement 64-bit SYSENTER).
1354 * 64-bit code should hence be able to write a non-canonical
1355 * value on AMD. Making the address canonical ensures that
1356 * vmentry does not fail on Intel after writing a non-canonical
1357 * value, and that something deterministic happens if the guest
1358 * invokes 64-bit SYSENTER.
1360 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1362 return kvm_x86_ops->set_msr(vcpu, msr);
1364 EXPORT_SYMBOL_GPL(kvm_set_msr);
1367 * Adapt set_msr() to msr_io()'s calling convention
1369 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1371 struct msr_data msr;
1375 msr.host_initiated = true;
1376 r = kvm_get_msr(vcpu, &msr);
1384 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1386 struct msr_data msr;
1390 msr.host_initiated = true;
1391 return kvm_set_msr(vcpu, &msr);
1394 #ifdef CONFIG_X86_64
1395 struct pvclock_gtod_data {
1398 struct { /* extract of a clocksource struct */
1411 static struct pvclock_gtod_data pvclock_gtod_data;
1413 static void update_pvclock_gtod(struct timekeeper *tk)
1415 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1418 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1420 write_seqcount_begin(&vdata->seq);
1422 /* copy pvclock gtod data */
1423 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1424 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1425 vdata->clock.mask = tk->tkr_mono.mask;
1426 vdata->clock.mult = tk->tkr_mono.mult;
1427 vdata->clock.shift = tk->tkr_mono.shift;
1429 vdata->boot_ns = boot_ns;
1430 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1432 vdata->wall_time_sec = tk->xtime_sec;
1434 write_seqcount_end(&vdata->seq);
1438 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1441 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1442 * vcpu_enter_guest. This function is only called from
1443 * the physical CPU that is running vcpu.
1445 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1448 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1452 struct pvclock_wall_clock wc;
1453 struct timespec64 boot;
1458 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1463 ++version; /* first time write, random junk */
1467 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1471 * The guest calculates current wall clock time by adding
1472 * system time (updated by kvm_guest_time_update below) to the
1473 * wall clock specified here. guest system time equals host
1474 * system time for us, thus we must fill in host boot time here.
1476 getboottime64(&boot);
1478 if (kvm->arch.kvmclock_offset) {
1479 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1480 boot = timespec64_sub(boot, ts);
1482 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1483 wc.nsec = boot.tv_nsec;
1484 wc.version = version;
1486 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1489 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1492 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1494 do_shl32_div32(dividend, divisor);
1498 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1499 s8 *pshift, u32 *pmultiplier)
1507 scaled64 = scaled_hz;
1508 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1513 tps32 = (uint32_t)tps64;
1514 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1515 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1523 *pmultiplier = div_frac(scaled64, tps32);
1525 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1526 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1529 #ifdef CONFIG_X86_64
1530 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1533 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1534 static unsigned long max_tsc_khz;
1536 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1538 u64 v = (u64)khz * (1000000 + ppm);
1543 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1547 /* Guest TSC same frequency as host TSC? */
1549 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1553 /* TSC scaling supported? */
1554 if (!kvm_has_tsc_control) {
1555 if (user_tsc_khz > tsc_khz) {
1556 vcpu->arch.tsc_catchup = 1;
1557 vcpu->arch.tsc_always_catchup = 1;
1560 WARN(1, "user requested TSC rate below hardware speed\n");
1565 /* TSC scaling required - calculate ratio */
1566 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1567 user_tsc_khz, tsc_khz);
1569 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1570 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1575 vcpu->arch.tsc_scaling_ratio = ratio;
1579 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1581 u32 thresh_lo, thresh_hi;
1582 int use_scaling = 0;
1584 /* tsc_khz can be zero if TSC calibration fails */
1585 if (user_tsc_khz == 0) {
1586 /* set tsc_scaling_ratio to a safe value */
1587 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1591 /* Compute a scale to convert nanoseconds in TSC cycles */
1592 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1593 &vcpu->arch.virtual_tsc_shift,
1594 &vcpu->arch.virtual_tsc_mult);
1595 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1598 * Compute the variation in TSC rate which is acceptable
1599 * within the range of tolerance and decide if the
1600 * rate being applied is within that bounds of the hardware
1601 * rate. If so, no scaling or compensation need be done.
1603 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1604 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1605 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1606 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1609 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1612 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1614 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1615 vcpu->arch.virtual_tsc_mult,
1616 vcpu->arch.virtual_tsc_shift);
1617 tsc += vcpu->arch.this_tsc_write;
1621 static inline int gtod_is_based_on_tsc(int mode)
1623 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1626 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1628 #ifdef CONFIG_X86_64
1630 struct kvm_arch *ka = &vcpu->kvm->arch;
1631 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1633 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1634 atomic_read(&vcpu->kvm->online_vcpus));
1637 * Once the masterclock is enabled, always perform request in
1638 * order to update it.
1640 * In order to enable masterclock, the host clocksource must be TSC
1641 * and the vcpus need to have matched TSCs. When that happens,
1642 * perform request to enable masterclock.
1644 if (ka->use_master_clock ||
1645 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1646 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1648 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1649 atomic_read(&vcpu->kvm->online_vcpus),
1650 ka->use_master_clock, gtod->clock.vclock_mode);
1654 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1656 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1657 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1661 * Multiply tsc by a fixed point number represented by ratio.
1663 * The most significant 64-N bits (mult) of ratio represent the
1664 * integral part of the fixed point number; the remaining N bits
1665 * (frac) represent the fractional part, ie. ratio represents a fixed
1666 * point number (mult + frac * 2^(-N)).
1668 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1670 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1672 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1675 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1678 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1680 if (ratio != kvm_default_tsc_scaling_ratio)
1681 _tsc = __scale_tsc(ratio, tsc);
1685 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1687 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1691 tsc = kvm_scale_tsc(vcpu, rdtsc());
1693 return target_tsc - tsc;
1696 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1698 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1700 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1702 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1704 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1706 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1709 static inline bool kvm_check_tsc_unstable(void)
1711 #ifdef CONFIG_X86_64
1713 * TSC is marked unstable when we're running on Hyper-V,
1714 * 'TSC page' clocksource is good.
1716 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1719 return check_tsc_unstable();
1722 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1724 struct kvm *kvm = vcpu->kvm;
1725 u64 offset, ns, elapsed;
1726 unsigned long flags;
1728 bool already_matched;
1729 u64 data = msr->data;
1730 bool synchronizing = false;
1732 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1733 offset = kvm_compute_tsc_offset(vcpu, data);
1734 ns = ktime_get_boot_ns();
1735 elapsed = ns - kvm->arch.last_tsc_nsec;
1737 if (vcpu->arch.virtual_tsc_khz) {
1738 if (data == 0 && msr->host_initiated) {
1740 * detection of vcpu initialization -- need to sync
1741 * with other vCPUs. This particularly helps to keep
1742 * kvm_clock stable after CPU hotplug
1744 synchronizing = true;
1746 u64 tsc_exp = kvm->arch.last_tsc_write +
1747 nsec_to_cycles(vcpu, elapsed);
1748 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1750 * Special case: TSC write with a small delta (1 second)
1751 * of virtual cycle time against real time is
1752 * interpreted as an attempt to synchronize the CPU.
1754 synchronizing = data < tsc_exp + tsc_hz &&
1755 data + tsc_hz > tsc_exp;
1760 * For a reliable TSC, we can match TSC offsets, and for an unstable
1761 * TSC, we add elapsed time in this computation. We could let the
1762 * compensation code attempt to catch up if we fall behind, but
1763 * it's better to try to match offsets from the beginning.
1765 if (synchronizing &&
1766 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1767 if (!kvm_check_tsc_unstable()) {
1768 offset = kvm->arch.cur_tsc_offset;
1769 pr_debug("kvm: matched tsc offset for %llu\n", data);
1771 u64 delta = nsec_to_cycles(vcpu, elapsed);
1773 offset = kvm_compute_tsc_offset(vcpu, data);
1774 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1777 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1780 * We split periods of matched TSC writes into generations.
1781 * For each generation, we track the original measured
1782 * nanosecond time, offset, and write, so if TSCs are in
1783 * sync, we can match exact offset, and if not, we can match
1784 * exact software computation in compute_guest_tsc()
1786 * These values are tracked in kvm->arch.cur_xxx variables.
1788 kvm->arch.cur_tsc_generation++;
1789 kvm->arch.cur_tsc_nsec = ns;
1790 kvm->arch.cur_tsc_write = data;
1791 kvm->arch.cur_tsc_offset = offset;
1793 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1794 kvm->arch.cur_tsc_generation, data);
1798 * We also track th most recent recorded KHZ, write and time to
1799 * allow the matching interval to be extended at each write.
1801 kvm->arch.last_tsc_nsec = ns;
1802 kvm->arch.last_tsc_write = data;
1803 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1805 vcpu->arch.last_guest_tsc = data;
1807 /* Keep track of which generation this VCPU has synchronized to */
1808 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1809 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1810 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1812 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1813 update_ia32_tsc_adjust_msr(vcpu, offset);
1815 kvm_vcpu_write_tsc_offset(vcpu, offset);
1816 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1818 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1820 kvm->arch.nr_vcpus_matched_tsc = 0;
1821 } else if (!already_matched) {
1822 kvm->arch.nr_vcpus_matched_tsc++;
1825 kvm_track_tsc_matching(vcpu);
1826 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1829 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1831 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1834 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1835 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1838 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1840 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1841 WARN_ON(adjustment < 0);
1842 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1843 adjust_tsc_offset_guest(vcpu, adjustment);
1846 #ifdef CONFIG_X86_64
1848 static u64 read_tsc(void)
1850 u64 ret = (u64)rdtsc_ordered();
1851 u64 last = pvclock_gtod_data.clock.cycle_last;
1853 if (likely(ret >= last))
1857 * GCC likes to generate cmov here, but this branch is extremely
1858 * predictable (it's just a function of time and the likely is
1859 * very likely) and there's a data dependence, so force GCC
1860 * to generate a branch instead. I don't barrier() because
1861 * we don't actually need a barrier, and if this function
1862 * ever gets inlined it will generate worse code.
1868 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1871 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1874 switch (gtod->clock.vclock_mode) {
1875 case VCLOCK_HVCLOCK:
1876 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1878 if (tsc_pg_val != U64_MAX) {
1879 /* TSC page valid */
1880 *mode = VCLOCK_HVCLOCK;
1881 v = (tsc_pg_val - gtod->clock.cycle_last) &
1884 /* TSC page invalid */
1885 *mode = VCLOCK_NONE;
1890 *tsc_timestamp = read_tsc();
1891 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1895 *mode = VCLOCK_NONE;
1898 if (*mode == VCLOCK_NONE)
1899 *tsc_timestamp = v = 0;
1901 return v * gtod->clock.mult;
1904 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1906 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1912 seq = read_seqcount_begin(>od->seq);
1913 ns = gtod->nsec_base;
1914 ns += vgettsc(tsc_timestamp, &mode);
1915 ns >>= gtod->clock.shift;
1916 ns += gtod->boot_ns;
1917 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1923 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1925 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1931 seq = read_seqcount_begin(>od->seq);
1932 ts->tv_sec = gtod->wall_time_sec;
1933 ns = gtod->nsec_base;
1934 ns += vgettsc(tsc_timestamp, &mode);
1935 ns >>= gtod->clock.shift;
1936 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1938 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1944 /* returns true if host is using TSC based clocksource */
1945 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1947 /* checked again under seqlock below */
1948 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1951 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1955 /* returns true if host is using TSC based clocksource */
1956 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1959 /* checked again under seqlock below */
1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1963 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1969 * Assuming a stable TSC across physical CPUS, and a stable TSC
1970 * across virtual CPUs, the following condition is possible.
1971 * Each numbered line represents an event visible to both
1972 * CPUs at the next numbered event.
1974 * "timespecX" represents host monotonic time. "tscX" represents
1977 * VCPU0 on CPU0 | VCPU1 on CPU1
1979 * 1. read timespec0,tsc0
1980 * 2. | timespec1 = timespec0 + N
1982 * 3. transition to guest | transition to guest
1983 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1984 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1985 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1987 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1990 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1992 * - 0 < N - M => M < N
1994 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1995 * always the case (the difference between two distinct xtime instances
1996 * might be smaller then the difference between corresponding TSC reads,
1997 * when updating guest vcpus pvclock areas).
1999 * To avoid that problem, do not allow visibility of distinct
2000 * system_timestamp/tsc_timestamp values simultaneously: use a master
2001 * copy of host monotonic time values. Update that master copy
2004 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2008 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2010 #ifdef CONFIG_X86_64
2011 struct kvm_arch *ka = &kvm->arch;
2013 bool host_tsc_clocksource, vcpus_matched;
2015 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2016 atomic_read(&kvm->online_vcpus));
2019 * If the host uses TSC clock, then passthrough TSC as stable
2022 host_tsc_clocksource = kvm_get_time_and_clockread(
2023 &ka->master_kernel_ns,
2024 &ka->master_cycle_now);
2026 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2027 && !ka->backwards_tsc_observed
2028 && !ka->boot_vcpu_runs_old_kvmclock;
2030 if (ka->use_master_clock)
2031 atomic_set(&kvm_guest_has_master_clock, 1);
2033 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2034 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2039 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2041 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2044 static void kvm_gen_update_masterclock(struct kvm *kvm)
2046 #ifdef CONFIG_X86_64
2048 struct kvm_vcpu *vcpu;
2049 struct kvm_arch *ka = &kvm->arch;
2051 spin_lock(&ka->pvclock_gtod_sync_lock);
2052 kvm_make_mclock_inprogress_request(kvm);
2053 /* no guest entries from this point */
2054 pvclock_update_vm_gtod_copy(kvm);
2056 kvm_for_each_vcpu(i, vcpu, kvm)
2057 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2059 /* guest entries allowed */
2060 kvm_for_each_vcpu(i, vcpu, kvm)
2061 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2063 spin_unlock(&ka->pvclock_gtod_sync_lock);
2067 u64 get_kvmclock_ns(struct kvm *kvm)
2069 struct kvm_arch *ka = &kvm->arch;
2070 struct pvclock_vcpu_time_info hv_clock;
2073 spin_lock(&ka->pvclock_gtod_sync_lock);
2074 if (!ka->use_master_clock) {
2075 spin_unlock(&ka->pvclock_gtod_sync_lock);
2076 return ktime_get_boot_ns() + ka->kvmclock_offset;
2079 hv_clock.tsc_timestamp = ka->master_cycle_now;
2080 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2081 spin_unlock(&ka->pvclock_gtod_sync_lock);
2083 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2086 if (__this_cpu_read(cpu_tsc_khz)) {
2087 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2088 &hv_clock.tsc_shift,
2089 &hv_clock.tsc_to_system_mul);
2090 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2092 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
2099 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2101 struct kvm_vcpu_arch *vcpu = &v->arch;
2102 struct pvclock_vcpu_time_info guest_hv_clock;
2104 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2105 &guest_hv_clock, sizeof(guest_hv_clock))))
2108 /* This VCPU is paused, but it's legal for a guest to read another
2109 * VCPU's kvmclock, so we really have to follow the specification where
2110 * it says that version is odd if data is being modified, and even after
2113 * Version field updates must be kept separate. This is because
2114 * kvm_write_guest_cached might use a "rep movs" instruction, and
2115 * writes within a string instruction are weakly ordered. So there
2116 * are three writes overall.
2118 * As a small optimization, only write the version field in the first
2119 * and third write. The vcpu->pv_time cache is still valid, because the
2120 * version field is the first in the struct.
2122 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2124 if (guest_hv_clock.version & 1)
2125 ++guest_hv_clock.version; /* first time write, random junk */
2127 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2128 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2130 sizeof(vcpu->hv_clock.version));
2134 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2135 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2137 if (vcpu->pvclock_set_guest_stopped_request) {
2138 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2139 vcpu->pvclock_set_guest_stopped_request = false;
2142 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2144 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2146 sizeof(vcpu->hv_clock));
2150 vcpu->hv_clock.version++;
2151 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2153 sizeof(vcpu->hv_clock.version));
2156 static int kvm_guest_time_update(struct kvm_vcpu *v)
2158 unsigned long flags, tgt_tsc_khz;
2159 struct kvm_vcpu_arch *vcpu = &v->arch;
2160 struct kvm_arch *ka = &v->kvm->arch;
2162 u64 tsc_timestamp, host_tsc;
2164 bool use_master_clock;
2170 * If the host uses TSC clock, then passthrough TSC as stable
2173 spin_lock(&ka->pvclock_gtod_sync_lock);
2174 use_master_clock = ka->use_master_clock;
2175 if (use_master_clock) {
2176 host_tsc = ka->master_cycle_now;
2177 kernel_ns = ka->master_kernel_ns;
2179 spin_unlock(&ka->pvclock_gtod_sync_lock);
2181 /* Keep irq disabled to prevent changes to the clock */
2182 local_irq_save(flags);
2183 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2184 if (unlikely(tgt_tsc_khz == 0)) {
2185 local_irq_restore(flags);
2186 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2189 if (!use_master_clock) {
2191 kernel_ns = ktime_get_boot_ns();
2194 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2197 * We may have to catch up the TSC to match elapsed wall clock
2198 * time for two reasons, even if kvmclock is used.
2199 * 1) CPU could have been running below the maximum TSC rate
2200 * 2) Broken TSC compensation resets the base at each VCPU
2201 * entry to avoid unknown leaps of TSC even when running
2202 * again on the same CPU. This may cause apparent elapsed
2203 * time to disappear, and the guest to stand still or run
2206 if (vcpu->tsc_catchup) {
2207 u64 tsc = compute_guest_tsc(v, kernel_ns);
2208 if (tsc > tsc_timestamp) {
2209 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2210 tsc_timestamp = tsc;
2214 local_irq_restore(flags);
2216 /* With all the info we got, fill in the values */
2218 if (kvm_has_tsc_control)
2219 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2221 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2222 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2223 &vcpu->hv_clock.tsc_shift,
2224 &vcpu->hv_clock.tsc_to_system_mul);
2225 vcpu->hw_tsc_khz = tgt_tsc_khz;
2228 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2229 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2230 vcpu->last_guest_tsc = tsc_timestamp;
2232 /* If the host uses TSC clocksource, then it is stable */
2234 if (use_master_clock)
2235 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2237 vcpu->hv_clock.flags = pvclock_flags;
2239 if (vcpu->pv_time_enabled)
2240 kvm_setup_pvclock_page(v);
2241 if (v == kvm_get_vcpu(v->kvm, 0))
2242 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2247 * kvmclock updates which are isolated to a given vcpu, such as
2248 * vcpu->cpu migration, should not allow system_timestamp from
2249 * the rest of the vcpus to remain static. Otherwise ntp frequency
2250 * correction applies to one vcpu's system_timestamp but not
2253 * So in those cases, request a kvmclock update for all vcpus.
2254 * We need to rate-limit these requests though, as they can
2255 * considerably slow guests that have a large number of vcpus.
2256 * The time for a remote vcpu to update its kvmclock is bound
2257 * by the delay we use to rate-limit the updates.
2260 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2262 static void kvmclock_update_fn(struct work_struct *work)
2265 struct delayed_work *dwork = to_delayed_work(work);
2266 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2267 kvmclock_update_work);
2268 struct kvm *kvm = container_of(ka, struct kvm, arch);
2269 struct kvm_vcpu *vcpu;
2271 kvm_for_each_vcpu(i, vcpu, kvm) {
2272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2273 kvm_vcpu_kick(vcpu);
2277 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2279 struct kvm *kvm = v->kvm;
2281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2282 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2283 KVMCLOCK_UPDATE_DELAY);
2286 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2288 static void kvmclock_sync_fn(struct work_struct *work)
2290 struct delayed_work *dwork = to_delayed_work(work);
2291 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2292 kvmclock_sync_work);
2293 struct kvm *kvm = container_of(ka, struct kvm, arch);
2295 if (!kvmclock_periodic_sync)
2298 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2299 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2300 KVMCLOCK_SYNC_PERIOD);
2304 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2306 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2308 /* McStatusWrEn enabled? */
2309 if (guest_cpuid_is_amd(vcpu))
2310 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2315 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2317 u64 mcg_cap = vcpu->arch.mcg_cap;
2318 unsigned bank_num = mcg_cap & 0xff;
2319 u32 msr = msr_info->index;
2320 u64 data = msr_info->data;
2323 case MSR_IA32_MCG_STATUS:
2324 vcpu->arch.mcg_status = data;
2326 case MSR_IA32_MCG_CTL:
2327 if (!(mcg_cap & MCG_CTL_P) &&
2328 (data || !msr_info->host_initiated))
2330 if (data != 0 && data != ~(u64)0)
2332 vcpu->arch.mcg_ctl = data;
2335 if (msr >= MSR_IA32_MC0_CTL &&
2336 msr < MSR_IA32_MCx_CTL(bank_num)) {
2337 u32 offset = msr - MSR_IA32_MC0_CTL;
2338 /* only 0 or all 1s can be written to IA32_MCi_CTL
2339 * some Linux kernels though clear bit 10 in bank 4 to
2340 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2341 * this to avoid an uncatched #GP in the guest
2343 if ((offset & 0x3) == 0 &&
2344 data != 0 && (data | (1 << 10)) != ~(u64)0)
2348 if (!msr_info->host_initiated &&
2349 (offset & 0x3) == 1 && data != 0) {
2350 if (!can_set_mci_status(vcpu))
2354 vcpu->arch.mce_banks[offset] = data;
2362 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2364 struct kvm *kvm = vcpu->kvm;
2365 int lm = is_long_mode(vcpu);
2366 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2367 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2368 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2369 : kvm->arch.xen_hvm_config.blob_size_32;
2370 u32 page_num = data & ~PAGE_MASK;
2371 u64 page_addr = data & PAGE_MASK;
2376 if (page_num >= blob_size)
2379 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2384 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2393 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2395 gpa_t gpa = data & ~0x3f;
2397 /* Bits 3:5 are reserved, Should be zero */
2401 vcpu->arch.apf.msr_val = data;
2403 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2404 kvm_clear_async_pf_completion_queue(vcpu);
2405 kvm_async_pf_hash_reset(vcpu);
2409 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2413 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2414 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2415 kvm_async_pf_wakeup_all(vcpu);
2419 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2421 vcpu->arch.pv_time_enabled = false;
2424 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2426 ++vcpu->stat.tlb_flush;
2427 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2430 static void record_steal_time(struct kvm_vcpu *vcpu)
2432 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2435 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2436 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2440 * Doing a TLB flush here, on the guest's behalf, can avoid
2443 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2444 kvm_vcpu_flush_tlb(vcpu, false);
2446 if (vcpu->arch.st.steal.version & 1)
2447 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2449 vcpu->arch.st.steal.version += 1;
2451 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2452 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2456 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2457 vcpu->arch.st.last_steal;
2458 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2460 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2461 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2465 vcpu->arch.st.steal.version += 1;
2467 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2468 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2471 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2474 u32 msr = msr_info->index;
2475 u64 data = msr_info->data;
2478 case MSR_AMD64_NB_CFG:
2479 case MSR_IA32_UCODE_WRITE:
2480 case MSR_VM_HSAVE_PA:
2481 case MSR_AMD64_PATCH_LOADER:
2482 case MSR_AMD64_BU_CFG2:
2483 case MSR_AMD64_DC_CFG:
2484 case MSR_F15H_EX_CFG:
2487 case MSR_IA32_UCODE_REV:
2488 if (msr_info->host_initiated)
2489 vcpu->arch.microcode_version = data;
2491 case MSR_IA32_ARCH_CAPABILITIES:
2492 if (!msr_info->host_initiated)
2494 vcpu->arch.arch_capabilities = data;
2497 return set_efer(vcpu, msr_info);
2499 data &= ~(u64)0x40; /* ignore flush filter disable */
2500 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2501 data &= ~(u64)0x8; /* ignore TLB cache disable */
2503 /* Handle McStatusWrEn */
2504 if (data == BIT_ULL(18)) {
2505 vcpu->arch.msr_hwcr = data;
2506 } else if (data != 0) {
2507 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2512 case MSR_FAM10H_MMIO_CONF_BASE:
2514 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2519 case MSR_IA32_DEBUGCTLMSR:
2521 /* We support the non-activated case already */
2523 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2524 /* Values other than LBR and BTF are vendor-specific,
2525 thus reserved and should throw a #GP */
2528 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2531 case 0x200 ... 0x2ff:
2532 return kvm_mtrr_set_msr(vcpu, msr, data);
2533 case MSR_IA32_APICBASE:
2534 return kvm_set_apic_base(vcpu, msr_info);
2535 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2536 return kvm_x2apic_msr_write(vcpu, msr, data);
2537 case MSR_IA32_TSCDEADLINE:
2538 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2540 case MSR_IA32_TSC_ADJUST:
2541 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2542 if (!msr_info->host_initiated) {
2543 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2544 adjust_tsc_offset_guest(vcpu, adj);
2546 vcpu->arch.ia32_tsc_adjust_msr = data;
2549 case MSR_IA32_MISC_ENABLE:
2550 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2551 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2552 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2554 vcpu->arch.ia32_misc_enable_msr = data;
2555 kvm_update_cpuid(vcpu);
2557 vcpu->arch.ia32_misc_enable_msr = data;
2560 case MSR_IA32_SMBASE:
2561 if (!msr_info->host_initiated)
2563 vcpu->arch.smbase = data;
2566 kvm_write_tsc(vcpu, msr_info);
2569 if (!msr_info->host_initiated)
2571 vcpu->arch.smi_count = data;
2573 case MSR_KVM_WALL_CLOCK_NEW:
2574 case MSR_KVM_WALL_CLOCK:
2575 vcpu->kvm->arch.wall_clock = data;
2576 kvm_write_wall_clock(vcpu->kvm, data);
2578 case MSR_KVM_SYSTEM_TIME_NEW:
2579 case MSR_KVM_SYSTEM_TIME: {
2580 struct kvm_arch *ka = &vcpu->kvm->arch;
2582 kvmclock_reset(vcpu);
2584 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2585 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2587 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2588 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2590 ka->boot_vcpu_runs_old_kvmclock = tmp;
2593 vcpu->arch.time = data;
2594 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2596 /* we verify if the enable bit is set... */
2600 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2601 &vcpu->arch.pv_time, data & ~1ULL,
2602 sizeof(struct pvclock_vcpu_time_info)))
2603 vcpu->arch.pv_time_enabled = false;
2605 vcpu->arch.pv_time_enabled = true;
2609 case MSR_KVM_ASYNC_PF_EN:
2610 if (kvm_pv_enable_async_pf(vcpu, data))
2613 case MSR_KVM_STEAL_TIME:
2615 if (unlikely(!sched_info_on()))
2618 if (data & KVM_STEAL_RESERVED_MASK)
2621 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2622 data & KVM_STEAL_VALID_BITS,
2623 sizeof(struct kvm_steal_time)))
2626 vcpu->arch.st.msr_val = data;
2628 if (!(data & KVM_MSR_ENABLED))
2631 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2634 case MSR_KVM_PV_EOI_EN:
2635 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2639 case MSR_IA32_MCG_CTL:
2640 case MSR_IA32_MCG_STATUS:
2641 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2642 return set_msr_mce(vcpu, msr_info);
2644 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2645 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2646 pr = true; /* fall through */
2647 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2648 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2649 if (kvm_pmu_is_valid_msr(vcpu, msr))
2650 return kvm_pmu_set_msr(vcpu, msr_info);
2652 if (pr || data != 0)
2653 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2654 "0x%x data 0x%llx\n", msr, data);
2656 case MSR_K7_CLK_CTL:
2658 * Ignore all writes to this no longer documented MSR.
2659 * Writes are only relevant for old K7 processors,
2660 * all pre-dating SVM, but a recommended workaround from
2661 * AMD for these chips. It is possible to specify the
2662 * affected processor models on the command line, hence
2663 * the need to ignore the workaround.
2666 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2667 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2668 case HV_X64_MSR_CRASH_CTL:
2669 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2670 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2671 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2672 case HV_X64_MSR_TSC_EMULATION_STATUS:
2673 return kvm_hv_set_msr_common(vcpu, msr, data,
2674 msr_info->host_initiated);
2675 case MSR_IA32_BBL_CR_CTL3:
2676 /* Drop writes to this legacy MSR -- see rdmsr
2677 * counterpart for further detail.
2679 if (report_ignored_msrs)
2680 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2683 case MSR_AMD64_OSVW_ID_LENGTH:
2684 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2686 vcpu->arch.osvw.length = data;
2688 case MSR_AMD64_OSVW_STATUS:
2689 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2691 vcpu->arch.osvw.status = data;
2693 case MSR_PLATFORM_INFO:
2694 if (!msr_info->host_initiated ||
2695 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2696 cpuid_fault_enabled(vcpu)))
2698 vcpu->arch.msr_platform_info = data;
2700 case MSR_MISC_FEATURES_ENABLES:
2701 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2702 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2703 !supports_cpuid_fault(vcpu)))
2705 vcpu->arch.msr_misc_features_enables = data;
2708 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2709 return xen_hvm_config(vcpu, data);
2710 if (kvm_pmu_is_valid_msr(vcpu, msr))
2711 return kvm_pmu_set_msr(vcpu, msr_info);
2713 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2717 if (report_ignored_msrs)
2719 "ignored wrmsr: 0x%x data 0x%llx\n",
2726 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2730 * Reads an msr value (of 'msr_index') into 'pdata'.
2731 * Returns 0 on success, non-0 otherwise.
2732 * Assumes vcpu_load() was already called.
2734 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2736 return kvm_x86_ops->get_msr(vcpu, msr);
2738 EXPORT_SYMBOL_GPL(kvm_get_msr);
2740 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2743 u64 mcg_cap = vcpu->arch.mcg_cap;
2744 unsigned bank_num = mcg_cap & 0xff;
2747 case MSR_IA32_P5_MC_ADDR:
2748 case MSR_IA32_P5_MC_TYPE:
2751 case MSR_IA32_MCG_CAP:
2752 data = vcpu->arch.mcg_cap;
2754 case MSR_IA32_MCG_CTL:
2755 if (!(mcg_cap & MCG_CTL_P) && !host)
2757 data = vcpu->arch.mcg_ctl;
2759 case MSR_IA32_MCG_STATUS:
2760 data = vcpu->arch.mcg_status;
2763 if (msr >= MSR_IA32_MC0_CTL &&
2764 msr < MSR_IA32_MCx_CTL(bank_num)) {
2765 u32 offset = msr - MSR_IA32_MC0_CTL;
2766 data = vcpu->arch.mce_banks[offset];
2775 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2777 switch (msr_info->index) {
2778 case MSR_IA32_PLATFORM_ID:
2779 case MSR_IA32_EBL_CR_POWERON:
2780 case MSR_IA32_DEBUGCTLMSR:
2781 case MSR_IA32_LASTBRANCHFROMIP:
2782 case MSR_IA32_LASTBRANCHTOIP:
2783 case MSR_IA32_LASTINTFROMIP:
2784 case MSR_IA32_LASTINTTOIP:
2786 case MSR_K8_TSEG_ADDR:
2787 case MSR_K8_TSEG_MASK:
2788 case MSR_VM_HSAVE_PA:
2789 case MSR_K8_INT_PENDING_MSG:
2790 case MSR_AMD64_NB_CFG:
2791 case MSR_FAM10H_MMIO_CONF_BASE:
2792 case MSR_AMD64_BU_CFG2:
2793 case MSR_IA32_PERF_CTL:
2794 case MSR_AMD64_DC_CFG:
2795 case MSR_F15H_EX_CFG:
2798 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2799 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2800 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2801 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2802 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2803 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2804 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2807 case MSR_IA32_UCODE_REV:
2808 msr_info->data = vcpu->arch.microcode_version;
2810 case MSR_IA32_ARCH_CAPABILITIES:
2811 if (!msr_info->host_initiated &&
2812 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2814 msr_info->data = vcpu->arch.arch_capabilities;
2817 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2820 case 0x200 ... 0x2ff:
2821 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2822 case 0xcd: /* fsb frequency */
2826 * MSR_EBC_FREQUENCY_ID
2827 * Conservative value valid for even the basic CPU models.
2828 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2829 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2830 * and 266MHz for model 3, or 4. Set Core Clock
2831 * Frequency to System Bus Frequency Ratio to 1 (bits
2832 * 31:24) even though these are only valid for CPU
2833 * models > 2, however guests may end up dividing or
2834 * multiplying by zero otherwise.
2836 case MSR_EBC_FREQUENCY_ID:
2837 msr_info->data = 1 << 24;
2839 case MSR_IA32_APICBASE:
2840 msr_info->data = kvm_get_apic_base(vcpu);
2842 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2843 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2845 case MSR_IA32_TSCDEADLINE:
2846 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2848 case MSR_IA32_TSC_ADJUST:
2849 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2851 case MSR_IA32_MISC_ENABLE:
2852 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2854 case MSR_IA32_SMBASE:
2855 if (!msr_info->host_initiated)
2857 msr_info->data = vcpu->arch.smbase;
2860 msr_info->data = vcpu->arch.smi_count;
2862 case MSR_IA32_PERF_STATUS:
2863 /* TSC increment by tick */
2864 msr_info->data = 1000ULL;
2865 /* CPU multiplier */
2866 msr_info->data |= (((uint64_t)4ULL) << 40);
2869 msr_info->data = vcpu->arch.efer;
2871 case MSR_KVM_WALL_CLOCK:
2872 case MSR_KVM_WALL_CLOCK_NEW:
2873 msr_info->data = vcpu->kvm->arch.wall_clock;
2875 case MSR_KVM_SYSTEM_TIME:
2876 case MSR_KVM_SYSTEM_TIME_NEW:
2877 msr_info->data = vcpu->arch.time;
2879 case MSR_KVM_ASYNC_PF_EN:
2880 msr_info->data = vcpu->arch.apf.msr_val;
2882 case MSR_KVM_STEAL_TIME:
2883 msr_info->data = vcpu->arch.st.msr_val;
2885 case MSR_KVM_PV_EOI_EN:
2886 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2888 case MSR_IA32_P5_MC_ADDR:
2889 case MSR_IA32_P5_MC_TYPE:
2890 case MSR_IA32_MCG_CAP:
2891 case MSR_IA32_MCG_CTL:
2892 case MSR_IA32_MCG_STATUS:
2893 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2894 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2895 msr_info->host_initiated);
2896 case MSR_K7_CLK_CTL:
2898 * Provide expected ramp-up count for K7. All other
2899 * are set to zero, indicating minimum divisors for
2902 * This prevents guest kernels on AMD host with CPU
2903 * type 6, model 8 and higher from exploding due to
2904 * the rdmsr failing.
2906 msr_info->data = 0x20000000;
2908 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2909 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2910 case HV_X64_MSR_CRASH_CTL:
2911 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2912 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2913 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2914 case HV_X64_MSR_TSC_EMULATION_STATUS:
2915 return kvm_hv_get_msr_common(vcpu,
2916 msr_info->index, &msr_info->data,
2917 msr_info->host_initiated);
2919 case MSR_IA32_BBL_CR_CTL3:
2920 /* This legacy MSR exists but isn't fully documented in current
2921 * silicon. It is however accessed by winxp in very narrow
2922 * scenarios where it sets bit #19, itself documented as
2923 * a "reserved" bit. Best effort attempt to source coherent
2924 * read data here should the balance of the register be
2925 * interpreted by the guest:
2927 * L2 cache control register 3: 64GB range, 256KB size,
2928 * enabled, latency 0x1, configured
2930 msr_info->data = 0xbe702111;
2932 case MSR_AMD64_OSVW_ID_LENGTH:
2933 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2935 msr_info->data = vcpu->arch.osvw.length;
2937 case MSR_AMD64_OSVW_STATUS:
2938 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2940 msr_info->data = vcpu->arch.osvw.status;
2942 case MSR_PLATFORM_INFO:
2943 if (!msr_info->host_initiated &&
2944 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2946 msr_info->data = vcpu->arch.msr_platform_info;
2948 case MSR_MISC_FEATURES_ENABLES:
2949 msr_info->data = vcpu->arch.msr_misc_features_enables;
2952 msr_info->data = vcpu->arch.msr_hwcr;
2955 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2956 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2958 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2962 if (report_ignored_msrs)
2963 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2971 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2974 * Read or write a bunch of msrs. All parameters are kernel addresses.
2976 * @return number of msrs set successfully.
2978 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2979 struct kvm_msr_entry *entries,
2980 int (*do_msr)(struct kvm_vcpu *vcpu,
2981 unsigned index, u64 *data))
2985 for (i = 0; i < msrs->nmsrs; ++i)
2986 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2993 * Read or write a bunch of msrs. Parameters are user addresses.
2995 * @return number of msrs set successfully.
2997 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2998 int (*do_msr)(struct kvm_vcpu *vcpu,
2999 unsigned index, u64 *data),
3002 struct kvm_msrs msrs;
3003 struct kvm_msr_entry *entries;
3008 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3012 if (msrs.nmsrs >= MAX_IO_MSRS)
3015 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3016 entries = memdup_user(user_msrs->entries, size);
3017 if (IS_ERR(entries)) {
3018 r = PTR_ERR(entries);
3022 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3027 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3038 static inline bool kvm_can_mwait_in_guest(void)
3040 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3041 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3042 boot_cpu_has(X86_FEATURE_ARAT);
3045 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3050 case KVM_CAP_IRQCHIP:
3052 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3053 case KVM_CAP_SET_TSS_ADDR:
3054 case KVM_CAP_EXT_CPUID:
3055 case KVM_CAP_EXT_EMUL_CPUID:
3056 case KVM_CAP_CLOCKSOURCE:
3058 case KVM_CAP_NOP_IO_DELAY:
3059 case KVM_CAP_MP_STATE:
3060 case KVM_CAP_SYNC_MMU:
3061 case KVM_CAP_USER_NMI:
3062 case KVM_CAP_REINJECT_CONTROL:
3063 case KVM_CAP_IRQ_INJECT_STATUS:
3064 case KVM_CAP_IOEVENTFD:
3065 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3067 case KVM_CAP_PIT_STATE2:
3068 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3069 case KVM_CAP_XEN_HVM:
3070 case KVM_CAP_VCPU_EVENTS:
3071 case KVM_CAP_HYPERV:
3072 case KVM_CAP_HYPERV_VAPIC:
3073 case KVM_CAP_HYPERV_SPIN:
3074 case KVM_CAP_HYPERV_SYNIC:
3075 case KVM_CAP_HYPERV_SYNIC2:
3076 case KVM_CAP_HYPERV_VP_INDEX:
3077 case KVM_CAP_HYPERV_EVENTFD:
3078 case KVM_CAP_HYPERV_TLBFLUSH:
3079 case KVM_CAP_HYPERV_SEND_IPI:
3080 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3081 case KVM_CAP_HYPERV_CPUID:
3082 case KVM_CAP_PCI_SEGMENT:
3083 case KVM_CAP_DEBUGREGS:
3084 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3086 case KVM_CAP_ASYNC_PF:
3087 case KVM_CAP_GET_TSC_KHZ:
3088 case KVM_CAP_KVMCLOCK_CTRL:
3089 case KVM_CAP_READONLY_MEM:
3090 case KVM_CAP_HYPERV_TIME:
3091 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3092 case KVM_CAP_TSC_DEADLINE_TIMER:
3093 case KVM_CAP_DISABLE_QUIRKS:
3094 case KVM_CAP_SET_BOOT_CPU_ID:
3095 case KVM_CAP_SPLIT_IRQCHIP:
3096 case KVM_CAP_IMMEDIATE_EXIT:
3097 case KVM_CAP_GET_MSR_FEATURES:
3098 case KVM_CAP_MSR_PLATFORM_INFO:
3099 case KVM_CAP_EXCEPTION_PAYLOAD:
3102 case KVM_CAP_SYNC_REGS:
3103 r = KVM_SYNC_X86_VALID_FIELDS;
3105 case KVM_CAP_ADJUST_CLOCK:
3106 r = KVM_CLOCK_TSC_STABLE;
3108 case KVM_CAP_X86_DISABLE_EXITS:
3109 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3110 KVM_X86_DISABLE_EXITS_CSTATE;
3111 if(kvm_can_mwait_in_guest())
3112 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3114 case KVM_CAP_X86_SMM:
3115 /* SMBASE is usually relocated above 1M on modern chipsets,
3116 * and SMM handlers might indeed rely on 4G segment limits,
3117 * so do not report SMM to be available if real mode is
3118 * emulated via vm86 mode. Still, do not go to great lengths
3119 * to avoid userspace's usage of the feature, because it is a
3120 * fringe case that is not enabled except via specific settings
3121 * of the module parameters.
3123 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3126 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3128 case KVM_CAP_NR_VCPUS:
3129 r = KVM_SOFT_MAX_VCPUS;
3131 case KVM_CAP_MAX_VCPUS:
3134 case KVM_CAP_MAX_VCPU_ID:
3135 r = KVM_MAX_VCPU_ID;
3137 case KVM_CAP_PV_MMU: /* obsolete */
3141 r = KVM_MAX_MCE_BANKS;
3144 r = boot_cpu_has(X86_FEATURE_XSAVE);
3146 case KVM_CAP_TSC_CONTROL:
3147 r = kvm_has_tsc_control;
3149 case KVM_CAP_X2APIC_API:
3150 r = KVM_X2APIC_API_VALID_FLAGS;
3152 case KVM_CAP_NESTED_STATE:
3153 r = kvm_x86_ops->get_nested_state ?
3154 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3163 long kvm_arch_dev_ioctl(struct file *filp,
3164 unsigned int ioctl, unsigned long arg)
3166 void __user *argp = (void __user *)arg;
3170 case KVM_GET_MSR_INDEX_LIST: {
3171 struct kvm_msr_list __user *user_msr_list = argp;
3172 struct kvm_msr_list msr_list;
3176 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3179 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3180 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3183 if (n < msr_list.nmsrs)
3186 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3187 num_msrs_to_save * sizeof(u32)))
3189 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3191 num_emulated_msrs * sizeof(u32)))
3196 case KVM_GET_SUPPORTED_CPUID:
3197 case KVM_GET_EMULATED_CPUID: {
3198 struct kvm_cpuid2 __user *cpuid_arg = argp;
3199 struct kvm_cpuid2 cpuid;
3202 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3205 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3211 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3216 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3218 if (copy_to_user(argp, &kvm_mce_cap_supported,
3219 sizeof(kvm_mce_cap_supported)))
3223 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3224 struct kvm_msr_list __user *user_msr_list = argp;
3225 struct kvm_msr_list msr_list;
3229 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3232 msr_list.nmsrs = num_msr_based_features;
3233 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3236 if (n < msr_list.nmsrs)
3239 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3240 num_msr_based_features * sizeof(u32)))
3246 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3256 static void wbinvd_ipi(void *garbage)
3261 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3263 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3266 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3268 /* Address WBINVD may be executed by guest */
3269 if (need_emulate_wbinvd(vcpu)) {
3270 if (kvm_x86_ops->has_wbinvd_exit())
3271 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3272 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3273 smp_call_function_single(vcpu->cpu,
3274 wbinvd_ipi, NULL, 1);
3277 kvm_x86_ops->vcpu_load(vcpu, cpu);
3279 /* Apply any externally detected TSC adjustments (due to suspend) */
3280 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3281 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3282 vcpu->arch.tsc_offset_adjustment = 0;
3283 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3286 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3287 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3288 rdtsc() - vcpu->arch.last_host_tsc;
3290 mark_tsc_unstable("KVM discovered backwards TSC");
3292 if (kvm_check_tsc_unstable()) {
3293 u64 offset = kvm_compute_tsc_offset(vcpu,
3294 vcpu->arch.last_guest_tsc);
3295 kvm_vcpu_write_tsc_offset(vcpu, offset);
3296 vcpu->arch.tsc_catchup = 1;
3299 if (kvm_lapic_hv_timer_in_use(vcpu))
3300 kvm_lapic_restart_hv_timer(vcpu);
3303 * On a host with synchronized TSC, there is no need to update
3304 * kvmclock on vcpu->cpu migration
3306 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3307 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3308 if (vcpu->cpu != cpu)
3309 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3313 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3316 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3318 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3321 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3323 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3324 &vcpu->arch.st.steal.preempted,
3325 offsetof(struct kvm_steal_time, preempted),
3326 sizeof(vcpu->arch.st.steal.preempted));
3329 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3333 if (vcpu->preempted)
3334 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3337 * Disable page faults because we're in atomic context here.
3338 * kvm_write_guest_offset_cached() would call might_fault()
3339 * that relies on pagefault_disable() to tell if there's a
3340 * bug. NOTE: the write to guest memory may not go through if
3341 * during postcopy live migration or if there's heavy guest
3344 pagefault_disable();
3346 * kvm_memslots() will be called by
3347 * kvm_write_guest_offset_cached() so take the srcu lock.
3349 idx = srcu_read_lock(&vcpu->kvm->srcu);
3350 kvm_steal_time_set_preempted(vcpu);
3351 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3353 kvm_x86_ops->vcpu_put(vcpu);
3354 vcpu->arch.last_host_tsc = rdtsc();
3356 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3357 * on every vmexit, but if not, we might have a stale dr6 from the
3358 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3363 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3364 struct kvm_lapic_state *s)
3366 if (vcpu->arch.apicv_active)
3367 kvm_x86_ops->sync_pir_to_irr(vcpu);
3369 return kvm_apic_get_state(vcpu, s);
3372 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3373 struct kvm_lapic_state *s)
3377 r = kvm_apic_set_state(vcpu, s);
3380 update_cr8_intercept(vcpu);
3385 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3387 return (!lapic_in_kernel(vcpu) ||
3388 kvm_apic_accept_pic_intr(vcpu));
3392 * if userspace requested an interrupt window, check that the
3393 * interrupt window is open.
3395 * No need to exit to userspace if we already have an interrupt queued.
3397 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3399 return kvm_arch_interrupt_allowed(vcpu) &&
3400 !kvm_cpu_has_interrupt(vcpu) &&
3401 !kvm_event_needs_reinjection(vcpu) &&
3402 kvm_cpu_accept_dm_intr(vcpu);
3405 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3406 struct kvm_interrupt *irq)
3408 if (irq->irq >= KVM_NR_INTERRUPTS)
3411 if (!irqchip_in_kernel(vcpu->kvm)) {
3412 kvm_queue_interrupt(vcpu, irq->irq, false);
3413 kvm_make_request(KVM_REQ_EVENT, vcpu);
3418 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3419 * fail for in-kernel 8259.
3421 if (pic_in_kernel(vcpu->kvm))
3424 if (vcpu->arch.pending_external_vector != -1)
3427 vcpu->arch.pending_external_vector = irq->irq;
3428 kvm_make_request(KVM_REQ_EVENT, vcpu);
3432 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3434 kvm_inject_nmi(vcpu);
3439 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3441 kvm_make_request(KVM_REQ_SMI, vcpu);
3446 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3447 struct kvm_tpr_access_ctl *tac)
3451 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3455 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3459 unsigned bank_num = mcg_cap & 0xff, bank;
3462 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3464 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3467 vcpu->arch.mcg_cap = mcg_cap;
3468 /* Init IA32_MCG_CTL to all 1s */
3469 if (mcg_cap & MCG_CTL_P)
3470 vcpu->arch.mcg_ctl = ~(u64)0;
3471 /* Init IA32_MCi_CTL to all 1s */
3472 for (bank = 0; bank < bank_num; bank++)
3473 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3475 if (kvm_x86_ops->setup_mce)
3476 kvm_x86_ops->setup_mce(vcpu);
3481 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3482 struct kvm_x86_mce *mce)
3484 u64 mcg_cap = vcpu->arch.mcg_cap;
3485 unsigned bank_num = mcg_cap & 0xff;
3486 u64 *banks = vcpu->arch.mce_banks;
3488 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3491 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3492 * reporting is disabled
3494 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3495 vcpu->arch.mcg_ctl != ~(u64)0)
3497 banks += 4 * mce->bank;
3499 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3500 * reporting is disabled for the bank
3502 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3504 if (mce->status & MCI_STATUS_UC) {
3505 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3506 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3510 if (banks[1] & MCI_STATUS_VAL)
3511 mce->status |= MCI_STATUS_OVER;
3512 banks[2] = mce->addr;
3513 banks[3] = mce->misc;
3514 vcpu->arch.mcg_status = mce->mcg_status;
3515 banks[1] = mce->status;
3516 kvm_queue_exception(vcpu, MC_VECTOR);
3517 } else if (!(banks[1] & MCI_STATUS_VAL)
3518 || !(banks[1] & MCI_STATUS_UC)) {
3519 if (banks[1] & MCI_STATUS_VAL)
3520 mce->status |= MCI_STATUS_OVER;
3521 banks[2] = mce->addr;
3522 banks[3] = mce->misc;
3523 banks[1] = mce->status;
3525 banks[1] |= MCI_STATUS_OVER;
3529 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3530 struct kvm_vcpu_events *events)
3535 * The API doesn't provide the instruction length for software
3536 * exceptions, so don't report them. As long as the guest RIP
3537 * isn't advanced, we should expect to encounter the exception
3540 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3541 events->exception.injected = 0;
3542 events->exception.pending = 0;
3544 events->exception.injected = vcpu->arch.exception.injected;
3545 events->exception.pending = vcpu->arch.exception.pending;
3547 * For ABI compatibility, deliberately conflate
3548 * pending and injected exceptions when
3549 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3551 if (!vcpu->kvm->arch.exception_payload_enabled)
3552 events->exception.injected |=
3553 vcpu->arch.exception.pending;
3555 events->exception.nr = vcpu->arch.exception.nr;
3556 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3557 events->exception.error_code = vcpu->arch.exception.error_code;
3558 events->exception_has_payload = vcpu->arch.exception.has_payload;
3559 events->exception_payload = vcpu->arch.exception.payload;
3561 events->interrupt.injected =
3562 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3563 events->interrupt.nr = vcpu->arch.interrupt.nr;
3564 events->interrupt.soft = 0;
3565 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3567 events->nmi.injected = vcpu->arch.nmi_injected;
3568 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3569 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3570 events->nmi.pad = 0;
3572 events->sipi_vector = 0; /* never valid when reporting to user space */
3574 events->smi.smm = is_smm(vcpu);
3575 events->smi.pending = vcpu->arch.smi_pending;
3576 events->smi.smm_inside_nmi =
3577 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3578 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3580 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3581 | KVM_VCPUEVENT_VALID_SHADOW
3582 | KVM_VCPUEVENT_VALID_SMM);
3583 if (vcpu->kvm->arch.exception_payload_enabled)
3584 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3586 memset(&events->reserved, 0, sizeof(events->reserved));
3589 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3591 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3592 struct kvm_vcpu_events *events)
3594 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3595 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3596 | KVM_VCPUEVENT_VALID_SHADOW
3597 | KVM_VCPUEVENT_VALID_SMM
3598 | KVM_VCPUEVENT_VALID_PAYLOAD))
3601 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3602 if (!vcpu->kvm->arch.exception_payload_enabled)
3604 if (events->exception.pending)
3605 events->exception.injected = 0;
3607 events->exception_has_payload = 0;
3609 events->exception.pending = 0;
3610 events->exception_has_payload = 0;
3613 if ((events->exception.injected || events->exception.pending) &&
3614 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3617 /* INITs are latched while in SMM */
3618 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3619 (events->smi.smm || events->smi.pending) &&
3620 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3624 vcpu->arch.exception.injected = events->exception.injected;
3625 vcpu->arch.exception.pending = events->exception.pending;
3626 vcpu->arch.exception.nr = events->exception.nr;
3627 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3628 vcpu->arch.exception.error_code = events->exception.error_code;
3629 vcpu->arch.exception.has_payload = events->exception_has_payload;
3630 vcpu->arch.exception.payload = events->exception_payload;
3632 vcpu->arch.interrupt.injected = events->interrupt.injected;
3633 vcpu->arch.interrupt.nr = events->interrupt.nr;
3634 vcpu->arch.interrupt.soft = events->interrupt.soft;
3635 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3636 kvm_x86_ops->set_interrupt_shadow(vcpu,
3637 events->interrupt.shadow);
3639 vcpu->arch.nmi_injected = events->nmi.injected;
3640 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3641 vcpu->arch.nmi_pending = events->nmi.pending;
3642 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3644 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3645 lapic_in_kernel(vcpu))
3646 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3648 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3649 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3650 if (events->smi.smm)
3651 vcpu->arch.hflags |= HF_SMM_MASK;
3653 vcpu->arch.hflags &= ~HF_SMM_MASK;
3654 kvm_smm_changed(vcpu);
3657 vcpu->arch.smi_pending = events->smi.pending;
3659 if (events->smi.smm) {
3660 if (events->smi.smm_inside_nmi)
3661 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3663 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3664 if (lapic_in_kernel(vcpu)) {
3665 if (events->smi.latched_init)
3666 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3668 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3673 kvm_make_request(KVM_REQ_EVENT, vcpu);
3678 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3679 struct kvm_debugregs *dbgregs)
3683 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3684 kvm_get_dr(vcpu, 6, &val);
3686 dbgregs->dr7 = vcpu->arch.dr7;
3688 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3691 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3692 struct kvm_debugregs *dbgregs)
3697 if (dbgregs->dr6 & ~0xffffffffull)
3699 if (dbgregs->dr7 & ~0xffffffffull)
3702 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3703 kvm_update_dr0123(vcpu);
3704 vcpu->arch.dr6 = dbgregs->dr6;
3705 kvm_update_dr6(vcpu);
3706 vcpu->arch.dr7 = dbgregs->dr7;
3707 kvm_update_dr7(vcpu);
3712 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3714 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3716 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3717 u64 xstate_bv = xsave->header.xfeatures;
3721 * Copy legacy XSAVE area, to avoid complications with CPUID
3722 * leaves 0 and 1 in the loop below.
3724 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3727 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3728 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3731 * Copy each region from the possibly compacted offset to the
3732 * non-compacted offset.
3734 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3736 u64 xfeature_mask = valid & -valid;
3737 int xfeature_nr = fls64(xfeature_mask) - 1;
3738 void *src = get_xsave_addr(xsave, xfeature_nr);
3741 u32 size, offset, ecx, edx;
3742 cpuid_count(XSTATE_CPUID, xfeature_nr,
3743 &size, &offset, &ecx, &edx);
3744 if (xfeature_nr == XFEATURE_PKRU)
3745 memcpy(dest + offset, &vcpu->arch.pkru,
3746 sizeof(vcpu->arch.pkru));
3748 memcpy(dest + offset, src, size);
3752 valid -= xfeature_mask;
3756 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3758 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3759 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3763 * Copy legacy XSAVE area, to avoid complications with CPUID
3764 * leaves 0 and 1 in the loop below.
3766 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3768 /* Set XSTATE_BV and possibly XCOMP_BV. */
3769 xsave->header.xfeatures = xstate_bv;
3770 if (boot_cpu_has(X86_FEATURE_XSAVES))
3771 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3774 * Copy each region from the non-compacted offset to the
3775 * possibly compacted offset.
3777 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3779 u64 xfeature_mask = valid & -valid;
3780 int xfeature_nr = fls64(xfeature_mask) - 1;
3781 void *dest = get_xsave_addr(xsave, xfeature_nr);
3784 u32 size, offset, ecx, edx;
3785 cpuid_count(XSTATE_CPUID, xfeature_nr,
3786 &size, &offset, &ecx, &edx);
3787 if (xfeature_nr == XFEATURE_PKRU)
3788 memcpy(&vcpu->arch.pkru, src + offset,
3789 sizeof(vcpu->arch.pkru));
3791 memcpy(dest, src + offset, size);
3794 valid -= xfeature_mask;
3798 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3799 struct kvm_xsave *guest_xsave)
3801 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3802 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3803 fill_xsave((u8 *) guest_xsave->region, vcpu);
3805 memcpy(guest_xsave->region,
3806 &vcpu->arch.guest_fpu->state.fxsave,
3807 sizeof(struct fxregs_state));
3808 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3809 XFEATURE_MASK_FPSSE;
3813 #define XSAVE_MXCSR_OFFSET 24
3815 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3816 struct kvm_xsave *guest_xsave)
3819 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3820 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3822 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3824 * Here we allow setting states that are not present in
3825 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3826 * with old userspace.
3828 if (xstate_bv & ~kvm_supported_xcr0() ||
3829 mxcsr & ~mxcsr_feature_mask)
3831 load_xsave(vcpu, (u8 *)guest_xsave->region);
3833 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3834 mxcsr & ~mxcsr_feature_mask)
3836 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3837 guest_xsave->region, sizeof(struct fxregs_state));
3842 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3843 struct kvm_xcrs *guest_xcrs)
3845 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3846 guest_xcrs->nr_xcrs = 0;
3850 guest_xcrs->nr_xcrs = 1;
3851 guest_xcrs->flags = 0;
3852 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3853 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3856 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3857 struct kvm_xcrs *guest_xcrs)
3861 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3864 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3867 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3868 /* Only support XCR0 currently */
3869 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3870 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3871 guest_xcrs->xcrs[i].value);
3880 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3881 * stopped by the hypervisor. This function will be called from the host only.
3882 * EINVAL is returned when the host attempts to set the flag for a guest that
3883 * does not support pv clocks.
3885 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3887 if (!vcpu->arch.pv_time_enabled)
3889 vcpu->arch.pvclock_set_guest_stopped_request = true;
3890 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3894 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3895 struct kvm_enable_cap *cap)
3898 uint16_t vmcs_version;
3899 void __user *user_ptr;
3905 case KVM_CAP_HYPERV_SYNIC2:
3910 case KVM_CAP_HYPERV_SYNIC:
3911 if (!irqchip_in_kernel(vcpu->kvm))
3913 return kvm_hv_activate_synic(vcpu, cap->cap ==
3914 KVM_CAP_HYPERV_SYNIC2);
3915 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3916 if (!kvm_x86_ops->nested_enable_evmcs)
3918 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3920 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3921 if (copy_to_user(user_ptr, &vmcs_version,
3922 sizeof(vmcs_version)))
3932 long kvm_arch_vcpu_ioctl(struct file *filp,
3933 unsigned int ioctl, unsigned long arg)
3935 struct kvm_vcpu *vcpu = filp->private_data;
3936 void __user *argp = (void __user *)arg;
3939 struct kvm_lapic_state *lapic;
3940 struct kvm_xsave *xsave;
3941 struct kvm_xcrs *xcrs;
3949 case KVM_GET_LAPIC: {
3951 if (!lapic_in_kernel(vcpu))
3953 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3954 GFP_KERNEL_ACCOUNT);
3959 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3963 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3968 case KVM_SET_LAPIC: {
3970 if (!lapic_in_kernel(vcpu))
3972 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3973 if (IS_ERR(u.lapic)) {
3974 r = PTR_ERR(u.lapic);
3978 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3981 case KVM_INTERRUPT: {
3982 struct kvm_interrupt irq;
3985 if (copy_from_user(&irq, argp, sizeof(irq)))
3987 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3991 r = kvm_vcpu_ioctl_nmi(vcpu);
3995 r = kvm_vcpu_ioctl_smi(vcpu);
3998 case KVM_SET_CPUID: {
3999 struct kvm_cpuid __user *cpuid_arg = argp;
4000 struct kvm_cpuid cpuid;
4003 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4005 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4008 case KVM_SET_CPUID2: {
4009 struct kvm_cpuid2 __user *cpuid_arg = argp;
4010 struct kvm_cpuid2 cpuid;
4013 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4015 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4016 cpuid_arg->entries);
4019 case KVM_GET_CPUID2: {
4020 struct kvm_cpuid2 __user *cpuid_arg = argp;
4021 struct kvm_cpuid2 cpuid;
4024 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4026 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4027 cpuid_arg->entries);
4031 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4036 case KVM_GET_MSRS: {
4037 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4038 r = msr_io(vcpu, argp, do_get_msr, 1);
4039 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4042 case KVM_SET_MSRS: {
4043 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4044 r = msr_io(vcpu, argp, do_set_msr, 0);
4045 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4048 case KVM_TPR_ACCESS_REPORTING: {
4049 struct kvm_tpr_access_ctl tac;
4052 if (copy_from_user(&tac, argp, sizeof(tac)))
4054 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4058 if (copy_to_user(argp, &tac, sizeof(tac)))
4063 case KVM_SET_VAPIC_ADDR: {
4064 struct kvm_vapic_addr va;
4068 if (!lapic_in_kernel(vcpu))
4071 if (copy_from_user(&va, argp, sizeof(va)))
4073 idx = srcu_read_lock(&vcpu->kvm->srcu);
4074 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4075 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4078 case KVM_X86_SETUP_MCE: {
4082 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4084 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4087 case KVM_X86_SET_MCE: {
4088 struct kvm_x86_mce mce;
4091 if (copy_from_user(&mce, argp, sizeof(mce)))
4093 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4096 case KVM_GET_VCPU_EVENTS: {
4097 struct kvm_vcpu_events events;
4099 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4102 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4107 case KVM_SET_VCPU_EVENTS: {
4108 struct kvm_vcpu_events events;
4111 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4114 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4117 case KVM_GET_DEBUGREGS: {
4118 struct kvm_debugregs dbgregs;
4120 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4123 if (copy_to_user(argp, &dbgregs,
4124 sizeof(struct kvm_debugregs)))
4129 case KVM_SET_DEBUGREGS: {
4130 struct kvm_debugregs dbgregs;
4133 if (copy_from_user(&dbgregs, argp,
4134 sizeof(struct kvm_debugregs)))
4137 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4140 case KVM_GET_XSAVE: {
4141 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4146 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4149 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4154 case KVM_SET_XSAVE: {
4155 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4156 if (IS_ERR(u.xsave)) {
4157 r = PTR_ERR(u.xsave);
4161 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4164 case KVM_GET_XCRS: {
4165 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4170 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4173 if (copy_to_user(argp, u.xcrs,
4174 sizeof(struct kvm_xcrs)))
4179 case KVM_SET_XCRS: {
4180 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4181 if (IS_ERR(u.xcrs)) {
4182 r = PTR_ERR(u.xcrs);
4186 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4189 case KVM_SET_TSC_KHZ: {
4193 user_tsc_khz = (u32)arg;
4195 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4198 if (user_tsc_khz == 0)
4199 user_tsc_khz = tsc_khz;
4201 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4206 case KVM_GET_TSC_KHZ: {
4207 r = vcpu->arch.virtual_tsc_khz;
4210 case KVM_KVMCLOCK_CTRL: {
4211 r = kvm_set_guest_paused(vcpu);
4214 case KVM_ENABLE_CAP: {
4215 struct kvm_enable_cap cap;
4218 if (copy_from_user(&cap, argp, sizeof(cap)))
4220 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4223 case KVM_GET_NESTED_STATE: {
4224 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4228 if (!kvm_x86_ops->get_nested_state)
4231 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4233 if (get_user(user_data_size, &user_kvm_nested_state->size))
4236 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4241 if (r > user_data_size) {
4242 if (put_user(r, &user_kvm_nested_state->size))
4252 case KVM_SET_NESTED_STATE: {
4253 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4254 struct kvm_nested_state kvm_state;
4257 if (!kvm_x86_ops->set_nested_state)
4261 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4265 if (kvm_state.size < sizeof(kvm_state))
4268 if (kvm_state.flags &
4269 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4270 | KVM_STATE_NESTED_EVMCS))
4273 /* nested_run_pending implies guest_mode. */
4274 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4275 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4278 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4281 case KVM_GET_SUPPORTED_HV_CPUID: {
4282 struct kvm_cpuid2 __user *cpuid_arg = argp;
4283 struct kvm_cpuid2 cpuid;
4286 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4289 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4290 cpuid_arg->entries);
4295 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4310 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4312 return VM_FAULT_SIGBUS;
4315 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4319 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4321 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4325 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4328 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4331 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4332 unsigned long kvm_nr_mmu_pages)
4334 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4337 mutex_lock(&kvm->slots_lock);
4339 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4340 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4342 mutex_unlock(&kvm->slots_lock);
4346 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4348 return kvm->arch.n_max_mmu_pages;
4351 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4353 struct kvm_pic *pic = kvm->arch.vpic;
4357 switch (chip->chip_id) {
4358 case KVM_IRQCHIP_PIC_MASTER:
4359 memcpy(&chip->chip.pic, &pic->pics[0],
4360 sizeof(struct kvm_pic_state));
4362 case KVM_IRQCHIP_PIC_SLAVE:
4363 memcpy(&chip->chip.pic, &pic->pics[1],
4364 sizeof(struct kvm_pic_state));
4366 case KVM_IRQCHIP_IOAPIC:
4367 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4376 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4378 struct kvm_pic *pic = kvm->arch.vpic;
4382 switch (chip->chip_id) {
4383 case KVM_IRQCHIP_PIC_MASTER:
4384 spin_lock(&pic->lock);
4385 memcpy(&pic->pics[0], &chip->chip.pic,
4386 sizeof(struct kvm_pic_state));
4387 spin_unlock(&pic->lock);
4389 case KVM_IRQCHIP_PIC_SLAVE:
4390 spin_lock(&pic->lock);
4391 memcpy(&pic->pics[1], &chip->chip.pic,
4392 sizeof(struct kvm_pic_state));
4393 spin_unlock(&pic->lock);
4395 case KVM_IRQCHIP_IOAPIC:
4396 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4402 kvm_pic_update_irq(pic);
4406 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4408 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4410 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4412 mutex_lock(&kps->lock);
4413 memcpy(ps, &kps->channels, sizeof(*ps));
4414 mutex_unlock(&kps->lock);
4418 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4421 struct kvm_pit *pit = kvm->arch.vpit;
4423 mutex_lock(&pit->pit_state.lock);
4424 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4425 for (i = 0; i < 3; i++)
4426 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4427 mutex_unlock(&pit->pit_state.lock);
4431 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4433 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4434 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4435 sizeof(ps->channels));
4436 ps->flags = kvm->arch.vpit->pit_state.flags;
4437 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4438 memset(&ps->reserved, 0, sizeof(ps->reserved));
4442 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4446 u32 prev_legacy, cur_legacy;
4447 struct kvm_pit *pit = kvm->arch.vpit;
4449 mutex_lock(&pit->pit_state.lock);
4450 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4451 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4452 if (!prev_legacy && cur_legacy)
4454 memcpy(&pit->pit_state.channels, &ps->channels,
4455 sizeof(pit->pit_state.channels));
4456 pit->pit_state.flags = ps->flags;
4457 for (i = 0; i < 3; i++)
4458 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4460 mutex_unlock(&pit->pit_state.lock);
4464 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4465 struct kvm_reinject_control *control)
4467 struct kvm_pit *pit = kvm->arch.vpit;
4472 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4473 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4474 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4476 mutex_lock(&pit->pit_state.lock);
4477 kvm_pit_set_reinject(pit, control->pit_reinject);
4478 mutex_unlock(&pit->pit_state.lock);
4484 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4485 * @kvm: kvm instance
4486 * @log: slot id and address to which we copy the log
4488 * Steps 1-4 below provide general overview of dirty page logging. See
4489 * kvm_get_dirty_log_protect() function description for additional details.
4491 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4492 * always flush the TLB (step 4) even if previous step failed and the dirty
4493 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4494 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4495 * writes will be marked dirty for next log read.
4497 * 1. Take a snapshot of the bit and clear it if needed.
4498 * 2. Write protect the corresponding page.
4499 * 3. Copy the snapshot to the userspace.
4500 * 4. Flush TLB's if needed.
4502 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4507 mutex_lock(&kvm->slots_lock);
4510 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4512 if (kvm_x86_ops->flush_log_dirty)
4513 kvm_x86_ops->flush_log_dirty(kvm);
4515 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4518 * All the TLBs can be flushed out of mmu lock, see the comments in
4519 * kvm_mmu_slot_remove_write_access().
4521 lockdep_assert_held(&kvm->slots_lock);
4523 kvm_flush_remote_tlbs(kvm);
4525 mutex_unlock(&kvm->slots_lock);
4529 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4534 mutex_lock(&kvm->slots_lock);
4537 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4539 if (kvm_x86_ops->flush_log_dirty)
4540 kvm_x86_ops->flush_log_dirty(kvm);
4542 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4545 * All the TLBs can be flushed out of mmu lock, see the comments in
4546 * kvm_mmu_slot_remove_write_access().
4548 lockdep_assert_held(&kvm->slots_lock);
4550 kvm_flush_remote_tlbs(kvm);
4552 mutex_unlock(&kvm->slots_lock);
4556 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4559 if (!irqchip_in_kernel(kvm))
4562 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4563 irq_event->irq, irq_event->level,
4568 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4569 struct kvm_enable_cap *cap)
4577 case KVM_CAP_DISABLE_QUIRKS:
4578 kvm->arch.disabled_quirks = cap->args[0];
4581 case KVM_CAP_SPLIT_IRQCHIP: {
4582 mutex_lock(&kvm->lock);
4584 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4585 goto split_irqchip_unlock;
4587 if (irqchip_in_kernel(kvm))
4588 goto split_irqchip_unlock;
4589 if (kvm->created_vcpus)
4590 goto split_irqchip_unlock;
4591 r = kvm_setup_empty_irq_routing(kvm);
4593 goto split_irqchip_unlock;
4594 /* Pairs with irqchip_in_kernel. */
4596 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4597 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4599 split_irqchip_unlock:
4600 mutex_unlock(&kvm->lock);
4603 case KVM_CAP_X2APIC_API:
4605 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4608 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4609 kvm->arch.x2apic_format = true;
4610 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4611 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4615 case KVM_CAP_X86_DISABLE_EXITS:
4617 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4620 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4621 kvm_can_mwait_in_guest())
4622 kvm->arch.mwait_in_guest = true;
4623 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4624 kvm->arch.hlt_in_guest = true;
4625 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4626 kvm->arch.pause_in_guest = true;
4627 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4628 kvm->arch.cstate_in_guest = true;
4631 case KVM_CAP_MSR_PLATFORM_INFO:
4632 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4635 case KVM_CAP_EXCEPTION_PAYLOAD:
4636 kvm->arch.exception_payload_enabled = cap->args[0];
4646 long kvm_arch_vm_ioctl(struct file *filp,
4647 unsigned int ioctl, unsigned long arg)
4649 struct kvm *kvm = filp->private_data;
4650 void __user *argp = (void __user *)arg;
4653 * This union makes it completely explicit to gcc-3.x
4654 * that these two variables' stack usage should be
4655 * combined, not added together.
4658 struct kvm_pit_state ps;
4659 struct kvm_pit_state2 ps2;
4660 struct kvm_pit_config pit_config;
4664 case KVM_SET_TSS_ADDR:
4665 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4667 case KVM_SET_IDENTITY_MAP_ADDR: {
4670 mutex_lock(&kvm->lock);
4672 if (kvm->created_vcpus)
4673 goto set_identity_unlock;
4675 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4676 goto set_identity_unlock;
4677 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4678 set_identity_unlock:
4679 mutex_unlock(&kvm->lock);
4682 case KVM_SET_NR_MMU_PAGES:
4683 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4685 case KVM_GET_NR_MMU_PAGES:
4686 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4688 case KVM_CREATE_IRQCHIP: {
4689 mutex_lock(&kvm->lock);
4692 if (irqchip_in_kernel(kvm))
4693 goto create_irqchip_unlock;
4696 if (kvm->created_vcpus)
4697 goto create_irqchip_unlock;
4699 r = kvm_pic_init(kvm);
4701 goto create_irqchip_unlock;
4703 r = kvm_ioapic_init(kvm);
4705 kvm_pic_destroy(kvm);
4706 goto create_irqchip_unlock;
4709 r = kvm_setup_default_irq_routing(kvm);
4711 kvm_ioapic_destroy(kvm);
4712 kvm_pic_destroy(kvm);
4713 goto create_irqchip_unlock;
4715 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4717 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4718 create_irqchip_unlock:
4719 mutex_unlock(&kvm->lock);
4722 case KVM_CREATE_PIT:
4723 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4725 case KVM_CREATE_PIT2:
4727 if (copy_from_user(&u.pit_config, argp,
4728 sizeof(struct kvm_pit_config)))
4731 mutex_lock(&kvm->lock);
4734 goto create_pit_unlock;
4736 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4740 mutex_unlock(&kvm->lock);
4742 case KVM_GET_IRQCHIP: {
4743 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4744 struct kvm_irqchip *chip;
4746 chip = memdup_user(argp, sizeof(*chip));
4753 if (!irqchip_kernel(kvm))
4754 goto get_irqchip_out;
4755 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4757 goto get_irqchip_out;
4759 if (copy_to_user(argp, chip, sizeof(*chip)))
4760 goto get_irqchip_out;
4766 case KVM_SET_IRQCHIP: {
4767 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4768 struct kvm_irqchip *chip;
4770 chip = memdup_user(argp, sizeof(*chip));
4777 if (!irqchip_kernel(kvm))
4778 goto set_irqchip_out;
4779 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4781 goto set_irqchip_out;
4789 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4792 if (!kvm->arch.vpit)
4794 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4798 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4805 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4808 if (!kvm->arch.vpit)
4810 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4813 case KVM_GET_PIT2: {
4815 if (!kvm->arch.vpit)
4817 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4821 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4826 case KVM_SET_PIT2: {
4828 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4831 if (!kvm->arch.vpit)
4833 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4836 case KVM_REINJECT_CONTROL: {
4837 struct kvm_reinject_control control;
4839 if (copy_from_user(&control, argp, sizeof(control)))
4841 r = kvm_vm_ioctl_reinject(kvm, &control);
4844 case KVM_SET_BOOT_CPU_ID:
4846 mutex_lock(&kvm->lock);
4847 if (kvm->created_vcpus)
4850 kvm->arch.bsp_vcpu_id = arg;
4851 mutex_unlock(&kvm->lock);
4853 case KVM_XEN_HVM_CONFIG: {
4854 struct kvm_xen_hvm_config xhc;
4856 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4861 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4865 case KVM_SET_CLOCK: {
4866 struct kvm_clock_data user_ns;
4870 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4879 * TODO: userspace has to take care of races with VCPU_RUN, so
4880 * kvm_gen_update_masterclock() can be cut down to locked
4881 * pvclock_update_vm_gtod_copy().
4883 kvm_gen_update_masterclock(kvm);
4884 now_ns = get_kvmclock_ns(kvm);
4885 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4886 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4889 case KVM_GET_CLOCK: {
4890 struct kvm_clock_data user_ns;
4893 now_ns = get_kvmclock_ns(kvm);
4894 user_ns.clock = now_ns;
4895 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4896 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4899 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4904 case KVM_MEMORY_ENCRYPT_OP: {
4906 if (kvm_x86_ops->mem_enc_op)
4907 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4910 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4911 struct kvm_enc_region region;
4914 if (copy_from_user(®ion, argp, sizeof(region)))
4918 if (kvm_x86_ops->mem_enc_reg_region)
4919 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4922 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4923 struct kvm_enc_region region;
4926 if (copy_from_user(®ion, argp, sizeof(region)))
4930 if (kvm_x86_ops->mem_enc_unreg_region)
4931 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4934 case KVM_HYPERV_EVENTFD: {
4935 struct kvm_hyperv_eventfd hvevfd;
4938 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4940 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4950 static void kvm_init_msr_list(void)
4955 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4956 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4960 * Even MSRs that are valid in the host may not be exposed
4961 * to the guests in some cases.
4963 switch (msrs_to_save[i]) {
4964 case MSR_IA32_BNDCFGS:
4965 if (!kvm_mpx_supported())
4969 if (!kvm_x86_ops->rdtscp_supported())
4972 case MSR_IA32_RTIT_CTL:
4973 case MSR_IA32_RTIT_STATUS:
4974 if (!kvm_x86_ops->pt_supported())
4977 case MSR_IA32_RTIT_CR3_MATCH:
4978 if (!kvm_x86_ops->pt_supported() ||
4979 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4982 case MSR_IA32_RTIT_OUTPUT_BASE:
4983 case MSR_IA32_RTIT_OUTPUT_MASK:
4984 if (!kvm_x86_ops->pt_supported() ||
4985 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4986 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4989 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4990 if (!kvm_x86_ops->pt_supported() ||
4991 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4992 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5001 msrs_to_save[j] = msrs_to_save[i];
5004 num_msrs_to_save = j;
5006 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5007 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5011 emulated_msrs[j] = emulated_msrs[i];
5014 num_emulated_msrs = j;
5016 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5017 struct kvm_msr_entry msr;
5019 msr.index = msr_based_features[i];
5020 if (kvm_get_msr_feature(&msr))
5024 msr_based_features[j] = msr_based_features[i];
5027 num_msr_based_features = j;
5030 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5038 if (!(lapic_in_kernel(vcpu) &&
5039 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5040 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5051 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5058 if (!(lapic_in_kernel(vcpu) &&
5059 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5061 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5063 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5073 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5074 struct kvm_segment *var, int seg)
5076 kvm_x86_ops->set_segment(vcpu, var, seg);
5079 void kvm_get_segment(struct kvm_vcpu *vcpu,
5080 struct kvm_segment *var, int seg)
5082 kvm_x86_ops->get_segment(vcpu, var, seg);
5085 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5086 struct x86_exception *exception)
5090 BUG_ON(!mmu_is_nested(vcpu));
5092 /* NPT walks are always user-walks */
5093 access |= PFERR_USER_MASK;
5094 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5099 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5100 struct x86_exception *exception)
5102 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5103 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5106 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5107 struct x86_exception *exception)
5109 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5110 access |= PFERR_FETCH_MASK;
5111 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5114 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5115 struct x86_exception *exception)
5117 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5118 access |= PFERR_WRITE_MASK;
5119 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5122 /* uses this to access any guest's mapped memory without checking CPL */
5123 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5124 struct x86_exception *exception)
5126 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5129 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5130 struct kvm_vcpu *vcpu, u32 access,
5131 struct x86_exception *exception)
5134 int r = X86EMUL_CONTINUE;
5137 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5139 unsigned offset = addr & (PAGE_SIZE-1);
5140 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5143 if (gpa == UNMAPPED_GVA)
5144 return X86EMUL_PROPAGATE_FAULT;
5145 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5148 r = X86EMUL_IO_NEEDED;
5160 /* used for instruction fetching */
5161 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5162 gva_t addr, void *val, unsigned int bytes,
5163 struct x86_exception *exception)
5165 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5166 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5170 /* Inline kvm_read_guest_virt_helper for speed. */
5171 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5173 if (unlikely(gpa == UNMAPPED_GVA))
5174 return X86EMUL_PROPAGATE_FAULT;
5176 offset = addr & (PAGE_SIZE-1);
5177 if (WARN_ON(offset + bytes > PAGE_SIZE))
5178 bytes = (unsigned)PAGE_SIZE - offset;
5179 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5181 if (unlikely(ret < 0))
5182 return X86EMUL_IO_NEEDED;
5184 return X86EMUL_CONTINUE;
5187 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5188 gva_t addr, void *val, unsigned int bytes,
5189 struct x86_exception *exception)
5191 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5194 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5195 * is returned, but our callers are not ready for that and they blindly
5196 * call kvm_inject_page_fault. Ensure that they at least do not leak
5197 * uninitialized kernel stack memory into cr2 and error code.
5199 memset(exception, 0, sizeof(*exception));
5200 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5203 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5205 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5206 gva_t addr, void *val, unsigned int bytes,
5207 struct x86_exception *exception, bool system)
5209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5212 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5213 access |= PFERR_USER_MASK;
5215 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5218 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5219 unsigned long addr, void *val, unsigned int bytes)
5221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5222 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5224 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5227 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5228 struct kvm_vcpu *vcpu, u32 access,
5229 struct x86_exception *exception)
5232 int r = X86EMUL_CONTINUE;
5235 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5238 unsigned offset = addr & (PAGE_SIZE-1);
5239 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5242 if (gpa == UNMAPPED_GVA)
5243 return X86EMUL_PROPAGATE_FAULT;
5244 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5246 r = X86EMUL_IO_NEEDED;
5258 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5259 unsigned int bytes, struct x86_exception *exception,
5262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5263 u32 access = PFERR_WRITE_MASK;
5265 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5266 access |= PFERR_USER_MASK;
5268 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5272 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5273 unsigned int bytes, struct x86_exception *exception)
5275 /* kvm_write_guest_virt_system can pull in tons of pages. */
5276 vcpu->arch.l1tf_flush_l1d = true;
5278 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5279 PFERR_WRITE_MASK, exception);
5281 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5283 int handle_ud(struct kvm_vcpu *vcpu)
5285 int emul_type = EMULTYPE_TRAP_UD;
5286 enum emulation_result er;
5287 char sig[5]; /* ud2; .ascii "kvm" */
5288 struct x86_exception e;
5290 if (force_emulation_prefix &&
5291 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5292 sig, sizeof(sig), &e) == 0 &&
5293 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5294 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5298 er = kvm_emulate_instruction(vcpu, emul_type);
5299 if (er == EMULATE_USER_EXIT)
5301 if (er != EMULATE_DONE)
5302 kvm_queue_exception(vcpu, UD_VECTOR);
5305 EXPORT_SYMBOL_GPL(handle_ud);
5307 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5308 gpa_t gpa, bool write)
5310 /* For APIC access vmexit */
5311 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5314 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5315 trace_vcpu_match_mmio(gva, gpa, write, true);
5322 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5323 gpa_t *gpa, struct x86_exception *exception,
5326 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5327 | (write ? PFERR_WRITE_MASK : 0);
5330 * currently PKRU is only applied to ept enabled guest so
5331 * there is no pkey in EPT page table for L1 guest or EPT
5332 * shadow page table for L2 guest.
5334 if (vcpu_match_mmio_gva(vcpu, gva)
5335 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5336 vcpu->arch.access, 0, access)) {
5337 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5338 (gva & (PAGE_SIZE - 1));
5339 trace_vcpu_match_mmio(gva, *gpa, write, false);
5343 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5345 if (*gpa == UNMAPPED_GVA)
5348 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5351 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5352 const void *val, int bytes)
5356 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5359 kvm_page_track_write(vcpu, gpa, val, bytes);
5363 struct read_write_emulator_ops {
5364 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5366 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5367 void *val, int bytes);
5368 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5369 int bytes, void *val);
5370 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5371 void *val, int bytes);
5375 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5377 if (vcpu->mmio_read_completed) {
5378 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5379 vcpu->mmio_fragments[0].gpa, val);
5380 vcpu->mmio_read_completed = 0;
5387 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5388 void *val, int bytes)
5390 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5393 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5394 void *val, int bytes)
5396 return emulator_write_phys(vcpu, gpa, val, bytes);
5399 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5401 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5402 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5405 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5406 void *val, int bytes)
5408 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5409 return X86EMUL_IO_NEEDED;
5412 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5413 void *val, int bytes)
5415 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5417 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5418 return X86EMUL_CONTINUE;
5421 static const struct read_write_emulator_ops read_emultor = {
5422 .read_write_prepare = read_prepare,
5423 .read_write_emulate = read_emulate,
5424 .read_write_mmio = vcpu_mmio_read,
5425 .read_write_exit_mmio = read_exit_mmio,
5428 static const struct read_write_emulator_ops write_emultor = {
5429 .read_write_emulate = write_emulate,
5430 .read_write_mmio = write_mmio,
5431 .read_write_exit_mmio = write_exit_mmio,
5435 static int emulator_read_write_onepage(unsigned long addr, void *val,
5437 struct x86_exception *exception,
5438 struct kvm_vcpu *vcpu,
5439 const struct read_write_emulator_ops *ops)
5443 bool write = ops->write;
5444 struct kvm_mmio_fragment *frag;
5445 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5448 * If the exit was due to a NPF we may already have a GPA.
5449 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5450 * Note, this cannot be used on string operations since string
5451 * operation using rep will only have the initial GPA from the NPF
5454 if (vcpu->arch.gpa_available &&
5455 emulator_can_use_gpa(ctxt) &&
5456 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5457 gpa = vcpu->arch.gpa_val;
5458 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5460 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5462 return X86EMUL_PROPAGATE_FAULT;
5465 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5466 return X86EMUL_CONTINUE;
5469 * Is this MMIO handled locally?
5471 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5472 if (handled == bytes)
5473 return X86EMUL_CONTINUE;
5479 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5480 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5484 return X86EMUL_CONTINUE;
5487 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5489 void *val, unsigned int bytes,
5490 struct x86_exception *exception,
5491 const struct read_write_emulator_ops *ops)
5493 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5497 if (ops->read_write_prepare &&
5498 ops->read_write_prepare(vcpu, val, bytes))
5499 return X86EMUL_CONTINUE;
5501 vcpu->mmio_nr_fragments = 0;
5503 /* Crossing a page boundary? */
5504 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5507 now = -addr & ~PAGE_MASK;
5508 rc = emulator_read_write_onepage(addr, val, now, exception,
5511 if (rc != X86EMUL_CONTINUE)
5514 if (ctxt->mode != X86EMUL_MODE_PROT64)
5520 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5522 if (rc != X86EMUL_CONTINUE)
5525 if (!vcpu->mmio_nr_fragments)
5528 gpa = vcpu->mmio_fragments[0].gpa;
5530 vcpu->mmio_needed = 1;
5531 vcpu->mmio_cur_fragment = 0;
5533 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5534 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5535 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5536 vcpu->run->mmio.phys_addr = gpa;
5538 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5541 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5545 struct x86_exception *exception)
5547 return emulator_read_write(ctxt, addr, val, bytes,
5548 exception, &read_emultor);
5551 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5555 struct x86_exception *exception)
5557 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5558 exception, &write_emultor);
5561 #define CMPXCHG_TYPE(t, ptr, old, new) \
5562 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5564 #ifdef CONFIG_X86_64
5565 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5567 # define CMPXCHG64(ptr, old, new) \
5568 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5571 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5576 struct x86_exception *exception)
5578 struct kvm_host_map map;
5579 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5584 /* guests cmpxchg8b have to be emulated atomically */
5585 if (bytes > 8 || (bytes & (bytes - 1)))
5588 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5590 if (gpa == UNMAPPED_GVA ||
5591 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5594 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5597 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5600 kaddr = map.hva + offset_in_page(gpa);
5604 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5607 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5610 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5613 exchanged = CMPXCHG64(kaddr, old, new);
5619 kvm_vcpu_unmap(vcpu, &map, true);
5622 return X86EMUL_CMPXCHG_FAILED;
5624 kvm_page_track_write(vcpu, gpa, new, bytes);
5626 return X86EMUL_CONTINUE;
5629 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5631 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5634 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5638 for (i = 0; i < vcpu->arch.pio.count; i++) {
5639 if (vcpu->arch.pio.in)
5640 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5641 vcpu->arch.pio.size, pd);
5643 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5644 vcpu->arch.pio.port, vcpu->arch.pio.size,
5648 pd += vcpu->arch.pio.size;
5653 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5654 unsigned short port, void *val,
5655 unsigned int count, bool in)
5657 vcpu->arch.pio.port = port;
5658 vcpu->arch.pio.in = in;
5659 vcpu->arch.pio.count = count;
5660 vcpu->arch.pio.size = size;
5662 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5663 vcpu->arch.pio.count = 0;
5667 vcpu->run->exit_reason = KVM_EXIT_IO;
5668 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5669 vcpu->run->io.size = size;
5670 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5671 vcpu->run->io.count = count;
5672 vcpu->run->io.port = port;
5677 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5678 int size, unsigned short port, void *val,
5681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5684 if (vcpu->arch.pio.count)
5687 memset(vcpu->arch.pio_data, 0, size * count);
5689 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5692 memcpy(val, vcpu->arch.pio_data, size * count);
5693 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5694 vcpu->arch.pio.count = 0;
5701 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5702 int size, unsigned short port,
5703 const void *val, unsigned int count)
5705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5707 memcpy(vcpu->arch.pio_data, val, size * count);
5708 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5709 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5712 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5714 return kvm_x86_ops->get_segment_base(vcpu, seg);
5717 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5719 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5722 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5724 if (!need_emulate_wbinvd(vcpu))
5725 return X86EMUL_CONTINUE;
5727 if (kvm_x86_ops->has_wbinvd_exit()) {
5728 int cpu = get_cpu();
5730 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5731 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5732 wbinvd_ipi, NULL, 1);
5734 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5737 return X86EMUL_CONTINUE;
5740 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5742 kvm_emulate_wbinvd_noskip(vcpu);
5743 return kvm_skip_emulated_instruction(vcpu);
5745 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5749 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5751 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5754 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5755 unsigned long *dest)
5757 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5760 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5761 unsigned long value)
5764 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5767 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5769 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5772 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5774 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5775 unsigned long value;
5779 value = kvm_read_cr0(vcpu);
5782 value = vcpu->arch.cr2;
5785 value = kvm_read_cr3(vcpu);
5788 value = kvm_read_cr4(vcpu);
5791 value = kvm_get_cr8(vcpu);
5794 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5801 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5808 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5811 vcpu->arch.cr2 = val;
5814 res = kvm_set_cr3(vcpu, val);
5817 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5820 res = kvm_set_cr8(vcpu, val);
5823 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5830 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5832 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5835 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5837 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5840 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5842 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5845 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5847 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5850 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5852 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5855 static unsigned long emulator_get_cached_segment_base(
5856 struct x86_emulate_ctxt *ctxt, int seg)
5858 return get_segment_base(emul_to_vcpu(ctxt), seg);
5861 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5862 struct desc_struct *desc, u32 *base3,
5865 struct kvm_segment var;
5867 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5868 *selector = var.selector;
5871 memset(desc, 0, sizeof(*desc));
5879 set_desc_limit(desc, var.limit);
5880 set_desc_base(desc, (unsigned long)var.base);
5881 #ifdef CONFIG_X86_64
5883 *base3 = var.base >> 32;
5885 desc->type = var.type;
5887 desc->dpl = var.dpl;
5888 desc->p = var.present;
5889 desc->avl = var.avl;
5897 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5898 struct desc_struct *desc, u32 base3,
5901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5902 struct kvm_segment var;
5904 var.selector = selector;
5905 var.base = get_desc_base(desc);
5906 #ifdef CONFIG_X86_64
5907 var.base |= ((u64)base3) << 32;
5909 var.limit = get_desc_limit(desc);
5911 var.limit = (var.limit << 12) | 0xfff;
5912 var.type = desc->type;
5913 var.dpl = desc->dpl;
5918 var.avl = desc->avl;
5919 var.present = desc->p;
5920 var.unusable = !var.present;
5923 kvm_set_segment(vcpu, &var, seg);
5927 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5928 u32 msr_index, u64 *pdata)
5930 struct msr_data msr;
5933 msr.index = msr_index;
5934 msr.host_initiated = false;
5935 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5943 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5944 u32 msr_index, u64 data)
5946 struct msr_data msr;
5949 msr.index = msr_index;
5950 msr.host_initiated = false;
5951 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5954 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5958 return vcpu->arch.smbase;
5961 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5965 vcpu->arch.smbase = smbase;
5968 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5971 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5974 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5975 u32 pmc, u64 *pdata)
5977 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5980 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5982 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5985 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5986 struct x86_instruction_info *info,
5987 enum x86_intercept_stage stage)
5989 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5992 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5993 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5995 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5998 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6000 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6003 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6005 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6008 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6010 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6013 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6015 return emul_to_vcpu(ctxt)->arch.hflags;
6018 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6020 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6023 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6024 const char *smstate)
6026 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6029 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6031 kvm_smm_changed(emul_to_vcpu(ctxt));
6034 static const struct x86_emulate_ops emulate_ops = {
6035 .read_gpr = emulator_read_gpr,
6036 .write_gpr = emulator_write_gpr,
6037 .read_std = emulator_read_std,
6038 .write_std = emulator_write_std,
6039 .read_phys = kvm_read_guest_phys_system,
6040 .fetch = kvm_fetch_guest_virt,
6041 .read_emulated = emulator_read_emulated,
6042 .write_emulated = emulator_write_emulated,
6043 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6044 .invlpg = emulator_invlpg,
6045 .pio_in_emulated = emulator_pio_in_emulated,
6046 .pio_out_emulated = emulator_pio_out_emulated,
6047 .get_segment = emulator_get_segment,
6048 .set_segment = emulator_set_segment,
6049 .get_cached_segment_base = emulator_get_cached_segment_base,
6050 .get_gdt = emulator_get_gdt,
6051 .get_idt = emulator_get_idt,
6052 .set_gdt = emulator_set_gdt,
6053 .set_idt = emulator_set_idt,
6054 .get_cr = emulator_get_cr,
6055 .set_cr = emulator_set_cr,
6056 .cpl = emulator_get_cpl,
6057 .get_dr = emulator_get_dr,
6058 .set_dr = emulator_set_dr,
6059 .get_smbase = emulator_get_smbase,
6060 .set_smbase = emulator_set_smbase,
6061 .set_msr = emulator_set_msr,
6062 .get_msr = emulator_get_msr,
6063 .check_pmc = emulator_check_pmc,
6064 .read_pmc = emulator_read_pmc,
6065 .halt = emulator_halt,
6066 .wbinvd = emulator_wbinvd,
6067 .fix_hypercall = emulator_fix_hypercall,
6068 .intercept = emulator_intercept,
6069 .get_cpuid = emulator_get_cpuid,
6070 .set_nmi_mask = emulator_set_nmi_mask,
6071 .get_hflags = emulator_get_hflags,
6072 .set_hflags = emulator_set_hflags,
6073 .pre_leave_smm = emulator_pre_leave_smm,
6074 .post_leave_smm = emulator_post_leave_smm,
6077 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6079 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6081 * an sti; sti; sequence only disable interrupts for the first
6082 * instruction. So, if the last instruction, be it emulated or
6083 * not, left the system with the INT_STI flag enabled, it
6084 * means that the last instruction is an sti. We should not
6085 * leave the flag on in this case. The same goes for mov ss
6087 if (int_shadow & mask)
6089 if (unlikely(int_shadow || mask)) {
6090 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6092 kvm_make_request(KVM_REQ_EVENT, vcpu);
6096 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6098 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6099 if (ctxt->exception.vector == PF_VECTOR)
6100 return kvm_propagate_fault(vcpu, &ctxt->exception);
6102 if (ctxt->exception.error_code_valid)
6103 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6104 ctxt->exception.error_code);
6106 kvm_queue_exception(vcpu, ctxt->exception.vector);
6110 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6112 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6115 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6117 ctxt->eflags = kvm_get_rflags(vcpu);
6118 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6120 ctxt->eip = kvm_rip_read(vcpu);
6121 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6122 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6123 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6124 cs_db ? X86EMUL_MODE_PROT32 :
6125 X86EMUL_MODE_PROT16;
6126 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6127 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6128 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6130 init_decode_cache(ctxt);
6131 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6134 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6136 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6139 init_emulate_ctxt(vcpu);
6143 ctxt->_eip = ctxt->eip + inc_eip;
6144 ret = emulate_int_real(ctxt, irq);
6146 if (ret != X86EMUL_CONTINUE)
6147 return EMULATE_FAIL;
6149 ctxt->eip = ctxt->_eip;
6150 kvm_rip_write(vcpu, ctxt->eip);
6151 kvm_set_rflags(vcpu, ctxt->eflags);
6153 return EMULATE_DONE;
6155 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6157 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6159 int r = EMULATE_DONE;
6161 ++vcpu->stat.insn_emulation_fail;
6162 trace_kvm_emulate_insn_failed(vcpu);
6164 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6165 return EMULATE_FAIL;
6167 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6168 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6169 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6170 vcpu->run->internal.ndata = 0;
6171 r = EMULATE_USER_EXIT;
6174 kvm_queue_exception(vcpu, UD_VECTOR);
6179 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6180 bool write_fault_to_shadow_pgtable,
6186 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6189 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6192 if (!vcpu->arch.mmu->direct_map) {
6194 * Write permission should be allowed since only
6195 * write access need to be emulated.
6197 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6200 * If the mapping is invalid in guest, let cpu retry
6201 * it to generate fault.
6203 if (gpa == UNMAPPED_GVA)
6208 * Do not retry the unhandleable instruction if it faults on the
6209 * readonly host memory, otherwise it will goto a infinite loop:
6210 * retry instruction -> write #PF -> emulation fail -> retry
6211 * instruction -> ...
6213 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6216 * If the instruction failed on the error pfn, it can not be fixed,
6217 * report the error to userspace.
6219 if (is_error_noslot_pfn(pfn))
6222 kvm_release_pfn_clean(pfn);
6224 /* The instructions are well-emulated on direct mmu. */
6225 if (vcpu->arch.mmu->direct_map) {
6226 unsigned int indirect_shadow_pages;
6228 spin_lock(&vcpu->kvm->mmu_lock);
6229 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6230 spin_unlock(&vcpu->kvm->mmu_lock);
6232 if (indirect_shadow_pages)
6233 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6239 * if emulation was due to access to shadowed page table
6240 * and it failed try to unshadow page and re-enter the
6241 * guest to let CPU execute the instruction.
6243 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6246 * If the access faults on its page table, it can not
6247 * be fixed by unprotecting shadow page and it should
6248 * be reported to userspace.
6250 return !write_fault_to_shadow_pgtable;
6253 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6254 unsigned long cr2, int emulation_type)
6256 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6257 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6259 last_retry_eip = vcpu->arch.last_retry_eip;
6260 last_retry_addr = vcpu->arch.last_retry_addr;
6263 * If the emulation is caused by #PF and it is non-page_table
6264 * writing instruction, it means the VM-EXIT is caused by shadow
6265 * page protected, we can zap the shadow page and retry this
6266 * instruction directly.
6268 * Note: if the guest uses a non-page-table modifying instruction
6269 * on the PDE that points to the instruction, then we will unmap
6270 * the instruction and go to an infinite loop. So, we cache the
6271 * last retried eip and the last fault address, if we meet the eip
6272 * and the address again, we can break out of the potential infinite
6275 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6277 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6280 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6283 if (x86_page_table_writing_insn(ctxt))
6286 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6289 vcpu->arch.last_retry_eip = ctxt->eip;
6290 vcpu->arch.last_retry_addr = cr2;
6292 if (!vcpu->arch.mmu->direct_map)
6293 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6295 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6300 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6301 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6303 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6305 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6306 /* This is a good place to trace that we are exiting SMM. */
6307 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6309 /* Process a latched INIT or SMI, if any. */
6310 kvm_make_request(KVM_REQ_EVENT, vcpu);
6313 kvm_mmu_reset_context(vcpu);
6316 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6325 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6326 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6331 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6333 struct kvm_run *kvm_run = vcpu->run;
6335 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6336 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6337 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6338 kvm_run->debug.arch.exception = DB_VECTOR;
6339 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6340 *r = EMULATE_USER_EXIT;
6342 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6346 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6348 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6349 int r = EMULATE_DONE;
6351 kvm_x86_ops->skip_emulated_instruction(vcpu);
6354 * rflags is the old, "raw" value of the flags. The new value has
6355 * not been saved yet.
6357 * This is correct even for TF set by the guest, because "the
6358 * processor will not generate this exception after the instruction
6359 * that sets the TF flag".
6361 if (unlikely(rflags & X86_EFLAGS_TF))
6362 kvm_vcpu_do_singlestep(vcpu, &r);
6363 return r == EMULATE_DONE;
6365 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6367 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6369 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6370 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6371 struct kvm_run *kvm_run = vcpu->run;
6372 unsigned long eip = kvm_get_linear_rip(vcpu);
6373 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6374 vcpu->arch.guest_debug_dr7,
6378 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6379 kvm_run->debug.arch.pc = eip;
6380 kvm_run->debug.arch.exception = DB_VECTOR;
6381 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6382 *r = EMULATE_USER_EXIT;
6387 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6388 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6389 unsigned long eip = kvm_get_linear_rip(vcpu);
6390 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6395 vcpu->arch.dr6 &= ~15;
6396 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6397 kvm_queue_exception(vcpu, DB_VECTOR);
6406 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6408 switch (ctxt->opcode_len) {
6415 case 0xe6: /* OUT */
6419 case 0x6c: /* INS */
6421 case 0x6e: /* OUTS */
6428 case 0x33: /* RDPMC */
6437 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6444 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6445 bool writeback = true;
6446 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6448 vcpu->arch.l1tf_flush_l1d = true;
6451 * Clear write_fault_to_shadow_pgtable here to ensure it is
6454 vcpu->arch.write_fault_to_shadow_pgtable = false;
6455 kvm_clear_exception_queue(vcpu);
6457 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6458 init_emulate_ctxt(vcpu);
6461 * We will reenter on the same instruction since
6462 * we do not set complete_userspace_io. This does not
6463 * handle watchpoints yet, those would be handled in
6466 if (!(emulation_type & EMULTYPE_SKIP) &&
6467 kvm_vcpu_check_breakpoint(vcpu, &r))
6470 ctxt->interruptibility = 0;
6471 ctxt->have_exception = false;
6472 ctxt->exception.vector = -1;
6473 ctxt->perm_ok = false;
6475 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6477 r = x86_decode_insn(ctxt, insn, insn_len);
6479 trace_kvm_emulate_insn_start(vcpu);
6480 ++vcpu->stat.insn_emulation;
6481 if (r != EMULATION_OK) {
6482 if (emulation_type & EMULTYPE_TRAP_UD)
6483 return EMULATE_FAIL;
6484 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6486 return EMULATE_DONE;
6487 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6488 return EMULATE_DONE;
6489 if (emulation_type & EMULTYPE_SKIP)
6490 return EMULATE_FAIL;
6491 return handle_emulation_failure(vcpu, emulation_type);
6495 if ((emulation_type & EMULTYPE_VMWARE) &&
6496 !is_vmware_backdoor_opcode(ctxt))
6497 return EMULATE_FAIL;
6499 if (emulation_type & EMULTYPE_SKIP) {
6500 kvm_rip_write(vcpu, ctxt->_eip);
6501 if (ctxt->eflags & X86_EFLAGS_RF)
6502 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6503 return EMULATE_DONE;
6506 if (retry_instruction(ctxt, cr2, emulation_type))
6507 return EMULATE_DONE;
6509 /* this is needed for vmware backdoor interface to work since it
6510 changes registers values during IO operation */
6511 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6512 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6513 emulator_invalidate_register_cache(ctxt);
6517 /* Save the faulting GPA (cr2) in the address field */
6518 ctxt->exception.address = cr2;
6520 r = x86_emulate_insn(ctxt);
6522 if (r == EMULATION_INTERCEPTED)
6523 return EMULATE_DONE;
6525 if (r == EMULATION_FAILED) {
6526 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6528 return EMULATE_DONE;
6530 return handle_emulation_failure(vcpu, emulation_type);
6533 if (ctxt->have_exception) {
6535 if (inject_emulated_exception(vcpu))
6537 } else if (vcpu->arch.pio.count) {
6538 if (!vcpu->arch.pio.in) {
6539 /* FIXME: return into emulator if single-stepping. */
6540 vcpu->arch.pio.count = 0;
6543 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6545 r = EMULATE_USER_EXIT;
6546 } else if (vcpu->mmio_needed) {
6547 if (!vcpu->mmio_is_write)
6549 r = EMULATE_USER_EXIT;
6550 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6551 } else if (r == EMULATION_RESTART)
6557 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6558 toggle_interruptibility(vcpu, ctxt->interruptibility);
6559 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6560 kvm_rip_write(vcpu, ctxt->eip);
6561 if (r == EMULATE_DONE && ctxt->tf)
6562 kvm_vcpu_do_singlestep(vcpu, &r);
6563 if (!ctxt->have_exception ||
6564 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6565 __kvm_set_rflags(vcpu, ctxt->eflags);
6568 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6569 * do nothing, and it will be requested again as soon as
6570 * the shadow expires. But we still need to check here,
6571 * because POPF has no interrupt shadow.
6573 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6574 kvm_make_request(KVM_REQ_EVENT, vcpu);
6576 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6581 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6583 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6585 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6587 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6588 void *insn, int insn_len)
6590 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6592 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6594 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6596 vcpu->arch.pio.count = 0;
6600 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6602 vcpu->arch.pio.count = 0;
6604 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6607 return kvm_skip_emulated_instruction(vcpu);
6610 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6611 unsigned short port)
6613 unsigned long val = kvm_rax_read(vcpu);
6614 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6615 size, port, &val, 1);
6620 * Workaround userspace that relies on old KVM behavior of %rip being
6621 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6624 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6625 vcpu->arch.complete_userspace_io =
6626 complete_fast_pio_out_port_0x7e;
6627 kvm_skip_emulated_instruction(vcpu);
6629 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6630 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6635 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6639 /* We should only ever be called with arch.pio.count equal to 1 */
6640 BUG_ON(vcpu->arch.pio.count != 1);
6642 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6643 vcpu->arch.pio.count = 0;
6647 /* For size less than 4 we merge, else we zero extend */
6648 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6651 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6652 * the copy and tracing
6654 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6655 vcpu->arch.pio.port, &val, 1);
6656 kvm_rax_write(vcpu, val);
6658 return kvm_skip_emulated_instruction(vcpu);
6661 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6662 unsigned short port)
6667 /* For size less than 4 we merge, else we zero extend */
6668 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6670 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6673 kvm_rax_write(vcpu, val);
6677 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6678 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6683 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6688 ret = kvm_fast_pio_in(vcpu, size, port);
6690 ret = kvm_fast_pio_out(vcpu, size, port);
6691 return ret && kvm_skip_emulated_instruction(vcpu);
6693 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6695 static int kvmclock_cpu_down_prep(unsigned int cpu)
6697 __this_cpu_write(cpu_tsc_khz, 0);
6701 static void tsc_khz_changed(void *data)
6703 struct cpufreq_freqs *freq = data;
6704 unsigned long khz = 0;
6708 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6709 khz = cpufreq_quick_get(raw_smp_processor_id());
6712 __this_cpu_write(cpu_tsc_khz, khz);
6715 #ifdef CONFIG_X86_64
6716 static void kvm_hyperv_tsc_notifier(void)
6719 struct kvm_vcpu *vcpu;
6722 spin_lock(&kvm_lock);
6723 list_for_each_entry(kvm, &vm_list, vm_list)
6724 kvm_make_mclock_inprogress_request(kvm);
6726 hyperv_stop_tsc_emulation();
6728 /* TSC frequency always matches when on Hyper-V */
6729 for_each_present_cpu(cpu)
6730 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6731 kvm_max_guest_tsc_khz = tsc_khz;
6733 list_for_each_entry(kvm, &vm_list, vm_list) {
6734 struct kvm_arch *ka = &kvm->arch;
6736 spin_lock(&ka->pvclock_gtod_sync_lock);
6738 pvclock_update_vm_gtod_copy(kvm);
6740 kvm_for_each_vcpu(cpu, vcpu, kvm)
6741 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6743 kvm_for_each_vcpu(cpu, vcpu, kvm)
6744 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6746 spin_unlock(&ka->pvclock_gtod_sync_lock);
6748 spin_unlock(&kvm_lock);
6752 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6755 struct kvm_vcpu *vcpu;
6756 int i, send_ipi = 0;
6759 * We allow guests to temporarily run on slowing clocks,
6760 * provided we notify them after, or to run on accelerating
6761 * clocks, provided we notify them before. Thus time never
6764 * However, we have a problem. We can't atomically update
6765 * the frequency of a given CPU from this function; it is
6766 * merely a notifier, which can be called from any CPU.
6767 * Changing the TSC frequency at arbitrary points in time
6768 * requires a recomputation of local variables related to
6769 * the TSC for each VCPU. We must flag these local variables
6770 * to be updated and be sure the update takes place with the
6771 * new frequency before any guests proceed.
6773 * Unfortunately, the combination of hotplug CPU and frequency
6774 * change creates an intractable locking scenario; the order
6775 * of when these callouts happen is undefined with respect to
6776 * CPU hotplug, and they can race with each other. As such,
6777 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6778 * undefined; you can actually have a CPU frequency change take
6779 * place in between the computation of X and the setting of the
6780 * variable. To protect against this problem, all updates of
6781 * the per_cpu tsc_khz variable are done in an interrupt
6782 * protected IPI, and all callers wishing to update the value
6783 * must wait for a synchronous IPI to complete (which is trivial
6784 * if the caller is on the CPU already). This establishes the
6785 * necessary total order on variable updates.
6787 * Note that because a guest time update may take place
6788 * anytime after the setting of the VCPU's request bit, the
6789 * correct TSC value must be set before the request. However,
6790 * to ensure the update actually makes it to any guest which
6791 * starts running in hardware virtualization between the set
6792 * and the acquisition of the spinlock, we must also ping the
6793 * CPU after setting the request bit.
6797 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6799 spin_lock(&kvm_lock);
6800 list_for_each_entry(kvm, &vm_list, vm_list) {
6801 kvm_for_each_vcpu(i, vcpu, kvm) {
6802 if (vcpu->cpu != cpu)
6804 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6805 if (vcpu->cpu != smp_processor_id())
6809 spin_unlock(&kvm_lock);
6811 if (freq->old < freq->new && send_ipi) {
6813 * We upscale the frequency. Must make the guest
6814 * doesn't see old kvmclock values while running with
6815 * the new frequency, otherwise we risk the guest sees
6816 * time go backwards.
6818 * In case we update the frequency for another cpu
6819 * (which might be in guest context) send an interrupt
6820 * to kick the cpu out of guest context. Next time
6821 * guest context is entered kvmclock will be updated,
6822 * so the guest will not see stale values.
6824 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6828 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6831 struct cpufreq_freqs *freq = data;
6834 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6836 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6839 for_each_cpu(cpu, freq->policy->cpus)
6840 __kvmclock_cpufreq_notifier(freq, cpu);
6845 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6846 .notifier_call = kvmclock_cpufreq_notifier
6849 static int kvmclock_cpu_online(unsigned int cpu)
6851 tsc_khz_changed(NULL);
6855 static void kvm_timer_init(void)
6857 max_tsc_khz = tsc_khz;
6859 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6860 #ifdef CONFIG_CPU_FREQ
6861 struct cpufreq_policy policy;
6864 memset(&policy, 0, sizeof(policy));
6866 cpufreq_get_policy(&policy, cpu);
6867 if (policy.cpuinfo.max_freq)
6868 max_tsc_khz = policy.cpuinfo.max_freq;
6871 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6872 CPUFREQ_TRANSITION_NOTIFIER);
6874 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6876 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6877 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6880 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6881 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6883 int kvm_is_in_guest(void)
6885 return __this_cpu_read(current_vcpu) != NULL;
6888 static int kvm_is_user_mode(void)
6892 if (__this_cpu_read(current_vcpu))
6893 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6895 return user_mode != 0;
6898 static unsigned long kvm_get_guest_ip(void)
6900 unsigned long ip = 0;
6902 if (__this_cpu_read(current_vcpu))
6903 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6908 static void kvm_handle_intel_pt_intr(void)
6910 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6912 kvm_make_request(KVM_REQ_PMI, vcpu);
6913 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6914 (unsigned long *)&vcpu->arch.pmu.global_status);
6917 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6918 .is_in_guest = kvm_is_in_guest,
6919 .is_user_mode = kvm_is_user_mode,
6920 .get_guest_ip = kvm_get_guest_ip,
6921 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
6924 #ifdef CONFIG_X86_64
6925 static void pvclock_gtod_update_fn(struct work_struct *work)
6929 struct kvm_vcpu *vcpu;
6932 spin_lock(&kvm_lock);
6933 list_for_each_entry(kvm, &vm_list, vm_list)
6934 kvm_for_each_vcpu(i, vcpu, kvm)
6935 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6936 atomic_set(&kvm_guest_has_master_clock, 0);
6937 spin_unlock(&kvm_lock);
6940 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6943 * Notification about pvclock gtod data update.
6945 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6948 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6949 struct timekeeper *tk = priv;
6951 update_pvclock_gtod(tk);
6953 /* disable master clock if host does not trust, or does not
6954 * use, TSC based clocksource.
6956 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6957 atomic_read(&kvm_guest_has_master_clock) != 0)
6958 queue_work(system_long_wq, &pvclock_gtod_work);
6963 static struct notifier_block pvclock_gtod_notifier = {
6964 .notifier_call = pvclock_gtod_notify,
6968 int kvm_arch_init(void *opaque)
6971 struct kvm_x86_ops *ops = opaque;
6974 printk(KERN_ERR "kvm: already loaded the other module\n");
6979 if (!ops->cpu_has_kvm_support()) {
6980 printk(KERN_ERR "kvm: no hardware support\n");
6984 if (ops->disabled_by_bios()) {
6985 printk(KERN_ERR "kvm: disabled by bios\n");
6991 * KVM explicitly assumes that the guest has an FPU and
6992 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6993 * vCPU's FPU state as a fxregs_state struct.
6995 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6996 printk(KERN_ERR "kvm: inadequate fpu\n");
7002 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7003 __alignof__(struct fpu), SLAB_ACCOUNT,
7005 if (!x86_fpu_cache) {
7006 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7010 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7012 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7013 goto out_free_x86_fpu_cache;
7016 r = kvm_mmu_module_init();
7018 goto out_free_percpu;
7022 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7023 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7024 PT_PRESENT_MASK, 0, sme_me_mask);
7027 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7029 if (boot_cpu_has(X86_FEATURE_XSAVE))
7030 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7033 #ifdef CONFIG_X86_64
7034 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7036 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7037 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7043 free_percpu(shared_msrs);
7044 out_free_x86_fpu_cache:
7045 kmem_cache_destroy(x86_fpu_cache);
7050 void kvm_arch_exit(void)
7052 #ifdef CONFIG_X86_64
7053 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7054 clear_hv_tscchange_cb();
7057 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7059 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7060 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7061 CPUFREQ_TRANSITION_NOTIFIER);
7062 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7063 #ifdef CONFIG_X86_64
7064 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7067 kvm_mmu_module_exit();
7068 free_percpu(shared_msrs);
7069 kmem_cache_destroy(x86_fpu_cache);
7072 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7074 ++vcpu->stat.halt_exits;
7075 if (lapic_in_kernel(vcpu)) {
7076 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7079 vcpu->run->exit_reason = KVM_EXIT_HLT;
7083 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7085 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7087 int ret = kvm_skip_emulated_instruction(vcpu);
7089 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7090 * KVM_EXIT_DEBUG here.
7092 return kvm_vcpu_halt(vcpu) && ret;
7094 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7096 #ifdef CONFIG_X86_64
7097 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7098 unsigned long clock_type)
7100 struct kvm_clock_pairing clock_pairing;
7101 struct timespec64 ts;
7105 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7106 return -KVM_EOPNOTSUPP;
7108 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7109 return -KVM_EOPNOTSUPP;
7111 clock_pairing.sec = ts.tv_sec;
7112 clock_pairing.nsec = ts.tv_nsec;
7113 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7114 clock_pairing.flags = 0;
7115 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7118 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7119 sizeof(struct kvm_clock_pairing)))
7127 * kvm_pv_kick_cpu_op: Kick a vcpu.
7129 * @apicid - apicid of vcpu to be kicked.
7131 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7133 struct kvm_lapic_irq lapic_irq;
7135 lapic_irq.shorthand = 0;
7136 lapic_irq.dest_mode = 0;
7137 lapic_irq.level = 0;
7138 lapic_irq.dest_id = apicid;
7139 lapic_irq.msi_redir_hint = false;
7141 lapic_irq.delivery_mode = APIC_DM_REMRD;
7142 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7145 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7147 if (!lapic_in_kernel(vcpu)) {
7148 WARN_ON_ONCE(vcpu->arch.apicv_active);
7151 if (!vcpu->arch.apicv_active)
7154 vcpu->arch.apicv_active = false;
7155 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7158 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7160 unsigned long nr, a0, a1, a2, a3, ret;
7163 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7164 return kvm_hv_hypercall(vcpu);
7166 nr = kvm_rax_read(vcpu);
7167 a0 = kvm_rbx_read(vcpu);
7168 a1 = kvm_rcx_read(vcpu);
7169 a2 = kvm_rdx_read(vcpu);
7170 a3 = kvm_rsi_read(vcpu);
7172 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7174 op_64_bit = is_64_bit_mode(vcpu);
7183 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7189 case KVM_HC_VAPIC_POLL_IRQ:
7192 case KVM_HC_KICK_CPU:
7193 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7196 #ifdef CONFIG_X86_64
7197 case KVM_HC_CLOCK_PAIRING:
7198 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7201 case KVM_HC_SEND_IPI:
7202 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7211 kvm_rax_write(vcpu, ret);
7213 ++vcpu->stat.hypercalls;
7214 return kvm_skip_emulated_instruction(vcpu);
7216 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7218 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7221 char instruction[3];
7222 unsigned long rip = kvm_rip_read(vcpu);
7224 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7226 return emulator_write_emulated(ctxt, rip, instruction, 3,
7230 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7232 return vcpu->run->request_interrupt_window &&
7233 likely(!pic_in_kernel(vcpu->kvm));
7236 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7238 struct kvm_run *kvm_run = vcpu->run;
7240 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7241 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7242 kvm_run->cr8 = kvm_get_cr8(vcpu);
7243 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7244 kvm_run->ready_for_interrupt_injection =
7245 pic_in_kernel(vcpu->kvm) ||
7246 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7249 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7253 if (!kvm_x86_ops->update_cr8_intercept)
7256 if (!lapic_in_kernel(vcpu))
7259 if (vcpu->arch.apicv_active)
7262 if (!vcpu->arch.apic->vapic_addr)
7263 max_irr = kvm_lapic_find_highest_irr(vcpu);
7270 tpr = kvm_lapic_get_cr8(vcpu);
7272 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7275 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7279 /* try to reinject previous events if any */
7281 if (vcpu->arch.exception.injected)
7282 kvm_x86_ops->queue_exception(vcpu);
7284 * Do not inject an NMI or interrupt if there is a pending
7285 * exception. Exceptions and interrupts are recognized at
7286 * instruction boundaries, i.e. the start of an instruction.
7287 * Trap-like exceptions, e.g. #DB, have higher priority than
7288 * NMIs and interrupts, i.e. traps are recognized before an
7289 * NMI/interrupt that's pending on the same instruction.
7290 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7291 * priority, but are only generated (pended) during instruction
7292 * execution, i.e. a pending fault-like exception means the
7293 * fault occurred on the *previous* instruction and must be
7294 * serviced prior to recognizing any new events in order to
7295 * fully complete the previous instruction.
7297 else if (!vcpu->arch.exception.pending) {
7298 if (vcpu->arch.nmi_injected)
7299 kvm_x86_ops->set_nmi(vcpu);
7300 else if (vcpu->arch.interrupt.injected)
7301 kvm_x86_ops->set_irq(vcpu);
7305 * Call check_nested_events() even if we reinjected a previous event
7306 * in order for caller to determine if it should require immediate-exit
7307 * from L2 to L1 due to pending L1 events which require exit
7310 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7311 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7316 /* try to inject new event if pending */
7317 if (vcpu->arch.exception.pending) {
7318 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7319 vcpu->arch.exception.has_error_code,
7320 vcpu->arch.exception.error_code);
7322 WARN_ON_ONCE(vcpu->arch.exception.injected);
7323 vcpu->arch.exception.pending = false;
7324 vcpu->arch.exception.injected = true;
7326 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7327 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7330 if (vcpu->arch.exception.nr == DB_VECTOR) {
7332 * This code assumes that nSVM doesn't use
7333 * check_nested_events(). If it does, the
7334 * DR6/DR7 changes should happen before L1
7335 * gets a #VMEXIT for an intercepted #DB in
7336 * L2. (Under VMX, on the other hand, the
7337 * DR6/DR7 changes should not happen in the
7338 * event of a VM-exit to L1 for an intercepted
7341 kvm_deliver_exception_payload(vcpu);
7342 if (vcpu->arch.dr7 & DR7_GD) {
7343 vcpu->arch.dr7 &= ~DR7_GD;
7344 kvm_update_dr7(vcpu);
7348 kvm_x86_ops->queue_exception(vcpu);
7351 /* Don't consider new event if we re-injected an event */
7352 if (kvm_event_needs_reinjection(vcpu))
7355 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7356 kvm_x86_ops->smi_allowed(vcpu)) {
7357 vcpu->arch.smi_pending = false;
7358 ++vcpu->arch.smi_count;
7360 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7361 --vcpu->arch.nmi_pending;
7362 vcpu->arch.nmi_injected = true;
7363 kvm_x86_ops->set_nmi(vcpu);
7364 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7366 * Because interrupts can be injected asynchronously, we are
7367 * calling check_nested_events again here to avoid a race condition.
7368 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7369 * proposal and current concerns. Perhaps we should be setting
7370 * KVM_REQ_EVENT only on certain events and not unconditionally?
7372 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7373 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7377 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7378 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7380 kvm_x86_ops->set_irq(vcpu);
7387 static void process_nmi(struct kvm_vcpu *vcpu)
7392 * x86 is limited to one NMI running, and one NMI pending after it.
7393 * If an NMI is already in progress, limit further NMIs to just one.
7394 * Otherwise, allow two (and we'll inject the first one immediately).
7396 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7399 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7400 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7401 kvm_make_request(KVM_REQ_EVENT, vcpu);
7404 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7407 flags |= seg->g << 23;
7408 flags |= seg->db << 22;
7409 flags |= seg->l << 21;
7410 flags |= seg->avl << 20;
7411 flags |= seg->present << 15;
7412 flags |= seg->dpl << 13;
7413 flags |= seg->s << 12;
7414 flags |= seg->type << 8;
7418 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7420 struct kvm_segment seg;
7423 kvm_get_segment(vcpu, &seg, n);
7424 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7427 offset = 0x7f84 + n * 12;
7429 offset = 0x7f2c + (n - 3) * 12;
7431 put_smstate(u32, buf, offset + 8, seg.base);
7432 put_smstate(u32, buf, offset + 4, seg.limit);
7433 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7436 #ifdef CONFIG_X86_64
7437 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7439 struct kvm_segment seg;
7443 kvm_get_segment(vcpu, &seg, n);
7444 offset = 0x7e00 + n * 16;
7446 flags = enter_smm_get_segment_flags(&seg) >> 8;
7447 put_smstate(u16, buf, offset, seg.selector);
7448 put_smstate(u16, buf, offset + 2, flags);
7449 put_smstate(u32, buf, offset + 4, seg.limit);
7450 put_smstate(u64, buf, offset + 8, seg.base);
7454 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7457 struct kvm_segment seg;
7461 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7462 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7463 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7464 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7466 for (i = 0; i < 8; i++)
7467 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7469 kvm_get_dr(vcpu, 6, &val);
7470 put_smstate(u32, buf, 0x7fcc, (u32)val);
7471 kvm_get_dr(vcpu, 7, &val);
7472 put_smstate(u32, buf, 0x7fc8, (u32)val);
7474 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7475 put_smstate(u32, buf, 0x7fc4, seg.selector);
7476 put_smstate(u32, buf, 0x7f64, seg.base);
7477 put_smstate(u32, buf, 0x7f60, seg.limit);
7478 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7480 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7481 put_smstate(u32, buf, 0x7fc0, seg.selector);
7482 put_smstate(u32, buf, 0x7f80, seg.base);
7483 put_smstate(u32, buf, 0x7f7c, seg.limit);
7484 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7486 kvm_x86_ops->get_gdt(vcpu, &dt);
7487 put_smstate(u32, buf, 0x7f74, dt.address);
7488 put_smstate(u32, buf, 0x7f70, dt.size);
7490 kvm_x86_ops->get_idt(vcpu, &dt);
7491 put_smstate(u32, buf, 0x7f58, dt.address);
7492 put_smstate(u32, buf, 0x7f54, dt.size);
7494 for (i = 0; i < 6; i++)
7495 enter_smm_save_seg_32(vcpu, buf, i);
7497 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7500 put_smstate(u32, buf, 0x7efc, 0x00020000);
7501 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7504 #ifdef CONFIG_X86_64
7505 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7508 struct kvm_segment seg;
7512 for (i = 0; i < 16; i++)
7513 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7515 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7516 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7518 kvm_get_dr(vcpu, 6, &val);
7519 put_smstate(u64, buf, 0x7f68, val);
7520 kvm_get_dr(vcpu, 7, &val);
7521 put_smstate(u64, buf, 0x7f60, val);
7523 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7524 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7525 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7527 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7530 put_smstate(u32, buf, 0x7efc, 0x00020064);
7532 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7534 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7535 put_smstate(u16, buf, 0x7e90, seg.selector);
7536 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7537 put_smstate(u32, buf, 0x7e94, seg.limit);
7538 put_smstate(u64, buf, 0x7e98, seg.base);
7540 kvm_x86_ops->get_idt(vcpu, &dt);
7541 put_smstate(u32, buf, 0x7e84, dt.size);
7542 put_smstate(u64, buf, 0x7e88, dt.address);
7544 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7545 put_smstate(u16, buf, 0x7e70, seg.selector);
7546 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7547 put_smstate(u32, buf, 0x7e74, seg.limit);
7548 put_smstate(u64, buf, 0x7e78, seg.base);
7550 kvm_x86_ops->get_gdt(vcpu, &dt);
7551 put_smstate(u32, buf, 0x7e64, dt.size);
7552 put_smstate(u64, buf, 0x7e68, dt.address);
7554 for (i = 0; i < 6; i++)
7555 enter_smm_save_seg_64(vcpu, buf, i);
7559 static void enter_smm(struct kvm_vcpu *vcpu)
7561 struct kvm_segment cs, ds;
7566 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7567 memset(buf, 0, 512);
7568 #ifdef CONFIG_X86_64
7569 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7570 enter_smm_save_state_64(vcpu, buf);
7573 enter_smm_save_state_32(vcpu, buf);
7576 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7577 * vCPU state (e.g. leave guest mode) after we've saved the state into
7578 * the SMM state-save area.
7580 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7582 vcpu->arch.hflags |= HF_SMM_MASK;
7583 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7585 if (kvm_x86_ops->get_nmi_mask(vcpu))
7586 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7588 kvm_x86_ops->set_nmi_mask(vcpu, true);
7590 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7591 kvm_rip_write(vcpu, 0x8000);
7593 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7594 kvm_x86_ops->set_cr0(vcpu, cr0);
7595 vcpu->arch.cr0 = cr0;
7597 kvm_x86_ops->set_cr4(vcpu, 0);
7599 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7600 dt.address = dt.size = 0;
7601 kvm_x86_ops->set_idt(vcpu, &dt);
7603 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7605 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7606 cs.base = vcpu->arch.smbase;
7611 cs.limit = ds.limit = 0xffffffff;
7612 cs.type = ds.type = 0x3;
7613 cs.dpl = ds.dpl = 0;
7618 cs.avl = ds.avl = 0;
7619 cs.present = ds.present = 1;
7620 cs.unusable = ds.unusable = 0;
7621 cs.padding = ds.padding = 0;
7623 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7624 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7625 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7626 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7627 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7628 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7630 #ifdef CONFIG_X86_64
7631 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7632 kvm_x86_ops->set_efer(vcpu, 0);
7635 kvm_update_cpuid(vcpu);
7636 kvm_mmu_reset_context(vcpu);
7639 static void process_smi(struct kvm_vcpu *vcpu)
7641 vcpu->arch.smi_pending = true;
7642 kvm_make_request(KVM_REQ_EVENT, vcpu);
7645 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7647 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7650 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7652 if (!kvm_apic_present(vcpu))
7655 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7657 if (irqchip_split(vcpu->kvm))
7658 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7660 if (vcpu->arch.apicv_active)
7661 kvm_x86_ops->sync_pir_to_irr(vcpu);
7662 if (ioapic_in_kernel(vcpu->kvm))
7663 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7666 if (is_guest_mode(vcpu))
7667 vcpu->arch.load_eoi_exitmap_pending = true;
7669 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7672 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7674 u64 eoi_exit_bitmap[4];
7676 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7679 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7680 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7681 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7684 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7685 unsigned long start, unsigned long end,
7688 unsigned long apic_address;
7691 * The physical address of apic access page is stored in the VMCS.
7692 * Update it when it becomes invalid.
7694 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7695 if (start <= apic_address && apic_address < end)
7696 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7701 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7703 struct page *page = NULL;
7705 if (!lapic_in_kernel(vcpu))
7708 if (!kvm_x86_ops->set_apic_access_page_addr)
7711 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7712 if (is_error_page(page))
7714 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7717 * Do not pin apic access page in memory, the MMU notifier
7718 * will call us again if it is migrated or swapped out.
7722 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7724 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7726 smp_send_reschedule(vcpu->cpu);
7728 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7731 * Returns 1 to let vcpu_run() continue the guest execution loop without
7732 * exiting to the userspace. Otherwise, the value will be returned to the
7735 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7739 dm_request_for_irq_injection(vcpu) &&
7740 kvm_cpu_accept_dm_intr(vcpu);
7742 bool req_immediate_exit = false;
7744 if (kvm_request_pending(vcpu)) {
7745 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7746 kvm_x86_ops->get_vmcs12_pages(vcpu);
7747 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7748 kvm_mmu_unload(vcpu);
7749 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7750 __kvm_migrate_timers(vcpu);
7751 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7752 kvm_gen_update_masterclock(vcpu->kvm);
7753 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7754 kvm_gen_kvmclock_update(vcpu);
7755 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7756 r = kvm_guest_time_update(vcpu);
7760 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7761 kvm_mmu_sync_roots(vcpu);
7762 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7763 kvm_mmu_load_cr3(vcpu);
7764 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7765 kvm_vcpu_flush_tlb(vcpu, true);
7766 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7767 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7771 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7772 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7773 vcpu->mmio_needed = 0;
7777 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7778 /* Page is swapped out. Do synthetic halt */
7779 vcpu->arch.apf.halted = true;
7783 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7784 record_steal_time(vcpu);
7785 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7787 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7789 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7790 kvm_pmu_handle_event(vcpu);
7791 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7792 kvm_pmu_deliver_pmi(vcpu);
7793 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7794 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7795 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7796 vcpu->arch.ioapic_handled_vectors)) {
7797 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7798 vcpu->run->eoi.vector =
7799 vcpu->arch.pending_ioapic_eoi;
7804 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7805 vcpu_scan_ioapic(vcpu);
7806 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7807 vcpu_load_eoi_exitmap(vcpu);
7808 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7809 kvm_vcpu_reload_apic_access_page(vcpu);
7810 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7811 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7812 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7816 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7817 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7818 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7822 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7823 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7824 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7830 * KVM_REQ_HV_STIMER has to be processed after
7831 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7832 * depend on the guest clock being up-to-date
7834 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7835 kvm_hv_process_stimers(vcpu);
7838 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7839 ++vcpu->stat.req_event;
7840 kvm_apic_accept_events(vcpu);
7841 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7846 if (inject_pending_event(vcpu, req_int_win) != 0)
7847 req_immediate_exit = true;
7849 /* Enable SMI/NMI/IRQ window open exits if needed.
7851 * SMIs have three cases:
7852 * 1) They can be nested, and then there is nothing to
7853 * do here because RSM will cause a vmexit anyway.
7854 * 2) There is an ISA-specific reason why SMI cannot be
7855 * injected, and the moment when this changes can be
7857 * 3) Or the SMI can be pending because
7858 * inject_pending_event has completed the injection
7859 * of an IRQ or NMI from the previous vmexit, and
7860 * then we request an immediate exit to inject the
7863 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7864 if (!kvm_x86_ops->enable_smi_window(vcpu))
7865 req_immediate_exit = true;
7866 if (vcpu->arch.nmi_pending)
7867 kvm_x86_ops->enable_nmi_window(vcpu);
7868 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7869 kvm_x86_ops->enable_irq_window(vcpu);
7870 WARN_ON(vcpu->arch.exception.pending);
7873 if (kvm_lapic_enabled(vcpu)) {
7874 update_cr8_intercept(vcpu);
7875 kvm_lapic_sync_to_vapic(vcpu);
7879 r = kvm_mmu_reload(vcpu);
7881 goto cancel_injection;
7886 kvm_x86_ops->prepare_guest_switch(vcpu);
7889 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7890 * IPI are then delayed after guest entry, which ensures that they
7891 * result in virtual interrupt delivery.
7893 local_irq_disable();
7894 vcpu->mode = IN_GUEST_MODE;
7896 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7899 * 1) We should set ->mode before checking ->requests. Please see
7900 * the comment in kvm_vcpu_exiting_guest_mode().
7902 * 2) For APICv, we should set ->mode before checking PID.ON. This
7903 * pairs with the memory barrier implicit in pi_test_and_set_on
7904 * (see vmx_deliver_posted_interrupt).
7906 * 3) This also orders the write to mode from any reads to the page
7907 * tables done while the VCPU is running. Please see the comment
7908 * in kvm_flush_remote_tlbs.
7910 smp_mb__after_srcu_read_unlock();
7913 * This handles the case where a posted interrupt was
7914 * notified with kvm_vcpu_kick.
7916 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7917 kvm_x86_ops->sync_pir_to_irr(vcpu);
7919 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7920 || need_resched() || signal_pending(current)) {
7921 vcpu->mode = OUTSIDE_GUEST_MODE;
7925 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7927 goto cancel_injection;
7930 if (req_immediate_exit) {
7931 kvm_make_request(KVM_REQ_EVENT, vcpu);
7932 kvm_x86_ops->request_immediate_exit(vcpu);
7935 trace_kvm_entry(vcpu->vcpu_id);
7936 guest_enter_irqoff();
7938 fpregs_assert_state_consistent();
7939 if (test_thread_flag(TIF_NEED_FPU_LOAD))
7940 switch_fpu_return();
7942 if (unlikely(vcpu->arch.switch_db_regs)) {
7944 set_debugreg(vcpu->arch.eff_db[0], 0);
7945 set_debugreg(vcpu->arch.eff_db[1], 1);
7946 set_debugreg(vcpu->arch.eff_db[2], 2);
7947 set_debugreg(vcpu->arch.eff_db[3], 3);
7948 set_debugreg(vcpu->arch.dr6, 6);
7949 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7952 kvm_x86_ops->run(vcpu);
7955 * Do this here before restoring debug registers on the host. And
7956 * since we do this before handling the vmexit, a DR access vmexit
7957 * can (a) read the correct value of the debug registers, (b) set
7958 * KVM_DEBUGREG_WONT_EXIT again.
7960 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7961 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7962 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7963 kvm_update_dr0123(vcpu);
7964 kvm_update_dr6(vcpu);
7965 kvm_update_dr7(vcpu);
7966 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7970 * If the guest has used debug registers, at least dr7
7971 * will be disabled while returning to the host.
7972 * If we don't have active breakpoints in the host, we don't
7973 * care about the messed up debug address registers. But if
7974 * we have some of them active, restore the old state.
7976 if (hw_breakpoint_active())
7977 hw_breakpoint_restore();
7979 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7981 vcpu->mode = OUTSIDE_GUEST_MODE;
7984 kvm_before_interrupt(vcpu);
7985 kvm_x86_ops->handle_external_intr(vcpu);
7986 kvm_after_interrupt(vcpu);
7990 guest_exit_irqoff();
7991 if (lapic_in_kernel(vcpu)) {
7992 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
7993 if (delta != S64_MIN) {
7994 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
7995 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8002 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8005 * Profile KVM exit RIPs:
8007 if (unlikely(prof_on == KVM_PROFILING)) {
8008 unsigned long rip = kvm_rip_read(vcpu);
8009 profile_hit(KVM_PROFILING, (void *)rip);
8012 if (unlikely(vcpu->arch.tsc_always_catchup))
8013 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8015 if (vcpu->arch.apic_attention)
8016 kvm_lapic_sync_from_vapic(vcpu);
8018 vcpu->arch.gpa_available = false;
8019 r = kvm_x86_ops->handle_exit(vcpu);
8023 kvm_x86_ops->cancel_injection(vcpu);
8024 if (unlikely(vcpu->arch.apic_attention))
8025 kvm_lapic_sync_from_vapic(vcpu);
8030 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8032 if (!kvm_arch_vcpu_runnable(vcpu) &&
8033 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8034 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8035 kvm_vcpu_block(vcpu);
8036 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8038 if (kvm_x86_ops->post_block)
8039 kvm_x86_ops->post_block(vcpu);
8041 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8045 kvm_apic_accept_events(vcpu);
8046 switch(vcpu->arch.mp_state) {
8047 case KVM_MP_STATE_HALTED:
8048 vcpu->arch.pv.pv_unhalted = false;
8049 vcpu->arch.mp_state =
8050 KVM_MP_STATE_RUNNABLE;
8052 case KVM_MP_STATE_RUNNABLE:
8053 vcpu->arch.apf.halted = false;
8055 case KVM_MP_STATE_INIT_RECEIVED:
8064 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8066 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8067 kvm_x86_ops->check_nested_events(vcpu, false);
8069 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8070 !vcpu->arch.apf.halted);
8073 static int vcpu_run(struct kvm_vcpu *vcpu)
8076 struct kvm *kvm = vcpu->kvm;
8078 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8079 vcpu->arch.l1tf_flush_l1d = true;
8082 if (kvm_vcpu_running(vcpu)) {
8083 r = vcpu_enter_guest(vcpu);
8085 r = vcpu_block(kvm, vcpu);
8091 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8092 if (kvm_cpu_has_pending_timer(vcpu))
8093 kvm_inject_pending_timer_irqs(vcpu);
8095 if (dm_request_for_irq_injection(vcpu) &&
8096 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8098 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8099 ++vcpu->stat.request_irq_exits;
8103 kvm_check_async_pf_completion(vcpu);
8105 if (signal_pending(current)) {
8107 vcpu->run->exit_reason = KVM_EXIT_INTR;
8108 ++vcpu->stat.signal_exits;
8111 if (need_resched()) {
8112 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8114 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8118 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8123 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8126 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8127 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8128 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8129 if (r != EMULATE_DONE)
8134 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8136 BUG_ON(!vcpu->arch.pio.count);
8138 return complete_emulated_io(vcpu);
8142 * Implements the following, as a state machine:
8146 * for each mmio piece in the fragment
8154 * for each mmio piece in the fragment
8159 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8161 struct kvm_run *run = vcpu->run;
8162 struct kvm_mmio_fragment *frag;
8165 BUG_ON(!vcpu->mmio_needed);
8167 /* Complete previous fragment */
8168 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8169 len = min(8u, frag->len);
8170 if (!vcpu->mmio_is_write)
8171 memcpy(frag->data, run->mmio.data, len);
8173 if (frag->len <= 8) {
8174 /* Switch to the next fragment. */
8176 vcpu->mmio_cur_fragment++;
8178 /* Go forward to the next mmio piece. */
8184 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8185 vcpu->mmio_needed = 0;
8187 /* FIXME: return into emulator if single-stepping. */
8188 if (vcpu->mmio_is_write)
8190 vcpu->mmio_read_completed = 1;
8191 return complete_emulated_io(vcpu);
8194 run->exit_reason = KVM_EXIT_MMIO;
8195 run->mmio.phys_addr = frag->gpa;
8196 if (vcpu->mmio_is_write)
8197 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8198 run->mmio.len = min(8u, frag->len);
8199 run->mmio.is_write = vcpu->mmio_is_write;
8200 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8204 /* Swap (qemu) user FPU context for the guest FPU context. */
8205 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8209 copy_fpregs_to_fpstate(¤t->thread.fpu);
8210 /* PKRU is separately restored in kvm_x86_ops->run. */
8211 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8212 ~XFEATURE_MASK_PKRU);
8214 fpregs_mark_activate();
8220 /* When vcpu_run ends, restore user space FPU context. */
8221 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8225 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8226 copy_kernel_to_fpregs(¤t->thread.fpu.state);
8228 fpregs_mark_activate();
8231 ++vcpu->stat.fpu_reload;
8235 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8240 kvm_sigset_activate(vcpu);
8241 kvm_load_guest_fpu(vcpu);
8243 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8244 if (kvm_run->immediate_exit) {
8248 kvm_vcpu_block(vcpu);
8249 kvm_apic_accept_events(vcpu);
8250 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8252 if (signal_pending(current)) {
8254 vcpu->run->exit_reason = KVM_EXIT_INTR;
8255 ++vcpu->stat.signal_exits;
8260 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8265 if (vcpu->run->kvm_dirty_regs) {
8266 r = sync_regs(vcpu);
8271 /* re-sync apic's tpr */
8272 if (!lapic_in_kernel(vcpu)) {
8273 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8279 if (unlikely(vcpu->arch.complete_userspace_io)) {
8280 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8281 vcpu->arch.complete_userspace_io = NULL;
8286 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8288 if (kvm_run->immediate_exit)
8294 kvm_put_guest_fpu(vcpu);
8295 if (vcpu->run->kvm_valid_regs)
8297 post_kvm_run_save(vcpu);
8298 kvm_sigset_deactivate(vcpu);
8304 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8306 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8308 * We are here if userspace calls get_regs() in the middle of
8309 * instruction emulation. Registers state needs to be copied
8310 * back from emulation context to vcpu. Userspace shouldn't do
8311 * that usually, but some bad designed PV devices (vmware
8312 * backdoor interface) need this to work
8314 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8315 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8317 regs->rax = kvm_rax_read(vcpu);
8318 regs->rbx = kvm_rbx_read(vcpu);
8319 regs->rcx = kvm_rcx_read(vcpu);
8320 regs->rdx = kvm_rdx_read(vcpu);
8321 regs->rsi = kvm_rsi_read(vcpu);
8322 regs->rdi = kvm_rdi_read(vcpu);
8323 regs->rsp = kvm_rsp_read(vcpu);
8324 regs->rbp = kvm_rbp_read(vcpu);
8325 #ifdef CONFIG_X86_64
8326 regs->r8 = kvm_r8_read(vcpu);
8327 regs->r9 = kvm_r9_read(vcpu);
8328 regs->r10 = kvm_r10_read(vcpu);
8329 regs->r11 = kvm_r11_read(vcpu);
8330 regs->r12 = kvm_r12_read(vcpu);
8331 regs->r13 = kvm_r13_read(vcpu);
8332 regs->r14 = kvm_r14_read(vcpu);
8333 regs->r15 = kvm_r15_read(vcpu);
8336 regs->rip = kvm_rip_read(vcpu);
8337 regs->rflags = kvm_get_rflags(vcpu);
8340 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8343 __get_regs(vcpu, regs);
8348 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8350 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8351 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8353 kvm_rax_write(vcpu, regs->rax);
8354 kvm_rbx_write(vcpu, regs->rbx);
8355 kvm_rcx_write(vcpu, regs->rcx);
8356 kvm_rdx_write(vcpu, regs->rdx);
8357 kvm_rsi_write(vcpu, regs->rsi);
8358 kvm_rdi_write(vcpu, regs->rdi);
8359 kvm_rsp_write(vcpu, regs->rsp);
8360 kvm_rbp_write(vcpu, regs->rbp);
8361 #ifdef CONFIG_X86_64
8362 kvm_r8_write(vcpu, regs->r8);
8363 kvm_r9_write(vcpu, regs->r9);
8364 kvm_r10_write(vcpu, regs->r10);
8365 kvm_r11_write(vcpu, regs->r11);
8366 kvm_r12_write(vcpu, regs->r12);
8367 kvm_r13_write(vcpu, regs->r13);
8368 kvm_r14_write(vcpu, regs->r14);
8369 kvm_r15_write(vcpu, regs->r15);
8372 kvm_rip_write(vcpu, regs->rip);
8373 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8375 vcpu->arch.exception.pending = false;
8377 kvm_make_request(KVM_REQ_EVENT, vcpu);
8380 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8383 __set_regs(vcpu, regs);
8388 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8390 struct kvm_segment cs;
8392 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8396 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8398 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8402 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8403 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8404 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8405 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8406 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8407 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8409 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8410 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8412 kvm_x86_ops->get_idt(vcpu, &dt);
8413 sregs->idt.limit = dt.size;
8414 sregs->idt.base = dt.address;
8415 kvm_x86_ops->get_gdt(vcpu, &dt);
8416 sregs->gdt.limit = dt.size;
8417 sregs->gdt.base = dt.address;
8419 sregs->cr0 = kvm_read_cr0(vcpu);
8420 sregs->cr2 = vcpu->arch.cr2;
8421 sregs->cr3 = kvm_read_cr3(vcpu);
8422 sregs->cr4 = kvm_read_cr4(vcpu);
8423 sregs->cr8 = kvm_get_cr8(vcpu);
8424 sregs->efer = vcpu->arch.efer;
8425 sregs->apic_base = kvm_get_apic_base(vcpu);
8427 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8429 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8430 set_bit(vcpu->arch.interrupt.nr,
8431 (unsigned long *)sregs->interrupt_bitmap);
8434 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8435 struct kvm_sregs *sregs)
8438 __get_sregs(vcpu, sregs);
8443 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8444 struct kvm_mp_state *mp_state)
8448 kvm_apic_accept_events(vcpu);
8449 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8450 vcpu->arch.pv.pv_unhalted)
8451 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8453 mp_state->mp_state = vcpu->arch.mp_state;
8459 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8460 struct kvm_mp_state *mp_state)
8466 if (!lapic_in_kernel(vcpu) &&
8467 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8470 /* INITs are latched while in SMM */
8471 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8472 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8473 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8476 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8477 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8478 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8480 vcpu->arch.mp_state = mp_state->mp_state;
8481 kvm_make_request(KVM_REQ_EVENT, vcpu);
8489 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8490 int reason, bool has_error_code, u32 error_code)
8492 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8495 init_emulate_ctxt(vcpu);
8497 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8498 has_error_code, error_code);
8501 return EMULATE_FAIL;
8503 kvm_rip_write(vcpu, ctxt->eip);
8504 kvm_set_rflags(vcpu, ctxt->eflags);
8505 kvm_make_request(KVM_REQ_EVENT, vcpu);
8506 return EMULATE_DONE;
8508 EXPORT_SYMBOL_GPL(kvm_task_switch);
8510 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8512 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8513 (sregs->cr4 & X86_CR4_OSXSAVE))
8516 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8518 * When EFER.LME and CR0.PG are set, the processor is in
8519 * 64-bit mode (though maybe in a 32-bit code segment).
8520 * CR4.PAE and EFER.LMA must be set.
8522 if (!(sregs->cr4 & X86_CR4_PAE)
8523 || !(sregs->efer & EFER_LMA))
8527 * Not in 64-bit mode: EFER.LMA is clear and the code
8528 * segment cannot be 64-bit.
8530 if (sregs->efer & EFER_LMA || sregs->cs.l)
8537 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8539 struct msr_data apic_base_msr;
8540 int mmu_reset_needed = 0;
8541 int cpuid_update_needed = 0;
8542 int pending_vec, max_bits, idx;
8546 if (kvm_valid_sregs(vcpu, sregs))
8549 apic_base_msr.data = sregs->apic_base;
8550 apic_base_msr.host_initiated = true;
8551 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8554 dt.size = sregs->idt.limit;
8555 dt.address = sregs->idt.base;
8556 kvm_x86_ops->set_idt(vcpu, &dt);
8557 dt.size = sregs->gdt.limit;
8558 dt.address = sregs->gdt.base;
8559 kvm_x86_ops->set_gdt(vcpu, &dt);
8561 vcpu->arch.cr2 = sregs->cr2;
8562 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8563 vcpu->arch.cr3 = sregs->cr3;
8564 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8566 kvm_set_cr8(vcpu, sregs->cr8);
8568 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8569 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8571 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8572 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8573 vcpu->arch.cr0 = sregs->cr0;
8575 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8576 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8577 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8578 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8579 if (cpuid_update_needed)
8580 kvm_update_cpuid(vcpu);
8582 idx = srcu_read_lock(&vcpu->kvm->srcu);
8583 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
8584 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8585 mmu_reset_needed = 1;
8587 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8589 if (mmu_reset_needed)
8590 kvm_mmu_reset_context(vcpu);
8592 max_bits = KVM_NR_INTERRUPTS;
8593 pending_vec = find_first_bit(
8594 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8595 if (pending_vec < max_bits) {
8596 kvm_queue_interrupt(vcpu, pending_vec, false);
8597 pr_debug("Set back pending irq %d\n", pending_vec);
8600 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8601 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8602 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8603 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8604 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8605 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8607 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8608 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8610 update_cr8_intercept(vcpu);
8612 /* Older userspace won't unhalt the vcpu on reset. */
8613 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8614 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8616 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8618 kvm_make_request(KVM_REQ_EVENT, vcpu);
8625 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8626 struct kvm_sregs *sregs)
8631 ret = __set_sregs(vcpu, sregs);
8636 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8637 struct kvm_guest_debug *dbg)
8639 unsigned long rflags;
8644 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8646 if (vcpu->arch.exception.pending)
8648 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8649 kvm_queue_exception(vcpu, DB_VECTOR);
8651 kvm_queue_exception(vcpu, BP_VECTOR);
8655 * Read rflags as long as potentially injected trace flags are still
8658 rflags = kvm_get_rflags(vcpu);
8660 vcpu->guest_debug = dbg->control;
8661 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8662 vcpu->guest_debug = 0;
8664 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8665 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8666 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8667 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8669 for (i = 0; i < KVM_NR_DB_REGS; i++)
8670 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8672 kvm_update_dr7(vcpu);
8674 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8675 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8676 get_segment_base(vcpu, VCPU_SREG_CS);
8679 * Trigger an rflags update that will inject or remove the trace
8682 kvm_set_rflags(vcpu, rflags);
8684 kvm_x86_ops->update_bp_intercept(vcpu);
8694 * Translate a guest virtual address to a guest physical address.
8696 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8697 struct kvm_translation *tr)
8699 unsigned long vaddr = tr->linear_address;
8705 idx = srcu_read_lock(&vcpu->kvm->srcu);
8706 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8707 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8708 tr->physical_address = gpa;
8709 tr->valid = gpa != UNMAPPED_GVA;
8717 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8719 struct fxregs_state *fxsave;
8723 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8724 memcpy(fpu->fpr, fxsave->st_space, 128);
8725 fpu->fcw = fxsave->cwd;
8726 fpu->fsw = fxsave->swd;
8727 fpu->ftwx = fxsave->twd;
8728 fpu->last_opcode = fxsave->fop;
8729 fpu->last_ip = fxsave->rip;
8730 fpu->last_dp = fxsave->rdp;
8731 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8737 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8739 struct fxregs_state *fxsave;
8743 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8745 memcpy(fxsave->st_space, fpu->fpr, 128);
8746 fxsave->cwd = fpu->fcw;
8747 fxsave->swd = fpu->fsw;
8748 fxsave->twd = fpu->ftwx;
8749 fxsave->fop = fpu->last_opcode;
8750 fxsave->rip = fpu->last_ip;
8751 fxsave->rdp = fpu->last_dp;
8752 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8758 static void store_regs(struct kvm_vcpu *vcpu)
8760 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8762 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8763 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8765 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8766 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8768 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8769 kvm_vcpu_ioctl_x86_get_vcpu_events(
8770 vcpu, &vcpu->run->s.regs.events);
8773 static int sync_regs(struct kvm_vcpu *vcpu)
8775 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8778 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8779 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8780 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8782 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8783 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8785 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8787 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8788 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8789 vcpu, &vcpu->run->s.regs.events))
8791 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8797 static void fx_init(struct kvm_vcpu *vcpu)
8799 fpstate_init(&vcpu->arch.guest_fpu->state);
8800 if (boot_cpu_has(X86_FEATURE_XSAVES))
8801 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8802 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8805 * Ensure guest xcr0 is valid for loading
8807 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8809 vcpu->arch.cr0 |= X86_CR0_ET;
8812 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8814 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8816 kvmclock_reset(vcpu);
8818 kvm_x86_ops->vcpu_free(vcpu);
8819 free_cpumask_var(wbinvd_dirty_mask);
8822 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8825 struct kvm_vcpu *vcpu;
8827 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8828 printk_once(KERN_WARNING
8829 "kvm: SMP vm created on host with unstable TSC; "
8830 "guest TSC will not be reliable\n");
8832 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8837 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8839 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8840 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8841 kvm_vcpu_mtrr_init(vcpu);
8843 kvm_vcpu_reset(vcpu, false);
8844 kvm_init_mmu(vcpu, false);
8849 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8851 struct msr_data msr;
8852 struct kvm *kvm = vcpu->kvm;
8854 kvm_hv_vcpu_postcreate(vcpu);
8856 if (mutex_lock_killable(&vcpu->mutex))
8860 msr.index = MSR_IA32_TSC;
8861 msr.host_initiated = true;
8862 kvm_write_tsc(vcpu, &msr);
8864 mutex_unlock(&vcpu->mutex);
8866 if (!kvmclock_periodic_sync)
8869 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8870 KVMCLOCK_SYNC_PERIOD);
8873 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8875 vcpu->arch.apf.msr_val = 0;
8878 kvm_mmu_unload(vcpu);
8881 kvm_x86_ops->vcpu_free(vcpu);
8884 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8886 kvm_lapic_reset(vcpu, init_event);
8888 vcpu->arch.hflags = 0;
8890 vcpu->arch.smi_pending = 0;
8891 vcpu->arch.smi_count = 0;
8892 atomic_set(&vcpu->arch.nmi_queued, 0);
8893 vcpu->arch.nmi_pending = 0;
8894 vcpu->arch.nmi_injected = false;
8895 kvm_clear_interrupt_queue(vcpu);
8896 kvm_clear_exception_queue(vcpu);
8897 vcpu->arch.exception.pending = false;
8899 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8900 kvm_update_dr0123(vcpu);
8901 vcpu->arch.dr6 = DR6_INIT;
8902 kvm_update_dr6(vcpu);
8903 vcpu->arch.dr7 = DR7_FIXED_1;
8904 kvm_update_dr7(vcpu);
8908 kvm_make_request(KVM_REQ_EVENT, vcpu);
8909 vcpu->arch.apf.msr_val = 0;
8910 vcpu->arch.st.msr_val = 0;
8912 kvmclock_reset(vcpu);
8914 kvm_clear_async_pf_completion_queue(vcpu);
8915 kvm_async_pf_hash_reset(vcpu);
8916 vcpu->arch.apf.halted = false;
8918 if (kvm_mpx_supported()) {
8919 void *mpx_state_buffer;
8922 * To avoid have the INIT path from kvm_apic_has_events() that be
8923 * called with loaded FPU and does not let userspace fix the state.
8926 kvm_put_guest_fpu(vcpu);
8927 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8929 if (mpx_state_buffer)
8930 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8931 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8933 if (mpx_state_buffer)
8934 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8936 kvm_load_guest_fpu(vcpu);
8940 kvm_pmu_reset(vcpu);
8941 vcpu->arch.smbase = 0x30000;
8943 vcpu->arch.msr_misc_features_enables = 0;
8945 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8948 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8949 vcpu->arch.regs_avail = ~0;
8950 vcpu->arch.regs_dirty = ~0;
8952 vcpu->arch.ia32_xss = 0;
8954 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8957 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8959 struct kvm_segment cs;
8961 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8962 cs.selector = vector << 8;
8963 cs.base = vector << 12;
8964 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8965 kvm_rip_write(vcpu, 0);
8968 int kvm_arch_hardware_enable(void)
8971 struct kvm_vcpu *vcpu;
8976 bool stable, backwards_tsc = false;
8978 kvm_shared_msr_cpu_online();
8979 ret = kvm_x86_ops->hardware_enable();
8983 local_tsc = rdtsc();
8984 stable = !kvm_check_tsc_unstable();
8985 list_for_each_entry(kvm, &vm_list, vm_list) {
8986 kvm_for_each_vcpu(i, vcpu, kvm) {
8987 if (!stable && vcpu->cpu == smp_processor_id())
8988 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8989 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8990 backwards_tsc = true;
8991 if (vcpu->arch.last_host_tsc > max_tsc)
8992 max_tsc = vcpu->arch.last_host_tsc;
8998 * Sometimes, even reliable TSCs go backwards. This happens on
8999 * platforms that reset TSC during suspend or hibernate actions, but
9000 * maintain synchronization. We must compensate. Fortunately, we can
9001 * detect that condition here, which happens early in CPU bringup,
9002 * before any KVM threads can be running. Unfortunately, we can't
9003 * bring the TSCs fully up to date with real time, as we aren't yet far
9004 * enough into CPU bringup that we know how much real time has actually
9005 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
9006 * variables that haven't been updated yet.
9008 * So we simply find the maximum observed TSC above, then record the
9009 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9010 * the adjustment will be applied. Note that we accumulate
9011 * adjustments, in case multiple suspend cycles happen before some VCPU
9012 * gets a chance to run again. In the event that no KVM threads get a
9013 * chance to run, we will miss the entire elapsed period, as we'll have
9014 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9015 * loose cycle time. This isn't too big a deal, since the loss will be
9016 * uniform across all VCPUs (not to mention the scenario is extremely
9017 * unlikely). It is possible that a second hibernate recovery happens
9018 * much faster than a first, causing the observed TSC here to be
9019 * smaller; this would require additional padding adjustment, which is
9020 * why we set last_host_tsc to the local tsc observed here.
9022 * N.B. - this code below runs only on platforms with reliable TSC,
9023 * as that is the only way backwards_tsc is set above. Also note
9024 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9025 * have the same delta_cyc adjustment applied if backwards_tsc
9026 * is detected. Note further, this adjustment is only done once,
9027 * as we reset last_host_tsc on all VCPUs to stop this from being
9028 * called multiple times (one for each physical CPU bringup).
9030 * Platforms with unreliable TSCs don't have to deal with this, they
9031 * will be compensated by the logic in vcpu_load, which sets the TSC to
9032 * catchup mode. This will catchup all VCPUs to real time, but cannot
9033 * guarantee that they stay in perfect synchronization.
9035 if (backwards_tsc) {
9036 u64 delta_cyc = max_tsc - local_tsc;
9037 list_for_each_entry(kvm, &vm_list, vm_list) {
9038 kvm->arch.backwards_tsc_observed = true;
9039 kvm_for_each_vcpu(i, vcpu, kvm) {
9040 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9041 vcpu->arch.last_host_tsc = local_tsc;
9042 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9046 * We have to disable TSC offset matching.. if you were
9047 * booting a VM while issuing an S4 host suspend....
9048 * you may have some problem. Solving this issue is
9049 * left as an exercise to the reader.
9051 kvm->arch.last_tsc_nsec = 0;
9052 kvm->arch.last_tsc_write = 0;
9059 void kvm_arch_hardware_disable(void)
9061 kvm_x86_ops->hardware_disable();
9062 drop_user_return_notifiers();
9065 int kvm_arch_hardware_setup(void)
9069 r = kvm_x86_ops->hardware_setup();
9073 if (kvm_has_tsc_control) {
9075 * Make sure the user can only configure tsc_khz values that
9076 * fit into a signed integer.
9077 * A min value is not calculated because it will always
9078 * be 1 on all machines.
9080 u64 max = min(0x7fffffffULL,
9081 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9082 kvm_max_guest_tsc_khz = max;
9084 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9087 kvm_init_msr_list();
9091 void kvm_arch_hardware_unsetup(void)
9093 kvm_x86_ops->hardware_unsetup();
9096 int kvm_arch_check_processor_compat(void)
9098 return kvm_x86_ops->check_processor_compatibility();
9101 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9103 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9105 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9107 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9109 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9112 struct static_key kvm_no_apic_vcpu __read_mostly;
9113 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9115 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9120 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9121 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9122 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9124 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9126 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9131 vcpu->arch.pio_data = page_address(page);
9133 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9135 r = kvm_mmu_create(vcpu);
9137 goto fail_free_pio_data;
9139 if (irqchip_in_kernel(vcpu->kvm)) {
9140 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9141 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9143 goto fail_mmu_destroy;
9145 static_key_slow_inc(&kvm_no_apic_vcpu);
9147 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9148 GFP_KERNEL_ACCOUNT);
9149 if (!vcpu->arch.mce_banks) {
9151 goto fail_free_lapic;
9153 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9155 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9156 GFP_KERNEL_ACCOUNT)) {
9158 goto fail_free_mce_banks;
9163 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9165 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9167 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9169 kvm_async_pf_hash_reset(vcpu);
9172 vcpu->arch.pending_external_vector = -1;
9173 vcpu->arch.preempted_in_kernel = false;
9175 kvm_hv_vcpu_init(vcpu);
9179 fail_free_mce_banks:
9180 kfree(vcpu->arch.mce_banks);
9182 kvm_free_lapic(vcpu);
9184 kvm_mmu_destroy(vcpu);
9186 free_page((unsigned long)vcpu->arch.pio_data);
9191 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9195 kvm_hv_vcpu_uninit(vcpu);
9196 kvm_pmu_destroy(vcpu);
9197 kfree(vcpu->arch.mce_banks);
9198 kvm_free_lapic(vcpu);
9199 idx = srcu_read_lock(&vcpu->kvm->srcu);
9200 kvm_mmu_destroy(vcpu);
9201 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9202 free_page((unsigned long)vcpu->arch.pio_data);
9203 if (!lapic_in_kernel(vcpu))
9204 static_key_slow_dec(&kvm_no_apic_vcpu);
9207 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9209 vcpu->arch.l1tf_flush_l1d = true;
9210 kvm_x86_ops->sched_in(vcpu, cpu);
9213 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9218 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9219 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9220 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9221 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9223 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9224 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9225 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9226 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9227 &kvm->arch.irq_sources_bitmap);
9229 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9230 mutex_init(&kvm->arch.apic_map_lock);
9231 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9233 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
9234 pvclock_update_vm_gtod_copy(kvm);
9236 kvm->arch.guest_can_read_msr_platform_info = true;
9238 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9239 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9241 kvm_hv_init_vm(kvm);
9242 kvm_page_track_init(kvm);
9243 kvm_mmu_init_vm(kvm);
9245 if (kvm_x86_ops->vm_init)
9246 return kvm_x86_ops->vm_init(kvm);
9251 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9254 kvm_mmu_unload(vcpu);
9258 static void kvm_free_vcpus(struct kvm *kvm)
9261 struct kvm_vcpu *vcpu;
9264 * Unpin any mmu pages first.
9266 kvm_for_each_vcpu(i, vcpu, kvm) {
9267 kvm_clear_async_pf_completion_queue(vcpu);
9268 kvm_unload_vcpu_mmu(vcpu);
9270 kvm_for_each_vcpu(i, vcpu, kvm)
9271 kvm_arch_vcpu_free(vcpu);
9273 mutex_lock(&kvm->lock);
9274 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9275 kvm->vcpus[i] = NULL;
9277 atomic_set(&kvm->online_vcpus, 0);
9278 mutex_unlock(&kvm->lock);
9281 void kvm_arch_sync_events(struct kvm *kvm)
9283 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9284 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9288 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9292 struct kvm_memslots *slots = kvm_memslots(kvm);
9293 struct kvm_memory_slot *slot, old;
9295 /* Called with kvm->slots_lock held. */
9296 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9299 slot = id_to_memslot(slots, id);
9305 * MAP_SHARED to prevent internal slot pages from being moved
9308 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9309 MAP_SHARED | MAP_ANONYMOUS, 0);
9310 if (IS_ERR((void *)hva))
9311 return PTR_ERR((void *)hva);
9320 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9321 struct kvm_userspace_memory_region m;
9323 m.slot = id | (i << 16);
9325 m.guest_phys_addr = gpa;
9326 m.userspace_addr = hva;
9327 m.memory_size = size;
9328 r = __kvm_set_memory_region(kvm, &m);
9334 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9338 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9340 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9344 mutex_lock(&kvm->slots_lock);
9345 r = __x86_set_memory_region(kvm, id, gpa, size);
9346 mutex_unlock(&kvm->slots_lock);
9350 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9352 void kvm_arch_destroy_vm(struct kvm *kvm)
9354 if (current->mm == kvm->mm) {
9356 * Free memory regions allocated on behalf of userspace,
9357 * unless the the memory map has changed due to process exit
9360 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9361 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9362 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9364 if (kvm_x86_ops->vm_destroy)
9365 kvm_x86_ops->vm_destroy(kvm);
9366 kvm_pic_destroy(kvm);
9367 kvm_ioapic_destroy(kvm);
9368 kvm_free_vcpus(kvm);
9369 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9370 kvm_mmu_uninit_vm(kvm);
9371 kvm_page_track_cleanup(kvm);
9372 kvm_hv_destroy_vm(kvm);
9375 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9376 struct kvm_memory_slot *dont)
9380 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9381 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9382 kvfree(free->arch.rmap[i]);
9383 free->arch.rmap[i] = NULL;
9388 if (!dont || free->arch.lpage_info[i - 1] !=
9389 dont->arch.lpage_info[i - 1]) {
9390 kvfree(free->arch.lpage_info[i - 1]);
9391 free->arch.lpage_info[i - 1] = NULL;
9395 kvm_page_track_free_memslot(free, dont);
9398 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9399 unsigned long npages)
9403 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9404 struct kvm_lpage_info *linfo;
9409 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9410 slot->base_gfn, level) + 1;
9412 slot->arch.rmap[i] =
9413 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9414 GFP_KERNEL_ACCOUNT);
9415 if (!slot->arch.rmap[i])
9420 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9424 slot->arch.lpage_info[i - 1] = linfo;
9426 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9427 linfo[0].disallow_lpage = 1;
9428 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9429 linfo[lpages - 1].disallow_lpage = 1;
9430 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9432 * If the gfn and userspace address are not aligned wrt each
9433 * other, or if explicitly asked to, disable large page
9434 * support for this slot
9436 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9437 !kvm_largepages_enabled()) {
9440 for (j = 0; j < lpages; ++j)
9441 linfo[j].disallow_lpage = 1;
9445 if (kvm_page_track_create_memslot(slot, npages))
9451 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9452 kvfree(slot->arch.rmap[i]);
9453 slot->arch.rmap[i] = NULL;
9457 kvfree(slot->arch.lpage_info[i - 1]);
9458 slot->arch.lpage_info[i - 1] = NULL;
9463 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9466 * memslots->generation has been incremented.
9467 * mmio generation may have reached its maximum value.
9469 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9472 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9473 struct kvm_memory_slot *memslot,
9474 const struct kvm_userspace_memory_region *mem,
9475 enum kvm_mr_change change)
9480 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9481 struct kvm_memory_slot *new)
9483 /* Still write protect RO slot */
9484 if (new->flags & KVM_MEM_READONLY) {
9485 kvm_mmu_slot_remove_write_access(kvm, new);
9490 * Call kvm_x86_ops dirty logging hooks when they are valid.
9492 * kvm_x86_ops->slot_disable_log_dirty is called when:
9494 * - KVM_MR_CREATE with dirty logging is disabled
9495 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9497 * The reason is, in case of PML, we need to set D-bit for any slots
9498 * with dirty logging disabled in order to eliminate unnecessary GPA
9499 * logging in PML buffer (and potential PML buffer full VMEXT). This
9500 * guarantees leaving PML enabled during guest's lifetime won't have
9501 * any additional overhead from PML when guest is running with dirty
9502 * logging disabled for memory slots.
9504 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9505 * to dirty logging mode.
9507 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9509 * In case of write protect:
9511 * Write protect all pages for dirty logging.
9513 * All the sptes including the large sptes which point to this
9514 * slot are set to readonly. We can not create any new large
9515 * spte on this slot until the end of the logging.
9517 * See the comments in fast_page_fault().
9519 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9520 if (kvm_x86_ops->slot_enable_log_dirty)
9521 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9523 kvm_mmu_slot_remove_write_access(kvm, new);
9525 if (kvm_x86_ops->slot_disable_log_dirty)
9526 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9530 void kvm_arch_commit_memory_region(struct kvm *kvm,
9531 const struct kvm_userspace_memory_region *mem,
9532 const struct kvm_memory_slot *old,
9533 const struct kvm_memory_slot *new,
9534 enum kvm_mr_change change)
9536 if (!kvm->arch.n_requested_mmu_pages)
9537 kvm_mmu_change_mmu_pages(kvm,
9538 kvm_mmu_calculate_default_mmu_pages(kvm));
9541 * Dirty logging tracks sptes in 4k granularity, meaning that large
9542 * sptes have to be split. If live migration is successful, the guest
9543 * in the source machine will be destroyed and large sptes will be
9544 * created in the destination. However, if the guest continues to run
9545 * in the source machine (for example if live migration fails), small
9546 * sptes will remain around and cause bad performance.
9548 * Scan sptes if dirty logging has been stopped, dropping those
9549 * which can be collapsed into a single large-page spte. Later
9550 * page faults will create the large-page sptes.
9552 if ((change != KVM_MR_DELETE) &&
9553 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9554 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9555 kvm_mmu_zap_collapsible_sptes(kvm, new);
9558 * Set up write protection and/or dirty logging for the new slot.
9560 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9561 * been zapped so no dirty logging staff is needed for old slot. For
9562 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9563 * new and it's also covered when dealing with the new slot.
9565 * FIXME: const-ify all uses of struct kvm_memory_slot.
9567 if (change != KVM_MR_DELETE)
9568 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9571 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9573 kvm_mmu_zap_all(kvm);
9576 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9577 struct kvm_memory_slot *slot)
9579 kvm_page_track_flush_slot(kvm, slot);
9582 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9584 return (is_guest_mode(vcpu) &&
9585 kvm_x86_ops->guest_apic_has_interrupt &&
9586 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9589 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9591 if (!list_empty_careful(&vcpu->async_pf.done))
9594 if (kvm_apic_has_events(vcpu))
9597 if (vcpu->arch.pv.pv_unhalted)
9600 if (vcpu->arch.exception.pending)
9603 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9604 (vcpu->arch.nmi_pending &&
9605 kvm_x86_ops->nmi_allowed(vcpu)))
9608 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9609 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9612 if (kvm_arch_interrupt_allowed(vcpu) &&
9613 (kvm_cpu_has_interrupt(vcpu) ||
9614 kvm_guest_apic_has_interrupt(vcpu)))
9617 if (kvm_hv_has_stimer_pending(vcpu))
9623 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9625 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9628 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9630 return vcpu->arch.preempted_in_kernel;
9633 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9635 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9638 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9640 return kvm_x86_ops->interrupt_allowed(vcpu);
9643 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9645 if (is_64_bit_mode(vcpu))
9646 return kvm_rip_read(vcpu);
9647 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9648 kvm_rip_read(vcpu));
9650 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9652 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9654 return kvm_get_linear_rip(vcpu) == linear_rip;
9656 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9658 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9660 unsigned long rflags;
9662 rflags = kvm_x86_ops->get_rflags(vcpu);
9663 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9664 rflags &= ~X86_EFLAGS_TF;
9667 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9669 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9671 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9672 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9673 rflags |= X86_EFLAGS_TF;
9674 kvm_x86_ops->set_rflags(vcpu, rflags);
9677 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9679 __kvm_set_rflags(vcpu, rflags);
9680 kvm_make_request(KVM_REQ_EVENT, vcpu);
9682 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9684 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9688 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9692 r = kvm_mmu_reload(vcpu);
9696 if (!vcpu->arch.mmu->direct_map &&
9697 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9700 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9703 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9705 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9708 static inline u32 kvm_async_pf_next_probe(u32 key)
9710 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9713 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9715 u32 key = kvm_async_pf_hash_fn(gfn);
9717 while (vcpu->arch.apf.gfns[key] != ~0)
9718 key = kvm_async_pf_next_probe(key);
9720 vcpu->arch.apf.gfns[key] = gfn;
9723 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9726 u32 key = kvm_async_pf_hash_fn(gfn);
9728 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9729 (vcpu->arch.apf.gfns[key] != gfn &&
9730 vcpu->arch.apf.gfns[key] != ~0); i++)
9731 key = kvm_async_pf_next_probe(key);
9736 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9738 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9741 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9745 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9747 vcpu->arch.apf.gfns[i] = ~0;
9749 j = kvm_async_pf_next_probe(j);
9750 if (vcpu->arch.apf.gfns[j] == ~0)
9752 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9754 * k lies cyclically in ]i,j]
9756 * |....j i.k.| or |.k..j i...|
9758 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9759 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9764 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9767 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9771 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9774 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9778 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9779 struct kvm_async_pf *work)
9781 struct x86_exception fault;
9783 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9784 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9786 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9787 (vcpu->arch.apf.send_user_only &&
9788 kvm_x86_ops->get_cpl(vcpu) == 0))
9789 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9790 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9791 fault.vector = PF_VECTOR;
9792 fault.error_code_valid = true;
9793 fault.error_code = 0;
9794 fault.nested_page_fault = false;
9795 fault.address = work->arch.token;
9796 fault.async_page_fault = true;
9797 kvm_inject_page_fault(vcpu, &fault);
9801 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9802 struct kvm_async_pf *work)
9804 struct x86_exception fault;
9807 if (work->wakeup_all)
9808 work->arch.token = ~0; /* broadcast wakeup */
9810 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9811 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9813 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9814 !apf_get_user(vcpu, &val)) {
9815 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9816 vcpu->arch.exception.pending &&
9817 vcpu->arch.exception.nr == PF_VECTOR &&
9818 !apf_put_user(vcpu, 0)) {
9819 vcpu->arch.exception.injected = false;
9820 vcpu->arch.exception.pending = false;
9821 vcpu->arch.exception.nr = 0;
9822 vcpu->arch.exception.has_error_code = false;
9823 vcpu->arch.exception.error_code = 0;
9824 vcpu->arch.exception.has_payload = false;
9825 vcpu->arch.exception.payload = 0;
9826 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9827 fault.vector = PF_VECTOR;
9828 fault.error_code_valid = true;
9829 fault.error_code = 0;
9830 fault.nested_page_fault = false;
9831 fault.address = work->arch.token;
9832 fault.async_page_fault = true;
9833 kvm_inject_page_fault(vcpu, &fault);
9836 vcpu->arch.apf.halted = false;
9837 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9840 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9842 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9845 return kvm_can_do_async_pf(vcpu);
9848 void kvm_arch_start_assignment(struct kvm *kvm)
9850 atomic_inc(&kvm->arch.assigned_device_count);
9852 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9854 void kvm_arch_end_assignment(struct kvm *kvm)
9856 atomic_dec(&kvm->arch.assigned_device_count);
9858 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9860 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9862 return atomic_read(&kvm->arch.assigned_device_count);
9864 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9866 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9868 atomic_inc(&kvm->arch.noncoherent_dma_count);
9870 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9872 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9874 atomic_dec(&kvm->arch.noncoherent_dma_count);
9876 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9878 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9880 return atomic_read(&kvm->arch.noncoherent_dma_count);
9882 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9884 bool kvm_arch_has_irq_bypass(void)
9886 return kvm_x86_ops->update_pi_irte != NULL;
9889 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9890 struct irq_bypass_producer *prod)
9892 struct kvm_kernel_irqfd *irqfd =
9893 container_of(cons, struct kvm_kernel_irqfd, consumer);
9895 irqfd->producer = prod;
9897 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9898 prod->irq, irqfd->gsi, 1);
9901 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9902 struct irq_bypass_producer *prod)
9905 struct kvm_kernel_irqfd *irqfd =
9906 container_of(cons, struct kvm_kernel_irqfd, consumer);
9908 WARN_ON(irqfd->producer != prod);
9909 irqfd->producer = NULL;
9912 * When producer of consumer is unregistered, we change back to
9913 * remapped mode, so we can re-use the current implementation
9914 * when the irq is masked/disabled or the consumer side (KVM
9915 * int this case doesn't want to receive the interrupts.
9917 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9919 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9920 " fails: %d\n", irqfd->consumer.token, ret);
9923 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9924 uint32_t guest_irq, bool set)
9926 if (!kvm_x86_ops->update_pi_irte)
9929 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9932 bool kvm_vector_hashing_enabled(void)
9934 return vector_hashing;
9936 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9938 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9939 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9940 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9941 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9942 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9943 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9944 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9945 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9946 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9947 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9948 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9949 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9950 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9951 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9952 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9953 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9954 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9955 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9956 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);