arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "mmu.h"
  22 #include "i8254.h"
  23 #include "tss.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28 #include "hyperv.h"
  29 #include "lapic.h"
  30
  31 #include <linux/clocksource.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/kvm.h>
  34 #include <linux/fs.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/export.h>
  37 #include <linux/moduleparam.h>
  38 #include <linux/mman.h>
  39 #include <linux/highmem.h>
  40 #include <linux/iommu.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/cpufreq.h>
  43 #include <linux/user-return-notifier.h>
  44 #include <linux/srcu.h>
  45 #include <linux/slab.h>
  46 #include <linux/perf_event.h>
  47 #include <linux/uaccess.h>
  48 #include <linux/hash.h>
  49 #include <linux/pci.h>
  50 #include <linux/timekeeper_internal.h>
  51 #include <linux/pvclock_gtod.h>
  52 #include <linux/kvm_irqfd.h>
  53 #include <linux/irqbypass.h>
  54 #include <linux/sched/stat.h>
  55 #include <linux/sched/isolation.h>
  56 #include <linux/mem_encrypt.h>
  57
  58 #include <trace/events/kvm.h>
  59
  60 #include <asm/debugreg.h>
  61 #include <asm/msr.h>
  62 #include <asm/desc.h>
  63 #include <asm/mce.h>
  64 #include <linux/kernel_stat.h>
  65 #include <asm/fpu/internal.h> /* Ugh! */
  66 #include <asm/pvclock.h>
  67 #include <asm/div64.h>
  68 #include <asm/irq_remapping.h>
  69 #include <asm/mshyperv.h>
  70 #include <asm/hypervisor.h>
  71 #include <asm/intel_pt.h>
  72 #include <asm/emulate_prefix.h>
  73 #include <clocksource/hyperv_timer.h>
  74
  75 #define CREATE_TRACE_POINTS
  76 #include "trace.h"
  77
  78 #define MAX_IO_MSRS 256
  79 #define KVM_MAX_MCE_BANKS 32
  80 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  81 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  82
  83 #define emul_to_vcpu(ctxt) \
  84         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
  85
  86 /* EFER defaults:
  87  * - enable syscall per default because its emulated by KVM
  88  * - enable LME and LMA per default on 64 bit KVM
  89  */
  90 #ifdef CONFIG_X86_64
  91 static
  92 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  93 #else
  94 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  95 #endif
  96
  97 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
  98
  99 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
 100 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
 101
 102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 103                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 104
 105 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 106 static void process_nmi(struct kvm_vcpu *vcpu);
 107 static void enter_smm(struct kvm_vcpu *vcpu);
 108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 109 static void store_regs(struct kvm_vcpu *vcpu);
 110 static int sync_regs(struct kvm_vcpu *vcpu);
 111
 112 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
 113 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 114
 115 static bool __read_mostly ignore_msrs = 0;
 116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 117
 118 static bool __read_mostly report_ignored_msrs = true;
 119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 120
 121 unsigned int min_timer_period_us = 200;
 122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 123
 124 static bool __read_mostly kvmclock_periodic_sync = true;
 125 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 126
 127 bool __read_mostly kvm_has_tsc_control;
 128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 129 u32  __read_mostly kvm_max_guest_tsc_khz;
 130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 131 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 133 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 135 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 137
 138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 139 static u32 __read_mostly tsc_tolerance_ppm = 250;
 140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 141
 142 /*
 143  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 144  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 145  * advancement entirely.  Any other value is used as-is and disables adaptive
 146  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 147  */
 148 static int __read_mostly lapic_timer_advance_ns = -1;
 149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 150
 151 static bool __read_mostly vector_hashing = true;
 152 module_param(vector_hashing, bool, S_IRUGO);
 153
 154 bool __read_mostly enable_vmware_backdoor = false;
 155 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 157
 158 static bool __read_mostly force_emulation_prefix = false;
 159 module_param(force_emulation_prefix, bool, S_IRUGO);
 160
 161 int __read_mostly pi_inject_timer = -1;
 162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 163
 164 #define KVM_NR_SHARED_MSRS 16
 165
 166 struct kvm_shared_msrs_global {
 167         int nr;
 168         u32 msrs[KVM_NR_SHARED_MSRS];
 169 };
 170
 171 struct kvm_shared_msrs {
 172         struct user_return_notifier urn;
 173         bool registered;
 174         struct kvm_shared_msr_values {
 175                 u64 host;
 176                 u64 curr;
 177         } values[KVM_NR_SHARED_MSRS];
 178 };
 179
 180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 181 static struct kvm_shared_msrs __percpu *shared_msrs;
 182
 183 static u64 __read_mostly host_xss;
 184
 185 struct kvm_stats_debugfs_item debugfs_entries[] = {
 186         { "pf_fixed", VCPU_STAT(pf_fixed) },
 187         { "pf_guest", VCPU_STAT(pf_guest) },
 188         { "tlb_flush", VCPU_STAT(tlb_flush) },
 189         { "invlpg", VCPU_STAT(invlpg) },
 190         { "exits", VCPU_STAT(exits) },
 191         { "io_exits", VCPU_STAT(io_exits) },
 192         { "mmio_exits", VCPU_STAT(mmio_exits) },
 193         { "signal_exits", VCPU_STAT(signal_exits) },
 194         { "irq_window", VCPU_STAT(irq_window_exits) },
 195         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 196         { "halt_exits", VCPU_STAT(halt_exits) },
 197         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
 198         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
 199         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
 200         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 201         { "hypercalls", VCPU_STAT(hypercalls) },
 202         { "request_irq", VCPU_STAT(request_irq_exits) },
 203         { "irq_exits", VCPU_STAT(irq_exits) },
 204         { "host_state_reload", VCPU_STAT(host_state_reload) },
 205         { "fpu_reload", VCPU_STAT(fpu_reload) },
 206         { "insn_emulation", VCPU_STAT(insn_emulation) },
 207         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 208         { "irq_injections", VCPU_STAT(irq_injections) },
 209         { "nmi_injections", VCPU_STAT(nmi_injections) },
 210         { "req_event", VCPU_STAT(req_event) },
 211         { "l1d_flush", VCPU_STAT(l1d_flush) },
 212         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 213         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 214         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 215         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 216         { "mmu_flooded", VM_STAT(mmu_flooded) },
 217         { "mmu_recycled", VM_STAT(mmu_recycled) },
 218         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 219         { "mmu_unsync", VM_STAT(mmu_unsync) },
 220         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 221         { "largepages", VM_STAT(lpages, .mode = 0444) },
 222         { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
 223         { "max_mmu_page_hash_collisions",
 224                 VM_STAT(max_mmu_page_hash_collisions) },
 225         { NULL }
 226 };
 227
 228 u64 __read_mostly host_xcr0;
 229
 230 struct kmem_cache *x86_fpu_cache;
 231 EXPORT_SYMBOL_GPL(x86_fpu_cache);
 232
 233 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 234
 235 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 236 {
 237         int i;
 238         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 239                 vcpu->arch.apf.gfns[i] = ~0;
 240 }
 241
 242 static void kvm_on_user_return(struct user_return_notifier *urn)
 243 {
 244         unsigned slot;
 245         struct kvm_shared_msrs *locals
 246                 = container_of(urn, struct kvm_shared_msrs, urn);
 247         struct kvm_shared_msr_values *values;
 248         unsigned long flags;
 249
 250         /*
 251          * Disabling irqs at this point since the following code could be
 252          * interrupted and executed through kvm_arch_hardware_disable()
 253          */
 254         local_irq_save(flags);
 255         if (locals->registered) {
 256                 locals->registered = false;
 257                 user_return_notifier_unregister(urn);
 258         }
 259         local_irq_restore(flags);
 260         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 261                 values = &locals->values[slot];
 262                 if (values->host != values->curr) {
 263                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 264                         values->curr = values->host;
 265                 }
 266         }
 267 }
 268
 269 void kvm_define_shared_msr(unsigned slot, u32 msr)
 270 {
 271         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 272         shared_msrs_global.msrs[slot] = msr;
 273         if (slot >= shared_msrs_global.nr)
 274                 shared_msrs_global.nr = slot + 1;
 275 }
 276 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 277
 278 static void kvm_shared_msr_cpu_online(void)
 279 {
 280         unsigned int cpu = smp_processor_id();
 281         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 282         u64 value;
 283         int i;
 284
 285         for (i = 0; i < shared_msrs_global.nr; ++i) {
 286                 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
 287                 smsr->values[i].host = value;
 288                 smsr->values[i].curr = value;
 289         }
 290 }
 291
 292 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 293 {
 294         unsigned int cpu = smp_processor_id();
 295         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 296         int err;
 297
 298         value = (value & mask) | (smsr->values[slot].host & ~mask);
 299         if (value == smsr->values[slot].curr)
 300                 return 0;
 301         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 302         if (err)
 303                 return 1;
 304
 305         smsr->values[slot].curr = value;
 306         if (!smsr->registered) {
 307                 smsr->urn.on_user_return = kvm_on_user_return;
 308                 user_return_notifier_register(&smsr->urn);
 309                 smsr->registered = true;
 310         }
 311         return 0;
 312 }
 313 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 314
 315 static void drop_user_return_notifiers(void)
 316 {
 317         unsigned int cpu = smp_processor_id();
 318         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 319
 320         if (smsr->registered)
 321                 kvm_on_user_return(&smsr->urn);
 322 }
 323
 324 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 325 {
 326         return vcpu->arch.apic_base;
 327 }
 328 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 329
 330 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 331 {
 332         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 333 }
 334 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 335
 336 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 337 {
 338         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 339         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 340         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 341                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 342
 343         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 344                 return 1;
 345         if (!msr_info->host_initiated) {
 346                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 347                         return 1;
 348                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 349                         return 1;
 350         }
 351
 352         kvm_lapic_set_base(vcpu, msr_info->data);
 353         return 0;
 354 }
 355 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 356
 357 asmlinkage __visible void kvm_spurious_fault(void)
 358 {
 359         /* Fault while not rebooting.  We want the trace. */
 360         BUG_ON(!kvm_rebooting);
 361 }
 362 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 363
 364 #define EXCPT_BENIGN            0
 365 #define EXCPT_CONTRIBUTORY      1
 366 #define EXCPT_PF                2
 367
 368 static int exception_class(int vector)
 369 {
 370         switch (vector) {
 371         case PF_VECTOR:
 372                 return EXCPT_PF;
 373         case DE_VECTOR:
 374         case TS_VECTOR:
 375         case NP_VECTOR:
 376         case SS_VECTOR:
 377         case GP_VECTOR:
 378                 return EXCPT_CONTRIBUTORY;
 379         default:
 380                 break;
 381         }
 382         return EXCPT_BENIGN;
 383 }
 384
 385 #define EXCPT_FAULT             0
 386 #define EXCPT_TRAP              1
 387 #define EXCPT_ABORT             2
 388 #define EXCPT_INTERRUPT         3
 389
 390 static int exception_type(int vector)
 391 {
 392         unsigned int mask;
 393
 394         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 395                 return EXCPT_INTERRUPT;
 396
 397         mask = 1 << vector;
 398
 399         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 400         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 401                 return EXCPT_TRAP;
 402
 403         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 404                 return EXCPT_ABORT;
 405
 406         /* Reserved exceptions will result in fault */
 407         return EXCPT_FAULT;
 408 }
 409
 410 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 411 {
 412         unsigned nr = vcpu->arch.exception.nr;
 413         bool has_payload = vcpu->arch.exception.has_payload;
 414         unsigned long payload = vcpu->arch.exception.payload;
 415
 416         if (!has_payload)
 417                 return;
 418
 419         switch (nr) {
 420         case DB_VECTOR:
 421                 /*
 422                  * "Certain debug exceptions may clear bit 0-3.  The
 423                  * remaining contents of the DR6 register are never
 424                  * cleared by the processor".
 425                  */
 426                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 427                 /*
 428                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 429                  */
 430                 vcpu->arch.dr6 |= DR6_RTM;
 431                 vcpu->arch.dr6 |= payload;
 432                 /*
 433                  * Bit 16 should be set in the payload whenever the #DB
 434                  * exception should clear DR6.RTM. This makes the payload
 435                  * compatible with the pending debug exceptions under VMX.
 436                  * Though not currently documented in the SDM, this also
 437                  * makes the payload compatible with the exit qualification
 438                  * for #DB exceptions under VMX.
 439                  */
 440                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 441
 442                 /*
 443                  * The #DB payload is defined as compatible with the 'pending
 444                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 445                  * defined in the 'pending debug exceptions' field (enabled
 446                  * breakpoint), it is reserved and must be zero in DR6.
 447                  */
 448                 vcpu->arch.dr6 &= ~BIT(12);
 449                 break;
 450         case PF_VECTOR:
 451                 vcpu->arch.cr2 = payload;
 452                 break;
 453         }
 454
 455         vcpu->arch.exception.has_payload = false;
 456         vcpu->arch.exception.payload = 0;
 457 }
 458 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 459
 460 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 461                 unsigned nr, bool has_error, u32 error_code,
 462                 bool has_payload, unsigned long payload, bool reinject)
 463 {
 464         u32 prev_nr;
 465         int class1, class2;
 466
 467         kvm_make_request(KVM_REQ_EVENT, vcpu);
 468
 469         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 470         queue:
 471                 if (has_error && !is_protmode(vcpu))
 472                         has_error = false;
 473                 if (reinject) {
 474                         /*
 475                          * On vmentry, vcpu->arch.exception.pending is only
 476                          * true if an event injection was blocked by
 477                          * nested_run_pending.  In that case, however,
 478                          * vcpu_enter_guest requests an immediate exit,
 479                          * and the guest shouldn't proceed far enough to
 480                          * need reinjection.
 481                          */
 482                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 483                         vcpu->arch.exception.injected = true;
 484                         if (WARN_ON_ONCE(has_payload)) {
 485                                 /*
 486                                  * A reinjected event has already
 487                                  * delivered its payload.
 488                                  */
 489                                 has_payload = false;
 490                                 payload = 0;
 491                         }
 492                 } else {
 493                         vcpu->arch.exception.pending = true;
 494                         vcpu->arch.exception.injected = false;
 495                 }
 496                 vcpu->arch.exception.has_error_code = has_error;
 497                 vcpu->arch.exception.nr = nr;
 498                 vcpu->arch.exception.error_code = error_code;
 499                 vcpu->arch.exception.has_payload = has_payload;
 500                 vcpu->arch.exception.payload = payload;
 501                 if (!is_guest_mode(vcpu))
 502                         kvm_deliver_exception_payload(vcpu);
 503                 return;
 504         }
 505
 506         /* to check exception */
 507         prev_nr = vcpu->arch.exception.nr;
 508         if (prev_nr == DF_VECTOR) {
 509                 /* triple fault -> shutdown */
 510                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 511                 return;
 512         }
 513         class1 = exception_class(prev_nr);
 514         class2 = exception_class(nr);
 515         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 516                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 517                 /*
 518                  * Generate double fault per SDM Table 5-5.  Set
 519                  * exception.pending = true so that the double fault
 520                  * can trigger a nested vmexit.
 521                  */
 522                 vcpu->arch.exception.pending = true;
 523                 vcpu->arch.exception.injected = false;
 524                 vcpu->arch.exception.has_error_code = true;
 525                 vcpu->arch.exception.nr = DF_VECTOR;
 526                 vcpu->arch.exception.error_code = 0;
 527                 vcpu->arch.exception.has_payload = false;
 528                 vcpu->arch.exception.payload = 0;
 529         } else
 530                 /* replace previous exception with a new one in a hope
 531                    that instruction re-execution will regenerate lost
 532                    exception */
 533                 goto queue;
 534 }
 535
 536 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 537 {
 538         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 539 }
 540 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 541
 542 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 543 {
 544         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 545 }
 546 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 547
 548 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 549                                   unsigned long payload)
 550 {
 551         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 552 }
 553
 554 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 555                                     u32 error_code, unsigned long payload)
 556 {
 557         kvm_multiple_exception(vcpu, nr, true, error_code,
 558                                true, payload, false);
 559 }
 560
 561 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 562 {
 563         if (err)
 564                 kvm_inject_gp(vcpu, 0);
 565         else
 566                 return kvm_skip_emulated_instruction(vcpu);
 567
 568         return 1;
 569 }
 570 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 571
 572 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 573 {
 574         ++vcpu->stat.pf_guest;
 575         vcpu->arch.exception.nested_apf =
 576                 is_guest_mode(vcpu) && fault->async_page_fault;
 577         if (vcpu->arch.exception.nested_apf) {
 578                 vcpu->arch.apf.nested_apf_token = fault->address;
 579                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 580         } else {
 581                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 582                                         fault->address);
 583         }
 584 }
 585 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 586
 587 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 588 {
 589         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 590                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 591         else
 592                 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
 593
 594         return fault->nested_page_fault;
 595 }
 596
 597 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 598 {
 599         atomic_inc(&vcpu->arch.nmi_queued);
 600         kvm_make_request(KVM_REQ_NMI, vcpu);
 601 }
 602 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 603
 604 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 605 {
 606         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 607 }
 608 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 609
 610 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 611 {
 612         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 613 }
 614 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 615
 616 /*
 617  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 618  * a #GP and return false.
 619  */
 620 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 621 {
 622         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 623                 return true;
 624         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 625         return false;
 626 }
 627 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 628
 629 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 630 {
 631         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 632                 return true;
 633
 634         kvm_queue_exception(vcpu, UD_VECTOR);
 635         return false;
 636 }
 637 EXPORT_SYMBOL_GPL(kvm_require_dr);
 638
 639 /*
 640  * This function will be used to read from the physical memory of the currently
 641  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 642  * can read from guest physical or from the guest's guest physical memory.
 643  */
 644 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 645                             gfn_t ngfn, void *data, int offset, int len,
 646                             u32 access)
 647 {
 648         struct x86_exception exception;
 649         gfn_t real_gfn;
 650         gpa_t ngpa;
 651
 652         ngpa     = gfn_to_gpa(ngfn);
 653         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 654         if (real_gfn == UNMAPPED_GVA)
 655                 return -EFAULT;
 656
 657         real_gfn = gpa_to_gfn(real_gfn);
 658
 659         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 660 }
 661 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 662
 663 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 664                                void *data, int offset, int len, u32 access)
 665 {
 666         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 667                                        data, offset, len, access);
 668 }
 669
 670 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 671 {
 672         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 673                rsvd_bits(1, 2);
 674 }
 675
 676 /*
 677  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 678  */
 679 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 680 {
 681         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 682         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 683         int i;
 684         int ret;
 685         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 686
 687         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 688                                       offset * sizeof(u64), sizeof(pdpte),
 689                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 690         if (ret < 0) {
 691                 ret = 0;
 692                 goto out;
 693         }
 694         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 695                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 696                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 697                         ret = 0;
 698                         goto out;
 699                 }
 700         }
 701         ret = 1;
 702
 703         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 704         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 705
 706 out:
 707
 708         return ret;
 709 }
 710 EXPORT_SYMBOL_GPL(load_pdptrs);
 711
 712 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 713 {
 714         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 715         int offset;
 716         gfn_t gfn;
 717         int r;
 718
 719         if (!is_pae_paging(vcpu))
 720                 return false;
 721
 722         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 723                 return true;
 724
 725         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 726         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 727         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 728                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 729         if (r < 0)
 730                 return true;
 731
 732         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 733 }
 734 EXPORT_SYMBOL_GPL(pdptrs_changed);
 735
 736 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 737 {
 738         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 739         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 740
 741         cr0 |= X86_CR0_ET;
 742
 743 #ifdef CONFIG_X86_64
 744         if (cr0 & 0xffffffff00000000UL)
 745                 return 1;
 746 #endif
 747
 748         cr0 &= ~CR0_RESERVED_BITS;
 749
 750         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 751                 return 1;
 752
 753         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 754                 return 1;
 755
 756         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 757 #ifdef CONFIG_X86_64
 758                 if ((vcpu->arch.efer & EFER_LME)) {
 759                         int cs_db, cs_l;
 760
 761                         if (!is_pae(vcpu))
 762                                 return 1;
 763                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 764                         if (cs_l)
 765                                 return 1;
 766                 } else
 767 #endif
 768                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 769                                                  kvm_read_cr3(vcpu)))
 770                         return 1;
 771         }
 772
 773         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 774                 return 1;
 775
 776         kvm_x86_ops->set_cr0(vcpu, cr0);
 777
 778         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 779                 kvm_clear_async_pf_completion_queue(vcpu);
 780                 kvm_async_pf_hash_reset(vcpu);
 781         }
 782
 783         if ((cr0 ^ old_cr0) & update_bits)
 784                 kvm_mmu_reset_context(vcpu);
 785
 786         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 787             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 788             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 789                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 790
 791         return 0;
 792 }
 793 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 794
 795 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 796 {
 797         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 798 }
 799 EXPORT_SYMBOL_GPL(kvm_lmsw);
 800
 801 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 802 {
 803         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 804
 805                 if (vcpu->arch.xcr0 != host_xcr0)
 806                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 807
 808                 if (vcpu->arch.xsaves_enabled &&
 809                     vcpu->arch.ia32_xss != host_xss)
 810                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 811         }
 812 }
 813 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 814
 815 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 816 {
 817         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 818
 819                 if (vcpu->arch.xcr0 != host_xcr0)
 820                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 821
 822                 if (vcpu->arch.xsaves_enabled &&
 823                     vcpu->arch.ia32_xss != host_xss)
 824                         wrmsrl(MSR_IA32_XSS, host_xss);
 825         }
 826
 827 }
 828 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 829
 830 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 831 {
 832         u64 xcr0 = xcr;
 833         u64 old_xcr0 = vcpu->arch.xcr0;
 834         u64 valid_bits;
 835
 836         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 837         if (index != XCR_XFEATURE_ENABLED_MASK)
 838                 return 1;
 839         if (!(xcr0 & XFEATURE_MASK_FP))
 840                 return 1;
 841         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 842                 return 1;
 843
 844         /*
 845          * Do not allow the guest to set bits that we do not support
 846          * saving.  However, xcr0 bit 0 is always set, even if the
 847          * emulated CPU does not support XSAVE (see fx_init).
 848          */
 849         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 850         if (xcr0 & ~valid_bits)
 851                 return 1;
 852
 853         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 854             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 855                 return 1;
 856
 857         if (xcr0 & XFEATURE_MASK_AVX512) {
 858                 if (!(xcr0 & XFEATURE_MASK_YMM))
 859                         return 1;
 860                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 861                         return 1;
 862         }
 863         vcpu->arch.xcr0 = xcr0;
 864
 865         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 866                 kvm_update_cpuid(vcpu);
 867         return 0;
 868 }
 869
 870 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 871 {
 872         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
 873             __kvm_set_xcr(vcpu, index, xcr)) {
 874                 kvm_inject_gp(vcpu, 0);
 875                 return 1;
 876         }
 877         return 0;
 878 }
 879 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 880
 881 #define __cr4_reserved_bits(__cpu_has, __c)             \
 882 ({                                                      \
 883         u64 __reserved_bits = CR4_RESERVED_BITS;        \
 884                                                         \
 885         if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
 886                 __reserved_bits |= X86_CR4_OSXSAVE;     \
 887         if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
 888                 __reserved_bits |= X86_CR4_SMEP;        \
 889         if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
 890                 __reserved_bits |= X86_CR4_SMAP;        \
 891         if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
 892                 __reserved_bits |= X86_CR4_FSGSBASE;    \
 893         if (!__cpu_has(__c, X86_FEATURE_PKU))           \
 894                 __reserved_bits |= X86_CR4_PKE;         \
 895         if (!__cpu_has(__c, X86_FEATURE_LA57))          \
 896                 __reserved_bits |= X86_CR4_LA57;        \
 897         if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
 898                 __reserved_bits |= X86_CR4_UMIP;        \
 899         __reserved_bits;                                \
 900 })
 901
 902 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
 903 {
 904         u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
 905
 906         if (cpuid_ecx(0x7) & feature_bit(LA57))
 907                 reserved_bits &= ~X86_CR4_LA57;
 908
 909         if (kvm_x86_ops->umip_emulated())
 910                 reserved_bits &= ~X86_CR4_UMIP;
 911
 912         return reserved_bits;
 913 }
 914
 915 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 916 {
 917         if (cr4 & cr4_reserved_bits)
 918                 return -EINVAL;
 919
 920         if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
 921                 return -EINVAL;
 922
 923         return 0;
 924 }
 925
 926 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 927 {
 928         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 929         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 930                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 931
 932         if (kvm_valid_cr4(vcpu, cr4))
 933                 return 1;
 934
 935         if (is_long_mode(vcpu)) {
 936                 if (!(cr4 & X86_CR4_PAE))
 937                         return 1;
 938         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 939                    && ((cr4 ^ old_cr4) & pdptr_bits)
 940                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 941                                    kvm_read_cr3(vcpu)))
 942                 return 1;
 943
 944         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 945                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 946                         return 1;
 947
 948                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 949                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 950                         return 1;
 951         }
 952
 953         if (kvm_x86_ops->set_cr4(vcpu, cr4))
 954                 return 1;
 955
 956         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 957             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 958                 kvm_mmu_reset_context(vcpu);
 959
 960         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
 961                 kvm_update_cpuid(vcpu);
 962
 963         return 0;
 964 }
 965 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 966
 967 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 968 {
 969         bool skip_tlb_flush = false;
 970 #ifdef CONFIG_X86_64
 971         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
 972
 973         if (pcid_enabled) {
 974                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
 975                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
 976         }
 977 #endif
 978
 979         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 980                 if (!skip_tlb_flush) {
 981                         kvm_mmu_sync_roots(vcpu);
 982                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 983                 }
 984                 return 0;
 985         }
 986
 987         if (is_long_mode(vcpu) &&
 988             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
 989                 return 1;
 990         else if (is_pae_paging(vcpu) &&
 991                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 992                 return 1;
 993
 994         kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
 995         vcpu->arch.cr3 = cr3;
 996         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
 997
 998         return 0;
 999 }
1000 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1001
1002 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1003 {
1004         if (cr8 & CR8_RESERVED_BITS)
1005                 return 1;
1006         if (lapic_in_kernel(vcpu))
1007                 kvm_lapic_set_tpr(vcpu, cr8);
1008         else
1009                 vcpu->arch.cr8 = cr8;
1010         return 0;
1011 }
1012 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1013
1014 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1015 {
1016         if (lapic_in_kernel(vcpu))
1017                 return kvm_lapic_get_cr8(vcpu);
1018         else
1019                 return vcpu->arch.cr8;
1020 }
1021 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1022
1023 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1024 {
1025         int i;
1026
1027         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1028                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1029                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1030                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1031         }
1032 }
1033
1034 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1035 {
1036         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1037                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1038 }
1039
1040 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1041 {
1042         unsigned long dr7;
1043
1044         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1045                 dr7 = vcpu->arch.guest_debug_dr7;
1046         else
1047                 dr7 = vcpu->arch.dr7;
1048         kvm_x86_ops->set_dr7(vcpu, dr7);
1049         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1050         if (dr7 & DR7_BP_EN_MASK)
1051                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1052 }
1053
1054 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1055 {
1056         u64 fixed = DR6_FIXED_1;
1057
1058         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1059                 fixed |= DR6_RTM;
1060         return fixed;
1061 }
1062
1063 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1064 {
1065         size_t size = ARRAY_SIZE(vcpu->arch.db);
1066
1067         switch (dr) {
1068         case 0 ... 3:
1069                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1070                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1071                         vcpu->arch.eff_db[dr] = val;
1072                 break;
1073         case 4:
1074                 /* fall through */
1075         case 6:
1076                 if (val & 0xffffffff00000000ULL)
1077                         return -1; /* #GP */
1078                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1079                 kvm_update_dr6(vcpu);
1080                 break;
1081         case 5:
1082                 /* fall through */
1083         default: /* 7 */
1084                 if (!kvm_dr7_valid(val))
1085                         return -1; /* #GP */
1086                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1087                 kvm_update_dr7(vcpu);
1088                 break;
1089         }
1090
1091         return 0;
1092 }
1093
1094 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1095 {
1096         if (__kvm_set_dr(vcpu, dr, val)) {
1097                 kvm_inject_gp(vcpu, 0);
1098                 return 1;
1099         }
1100         return 0;
1101 }
1102 EXPORT_SYMBOL_GPL(kvm_set_dr);
1103
1104 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1105 {
1106         size_t size = ARRAY_SIZE(vcpu->arch.db);
1107
1108         switch (dr) {
1109         case 0 ... 3:
1110                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1111                 break;
1112         case 4:
1113                 /* fall through */
1114         case 6:
1115                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116                         *val = vcpu->arch.dr6;
1117                 else
1118                         *val = kvm_x86_ops->get_dr6(vcpu);
1119                 break;
1120         case 5:
1121                 /* fall through */
1122         default: /* 7 */
1123                 *val = vcpu->arch.dr7;
1124                 break;
1125         }
1126         return 0;
1127 }
1128 EXPORT_SYMBOL_GPL(kvm_get_dr);
1129
1130 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1131 {
1132         u32 ecx = kvm_rcx_read(vcpu);
1133         u64 data;
1134         int err;
1135
1136         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1137         if (err)
1138                 return err;
1139         kvm_rax_write(vcpu, (u32)data);
1140         kvm_rdx_write(vcpu, data >> 32);
1141         return err;
1142 }
1143 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1144
1145 /*
1146  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1147  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1148  *
1149  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1150  * extract the supported MSRs from the related const lists.
1151  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1152  * capabilities of the host cpu. This capabilities test skips MSRs that are
1153  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1154  * may depend on host virtualization features rather than host cpu features.
1155  */
1156
1157 static const u32 msrs_to_save_all[] = {
1158         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1159         MSR_STAR,
1160 #ifdef CONFIG_X86_64
1161         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1162 #endif
1163         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1164         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1165         MSR_IA32_SPEC_CTRL,
1166         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1167         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1168         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1169         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1170         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1171         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1172         MSR_IA32_UMWAIT_CONTROL,
1173
1174         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1175         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1176         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1177         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1178         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1179         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1180         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1181         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1182         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1183         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1184         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1185         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1186         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1187         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1188         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1189         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1190         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1191         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1192         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1193         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1194         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1195         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1196 };
1197
1198 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1199 static unsigned num_msrs_to_save;
1200
1201 static const u32 emulated_msrs_all[] = {
1202         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1203         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1204         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1205         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1206         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1207         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1208         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1209         HV_X64_MSR_RESET,
1210         HV_X64_MSR_VP_INDEX,
1211         HV_X64_MSR_VP_RUNTIME,
1212         HV_X64_MSR_SCONTROL,
1213         HV_X64_MSR_STIMER0_CONFIG,
1214         HV_X64_MSR_VP_ASSIST_PAGE,
1215         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1216         HV_X64_MSR_TSC_EMULATION_STATUS,
1217
1218         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1219         MSR_KVM_PV_EOI_EN,
1220
1221         MSR_IA32_TSC_ADJUST,
1222         MSR_IA32_TSCDEADLINE,
1223         MSR_IA32_ARCH_CAPABILITIES,
1224         MSR_IA32_MISC_ENABLE,
1225         MSR_IA32_MCG_STATUS,
1226         MSR_IA32_MCG_CTL,
1227         MSR_IA32_MCG_EXT_CTL,
1228         MSR_IA32_SMBASE,
1229         MSR_SMI_COUNT,
1230         MSR_PLATFORM_INFO,
1231         MSR_MISC_FEATURES_ENABLES,
1232         MSR_AMD64_VIRT_SPEC_CTRL,
1233         MSR_IA32_POWER_CTL,
1234         MSR_IA32_UCODE_REV,
1235
1236         /*
1237          * The following list leaves out MSRs whose values are determined
1238          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1239          * We always support the "true" VMX control MSRs, even if the host
1240          * processor does not, so I am putting these registers here rather
1241          * than in msrs_to_save_all.
1242          */
1243         MSR_IA32_VMX_BASIC,
1244         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1245         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1246         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1247         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1248         MSR_IA32_VMX_MISC,
1249         MSR_IA32_VMX_CR0_FIXED0,
1250         MSR_IA32_VMX_CR4_FIXED0,
1251         MSR_IA32_VMX_VMCS_ENUM,
1252         MSR_IA32_VMX_PROCBASED_CTLS2,
1253         MSR_IA32_VMX_EPT_VPID_CAP,
1254         MSR_IA32_VMX_VMFUNC,
1255
1256         MSR_K7_HWCR,
1257         MSR_KVM_POLL_CONTROL,
1258 };
1259
1260 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1261 static unsigned num_emulated_msrs;
1262
1263 /*
1264  * List of msr numbers which are used to expose MSR-based features that
1265  * can be used by a hypervisor to validate requested CPU features.
1266  */
1267 static const u32 msr_based_features_all[] = {
1268         MSR_IA32_VMX_BASIC,
1269         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1270         MSR_IA32_VMX_PINBASED_CTLS,
1271         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1272         MSR_IA32_VMX_PROCBASED_CTLS,
1273         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1274         MSR_IA32_VMX_EXIT_CTLS,
1275         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1276         MSR_IA32_VMX_ENTRY_CTLS,
1277         MSR_IA32_VMX_MISC,
1278         MSR_IA32_VMX_CR0_FIXED0,
1279         MSR_IA32_VMX_CR0_FIXED1,
1280         MSR_IA32_VMX_CR4_FIXED0,
1281         MSR_IA32_VMX_CR4_FIXED1,
1282         MSR_IA32_VMX_VMCS_ENUM,
1283         MSR_IA32_VMX_PROCBASED_CTLS2,
1284         MSR_IA32_VMX_EPT_VPID_CAP,
1285         MSR_IA32_VMX_VMFUNC,
1286
1287         MSR_F10H_DECFG,
1288         MSR_IA32_UCODE_REV,
1289         MSR_IA32_ARCH_CAPABILITIES,
1290 };
1291
1292 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1293 static unsigned int num_msr_based_features;
1294
1295 static u64 kvm_get_arch_capabilities(void)
1296 {
1297         u64 data = 0;
1298
1299         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1300                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1301
1302         /*
1303          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1304          * the nested hypervisor runs with NX huge pages.  If it is not,
1305          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1306          * L1 guests, so it need not worry about its own (L2) guests.
1307          */
1308         data |= ARCH_CAP_PSCHANGE_MC_NO;
1309
1310         /*
1311          * If we're doing cache flushes (either "always" or "cond")
1312          * we will do one whenever the guest does a vmlaunch/vmresume.
1313          * If an outer hypervisor is doing the cache flush for us
1314          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1315          * capability to the guest too, and if EPT is disabled we're not
1316          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1317          * require a nested hypervisor to do a flush of its own.
1318          */
1319         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1320                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1321
1322         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1323                 data |= ARCH_CAP_RDCL_NO;
1324         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1325                 data |= ARCH_CAP_SSB_NO;
1326         if (!boot_cpu_has_bug(X86_BUG_MDS))
1327                 data |= ARCH_CAP_MDS_NO;
1328
1329         /*
1330          * On TAA affected systems:
1331          *      - nothing to do if TSX is disabled on the host.
1332          *      - we emulate TSX_CTRL if present on the host.
1333          *        This lets the guest use VERW to clear CPU buffers.
1334          */
1335         if (!boot_cpu_has(X86_FEATURE_RTM))
1336                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1337         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1338                 data |= ARCH_CAP_TAA_NO;
1339
1340         return data;
1341 }
1342
1343 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1344 {
1345         switch (msr->index) {
1346         case MSR_IA32_ARCH_CAPABILITIES:
1347                 msr->data = kvm_get_arch_capabilities();
1348                 break;
1349         case MSR_IA32_UCODE_REV:
1350                 rdmsrl_safe(msr->index, &msr->data);
1351                 break;
1352         default:
1353                 if (kvm_x86_ops->get_msr_feature(msr))
1354                         return 1;
1355         }
1356         return 0;
1357 }
1358
1359 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1360 {
1361         struct kvm_msr_entry msr;
1362         int r;
1363
1364         msr.index = index;
1365         r = kvm_get_msr_feature(&msr);
1366         if (r)
1367                 return r;
1368
1369         *data = msr.data;
1370
1371         return 0;
1372 }
1373
1374 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1375 {
1376         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1377                 return false;
1378
1379         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1380                 return false;
1381
1382         if (efer & (EFER_LME | EFER_LMA) &&
1383             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1384                 return false;
1385
1386         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1387                 return false;
1388
1389         return true;
1390
1391 }
1392 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1393 {
1394         if (efer & efer_reserved_bits)
1395                 return false;
1396
1397         return __kvm_valid_efer(vcpu, efer);
1398 }
1399 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1400
1401 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1402 {
1403         u64 old_efer = vcpu->arch.efer;
1404         u64 efer = msr_info->data;
1405
1406         if (efer & efer_reserved_bits)
1407                 return 1;
1408
1409         if (!msr_info->host_initiated) {
1410                 if (!__kvm_valid_efer(vcpu, efer))
1411                         return 1;
1412
1413                 if (is_paging(vcpu) &&
1414                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1415                         return 1;
1416         }
1417
1418         efer &= ~EFER_LMA;
1419         efer |= vcpu->arch.efer & EFER_LMA;
1420
1421         kvm_x86_ops->set_efer(vcpu, efer);
1422
1423         /* Update reserved bits */
1424         if ((efer ^ old_efer) & EFER_NX)
1425                 kvm_mmu_reset_context(vcpu);
1426
1427         return 0;
1428 }
1429
1430 void kvm_enable_efer_bits(u64 mask)
1431 {
1432        efer_reserved_bits &= ~mask;
1433 }
1434 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1435
1436 /*
1437  * Write @data into the MSR specified by @index.  Select MSR specific fault
1438  * checks are bypassed if @host_initiated is %true.
1439  * Returns 0 on success, non-0 otherwise.
1440  * Assumes vcpu_load() was already called.
1441  */
1442 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1443                          bool host_initiated)
1444 {
1445         struct msr_data msr;
1446
1447         switch (index) {
1448         case MSR_FS_BASE:
1449         case MSR_GS_BASE:
1450         case MSR_KERNEL_GS_BASE:
1451         case MSR_CSTAR:
1452         case MSR_LSTAR:
1453                 if (is_noncanonical_address(data, vcpu))
1454                         return 1;
1455                 break;
1456         case MSR_IA32_SYSENTER_EIP:
1457         case MSR_IA32_SYSENTER_ESP:
1458                 /*
1459                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1460                  * non-canonical address is written on Intel but not on
1461                  * AMD (which ignores the top 32-bits, because it does
1462                  * not implement 64-bit SYSENTER).
1463                  *
1464                  * 64-bit code should hence be able to write a non-canonical
1465                  * value on AMD.  Making the address canonical ensures that
1466                  * vmentry does not fail on Intel after writing a non-canonical
1467                  * value, and that something deterministic happens if the guest
1468                  * invokes 64-bit SYSENTER.
1469                  */
1470                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1471         }
1472
1473         msr.data = data;
1474         msr.index = index;
1475         msr.host_initiated = host_initiated;
1476
1477         return kvm_x86_ops->set_msr(vcpu, &msr);
1478 }
1479
1480 /*
1481  * Read the MSR specified by @index into @data.  Select MSR specific fault
1482  * checks are bypassed if @host_initiated is %true.
1483  * Returns 0 on success, non-0 otherwise.
1484  * Assumes vcpu_load() was already called.
1485  */
1486 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1487                   bool host_initiated)
1488 {
1489         struct msr_data msr;
1490         int ret;
1491
1492         msr.index = index;
1493         msr.host_initiated = host_initiated;
1494
1495         ret = kvm_x86_ops->get_msr(vcpu, &msr);
1496         if (!ret)
1497                 *data = msr.data;
1498         return ret;
1499 }
1500
1501 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1502 {
1503         return __kvm_get_msr(vcpu, index, data, false);
1504 }
1505 EXPORT_SYMBOL_GPL(kvm_get_msr);
1506
1507 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1508 {
1509         return __kvm_set_msr(vcpu, index, data, false);
1510 }
1511 EXPORT_SYMBOL_GPL(kvm_set_msr);
1512
1513 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1514 {
1515         u32 ecx = kvm_rcx_read(vcpu);
1516         u64 data;
1517
1518         if (kvm_get_msr(vcpu, ecx, &data)) {
1519                 trace_kvm_msr_read_ex(ecx);
1520                 kvm_inject_gp(vcpu, 0);
1521                 return 1;
1522         }
1523
1524         trace_kvm_msr_read(ecx, data);
1525
1526         kvm_rax_write(vcpu, data & -1u);
1527         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1528         return kvm_skip_emulated_instruction(vcpu);
1529 }
1530 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1531
1532 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1533 {
1534         u32 ecx = kvm_rcx_read(vcpu);
1535         u64 data = kvm_read_edx_eax(vcpu);
1536
1537         if (kvm_set_msr(vcpu, ecx, data)) {
1538                 trace_kvm_msr_write_ex(ecx, data);
1539                 kvm_inject_gp(vcpu, 0);
1540                 return 1;
1541         }
1542
1543         trace_kvm_msr_write(ecx, data);
1544         return kvm_skip_emulated_instruction(vcpu);
1545 }
1546 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1547
1548 /*
1549  * The fast path for frequent and performance sensitive wrmsr emulation,
1550  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1551  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1552  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1553  * other cases which must be called after interrupts are enabled on the host.
1554  */
1555 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1556 {
1557         if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1558                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1559                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1560
1561                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1562                 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data);
1563         }
1564
1565         return 1;
1566 }
1567
1568 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1569 {
1570         u32 msr = kvm_rcx_read(vcpu);
1571         u64 data = kvm_read_edx_eax(vcpu);
1572         int ret = 0;
1573
1574         switch (msr) {
1575         case APIC_BASE_MSR + (APIC_ICR >> 4):
1576                 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1577                 break;
1578         default:
1579                 return EXIT_FASTPATH_NONE;
1580         }
1581
1582         if (!ret) {
1583                 trace_kvm_msr_write(msr, data);
1584                 return EXIT_FASTPATH_SKIP_EMUL_INS;
1585         }
1586
1587         return EXIT_FASTPATH_NONE;
1588 }
1589 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1590
1591 /*
1592  * Adapt set_msr() to msr_io()'s calling convention
1593  */
1594 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1595 {
1596         return __kvm_get_msr(vcpu, index, data, true);
1597 }
1598
1599 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1600 {
1601         return __kvm_set_msr(vcpu, index, *data, true);
1602 }
1603
1604 #ifdef CONFIG_X86_64
1605 struct pvclock_clock {
1606         int vclock_mode;
1607         u64 cycle_last;
1608         u64 mask;
1609         u32 mult;
1610         u32 shift;
1611         u64 base_cycles;
1612         u64 offset;
1613 };
1614
1615 struct pvclock_gtod_data {
1616         seqcount_t      seq;
1617
1618         struct pvclock_clock clock; /* extract of a clocksource struct */
1619         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1620
1621         ktime_t         offs_boot;
1622         u64             wall_time_sec;
1623 };
1624
1625 static struct pvclock_gtod_data pvclock_gtod_data;
1626
1627 static void update_pvclock_gtod(struct timekeeper *tk)
1628 {
1629         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1630
1631         write_seqcount_begin(&vdata->seq);
1632
1633         /* copy pvclock gtod data */
1634         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1635         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1636         vdata->clock.mask               = tk->tkr_mono.mask;
1637         vdata->clock.mult               = tk->tkr_mono.mult;
1638         vdata->clock.shift              = tk->tkr_mono.shift;
1639         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1640         vdata->clock.offset             = tk->tkr_mono.base;
1641
1642         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->archdata.vclock_mode;
1643         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1644         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1645         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1646         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1647         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1648         vdata->raw_clock.offset         = tk->tkr_raw.base;
1649
1650         vdata->wall_time_sec            = tk->xtime_sec;
1651
1652         vdata->offs_boot                = tk->offs_boot;
1653
1654         write_seqcount_end(&vdata->seq);
1655 }
1656
1657 static s64 get_kvmclock_base_ns(void)
1658 {
1659         /* Count up from boot time, but with the frequency of the raw clock.  */
1660         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1661 }
1662 #else
1663 static s64 get_kvmclock_base_ns(void)
1664 {
1665         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1666         return ktime_get_boottime_ns();
1667 }
1668 #endif
1669
1670 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1671 {
1672         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1673         kvm_vcpu_kick(vcpu);
1674 }
1675
1676 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1677 {
1678         int version;
1679         int r;
1680         struct pvclock_wall_clock wc;
1681         u64 wall_nsec;
1682
1683         if (!wall_clock)
1684                 return;
1685
1686         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1687         if (r)
1688                 return;
1689
1690         if (version & 1)
1691                 ++version;  /* first time write, random junk */
1692
1693         ++version;
1694
1695         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1696                 return;
1697
1698         /*
1699          * The guest calculates current wall clock time by adding
1700          * system time (updated by kvm_guest_time_update below) to the
1701          * wall clock specified here.  We do the reverse here.
1702          */
1703         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1704
1705         wc.nsec = do_div(wall_nsec, 1000000000);
1706         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1707         wc.version = version;
1708
1709         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1710
1711         version++;
1712         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1713 }
1714
1715 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1716 {
1717         do_shl32_div32(dividend, divisor);
1718         return dividend;
1719 }
1720
1721 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1722                                s8 *pshift, u32 *pmultiplier)
1723 {
1724         uint64_t scaled64;
1725         int32_t  shift = 0;
1726         uint64_t tps64;
1727         uint32_t tps32;
1728
1729         tps64 = base_hz;
1730         scaled64 = scaled_hz;
1731         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1732                 tps64 >>= 1;
1733                 shift--;
1734         }
1735
1736         tps32 = (uint32_t)tps64;
1737         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1738                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1739                         scaled64 >>= 1;
1740                 else
1741                         tps32 <<= 1;
1742                 shift++;
1743         }
1744
1745         *pshift = shift;
1746         *pmultiplier = div_frac(scaled64, tps32);
1747 }
1748
1749 #ifdef CONFIG_X86_64
1750 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1751 #endif
1752
1753 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1754 static unsigned long max_tsc_khz;
1755
1756 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1757 {
1758         u64 v = (u64)khz * (1000000 + ppm);
1759         do_div(v, 1000000);
1760         return v;
1761 }
1762
1763 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1764 {
1765         u64 ratio;
1766
1767         /* Guest TSC same frequency as host TSC? */
1768         if (!scale) {
1769                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1770                 return 0;
1771         }
1772
1773         /* TSC scaling supported? */
1774         if (!kvm_has_tsc_control) {
1775                 if (user_tsc_khz > tsc_khz) {
1776                         vcpu->arch.tsc_catchup = 1;
1777                         vcpu->arch.tsc_always_catchup = 1;
1778                         return 0;
1779                 } else {
1780                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1781                         return -1;
1782                 }
1783         }
1784
1785         /* TSC scaling required  - calculate ratio */
1786         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1787                                 user_tsc_khz, tsc_khz);
1788
1789         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1790                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1791                                     user_tsc_khz);
1792                 return -1;
1793         }
1794
1795         vcpu->arch.tsc_scaling_ratio = ratio;
1796         return 0;
1797 }
1798
1799 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1800 {
1801         u32 thresh_lo, thresh_hi;
1802         int use_scaling = 0;
1803
1804         /* tsc_khz can be zero if TSC calibration fails */
1805         if (user_tsc_khz == 0) {
1806                 /* set tsc_scaling_ratio to a safe value */
1807                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1808                 return -1;
1809         }
1810
1811         /* Compute a scale to convert nanoseconds in TSC cycles */
1812         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1813                            &vcpu->arch.virtual_tsc_shift,
1814                            &vcpu->arch.virtual_tsc_mult);
1815         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1816
1817         /*
1818          * Compute the variation in TSC rate which is acceptable
1819          * within the range of tolerance and decide if the
1820          * rate being applied is within that bounds of the hardware
1821          * rate.  If so, no scaling or compensation need be done.
1822          */
1823         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1824         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1825         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1826                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1827                 use_scaling = 1;
1828         }
1829         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1830 }
1831
1832 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1833 {
1834         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1835                                       vcpu->arch.virtual_tsc_mult,
1836                                       vcpu->arch.virtual_tsc_shift);
1837         tsc += vcpu->arch.this_tsc_write;
1838         return tsc;
1839 }
1840
1841 static inline int gtod_is_based_on_tsc(int mode)
1842 {
1843         return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1844 }
1845
1846 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1847 {
1848 #ifdef CONFIG_X86_64
1849         bool vcpus_matched;
1850         struct kvm_arch *ka = &vcpu->kvm->arch;
1851         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1852
1853         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1854                          atomic_read(&vcpu->kvm->online_vcpus));
1855
1856         /*
1857          * Once the masterclock is enabled, always perform request in
1858          * order to update it.
1859          *
1860          * In order to enable masterclock, the host clocksource must be TSC
1861          * and the vcpus need to have matched TSCs.  When that happens,
1862          * perform request to enable masterclock.
1863          */
1864         if (ka->use_master_clock ||
1865             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1866                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1867
1868         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1869                             atomic_read(&vcpu->kvm->online_vcpus),
1870                             ka->use_master_clock, gtod->clock.vclock_mode);
1871 #endif
1872 }
1873
1874 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1875 {
1876         u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1877         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1878 }
1879
1880 /*
1881  * Multiply tsc by a fixed point number represented by ratio.
1882  *
1883  * The most significant 64-N bits (mult) of ratio represent the
1884  * integral part of the fixed point number; the remaining N bits
1885  * (frac) represent the fractional part, ie. ratio represents a fixed
1886  * point number (mult + frac * 2^(-N)).
1887  *
1888  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1889  */
1890 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1891 {
1892         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1893 }
1894
1895 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1896 {
1897         u64 _tsc = tsc;
1898         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1899
1900         if (ratio != kvm_default_tsc_scaling_ratio)
1901                 _tsc = __scale_tsc(ratio, tsc);
1902
1903         return _tsc;
1904 }
1905 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1906
1907 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1908 {
1909         u64 tsc;
1910
1911         tsc = kvm_scale_tsc(vcpu, rdtsc());
1912
1913         return target_tsc - tsc;
1914 }
1915
1916 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1917 {
1918         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1919
1920         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1921 }
1922 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1923
1924 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1925 {
1926         vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1927 }
1928
1929 static inline bool kvm_check_tsc_unstable(void)
1930 {
1931 #ifdef CONFIG_X86_64
1932         /*
1933          * TSC is marked unstable when we're running on Hyper-V,
1934          * 'TSC page' clocksource is good.
1935          */
1936         if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1937                 return false;
1938 #endif
1939         return check_tsc_unstable();
1940 }
1941
1942 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1943 {
1944         struct kvm *kvm = vcpu->kvm;
1945         u64 offset, ns, elapsed;
1946         unsigned long flags;
1947         bool matched;
1948         bool already_matched;
1949         u64 data = msr->data;
1950         bool synchronizing = false;
1951
1952         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1953         offset = kvm_compute_tsc_offset(vcpu, data);
1954         ns = get_kvmclock_base_ns();
1955         elapsed = ns - kvm->arch.last_tsc_nsec;
1956
1957         if (vcpu->arch.virtual_tsc_khz) {
1958                 if (data == 0 && msr->host_initiated) {
1959                         /*
1960                          * detection of vcpu initialization -- need to sync
1961                          * with other vCPUs. This particularly helps to keep
1962                          * kvm_clock stable after CPU hotplug
1963                          */
1964                         synchronizing = true;
1965                 } else {
1966                         u64 tsc_exp = kvm->arch.last_tsc_write +
1967                                                 nsec_to_cycles(vcpu, elapsed);
1968                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1969                         /*
1970                          * Special case: TSC write with a small delta (1 second)
1971                          * of virtual cycle time against real time is
1972                          * interpreted as an attempt to synchronize the CPU.
1973                          */
1974                         synchronizing = data < tsc_exp + tsc_hz &&
1975                                         data + tsc_hz > tsc_exp;
1976                 }
1977         }
1978
1979         /*
1980          * For a reliable TSC, we can match TSC offsets, and for an unstable
1981          * TSC, we add elapsed time in this computation.  We could let the
1982          * compensation code attempt to catch up if we fall behind, but
1983          * it's better to try to match offsets from the beginning.
1984          */
1985         if (synchronizing &&
1986             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1987                 if (!kvm_check_tsc_unstable()) {
1988                         offset = kvm->arch.cur_tsc_offset;
1989                 } else {
1990                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1991                         data += delta;
1992                         offset = kvm_compute_tsc_offset(vcpu, data);
1993                 }
1994                 matched = true;
1995                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1996         } else {
1997                 /*
1998                  * We split periods of matched TSC writes into generations.
1999                  * For each generation, we track the original measured
2000                  * nanosecond time, offset, and write, so if TSCs are in
2001                  * sync, we can match exact offset, and if not, we can match
2002                  * exact software computation in compute_guest_tsc()
2003                  *
2004                  * These values are tracked in kvm->arch.cur_xxx variables.
2005                  */
2006                 kvm->arch.cur_tsc_generation++;
2007                 kvm->arch.cur_tsc_nsec = ns;
2008                 kvm->arch.cur_tsc_write = data;
2009                 kvm->arch.cur_tsc_offset = offset;
2010                 matched = false;
2011         }
2012
2013         /*
2014          * We also track th most recent recorded KHZ, write and time to
2015          * allow the matching interval to be extended at each write.
2016          */
2017         kvm->arch.last_tsc_nsec = ns;
2018         kvm->arch.last_tsc_write = data;
2019         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2020
2021         vcpu->arch.last_guest_tsc = data;
2022
2023         /* Keep track of which generation this VCPU has synchronized to */
2024         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2025         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2026         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2027
2028         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2029                 update_ia32_tsc_adjust_msr(vcpu, offset);
2030
2031         kvm_vcpu_write_tsc_offset(vcpu, offset);
2032         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2033
2034         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2035         if (!matched) {
2036                 kvm->arch.nr_vcpus_matched_tsc = 0;
2037         } else if (!already_matched) {
2038                 kvm->arch.nr_vcpus_matched_tsc++;
2039         }
2040
2041         kvm_track_tsc_matching(vcpu);
2042         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2043 }
2044
2045 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2046
2047 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2048                                            s64 adjustment)
2049 {
2050         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2051         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2052 }
2053
2054 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2055 {
2056         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2057                 WARN_ON(adjustment < 0);
2058         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2059         adjust_tsc_offset_guest(vcpu, adjustment);
2060 }
2061
2062 #ifdef CONFIG_X86_64
2063
2064 static u64 read_tsc(void)
2065 {
2066         u64 ret = (u64)rdtsc_ordered();
2067         u64 last = pvclock_gtod_data.clock.cycle_last;
2068
2069         if (likely(ret >= last))
2070                 return ret;
2071
2072         /*
2073          * GCC likes to generate cmov here, but this branch is extremely
2074          * predictable (it's just a function of time and the likely is
2075          * very likely) and there's a data dependence, so force GCC
2076          * to generate a branch instead.  I don't barrier() because
2077          * we don't actually need a barrier, and if this function
2078          * ever gets inlined it will generate worse code.
2079          */
2080         asm volatile ("");
2081         return last;
2082 }
2083
2084 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2085                           int *mode)
2086 {
2087         long v;
2088         u64 tsc_pg_val;
2089
2090         switch (clock->vclock_mode) {
2091         case VCLOCK_HVCLOCK:
2092                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2093                                                   tsc_timestamp);
2094                 if (tsc_pg_val != U64_MAX) {
2095                         /* TSC page valid */
2096                         *mode = VCLOCK_HVCLOCK;
2097                         v = (tsc_pg_val - clock->cycle_last) &
2098                                 clock->mask;
2099                 } else {
2100                         /* TSC page invalid */
2101                         *mode = VCLOCK_NONE;
2102                 }
2103                 break;
2104         case VCLOCK_TSC:
2105                 *mode = VCLOCK_TSC;
2106                 *tsc_timestamp = read_tsc();
2107                 v = (*tsc_timestamp - clock->cycle_last) &
2108                         clock->mask;
2109                 break;
2110         default:
2111                 *mode = VCLOCK_NONE;
2112         }
2113
2114         if (*mode == VCLOCK_NONE)
2115                 *tsc_timestamp = v = 0;
2116
2117         return v * clock->mult;
2118 }
2119
2120 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2121 {
2122         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2123         unsigned long seq;
2124         int mode;
2125         u64 ns;
2126
2127         do {
2128                 seq = read_seqcount_begin(&gtod->seq);
2129                 ns = gtod->raw_clock.base_cycles;
2130                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2131                 ns >>= gtod->raw_clock.shift;
2132                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2133         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2134         *t = ns;
2135
2136         return mode;
2137 }
2138
2139 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2140 {
2141         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2142         unsigned long seq;
2143         int mode;
2144         u64 ns;
2145
2146         do {
2147                 seq = read_seqcount_begin(&gtod->seq);
2148                 ts->tv_sec = gtod->wall_time_sec;
2149                 ns = gtod->clock.base_cycles;
2150                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2151                 ns >>= gtod->clock.shift;
2152         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2153
2154         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2155         ts->tv_nsec = ns;
2156
2157         return mode;
2158 }
2159
2160 /* returns true if host is using TSC based clocksource */
2161 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2162 {
2163         /* checked again under seqlock below */
2164         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2165                 return false;
2166
2167         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2168                                                       tsc_timestamp));
2169 }
2170
2171 /* returns true if host is using TSC based clocksource */
2172 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2173                                            u64 *tsc_timestamp)
2174 {
2175         /* checked again under seqlock below */
2176         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2177                 return false;
2178
2179         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2180 }
2181 #endif
2182
2183 /*
2184  *
2185  * Assuming a stable TSC across physical CPUS, and a stable TSC
2186  * across virtual CPUs, the following condition is possible.
2187  * Each numbered line represents an event visible to both
2188  * CPUs at the next numbered event.
2189  *
2190  * "timespecX" represents host monotonic time. "tscX" represents
2191  * RDTSC value.
2192  *
2193  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2194  *
2195  * 1.  read timespec0,tsc0
2196  * 2.                                   | timespec1 = timespec0 + N
2197  *                                      | tsc1 = tsc0 + M
2198  * 3. transition to guest               | transition to guest
2199  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2200  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2201  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2202  *
2203  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2204  *
2205  *      - ret0 < ret1
2206  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2207  *              ...
2208  *      - 0 < N - M => M < N
2209  *
2210  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2211  * always the case (the difference between two distinct xtime instances
2212  * might be smaller then the difference between corresponding TSC reads,
2213  * when updating guest vcpus pvclock areas).
2214  *
2215  * To avoid that problem, do not allow visibility of distinct
2216  * system_timestamp/tsc_timestamp values simultaneously: use a master
2217  * copy of host monotonic time values. Update that master copy
2218  * in lockstep.
2219  *
2220  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2221  *
2222  */
2223
2224 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2225 {
2226 #ifdef CONFIG_X86_64
2227         struct kvm_arch *ka = &kvm->arch;
2228         int vclock_mode;
2229         bool host_tsc_clocksource, vcpus_matched;
2230
2231         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2232                         atomic_read(&kvm->online_vcpus));
2233
2234         /*
2235          * If the host uses TSC clock, then passthrough TSC as stable
2236          * to the guest.
2237          */
2238         host_tsc_clocksource = kvm_get_time_and_clockread(
2239                                         &ka->master_kernel_ns,
2240                                         &ka->master_cycle_now);
2241
2242         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2243                                 && !ka->backwards_tsc_observed
2244                                 && !ka->boot_vcpu_runs_old_kvmclock;
2245
2246         if (ka->use_master_clock)
2247                 atomic_set(&kvm_guest_has_master_clock, 1);
2248
2249         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2250         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2251                                         vcpus_matched);
2252 #endif
2253 }
2254
2255 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2256 {
2257         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2258 }
2259
2260 static void kvm_gen_update_masterclock(struct kvm *kvm)
2261 {
2262 #ifdef CONFIG_X86_64
2263         int i;
2264         struct kvm_vcpu *vcpu;
2265         struct kvm_arch *ka = &kvm->arch;
2266
2267         spin_lock(&ka->pvclock_gtod_sync_lock);
2268         kvm_make_mclock_inprogress_request(kvm);
2269         /* no guest entries from this point */
2270         pvclock_update_vm_gtod_copy(kvm);
2271
2272         kvm_for_each_vcpu(i, vcpu, kvm)
2273                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2274
2275         /* guest entries allowed */
2276         kvm_for_each_vcpu(i, vcpu, kvm)
2277                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2278
2279         spin_unlock(&ka->pvclock_gtod_sync_lock);
2280 #endif
2281 }
2282
2283 u64 get_kvmclock_ns(struct kvm *kvm)
2284 {
2285         struct kvm_arch *ka = &kvm->arch;
2286         struct pvclock_vcpu_time_info hv_clock;
2287         u64 ret;
2288
2289         spin_lock(&ka->pvclock_gtod_sync_lock);
2290         if (!ka->use_master_clock) {
2291                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2292                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2293         }
2294
2295         hv_clock.tsc_timestamp = ka->master_cycle_now;
2296         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2297         spin_unlock(&ka->pvclock_gtod_sync_lock);
2298
2299         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2300         get_cpu();
2301
2302         if (__this_cpu_read(cpu_tsc_khz)) {
2303                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2304                                    &hv_clock.tsc_shift,
2305                                    &hv_clock.tsc_to_system_mul);
2306                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2307         } else
2308                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2309
2310         put_cpu();
2311
2312         return ret;
2313 }
2314
2315 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2316 {
2317         struct kvm_vcpu_arch *vcpu = &v->arch;
2318         struct pvclock_vcpu_time_info guest_hv_clock;
2319
2320         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2321                 &guest_hv_clock, sizeof(guest_hv_clock))))
2322                 return;
2323
2324         /* This VCPU is paused, but it's legal for a guest to read another
2325          * VCPU's kvmclock, so we really have to follow the specification where
2326          * it says that version is odd if data is being modified, and even after
2327          * it is consistent.
2328          *
2329          * Version field updates must be kept separate.  This is because
2330          * kvm_write_guest_cached might use a "rep movs" instruction, and
2331          * writes within a string instruction are weakly ordered.  So there
2332          * are three writes overall.
2333          *
2334          * As a small optimization, only write the version field in the first
2335          * and third write.  The vcpu->pv_time cache is still valid, because the
2336          * version field is the first in the struct.
2337          */
2338         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2339
2340         if (guest_hv_clock.version & 1)
2341                 ++guest_hv_clock.version;  /* first time write, random junk */
2342
2343         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2344         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2345                                 &vcpu->hv_clock,
2346                                 sizeof(vcpu->hv_clock.version));
2347
2348         smp_wmb();
2349
2350         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2351         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2352
2353         if (vcpu->pvclock_set_guest_stopped_request) {
2354                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2355                 vcpu->pvclock_set_guest_stopped_request = false;
2356         }
2357
2358         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2359
2360         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2361                                 &vcpu->hv_clock,
2362                                 sizeof(vcpu->hv_clock));
2363
2364         smp_wmb();
2365
2366         vcpu->hv_clock.version++;
2367         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2368                                 &vcpu->hv_clock,
2369                                 sizeof(vcpu->hv_clock.version));
2370 }
2371
2372 static int kvm_guest_time_update(struct kvm_vcpu *v)
2373 {
2374         unsigned long flags, tgt_tsc_khz;
2375         struct kvm_vcpu_arch *vcpu = &v->arch;
2376         struct kvm_arch *ka = &v->kvm->arch;
2377         s64 kernel_ns;
2378         u64 tsc_timestamp, host_tsc;
2379         u8 pvclock_flags;
2380         bool use_master_clock;
2381
2382         kernel_ns = 0;
2383         host_tsc = 0;
2384
2385         /*
2386          * If the host uses TSC clock, then passthrough TSC as stable
2387          * to the guest.
2388          */
2389         spin_lock(&ka->pvclock_gtod_sync_lock);
2390         use_master_clock = ka->use_master_clock;
2391         if (use_master_clock) {
2392                 host_tsc = ka->master_cycle_now;
2393                 kernel_ns = ka->master_kernel_ns;
2394         }
2395         spin_unlock(&ka->pvclock_gtod_sync_lock);
2396
2397         /* Keep irq disabled to prevent changes to the clock */
2398         local_irq_save(flags);
2399         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2400         if (unlikely(tgt_tsc_khz == 0)) {
2401                 local_irq_restore(flags);
2402                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2403                 return 1;
2404         }
2405         if (!use_master_clock) {
2406                 host_tsc = rdtsc();
2407                 kernel_ns = get_kvmclock_base_ns();
2408         }
2409
2410         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2411
2412         /*
2413          * We may have to catch up the TSC to match elapsed wall clock
2414          * time for two reasons, even if kvmclock is used.
2415          *   1) CPU could have been running below the maximum TSC rate
2416          *   2) Broken TSC compensation resets the base at each VCPU
2417          *      entry to avoid unknown leaps of TSC even when running
2418          *      again on the same CPU.  This may cause apparent elapsed
2419          *      time to disappear, and the guest to stand still or run
2420          *      very slowly.
2421          */
2422         if (vcpu->tsc_catchup) {
2423                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2424                 if (tsc > tsc_timestamp) {
2425                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2426                         tsc_timestamp = tsc;
2427                 }
2428         }
2429
2430         local_irq_restore(flags);
2431
2432         /* With all the info we got, fill in the values */
2433
2434         if (kvm_has_tsc_control)
2435                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2436
2437         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2438                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2439                                    &vcpu->hv_clock.tsc_shift,
2440                                    &vcpu->hv_clock.tsc_to_system_mul);
2441                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2442         }
2443
2444         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2445         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2446         vcpu->last_guest_tsc = tsc_timestamp;
2447         WARN_ON((s64)vcpu->hv_clock.system_time < 0);
2448
2449         /* If the host uses TSC clocksource, then it is stable */
2450         pvclock_flags = 0;
2451         if (use_master_clock)
2452                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2453
2454         vcpu->hv_clock.flags = pvclock_flags;
2455
2456         if (vcpu->pv_time_enabled)
2457                 kvm_setup_pvclock_page(v);
2458         if (v == kvm_get_vcpu(v->kvm, 0))
2459                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2460         return 0;
2461 }
2462
2463 /*
2464  * kvmclock updates which are isolated to a given vcpu, such as
2465  * vcpu->cpu migration, should not allow system_timestamp from
2466  * the rest of the vcpus to remain static. Otherwise ntp frequency
2467  * correction applies to one vcpu's system_timestamp but not
2468  * the others.
2469  *
2470  * So in those cases, request a kvmclock update for all vcpus.
2471  * We need to rate-limit these requests though, as they can
2472  * considerably slow guests that have a large number of vcpus.
2473  * The time for a remote vcpu to update its kvmclock is bound
2474  * by the delay we use to rate-limit the updates.
2475  */
2476
2477 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2478
2479 static void kvmclock_update_fn(struct work_struct *work)
2480 {
2481         int i;
2482         struct delayed_work *dwork = to_delayed_work(work);
2483         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2484                                            kvmclock_update_work);
2485         struct kvm *kvm = container_of(ka, struct kvm, arch);
2486         struct kvm_vcpu *vcpu;
2487
2488         kvm_for_each_vcpu(i, vcpu, kvm) {
2489                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2490                 kvm_vcpu_kick(vcpu);
2491         }
2492 }
2493
2494 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2495 {
2496         struct kvm *kvm = v->kvm;
2497
2498         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2499         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2500                                         KVMCLOCK_UPDATE_DELAY);
2501 }
2502
2503 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2504
2505 static void kvmclock_sync_fn(struct work_struct *work)
2506 {
2507         struct delayed_work *dwork = to_delayed_work(work);
2508         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2509                                            kvmclock_sync_work);
2510         struct kvm *kvm = container_of(ka, struct kvm, arch);
2511
2512         if (!kvmclock_periodic_sync)
2513                 return;
2514
2515         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2516         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2517                                         KVMCLOCK_SYNC_PERIOD);
2518 }
2519
2520 /*
2521  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2522  */
2523 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2524 {
2525         /* McStatusWrEn enabled? */
2526         if (guest_cpuid_is_amd(vcpu))
2527                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2528
2529         return false;
2530 }
2531
2532 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2533 {
2534         u64 mcg_cap = vcpu->arch.mcg_cap;
2535         unsigned bank_num = mcg_cap & 0xff;
2536         u32 msr = msr_info->index;
2537         u64 data = msr_info->data;
2538
2539         switch (msr) {
2540         case MSR_IA32_MCG_STATUS:
2541                 vcpu->arch.mcg_status = data;
2542                 break;
2543         case MSR_IA32_MCG_CTL:
2544                 if (!(mcg_cap & MCG_CTL_P) &&
2545                     (data || !msr_info->host_initiated))
2546                         return 1;
2547                 if (data != 0 && data != ~(u64)0)
2548                         return 1;
2549                 vcpu->arch.mcg_ctl = data;
2550                 break;
2551         default:
2552                 if (msr >= MSR_IA32_MC0_CTL &&
2553                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2554                         u32 offset = array_index_nospec(
2555                                 msr - MSR_IA32_MC0_CTL,
2556                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2557
2558                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2559                          * some Linux kernels though clear bit 10 in bank 4 to
2560                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2561                          * this to avoid an uncatched #GP in the guest
2562                          */
2563                         if ((offset & 0x3) == 0 &&
2564                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2565                                 return -1;
2566
2567                         /* MCi_STATUS */
2568                         if (!msr_info->host_initiated &&
2569                             (offset & 0x3) == 1 && data != 0) {
2570                                 if (!can_set_mci_status(vcpu))
2571                                         return -1;
2572                         }
2573
2574                         vcpu->arch.mce_banks[offset] = data;
2575                         break;
2576                 }
2577                 return 1;
2578         }
2579         return 0;
2580 }
2581
2582 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2583 {
2584         struct kvm *kvm = vcpu->kvm;
2585         int lm = is_long_mode(vcpu);
2586         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2587                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2588         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2589                 : kvm->arch.xen_hvm_config.blob_size_32;
2590         u32 page_num = data & ~PAGE_MASK;
2591         u64 page_addr = data & PAGE_MASK;
2592         u8 *page;
2593         int r;
2594
2595         r = -E2BIG;
2596         if (page_num >= blob_size)
2597                 goto out;
2598         r = -ENOMEM;
2599         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2600         if (IS_ERR(page)) {
2601                 r = PTR_ERR(page);
2602                 goto out;
2603         }
2604         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2605                 goto out_free;
2606         r = 0;
2607 out_free:
2608         kfree(page);
2609 out:
2610         return r;
2611 }
2612
2613 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2614 {
2615         gpa_t gpa = data & ~0x3f;
2616
2617         /* Bits 3:5 are reserved, Should be zero */
2618         if (data & 0x38)
2619                 return 1;
2620
2621         vcpu->arch.apf.msr_val = data;
2622
2623         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2624                 kvm_clear_async_pf_completion_queue(vcpu);
2625                 kvm_async_pf_hash_reset(vcpu);
2626                 return 0;
2627         }
2628
2629         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2630                                         sizeof(u32)))
2631                 return 1;
2632
2633         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2634         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2635         kvm_async_pf_wakeup_all(vcpu);
2636         return 0;
2637 }
2638
2639 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2640 {
2641         vcpu->arch.pv_time_enabled = false;
2642         vcpu->arch.time = 0;
2643 }
2644
2645 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2646 {
2647         ++vcpu->stat.tlb_flush;
2648         kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2649 }
2650
2651 static void record_steal_time(struct kvm_vcpu *vcpu)
2652 {
2653         struct kvm_host_map map;
2654         struct kvm_steal_time *st;
2655
2656         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2657                 return;
2658
2659         /* -EAGAIN is returned in atomic context so we can just return. */
2660         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2661                         &map, &vcpu->arch.st.cache, false))
2662                 return;
2663
2664         st = map.hva +
2665                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2666
2667         /*
2668          * Doing a TLB flush here, on the guest's behalf, can avoid
2669          * expensive IPIs.
2670          */
2671         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2672                 st->preempted & KVM_VCPU_FLUSH_TLB);
2673         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2674                 kvm_vcpu_flush_tlb(vcpu, false);
2675
2676         vcpu->arch.st.preempted = 0;
2677
2678         if (st->version & 1)
2679                 st->version += 1;  /* first time write, random junk */
2680
2681         st->version += 1;
2682
2683         smp_wmb();
2684
2685         st->steal += current->sched_info.run_delay -
2686                 vcpu->arch.st.last_steal;
2687         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2688
2689         smp_wmb();
2690
2691         st->version += 1;
2692
2693         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2694 }
2695
2696 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2697 {
2698         bool pr = false;
2699         u32 msr = msr_info->index;
2700         u64 data = msr_info->data;
2701
2702         switch (msr) {
2703         case MSR_AMD64_NB_CFG:
2704         case MSR_IA32_UCODE_WRITE:
2705         case MSR_VM_HSAVE_PA:
2706         case MSR_AMD64_PATCH_LOADER:
2707         case MSR_AMD64_BU_CFG2:
2708         case MSR_AMD64_DC_CFG:
2709         case MSR_F15H_EX_CFG:
2710                 break;
2711
2712         case MSR_IA32_UCODE_REV:
2713                 if (msr_info->host_initiated)
2714                         vcpu->arch.microcode_version = data;
2715                 break;
2716         case MSR_IA32_ARCH_CAPABILITIES:
2717                 if (!msr_info->host_initiated)
2718                         return 1;
2719                 vcpu->arch.arch_capabilities = data;
2720                 break;
2721         case MSR_EFER:
2722                 return set_efer(vcpu, msr_info);
2723         case MSR_K7_HWCR:
2724                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2725                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2726                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2727
2728                 /* Handle McStatusWrEn */
2729                 if (data == BIT_ULL(18)) {
2730                         vcpu->arch.msr_hwcr = data;
2731                 } else if (data != 0) {
2732                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2733                                     data);
2734                         return 1;
2735                 }
2736                 break;
2737         case MSR_FAM10H_MMIO_CONF_BASE:
2738                 if (data != 0) {
2739                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2740                                     "0x%llx\n", data);
2741                         return 1;
2742                 }
2743                 break;
2744         case MSR_IA32_DEBUGCTLMSR:
2745                 if (!data) {
2746                         /* We support the non-activated case already */
2747                         break;
2748                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2749                         /* Values other than LBR and BTF are vendor-specific,
2750                            thus reserved and should throw a #GP */
2751                         return 1;
2752                 }
2753                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2754                             __func__, data);
2755                 break;
2756         case 0x200 ... 0x2ff:
2757                 return kvm_mtrr_set_msr(vcpu, msr, data);
2758         case MSR_IA32_APICBASE:
2759                 return kvm_set_apic_base(vcpu, msr_info);
2760         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2761                 return kvm_x2apic_msr_write(vcpu, msr, data);
2762         case MSR_IA32_TSCDEADLINE:
2763                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2764                 break;
2765         case MSR_IA32_TSC_ADJUST:
2766                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2767                         if (!msr_info->host_initiated) {
2768                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2769                                 adjust_tsc_offset_guest(vcpu, adj);
2770                         }
2771                         vcpu->arch.ia32_tsc_adjust_msr = data;
2772                 }
2773                 break;
2774         case MSR_IA32_MISC_ENABLE:
2775                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2776                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2777                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2778                                 return 1;
2779                         vcpu->arch.ia32_misc_enable_msr = data;
2780                         kvm_update_cpuid(vcpu);
2781                 } else {
2782                         vcpu->arch.ia32_misc_enable_msr = data;
2783                 }
2784                 break;
2785         case MSR_IA32_SMBASE:
2786                 if (!msr_info->host_initiated)
2787                         return 1;
2788                 vcpu->arch.smbase = data;
2789                 break;
2790         case MSR_IA32_POWER_CTL:
2791                 vcpu->arch.msr_ia32_power_ctl = data;
2792                 break;
2793         case MSR_IA32_TSC:
2794                 kvm_write_tsc(vcpu, msr_info);
2795                 break;
2796         case MSR_IA32_XSS:
2797                 if (!msr_info->host_initiated &&
2798                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2799                         return 1;
2800                 /*
2801                  * We do support PT if kvm_x86_ops->pt_supported(), but we do
2802                  * not support IA32_XSS[bit 8]. Guests will have to use
2803                  * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT
2804                  * MSRs.
2805                  */
2806                 if (data != 0)
2807                         return 1;
2808                 vcpu->arch.ia32_xss = data;
2809                 break;
2810         case MSR_SMI_COUNT:
2811                 if (!msr_info->host_initiated)
2812                         return 1;
2813                 vcpu->arch.smi_count = data;
2814                 break;
2815         case MSR_KVM_WALL_CLOCK_NEW:
2816         case MSR_KVM_WALL_CLOCK:
2817                 vcpu->kvm->arch.wall_clock = data;
2818                 kvm_write_wall_clock(vcpu->kvm, data);
2819                 break;
2820         case MSR_KVM_SYSTEM_TIME_NEW:
2821         case MSR_KVM_SYSTEM_TIME: {
2822                 struct kvm_arch *ka = &vcpu->kvm->arch;
2823
2824                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2825                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2826
2827                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2828                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2829
2830                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2831                 }
2832
2833                 vcpu->arch.time = data;
2834                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2835
2836                 /* we verify if the enable bit is set... */
2837                 vcpu->arch.pv_time_enabled = false;
2838                 if (!(data & 1))
2839                         break;
2840
2841                 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2842                      &vcpu->arch.pv_time, data & ~1ULL,
2843                      sizeof(struct pvclock_vcpu_time_info)))
2844                         vcpu->arch.pv_time_enabled = true;
2845
2846                 break;
2847         }
2848         case MSR_KVM_ASYNC_PF_EN:
2849                 if (kvm_pv_enable_async_pf(vcpu, data))
2850                         return 1;
2851                 break;
2852         case MSR_KVM_STEAL_TIME:
2853
2854                 if (unlikely(!sched_info_on()))
2855                         return 1;
2856
2857                 if (data & KVM_STEAL_RESERVED_MASK)
2858                         return 1;
2859
2860                 vcpu->arch.st.msr_val = data;
2861
2862                 if (!(data & KVM_MSR_ENABLED))
2863                         break;
2864
2865                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2866
2867                 break;
2868         case MSR_KVM_PV_EOI_EN:
2869                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2870                         return 1;
2871                 break;
2872
2873         case MSR_KVM_POLL_CONTROL:
2874                 /* only enable bit supported */
2875                 if (data & (-1ULL << 1))
2876                         return 1;
2877
2878                 vcpu->arch.msr_kvm_poll_control = data;
2879                 break;
2880
2881         case MSR_IA32_MCG_CTL:
2882         case MSR_IA32_MCG_STATUS:
2883         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2884                 return set_msr_mce(vcpu, msr_info);
2885
2886         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2887         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2888                 pr = true; /* fall through */
2889         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2890         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2891                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2892                         return kvm_pmu_set_msr(vcpu, msr_info);
2893
2894                 if (pr || data != 0)
2895                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2896                                     "0x%x data 0x%llx\n", msr, data);
2897                 break;
2898         case MSR_K7_CLK_CTL:
2899                 /*
2900                  * Ignore all writes to this no longer documented MSR.
2901                  * Writes are only relevant for old K7 processors,
2902                  * all pre-dating SVM, but a recommended workaround from
2903                  * AMD for these chips. It is possible to specify the
2904                  * affected processor models on the command line, hence
2905                  * the need to ignore the workaround.
2906                  */
2907                 break;
2908         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2909         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2910         case HV_X64_MSR_CRASH_CTL:
2911         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2912         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2913         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2914         case HV_X64_MSR_TSC_EMULATION_STATUS:
2915                 return kvm_hv_set_msr_common(vcpu, msr, data,
2916                                              msr_info->host_initiated);
2917         case MSR_IA32_BBL_CR_CTL3:
2918                 /* Drop writes to this legacy MSR -- see rdmsr
2919                  * counterpart for further detail.
2920                  */
2921                 if (report_ignored_msrs)
2922                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2923                                 msr, data);
2924                 break;
2925         case MSR_AMD64_OSVW_ID_LENGTH:
2926                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2927                         return 1;
2928                 vcpu->arch.osvw.length = data;
2929                 break;
2930         case MSR_AMD64_OSVW_STATUS:
2931                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2932                         return 1;
2933                 vcpu->arch.osvw.status = data;
2934                 break;
2935         case MSR_PLATFORM_INFO:
2936                 if (!msr_info->host_initiated ||
2937                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2938                      cpuid_fault_enabled(vcpu)))
2939                         return 1;
2940                 vcpu->arch.msr_platform_info = data;
2941                 break;
2942         case MSR_MISC_FEATURES_ENABLES:
2943                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2944                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2945                      !supports_cpuid_fault(vcpu)))
2946                         return 1;
2947                 vcpu->arch.msr_misc_features_enables = data;
2948                 break;
2949         default:
2950                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2951                         return xen_hvm_config(vcpu, data);
2952                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2953                         return kvm_pmu_set_msr(vcpu, msr_info);
2954                 if (!ignore_msrs) {
2955                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2956                                     msr, data);
2957                         return 1;
2958                 } else {
2959                         if (report_ignored_msrs)
2960                                 vcpu_unimpl(vcpu,
2961                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2962                                         msr, data);
2963                         break;
2964                 }
2965         }
2966         return 0;
2967 }
2968 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2969
2970 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2971 {
2972         u64 data;
2973         u64 mcg_cap = vcpu->arch.mcg_cap;
2974         unsigned bank_num = mcg_cap & 0xff;
2975
2976         switch (msr) {
2977         case MSR_IA32_P5_MC_ADDR:
2978         case MSR_IA32_P5_MC_TYPE:
2979                 data = 0;
2980                 break;
2981         case MSR_IA32_MCG_CAP:
2982                 data = vcpu->arch.mcg_cap;
2983                 break;
2984         case MSR_IA32_MCG_CTL:
2985                 if (!(mcg_cap & MCG_CTL_P) && !host)
2986                         return 1;
2987                 data = vcpu->arch.mcg_ctl;
2988                 break;
2989         case MSR_IA32_MCG_STATUS:
2990                 data = vcpu->arch.mcg_status;
2991                 break;
2992         default:
2993                 if (msr >= MSR_IA32_MC0_CTL &&
2994                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2995                         u32 offset = array_index_nospec(
2996                                 msr - MSR_IA32_MC0_CTL,
2997                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2998
2999                         data = vcpu->arch.mce_banks[offset];
3000                         break;
3001                 }
3002                 return 1;
3003         }
3004         *pdata = data;
3005         return 0;
3006 }
3007
3008 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3009 {
3010         switch (msr_info->index) {
3011         case MSR_IA32_PLATFORM_ID:
3012         case MSR_IA32_EBL_CR_POWERON:
3013         case MSR_IA32_DEBUGCTLMSR:
3014         case MSR_IA32_LASTBRANCHFROMIP:
3015         case MSR_IA32_LASTBRANCHTOIP:
3016         case MSR_IA32_LASTINTFROMIP:
3017         case MSR_IA32_LASTINTTOIP:
3018         case MSR_K8_SYSCFG:
3019         case MSR_K8_TSEG_ADDR:
3020         case MSR_K8_TSEG_MASK:
3021         case MSR_VM_HSAVE_PA:
3022         case MSR_K8_INT_PENDING_MSG:
3023         case MSR_AMD64_NB_CFG:
3024         case MSR_FAM10H_MMIO_CONF_BASE:
3025         case MSR_AMD64_BU_CFG2:
3026         case MSR_IA32_PERF_CTL:
3027         case MSR_AMD64_DC_CFG:
3028         case MSR_F15H_EX_CFG:
3029                 msr_info->data = 0;
3030                 break;
3031         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3032         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3033         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3034         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3035         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3036                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3037                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3038                 msr_info->data = 0;
3039                 break;
3040         case MSR_IA32_UCODE_REV:
3041                 msr_info->data = vcpu->arch.microcode_version;
3042                 break;
3043         case MSR_IA32_ARCH_CAPABILITIES:
3044                 if (!msr_info->host_initiated &&
3045                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3046                         return 1;
3047                 msr_info->data = vcpu->arch.arch_capabilities;
3048                 break;
3049         case MSR_IA32_POWER_CTL:
3050                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3051                 break;
3052         case MSR_IA32_TSC:
3053                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3054                 break;
3055         case MSR_MTRRcap:
3056         case 0x200 ... 0x2ff:
3057                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3058         case 0xcd: /* fsb frequency */
3059                 msr_info->data = 3;
3060                 break;
3061                 /*
3062                  * MSR_EBC_FREQUENCY_ID
3063                  * Conservative value valid for even the basic CPU models.
3064                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3065                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3066                  * and 266MHz for model 3, or 4. Set Core Clock
3067                  * Frequency to System Bus Frequency Ratio to 1 (bits
3068                  * 31:24) even though these are only valid for CPU
3069                  * models > 2, however guests may end up dividing or
3070                  * multiplying by zero otherwise.
3071                  */
3072         case MSR_EBC_FREQUENCY_ID:
3073                 msr_info->data = 1 << 24;
3074                 break;
3075         case MSR_IA32_APICBASE:
3076                 msr_info->data = kvm_get_apic_base(vcpu);
3077                 break;
3078         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3079                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3080                 break;
3081         case MSR_IA32_TSCDEADLINE:
3082                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3083                 break;
3084         case MSR_IA32_TSC_ADJUST:
3085                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3086                 break;
3087         case MSR_IA32_MISC_ENABLE:
3088                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3089                 break;
3090         case MSR_IA32_SMBASE:
3091                 if (!msr_info->host_initiated)
3092                         return 1;
3093                 msr_info->data = vcpu->arch.smbase;
3094                 break;
3095         case MSR_SMI_COUNT:
3096                 msr_info->data = vcpu->arch.smi_count;
3097                 break;
3098         case MSR_IA32_PERF_STATUS:
3099                 /* TSC increment by tick */
3100                 msr_info->data = 1000ULL;
3101                 /* CPU multiplier */
3102                 msr_info->data |= (((uint64_t)4ULL) << 40);
3103                 break;
3104         case MSR_EFER:
3105                 msr_info->data = vcpu->arch.efer;
3106                 break;
3107         case MSR_KVM_WALL_CLOCK:
3108         case MSR_KVM_WALL_CLOCK_NEW:
3109                 msr_info->data = vcpu->kvm->arch.wall_clock;
3110                 break;
3111         case MSR_KVM_SYSTEM_TIME:
3112         case MSR_KVM_SYSTEM_TIME_NEW:
3113                 msr_info->data = vcpu->arch.time;
3114                 break;
3115         case MSR_KVM_ASYNC_PF_EN:
3116                 msr_info->data = vcpu->arch.apf.msr_val;
3117                 break;
3118         case MSR_KVM_STEAL_TIME:
3119                 msr_info->data = vcpu->arch.st.msr_val;
3120                 break;
3121         case MSR_KVM_PV_EOI_EN:
3122                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3123                 break;
3124         case MSR_KVM_POLL_CONTROL:
3125                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3126                 break;
3127         case MSR_IA32_P5_MC_ADDR:
3128         case MSR_IA32_P5_MC_TYPE:
3129         case MSR_IA32_MCG_CAP:
3130         case MSR_IA32_MCG_CTL:
3131         case MSR_IA32_MCG_STATUS:
3132         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3133                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3134                                    msr_info->host_initiated);
3135         case MSR_IA32_XSS:
3136                 if (!msr_info->host_initiated &&
3137                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3138                         return 1;
3139                 msr_info->data = vcpu->arch.ia32_xss;
3140                 break;
3141         case MSR_K7_CLK_CTL:
3142                 /*
3143                  * Provide expected ramp-up count for K7. All other
3144                  * are set to zero, indicating minimum divisors for
3145                  * every field.
3146                  *
3147                  * This prevents guest kernels on AMD host with CPU
3148                  * type 6, model 8 and higher from exploding due to
3149                  * the rdmsr failing.
3150                  */
3151                 msr_info->data = 0x20000000;
3152                 break;
3153         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3154         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3155         case HV_X64_MSR_CRASH_CTL:
3156         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3157         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3158         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3159         case HV_X64_MSR_TSC_EMULATION_STATUS:
3160                 return kvm_hv_get_msr_common(vcpu,
3161                                              msr_info->index, &msr_info->data,
3162                                              msr_info->host_initiated);
3163                 break;
3164         case MSR_IA32_BBL_CR_CTL3:
3165                 /* This legacy MSR exists but isn't fully documented in current
3166                  * silicon.  It is however accessed by winxp in very narrow
3167                  * scenarios where it sets bit #19, itself documented as
3168                  * a "reserved" bit.  Best effort attempt to source coherent
3169                  * read data here should the balance of the register be
3170                  * interpreted by the guest:
3171                  *
3172                  * L2 cache control register 3: 64GB range, 256KB size,
3173                  * enabled, latency 0x1, configured
3174                  */
3175                 msr_info->data = 0xbe702111;
3176                 break;
3177         case MSR_AMD64_OSVW_ID_LENGTH:
3178                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3179                         return 1;
3180                 msr_info->data = vcpu->arch.osvw.length;
3181                 break;
3182         case MSR_AMD64_OSVW_STATUS:
3183                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3184                         return 1;
3185                 msr_info->data = vcpu->arch.osvw.status;
3186                 break;
3187         case MSR_PLATFORM_INFO:
3188                 if (!msr_info->host_initiated &&
3189                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3190                         return 1;
3191                 msr_info->data = vcpu->arch.msr_platform_info;
3192                 break;
3193         case MSR_MISC_FEATURES_ENABLES:
3194                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3195                 break;
3196         case MSR_K7_HWCR:
3197                 msr_info->data = vcpu->arch.msr_hwcr;
3198                 break;
3199         default:
3200                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3201                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3202                 if (!ignore_msrs) {
3203                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3204                                                msr_info->index);
3205                         return 1;
3206                 } else {
3207                         if (report_ignored_msrs)
3208                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3209                                         msr_info->index);
3210                         msr_info->data = 0;
3211                 }
3212                 break;
3213         }
3214         return 0;
3215 }
3216 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3217
3218 /*
3219  * Read or write a bunch of msrs. All parameters are kernel addresses.
3220  *
3221  * @return number of msrs set successfully.
3222  */
3223 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3224                     struct kvm_msr_entry *entries,
3225                     int (*do_msr)(struct kvm_vcpu *vcpu,
3226                                   unsigned index, u64 *data))
3227 {
3228         int i;
3229
3230         for (i = 0; i < msrs->nmsrs; ++i)
3231                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3232                         break;
3233
3234         return i;
3235 }
3236
3237 /*
3238  * Read or write a bunch of msrs. Parameters are user addresses.
3239  *
3240  * @return number of msrs set successfully.
3241  */
3242 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3243                   int (*do_msr)(struct kvm_vcpu *vcpu,
3244                                 unsigned index, u64 *data),
3245                   int writeback)
3246 {
3247         struct kvm_msrs msrs;
3248         struct kvm_msr_entry *entries;
3249         int r, n;
3250         unsigned size;
3251
3252         r = -EFAULT;
3253         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3254                 goto out;
3255
3256         r = -E2BIG;
3257         if (msrs.nmsrs >= MAX_IO_MSRS)
3258                 goto out;
3259
3260         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3261         entries = memdup_user(user_msrs->entries, size);
3262         if (IS_ERR(entries)) {
3263                 r = PTR_ERR(entries);
3264                 goto out;
3265         }
3266
3267         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3268         if (r < 0)
3269                 goto out_free;
3270
3271         r = -EFAULT;
3272         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3273                 goto out_free;
3274
3275         r = n;
3276
3277 out_free:
3278         kfree(entries);
3279 out:
3280         return r;
3281 }
3282
3283 static inline bool kvm_can_mwait_in_guest(void)
3284 {
3285         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3286                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3287                 boot_cpu_has(X86_FEATURE_ARAT);
3288 }
3289
3290 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3291 {
3292         int r = 0;
3293
3294         switch (ext) {
3295         case KVM_CAP_IRQCHIP:
3296         case KVM_CAP_HLT:
3297         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3298         case KVM_CAP_SET_TSS_ADDR:
3299         case KVM_CAP_EXT_CPUID:
3300         case KVM_CAP_EXT_EMUL_CPUID:
3301         case KVM_CAP_CLOCKSOURCE:
3302         case KVM_CAP_PIT:
3303         case KVM_CAP_NOP_IO_DELAY:
3304         case KVM_CAP_MP_STATE:
3305         case KVM_CAP_SYNC_MMU:
3306         case KVM_CAP_USER_NMI:
3307         case KVM_CAP_REINJECT_CONTROL:
3308         case KVM_CAP_IRQ_INJECT_STATUS:
3309         case KVM_CAP_IOEVENTFD:
3310         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3311         case KVM_CAP_PIT2:
3312         case KVM_CAP_PIT_STATE2:
3313         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3314         case KVM_CAP_XEN_HVM:
3315         case KVM_CAP_VCPU_EVENTS:
3316         case KVM_CAP_HYPERV:
3317         case KVM_CAP_HYPERV_VAPIC:
3318         case KVM_CAP_HYPERV_SPIN:
3319         case KVM_CAP_HYPERV_SYNIC:
3320         case KVM_CAP_HYPERV_SYNIC2:
3321         case KVM_CAP_HYPERV_VP_INDEX:
3322         case KVM_CAP_HYPERV_EVENTFD:
3323         case KVM_CAP_HYPERV_TLBFLUSH:
3324         case KVM_CAP_HYPERV_SEND_IPI:
3325         case KVM_CAP_HYPERV_CPUID:
3326         case KVM_CAP_PCI_SEGMENT:
3327         case KVM_CAP_DEBUGREGS:
3328         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3329         case KVM_CAP_XSAVE:
3330         case KVM_CAP_ASYNC_PF:
3331         case KVM_CAP_GET_TSC_KHZ:
3332         case KVM_CAP_KVMCLOCK_CTRL:
3333         case KVM_CAP_READONLY_MEM:
3334         case KVM_CAP_HYPERV_TIME:
3335         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3336         case KVM_CAP_TSC_DEADLINE_TIMER:
3337         case KVM_CAP_DISABLE_QUIRKS:
3338         case KVM_CAP_SET_BOOT_CPU_ID:
3339         case KVM_CAP_SPLIT_IRQCHIP:
3340         case KVM_CAP_IMMEDIATE_EXIT:
3341         case KVM_CAP_PMU_EVENT_FILTER:
3342         case KVM_CAP_GET_MSR_FEATURES:
3343         case KVM_CAP_MSR_PLATFORM_INFO:
3344         case KVM_CAP_EXCEPTION_PAYLOAD:
3345                 r = 1;
3346                 break;
3347         case KVM_CAP_SYNC_REGS:
3348                 r = KVM_SYNC_X86_VALID_FIELDS;
3349                 break;
3350         case KVM_CAP_ADJUST_CLOCK:
3351                 r = KVM_CLOCK_TSC_STABLE;
3352                 break;
3353         case KVM_CAP_X86_DISABLE_EXITS:
3354                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3355                       KVM_X86_DISABLE_EXITS_CSTATE;
3356                 if(kvm_can_mwait_in_guest())
3357                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3358                 break;
3359         case KVM_CAP_X86_SMM:
3360                 /* SMBASE is usually relocated above 1M on modern chipsets,
3361                  * and SMM handlers might indeed rely on 4G segment limits,
3362                  * so do not report SMM to be available if real mode is
3363                  * emulated via vm86 mode.  Still, do not go to great lengths
3364                  * to avoid userspace's usage of the feature, because it is a
3365                  * fringe case that is not enabled except via specific settings
3366                  * of the module parameters.
3367                  */
3368                 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3369                 break;
3370         case KVM_CAP_VAPIC:
3371                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3372                 break;
3373         case KVM_CAP_NR_VCPUS:
3374                 r = KVM_SOFT_MAX_VCPUS;
3375                 break;
3376         case KVM_CAP_MAX_VCPUS:
3377                 r = KVM_MAX_VCPUS;
3378                 break;
3379         case KVM_CAP_MAX_VCPU_ID:
3380                 r = KVM_MAX_VCPU_ID;
3381                 break;
3382         case KVM_CAP_PV_MMU:    /* obsolete */
3383                 r = 0;
3384                 break;
3385         case KVM_CAP_MCE:
3386                 r = KVM_MAX_MCE_BANKS;
3387                 break;
3388         case KVM_CAP_XCRS:
3389                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3390                 break;
3391         case KVM_CAP_TSC_CONTROL:
3392                 r = kvm_has_tsc_control;
3393                 break;
3394         case KVM_CAP_X2APIC_API:
3395                 r = KVM_X2APIC_API_VALID_FLAGS;
3396                 break;
3397         case KVM_CAP_NESTED_STATE:
3398                 r = kvm_x86_ops->get_nested_state ?
3399                         kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3400                 break;
3401         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3402                 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3403                 break;
3404         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3405                 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3406                 break;
3407         default:
3408                 break;
3409         }
3410         return r;
3411
3412 }
3413
3414 long kvm_arch_dev_ioctl(struct file *filp,
3415                         unsigned int ioctl, unsigned long arg)
3416 {
3417         void __user *argp = (void __user *)arg;
3418         long r;
3419
3420         switch (ioctl) {
3421         case KVM_GET_MSR_INDEX_LIST: {
3422                 struct kvm_msr_list __user *user_msr_list = argp;
3423                 struct kvm_msr_list msr_list;
3424                 unsigned n;
3425
3426                 r = -EFAULT;
3427                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3428                         goto out;
3429                 n = msr_list.nmsrs;
3430                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3431                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3432                         goto out;
3433                 r = -E2BIG;
3434                 if (n < msr_list.nmsrs)
3435                         goto out;
3436                 r = -EFAULT;
3437                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3438                                  num_msrs_to_save * sizeof(u32)))
3439                         goto out;
3440                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3441                                  &emulated_msrs,
3442                                  num_emulated_msrs * sizeof(u32)))
3443                         goto out;
3444                 r = 0;
3445                 break;
3446         }
3447         case KVM_GET_SUPPORTED_CPUID:
3448         case KVM_GET_EMULATED_CPUID: {
3449                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3450                 struct kvm_cpuid2 cpuid;
3451
3452                 r = -EFAULT;
3453                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3454                         goto out;
3455
3456                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3457                                             ioctl);
3458                 if (r)
3459                         goto out;
3460
3461                 r = -EFAULT;
3462                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3463                         goto out;
3464                 r = 0;
3465                 break;
3466         }
3467         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3468                 r = -EFAULT;
3469                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3470                                  sizeof(kvm_mce_cap_supported)))
3471                         goto out;
3472                 r = 0;
3473                 break;
3474         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3475                 struct kvm_msr_list __user *user_msr_list = argp;
3476                 struct kvm_msr_list msr_list;
3477                 unsigned int n;
3478
3479                 r = -EFAULT;
3480                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3481                         goto out;
3482                 n = msr_list.nmsrs;
3483                 msr_list.nmsrs = num_msr_based_features;
3484                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3485                         goto out;
3486                 r = -E2BIG;
3487                 if (n < msr_list.nmsrs)
3488                         goto out;
3489                 r = -EFAULT;
3490                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3491                                  num_msr_based_features * sizeof(u32)))
3492                         goto out;
3493                 r = 0;
3494                 break;
3495         }
3496         case KVM_GET_MSRS:
3497                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3498                 break;
3499         }
3500         default:
3501                 r = -EINVAL;
3502         }
3503 out:
3504         return r;
3505 }
3506
3507 static void wbinvd_ipi(void *garbage)
3508 {
3509         wbinvd();
3510 }
3511
3512 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3513 {
3514         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3515 }
3516
3517 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3518 {
3519         /* Address WBINVD may be executed by guest */
3520         if (need_emulate_wbinvd(vcpu)) {
3521                 if (kvm_x86_ops->has_wbinvd_exit())
3522                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3523                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3524                         smp_call_function_single(vcpu->cpu,
3525                                         wbinvd_ipi, NULL, 1);
3526         }
3527
3528         kvm_x86_ops->vcpu_load(vcpu, cpu);
3529
3530         /* Apply any externally detected TSC adjustments (due to suspend) */
3531         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3532                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3533                 vcpu->arch.tsc_offset_adjustment = 0;
3534                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3535         }
3536
3537         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3538                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3539                                 rdtsc() - vcpu->arch.last_host_tsc;
3540                 if (tsc_delta < 0)
3541                         mark_tsc_unstable("KVM discovered backwards TSC");
3542
3543                 if (kvm_check_tsc_unstable()) {
3544                         u64 offset = kvm_compute_tsc_offset(vcpu,
3545                                                 vcpu->arch.last_guest_tsc);
3546                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3547                         vcpu->arch.tsc_catchup = 1;
3548                 }
3549
3550                 if (kvm_lapic_hv_timer_in_use(vcpu))
3551                         kvm_lapic_restart_hv_timer(vcpu);
3552
3553                 /*
3554                  * On a host with synchronized TSC, there is no need to update
3555                  * kvmclock on vcpu->cpu migration
3556                  */
3557                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3558                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3559                 if (vcpu->cpu != cpu)
3560                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3561                 vcpu->cpu = cpu;
3562         }
3563
3564         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3565 }
3566
3567 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3568 {
3569         struct kvm_host_map map;
3570         struct kvm_steal_time *st;
3571
3572         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3573                 return;
3574
3575         if (vcpu->arch.st.preempted)
3576                 return;
3577
3578         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3579                         &vcpu->arch.st.cache, true))
3580                 return;
3581
3582         st = map.hva +
3583                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3584
3585         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3586
3587         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3588 }
3589
3590 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3591 {
3592         int idx;
3593
3594         if (vcpu->preempted)
3595                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3596
3597         /*
3598          * Disable page faults because we're in atomic context here.
3599          * kvm_write_guest_offset_cached() would call might_fault()
3600          * that relies on pagefault_disable() to tell if there's a
3601          * bug. NOTE: the write to guest memory may not go through if
3602          * during postcopy live migration or if there's heavy guest
3603          * paging.
3604          */
3605         pagefault_disable();
3606         /*
3607          * kvm_memslots() will be called by
3608          * kvm_write_guest_offset_cached() so take the srcu lock.
3609          */
3610         idx = srcu_read_lock(&vcpu->kvm->srcu);
3611         kvm_steal_time_set_preempted(vcpu);
3612         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3613         pagefault_enable();
3614         kvm_x86_ops->vcpu_put(vcpu);
3615         vcpu->arch.last_host_tsc = rdtsc();
3616         /*
3617          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3618          * on every vmexit, but if not, we might have a stale dr6 from the
3619          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3620          */
3621         set_debugreg(0, 6);
3622 }
3623
3624 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3625                                     struct kvm_lapic_state *s)
3626 {
3627         if (vcpu->arch.apicv_active)
3628                 kvm_x86_ops->sync_pir_to_irr(vcpu);
3629
3630         return kvm_apic_get_state(vcpu, s);
3631 }
3632
3633 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3634                                     struct kvm_lapic_state *s)
3635 {
3636         int r;
3637
3638         r = kvm_apic_set_state(vcpu, s);
3639         if (r)
3640                 return r;
3641         update_cr8_intercept(vcpu);
3642
3643         return 0;
3644 }
3645
3646 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3647 {
3648         return (!lapic_in_kernel(vcpu) ||
3649                 kvm_apic_accept_pic_intr(vcpu));
3650 }
3651
3652 /*
3653  * if userspace requested an interrupt window, check that the
3654  * interrupt window is open.
3655  *
3656  * No need to exit to userspace if we already have an interrupt queued.
3657  */
3658 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3659 {
3660         return kvm_arch_interrupt_allowed(vcpu) &&
3661                 !kvm_cpu_has_interrupt(vcpu) &&
3662                 !kvm_event_needs_reinjection(vcpu) &&
3663                 kvm_cpu_accept_dm_intr(vcpu);
3664 }
3665
3666 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3667                                     struct kvm_interrupt *irq)
3668 {
3669         if (irq->irq >= KVM_NR_INTERRUPTS)
3670                 return -EINVAL;
3671
3672         if (!irqchip_in_kernel(vcpu->kvm)) {
3673                 kvm_queue_interrupt(vcpu, irq->irq, false);
3674                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3675                 return 0;
3676         }
3677
3678         /*
3679          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3680          * fail for in-kernel 8259.
3681          */
3682         if (pic_in_kernel(vcpu->kvm))
3683                 return -ENXIO;
3684
3685         if (vcpu->arch.pending_external_vector != -1)
3686                 return -EEXIST;
3687
3688         vcpu->arch.pending_external_vector = irq->irq;
3689         kvm_make_request(KVM_REQ_EVENT, vcpu);
3690         return 0;
3691 }
3692
3693 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3694 {
3695         kvm_inject_nmi(vcpu);
3696
3697         return 0;
3698 }
3699
3700 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3701 {
3702         kvm_make_request(KVM_REQ_SMI, vcpu);
3703
3704         return 0;
3705 }
3706
3707 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3708                                            struct kvm_tpr_access_ctl *tac)
3709 {
3710         if (tac->flags)
3711                 return -EINVAL;
3712         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3713         return 0;
3714 }
3715
3716 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3717                                         u64 mcg_cap)
3718 {
3719         int r;
3720         unsigned bank_num = mcg_cap & 0xff, bank;
3721
3722         r = -EINVAL;
3723         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3724                 goto out;
3725         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3726                 goto out;
3727         r = 0;
3728         vcpu->arch.mcg_cap = mcg_cap;
3729         /* Init IA32_MCG_CTL to all 1s */
3730         if (mcg_cap & MCG_CTL_P)
3731                 vcpu->arch.mcg_ctl = ~(u64)0;
3732         /* Init IA32_MCi_CTL to all 1s */
3733         for (bank = 0; bank < bank_num; bank++)
3734                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3735
3736         kvm_x86_ops->setup_mce(vcpu);
3737 out:
3738         return r;
3739 }
3740
3741 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3742                                       struct kvm_x86_mce *mce)
3743 {
3744         u64 mcg_cap = vcpu->arch.mcg_cap;
3745         unsigned bank_num = mcg_cap & 0xff;
3746         u64 *banks = vcpu->arch.mce_banks;
3747
3748         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3749                 return -EINVAL;
3750         /*
3751          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3752          * reporting is disabled
3753          */
3754         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3755             vcpu->arch.mcg_ctl != ~(u64)0)
3756                 return 0;
3757         banks += 4 * mce->bank;
3758         /*
3759          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3760          * reporting is disabled for the bank
3761          */
3762         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3763                 return 0;
3764         if (mce->status & MCI_STATUS_UC) {
3765                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3766                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3767                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3768                         return 0;
3769                 }
3770                 if (banks[1] & MCI_STATUS_VAL)
3771                         mce->status |= MCI_STATUS_OVER;
3772                 banks[2] = mce->addr;
3773                 banks[3] = mce->misc;
3774                 vcpu->arch.mcg_status = mce->mcg_status;
3775                 banks[1] = mce->status;
3776                 kvm_queue_exception(vcpu, MC_VECTOR);
3777         } else if (!(banks[1] & MCI_STATUS_VAL)
3778                    || !(banks[1] & MCI_STATUS_UC)) {
3779                 if (banks[1] & MCI_STATUS_VAL)
3780                         mce->status |= MCI_STATUS_OVER;
3781                 banks[2] = mce->addr;
3782                 banks[3] = mce->misc;
3783                 banks[1] = mce->status;
3784         } else
3785                 banks[1] |= MCI_STATUS_OVER;
3786         return 0;
3787 }
3788
3789 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3790                                                struct kvm_vcpu_events *events)
3791 {
3792         process_nmi(vcpu);
3793
3794         /*
3795          * In guest mode, payload delivery should be deferred,
3796          * so that the L1 hypervisor can intercept #PF before
3797          * CR2 is modified (or intercept #DB before DR6 is
3798          * modified under nVMX). Unless the per-VM capability,
3799          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3800          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3801          * opportunistically defer the exception payload, deliver it if the
3802          * capability hasn't been requested before processing a
3803          * KVM_GET_VCPU_EVENTS.
3804          */
3805         if (!vcpu->kvm->arch.exception_payload_enabled &&
3806             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3807                 kvm_deliver_exception_payload(vcpu);
3808
3809         /*
3810          * The API doesn't provide the instruction length for software
3811          * exceptions, so don't report them. As long as the guest RIP
3812          * isn't advanced, we should expect to encounter the exception
3813          * again.
3814          */
3815         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3816                 events->exception.injected = 0;
3817                 events->exception.pending = 0;
3818         } else {
3819                 events->exception.injected = vcpu->arch.exception.injected;
3820                 events->exception.pending = vcpu->arch.exception.pending;
3821                 /*
3822                  * For ABI compatibility, deliberately conflate
3823                  * pending and injected exceptions when
3824                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3825                  */
3826                 if (!vcpu->kvm->arch.exception_payload_enabled)
3827                         events->exception.injected |=
3828                                 vcpu->arch.exception.pending;
3829         }
3830         events->exception.nr = vcpu->arch.exception.nr;
3831         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3832         events->exception.error_code = vcpu->arch.exception.error_code;
3833         events->exception_has_payload = vcpu->arch.exception.has_payload;
3834         events->exception_payload = vcpu->arch.exception.payload;
3835
3836         events->interrupt.injected =
3837                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3838         events->interrupt.nr = vcpu->arch.interrupt.nr;
3839         events->interrupt.soft = 0;
3840         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3841
3842         events->nmi.injected = vcpu->arch.nmi_injected;
3843         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3844         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3845         events->nmi.pad = 0;
3846
3847         events->sipi_vector = 0; /* never valid when reporting to user space */
3848
3849         events->smi.smm = is_smm(vcpu);
3850         events->smi.pending = vcpu->arch.smi_pending;
3851         events->smi.smm_inside_nmi =
3852                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3853         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3854
3855         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3856                          | KVM_VCPUEVENT_VALID_SHADOW
3857                          | KVM_VCPUEVENT_VALID_SMM);
3858         if (vcpu->kvm->arch.exception_payload_enabled)
3859                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3860
3861         memset(&events->reserved, 0, sizeof(events->reserved));
3862 }
3863
3864 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3865
3866 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3867                                               struct kvm_vcpu_events *events)
3868 {
3869         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3870                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3871                               | KVM_VCPUEVENT_VALID_SHADOW
3872                               | KVM_VCPUEVENT_VALID_SMM
3873                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3874                 return -EINVAL;
3875
3876         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3877                 if (!vcpu->kvm->arch.exception_payload_enabled)
3878                         return -EINVAL;
3879                 if (events->exception.pending)
3880                         events->exception.injected = 0;
3881                 else
3882                         events->exception_has_payload = 0;
3883         } else {
3884                 events->exception.pending = 0;
3885                 events->exception_has_payload = 0;
3886         }
3887
3888         if ((events->exception.injected || events->exception.pending) &&
3889             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3890                 return -EINVAL;
3891
3892         /* INITs are latched while in SMM */
3893         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3894             (events->smi.smm || events->smi.pending) &&
3895             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3896                 return -EINVAL;
3897
3898         process_nmi(vcpu);
3899         vcpu->arch.exception.injected = events->exception.injected;
3900         vcpu->arch.exception.pending = events->exception.pending;
3901         vcpu->arch.exception.nr = events->exception.nr;
3902         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3903         vcpu->arch.exception.error_code = events->exception.error_code;
3904         vcpu->arch.exception.has_payload = events->exception_has_payload;
3905         vcpu->arch.exception.payload = events->exception_payload;
3906
3907         vcpu->arch.interrupt.injected = events->interrupt.injected;
3908         vcpu->arch.interrupt.nr = events->interrupt.nr;
3909         vcpu->arch.interrupt.soft = events->interrupt.soft;
3910         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3911                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3912                                                   events->interrupt.shadow);
3913
3914         vcpu->arch.nmi_injected = events->nmi.injected;
3915         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3916                 vcpu->arch.nmi_pending = events->nmi.pending;
3917         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3918
3919         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3920             lapic_in_kernel(vcpu))
3921                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3922
3923         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3924                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3925                         if (events->smi.smm)
3926                                 vcpu->arch.hflags |= HF_SMM_MASK;
3927                         else
3928                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
3929                         kvm_smm_changed(vcpu);
3930                 }
3931
3932                 vcpu->arch.smi_pending = events->smi.pending;
3933
3934                 if (events->smi.smm) {
3935                         if (events->smi.smm_inside_nmi)
3936                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3937                         else
3938                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3939                 }
3940
3941                 if (lapic_in_kernel(vcpu)) {
3942                         if (events->smi.latched_init)
3943                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3944                         else
3945                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3946                 }
3947         }
3948
3949         kvm_make_request(KVM_REQ_EVENT, vcpu);
3950
3951         return 0;
3952 }
3953
3954 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3955                                              struct kvm_debugregs *dbgregs)
3956 {
3957         unsigned long val;
3958
3959         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3960         kvm_get_dr(vcpu, 6, &val);
3961         dbgregs->dr6 = val;
3962         dbgregs->dr7 = vcpu->arch.dr7;
3963         dbgregs->flags = 0;
3964         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3965 }
3966
3967 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3968                                             struct kvm_debugregs *dbgregs)
3969 {
3970         if (dbgregs->flags)
3971                 return -EINVAL;
3972
3973         if (dbgregs->dr6 & ~0xffffffffull)
3974                 return -EINVAL;
3975         if (dbgregs->dr7 & ~0xffffffffull)
3976                 return -EINVAL;
3977
3978         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3979         kvm_update_dr0123(vcpu);
3980         vcpu->arch.dr6 = dbgregs->dr6;
3981         kvm_update_dr6(vcpu);
3982         vcpu->arch.dr7 = dbgregs->dr7;
3983         kvm_update_dr7(vcpu);
3984
3985         return 0;
3986 }
3987
3988 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3989
3990 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3991 {
3992         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3993         u64 xstate_bv = xsave->header.xfeatures;
3994         u64 valid;
3995
3996         /*
3997          * Copy legacy XSAVE area, to avoid complications with CPUID
3998          * leaves 0 and 1 in the loop below.
3999          */
4000         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4001
4002         /* Set XSTATE_BV */
4003         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4004         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4005
4006         /*
4007          * Copy each region from the possibly compacted offset to the
4008          * non-compacted offset.
4009          */
4010         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4011         while (valid) {
4012                 u64 xfeature_mask = valid & -valid;
4013                 int xfeature_nr = fls64(xfeature_mask) - 1;
4014                 void *src = get_xsave_addr(xsave, xfeature_nr);
4015
4016                 if (src) {
4017                         u32 size, offset, ecx, edx;
4018                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4019                                     &size, &offset, &ecx, &edx);
4020                         if (xfeature_nr == XFEATURE_PKRU)
4021                                 memcpy(dest + offset, &vcpu->arch.pkru,
4022                                        sizeof(vcpu->arch.pkru));
4023                         else
4024                                 memcpy(dest + offset, src, size);
4025
4026                 }
4027
4028                 valid -= xfeature_mask;
4029         }
4030 }
4031
4032 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4033 {
4034         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4035         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4036         u64 valid;
4037
4038         /*
4039          * Copy legacy XSAVE area, to avoid complications with CPUID
4040          * leaves 0 and 1 in the loop below.
4041          */
4042         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4043
4044         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4045         xsave->header.xfeatures = xstate_bv;
4046         if (boot_cpu_has(X86_FEATURE_XSAVES))
4047                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4048
4049         /*
4050          * Copy each region from the non-compacted offset to the
4051          * possibly compacted offset.
4052          */
4053         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4054         while (valid) {
4055                 u64 xfeature_mask = valid & -valid;
4056                 int xfeature_nr = fls64(xfeature_mask) - 1;
4057                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4058
4059                 if (dest) {
4060                         u32 size, offset, ecx, edx;
4061                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4062                                     &size, &offset, &ecx, &edx);
4063                         if (xfeature_nr == XFEATURE_PKRU)
4064                                 memcpy(&vcpu->arch.pkru, src + offset,
4065                                        sizeof(vcpu->arch.pkru));
4066                         else
4067                                 memcpy(dest, src + offset, size);
4068                 }
4069
4070                 valid -= xfeature_mask;
4071         }
4072 }
4073
4074 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4075                                          struct kvm_xsave *guest_xsave)
4076 {
4077         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4078                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4079                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4080         } else {
4081                 memcpy(guest_xsave->region,
4082                         &vcpu->arch.guest_fpu->state.fxsave,
4083                         sizeof(struct fxregs_state));
4084                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4085                         XFEATURE_MASK_FPSSE;
4086         }
4087 }
4088
4089 #define XSAVE_MXCSR_OFFSET 24
4090
4091 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4092                                         struct kvm_xsave *guest_xsave)
4093 {
4094         u64 xstate_bv =
4095                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4096         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4097
4098         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4099                 /*
4100                  * Here we allow setting states that are not present in
4101                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4102                  * with old userspace.
4103                  */
4104                 if (xstate_bv & ~kvm_supported_xcr0() ||
4105                         mxcsr & ~mxcsr_feature_mask)
4106                         return -EINVAL;
4107                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4108         } else {
4109                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4110                         mxcsr & ~mxcsr_feature_mask)
4111                         return -EINVAL;
4112                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4113                         guest_xsave->region, sizeof(struct fxregs_state));
4114         }
4115         return 0;
4116 }
4117
4118 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4119                                         struct kvm_xcrs *guest_xcrs)
4120 {
4121         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4122                 guest_xcrs->nr_xcrs = 0;
4123                 return;
4124         }
4125
4126         guest_xcrs->nr_xcrs = 1;
4127         guest_xcrs->flags = 0;
4128         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4129         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4130 }
4131
4132 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4133                                        struct kvm_xcrs *guest_xcrs)
4134 {
4135         int i, r = 0;
4136
4137         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4138                 return -EINVAL;
4139
4140         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4141                 return -EINVAL;
4142
4143         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4144                 /* Only support XCR0 currently */
4145                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4146                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4147                                 guest_xcrs->xcrs[i].value);
4148                         break;
4149                 }
4150         if (r)
4151                 r = -EINVAL;
4152         return r;
4153 }
4154
4155 /*
4156  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4157  * stopped by the hypervisor.  This function will be called from the host only.
4158  * EINVAL is returned when the host attempts to set the flag for a guest that
4159  * does not support pv clocks.
4160  */
4161 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4162 {
4163         if (!vcpu->arch.pv_time_enabled)
4164                 return -EINVAL;
4165         vcpu->arch.pvclock_set_guest_stopped_request = true;
4166         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4167         return 0;
4168 }
4169
4170 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4171                                      struct kvm_enable_cap *cap)
4172 {
4173         int r;
4174         uint16_t vmcs_version;
4175         void __user *user_ptr;
4176
4177         if (cap->flags)
4178                 return -EINVAL;
4179
4180         switch (cap->cap) {
4181         case KVM_CAP_HYPERV_SYNIC2:
4182                 if (cap->args[0])
4183                         return -EINVAL;
4184                 /* fall through */
4185
4186         case KVM_CAP_HYPERV_SYNIC:
4187                 if (!irqchip_in_kernel(vcpu->kvm))
4188                         return -EINVAL;
4189                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4190                                              KVM_CAP_HYPERV_SYNIC2);
4191         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4192                 if (!kvm_x86_ops->nested_enable_evmcs)
4193                         return -ENOTTY;
4194                 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4195                 if (!r) {
4196                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4197                         if (copy_to_user(user_ptr, &vmcs_version,
4198                                          sizeof(vmcs_version)))
4199                                 r = -EFAULT;
4200                 }
4201                 return r;
4202         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4203                 if (!kvm_x86_ops->enable_direct_tlbflush)
4204                         return -ENOTTY;
4205
4206                 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4207
4208         default:
4209                 return -EINVAL;
4210         }
4211 }
4212
4213 long kvm_arch_vcpu_ioctl(struct file *filp,
4214                          unsigned int ioctl, unsigned long arg)
4215 {
4216         struct kvm_vcpu *vcpu = filp->private_data;
4217         void __user *argp = (void __user *)arg;
4218         int r;
4219         union {
4220                 struct kvm_lapic_state *lapic;
4221                 struct kvm_xsave *xsave;
4222                 struct kvm_xcrs *xcrs;
4223                 void *buffer;
4224         } u;
4225
4226         vcpu_load(vcpu);
4227
4228         u.buffer = NULL;
4229         switch (ioctl) {
4230         case KVM_GET_LAPIC: {
4231                 r = -EINVAL;
4232                 if (!lapic_in_kernel(vcpu))
4233                         goto out;
4234                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4235                                 GFP_KERNEL_ACCOUNT);
4236
4237                 r = -ENOMEM;
4238                 if (!u.lapic)
4239                         goto out;
4240                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4241                 if (r)
4242                         goto out;
4243                 r = -EFAULT;
4244                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4245                         goto out;
4246                 r = 0;
4247                 break;
4248         }
4249         case KVM_SET_LAPIC: {
4250                 r = -EINVAL;
4251                 if (!lapic_in_kernel(vcpu))
4252                         goto out;
4253                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4254                 if (IS_ERR(u.lapic)) {
4255                         r = PTR_ERR(u.lapic);
4256                         goto out_nofree;
4257                 }
4258
4259                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4260                 break;
4261         }
4262         case KVM_INTERRUPT: {
4263                 struct kvm_interrupt irq;
4264
4265                 r = -EFAULT;
4266                 if (copy_from_user(&irq, argp, sizeof(irq)))
4267                         goto out;
4268                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4269                 break;
4270         }
4271         case KVM_NMI: {
4272                 r = kvm_vcpu_ioctl_nmi(vcpu);
4273                 break;
4274         }
4275         case KVM_SMI: {
4276                 r = kvm_vcpu_ioctl_smi(vcpu);
4277                 break;
4278         }
4279         case KVM_SET_CPUID: {
4280                 struct kvm_cpuid __user *cpuid_arg = argp;
4281                 struct kvm_cpuid cpuid;
4282
4283                 r = -EFAULT;
4284                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4285                         goto out;
4286                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4287                 break;
4288         }
4289         case KVM_SET_CPUID2: {
4290                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4291                 struct kvm_cpuid2 cpuid;
4292
4293                 r = -EFAULT;
4294                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4295                         goto out;
4296                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4297                                               cpuid_arg->entries);
4298                 break;
4299         }
4300         case KVM_GET_CPUID2: {
4301                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4302                 struct kvm_cpuid2 cpuid;
4303
4304                 r = -EFAULT;
4305                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4306                         goto out;
4307                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4308                                               cpuid_arg->entries);
4309                 if (r)
4310                         goto out;
4311                 r = -EFAULT;
4312                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4313                         goto out;
4314                 r = 0;
4315                 break;
4316         }
4317         case KVM_GET_MSRS: {
4318                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4319                 r = msr_io(vcpu, argp, do_get_msr, 1);
4320                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4321                 break;
4322         }
4323         case KVM_SET_MSRS: {
4324                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4325                 r = msr_io(vcpu, argp, do_set_msr, 0);
4326                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4327                 break;
4328         }
4329         case KVM_TPR_ACCESS_REPORTING: {
4330                 struct kvm_tpr_access_ctl tac;
4331
4332                 r = -EFAULT;
4333                 if (copy_from_user(&tac, argp, sizeof(tac)))
4334                         goto out;
4335                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4336                 if (r)
4337                         goto out;
4338                 r = -EFAULT;
4339                 if (copy_to_user(argp, &tac, sizeof(tac)))
4340                         goto out;
4341                 r = 0;
4342                 break;
4343         };
4344         case KVM_SET_VAPIC_ADDR: {
4345                 struct kvm_vapic_addr va;
4346                 int idx;
4347
4348                 r = -EINVAL;
4349                 if (!lapic_in_kernel(vcpu))
4350                         goto out;
4351                 r = -EFAULT;
4352                 if (copy_from_user(&va, argp, sizeof(va)))
4353                         goto out;
4354                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4355                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4356                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4357                 break;
4358         }
4359         case KVM_X86_SETUP_MCE: {
4360                 u64 mcg_cap;
4361
4362                 r = -EFAULT;
4363                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4364                         goto out;
4365                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4366                 break;
4367         }
4368         case KVM_X86_SET_MCE: {
4369                 struct kvm_x86_mce mce;
4370
4371                 r = -EFAULT;
4372                 if (copy_from_user(&mce, argp, sizeof(mce)))
4373                         goto out;
4374                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4375                 break;
4376         }
4377         case KVM_GET_VCPU_EVENTS: {
4378                 struct kvm_vcpu_events events;
4379
4380                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4381
4382                 r = -EFAULT;
4383                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4384                         break;
4385                 r = 0;
4386                 break;
4387         }
4388         case KVM_SET_VCPU_EVENTS: {
4389                 struct kvm_vcpu_events events;
4390
4391                 r = -EFAULT;
4392                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4393                         break;
4394
4395                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4396                 break;
4397         }
4398         case KVM_GET_DEBUGREGS: {
4399                 struct kvm_debugregs dbgregs;
4400
4401                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4402
4403                 r = -EFAULT;
4404                 if (copy_to_user(argp, &dbgregs,
4405                                  sizeof(struct kvm_debugregs)))
4406                         break;
4407                 r = 0;
4408                 break;
4409         }
4410         case KVM_SET_DEBUGREGS: {
4411                 struct kvm_debugregs dbgregs;
4412
4413                 r = -EFAULT;
4414                 if (copy_from_user(&dbgregs, argp,
4415                                    sizeof(struct kvm_debugregs)))
4416                         break;
4417
4418                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4419                 break;
4420         }
4421         case KVM_GET_XSAVE: {
4422                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4423                 r = -ENOMEM;
4424                 if (!u.xsave)
4425                         break;
4426
4427                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4428
4429                 r = -EFAULT;
4430                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4431                         break;
4432                 r = 0;
4433                 break;
4434         }
4435         case KVM_SET_XSAVE: {
4436                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4437                 if (IS_ERR(u.xsave)) {
4438                         r = PTR_ERR(u.xsave);
4439                         goto out_nofree;
4440                 }
4441
4442                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4443                 break;
4444         }
4445         case KVM_GET_XCRS: {
4446                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4447                 r = -ENOMEM;
4448                 if (!u.xcrs)
4449                         break;
4450
4451                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4452
4453                 r = -EFAULT;
4454                 if (copy_to_user(argp, u.xcrs,
4455                                  sizeof(struct kvm_xcrs)))
4456                         break;
4457                 r = 0;
4458                 break;
4459         }
4460         case KVM_SET_XCRS: {
4461                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4462                 if (IS_ERR(u.xcrs)) {
4463                         r = PTR_ERR(u.xcrs);
4464                         goto out_nofree;
4465                 }
4466
4467                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4468                 break;
4469         }
4470         case KVM_SET_TSC_KHZ: {
4471                 u32 user_tsc_khz;
4472
4473                 r = -EINVAL;
4474                 user_tsc_khz = (u32)arg;
4475
4476                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4477                         goto out;
4478
4479                 if (user_tsc_khz == 0)
4480                         user_tsc_khz = tsc_khz;
4481
4482                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4483                         r = 0;
4484
4485                 goto out;
4486         }
4487         case KVM_GET_TSC_KHZ: {
4488                 r = vcpu->arch.virtual_tsc_khz;
4489                 goto out;
4490         }
4491         case KVM_KVMCLOCK_CTRL: {
4492                 r = kvm_set_guest_paused(vcpu);
4493                 goto out;
4494         }
4495         case KVM_ENABLE_CAP: {
4496                 struct kvm_enable_cap cap;
4497
4498                 r = -EFAULT;
4499                 if (copy_from_user(&cap, argp, sizeof(cap)))
4500                         goto out;
4501                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4502                 break;
4503         }
4504         case KVM_GET_NESTED_STATE: {
4505                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4506                 u32 user_data_size;
4507
4508                 r = -EINVAL;
4509                 if (!kvm_x86_ops->get_nested_state)
4510                         break;
4511
4512                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4513                 r = -EFAULT;
4514                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4515                         break;
4516
4517                 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4518                                                   user_data_size);
4519                 if (r < 0)
4520                         break;
4521
4522                 if (r > user_data_size) {
4523                         if (put_user(r, &user_kvm_nested_state->size))
4524                                 r = -EFAULT;
4525                         else
4526                                 r = -E2BIG;
4527                         break;
4528                 }
4529
4530                 r = 0;
4531                 break;
4532         }
4533         case KVM_SET_NESTED_STATE: {
4534                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4535                 struct kvm_nested_state kvm_state;
4536                 int idx;
4537
4538                 r = -EINVAL;
4539                 if (!kvm_x86_ops->set_nested_state)
4540                         break;
4541
4542                 r = -EFAULT;
4543                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4544                         break;
4545
4546                 r = -EINVAL;
4547                 if (kvm_state.size < sizeof(kvm_state))
4548                         break;
4549
4550                 if (kvm_state.flags &
4551                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4552                       | KVM_STATE_NESTED_EVMCS))
4553                         break;
4554
4555                 /* nested_run_pending implies guest_mode.  */
4556                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4557                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4558                         break;
4559
4560                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4561                 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4562                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4563                 break;
4564         }
4565         case KVM_GET_SUPPORTED_HV_CPUID: {
4566                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4567                 struct kvm_cpuid2 cpuid;
4568
4569                 r = -EFAULT;
4570                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4571                         goto out;
4572
4573                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4574                                                 cpuid_arg->entries);
4575                 if (r)
4576                         goto out;
4577
4578                 r = -EFAULT;
4579                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4580                         goto out;
4581                 r = 0;
4582                 break;
4583         }
4584         default:
4585                 r = -EINVAL;
4586         }
4587 out:
4588         kfree(u.buffer);
4589 out_nofree:
4590         vcpu_put(vcpu);
4591         return r;
4592 }
4593
4594 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4595 {
4596         return VM_FAULT_SIGBUS;
4597 }
4598
4599 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4600 {
4601         int ret;
4602
4603         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4604                 return -EINVAL;
4605         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4606         return ret;
4607 }
4608
4609 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4610                                               u64 ident_addr)
4611 {
4612         return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4613 }
4614
4615 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4616                                          unsigned long kvm_nr_mmu_pages)
4617 {
4618         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4619                 return -EINVAL;
4620
4621         mutex_lock(&kvm->slots_lock);
4622
4623         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4624         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4625
4626         mutex_unlock(&kvm->slots_lock);
4627         return 0;
4628 }
4629
4630 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4631 {
4632         return kvm->arch.n_max_mmu_pages;
4633 }
4634
4635 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4636 {
4637         struct kvm_pic *pic = kvm->arch.vpic;
4638         int r;
4639
4640         r = 0;
4641         switch (chip->chip_id) {
4642         case KVM_IRQCHIP_PIC_MASTER:
4643                 memcpy(&chip->chip.pic, &pic->pics[0],
4644                         sizeof(struct kvm_pic_state));
4645                 break;
4646         case KVM_IRQCHIP_PIC_SLAVE:
4647                 memcpy(&chip->chip.pic, &pic->pics[1],
4648                         sizeof(struct kvm_pic_state));
4649                 break;
4650         case KVM_IRQCHIP_IOAPIC:
4651                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4652                 break;
4653         default:
4654                 r = -EINVAL;
4655                 break;
4656         }
4657         return r;
4658 }
4659
4660 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4661 {
4662         struct kvm_pic *pic = kvm->arch.vpic;
4663         int r;
4664
4665         r = 0;
4666         switch (chip->chip_id) {
4667         case KVM_IRQCHIP_PIC_MASTER:
4668                 spin_lock(&pic->lock);
4669                 memcpy(&pic->pics[0], &chip->chip.pic,
4670                         sizeof(struct kvm_pic_state));
4671                 spin_unlock(&pic->lock);
4672                 break;
4673         case KVM_IRQCHIP_PIC_SLAVE:
4674                 spin_lock(&pic->lock);
4675                 memcpy(&pic->pics[1], &chip->chip.pic,
4676                         sizeof(struct kvm_pic_state));
4677                 spin_unlock(&pic->lock);
4678                 break;
4679         case KVM_IRQCHIP_IOAPIC:
4680                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4681                 break;
4682         default:
4683                 r = -EINVAL;
4684                 break;
4685         }
4686         kvm_pic_update_irq(pic);
4687         return r;
4688 }
4689
4690 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4691 {
4692         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4693
4694         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4695
4696         mutex_lock(&kps->lock);
4697         memcpy(ps, &kps->channels, sizeof(*ps));
4698         mutex_unlock(&kps->lock);
4699         return 0;
4700 }
4701
4702 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4703 {
4704         int i;
4705         struct kvm_pit *pit = kvm->arch.vpit;
4706
4707         mutex_lock(&pit->pit_state.lock);
4708         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4709         for (i = 0; i < 3; i++)
4710                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4711         mutex_unlock(&pit->pit_state.lock);
4712         return 0;
4713 }
4714
4715 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4716 {
4717         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4718         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4719                 sizeof(ps->channels));
4720         ps->flags = kvm->arch.vpit->pit_state.flags;
4721         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4722         memset(&ps->reserved, 0, sizeof(ps->reserved));
4723         return 0;
4724 }
4725
4726 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4727 {
4728         int start = 0;
4729         int i;
4730         u32 prev_legacy, cur_legacy;
4731         struct kvm_pit *pit = kvm->arch.vpit;
4732
4733         mutex_lock(&pit->pit_state.lock);
4734         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4735         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4736         if (!prev_legacy && cur_legacy)
4737                 start = 1;
4738         memcpy(&pit->pit_state.channels, &ps->channels,
4739                sizeof(pit->pit_state.channels));
4740         pit->pit_state.flags = ps->flags;
4741         for (i = 0; i < 3; i++)
4742                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4743                                    start && i == 0);
4744         mutex_unlock(&pit->pit_state.lock);
4745         return 0;
4746 }
4747
4748 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4749                                  struct kvm_reinject_control *control)
4750 {
4751         struct kvm_pit *pit = kvm->arch.vpit;
4752
4753         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4754          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4755          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4756          */
4757         mutex_lock(&pit->pit_state.lock);
4758         kvm_pit_set_reinject(pit, control->pit_reinject);
4759         mutex_unlock(&pit->pit_state.lock);
4760
4761         return 0;
4762 }
4763
4764 /**
4765  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4766  * @kvm: kvm instance
4767  * @log: slot id and address to which we copy the log
4768  *
4769  * Steps 1-4 below provide general overview of dirty page logging. See
4770  * kvm_get_dirty_log_protect() function description for additional details.
4771  *
4772  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4773  * always flush the TLB (step 4) even if previous step failed  and the dirty
4774  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4775  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4776  * writes will be marked dirty for next log read.
4777  *
4778  *   1. Take a snapshot of the bit and clear it if needed.
4779  *   2. Write protect the corresponding page.
4780  *   3. Copy the snapshot to the userspace.
4781  *   4. Flush TLB's if needed.
4782  */
4783 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4784 {
4785         bool flush = false;
4786         int r;
4787
4788         mutex_lock(&kvm->slots_lock);
4789
4790         /*
4791          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4792          */
4793         if (kvm_x86_ops->flush_log_dirty)
4794                 kvm_x86_ops->flush_log_dirty(kvm);
4795
4796         r = kvm_get_dirty_log_protect(kvm, log, &flush);
4797
4798         /*
4799          * All the TLBs can be flushed out of mmu lock, see the comments in
4800          * kvm_mmu_slot_remove_write_access().
4801          */
4802         lockdep_assert_held(&kvm->slots_lock);
4803         if (flush)
4804                 kvm_flush_remote_tlbs(kvm);
4805
4806         mutex_unlock(&kvm->slots_lock);
4807         return r;
4808 }
4809
4810 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4811 {
4812         bool flush = false;
4813         int r;
4814
4815         mutex_lock(&kvm->slots_lock);
4816
4817         /*
4818          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4819          */
4820         if (kvm_x86_ops->flush_log_dirty)
4821                 kvm_x86_ops->flush_log_dirty(kvm);
4822
4823         r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4824
4825         /*
4826          * All the TLBs can be flushed out of mmu lock, see the comments in
4827          * kvm_mmu_slot_remove_write_access().
4828          */
4829         lockdep_assert_held(&kvm->slots_lock);
4830         if (flush)
4831                 kvm_flush_remote_tlbs(kvm);
4832
4833         mutex_unlock(&kvm->slots_lock);
4834         return r;
4835 }
4836
4837 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4838                         bool line_status)
4839 {
4840         if (!irqchip_in_kernel(kvm))
4841                 return -ENXIO;
4842
4843         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4844                                         irq_event->irq, irq_event->level,
4845                                         line_status);
4846         return 0;
4847 }
4848
4849 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4850                             struct kvm_enable_cap *cap)
4851 {
4852         int r;
4853
4854         if (cap->flags)
4855                 return -EINVAL;
4856
4857         switch (cap->cap) {
4858         case KVM_CAP_DISABLE_QUIRKS:
4859                 kvm->arch.disabled_quirks = cap->args[0];
4860                 r = 0;
4861                 break;
4862         case KVM_CAP_SPLIT_IRQCHIP: {
4863                 mutex_lock(&kvm->lock);
4864                 r = -EINVAL;
4865                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4866                         goto split_irqchip_unlock;
4867                 r = -EEXIST;
4868                 if (irqchip_in_kernel(kvm))
4869                         goto split_irqchip_unlock;
4870                 if (kvm->created_vcpus)
4871                         goto split_irqchip_unlock;
4872                 r = kvm_setup_empty_irq_routing(kvm);
4873                 if (r)
4874                         goto split_irqchip_unlock;
4875                 /* Pairs with irqchip_in_kernel. */
4876                 smp_wmb();
4877                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4878                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4879                 r = 0;
4880 split_irqchip_unlock:
4881                 mutex_unlock(&kvm->lock);
4882                 break;
4883         }
4884         case KVM_CAP_X2APIC_API:
4885                 r = -EINVAL;
4886                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4887                         break;
4888
4889                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4890                         kvm->arch.x2apic_format = true;
4891                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4892                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4893
4894                 r = 0;
4895                 break;
4896         case KVM_CAP_X86_DISABLE_EXITS:
4897                 r = -EINVAL;
4898                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4899                         break;
4900
4901                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4902                         kvm_can_mwait_in_guest())
4903                         kvm->arch.mwait_in_guest = true;
4904                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4905                         kvm->arch.hlt_in_guest = true;
4906                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4907                         kvm->arch.pause_in_guest = true;
4908                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4909                         kvm->arch.cstate_in_guest = true;
4910                 r = 0;
4911                 break;
4912         case KVM_CAP_MSR_PLATFORM_INFO:
4913                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4914                 r = 0;
4915                 break;
4916         case KVM_CAP_EXCEPTION_PAYLOAD:
4917                 kvm->arch.exception_payload_enabled = cap->args[0];
4918                 r = 0;
4919                 break;
4920         default:
4921                 r = -EINVAL;
4922                 break;
4923         }
4924         return r;
4925 }
4926
4927 long kvm_arch_vm_ioctl(struct file *filp,
4928                        unsigned int ioctl, unsigned long arg)
4929 {
4930         struct kvm *kvm = filp->private_data;
4931         void __user *argp = (void __user *)arg;
4932         int r = -ENOTTY;
4933         /*
4934          * This union makes it completely explicit to gcc-3.x
4935          * that these two variables' stack usage should be
4936          * combined, not added together.
4937          */
4938         union {
4939                 struct kvm_pit_state ps;
4940                 struct kvm_pit_state2 ps2;
4941                 struct kvm_pit_config pit_config;
4942         } u;
4943
4944         switch (ioctl) {
4945         case KVM_SET_TSS_ADDR:
4946                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4947                 break;
4948         case KVM_SET_IDENTITY_MAP_ADDR: {
4949                 u64 ident_addr;
4950
4951                 mutex_lock(&kvm->lock);
4952                 r = -EINVAL;
4953                 if (kvm->created_vcpus)
4954                         goto set_identity_unlock;
4955                 r = -EFAULT;
4956                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4957                         goto set_identity_unlock;
4958                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4959 set_identity_unlock:
4960                 mutex_unlock(&kvm->lock);
4961                 break;
4962         }
4963         case KVM_SET_NR_MMU_PAGES:
4964                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4965                 break;
4966         case KVM_GET_NR_MMU_PAGES:
4967                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4968                 break;
4969         case KVM_CREATE_IRQCHIP: {
4970                 mutex_lock(&kvm->lock);
4971
4972                 r = -EEXIST;
4973                 if (irqchip_in_kernel(kvm))
4974                         goto create_irqchip_unlock;
4975
4976                 r = -EINVAL;
4977                 if (kvm->created_vcpus)
4978                         goto create_irqchip_unlock;
4979
4980                 r = kvm_pic_init(kvm);
4981                 if (r)
4982                         goto create_irqchip_unlock;
4983
4984                 r = kvm_ioapic_init(kvm);
4985                 if (r) {
4986                         kvm_pic_destroy(kvm);
4987                         goto create_irqchip_unlock;
4988                 }
4989
4990                 r = kvm_setup_default_irq_routing(kvm);
4991                 if (r) {
4992                         kvm_ioapic_destroy(kvm);
4993                         kvm_pic_destroy(kvm);
4994                         goto create_irqchip_unlock;
4995                 }
4996                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4997                 smp_wmb();
4998                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4999         create_irqchip_unlock:
5000                 mutex_unlock(&kvm->lock);
5001                 break;
5002         }
5003         case KVM_CREATE_PIT:
5004                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5005                 goto create_pit;
5006         case KVM_CREATE_PIT2:
5007                 r = -EFAULT;
5008                 if (copy_from_user(&u.pit_config, argp,
5009                                    sizeof(struct kvm_pit_config)))
5010                         goto out;
5011         create_pit:
5012                 mutex_lock(&kvm->lock);
5013                 r = -EEXIST;
5014                 if (kvm->arch.vpit)
5015                         goto create_pit_unlock;
5016                 r = -ENOMEM;
5017                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5018                 if (kvm->arch.vpit)
5019                         r = 0;
5020         create_pit_unlock:
5021                 mutex_unlock(&kvm->lock);
5022                 break;
5023         case KVM_GET_IRQCHIP: {
5024                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5025                 struct kvm_irqchip *chip;
5026
5027                 chip = memdup_user(argp, sizeof(*chip));
5028                 if (IS_ERR(chip)) {
5029                         r = PTR_ERR(chip);
5030                         goto out;
5031                 }
5032
5033                 r = -ENXIO;
5034                 if (!irqchip_kernel(kvm))
5035                         goto get_irqchip_out;
5036                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5037                 if (r)
5038                         goto get_irqchip_out;
5039                 r = -EFAULT;
5040                 if (copy_to_user(argp, chip, sizeof(*chip)))
5041                         goto get_irqchip_out;
5042                 r = 0;
5043         get_irqchip_out:
5044                 kfree(chip);
5045                 break;
5046         }
5047         case KVM_SET_IRQCHIP: {
5048                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5049                 struct kvm_irqchip *chip;
5050
5051                 chip = memdup_user(argp, sizeof(*chip));
5052                 if (IS_ERR(chip)) {
5053                         r = PTR_ERR(chip);
5054                         goto out;
5055                 }
5056
5057                 r = -ENXIO;
5058                 if (!irqchip_kernel(kvm))
5059                         goto set_irqchip_out;
5060                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5061         set_irqchip_out:
5062                 kfree(chip);
5063                 break;
5064         }
5065         case KVM_GET_PIT: {
5066                 r = -EFAULT;
5067                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5068                         goto out;
5069                 r = -ENXIO;
5070                 if (!kvm->arch.vpit)
5071                         goto out;
5072                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5073                 if (r)
5074                         goto out;
5075                 r = -EFAULT;
5076                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5077                         goto out;
5078                 r = 0;
5079                 break;
5080         }
5081         case KVM_SET_PIT: {
5082                 r = -EFAULT;
5083                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5084                         goto out;
5085                 r = -ENXIO;
5086                 if (!kvm->arch.vpit)
5087                         goto out;
5088                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5089                 break;
5090         }
5091         case KVM_GET_PIT2: {
5092                 r = -ENXIO;
5093                 if (!kvm->arch.vpit)
5094                         goto out;
5095                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5096                 if (r)
5097                         goto out;
5098                 r = -EFAULT;
5099                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5100                         goto out;
5101                 r = 0;
5102                 break;
5103         }
5104         case KVM_SET_PIT2: {
5105                 r = -EFAULT;
5106                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5107                         goto out;
5108                 r = -ENXIO;
5109                 if (!kvm->arch.vpit)
5110                         goto out;
5111                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5112                 break;
5113         }
5114         case KVM_REINJECT_CONTROL: {
5115                 struct kvm_reinject_control control;
5116                 r =  -EFAULT;
5117                 if (copy_from_user(&control, argp, sizeof(control)))
5118                         goto out;
5119                 r = -ENXIO;
5120                 if (!kvm->arch.vpit)
5121                         goto out;
5122                 r = kvm_vm_ioctl_reinject(kvm, &control);
5123                 break;
5124         }
5125         case KVM_SET_BOOT_CPU_ID:
5126                 r = 0;
5127                 mutex_lock(&kvm->lock);
5128                 if (kvm->created_vcpus)
5129                         r = -EBUSY;
5130                 else
5131                         kvm->arch.bsp_vcpu_id = arg;
5132                 mutex_unlock(&kvm->lock);
5133                 break;
5134         case KVM_XEN_HVM_CONFIG: {
5135                 struct kvm_xen_hvm_config xhc;
5136                 r = -EFAULT;
5137                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5138                         goto out;
5139                 r = -EINVAL;
5140                 if (xhc.flags)
5141                         goto out;
5142                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5143                 r = 0;
5144                 break;
5145         }
5146         case KVM_SET_CLOCK: {
5147                 struct kvm_clock_data user_ns;
5148                 u64 now_ns;
5149
5150                 r = -EFAULT;
5151                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5152                         goto out;
5153
5154                 r = -EINVAL;
5155                 if (user_ns.flags)
5156                         goto out;
5157
5158                 r = 0;
5159                 /*
5160                  * TODO: userspace has to take care of races with VCPU_RUN, so
5161                  * kvm_gen_update_masterclock() can be cut down to locked
5162                  * pvclock_update_vm_gtod_copy().
5163                  */
5164                 kvm_gen_update_masterclock(kvm);
5165                 now_ns = get_kvmclock_ns(kvm);
5166                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5167                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5168                 break;
5169         }
5170         case KVM_GET_CLOCK: {
5171                 struct kvm_clock_data user_ns;
5172                 u64 now_ns;
5173
5174                 now_ns = get_kvmclock_ns(kvm);
5175                 user_ns.clock = now_ns;
5176                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5177                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5178
5179                 r = -EFAULT;
5180                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5181                         goto out;
5182                 r = 0;
5183                 break;
5184         }
5185         case KVM_MEMORY_ENCRYPT_OP: {
5186                 r = -ENOTTY;
5187                 if (kvm_x86_ops->mem_enc_op)
5188                         r = kvm_x86_ops->mem_enc_op(kvm, argp);
5189                 break;
5190         }
5191         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5192                 struct kvm_enc_region region;
5193
5194                 r = -EFAULT;
5195                 if (copy_from_user(&region, argp, sizeof(region)))
5196                         goto out;
5197
5198                 r = -ENOTTY;
5199                 if (kvm_x86_ops->mem_enc_reg_region)
5200                         r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5201                 break;
5202         }
5203         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5204                 struct kvm_enc_region region;
5205
5206                 r = -EFAULT;
5207                 if (copy_from_user(&region, argp, sizeof(region)))
5208                         goto out;
5209
5210                 r = -ENOTTY;
5211                 if (kvm_x86_ops->mem_enc_unreg_region)
5212                         r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5213                 break;
5214         }
5215         case KVM_HYPERV_EVENTFD: {
5216                 struct kvm_hyperv_eventfd hvevfd;
5217
5218                 r = -EFAULT;
5219                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5220                         goto out;
5221                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5222                 break;
5223         }
5224         case KVM_SET_PMU_EVENT_FILTER:
5225                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5226                 break;
5227         default:
5228                 r = -ENOTTY;
5229         }
5230 out:
5231         return r;
5232 }
5233
5234 static void kvm_init_msr_list(void)
5235 {
5236         struct x86_pmu_capability x86_pmu;
5237         u32 dummy[2];
5238         unsigned i;
5239
5240         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5241                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5242
5243         perf_get_x86_pmu_capability(&x86_pmu);
5244
5245         num_msrs_to_save = 0;
5246         num_emulated_msrs = 0;
5247         num_msr_based_features = 0;
5248
5249         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5250                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5251                         continue;
5252
5253                 /*
5254                  * Even MSRs that are valid in the host may not be exposed
5255                  * to the guests in some cases.
5256                  */
5257                 switch (msrs_to_save_all[i]) {
5258                 case MSR_IA32_BNDCFGS:
5259                         if (!kvm_mpx_supported())
5260                                 continue;
5261                         break;
5262                 case MSR_TSC_AUX:
5263                         if (!kvm_x86_ops->rdtscp_supported())
5264                                 continue;
5265                         break;
5266                 case MSR_IA32_RTIT_CTL:
5267                 case MSR_IA32_RTIT_STATUS:
5268                         if (!kvm_x86_ops->pt_supported())
5269                                 continue;
5270                         break;
5271                 case MSR_IA32_RTIT_CR3_MATCH:
5272                         if (!kvm_x86_ops->pt_supported() ||
5273                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5274                                 continue;
5275                         break;
5276                 case MSR_IA32_RTIT_OUTPUT_BASE:
5277                 case MSR_IA32_RTIT_OUTPUT_MASK:
5278                         if (!kvm_x86_ops->pt_supported() ||
5279                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5280                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5281                                 continue;
5282                         break;
5283                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5284                         if (!kvm_x86_ops->pt_supported() ||
5285                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5286                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5287                                 continue;
5288                         break;
5289                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5290                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5291                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5292                                 continue;
5293                         break;
5294                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5295                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5296                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5297                                 continue;
5298                 }
5299                 default:
5300                         break;
5301                 }
5302
5303                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5304         }
5305
5306         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5307                 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
5308                         continue;
5309
5310                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5311         }
5312
5313         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5314                 struct kvm_msr_entry msr;
5315
5316                 msr.index = msr_based_features_all[i];
5317                 if (kvm_get_msr_feature(&msr))
5318                         continue;
5319
5320                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5321         }
5322 }
5323
5324 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5325                            const void *v)
5326 {
5327         int handled = 0;
5328         int n;
5329
5330         do {
5331                 n = min(len, 8);
5332                 if (!(lapic_in_kernel(vcpu) &&
5333                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5334                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5335                         break;
5336                 handled += n;
5337                 addr += n;
5338                 len -= n;
5339                 v += n;
5340         } while (len);
5341
5342         return handled;
5343 }
5344
5345 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5346 {
5347         int handled = 0;
5348         int n;
5349
5350         do {
5351                 n = min(len, 8);
5352                 if (!(lapic_in_kernel(vcpu) &&
5353                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5354                                          addr, n, v))
5355                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5356                         break;
5357                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5358                 handled += n;
5359                 addr += n;
5360                 len -= n;
5361                 v += n;
5362         } while (len);
5363
5364         return handled;
5365 }
5366
5367 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5368                         struct kvm_segment *var, int seg)
5369 {
5370         kvm_x86_ops->set_segment(vcpu, var, seg);
5371 }
5372
5373 void kvm_get_segment(struct kvm_vcpu *vcpu,
5374                      struct kvm_segment *var, int seg)
5375 {
5376         kvm_x86_ops->get_segment(vcpu, var, seg);
5377 }
5378
5379 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5380                            struct x86_exception *exception)
5381 {
5382         gpa_t t_gpa;
5383
5384         BUG_ON(!mmu_is_nested(vcpu));
5385
5386         /* NPT walks are always user-walks */
5387         access |= PFERR_USER_MASK;
5388         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5389
5390         return t_gpa;
5391 }
5392
5393 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5394                               struct x86_exception *exception)
5395 {
5396         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5397         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5398 }
5399
5400  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5401                                 struct x86_exception *exception)
5402 {
5403         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5404         access |= PFERR_FETCH_MASK;
5405         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5406 }
5407
5408 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5409                                struct x86_exception *exception)
5410 {
5411         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5412         access |= PFERR_WRITE_MASK;
5413         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5414 }
5415
5416 /* uses this to access any guest's mapped memory without checking CPL */
5417 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5418                                 struct x86_exception *exception)
5419 {
5420         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5421 }
5422
5423 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5424                                       struct kvm_vcpu *vcpu, u32 access,
5425                                       struct x86_exception *exception)
5426 {
5427         void *data = val;
5428         int r = X86EMUL_CONTINUE;
5429
5430         while (bytes) {
5431                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5432                                                             exception);
5433                 unsigned offset = addr & (PAGE_SIZE-1);
5434                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5435                 int ret;
5436
5437                 if (gpa == UNMAPPED_GVA)
5438                         return X86EMUL_PROPAGATE_FAULT;
5439                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5440                                                offset, toread);
5441                 if (ret < 0) {
5442                         r = X86EMUL_IO_NEEDED;
5443                         goto out;
5444                 }
5445
5446                 bytes -= toread;
5447                 data += toread;
5448                 addr += toread;
5449         }
5450 out:
5451         return r;
5452 }
5453
5454 /* used for instruction fetching */
5455 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5456                                 gva_t addr, void *val, unsigned int bytes,
5457                                 struct x86_exception *exception)
5458 {
5459         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5460         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5461         unsigned offset;
5462         int ret;
5463
5464         /* Inline kvm_read_guest_virt_helper for speed.  */
5465         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5466                                                     exception);
5467         if (unlikely(gpa == UNMAPPED_GVA))
5468                 return X86EMUL_PROPAGATE_FAULT;
5469
5470         offset = addr & (PAGE_SIZE-1);
5471         if (WARN_ON(offset + bytes > PAGE_SIZE))
5472                 bytes = (unsigned)PAGE_SIZE - offset;
5473         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5474                                        offset, bytes);
5475         if (unlikely(ret < 0))
5476                 return X86EMUL_IO_NEEDED;
5477
5478         return X86EMUL_CONTINUE;
5479 }
5480
5481 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5482                                gva_t addr, void *val, unsigned int bytes,
5483                                struct x86_exception *exception)
5484 {
5485         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5486
5487         /*
5488          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5489          * is returned, but our callers are not ready for that and they blindly
5490          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5491          * uninitialized kernel stack memory into cr2 and error code.
5492          */
5493         memset(exception, 0, sizeof(*exception));
5494         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5495                                           exception);
5496 }
5497 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5498
5499 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5500                              gva_t addr, void *val, unsigned int bytes,
5501                              struct x86_exception *exception, bool system)
5502 {
5503         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5504         u32 access = 0;
5505
5506         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5507                 access |= PFERR_USER_MASK;
5508
5509         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5510 }
5511
5512 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5513                 unsigned long addr, void *val, unsigned int bytes)
5514 {
5515         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5516         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5517
5518         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5519 }
5520
5521 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5522                                       struct kvm_vcpu *vcpu, u32 access,
5523                                       struct x86_exception *exception)
5524 {
5525         void *data = val;
5526         int r = X86EMUL_CONTINUE;
5527
5528         while (bytes) {
5529                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5530                                                              access,
5531                                                              exception);
5532                 unsigned offset = addr & (PAGE_SIZE-1);
5533                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5534                 int ret;
5535
5536                 if (gpa == UNMAPPED_GVA)
5537                         return X86EMUL_PROPAGATE_FAULT;
5538                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5539                 if (ret < 0) {
5540                         r = X86EMUL_IO_NEEDED;
5541                         goto out;
5542                 }
5543
5544                 bytes -= towrite;
5545                 data += towrite;
5546                 addr += towrite;
5547         }
5548 out:
5549         return r;
5550 }
5551
5552 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5553                               unsigned int bytes, struct x86_exception *exception,
5554                               bool system)
5555 {
5556         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5557         u32 access = PFERR_WRITE_MASK;
5558
5559         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5560                 access |= PFERR_USER_MASK;
5561
5562         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5563                                            access, exception);
5564 }
5565
5566 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5567                                 unsigned int bytes, struct x86_exception *exception)
5568 {
5569         /* kvm_write_guest_virt_system can pull in tons of pages. */
5570         vcpu->arch.l1tf_flush_l1d = true;
5571
5572         /*
5573          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5574          * is returned, but our callers are not ready for that and they blindly
5575          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5576          * uninitialized kernel stack memory into cr2 and error code.
5577          */
5578         memset(exception, 0, sizeof(*exception));
5579         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5580                                            PFERR_WRITE_MASK, exception);
5581 }
5582 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5583
5584 int handle_ud(struct kvm_vcpu *vcpu)
5585 {
5586         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5587         int emul_type = EMULTYPE_TRAP_UD;
5588         char sig[5]; /* ud2; .ascii "kvm" */
5589         struct x86_exception e;
5590
5591         if (force_emulation_prefix &&
5592             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5593                                 sig, sizeof(sig), &e) == 0 &&
5594             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5595                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5596                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5597         }
5598
5599         return kvm_emulate_instruction(vcpu, emul_type);
5600 }
5601 EXPORT_SYMBOL_GPL(handle_ud);
5602
5603 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5604                             gpa_t gpa, bool write)
5605 {
5606         /* For APIC access vmexit */
5607         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5608                 return 1;
5609
5610         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5611                 trace_vcpu_match_mmio(gva, gpa, write, true);
5612                 return 1;
5613         }
5614
5615         return 0;
5616 }
5617
5618 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5619                                 gpa_t *gpa, struct x86_exception *exception,
5620                                 bool write)
5621 {
5622         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5623                 | (write ? PFERR_WRITE_MASK : 0);
5624
5625         /*
5626          * currently PKRU is only applied to ept enabled guest so
5627          * there is no pkey in EPT page table for L1 guest or EPT
5628          * shadow page table for L2 guest.
5629          */
5630         if (vcpu_match_mmio_gva(vcpu, gva)
5631             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5632                                  vcpu->arch.mmio_access, 0, access)) {
5633                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5634                                         (gva & (PAGE_SIZE - 1));
5635                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5636                 return 1;
5637         }
5638
5639         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5640
5641         if (*gpa == UNMAPPED_GVA)
5642                 return -1;
5643
5644         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5645 }
5646
5647 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5648                         const void *val, int bytes)
5649 {
5650         int ret;
5651
5652         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5653         if (ret < 0)
5654                 return 0;
5655         kvm_page_track_write(vcpu, gpa, val, bytes);
5656         return 1;
5657 }
5658
5659 struct read_write_emulator_ops {
5660         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5661                                   int bytes);
5662         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5663                                   void *val, int bytes);
5664         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5665                                int bytes, void *val);
5666         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5667                                     void *val, int bytes);
5668         bool write;
5669 };
5670
5671 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5672 {
5673         if (vcpu->mmio_read_completed) {
5674                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5675                                vcpu->mmio_fragments[0].gpa, val);
5676                 vcpu->mmio_read_completed = 0;
5677                 return 1;
5678         }
5679
5680         return 0;
5681 }
5682
5683 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5684                         void *val, int bytes)
5685 {
5686         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5687 }
5688
5689 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5690                          void *val, int bytes)
5691 {
5692         return emulator_write_phys(vcpu, gpa, val, bytes);
5693 }
5694
5695 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5696 {
5697         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5698         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5699 }
5700
5701 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5702                           void *val, int bytes)
5703 {
5704         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5705         return X86EMUL_IO_NEEDED;
5706 }
5707
5708 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5709                            void *val, int bytes)
5710 {
5711         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5712
5713         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5714         return X86EMUL_CONTINUE;
5715 }
5716
5717 static const struct read_write_emulator_ops read_emultor = {
5718         .read_write_prepare = read_prepare,
5719         .read_write_emulate = read_emulate,
5720         .read_write_mmio = vcpu_mmio_read,
5721         .read_write_exit_mmio = read_exit_mmio,
5722 };
5723
5724 static const struct read_write_emulator_ops write_emultor = {
5725         .read_write_emulate = write_emulate,
5726         .read_write_mmio = write_mmio,
5727         .read_write_exit_mmio = write_exit_mmio,
5728         .write = true,
5729 };
5730
5731 static int emulator_read_write_onepage(unsigned long addr, void *val,
5732                                        unsigned int bytes,
5733                                        struct x86_exception *exception,
5734                                        struct kvm_vcpu *vcpu,
5735                                        const struct read_write_emulator_ops *ops)
5736 {
5737         gpa_t gpa;
5738         int handled, ret;
5739         bool write = ops->write;
5740         struct kvm_mmio_fragment *frag;
5741         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5742
5743         /*
5744          * If the exit was due to a NPF we may already have a GPA.
5745          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5746          * Note, this cannot be used on string operations since string
5747          * operation using rep will only have the initial GPA from the NPF
5748          * occurred.
5749          */
5750         if (vcpu->arch.gpa_available &&
5751             emulator_can_use_gpa(ctxt) &&
5752             (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5753                 gpa = vcpu->arch.gpa_val;
5754                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5755         } else {
5756                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5757                 if (ret < 0)
5758                         return X86EMUL_PROPAGATE_FAULT;
5759         }
5760
5761         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5762                 return X86EMUL_CONTINUE;
5763
5764         /*
5765          * Is this MMIO handled locally?
5766          */
5767         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5768         if (handled == bytes)
5769                 return X86EMUL_CONTINUE;
5770
5771         gpa += handled;
5772         bytes -= handled;
5773         val += handled;
5774
5775         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5776         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5777         frag->gpa = gpa;
5778         frag->data = val;
5779         frag->len = bytes;
5780         return X86EMUL_CONTINUE;
5781 }
5782
5783 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5784                         unsigned long addr,
5785                         void *val, unsigned int bytes,
5786                         struct x86_exception *exception,
5787                         const struct read_write_emulator_ops *ops)
5788 {
5789         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5790         gpa_t gpa;
5791         int rc;
5792
5793         if (ops->read_write_prepare &&
5794                   ops->read_write_prepare(vcpu, val, bytes))
5795                 return X86EMUL_CONTINUE;
5796
5797         vcpu->mmio_nr_fragments = 0;
5798
5799         /* Crossing a page boundary? */
5800         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5801                 int now;
5802
5803                 now = -addr & ~PAGE_MASK;
5804                 rc = emulator_read_write_onepage(addr, val, now, exception,
5805                                                  vcpu, ops);
5806
5807                 if (rc != X86EMUL_CONTINUE)
5808                         return rc;
5809                 addr += now;
5810                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5811                         addr = (u32)addr;
5812                 val += now;
5813                 bytes -= now;
5814         }
5815
5816         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5817                                          vcpu, ops);
5818         if (rc != X86EMUL_CONTINUE)
5819                 return rc;
5820
5821         if (!vcpu->mmio_nr_fragments)
5822                 return rc;
5823
5824         gpa = vcpu->mmio_fragments[0].gpa;
5825
5826         vcpu->mmio_needed = 1;
5827         vcpu->mmio_cur_fragment = 0;
5828
5829         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5830         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5831         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5832         vcpu->run->mmio.phys_addr = gpa;
5833
5834         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5835 }
5836
5837 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5838                                   unsigned long addr,
5839                                   void *val,
5840                                   unsigned int bytes,
5841                                   struct x86_exception *exception)
5842 {
5843         return emulator_read_write(ctxt, addr, val, bytes,
5844                                    exception, &read_emultor);
5845 }
5846
5847 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5848                             unsigned long addr,
5849                             const void *val,
5850                             unsigned int bytes,
5851                             struct x86_exception *exception)
5852 {
5853         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5854                                    exception, &write_emultor);
5855 }
5856
5857 #define CMPXCHG_TYPE(t, ptr, old, new) \
5858         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5859
5860 #ifdef CONFIG_X86_64
5861 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5862 #else
5863 #  define CMPXCHG64(ptr, old, new) \
5864         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5865 #endif
5866
5867 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5868                                      unsigned long addr,
5869                                      const void *old,
5870                                      const void *new,
5871                                      unsigned int bytes,
5872                                      struct x86_exception *exception)
5873 {
5874         struct kvm_host_map map;
5875         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5876         gpa_t gpa;
5877         char *kaddr;
5878         bool exchanged;
5879
5880         /* guests cmpxchg8b have to be emulated atomically */
5881         if (bytes > 8 || (bytes & (bytes - 1)))
5882                 goto emul_write;
5883
5884         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5885
5886         if (gpa == UNMAPPED_GVA ||
5887             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5888                 goto emul_write;
5889
5890         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5891                 goto emul_write;
5892
5893         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5894                 goto emul_write;
5895
5896         kaddr = map.hva + offset_in_page(gpa);
5897
5898         switch (bytes) {
5899         case 1:
5900                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5901                 break;
5902         case 2:
5903                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5904                 break;
5905         case 4:
5906                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5907                 break;
5908         case 8:
5909                 exchanged = CMPXCHG64(kaddr, old, new);
5910                 break;
5911         default:
5912                 BUG();
5913         }
5914
5915         kvm_vcpu_unmap(vcpu, &map, true);
5916
5917         if (!exchanged)
5918                 return X86EMUL_CMPXCHG_FAILED;
5919
5920         kvm_page_track_write(vcpu, gpa, new, bytes);
5921
5922         return X86EMUL_CONTINUE;
5923
5924 emul_write:
5925         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5926
5927         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5928 }
5929
5930 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5931 {
5932         int r = 0, i;
5933
5934         for (i = 0; i < vcpu->arch.pio.count; i++) {
5935                 if (vcpu->arch.pio.in)
5936                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5937                                             vcpu->arch.pio.size, pd);
5938                 else
5939                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5940                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5941                                              pd);
5942                 if (r)
5943                         break;
5944                 pd += vcpu->arch.pio.size;
5945         }
5946         return r;
5947 }
5948
5949 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5950                                unsigned short port, void *val,
5951                                unsigned int count, bool in)
5952 {
5953         vcpu->arch.pio.port = port;
5954         vcpu->arch.pio.in = in;
5955         vcpu->arch.pio.count  = count;
5956         vcpu->arch.pio.size = size;
5957
5958         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5959                 vcpu->arch.pio.count = 0;
5960                 return 1;
5961         }
5962
5963         vcpu->run->exit_reason = KVM_EXIT_IO;
5964         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5965         vcpu->run->io.size = size;
5966         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5967         vcpu->run->io.count = count;
5968         vcpu->run->io.port = port;
5969
5970         return 0;
5971 }
5972
5973 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5974                                     int size, unsigned short port, void *val,
5975                                     unsigned int count)
5976 {
5977         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5978         int ret;
5979
5980         if (vcpu->arch.pio.count)
5981                 goto data_avail;
5982
5983         memset(vcpu->arch.pio_data, 0, size * count);
5984
5985         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5986         if (ret) {
5987 data_avail:
5988                 memcpy(val, vcpu->arch.pio_data, size * count);
5989                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5990                 vcpu->arch.pio.count = 0;
5991                 return 1;
5992         }
5993
5994         return 0;
5995 }
5996
5997 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5998                                      int size, unsigned short port,
5999                                      const void *val, unsigned int count)
6000 {
6001         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6002
6003         memcpy(vcpu->arch.pio_data, val, size * count);
6004         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6005         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6006 }
6007
6008 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6009 {
6010         return kvm_x86_ops->get_segment_base(vcpu, seg);
6011 }
6012
6013 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6014 {
6015         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6016 }
6017
6018 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6019 {
6020         if (!need_emulate_wbinvd(vcpu))
6021                 return X86EMUL_CONTINUE;
6022
6023         if (kvm_x86_ops->has_wbinvd_exit()) {
6024                 int cpu = get_cpu();
6025
6026                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6027                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6028                                 wbinvd_ipi, NULL, 1);
6029                 put_cpu();
6030                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6031         } else
6032                 wbinvd();
6033         return X86EMUL_CONTINUE;
6034 }
6035
6036 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6037 {
6038         kvm_emulate_wbinvd_noskip(vcpu);
6039         return kvm_skip_emulated_instruction(vcpu);
6040 }
6041 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6042
6043
6044
6045 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6046 {
6047         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6048 }
6049
6050 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6051                            unsigned long *dest)
6052 {
6053         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6054 }
6055
6056 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6057                            unsigned long value)
6058 {
6059
6060         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6061 }
6062
6063 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6064 {
6065         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6066 }
6067
6068 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6069 {
6070         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6071         unsigned long value;
6072
6073         switch (cr) {
6074         case 0:
6075                 value = kvm_read_cr0(vcpu);
6076                 break;
6077         case 2:
6078                 value = vcpu->arch.cr2;
6079                 break;
6080         case 3:
6081                 value = kvm_read_cr3(vcpu);
6082                 break;
6083         case 4:
6084                 value = kvm_read_cr4(vcpu);
6085                 break;
6086         case 8:
6087                 value = kvm_get_cr8(vcpu);
6088                 break;
6089         default:
6090                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6091                 return 0;
6092         }
6093
6094         return value;
6095 }
6096
6097 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6098 {
6099         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6100         int res = 0;
6101
6102         switch (cr) {
6103         case 0:
6104                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6105                 break;
6106         case 2:
6107                 vcpu->arch.cr2 = val;
6108                 break;
6109         case 3:
6110                 res = kvm_set_cr3(vcpu, val);
6111                 break;
6112         case 4:
6113                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6114                 break;
6115         case 8:
6116                 res = kvm_set_cr8(vcpu, val);
6117                 break;
6118         default:
6119                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6120                 res = -1;
6121         }
6122
6123         return res;
6124 }
6125
6126 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6127 {
6128         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
6129 }
6130
6131 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6132 {
6133         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
6134 }
6135
6136 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6137 {
6138         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6139 }
6140
6141 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6142 {
6143         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6144 }
6145
6146 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6147 {
6148         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6149 }
6150
6151 static unsigned long emulator_get_cached_segment_base(
6152         struct x86_emulate_ctxt *ctxt, int seg)
6153 {
6154         return get_segment_base(emul_to_vcpu(ctxt), seg);
6155 }
6156
6157 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6158                                  struct desc_struct *desc, u32 *base3,
6159                                  int seg)
6160 {
6161         struct kvm_segment var;
6162
6163         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6164         *selector = var.selector;
6165
6166         if (var.unusable) {
6167                 memset(desc, 0, sizeof(*desc));
6168                 if (base3)
6169                         *base3 = 0;
6170                 return false;
6171         }
6172
6173         if (var.g)
6174                 var.limit >>= 12;
6175         set_desc_limit(desc, var.limit);
6176         set_desc_base(desc, (unsigned long)var.base);
6177 #ifdef CONFIG_X86_64
6178         if (base3)
6179                 *base3 = var.base >> 32;
6180 #endif
6181         desc->type = var.type;
6182         desc->s = var.s;
6183         desc->dpl = var.dpl;
6184         desc->p = var.present;
6185         desc->avl = var.avl;
6186         desc->l = var.l;
6187         desc->d = var.db;
6188         desc->g = var.g;
6189
6190         return true;
6191 }
6192
6193 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6194                                  struct desc_struct *desc, u32 base3,
6195                                  int seg)
6196 {
6197         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6198         struct kvm_segment var;
6199
6200         var.selector = selector;
6201         var.base = get_desc_base(desc);
6202 #ifdef CONFIG_X86_64
6203         var.base |= ((u64)base3) << 32;
6204 #endif
6205         var.limit = get_desc_limit(desc);
6206         if (desc->g)
6207                 var.limit = (var.limit << 12) | 0xfff;
6208         var.type = desc->type;
6209         var.dpl = desc->dpl;
6210         var.db = desc->d;
6211         var.s = desc->s;
6212         var.l = desc->l;
6213         var.g = desc->g;
6214         var.avl = desc->avl;
6215         var.present = desc->p;
6216         var.unusable = !var.present;
6217         var.padding = 0;
6218
6219         kvm_set_segment(vcpu, &var, seg);
6220         return;
6221 }
6222
6223 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6224                             u32 msr_index, u64 *pdata)
6225 {
6226         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6227 }
6228
6229 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6230                             u32 msr_index, u64 data)
6231 {
6232         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6233 }
6234
6235 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6236 {
6237         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6238
6239         return vcpu->arch.smbase;
6240 }
6241
6242 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6243 {
6244         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6245
6246         vcpu->arch.smbase = smbase;
6247 }
6248
6249 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6250                               u32 pmc)
6251 {
6252         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6253 }
6254
6255 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6256                              u32 pmc, u64 *pdata)
6257 {
6258         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6259 }
6260
6261 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6262 {
6263         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6264 }
6265
6266 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6267                               struct x86_instruction_info *info,
6268                               enum x86_intercept_stage stage)
6269 {
6270         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6271 }
6272
6273 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6274                         u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6275 {
6276         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6277 }
6278
6279 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6280 {
6281         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6282 }
6283
6284 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6285 {
6286         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6287 }
6288
6289 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6290 {
6291         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6292 }
6293
6294 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6295 {
6296         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6297 }
6298
6299 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6300 {
6301         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6302 }
6303
6304 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6305 {
6306         kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6307 }
6308
6309 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6310 {
6311         return emul_to_vcpu(ctxt)->arch.hflags;
6312 }
6313
6314 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6315 {
6316         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6317 }
6318
6319 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6320                                   const char *smstate)
6321 {
6322         return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6323 }
6324
6325 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6326 {
6327         kvm_smm_changed(emul_to_vcpu(ctxt));
6328 }
6329
6330 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6331 {
6332         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6333 }
6334
6335 static const struct x86_emulate_ops emulate_ops = {
6336         .read_gpr            = emulator_read_gpr,
6337         .write_gpr           = emulator_write_gpr,
6338         .read_std            = emulator_read_std,
6339         .write_std           = emulator_write_std,
6340         .read_phys           = kvm_read_guest_phys_system,
6341         .fetch               = kvm_fetch_guest_virt,
6342         .read_emulated       = emulator_read_emulated,
6343         .write_emulated      = emulator_write_emulated,
6344         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6345         .invlpg              = emulator_invlpg,
6346         .pio_in_emulated     = emulator_pio_in_emulated,
6347         .pio_out_emulated    = emulator_pio_out_emulated,
6348         .get_segment         = emulator_get_segment,
6349         .set_segment         = emulator_set_segment,
6350         .get_cached_segment_base = emulator_get_cached_segment_base,
6351         .get_gdt             = emulator_get_gdt,
6352         .get_idt             = emulator_get_idt,
6353         .set_gdt             = emulator_set_gdt,
6354         .set_idt             = emulator_set_idt,
6355         .get_cr              = emulator_get_cr,
6356         .set_cr              = emulator_set_cr,
6357         .cpl                 = emulator_get_cpl,
6358         .get_dr              = emulator_get_dr,
6359         .set_dr              = emulator_set_dr,
6360         .get_smbase          = emulator_get_smbase,
6361         .set_smbase          = emulator_set_smbase,
6362         .set_msr             = emulator_set_msr,
6363         .get_msr             = emulator_get_msr,
6364         .check_pmc           = emulator_check_pmc,
6365         .read_pmc            = emulator_read_pmc,
6366         .halt                = emulator_halt,
6367         .wbinvd              = emulator_wbinvd,
6368         .fix_hypercall       = emulator_fix_hypercall,
6369         .intercept           = emulator_intercept,
6370         .get_cpuid           = emulator_get_cpuid,
6371         .guest_has_long_mode = emulator_guest_has_long_mode,
6372         .guest_has_movbe     = emulator_guest_has_movbe,
6373         .guest_has_fxsr      = emulator_guest_has_fxsr,
6374         .set_nmi_mask        = emulator_set_nmi_mask,
6375         .get_hflags          = emulator_get_hflags,
6376         .set_hflags          = emulator_set_hflags,
6377         .pre_leave_smm       = emulator_pre_leave_smm,
6378         .post_leave_smm      = emulator_post_leave_smm,
6379         .set_xcr             = emulator_set_xcr,
6380 };
6381
6382 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6383 {
6384         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6385         /*
6386          * an sti; sti; sequence only disable interrupts for the first
6387          * instruction. So, if the last instruction, be it emulated or
6388          * not, left the system with the INT_STI flag enabled, it
6389          * means that the last instruction is an sti. We should not
6390          * leave the flag on in this case. The same goes for mov ss
6391          */
6392         if (int_shadow & mask)
6393                 mask = 0;
6394         if (unlikely(int_shadow || mask)) {
6395                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6396                 if (!mask)
6397                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6398         }
6399 }
6400
6401 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6402 {
6403         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6404         if (ctxt->exception.vector == PF_VECTOR)
6405                 return kvm_propagate_fault(vcpu, &ctxt->exception);
6406
6407         if (ctxt->exception.error_code_valid)
6408                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6409                                       ctxt->exception.error_code);
6410         else
6411                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6412         return false;
6413 }
6414
6415 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6416 {
6417         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6418         int cs_db, cs_l;
6419
6420         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6421
6422         ctxt->eflags = kvm_get_rflags(vcpu);
6423         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6424
6425         ctxt->eip = kvm_rip_read(vcpu);
6426         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6427                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6428                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6429                      cs_db                              ? X86EMUL_MODE_PROT32 :
6430                                                           X86EMUL_MODE_PROT16;
6431         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6432         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6433         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6434
6435         init_decode_cache(ctxt);
6436         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6437 }
6438
6439 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6440 {
6441         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6442         int ret;
6443
6444         init_emulate_ctxt(vcpu);
6445
6446         ctxt->op_bytes = 2;
6447         ctxt->ad_bytes = 2;
6448         ctxt->_eip = ctxt->eip + inc_eip;
6449         ret = emulate_int_real(ctxt, irq);
6450
6451         if (ret != X86EMUL_CONTINUE) {
6452                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6453         } else {
6454                 ctxt->eip = ctxt->_eip;
6455                 kvm_rip_write(vcpu, ctxt->eip);
6456                 kvm_set_rflags(vcpu, ctxt->eflags);
6457         }
6458 }
6459 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6460
6461 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6462 {
6463         ++vcpu->stat.insn_emulation_fail;
6464         trace_kvm_emulate_insn_failed(vcpu);
6465
6466         if (emulation_type & EMULTYPE_VMWARE_GP) {
6467                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6468                 return 1;
6469         }
6470
6471         if (emulation_type & EMULTYPE_SKIP) {
6472                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6473                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6474                 vcpu->run->internal.ndata = 0;
6475                 return 0;
6476         }
6477
6478         kvm_queue_exception(vcpu, UD_VECTOR);
6479
6480         if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6481                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6482                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6483                 vcpu->run->internal.ndata = 0;
6484                 return 0;
6485         }
6486
6487         return 1;
6488 }
6489
6490 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6491                                   bool write_fault_to_shadow_pgtable,
6492                                   int emulation_type)
6493 {
6494         gpa_t gpa = cr2_or_gpa;
6495         kvm_pfn_t pfn;
6496
6497         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6498                 return false;
6499
6500         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6501                 return false;
6502
6503         if (!vcpu->arch.mmu->direct_map) {
6504                 /*
6505                  * Write permission should be allowed since only
6506                  * write access need to be emulated.
6507                  */
6508                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6509
6510                 /*
6511                  * If the mapping is invalid in guest, let cpu retry
6512                  * it to generate fault.
6513                  */
6514                 if (gpa == UNMAPPED_GVA)
6515                         return true;
6516         }
6517
6518         /*
6519          * Do not retry the unhandleable instruction if it faults on the
6520          * readonly host memory, otherwise it will goto a infinite loop:
6521          * retry instruction -> write #PF -> emulation fail -> retry
6522          * instruction -> ...
6523          */
6524         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6525
6526         /*
6527          * If the instruction failed on the error pfn, it can not be fixed,
6528          * report the error to userspace.
6529          */
6530         if (is_error_noslot_pfn(pfn))
6531                 return false;
6532
6533         kvm_release_pfn_clean(pfn);
6534
6535         /* The instructions are well-emulated on direct mmu. */
6536         if (vcpu->arch.mmu->direct_map) {
6537                 unsigned int indirect_shadow_pages;
6538
6539                 spin_lock(&vcpu->kvm->mmu_lock);
6540                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6541                 spin_unlock(&vcpu->kvm->mmu_lock);
6542
6543                 if (indirect_shadow_pages)
6544                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6545
6546                 return true;
6547         }
6548
6549         /*
6550          * if emulation was due to access to shadowed page table
6551          * and it failed try to unshadow page and re-enter the
6552          * guest to let CPU execute the instruction.
6553          */
6554         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6555
6556         /*
6557          * If the access faults on its page table, it can not
6558          * be fixed by unprotecting shadow page and it should
6559          * be reported to userspace.
6560          */
6561         return !write_fault_to_shadow_pgtable;
6562 }
6563
6564 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6565                               gpa_t cr2_or_gpa,  int emulation_type)
6566 {
6567         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6568         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6569
6570         last_retry_eip = vcpu->arch.last_retry_eip;
6571         last_retry_addr = vcpu->arch.last_retry_addr;
6572
6573         /*
6574          * If the emulation is caused by #PF and it is non-page_table
6575          * writing instruction, it means the VM-EXIT is caused by shadow
6576          * page protected, we can zap the shadow page and retry this
6577          * instruction directly.
6578          *
6579          * Note: if the guest uses a non-page-table modifying instruction
6580          * on the PDE that points to the instruction, then we will unmap
6581          * the instruction and go to an infinite loop. So, we cache the
6582          * last retried eip and the last fault address, if we meet the eip
6583          * and the address again, we can break out of the potential infinite
6584          * loop.
6585          */
6586         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6587
6588         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6589                 return false;
6590
6591         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6592                 return false;
6593
6594         if (x86_page_table_writing_insn(ctxt))
6595                 return false;
6596
6597         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6598                 return false;
6599
6600         vcpu->arch.last_retry_eip = ctxt->eip;
6601         vcpu->arch.last_retry_addr = cr2_or_gpa;
6602
6603         if (!vcpu->arch.mmu->direct_map)
6604                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6605
6606         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6607
6608         return true;
6609 }
6610
6611 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6612 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6613
6614 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6615 {
6616         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6617                 /* This is a good place to trace that we are exiting SMM.  */
6618                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6619
6620                 /* Process a latched INIT or SMI, if any.  */
6621                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6622         }
6623
6624         kvm_mmu_reset_context(vcpu);
6625 }
6626
6627 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6628                                 unsigned long *db)
6629 {
6630         u32 dr6 = 0;
6631         int i;
6632         u32 enable, rwlen;
6633
6634         enable = dr7;
6635         rwlen = dr7 >> 16;
6636         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6637                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6638                         dr6 |= (1 << i);
6639         return dr6;
6640 }
6641
6642 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6643 {
6644         struct kvm_run *kvm_run = vcpu->run;
6645
6646         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6647                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6648                 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6649                 kvm_run->debug.arch.exception = DB_VECTOR;
6650                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6651                 return 0;
6652         }
6653         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6654         return 1;
6655 }
6656
6657 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6658 {
6659         unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6660         int r;
6661
6662         r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6663         if (unlikely(!r))
6664                 return 0;
6665
6666         /*
6667          * rflags is the old, "raw" value of the flags.  The new value has
6668          * not been saved yet.
6669          *
6670          * This is correct even for TF set by the guest, because "the
6671          * processor will not generate this exception after the instruction
6672          * that sets the TF flag".
6673          */
6674         if (unlikely(rflags & X86_EFLAGS_TF))
6675                 r = kvm_vcpu_do_singlestep(vcpu);
6676         return r;
6677 }
6678 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6679
6680 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6681 {
6682         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6683             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6684                 struct kvm_run *kvm_run = vcpu->run;
6685                 unsigned long eip = kvm_get_linear_rip(vcpu);
6686                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6687                                            vcpu->arch.guest_debug_dr7,
6688                                            vcpu->arch.eff_db);
6689
6690                 if (dr6 != 0) {
6691                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6692                         kvm_run->debug.arch.pc = eip;
6693                         kvm_run->debug.arch.exception = DB_VECTOR;
6694                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6695                         *r = 0;
6696                         return true;
6697                 }
6698         }
6699
6700         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6701             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6702                 unsigned long eip = kvm_get_linear_rip(vcpu);
6703                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6704                                            vcpu->arch.dr7,
6705                                            vcpu->arch.db);
6706
6707                 if (dr6 != 0) {
6708                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6709                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6710                         kvm_queue_exception(vcpu, DB_VECTOR);
6711                         *r = 1;
6712                         return true;
6713                 }
6714         }
6715
6716         return false;
6717 }
6718
6719 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6720 {
6721         switch (ctxt->opcode_len) {
6722         case 1:
6723                 switch (ctxt->b) {
6724                 case 0xe4:      /* IN */
6725                 case 0xe5:
6726                 case 0xec:
6727                 case 0xed:
6728                 case 0xe6:      /* OUT */
6729                 case 0xe7:
6730                 case 0xee:
6731                 case 0xef:
6732                 case 0x6c:      /* INS */
6733                 case 0x6d:
6734                 case 0x6e:      /* OUTS */
6735                 case 0x6f:
6736                         return true;
6737                 }
6738                 break;
6739         case 2:
6740                 switch (ctxt->b) {
6741                 case 0x33:      /* RDPMC */
6742                         return true;
6743                 }
6744                 break;
6745         }
6746
6747         return false;
6748 }
6749
6750 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6751                             int emulation_type, void *insn, int insn_len)
6752 {
6753         int r;
6754         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6755         bool writeback = true;
6756         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6757
6758         vcpu->arch.l1tf_flush_l1d = true;
6759
6760         /*
6761          * Clear write_fault_to_shadow_pgtable here to ensure it is
6762          * never reused.
6763          */
6764         vcpu->arch.write_fault_to_shadow_pgtable = false;
6765         kvm_clear_exception_queue(vcpu);
6766
6767         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6768                 init_emulate_ctxt(vcpu);
6769
6770                 /*
6771                  * We will reenter on the same instruction since
6772                  * we do not set complete_userspace_io.  This does not
6773                  * handle watchpoints yet, those would be handled in
6774                  * the emulate_ops.
6775                  */
6776                 if (!(emulation_type & EMULTYPE_SKIP) &&
6777                     kvm_vcpu_check_breakpoint(vcpu, &r))
6778                         return r;
6779
6780                 ctxt->interruptibility = 0;
6781                 ctxt->have_exception = false;
6782                 ctxt->exception.vector = -1;
6783                 ctxt->perm_ok = false;
6784
6785                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6786
6787                 r = x86_decode_insn(ctxt, insn, insn_len);
6788
6789                 trace_kvm_emulate_insn_start(vcpu);
6790                 ++vcpu->stat.insn_emulation;
6791                 if (r != EMULATION_OK)  {
6792                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6793                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6794                                 kvm_queue_exception(vcpu, UD_VECTOR);
6795                                 return 1;
6796                         }
6797                         if (reexecute_instruction(vcpu, cr2_or_gpa,
6798                                                   write_fault_to_spt,
6799                                                   emulation_type))
6800                                 return 1;
6801                         if (ctxt->have_exception) {
6802                                 /*
6803                                  * #UD should result in just EMULATION_FAILED, and trap-like
6804                                  * exception should not be encountered during decode.
6805                                  */
6806                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6807                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6808                                 inject_emulated_exception(vcpu);
6809                                 return 1;
6810                         }
6811                         return handle_emulation_failure(vcpu, emulation_type);
6812                 }
6813         }
6814
6815         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6816             !is_vmware_backdoor_opcode(ctxt)) {
6817                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6818                 return 1;
6819         }
6820
6821         /*
6822          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6823          * for kvm_skip_emulated_instruction().  The caller is responsible for
6824          * updating interruptibility state and injecting single-step #DBs.
6825          */
6826         if (emulation_type & EMULTYPE_SKIP) {
6827                 kvm_rip_write(vcpu, ctxt->_eip);
6828                 if (ctxt->eflags & X86_EFLAGS_RF)
6829                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6830                 return 1;
6831         }
6832
6833         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6834                 return 1;
6835
6836         /* this is needed for vmware backdoor interface to work since it
6837            changes registers values  during IO operation */
6838         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6839                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6840                 emulator_invalidate_register_cache(ctxt);
6841         }
6842
6843 restart:
6844         /* Save the faulting GPA (cr2) in the address field */
6845         ctxt->exception.address = cr2_or_gpa;
6846
6847         r = x86_emulate_insn(ctxt);
6848
6849         if (r == EMULATION_INTERCEPTED)
6850                 return 1;
6851
6852         if (r == EMULATION_FAILED) {
6853                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6854                                         emulation_type))
6855                         return 1;
6856
6857                 return handle_emulation_failure(vcpu, emulation_type);
6858         }
6859
6860         if (ctxt->have_exception) {
6861                 r = 1;
6862                 if (inject_emulated_exception(vcpu))
6863                         return r;
6864         } else if (vcpu->arch.pio.count) {
6865                 if (!vcpu->arch.pio.in) {
6866                         /* FIXME: return into emulator if single-stepping.  */
6867                         vcpu->arch.pio.count = 0;
6868                 } else {
6869                         writeback = false;
6870                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6871                 }
6872                 r = 0;
6873         } else if (vcpu->mmio_needed) {
6874                 ++vcpu->stat.mmio_exits;
6875
6876                 if (!vcpu->mmio_is_write)
6877                         writeback = false;
6878                 r = 0;
6879                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6880         } else if (r == EMULATION_RESTART)
6881                 goto restart;
6882         else
6883                 r = 1;
6884
6885         if (writeback) {
6886                 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6887                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6888                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6889                 if (!ctxt->have_exception ||
6890                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6891                         kvm_rip_write(vcpu, ctxt->eip);
6892                         if (r && ctxt->tf)
6893                                 r = kvm_vcpu_do_singlestep(vcpu);
6894                         if (kvm_x86_ops->update_emulated_instruction)
6895                                 kvm_x86_ops->update_emulated_instruction(vcpu);
6896                         __kvm_set_rflags(vcpu, ctxt->eflags);
6897                 }
6898
6899                 /*
6900                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6901                  * do nothing, and it will be requested again as soon as
6902                  * the shadow expires.  But we still need to check here,
6903                  * because POPF has no interrupt shadow.
6904                  */
6905                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6906                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6907         } else
6908                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6909
6910         return r;
6911 }
6912
6913 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6914 {
6915         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6916 }
6917 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6918
6919 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6920                                         void *insn, int insn_len)
6921 {
6922         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6923 }
6924 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6925
6926 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6927 {
6928         vcpu->arch.pio.count = 0;
6929         return 1;
6930 }
6931
6932 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6933 {
6934         vcpu->arch.pio.count = 0;
6935
6936         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6937                 return 1;
6938
6939         return kvm_skip_emulated_instruction(vcpu);
6940 }
6941
6942 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6943                             unsigned short port)
6944 {
6945         unsigned long val = kvm_rax_read(vcpu);
6946         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6947                                             size, port, &val, 1);
6948         if (ret)
6949                 return ret;
6950
6951         /*
6952          * Workaround userspace that relies on old KVM behavior of %rip being
6953          * incremented prior to exiting to userspace to handle "OUT 0x7e".
6954          */
6955         if (port == 0x7e &&
6956             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6957                 vcpu->arch.complete_userspace_io =
6958                         complete_fast_pio_out_port_0x7e;
6959                 kvm_skip_emulated_instruction(vcpu);
6960         } else {
6961                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6962                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6963         }
6964         return 0;
6965 }
6966
6967 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6968 {
6969         unsigned long val;
6970
6971         /* We should only ever be called with arch.pio.count equal to 1 */
6972         BUG_ON(vcpu->arch.pio.count != 1);
6973
6974         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6975                 vcpu->arch.pio.count = 0;
6976                 return 1;
6977         }
6978
6979         /* For size less than 4 we merge, else we zero extend */
6980         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6981
6982         /*
6983          * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6984          * the copy and tracing
6985          */
6986         emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6987                                  vcpu->arch.pio.port, &val, 1);
6988         kvm_rax_write(vcpu, val);
6989
6990         return kvm_skip_emulated_instruction(vcpu);
6991 }
6992
6993 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6994                            unsigned short port)
6995 {
6996         unsigned long val;
6997         int ret;
6998
6999         /* For size less than 4 we merge, else we zero extend */
7000         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7001
7002         ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
7003                                        &val, 1);
7004         if (ret) {
7005                 kvm_rax_write(vcpu, val);
7006                 return ret;
7007         }
7008
7009         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7010         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7011
7012         return 0;
7013 }
7014
7015 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7016 {
7017         int ret;
7018
7019         if (in)
7020                 ret = kvm_fast_pio_in(vcpu, size, port);
7021         else
7022                 ret = kvm_fast_pio_out(vcpu, size, port);
7023         return ret && kvm_skip_emulated_instruction(vcpu);
7024 }
7025 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7026
7027 static int kvmclock_cpu_down_prep(unsigned int cpu)
7028 {
7029         __this_cpu_write(cpu_tsc_khz, 0);
7030         return 0;
7031 }
7032
7033 static void tsc_khz_changed(void *data)
7034 {
7035         struct cpufreq_freqs *freq = data;
7036         unsigned long khz = 0;
7037
7038         if (data)
7039                 khz = freq->new;
7040         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7041                 khz = cpufreq_quick_get(raw_smp_processor_id());
7042         if (!khz)
7043                 khz = tsc_khz;
7044         __this_cpu_write(cpu_tsc_khz, khz);
7045 }
7046
7047 #ifdef CONFIG_X86_64
7048 static void kvm_hyperv_tsc_notifier(void)
7049 {
7050         struct kvm *kvm;
7051         struct kvm_vcpu *vcpu;
7052         int cpu;
7053
7054         mutex_lock(&kvm_lock);
7055         list_for_each_entry(kvm, &vm_list, vm_list)
7056                 kvm_make_mclock_inprogress_request(kvm);
7057
7058         hyperv_stop_tsc_emulation();
7059
7060         /* TSC frequency always matches when on Hyper-V */
7061         for_each_present_cpu(cpu)
7062                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7063         kvm_max_guest_tsc_khz = tsc_khz;
7064
7065         list_for_each_entry(kvm, &vm_list, vm_list) {
7066                 struct kvm_arch *ka = &kvm->arch;
7067
7068                 spin_lock(&ka->pvclock_gtod_sync_lock);
7069
7070                 pvclock_update_vm_gtod_copy(kvm);
7071
7072                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7073                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7074
7075                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7076                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7077
7078                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7079         }
7080         mutex_unlock(&kvm_lock);
7081 }
7082 #endif
7083
7084 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7085 {
7086         struct kvm *kvm;
7087         struct kvm_vcpu *vcpu;
7088         int i, send_ipi = 0;
7089
7090         /*
7091          * We allow guests to temporarily run on slowing clocks,
7092          * provided we notify them after, or to run on accelerating
7093          * clocks, provided we notify them before.  Thus time never
7094          * goes backwards.
7095          *
7096          * However, we have a problem.  We can't atomically update
7097          * the frequency of a given CPU from this function; it is
7098          * merely a notifier, which can be called from any CPU.
7099          * Changing the TSC frequency at arbitrary points in time
7100          * requires a recomputation of local variables related to
7101          * the TSC for each VCPU.  We must flag these local variables
7102          * to be updated and be sure the update takes place with the
7103          * new frequency before any guests proceed.
7104          *
7105          * Unfortunately, the combination of hotplug CPU and frequency
7106          * change creates an intractable locking scenario; the order
7107          * of when these callouts happen is undefined with respect to
7108          * CPU hotplug, and they can race with each other.  As such,
7109          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7110          * undefined; you can actually have a CPU frequency change take
7111          * place in between the computation of X and the setting of the
7112          * variable.  To protect against this problem, all updates of
7113          * the per_cpu tsc_khz variable are done in an interrupt
7114          * protected IPI, and all callers wishing to update the value
7115          * must wait for a synchronous IPI to complete (which is trivial
7116          * if the caller is on the CPU already).  This establishes the
7117          * necessary total order on variable updates.
7118          *
7119          * Note that because a guest time update may take place
7120          * anytime after the setting of the VCPU's request bit, the
7121          * correct TSC value must be set before the request.  However,
7122          * to ensure the update actually makes it to any guest which
7123          * starts running in hardware virtualization between the set
7124          * and the acquisition of the spinlock, we must also ping the
7125          * CPU after setting the request bit.
7126          *
7127          */
7128
7129         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7130
7131         mutex_lock(&kvm_lock);
7132         list_for_each_entry(kvm, &vm_list, vm_list) {
7133                 kvm_for_each_vcpu(i, vcpu, kvm) {
7134                         if (vcpu->cpu != cpu)
7135                                 continue;
7136                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7137                         if (vcpu->cpu != raw_smp_processor_id())
7138                                 send_ipi = 1;
7139                 }
7140         }
7141         mutex_unlock(&kvm_lock);
7142
7143         if (freq->old < freq->new && send_ipi) {
7144                 /*
7145                  * We upscale the frequency.  Must make the guest
7146                  * doesn't see old kvmclock values while running with
7147                  * the new frequency, otherwise we risk the guest sees
7148                  * time go backwards.
7149                  *
7150                  * In case we update the frequency for another cpu
7151                  * (which might be in guest context) send an interrupt
7152                  * to kick the cpu out of guest context.  Next time
7153                  * guest context is entered kvmclock will be updated,
7154                  * so the guest will not see stale values.
7155                  */
7156                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7157         }
7158 }
7159
7160 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7161                                      void *data)
7162 {
7163         struct cpufreq_freqs *freq = data;
7164         int cpu;
7165
7166         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7167                 return 0;
7168         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7169                 return 0;
7170
7171         for_each_cpu(cpu, freq->policy->cpus)
7172                 __kvmclock_cpufreq_notifier(freq, cpu);
7173
7174         return 0;
7175 }
7176
7177 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7178         .notifier_call  = kvmclock_cpufreq_notifier
7179 };
7180
7181 static int kvmclock_cpu_online(unsigned int cpu)
7182 {
7183         tsc_khz_changed(NULL);
7184         return 0;
7185 }
7186
7187 static void kvm_timer_init(void)
7188 {
7189         max_tsc_khz = tsc_khz;
7190
7191         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7192 #ifdef CONFIG_CPU_FREQ
7193                 struct cpufreq_policy *policy;
7194                 int cpu;
7195
7196                 cpu = get_cpu();
7197                 policy = cpufreq_cpu_get(cpu);
7198                 if (policy) {
7199                         if (policy->cpuinfo.max_freq)
7200                                 max_tsc_khz = policy->cpuinfo.max_freq;
7201                         cpufreq_cpu_put(policy);
7202                 }
7203                 put_cpu();
7204 #endif
7205                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7206                                           CPUFREQ_TRANSITION_NOTIFIER);
7207         }
7208
7209         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7210                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7211 }
7212
7213 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7214 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7215
7216 int kvm_is_in_guest(void)
7217 {
7218         return __this_cpu_read(current_vcpu) != NULL;
7219 }
7220
7221 static int kvm_is_user_mode(void)
7222 {
7223         int user_mode = 3;
7224
7225         if (__this_cpu_read(current_vcpu))
7226                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7227
7228         return user_mode != 0;
7229 }
7230
7231 static unsigned long kvm_get_guest_ip(void)
7232 {
7233         unsigned long ip = 0;
7234
7235         if (__this_cpu_read(current_vcpu))
7236                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7237
7238         return ip;
7239 }
7240
7241 static void kvm_handle_intel_pt_intr(void)
7242 {
7243         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7244
7245         kvm_make_request(KVM_REQ_PMI, vcpu);
7246         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7247                         (unsigned long *)&vcpu->arch.pmu.global_status);
7248 }
7249
7250 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7251         .is_in_guest            = kvm_is_in_guest,
7252         .is_user_mode           = kvm_is_user_mode,
7253         .get_guest_ip           = kvm_get_guest_ip,
7254         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7255 };
7256
7257 #ifdef CONFIG_X86_64
7258 static void pvclock_gtod_update_fn(struct work_struct *work)
7259 {
7260         struct kvm *kvm;
7261
7262         struct kvm_vcpu *vcpu;
7263         int i;
7264
7265         mutex_lock(&kvm_lock);
7266         list_for_each_entry(kvm, &vm_list, vm_list)
7267                 kvm_for_each_vcpu(i, vcpu, kvm)
7268                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7269         atomic_set(&kvm_guest_has_master_clock, 0);
7270         mutex_unlock(&kvm_lock);
7271 }
7272
7273 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7274
7275 /*
7276  * Notification about pvclock gtod data update.
7277  */
7278 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7279                                void *priv)
7280 {
7281         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7282         struct timekeeper *tk = priv;
7283
7284         update_pvclock_gtod(tk);
7285
7286         /* disable master clock if host does not trust, or does not
7287          * use, TSC based clocksource.
7288          */
7289         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7290             atomic_read(&kvm_guest_has_master_clock) != 0)
7291                 queue_work(system_long_wq, &pvclock_gtod_work);
7292
7293         return 0;
7294 }
7295
7296 static struct notifier_block pvclock_gtod_notifier = {
7297         .notifier_call = pvclock_gtod_notify,
7298 };
7299 #endif
7300
7301 int kvm_arch_init(void *opaque)
7302 {
7303         int r;
7304         struct kvm_x86_ops *ops = opaque;
7305
7306         if (kvm_x86_ops) {
7307                 printk(KERN_ERR "kvm: already loaded the other module\n");
7308                 r = -EEXIST;
7309                 goto out;
7310         }
7311
7312         if (!ops->cpu_has_kvm_support()) {
7313                 pr_err_ratelimited("kvm: no hardware support\n");
7314                 r = -EOPNOTSUPP;
7315                 goto out;
7316         }
7317         if (ops->disabled_by_bios()) {
7318                 pr_err_ratelimited("kvm: disabled by bios\n");
7319                 r = -EOPNOTSUPP;
7320                 goto out;
7321         }
7322
7323         /*
7324          * KVM explicitly assumes that the guest has an FPU and
7325          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7326          * vCPU's FPU state as a fxregs_state struct.
7327          */
7328         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7329                 printk(KERN_ERR "kvm: inadequate fpu\n");
7330                 r = -EOPNOTSUPP;
7331                 goto out;
7332         }
7333
7334         r = -ENOMEM;
7335         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7336                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7337                                           NULL);
7338         if (!x86_fpu_cache) {
7339                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7340                 goto out;
7341         }
7342
7343         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7344         if (!shared_msrs) {
7345                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7346                 goto out_free_x86_fpu_cache;
7347         }
7348
7349         r = kvm_mmu_module_init();
7350         if (r)
7351                 goto out_free_percpu;
7352
7353         kvm_x86_ops = ops;
7354
7355         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7356                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7357                         PT_PRESENT_MASK, 0, sme_me_mask);
7358         kvm_timer_init();
7359
7360         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7361
7362         if (boot_cpu_has(X86_FEATURE_XSAVE))
7363                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7364
7365         kvm_lapic_init();
7366         if (pi_inject_timer == -1)
7367                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7368 #ifdef CONFIG_X86_64
7369         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7370
7371         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7372                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7373 #endif
7374
7375         return 0;
7376
7377 out_free_percpu:
7378         free_percpu(shared_msrs);
7379 out_free_x86_fpu_cache:
7380         kmem_cache_destroy(x86_fpu_cache);
7381 out:
7382         return r;
7383 }
7384
7385 void kvm_arch_exit(void)
7386 {
7387 #ifdef CONFIG_X86_64
7388         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7389                 clear_hv_tscchange_cb();
7390 #endif
7391         kvm_lapic_exit();
7392         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7393
7394         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7395                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7396                                             CPUFREQ_TRANSITION_NOTIFIER);
7397         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7398 #ifdef CONFIG_X86_64
7399         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7400 #endif
7401         kvm_x86_ops = NULL;
7402         kvm_mmu_module_exit();
7403         free_percpu(shared_msrs);
7404         kmem_cache_destroy(x86_fpu_cache);
7405 }
7406
7407 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7408 {
7409         ++vcpu->stat.halt_exits;
7410         if (lapic_in_kernel(vcpu)) {
7411                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7412                 return 1;
7413         } else {
7414                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7415                 return 0;
7416         }
7417 }
7418 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7419
7420 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7421 {
7422         int ret = kvm_skip_emulated_instruction(vcpu);
7423         /*
7424          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7425          * KVM_EXIT_DEBUG here.
7426          */
7427         return kvm_vcpu_halt(vcpu) && ret;
7428 }
7429 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7430
7431 #ifdef CONFIG_X86_64
7432 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7433                                 unsigned long clock_type)
7434 {
7435         struct kvm_clock_pairing clock_pairing;
7436         struct timespec64 ts;
7437         u64 cycle;
7438         int ret;
7439
7440         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7441                 return -KVM_EOPNOTSUPP;
7442
7443         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7444                 return -KVM_EOPNOTSUPP;
7445
7446         clock_pairing.sec = ts.tv_sec;
7447         clock_pairing.nsec = ts.tv_nsec;
7448         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7449         clock_pairing.flags = 0;
7450         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7451
7452         ret = 0;
7453         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7454                             sizeof(struct kvm_clock_pairing)))
7455                 ret = -KVM_EFAULT;
7456
7457         return ret;
7458 }
7459 #endif
7460
7461 /*
7462  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7463  *
7464  * @apicid - apicid of vcpu to be kicked.
7465  */
7466 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7467 {
7468         struct kvm_lapic_irq lapic_irq;
7469
7470         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7471         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7472         lapic_irq.level = 0;
7473         lapic_irq.dest_id = apicid;
7474         lapic_irq.msi_redir_hint = false;
7475
7476         lapic_irq.delivery_mode = APIC_DM_REMRD;
7477         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7478 }
7479
7480 bool kvm_apicv_activated(struct kvm *kvm)
7481 {
7482         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7483 }
7484 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7485
7486 void kvm_apicv_init(struct kvm *kvm, bool enable)
7487 {
7488         if (enable)
7489                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7490                           &kvm->arch.apicv_inhibit_reasons);
7491         else
7492                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7493                         &kvm->arch.apicv_inhibit_reasons);
7494 }
7495 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7496
7497 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7498 {
7499         struct kvm_vcpu *target = NULL;
7500         struct kvm_apic_map *map;
7501
7502         rcu_read_lock();
7503         map = rcu_dereference(kvm->arch.apic_map);
7504
7505         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7506                 target = map->phys_map[dest_id]->vcpu;
7507
7508         rcu_read_unlock();
7509
7510         if (target && READ_ONCE(target->ready))
7511                 kvm_vcpu_yield_to(target);
7512 }
7513
7514 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7515 {
7516         unsigned long nr, a0, a1, a2, a3, ret;
7517         int op_64_bit;
7518
7519         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7520                 return kvm_hv_hypercall(vcpu);
7521
7522         nr = kvm_rax_read(vcpu);
7523         a0 = kvm_rbx_read(vcpu);
7524         a1 = kvm_rcx_read(vcpu);
7525         a2 = kvm_rdx_read(vcpu);
7526         a3 = kvm_rsi_read(vcpu);
7527
7528         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7529
7530         op_64_bit = is_64_bit_mode(vcpu);
7531         if (!op_64_bit) {
7532                 nr &= 0xFFFFFFFF;
7533                 a0 &= 0xFFFFFFFF;
7534                 a1 &= 0xFFFFFFFF;
7535                 a2 &= 0xFFFFFFFF;
7536                 a3 &= 0xFFFFFFFF;
7537         }
7538
7539         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7540                 ret = -KVM_EPERM;
7541                 goto out;
7542         }
7543
7544         switch (nr) {
7545         case KVM_HC_VAPIC_POLL_IRQ:
7546                 ret = 0;
7547                 break;
7548         case KVM_HC_KICK_CPU:
7549                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7550                 kvm_sched_yield(vcpu->kvm, a1);
7551                 ret = 0;
7552                 break;
7553 #ifdef CONFIG_X86_64
7554         case KVM_HC_CLOCK_PAIRING:
7555                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7556                 break;
7557 #endif
7558         case KVM_HC_SEND_IPI:
7559                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7560                 break;
7561         case KVM_HC_SCHED_YIELD:
7562                 kvm_sched_yield(vcpu->kvm, a0);
7563                 ret = 0;
7564                 break;
7565         default:
7566                 ret = -KVM_ENOSYS;
7567                 break;
7568         }
7569 out:
7570         if (!op_64_bit)
7571                 ret = (u32)ret;
7572         kvm_rax_write(vcpu, ret);
7573
7574         ++vcpu->stat.hypercalls;
7575         return kvm_skip_emulated_instruction(vcpu);
7576 }
7577 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7578
7579 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7580 {
7581         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7582         char instruction[3];
7583         unsigned long rip = kvm_rip_read(vcpu);
7584
7585         kvm_x86_ops->patch_hypercall(vcpu, instruction);
7586
7587         return emulator_write_emulated(ctxt, rip, instruction, 3,
7588                 &ctxt->exception);
7589 }
7590
7591 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7592 {
7593         return vcpu->run->request_interrupt_window &&
7594                 likely(!pic_in_kernel(vcpu->kvm));
7595 }
7596
7597 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7598 {
7599         struct kvm_run *kvm_run = vcpu->run;
7600
7601         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7602         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7603         kvm_run->cr8 = kvm_get_cr8(vcpu);
7604         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7605         kvm_run->ready_for_interrupt_injection =
7606                 pic_in_kernel(vcpu->kvm) ||
7607                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7608 }
7609
7610 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7611 {
7612         int max_irr, tpr;
7613
7614         if (!kvm_x86_ops->update_cr8_intercept)
7615                 return;
7616
7617         if (!lapic_in_kernel(vcpu))
7618                 return;
7619
7620         if (vcpu->arch.apicv_active)
7621                 return;
7622
7623         if (!vcpu->arch.apic->vapic_addr)
7624                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7625         else
7626                 max_irr = -1;
7627
7628         if (max_irr != -1)
7629                 max_irr >>= 4;
7630
7631         tpr = kvm_lapic_get_cr8(vcpu);
7632
7633         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7634 }
7635
7636 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7637 {
7638         int r;
7639
7640         /* try to reinject previous events if any */
7641
7642         if (vcpu->arch.exception.injected)
7643                 kvm_x86_ops->queue_exception(vcpu);
7644         /*
7645          * Do not inject an NMI or interrupt if there is a pending
7646          * exception.  Exceptions and interrupts are recognized at
7647          * instruction boundaries, i.e. the start of an instruction.
7648          * Trap-like exceptions, e.g. #DB, have higher priority than
7649          * NMIs and interrupts, i.e. traps are recognized before an
7650          * NMI/interrupt that's pending on the same instruction.
7651          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7652          * priority, but are only generated (pended) during instruction
7653          * execution, i.e. a pending fault-like exception means the
7654          * fault occurred on the *previous* instruction and must be
7655          * serviced prior to recognizing any new events in order to
7656          * fully complete the previous instruction.
7657          */
7658         else if (!vcpu->arch.exception.pending) {
7659                 if (vcpu->arch.nmi_injected)
7660                         kvm_x86_ops->set_nmi(vcpu);
7661                 else if (vcpu->arch.interrupt.injected)
7662                         kvm_x86_ops->set_irq(vcpu);
7663         }
7664
7665         /*
7666          * Call check_nested_events() even if we reinjected a previous event
7667          * in order for caller to determine if it should require immediate-exit
7668          * from L2 to L1 due to pending L1 events which require exit
7669          * from L2 to L1.
7670          */
7671         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7672                 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7673                 if (r != 0)
7674                         return r;
7675         }
7676
7677         /* try to inject new event if pending */
7678         if (vcpu->arch.exception.pending) {
7679                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7680                                         vcpu->arch.exception.has_error_code,
7681                                         vcpu->arch.exception.error_code);
7682
7683                 WARN_ON_ONCE(vcpu->arch.exception.injected);
7684                 vcpu->arch.exception.pending = false;
7685                 vcpu->arch.exception.injected = true;
7686
7687                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7688                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7689                                              X86_EFLAGS_RF);
7690
7691                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7692                         /*
7693                          * This code assumes that nSVM doesn't use
7694                          * check_nested_events(). If it does, the
7695                          * DR6/DR7 changes should happen before L1
7696                          * gets a #VMEXIT for an intercepted #DB in
7697                          * L2.  (Under VMX, on the other hand, the
7698                          * DR6/DR7 changes should not happen in the
7699                          * event of a VM-exit to L1 for an intercepted
7700                          * #DB in L2.)
7701                          */
7702                         kvm_deliver_exception_payload(vcpu);
7703                         if (vcpu->arch.dr7 & DR7_GD) {
7704                                 vcpu->arch.dr7 &= ~DR7_GD;
7705                                 kvm_update_dr7(vcpu);
7706                         }
7707                 }
7708
7709                 kvm_x86_ops->queue_exception(vcpu);
7710         }
7711
7712         /* Don't consider new event if we re-injected an event */
7713         if (kvm_event_needs_reinjection(vcpu))
7714                 return 0;
7715
7716         if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7717             kvm_x86_ops->smi_allowed(vcpu)) {
7718                 vcpu->arch.smi_pending = false;
7719                 ++vcpu->arch.smi_count;
7720                 enter_smm(vcpu);
7721         } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7722                 --vcpu->arch.nmi_pending;
7723                 vcpu->arch.nmi_injected = true;
7724                 kvm_x86_ops->set_nmi(vcpu);
7725         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7726                 /*
7727                  * Because interrupts can be injected asynchronously, we are
7728                  * calling check_nested_events again here to avoid a race condition.
7729                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7730                  * proposal and current concerns.  Perhaps we should be setting
7731                  * KVM_REQ_EVENT only on certain events and not unconditionally?
7732                  */
7733                 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7734                         r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7735                         if (r != 0)
7736                                 return r;
7737                 }
7738                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7739                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7740                                             false);
7741                         kvm_x86_ops->set_irq(vcpu);
7742                 }
7743         }
7744
7745         return 0;
7746 }
7747
7748 static void process_nmi(struct kvm_vcpu *vcpu)
7749 {
7750         unsigned limit = 2;
7751
7752         /*
7753          * x86 is limited to one NMI running, and one NMI pending after it.
7754          * If an NMI is already in progress, limit further NMIs to just one.
7755          * Otherwise, allow two (and we'll inject the first one immediately).
7756          */
7757         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7758                 limit = 1;
7759
7760         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7761         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7762         kvm_make_request(KVM_REQ_EVENT, vcpu);
7763 }
7764
7765 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7766 {
7767         u32 flags = 0;
7768         flags |= seg->g       << 23;
7769         flags |= seg->db      << 22;
7770         flags |= seg->l       << 21;
7771         flags |= seg->avl     << 20;
7772         flags |= seg->present << 15;
7773         flags |= seg->dpl     << 13;
7774         flags |= seg->s       << 12;
7775         flags |= seg->type    << 8;
7776         return flags;
7777 }
7778
7779 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7780 {
7781         struct kvm_segment seg;
7782         int offset;
7783
7784         kvm_get_segment(vcpu, &seg, n);
7785         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7786
7787         if (n < 3)
7788                 offset = 0x7f84 + n * 12;
7789         else
7790                 offset = 0x7f2c + (n - 3) * 12;
7791
7792         put_smstate(u32, buf, offset + 8, seg.base);
7793         put_smstate(u32, buf, offset + 4, seg.limit);
7794         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7795 }
7796
7797 #ifdef CONFIG_X86_64
7798 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7799 {
7800         struct kvm_segment seg;
7801         int offset;
7802         u16 flags;
7803
7804         kvm_get_segment(vcpu, &seg, n);
7805         offset = 0x7e00 + n * 16;
7806
7807         flags = enter_smm_get_segment_flags(&seg) >> 8;
7808         put_smstate(u16, buf, offset, seg.selector);
7809         put_smstate(u16, buf, offset + 2, flags);
7810         put_smstate(u32, buf, offset + 4, seg.limit);
7811         put_smstate(u64, buf, offset + 8, seg.base);
7812 }
7813 #endif
7814
7815 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7816 {
7817         struct desc_ptr dt;
7818         struct kvm_segment seg;
7819         unsigned long val;
7820         int i;
7821
7822         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7823         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7824         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7825         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7826
7827         for (i = 0; i < 8; i++)
7828                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7829
7830         kvm_get_dr(vcpu, 6, &val);
7831         put_smstate(u32, buf, 0x7fcc, (u32)val);
7832         kvm_get_dr(vcpu, 7, &val);
7833         put_smstate(u32, buf, 0x7fc8, (u32)val);
7834
7835         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7836         put_smstate(u32, buf, 0x7fc4, seg.selector);
7837         put_smstate(u32, buf, 0x7f64, seg.base);
7838         put_smstate(u32, buf, 0x7f60, seg.limit);
7839         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7840
7841         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7842         put_smstate(u32, buf, 0x7fc0, seg.selector);
7843         put_smstate(u32, buf, 0x7f80, seg.base);
7844         put_smstate(u32, buf, 0x7f7c, seg.limit);
7845         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7846
7847         kvm_x86_ops->get_gdt(vcpu, &dt);
7848         put_smstate(u32, buf, 0x7f74, dt.address);
7849         put_smstate(u32, buf, 0x7f70, dt.size);
7850
7851         kvm_x86_ops->get_idt(vcpu, &dt);
7852         put_smstate(u32, buf, 0x7f58, dt.address);
7853         put_smstate(u32, buf, 0x7f54, dt.size);
7854
7855         for (i = 0; i < 6; i++)
7856                 enter_smm_save_seg_32(vcpu, buf, i);
7857
7858         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7859
7860         /* revision id */
7861         put_smstate(u32, buf, 0x7efc, 0x00020000);
7862         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7863 }
7864
7865 #ifdef CONFIG_X86_64
7866 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7867 {
7868         struct desc_ptr dt;
7869         struct kvm_segment seg;
7870         unsigned long val;
7871         int i;
7872
7873         for (i = 0; i < 16; i++)
7874                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7875
7876         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7877         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7878
7879         kvm_get_dr(vcpu, 6, &val);
7880         put_smstate(u64, buf, 0x7f68, val);
7881         kvm_get_dr(vcpu, 7, &val);
7882         put_smstate(u64, buf, 0x7f60, val);
7883
7884         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7885         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7886         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7887
7888         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7889
7890         /* revision id */
7891         put_smstate(u32, buf, 0x7efc, 0x00020064);
7892
7893         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7894
7895         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7896         put_smstate(u16, buf, 0x7e90, seg.selector);
7897         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7898         put_smstate(u32, buf, 0x7e94, seg.limit);
7899         put_smstate(u64, buf, 0x7e98, seg.base);
7900
7901         kvm_x86_ops->get_idt(vcpu, &dt);
7902         put_smstate(u32, buf, 0x7e84, dt.size);
7903         put_smstate(u64, buf, 0x7e88, dt.address);
7904
7905         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7906         put_smstate(u16, buf, 0x7e70, seg.selector);
7907         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7908         put_smstate(u32, buf, 0x7e74, seg.limit);
7909         put_smstate(u64, buf, 0x7e78, seg.base);
7910
7911         kvm_x86_ops->get_gdt(vcpu, &dt);
7912         put_smstate(u32, buf, 0x7e64, dt.size);
7913         put_smstate(u64, buf, 0x7e68, dt.address);
7914
7915         for (i = 0; i < 6; i++)
7916                 enter_smm_save_seg_64(vcpu, buf, i);
7917 }
7918 #endif
7919
7920 static void enter_smm(struct kvm_vcpu *vcpu)
7921 {
7922         struct kvm_segment cs, ds;
7923         struct desc_ptr dt;
7924         char buf[512];
7925         u32 cr0;
7926
7927         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7928         memset(buf, 0, 512);
7929 #ifdef CONFIG_X86_64
7930         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7931                 enter_smm_save_state_64(vcpu, buf);
7932         else
7933 #endif
7934                 enter_smm_save_state_32(vcpu, buf);
7935
7936         /*
7937          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7938          * vCPU state (e.g. leave guest mode) after we've saved the state into
7939          * the SMM state-save area.
7940          */
7941         kvm_x86_ops->pre_enter_smm(vcpu, buf);
7942
7943         vcpu->arch.hflags |= HF_SMM_MASK;
7944         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7945
7946         if (kvm_x86_ops->get_nmi_mask(vcpu))
7947                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7948         else
7949                 kvm_x86_ops->set_nmi_mask(vcpu, true);
7950
7951         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7952         kvm_rip_write(vcpu, 0x8000);
7953
7954         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7955         kvm_x86_ops->set_cr0(vcpu, cr0);
7956         vcpu->arch.cr0 = cr0;
7957
7958         kvm_x86_ops->set_cr4(vcpu, 0);
7959
7960         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
7961         dt.address = dt.size = 0;
7962         kvm_x86_ops->set_idt(vcpu, &dt);
7963
7964         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7965
7966         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7967         cs.base = vcpu->arch.smbase;
7968
7969         ds.selector = 0;
7970         ds.base = 0;
7971
7972         cs.limit    = ds.limit = 0xffffffff;
7973         cs.type     = ds.type = 0x3;
7974         cs.dpl      = ds.dpl = 0;
7975         cs.db       = ds.db = 0;
7976         cs.s        = ds.s = 1;
7977         cs.l        = ds.l = 0;
7978         cs.g        = ds.g = 1;
7979         cs.avl      = ds.avl = 0;
7980         cs.present  = ds.present = 1;
7981         cs.unusable = ds.unusable = 0;
7982         cs.padding  = ds.padding = 0;
7983
7984         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7985         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7986         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7987         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7988         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7989         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7990
7991 #ifdef CONFIG_X86_64
7992         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7993                 kvm_x86_ops->set_efer(vcpu, 0);
7994 #endif
7995
7996         kvm_update_cpuid(vcpu);
7997         kvm_mmu_reset_context(vcpu);
7998 }
7999
8000 static void process_smi(struct kvm_vcpu *vcpu)
8001 {
8002         vcpu->arch.smi_pending = true;
8003         kvm_make_request(KVM_REQ_EVENT, vcpu);
8004 }
8005
8006 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8007                                        unsigned long *vcpu_bitmap)
8008 {
8009         cpumask_var_t cpus;
8010
8011         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8012
8013         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8014                                     vcpu_bitmap, cpus);
8015
8016         free_cpumask_var(cpus);
8017 }
8018
8019 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8020 {
8021         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8022 }
8023
8024 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8025 {
8026         if (!lapic_in_kernel(vcpu))
8027                 return;
8028
8029         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8030         kvm_apic_update_apicv(vcpu);
8031         kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
8032 }
8033 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8034
8035 /*
8036  * NOTE: Do not hold any lock prior to calling this.
8037  *
8038  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8039  * locked, because it calls __x86_set_memory_region() which does
8040  * synchronize_srcu(&kvm->srcu).
8041  */
8042 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8043 {
8044         if (!kvm_x86_ops->check_apicv_inhibit_reasons ||
8045             !kvm_x86_ops->check_apicv_inhibit_reasons(bit))
8046                 return;
8047
8048         if (activate) {
8049                 if (!test_and_clear_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
8050                     !kvm_apicv_activated(kvm))
8051                         return;
8052         } else {
8053                 if (test_and_set_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
8054                     kvm_apicv_activated(kvm))
8055                         return;
8056         }
8057
8058         trace_kvm_apicv_update_request(activate, bit);
8059         if (kvm_x86_ops->pre_update_apicv_exec_ctrl)
8060                 kvm_x86_ops->pre_update_apicv_exec_ctrl(kvm, activate);
8061         kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8062 }
8063 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8064
8065 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8066 {
8067         if (!kvm_apic_present(vcpu))
8068                 return;
8069
8070         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8071
8072         if (irqchip_split(vcpu->kvm))
8073                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8074         else {
8075                 if (vcpu->arch.apicv_active)
8076                         kvm_x86_ops->sync_pir_to_irr(vcpu);
8077                 if (ioapic_in_kernel(vcpu->kvm))
8078                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8079         }
8080
8081         if (is_guest_mode(vcpu))
8082                 vcpu->arch.load_eoi_exitmap_pending = true;
8083         else
8084                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8085 }
8086
8087 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8088 {
8089         u64 eoi_exit_bitmap[4];
8090
8091         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8092                 return;
8093
8094         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8095                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8096         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8097 }
8098
8099 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8100                 unsigned long start, unsigned long end,
8101                 bool blockable)
8102 {
8103         unsigned long apic_address;
8104
8105         /*
8106          * The physical address of apic access page is stored in the VMCS.
8107          * Update it when it becomes invalid.
8108          */
8109         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8110         if (start <= apic_address && apic_address < end)
8111                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8112
8113         return 0;
8114 }
8115
8116 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8117 {
8118         struct page *page = NULL;
8119
8120         if (!lapic_in_kernel(vcpu))
8121                 return;
8122
8123         if (!kvm_x86_ops->set_apic_access_page_addr)
8124                 return;
8125
8126         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8127         if (is_error_page(page))
8128                 return;
8129         kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8130
8131         /*
8132          * Do not pin apic access page in memory, the MMU notifier
8133          * will call us again if it is migrated or swapped out.
8134          */
8135         put_page(page);
8136 }
8137
8138 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8139 {
8140         smp_send_reschedule(vcpu->cpu);
8141 }
8142 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8143
8144 /*
8145  * Returns 1 to let vcpu_run() continue the guest execution loop without
8146  * exiting to the userspace.  Otherwise, the value will be returned to the
8147  * userspace.
8148  */
8149 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8150 {
8151         int r;
8152         bool req_int_win =
8153                 dm_request_for_irq_injection(vcpu) &&
8154                 kvm_cpu_accept_dm_intr(vcpu);
8155         enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8156
8157         bool req_immediate_exit = false;
8158
8159         if (kvm_request_pending(vcpu)) {
8160                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8161                         if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8162                                 r = 0;
8163                                 goto out;
8164                         }
8165                 }
8166                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8167                         kvm_mmu_unload(vcpu);
8168                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8169                         __kvm_migrate_timers(vcpu);
8170                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8171                         kvm_gen_update_masterclock(vcpu->kvm);
8172                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8173                         kvm_gen_kvmclock_update(vcpu);
8174                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8175                         r = kvm_guest_time_update(vcpu);
8176                         if (unlikely(r))
8177                                 goto out;
8178                 }
8179                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8180                         kvm_mmu_sync_roots(vcpu);
8181                 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
8182                         kvm_mmu_load_cr3(vcpu);
8183                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8184                         kvm_vcpu_flush_tlb(vcpu, true);
8185                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8186                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8187                         r = 0;
8188                         goto out;
8189                 }
8190                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8191                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8192                         vcpu->mmio_needed = 0;
8193                         r = 0;
8194                         goto out;
8195                 }
8196                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8197                         /* Page is swapped out. Do synthetic halt */
8198                         vcpu->arch.apf.halted = true;
8199                         r = 1;
8200                         goto out;
8201                 }
8202                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8203                         record_steal_time(vcpu);
8204                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8205                         process_smi(vcpu);
8206                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8207                         process_nmi(vcpu);
8208                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8209                         kvm_pmu_handle_event(vcpu);
8210                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8211                         kvm_pmu_deliver_pmi(vcpu);
8212                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8213                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8214                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8215                                      vcpu->arch.ioapic_handled_vectors)) {
8216                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8217                                 vcpu->run->eoi.vector =
8218                                                 vcpu->arch.pending_ioapic_eoi;
8219                                 r = 0;
8220                                 goto out;
8221                         }
8222                 }
8223                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8224                         vcpu_scan_ioapic(vcpu);
8225                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8226                         vcpu_load_eoi_exitmap(vcpu);
8227                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8228                         kvm_vcpu_reload_apic_access_page(vcpu);
8229                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8230                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8231                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8232                         r = 0;
8233                         goto out;
8234                 }
8235                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8236                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8237                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8238                         r = 0;
8239                         goto out;
8240                 }
8241                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8242                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8243                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8244                         r = 0;
8245                         goto out;
8246                 }
8247
8248                 /*
8249                  * KVM_REQ_HV_STIMER has to be processed after
8250                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8251                  * depend on the guest clock being up-to-date
8252                  */
8253                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8254                         kvm_hv_process_stimers(vcpu);
8255                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8256                         kvm_vcpu_update_apicv(vcpu);
8257         }
8258
8259         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8260                 ++vcpu->stat.req_event;
8261                 kvm_apic_accept_events(vcpu);
8262                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8263                         r = 1;
8264                         goto out;
8265                 }
8266
8267                 if (inject_pending_event(vcpu, req_int_win) != 0)
8268                         req_immediate_exit = true;
8269                 else {
8270                         /* Enable SMI/NMI/IRQ window open exits if needed.
8271                          *
8272                          * SMIs have three cases:
8273                          * 1) They can be nested, and then there is nothing to
8274                          *    do here because RSM will cause a vmexit anyway.
8275                          * 2) There is an ISA-specific reason why SMI cannot be
8276                          *    injected, and the moment when this changes can be
8277                          *    intercepted.
8278                          * 3) Or the SMI can be pending because
8279                          *    inject_pending_event has completed the injection
8280                          *    of an IRQ or NMI from the previous vmexit, and
8281                          *    then we request an immediate exit to inject the
8282                          *    SMI.
8283                          */
8284                         if (vcpu->arch.smi_pending && !is_smm(vcpu))
8285                                 if (!kvm_x86_ops->enable_smi_window(vcpu))
8286                                         req_immediate_exit = true;
8287                         if (vcpu->arch.nmi_pending)
8288                                 kvm_x86_ops->enable_nmi_window(vcpu);
8289                         if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8290                                 kvm_x86_ops->enable_irq_window(vcpu);
8291                         WARN_ON(vcpu->arch.exception.pending);
8292                 }
8293
8294                 if (kvm_lapic_enabled(vcpu)) {
8295                         update_cr8_intercept(vcpu);
8296                         kvm_lapic_sync_to_vapic(vcpu);
8297                 }
8298         }
8299
8300         r = kvm_mmu_reload(vcpu);
8301         if (unlikely(r)) {
8302                 goto cancel_injection;
8303         }
8304
8305         preempt_disable();
8306
8307         kvm_x86_ops->prepare_guest_switch(vcpu);
8308
8309         /*
8310          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8311          * IPI are then delayed after guest entry, which ensures that they
8312          * result in virtual interrupt delivery.
8313          */
8314         local_irq_disable();
8315         vcpu->mode = IN_GUEST_MODE;
8316
8317         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8318
8319         /*
8320          * 1) We should set ->mode before checking ->requests.  Please see
8321          * the comment in kvm_vcpu_exiting_guest_mode().
8322          *
8323          * 2) For APICv, we should set ->mode before checking PID.ON. This
8324          * pairs with the memory barrier implicit in pi_test_and_set_on
8325          * (see vmx_deliver_posted_interrupt).
8326          *
8327          * 3) This also orders the write to mode from any reads to the page
8328          * tables done while the VCPU is running.  Please see the comment
8329          * in kvm_flush_remote_tlbs.
8330          */
8331         smp_mb__after_srcu_read_unlock();
8332
8333         /*
8334          * This handles the case where a posted interrupt was
8335          * notified with kvm_vcpu_kick.
8336          */
8337         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8338                 kvm_x86_ops->sync_pir_to_irr(vcpu);
8339
8340         if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8341             || need_resched() || signal_pending(current)) {
8342                 vcpu->mode = OUTSIDE_GUEST_MODE;
8343                 smp_wmb();
8344                 local_irq_enable();
8345                 preempt_enable();
8346                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8347                 r = 1;
8348                 goto cancel_injection;
8349         }
8350
8351         if (req_immediate_exit) {
8352                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8353                 kvm_x86_ops->request_immediate_exit(vcpu);
8354         }
8355
8356         trace_kvm_entry(vcpu->vcpu_id);
8357         guest_enter_irqoff();
8358
8359         fpregs_assert_state_consistent();
8360         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8361                 switch_fpu_return();
8362
8363         if (unlikely(vcpu->arch.switch_db_regs)) {
8364                 set_debugreg(0, 7);
8365                 set_debugreg(vcpu->arch.eff_db[0], 0);
8366                 set_debugreg(vcpu->arch.eff_db[1], 1);
8367                 set_debugreg(vcpu->arch.eff_db[2], 2);
8368                 set_debugreg(vcpu->arch.eff_db[3], 3);
8369                 set_debugreg(vcpu->arch.dr6, 6);
8370                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8371         }
8372
8373         kvm_x86_ops->run(vcpu);
8374
8375         /*
8376          * Do this here before restoring debug registers on the host.  And
8377          * since we do this before handling the vmexit, a DR access vmexit
8378          * can (a) read the correct value of the debug registers, (b) set
8379          * KVM_DEBUGREG_WONT_EXIT again.
8380          */
8381         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8382                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8383                 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8384                 kvm_update_dr0123(vcpu);
8385                 kvm_update_dr6(vcpu);
8386                 kvm_update_dr7(vcpu);
8387                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8388         }
8389
8390         /*
8391          * If the guest has used debug registers, at least dr7
8392          * will be disabled while returning to the host.
8393          * If we don't have active breakpoints in the host, we don't
8394          * care about the messed up debug address registers. But if
8395          * we have some of them active, restore the old state.
8396          */
8397         if (hw_breakpoint_active())
8398                 hw_breakpoint_restore();
8399
8400         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8401
8402         vcpu->mode = OUTSIDE_GUEST_MODE;
8403         smp_wmb();
8404
8405         kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
8406
8407         /*
8408          * Consume any pending interrupts, including the possible source of
8409          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8410          * An instruction is required after local_irq_enable() to fully unblock
8411          * interrupts on processors that implement an interrupt shadow, the
8412          * stat.exits increment will do nicely.
8413          */
8414         kvm_before_interrupt(vcpu);
8415         local_irq_enable();
8416         ++vcpu->stat.exits;
8417         local_irq_disable();
8418         kvm_after_interrupt(vcpu);
8419
8420         guest_exit_irqoff();
8421         if (lapic_in_kernel(vcpu)) {
8422                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8423                 if (delta != S64_MIN) {
8424                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8425                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8426                 }
8427         }
8428
8429         local_irq_enable();
8430         preempt_enable();
8431
8432         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8433
8434         /*
8435          * Profile KVM exit RIPs:
8436          */
8437         if (unlikely(prof_on == KVM_PROFILING)) {
8438                 unsigned long rip = kvm_rip_read(vcpu);
8439                 profile_hit(KVM_PROFILING, (void *)rip);
8440         }
8441
8442         if (unlikely(vcpu->arch.tsc_always_catchup))
8443                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8444
8445         if (vcpu->arch.apic_attention)
8446                 kvm_lapic_sync_from_vapic(vcpu);
8447
8448         vcpu->arch.gpa_available = false;
8449         r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
8450         return r;
8451
8452 cancel_injection:
8453         kvm_x86_ops->cancel_injection(vcpu);
8454         if (unlikely(vcpu->arch.apic_attention))
8455                 kvm_lapic_sync_from_vapic(vcpu);
8456 out:
8457         return r;
8458 }
8459
8460 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8461 {
8462         if (!kvm_arch_vcpu_runnable(vcpu) &&
8463             (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8464                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8465                 kvm_vcpu_block(vcpu);
8466                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8467
8468                 if (kvm_x86_ops->post_block)
8469                         kvm_x86_ops->post_block(vcpu);
8470
8471                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8472                         return 1;
8473         }
8474
8475         kvm_apic_accept_events(vcpu);
8476         switch(vcpu->arch.mp_state) {
8477         case KVM_MP_STATE_HALTED:
8478                 vcpu->arch.pv.pv_unhalted = false;
8479                 vcpu->arch.mp_state =
8480                         KVM_MP_STATE_RUNNABLE;
8481                 /* fall through */
8482         case KVM_MP_STATE_RUNNABLE:
8483                 vcpu->arch.apf.halted = false;
8484                 break;
8485         case KVM_MP_STATE_INIT_RECEIVED:
8486                 break;
8487         default:
8488                 return -EINTR;
8489                 break;
8490         }
8491         return 1;
8492 }
8493
8494 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8495 {
8496         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8497                 kvm_x86_ops->check_nested_events(vcpu, false);
8498
8499         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8500                 !vcpu->arch.apf.halted);
8501 }
8502
8503 static int vcpu_run(struct kvm_vcpu *vcpu)
8504 {
8505         int r;
8506         struct kvm *kvm = vcpu->kvm;
8507
8508         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8509         vcpu->arch.l1tf_flush_l1d = true;
8510
8511         for (;;) {
8512                 if (kvm_vcpu_running(vcpu)) {
8513                         r = vcpu_enter_guest(vcpu);
8514                 } else {
8515                         r = vcpu_block(kvm, vcpu);
8516                 }
8517
8518                 if (r <= 0)
8519                         break;
8520
8521                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8522                 if (kvm_cpu_has_pending_timer(vcpu))
8523                         kvm_inject_pending_timer_irqs(vcpu);
8524
8525                 if (dm_request_for_irq_injection(vcpu) &&
8526                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8527                         r = 0;
8528                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8529                         ++vcpu->stat.request_irq_exits;
8530                         break;
8531                 }
8532
8533                 kvm_check_async_pf_completion(vcpu);
8534
8535                 if (signal_pending(current)) {
8536                         r = -EINTR;
8537                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8538                         ++vcpu->stat.signal_exits;
8539                         break;
8540                 }
8541                 if (need_resched()) {
8542                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8543                         cond_resched();
8544                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8545                 }
8546         }
8547
8548         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8549
8550         return r;
8551 }
8552
8553 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8554 {
8555         int r;
8556
8557         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8558         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8559         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8560         return r;
8561 }
8562
8563 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8564 {
8565         BUG_ON(!vcpu->arch.pio.count);
8566
8567         return complete_emulated_io(vcpu);
8568 }
8569
8570 /*
8571  * Implements the following, as a state machine:
8572  *
8573  * read:
8574  *   for each fragment
8575  *     for each mmio piece in the fragment
8576  *       write gpa, len
8577  *       exit
8578  *       copy data
8579  *   execute insn
8580  *
8581  * write:
8582  *   for each fragment
8583  *     for each mmio piece in the fragment
8584  *       write gpa, len
8585  *       copy data
8586  *       exit
8587  */
8588 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8589 {
8590         struct kvm_run *run = vcpu->run;
8591         struct kvm_mmio_fragment *frag;
8592         unsigned len;
8593
8594         BUG_ON(!vcpu->mmio_needed);
8595
8596         /* Complete previous fragment */
8597         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8598         len = min(8u, frag->len);
8599         if (!vcpu->mmio_is_write)
8600                 memcpy(frag->data, run->mmio.data, len);
8601
8602         if (frag->len <= 8) {
8603                 /* Switch to the next fragment. */
8604                 frag++;
8605                 vcpu->mmio_cur_fragment++;
8606         } else {
8607                 /* Go forward to the next mmio piece. */
8608                 frag->data += len;
8609                 frag->gpa += len;
8610                 frag->len -= len;
8611         }
8612
8613         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8614                 vcpu->mmio_needed = 0;
8615
8616                 /* FIXME: return into emulator if single-stepping.  */
8617                 if (vcpu->mmio_is_write)
8618                         return 1;
8619                 vcpu->mmio_read_completed = 1;
8620                 return complete_emulated_io(vcpu);
8621         }
8622
8623         run->exit_reason = KVM_EXIT_MMIO;
8624         run->mmio.phys_addr = frag->gpa;
8625         if (vcpu->mmio_is_write)
8626                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8627         run->mmio.len = min(8u, frag->len);
8628         run->mmio.is_write = vcpu->mmio_is_write;
8629         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8630         return 0;
8631 }
8632
8633 static void kvm_save_current_fpu(struct fpu *fpu)
8634 {
8635         /*
8636          * If the target FPU state is not resident in the CPU registers, just
8637          * memcpy() from current, else save CPU state directly to the target.
8638          */
8639         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8640                 memcpy(&fpu->state, &current->thread.fpu.state,
8641                        fpu_kernel_xstate_size);
8642         else
8643                 copy_fpregs_to_fpstate(fpu);
8644 }
8645
8646 /* Swap (qemu) user FPU context for the guest FPU context. */
8647 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8648 {
8649         fpregs_lock();
8650
8651         kvm_save_current_fpu(vcpu->arch.user_fpu);
8652
8653         /* PKRU is separately restored in kvm_x86_ops->run.  */
8654         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8655                                 ~XFEATURE_MASK_PKRU);
8656
8657         fpregs_mark_activate();
8658         fpregs_unlock();
8659
8660         trace_kvm_fpu(1);
8661 }
8662
8663 /* When vcpu_run ends, restore user space FPU context. */
8664 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8665 {
8666         fpregs_lock();
8667
8668         kvm_save_current_fpu(vcpu->arch.guest_fpu);
8669
8670         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8671
8672         fpregs_mark_activate();
8673         fpregs_unlock();
8674
8675         ++vcpu->stat.fpu_reload;
8676         trace_kvm_fpu(0);
8677 }
8678
8679 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8680 {
8681         int r;
8682
8683         vcpu_load(vcpu);
8684         kvm_sigset_activate(vcpu);
8685         kvm_load_guest_fpu(vcpu);
8686
8687         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8688                 if (kvm_run->immediate_exit) {
8689                         r = -EINTR;
8690                         goto out;
8691                 }
8692                 kvm_vcpu_block(vcpu);
8693                 kvm_apic_accept_events(vcpu);
8694                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8695                 r = -EAGAIN;
8696                 if (signal_pending(current)) {
8697                         r = -EINTR;
8698                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8699                         ++vcpu->stat.signal_exits;
8700                 }
8701                 goto out;
8702         }
8703
8704         if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8705                 r = -EINVAL;
8706                 goto out;
8707         }
8708
8709         if (vcpu->run->kvm_dirty_regs) {
8710                 r = sync_regs(vcpu);
8711                 if (r != 0)
8712                         goto out;
8713         }
8714
8715         /* re-sync apic's tpr */
8716         if (!lapic_in_kernel(vcpu)) {
8717                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8718                         r = -EINVAL;
8719                         goto out;
8720                 }
8721         }
8722
8723         if (unlikely(vcpu->arch.complete_userspace_io)) {
8724                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8725                 vcpu->arch.complete_userspace_io = NULL;
8726                 r = cui(vcpu);
8727                 if (r <= 0)
8728                         goto out;
8729         } else
8730                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8731
8732         if (kvm_run->immediate_exit)
8733                 r = -EINTR;
8734         else
8735                 r = vcpu_run(vcpu);
8736
8737 out:
8738         kvm_put_guest_fpu(vcpu);
8739         if (vcpu->run->kvm_valid_regs)
8740                 store_regs(vcpu);
8741         post_kvm_run_save(vcpu);
8742         kvm_sigset_deactivate(vcpu);
8743
8744         vcpu_put(vcpu);
8745         return r;
8746 }
8747
8748 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8749 {
8750         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8751                 /*
8752                  * We are here if userspace calls get_regs() in the middle of
8753                  * instruction emulation. Registers state needs to be copied
8754                  * back from emulation context to vcpu. Userspace shouldn't do
8755                  * that usually, but some bad designed PV devices (vmware
8756                  * backdoor interface) need this to work
8757                  */
8758                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8759                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8760         }
8761         regs->rax = kvm_rax_read(vcpu);
8762         regs->rbx = kvm_rbx_read(vcpu);
8763         regs->rcx = kvm_rcx_read(vcpu);
8764         regs->rdx = kvm_rdx_read(vcpu);
8765         regs->rsi = kvm_rsi_read(vcpu);
8766         regs->rdi = kvm_rdi_read(vcpu);
8767         regs->rsp = kvm_rsp_read(vcpu);
8768         regs->rbp = kvm_rbp_read(vcpu);
8769 #ifdef CONFIG_X86_64
8770         regs->r8 = kvm_r8_read(vcpu);
8771         regs->r9 = kvm_r9_read(vcpu);
8772         regs->r10 = kvm_r10_read(vcpu);
8773         regs->r11 = kvm_r11_read(vcpu);
8774         regs->r12 = kvm_r12_read(vcpu);
8775         regs->r13 = kvm_r13_read(vcpu);
8776         regs->r14 = kvm_r14_read(vcpu);
8777         regs->r15 = kvm_r15_read(vcpu);
8778 #endif
8779
8780         regs->rip = kvm_rip_read(vcpu);
8781         regs->rflags = kvm_get_rflags(vcpu);
8782 }
8783
8784 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8785 {
8786         vcpu_load(vcpu);
8787         __get_regs(vcpu, regs);
8788         vcpu_put(vcpu);
8789         return 0;
8790 }
8791
8792 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8793 {
8794         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8795         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8796
8797         kvm_rax_write(vcpu, regs->rax);
8798         kvm_rbx_write(vcpu, regs->rbx);
8799         kvm_rcx_write(vcpu, regs->rcx);
8800         kvm_rdx_write(vcpu, regs->rdx);
8801         kvm_rsi_write(vcpu, regs->rsi);
8802         kvm_rdi_write(vcpu, regs->rdi);
8803         kvm_rsp_write(vcpu, regs->rsp);
8804         kvm_rbp_write(vcpu, regs->rbp);
8805 #ifdef CONFIG_X86_64
8806         kvm_r8_write(vcpu, regs->r8);
8807         kvm_r9_write(vcpu, regs->r9);
8808         kvm_r10_write(vcpu, regs->r10);
8809         kvm_r11_write(vcpu, regs->r11);
8810         kvm_r12_write(vcpu, regs->r12);
8811         kvm_r13_write(vcpu, regs->r13);
8812         kvm_r14_write(vcpu, regs->r14);
8813         kvm_r15_write(vcpu, regs->r15);
8814 #endif
8815
8816         kvm_rip_write(vcpu, regs->rip);
8817         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8818
8819         vcpu->arch.exception.pending = false;
8820
8821         kvm_make_request(KVM_REQ_EVENT, vcpu);
8822 }
8823
8824 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8825 {
8826         vcpu_load(vcpu);
8827         __set_regs(vcpu, regs);
8828         vcpu_put(vcpu);
8829         return 0;
8830 }
8831
8832 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8833 {
8834         struct kvm_segment cs;
8835
8836         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8837         *db = cs.db;
8838         *l = cs.l;
8839 }
8840 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8841
8842 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8843 {
8844         struct desc_ptr dt;
8845
8846         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8847         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8848         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8849         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8850         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8851         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8852
8853         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8854         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8855
8856         kvm_x86_ops->get_idt(vcpu, &dt);
8857         sregs->idt.limit = dt.size;
8858         sregs->idt.base = dt.address;
8859         kvm_x86_ops->get_gdt(vcpu, &dt);
8860         sregs->gdt.limit = dt.size;
8861         sregs->gdt.base = dt.address;
8862
8863         sregs->cr0 = kvm_read_cr0(vcpu);
8864         sregs->cr2 = vcpu->arch.cr2;
8865         sregs->cr3 = kvm_read_cr3(vcpu);
8866         sregs->cr4 = kvm_read_cr4(vcpu);
8867         sregs->cr8 = kvm_get_cr8(vcpu);
8868         sregs->efer = vcpu->arch.efer;
8869         sregs->apic_base = kvm_get_apic_base(vcpu);
8870
8871         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8872
8873         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8874                 set_bit(vcpu->arch.interrupt.nr,
8875                         (unsigned long *)sregs->interrupt_bitmap);
8876 }
8877
8878 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8879                                   struct kvm_sregs *sregs)
8880 {
8881         vcpu_load(vcpu);
8882         __get_sregs(vcpu, sregs);
8883         vcpu_put(vcpu);
8884         return 0;
8885 }
8886
8887 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8888                                     struct kvm_mp_state *mp_state)
8889 {
8890         vcpu_load(vcpu);
8891         if (kvm_mpx_supported())
8892                 kvm_load_guest_fpu(vcpu);
8893
8894         kvm_apic_accept_events(vcpu);
8895         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8896                                         vcpu->arch.pv.pv_unhalted)
8897                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8898         else
8899                 mp_state->mp_state = vcpu->arch.mp_state;
8900
8901         if (kvm_mpx_supported())
8902                 kvm_put_guest_fpu(vcpu);
8903         vcpu_put(vcpu);
8904         return 0;
8905 }
8906
8907 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8908                                     struct kvm_mp_state *mp_state)
8909 {
8910         int ret = -EINVAL;
8911
8912         vcpu_load(vcpu);
8913
8914         if (!lapic_in_kernel(vcpu) &&
8915             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8916                 goto out;
8917
8918         /*
8919          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8920          * INIT state; latched init should be reported using
8921          * KVM_SET_VCPU_EVENTS, so reject it here.
8922          */
8923         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8924             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8925              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8926                 goto out;
8927
8928         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8929                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8930                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8931         } else
8932                 vcpu->arch.mp_state = mp_state->mp_state;
8933         kvm_make_request(KVM_REQ_EVENT, vcpu);
8934
8935         ret = 0;
8936 out:
8937         vcpu_put(vcpu);
8938         return ret;
8939 }
8940
8941 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8942                     int reason, bool has_error_code, u32 error_code)
8943 {
8944         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8945         int ret;
8946
8947         init_emulate_ctxt(vcpu);
8948
8949         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8950                                    has_error_code, error_code);
8951         if (ret) {
8952                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8953                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8954                 vcpu->run->internal.ndata = 0;
8955                 return 0;
8956         }
8957
8958         kvm_rip_write(vcpu, ctxt->eip);
8959         kvm_set_rflags(vcpu, ctxt->eflags);
8960         return 1;
8961 }
8962 EXPORT_SYMBOL_GPL(kvm_task_switch);
8963
8964 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8965 {
8966         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8967                 /*
8968                  * When EFER.LME and CR0.PG are set, the processor is in
8969                  * 64-bit mode (though maybe in a 32-bit code segment).
8970                  * CR4.PAE and EFER.LMA must be set.
8971                  */
8972                 if (!(sregs->cr4 & X86_CR4_PAE)
8973                     || !(sregs->efer & EFER_LMA))
8974                         return -EINVAL;
8975         } else {
8976                 /*
8977                  * Not in 64-bit mode: EFER.LMA is clear and the code
8978                  * segment cannot be 64-bit.
8979                  */
8980                 if (sregs->efer & EFER_LMA || sregs->cs.l)
8981                         return -EINVAL;
8982         }
8983
8984         return kvm_valid_cr4(vcpu, sregs->cr4);
8985 }
8986
8987 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8988 {
8989         struct msr_data apic_base_msr;
8990         int mmu_reset_needed = 0;
8991         int cpuid_update_needed = 0;
8992         int pending_vec, max_bits, idx;
8993         struct desc_ptr dt;
8994         int ret = -EINVAL;
8995
8996         if (kvm_valid_sregs(vcpu, sregs))
8997                 goto out;
8998
8999         apic_base_msr.data = sregs->apic_base;
9000         apic_base_msr.host_initiated = true;
9001         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9002                 goto out;
9003
9004         dt.size = sregs->idt.limit;
9005         dt.address = sregs->idt.base;
9006         kvm_x86_ops->set_idt(vcpu, &dt);
9007         dt.size = sregs->gdt.limit;
9008         dt.address = sregs->gdt.base;
9009         kvm_x86_ops->set_gdt(vcpu, &dt);
9010
9011         vcpu->arch.cr2 = sregs->cr2;
9012         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9013         vcpu->arch.cr3 = sregs->cr3;
9014         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9015
9016         kvm_set_cr8(vcpu, sregs->cr8);
9017
9018         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9019         kvm_x86_ops->set_efer(vcpu, sregs->efer);
9020
9021         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9022         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
9023         vcpu->arch.cr0 = sregs->cr0;
9024
9025         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9026         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9027                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9028         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
9029         if (cpuid_update_needed)
9030                 kvm_update_cpuid(vcpu);
9031
9032         idx = srcu_read_lock(&vcpu->kvm->srcu);
9033         if (is_pae_paging(vcpu)) {
9034                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9035                 mmu_reset_needed = 1;
9036         }
9037         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9038
9039         if (mmu_reset_needed)
9040                 kvm_mmu_reset_context(vcpu);
9041
9042         max_bits = KVM_NR_INTERRUPTS;
9043         pending_vec = find_first_bit(
9044                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9045         if (pending_vec < max_bits) {
9046                 kvm_queue_interrupt(vcpu, pending_vec, false);
9047                 pr_debug("Set back pending irq %d\n", pending_vec);
9048         }
9049
9050         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9051         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9052         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9053         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9054         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9055         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9056
9057         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9058         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9059
9060         update_cr8_intercept(vcpu);
9061
9062         /* Older userspace won't unhalt the vcpu on reset. */
9063         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9064             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9065             !is_protmode(vcpu))
9066                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9067
9068         kvm_make_request(KVM_REQ_EVENT, vcpu);
9069
9070         ret = 0;
9071 out:
9072         return ret;
9073 }
9074
9075 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9076                                   struct kvm_sregs *sregs)
9077 {
9078         int ret;
9079
9080         vcpu_load(vcpu);
9081         ret = __set_sregs(vcpu, sregs);
9082         vcpu_put(vcpu);
9083         return ret;
9084 }
9085
9086 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9087                                         struct kvm_guest_debug *dbg)
9088 {
9089         unsigned long rflags;
9090         int i, r;
9091
9092         vcpu_load(vcpu);
9093
9094         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9095                 r = -EBUSY;
9096                 if (vcpu->arch.exception.pending)
9097                         goto out;
9098                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9099                         kvm_queue_exception(vcpu, DB_VECTOR);
9100                 else
9101                         kvm_queue_exception(vcpu, BP_VECTOR);
9102         }
9103
9104         /*
9105          * Read rflags as long as potentially injected trace flags are still
9106          * filtered out.
9107          */
9108         rflags = kvm_get_rflags(vcpu);
9109
9110         vcpu->guest_debug = dbg->control;
9111         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9112                 vcpu->guest_debug = 0;
9113
9114         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9115                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9116                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9117                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9118         } else {
9119                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9120                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9121         }
9122         kvm_update_dr7(vcpu);
9123
9124         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9125                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9126                         get_segment_base(vcpu, VCPU_SREG_CS);
9127
9128         /*
9129          * Trigger an rflags update that will inject or remove the trace
9130          * flags.
9131          */
9132         kvm_set_rflags(vcpu, rflags);
9133
9134         kvm_x86_ops->update_bp_intercept(vcpu);
9135
9136         r = 0;
9137
9138 out:
9139         vcpu_put(vcpu);
9140         return r;
9141 }
9142
9143 /*
9144  * Translate a guest virtual address to a guest physical address.
9145  */
9146 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9147                                     struct kvm_translation *tr)
9148 {
9149         unsigned long vaddr = tr->linear_address;
9150         gpa_t gpa;
9151         int idx;
9152
9153         vcpu_load(vcpu);
9154
9155         idx = srcu_read_lock(&vcpu->kvm->srcu);
9156         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9157         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9158         tr->physical_address = gpa;
9159         tr->valid = gpa != UNMAPPED_GVA;
9160         tr->writeable = 1;
9161         tr->usermode = 0;
9162
9163         vcpu_put(vcpu);
9164         return 0;
9165 }
9166
9167 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9168 {
9169         struct fxregs_state *fxsave;
9170
9171         vcpu_load(vcpu);
9172
9173         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9174         memcpy(fpu->fpr, fxsave->st_space, 128);
9175         fpu->fcw = fxsave->cwd;
9176         fpu->fsw = fxsave->swd;
9177         fpu->ftwx = fxsave->twd;
9178         fpu->last_opcode = fxsave->fop;
9179         fpu->last_ip = fxsave->rip;
9180         fpu->last_dp = fxsave->rdp;
9181         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9182
9183         vcpu_put(vcpu);
9184         return 0;
9185 }
9186
9187 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9188 {
9189         struct fxregs_state *fxsave;
9190
9191         vcpu_load(vcpu);
9192
9193         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9194
9195         memcpy(fxsave->st_space, fpu->fpr, 128);
9196         fxsave->cwd = fpu->fcw;
9197         fxsave->swd = fpu->fsw;
9198         fxsave->twd = fpu->ftwx;
9199         fxsave->fop = fpu->last_opcode;
9200         fxsave->rip = fpu->last_ip;
9201         fxsave->rdp = fpu->last_dp;
9202         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9203
9204         vcpu_put(vcpu);
9205         return 0;
9206 }
9207
9208 static void store_regs(struct kvm_vcpu *vcpu)
9209 {
9210         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9211
9212         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9213                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9214
9215         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9216                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9217
9218         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9219                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9220                                 vcpu, &vcpu->run->s.regs.events);
9221 }
9222
9223 static int sync_regs(struct kvm_vcpu *vcpu)
9224 {
9225         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9226                 return -EINVAL;
9227
9228         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9229                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9230                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9231         }
9232         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9233                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9234                         return -EINVAL;
9235                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9236         }
9237         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9238                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9239                                 vcpu, &vcpu->run->s.regs.events))
9240                         return -EINVAL;
9241                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9242         }
9243
9244         return 0;
9245 }
9246
9247 static void fx_init(struct kvm_vcpu *vcpu)
9248 {
9249         fpstate_init(&vcpu->arch.guest_fpu->state);
9250         if (boot_cpu_has(X86_FEATURE_XSAVES))
9251                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9252                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9253
9254         /*
9255          * Ensure guest xcr0 is valid for loading
9256          */
9257         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9258
9259         vcpu->arch.cr0 |= X86_CR0_ET;
9260 }
9261
9262 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9263 {
9264         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9265                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9266                              "guest TSC will not be reliable\n");
9267
9268         return 0;
9269 }
9270
9271 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9272 {
9273         struct page *page;
9274         int r;
9275
9276         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9277         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9278                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9279         else
9280                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9281
9282         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9283
9284         r = kvm_mmu_create(vcpu);
9285         if (r < 0)
9286                 return r;
9287
9288         if (irqchip_in_kernel(vcpu->kvm)) {
9289                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9290                 if (r < 0)
9291                         goto fail_mmu_destroy;
9292                 if (kvm_apicv_activated(vcpu->kvm))
9293                         vcpu->arch.apicv_active = true;
9294         } else
9295                 static_key_slow_inc(&kvm_no_apic_vcpu);
9296
9297         r = -ENOMEM;
9298
9299         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9300         if (!page)
9301                 goto fail_free_lapic;
9302         vcpu->arch.pio_data = page_address(page);
9303
9304         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9305                                        GFP_KERNEL_ACCOUNT);
9306         if (!vcpu->arch.mce_banks)
9307                 goto fail_free_pio_data;
9308         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9309
9310         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9311                                 GFP_KERNEL_ACCOUNT))
9312                 goto fail_free_mce_banks;
9313
9314         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9315                                                 GFP_KERNEL_ACCOUNT);
9316         if (!vcpu->arch.user_fpu) {
9317                 pr_err("kvm: failed to allocate userspace's fpu\n");
9318                 goto free_wbinvd_dirty_mask;
9319         }
9320
9321         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9322                                                  GFP_KERNEL_ACCOUNT);
9323         if (!vcpu->arch.guest_fpu) {
9324                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9325                 goto free_user_fpu;
9326         }
9327         fx_init(vcpu);
9328
9329         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9330
9331         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9332
9333         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9334
9335         kvm_async_pf_hash_reset(vcpu);
9336         kvm_pmu_init(vcpu);
9337
9338         vcpu->arch.pending_external_vector = -1;
9339         vcpu->arch.preempted_in_kernel = false;
9340
9341         kvm_hv_vcpu_init(vcpu);
9342
9343         r = kvm_x86_ops->vcpu_create(vcpu);
9344         if (r)
9345                 goto free_guest_fpu;
9346
9347         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9348         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9349         kvm_vcpu_mtrr_init(vcpu);
9350         vcpu_load(vcpu);
9351         kvm_vcpu_reset(vcpu, false);
9352         kvm_init_mmu(vcpu, false);
9353         vcpu_put(vcpu);
9354         return 0;
9355
9356 free_guest_fpu:
9357         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9358 free_user_fpu:
9359         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9360 free_wbinvd_dirty_mask:
9361         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9362 fail_free_mce_banks:
9363         kfree(vcpu->arch.mce_banks);
9364 fail_free_pio_data:
9365         free_page((unsigned long)vcpu->arch.pio_data);
9366 fail_free_lapic:
9367         kvm_free_lapic(vcpu);
9368 fail_mmu_destroy:
9369         kvm_mmu_destroy(vcpu);
9370         return r;
9371 }
9372
9373 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9374 {
9375         struct msr_data msr;
9376         struct kvm *kvm = vcpu->kvm;
9377
9378         kvm_hv_vcpu_postcreate(vcpu);
9379
9380         if (mutex_lock_killable(&vcpu->mutex))
9381                 return;
9382         vcpu_load(vcpu);
9383         msr.data = 0x0;
9384         msr.index = MSR_IA32_TSC;
9385         msr.host_initiated = true;
9386         kvm_write_tsc(vcpu, &msr);
9387         vcpu_put(vcpu);
9388
9389         /* poll control enabled by default */
9390         vcpu->arch.msr_kvm_poll_control = 1;
9391
9392         mutex_unlock(&vcpu->mutex);
9393
9394         if (!kvmclock_periodic_sync)
9395                 return;
9396
9397         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9398                                         KVMCLOCK_SYNC_PERIOD);
9399 }
9400
9401 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9402 {
9403         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9404         int idx;
9405
9406         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9407
9408         kvmclock_reset(vcpu);
9409
9410         kvm_x86_ops->vcpu_free(vcpu);
9411
9412         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9413         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9414         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9415
9416         kvm_hv_vcpu_uninit(vcpu);
9417         kvm_pmu_destroy(vcpu);
9418         kfree(vcpu->arch.mce_banks);
9419         kvm_free_lapic(vcpu);
9420         idx = srcu_read_lock(&vcpu->kvm->srcu);
9421         kvm_mmu_destroy(vcpu);
9422         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9423         free_page((unsigned long)vcpu->arch.pio_data);
9424         if (!lapic_in_kernel(vcpu))
9425                 static_key_slow_dec(&kvm_no_apic_vcpu);
9426 }
9427
9428 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9429 {
9430         kvm_lapic_reset(vcpu, init_event);
9431
9432         vcpu->arch.hflags = 0;
9433
9434         vcpu->arch.smi_pending = 0;
9435         vcpu->arch.smi_count = 0;
9436         atomic_set(&vcpu->arch.nmi_queued, 0);
9437         vcpu->arch.nmi_pending = 0;
9438         vcpu->arch.nmi_injected = false;
9439         kvm_clear_interrupt_queue(vcpu);
9440         kvm_clear_exception_queue(vcpu);
9441
9442         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9443         kvm_update_dr0123(vcpu);
9444         vcpu->arch.dr6 = DR6_INIT;
9445         kvm_update_dr6(vcpu);
9446         vcpu->arch.dr7 = DR7_FIXED_1;
9447         kvm_update_dr7(vcpu);
9448
9449         vcpu->arch.cr2 = 0;
9450
9451         kvm_make_request(KVM_REQ_EVENT, vcpu);
9452         vcpu->arch.apf.msr_val = 0;
9453         vcpu->arch.st.msr_val = 0;
9454
9455         kvmclock_reset(vcpu);
9456
9457         kvm_clear_async_pf_completion_queue(vcpu);
9458         kvm_async_pf_hash_reset(vcpu);
9459         vcpu->arch.apf.halted = false;
9460
9461         if (kvm_mpx_supported()) {
9462                 void *mpx_state_buffer;
9463
9464                 /*
9465                  * To avoid have the INIT path from kvm_apic_has_events() that be
9466                  * called with loaded FPU and does not let userspace fix the state.
9467                  */
9468                 if (init_event)
9469                         kvm_put_guest_fpu(vcpu);
9470                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9471                                         XFEATURE_BNDREGS);
9472                 if (mpx_state_buffer)
9473                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9474                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9475                                         XFEATURE_BNDCSR);
9476                 if (mpx_state_buffer)
9477                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9478                 if (init_event)
9479                         kvm_load_guest_fpu(vcpu);
9480         }
9481
9482         if (!init_event) {
9483                 kvm_pmu_reset(vcpu);
9484                 vcpu->arch.smbase = 0x30000;
9485
9486                 vcpu->arch.msr_misc_features_enables = 0;
9487
9488                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9489         }
9490
9491         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9492         vcpu->arch.regs_avail = ~0;
9493         vcpu->arch.regs_dirty = ~0;
9494
9495         vcpu->arch.ia32_xss = 0;
9496
9497         kvm_x86_ops->vcpu_reset(vcpu, init_event);
9498 }
9499
9500 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9501 {
9502         struct kvm_segment cs;
9503
9504         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9505         cs.selector = vector << 8;
9506         cs.base = vector << 12;
9507         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9508         kvm_rip_write(vcpu, 0);
9509 }
9510
9511 int kvm_arch_hardware_enable(void)
9512 {
9513         struct kvm *kvm;
9514         struct kvm_vcpu *vcpu;
9515         int i;
9516         int ret;
9517         u64 local_tsc;
9518         u64 max_tsc = 0;
9519         bool stable, backwards_tsc = false;
9520
9521         kvm_shared_msr_cpu_online();
9522         ret = kvm_x86_ops->hardware_enable();
9523         if (ret != 0)
9524                 return ret;
9525
9526         local_tsc = rdtsc();
9527         stable = !kvm_check_tsc_unstable();
9528         list_for_each_entry(kvm, &vm_list, vm_list) {
9529                 kvm_for_each_vcpu(i, vcpu, kvm) {
9530                         if (!stable && vcpu->cpu == smp_processor_id())
9531                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9532                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9533                                 backwards_tsc = true;
9534                                 if (vcpu->arch.last_host_tsc > max_tsc)
9535                                         max_tsc = vcpu->arch.last_host_tsc;
9536                         }
9537                 }
9538         }
9539
9540         /*
9541          * Sometimes, even reliable TSCs go backwards.  This happens on
9542          * platforms that reset TSC during suspend or hibernate actions, but
9543          * maintain synchronization.  We must compensate.  Fortunately, we can
9544          * detect that condition here, which happens early in CPU bringup,
9545          * before any KVM threads can be running.  Unfortunately, we can't
9546          * bring the TSCs fully up to date with real time, as we aren't yet far
9547          * enough into CPU bringup that we know how much real time has actually
9548          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9549          * variables that haven't been updated yet.
9550          *
9551          * So we simply find the maximum observed TSC above, then record the
9552          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9553          * the adjustment will be applied.  Note that we accumulate
9554          * adjustments, in case multiple suspend cycles happen before some VCPU
9555          * gets a chance to run again.  In the event that no KVM threads get a
9556          * chance to run, we will miss the entire elapsed period, as we'll have
9557          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9558          * loose cycle time.  This isn't too big a deal, since the loss will be
9559          * uniform across all VCPUs (not to mention the scenario is extremely
9560          * unlikely). It is possible that a second hibernate recovery happens
9561          * much faster than a first, causing the observed TSC here to be
9562          * smaller; this would require additional padding adjustment, which is
9563          * why we set last_host_tsc to the local tsc observed here.
9564          *
9565          * N.B. - this code below runs only on platforms with reliable TSC,
9566          * as that is the only way backwards_tsc is set above.  Also note
9567          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9568          * have the same delta_cyc adjustment applied if backwards_tsc
9569          * is detected.  Note further, this adjustment is only done once,
9570          * as we reset last_host_tsc on all VCPUs to stop this from being
9571          * called multiple times (one for each physical CPU bringup).
9572          *
9573          * Platforms with unreliable TSCs don't have to deal with this, they
9574          * will be compensated by the logic in vcpu_load, which sets the TSC to
9575          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9576          * guarantee that they stay in perfect synchronization.
9577          */
9578         if (backwards_tsc) {
9579                 u64 delta_cyc = max_tsc - local_tsc;
9580                 list_for_each_entry(kvm, &vm_list, vm_list) {
9581                         kvm->arch.backwards_tsc_observed = true;
9582                         kvm_for_each_vcpu(i, vcpu, kvm) {
9583                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9584                                 vcpu->arch.last_host_tsc = local_tsc;
9585                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9586                         }
9587
9588                         /*
9589                          * We have to disable TSC offset matching.. if you were
9590                          * booting a VM while issuing an S4 host suspend....
9591                          * you may have some problem.  Solving this issue is
9592                          * left as an exercise to the reader.
9593                          */
9594                         kvm->arch.last_tsc_nsec = 0;
9595                         kvm->arch.last_tsc_write = 0;
9596                 }
9597
9598         }
9599         return 0;
9600 }
9601
9602 void kvm_arch_hardware_disable(void)
9603 {
9604         kvm_x86_ops->hardware_disable();
9605         drop_user_return_notifiers();
9606 }
9607
9608 int kvm_arch_hardware_setup(void)
9609 {
9610         int r;
9611
9612         r = kvm_x86_ops->hardware_setup();
9613         if (r != 0)
9614                 return r;
9615
9616         cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9617
9618         if (kvm_has_tsc_control) {
9619                 /*
9620                  * Make sure the user can only configure tsc_khz values that
9621                  * fit into a signed integer.
9622                  * A min value is not calculated because it will always
9623                  * be 1 on all machines.
9624                  */
9625                 u64 max = min(0x7fffffffULL,
9626                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9627                 kvm_max_guest_tsc_khz = max;
9628
9629                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9630         }
9631
9632         if (boot_cpu_has(X86_FEATURE_XSAVES))
9633                 rdmsrl(MSR_IA32_XSS, host_xss);
9634
9635         kvm_init_msr_list();
9636         return 0;
9637 }
9638
9639 void kvm_arch_hardware_unsetup(void)
9640 {
9641         kvm_x86_ops->hardware_unsetup();
9642 }
9643
9644 int kvm_arch_check_processor_compat(void)
9645 {
9646         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9647
9648         WARN_ON(!irqs_disabled());
9649
9650         if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9651                 return -EIO;
9652
9653         return kvm_x86_ops->check_processor_compatibility();
9654 }
9655
9656 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9657 {
9658         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9659 }
9660 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9661
9662 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9663 {
9664         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9665 }
9666
9667 struct static_key kvm_no_apic_vcpu __read_mostly;
9668 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9669
9670 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9671 {
9672         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9673
9674         vcpu->arch.l1tf_flush_l1d = true;
9675         if (pmu->version && unlikely(pmu->event_count)) {
9676                 pmu->need_cleanup = true;
9677                 kvm_make_request(KVM_REQ_PMU, vcpu);
9678         }
9679         kvm_x86_ops->sched_in(vcpu, cpu);
9680 }
9681
9682 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9683 {
9684         if (type)
9685                 return -EINVAL;
9686
9687         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9688         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9689         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9690         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9691         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9692         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9693
9694         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9695         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9696         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9697         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9698                 &kvm->arch.irq_sources_bitmap);
9699
9700         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9701         mutex_init(&kvm->arch.apic_map_lock);
9702         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9703
9704         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9705         pvclock_update_vm_gtod_copy(kvm);
9706
9707         kvm->arch.guest_can_read_msr_platform_info = true;
9708
9709         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9710         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9711
9712         kvm_hv_init_vm(kvm);
9713         kvm_page_track_init(kvm);
9714         kvm_mmu_init_vm(kvm);
9715
9716         return kvm_x86_ops->vm_init(kvm);
9717 }
9718
9719 int kvm_arch_post_init_vm(struct kvm *kvm)
9720 {
9721         return kvm_mmu_post_init_vm(kvm);
9722 }
9723
9724 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9725 {
9726         vcpu_load(vcpu);
9727         kvm_mmu_unload(vcpu);
9728         vcpu_put(vcpu);
9729 }
9730
9731 static void kvm_free_vcpus(struct kvm *kvm)
9732 {
9733         unsigned int i;
9734         struct kvm_vcpu *vcpu;
9735
9736         /*
9737          * Unpin any mmu pages first.
9738          */
9739         kvm_for_each_vcpu(i, vcpu, kvm) {
9740                 kvm_clear_async_pf_completion_queue(vcpu);
9741                 kvm_unload_vcpu_mmu(vcpu);
9742         }
9743         kvm_for_each_vcpu(i, vcpu, kvm)
9744                 kvm_vcpu_destroy(vcpu);
9745
9746         mutex_lock(&kvm->lock);
9747         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9748                 kvm->vcpus[i] = NULL;
9749
9750         atomic_set(&kvm->online_vcpus, 0);
9751         mutex_unlock(&kvm->lock);
9752 }
9753
9754 void kvm_arch_sync_events(struct kvm *kvm)
9755 {
9756         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9757         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9758         kvm_free_pit(kvm);
9759 }
9760
9761 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9762 {
9763         int i, r;
9764         unsigned long hva;
9765         struct kvm_memslots *slots = kvm_memslots(kvm);
9766         struct kvm_memory_slot *slot, old;
9767
9768         /* Called with kvm->slots_lock held.  */
9769         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9770                 return -EINVAL;
9771
9772         slot = id_to_memslot(slots, id);
9773         if (size) {
9774                 if (slot->npages)
9775                         return -EEXIST;
9776
9777                 /*
9778                  * MAP_SHARED to prevent internal slot pages from being moved
9779                  * by fork()/COW.
9780                  */
9781                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9782                               MAP_SHARED | MAP_ANONYMOUS, 0);
9783                 if (IS_ERR((void *)hva))
9784                         return PTR_ERR((void *)hva);
9785         } else {
9786                 if (!slot->npages)
9787                         return 0;
9788
9789                 hva = 0;
9790         }
9791
9792         old = *slot;
9793         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9794                 struct kvm_userspace_memory_region m;
9795
9796                 m.slot = id | (i << 16);
9797                 m.flags = 0;
9798                 m.guest_phys_addr = gpa;
9799                 m.userspace_addr = hva;
9800                 m.memory_size = size;
9801                 r = __kvm_set_memory_region(kvm, &m);
9802                 if (r < 0)
9803                         return r;
9804         }
9805
9806         if (!size)
9807                 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9808
9809         return 0;
9810 }
9811 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9812
9813 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9814 {
9815         kvm_mmu_pre_destroy_vm(kvm);
9816 }
9817
9818 void kvm_arch_destroy_vm(struct kvm *kvm)
9819 {
9820         if (current->mm == kvm->mm) {
9821                 /*
9822                  * Free memory regions allocated on behalf of userspace,
9823                  * unless the the memory map has changed due to process exit
9824                  * or fd copying.
9825                  */
9826                 mutex_lock(&kvm->slots_lock);
9827                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9828                                         0, 0);
9829                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9830                                         0, 0);
9831                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9832                 mutex_unlock(&kvm->slots_lock);
9833         }
9834         if (kvm_x86_ops->vm_destroy)
9835                 kvm_x86_ops->vm_destroy(kvm);
9836         kvm_pic_destroy(kvm);
9837         kvm_ioapic_destroy(kvm);
9838         kvm_free_vcpus(kvm);
9839         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9840         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9841         kvm_mmu_uninit_vm(kvm);
9842         kvm_page_track_cleanup(kvm);
9843         kvm_hv_destroy_vm(kvm);
9844 }
9845
9846 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9847                            struct kvm_memory_slot *dont)
9848 {
9849         int i;
9850
9851         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9852                 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9853                         kvfree(free->arch.rmap[i]);
9854                         free->arch.rmap[i] = NULL;
9855                 }
9856                 if (i == 0)
9857                         continue;
9858
9859                 if (!dont || free->arch.lpage_info[i - 1] !=
9860                              dont->arch.lpage_info[i - 1]) {
9861                         kvfree(free->arch.lpage_info[i - 1]);
9862                         free->arch.lpage_info[i - 1] = NULL;
9863                 }
9864         }
9865
9866         kvm_page_track_free_memslot(free, dont);
9867 }
9868
9869 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9870                             unsigned long npages)
9871 {
9872         int i;
9873
9874         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9875                 struct kvm_lpage_info *linfo;
9876                 unsigned long ugfn;
9877                 int lpages;
9878                 int level = i + 1;
9879
9880                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9881                                       slot->base_gfn, level) + 1;
9882
9883                 slot->arch.rmap[i] =
9884                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9885                                  GFP_KERNEL_ACCOUNT);
9886                 if (!slot->arch.rmap[i])
9887                         goto out_free;
9888                 if (i == 0)
9889                         continue;
9890
9891                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9892                 if (!linfo)
9893                         goto out_free;
9894
9895                 slot->arch.lpage_info[i - 1] = linfo;
9896
9897                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9898                         linfo[0].disallow_lpage = 1;
9899                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9900                         linfo[lpages - 1].disallow_lpage = 1;
9901                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9902                 /*
9903                  * If the gfn and userspace address are not aligned wrt each
9904                  * other, or if explicitly asked to, disable large page
9905                  * support for this slot
9906                  */
9907                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9908                     !kvm_largepages_enabled()) {
9909                         unsigned long j;
9910
9911                         for (j = 0; j < lpages; ++j)
9912                                 linfo[j].disallow_lpage = 1;
9913                 }
9914         }
9915
9916         if (kvm_page_track_create_memslot(slot, npages))
9917                 goto out_free;
9918
9919         return 0;
9920
9921 out_free:
9922         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9923                 kvfree(slot->arch.rmap[i]);
9924                 slot->arch.rmap[i] = NULL;
9925                 if (i == 0)
9926                         continue;
9927
9928                 kvfree(slot->arch.lpage_info[i - 1]);
9929                 slot->arch.lpage_info[i - 1] = NULL;
9930         }
9931         return -ENOMEM;
9932 }
9933
9934 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9935 {
9936         struct kvm_vcpu *vcpu;
9937         int i;
9938
9939         /*
9940          * memslots->generation has been incremented.
9941          * mmio generation may have reached its maximum value.
9942          */
9943         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9944
9945         /* Force re-initialization of steal_time cache */
9946         kvm_for_each_vcpu(i, vcpu, kvm)
9947                 kvm_vcpu_kick(vcpu);
9948 }
9949
9950 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9951                                 struct kvm_memory_slot *memslot,
9952                                 const struct kvm_userspace_memory_region *mem,
9953                                 enum kvm_mr_change change)
9954 {
9955         return 0;
9956 }
9957
9958 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9959                                      struct kvm_memory_slot *new)
9960 {
9961         /* Still write protect RO slot */
9962         if (new->flags & KVM_MEM_READONLY) {
9963                 kvm_mmu_slot_remove_write_access(kvm, new);
9964                 return;
9965         }
9966
9967         /*
9968          * Call kvm_x86_ops dirty logging hooks when they are valid.
9969          *
9970          * kvm_x86_ops->slot_disable_log_dirty is called when:
9971          *
9972          *  - KVM_MR_CREATE with dirty logging is disabled
9973          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9974          *
9975          * The reason is, in case of PML, we need to set D-bit for any slots
9976          * with dirty logging disabled in order to eliminate unnecessary GPA
9977          * logging in PML buffer (and potential PML buffer full VMEXIT). This
9978          * guarantees leaving PML enabled during guest's lifetime won't have
9979          * any additional overhead from PML when guest is running with dirty
9980          * logging disabled for memory slots.
9981          *
9982          * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9983          * to dirty logging mode.
9984          *
9985          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9986          *
9987          * In case of write protect:
9988          *
9989          * Write protect all pages for dirty logging.
9990          *
9991          * All the sptes including the large sptes which point to this
9992          * slot are set to readonly. We can not create any new large
9993          * spte on this slot until the end of the logging.
9994          *
9995          * See the comments in fast_page_fault().
9996          */
9997         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9998                 if (kvm_x86_ops->slot_enable_log_dirty)
9999                         kvm_x86_ops->slot_enable_log_dirty(kvm, new);
10000                 else
10001                         kvm_mmu_slot_remove_write_access(kvm, new);
10002         } else {
10003                 if (kvm_x86_ops->slot_disable_log_dirty)
10004                         kvm_x86_ops->slot_disable_log_dirty(kvm, new);
10005         }
10006 }
10007
10008 void kvm_arch_commit_memory_region(struct kvm *kvm,
10009                                 const struct kvm_userspace_memory_region *mem,
10010                                 const struct kvm_memory_slot *old,
10011                                 const struct kvm_memory_slot *new,
10012                                 enum kvm_mr_change change)
10013 {
10014         if (!kvm->arch.n_requested_mmu_pages)
10015                 kvm_mmu_change_mmu_pages(kvm,
10016                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10017
10018         /*
10019          * Dirty logging tracks sptes in 4k granularity, meaning that large
10020          * sptes have to be split.  If live migration is successful, the guest
10021          * in the source machine will be destroyed and large sptes will be
10022          * created in the destination. However, if the guest continues to run
10023          * in the source machine (for example if live migration fails), small
10024          * sptes will remain around and cause bad performance.
10025          *
10026          * Scan sptes if dirty logging has been stopped, dropping those
10027          * which can be collapsed into a single large-page spte.  Later
10028          * page faults will create the large-page sptes.
10029          *
10030          * There is no need to do this in any of the following cases:
10031          * CREATE:      No dirty mappings will already exist.
10032          * MOVE/DELETE: The old mappings will already have been cleaned up by
10033          *              kvm_arch_flush_shadow_memslot()
10034          */
10035         if (change == KVM_MR_FLAGS_ONLY &&
10036                 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10037                 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10038                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10039
10040         /*
10041          * Set up write protection and/or dirty logging for the new slot.
10042          *
10043          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10044          * been zapped so no dirty logging staff is needed for old slot. For
10045          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10046          * new and it's also covered when dealing with the new slot.
10047          *
10048          * FIXME: const-ify all uses of struct kvm_memory_slot.
10049          */
10050         if (change != KVM_MR_DELETE)
10051                 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10052 }
10053
10054 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10055 {
10056         kvm_mmu_zap_all(kvm);
10057 }
10058
10059 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10060                                    struct kvm_memory_slot *slot)
10061 {
10062         kvm_page_track_flush_slot(kvm, slot);
10063 }
10064
10065 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10066 {
10067         return (is_guest_mode(vcpu) &&
10068                         kvm_x86_ops->guest_apic_has_interrupt &&
10069                         kvm_x86_ops->guest_apic_has_interrupt(vcpu));
10070 }
10071
10072 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10073 {
10074         if (!list_empty_careful(&vcpu->async_pf.done))
10075                 return true;
10076
10077         if (kvm_apic_has_events(vcpu))
10078                 return true;
10079
10080         if (vcpu->arch.pv.pv_unhalted)
10081                 return true;
10082
10083         if (vcpu->arch.exception.pending)
10084                 return true;
10085
10086         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10087             (vcpu->arch.nmi_pending &&
10088              kvm_x86_ops->nmi_allowed(vcpu)))
10089                 return true;
10090
10091         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10092             (vcpu->arch.smi_pending && !is_smm(vcpu)))
10093                 return true;
10094
10095         if (kvm_arch_interrupt_allowed(vcpu) &&
10096             (kvm_cpu_has_interrupt(vcpu) ||
10097             kvm_guest_apic_has_interrupt(vcpu)))
10098                 return true;
10099
10100         if (kvm_hv_has_stimer_pending(vcpu))
10101                 return true;
10102
10103         return false;
10104 }
10105
10106 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10107 {
10108         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10109 }
10110
10111 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10112 {
10113         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10114                 return true;
10115
10116         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10117                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10118                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10119                 return true;
10120
10121         if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10122                 return true;
10123
10124         return false;
10125 }
10126
10127 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10128 {
10129         return vcpu->arch.preempted_in_kernel;
10130 }
10131
10132 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10133 {
10134         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10135 }
10136
10137 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10138 {
10139         return kvm_x86_ops->interrupt_allowed(vcpu);
10140 }
10141
10142 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10143 {
10144         if (is_64_bit_mode(vcpu))
10145                 return kvm_rip_read(vcpu);
10146         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10147                      kvm_rip_read(vcpu));
10148 }
10149 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10150
10151 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10152 {
10153         return kvm_get_linear_rip(vcpu) == linear_rip;
10154 }
10155 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10156
10157 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10158 {
10159         unsigned long rflags;
10160
10161         rflags = kvm_x86_ops->get_rflags(vcpu);
10162         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10163                 rflags &= ~X86_EFLAGS_TF;
10164         return rflags;
10165 }
10166 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10167
10168 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10169 {
10170         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10171             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10172                 rflags |= X86_EFLAGS_TF;
10173         kvm_x86_ops->set_rflags(vcpu, rflags);
10174 }
10175
10176 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10177 {
10178         __kvm_set_rflags(vcpu, rflags);
10179         kvm_make_request(KVM_REQ_EVENT, vcpu);
10180 }
10181 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10182
10183 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10184 {
10185         int r;
10186
10187         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10188               work->wakeup_all)
10189                 return;
10190
10191         r = kvm_mmu_reload(vcpu);
10192         if (unlikely(r))
10193                 return;
10194
10195         if (!vcpu->arch.mmu->direct_map &&
10196               work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
10197                 return;
10198
10199         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10200 }
10201
10202 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10203 {
10204         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10205 }
10206
10207 static inline u32 kvm_async_pf_next_probe(u32 key)
10208 {
10209         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10210 }
10211
10212 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10213 {
10214         u32 key = kvm_async_pf_hash_fn(gfn);
10215
10216         while (vcpu->arch.apf.gfns[key] != ~0)
10217                 key = kvm_async_pf_next_probe(key);
10218
10219         vcpu->arch.apf.gfns[key] = gfn;
10220 }
10221
10222 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10223 {
10224         int i;
10225         u32 key = kvm_async_pf_hash_fn(gfn);
10226
10227         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10228                      (vcpu->arch.apf.gfns[key] != gfn &&
10229                       vcpu->arch.apf.gfns[key] != ~0); i++)
10230                 key = kvm_async_pf_next_probe(key);
10231
10232         return key;
10233 }
10234
10235 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10236 {
10237         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10238 }
10239
10240 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10241 {
10242         u32 i, j, k;
10243
10244         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10245         while (true) {
10246                 vcpu->arch.apf.gfns[i] = ~0;
10247                 do {
10248                         j = kvm_async_pf_next_probe(j);
10249                         if (vcpu->arch.apf.gfns[j] == ~0)
10250                                 return;
10251                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10252                         /*
10253                          * k lies cyclically in ]i,j]
10254                          * |    i.k.j |
10255                          * |....j i.k.| or  |.k..j i...|
10256                          */
10257                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10258                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10259                 i = j;
10260         }
10261 }
10262
10263 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10264 {
10265
10266         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10267                                       sizeof(val));
10268 }
10269
10270 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10271 {
10272
10273         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10274                                       sizeof(u32));
10275 }
10276
10277 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10278 {
10279         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10280                 return false;
10281
10282         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10283             (vcpu->arch.apf.send_user_only &&
10284              kvm_x86_ops->get_cpl(vcpu) == 0))
10285                 return false;
10286
10287         return true;
10288 }
10289
10290 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10291 {
10292         if (unlikely(!lapic_in_kernel(vcpu) ||
10293                      kvm_event_needs_reinjection(vcpu) ||
10294                      vcpu->arch.exception.pending))
10295                 return false;
10296
10297         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10298                 return false;
10299
10300         /*
10301          * If interrupts are off we cannot even use an artificial
10302          * halt state.
10303          */
10304         return kvm_x86_ops->interrupt_allowed(vcpu);
10305 }
10306
10307 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10308                                      struct kvm_async_pf *work)
10309 {
10310         struct x86_exception fault;
10311
10312         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10313         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10314
10315         if (kvm_can_deliver_async_pf(vcpu) &&
10316             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10317                 fault.vector = PF_VECTOR;
10318                 fault.error_code_valid = true;
10319                 fault.error_code = 0;
10320                 fault.nested_page_fault = false;
10321                 fault.address = work->arch.token;
10322                 fault.async_page_fault = true;
10323                 kvm_inject_page_fault(vcpu, &fault);
10324         } else {
10325                 /*
10326                  * It is not possible to deliver a paravirtualized asynchronous
10327                  * page fault, but putting the guest in an artificial halt state
10328                  * can be beneficial nevertheless: if an interrupt arrives, we
10329                  * can deliver it timely and perhaps the guest will schedule
10330                  * another process.  When the instruction that triggered a page
10331                  * fault is retried, hopefully the page will be ready in the host.
10332                  */
10333                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10334         }
10335 }
10336
10337 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10338                                  struct kvm_async_pf *work)
10339 {
10340         struct x86_exception fault;
10341         u32 val;
10342
10343         if (work->wakeup_all)
10344                 work->arch.token = ~0; /* broadcast wakeup */
10345         else
10346                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10347         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10348
10349         if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10350             !apf_get_user(vcpu, &val)) {
10351                 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10352                     vcpu->arch.exception.pending &&
10353                     vcpu->arch.exception.nr == PF_VECTOR &&
10354                     !apf_put_user(vcpu, 0)) {
10355                         vcpu->arch.exception.injected = false;
10356                         vcpu->arch.exception.pending = false;
10357                         vcpu->arch.exception.nr = 0;
10358                         vcpu->arch.exception.has_error_code = false;
10359                         vcpu->arch.exception.error_code = 0;
10360                         vcpu->arch.exception.has_payload = false;
10361                         vcpu->arch.exception.payload = 0;
10362                 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10363                         fault.vector = PF_VECTOR;
10364                         fault.error_code_valid = true;
10365                         fault.error_code = 0;
10366                         fault.nested_page_fault = false;
10367                         fault.address = work->arch.token;
10368                         fault.async_page_fault = true;
10369                         kvm_inject_page_fault(vcpu, &fault);
10370                 }
10371         }
10372         vcpu->arch.apf.halted = false;
10373         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10374 }
10375
10376 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10377 {
10378         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10379                 return true;
10380         else
10381                 return kvm_can_do_async_pf(vcpu);
10382 }
10383
10384 void kvm_arch_start_assignment(struct kvm *kvm)
10385 {
10386         atomic_inc(&kvm->arch.assigned_device_count);
10387 }
10388 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10389
10390 void kvm_arch_end_assignment(struct kvm *kvm)
10391 {
10392         atomic_dec(&kvm->arch.assigned_device_count);
10393 }
10394 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10395
10396 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10397 {
10398         return atomic_read(&kvm->arch.assigned_device_count);
10399 }
10400 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10401
10402 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10403 {
10404         atomic_inc(&kvm->arch.noncoherent_dma_count);
10405 }
10406 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10407
10408 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10409 {
10410         atomic_dec(&kvm->arch.noncoherent_dma_count);
10411 }
10412 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10413
10414 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10415 {
10416         return atomic_read(&kvm->arch.noncoherent_dma_count);
10417 }
10418 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10419
10420 bool kvm_arch_has_irq_bypass(void)
10421 {
10422         return true;
10423 }
10424
10425 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10426                                       struct irq_bypass_producer *prod)
10427 {
10428         struct kvm_kernel_irqfd *irqfd =
10429                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10430
10431         irqfd->producer = prod;
10432
10433         return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10434                                            prod->irq, irqfd->gsi, 1);
10435 }
10436
10437 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10438                                       struct irq_bypass_producer *prod)
10439 {
10440         int ret;
10441         struct kvm_kernel_irqfd *irqfd =
10442                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10443
10444         WARN_ON(irqfd->producer != prod);
10445         irqfd->producer = NULL;
10446
10447         /*
10448          * When producer of consumer is unregistered, we change back to
10449          * remapped mode, so we can re-use the current implementation
10450          * when the irq is masked/disabled or the consumer side (KVM
10451          * int this case doesn't want to receive the interrupts.
10452         */
10453         ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10454         if (ret)
10455                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10456                        " fails: %d\n", irqfd->consumer.token, ret);
10457 }
10458
10459 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10460                                    uint32_t guest_irq, bool set)
10461 {
10462         return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10463 }
10464
10465 bool kvm_vector_hashing_enabled(void)
10466 {
10467         return vector_hashing;
10468 }
10469
10470 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10471 {
10472         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10473 }
10474 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10475
10476 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10477 {
10478         uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10479
10480         /* The STIBP bit doesn't fault even if it's not advertised */
10481         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10482             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10483                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10484         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10485             !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10486                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10487
10488         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10489             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10490                 bits &= ~SPEC_CTRL_SSBD;
10491         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10492             !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10493                 bits &= ~SPEC_CTRL_SSBD;
10494
10495         return bits;
10496 }
10497 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10498
10499 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10500 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10501 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10502 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10503 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10504 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10505 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10506 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10507 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10508 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10509 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10510 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10511 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10512 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10513 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10514 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10515 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10516 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10517 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10518 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10519 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);