1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/export.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <linux/kvm_irqfd.h>
52 #include <linux/irqbypass.h>
53 #include <linux/sched/stat.h>
54 #include <linux/sched/isolation.h>
55 #include <linux/mem_encrypt.h>
57 #include <trace/events/kvm.h>
59 #include <asm/debugreg.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68 #include <asm/mshyperv.h>
69 #include <asm/hypervisor.h>
70 #include <asm/intel_pt.h>
71 #include <clocksource/hyperv_timer.h>
73 #define CREATE_TRACE_POINTS
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 #define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32 __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64 __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
144 static int __read_mostly lapic_timer_advance_ns = -1;
145 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
147 static bool __read_mostly vector_hashing = true;
148 module_param(vector_hashing, bool, S_IRUGO);
150 bool __read_mostly enable_vmware_backdoor = false;
151 module_param(enable_vmware_backdoor, bool, S_IRUGO);
152 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
154 static bool __read_mostly force_emulation_prefix = false;
155 module_param(force_emulation_prefix, bool, S_IRUGO);
157 int __read_mostly pi_inject_timer = -1;
158 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
160 #define KVM_NR_SHARED_MSRS 16
162 struct kvm_shared_msrs_global {
164 u32 msrs[KVM_NR_SHARED_MSRS];
167 struct kvm_shared_msrs {
168 struct user_return_notifier urn;
170 struct kvm_shared_msr_values {
173 } values[KVM_NR_SHARED_MSRS];
176 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
177 static struct kvm_shared_msrs __percpu *shared_msrs;
179 struct kvm_stats_debugfs_item debugfs_entries[] = {
180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
190 { "halt_exits", VCPU_STAT(halt_exits) },
191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
195 { "hypercalls", VCPU_STAT(hypercalls) },
196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
202 { "irq_injections", VCPU_STAT(irq_injections) },
203 { "nmi_injections", VCPU_STAT(nmi_injections) },
204 { "req_event", VCPU_STAT(req_event) },
205 { "l1d_flush", VCPU_STAT(l1d_flush) },
206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
213 { "mmu_unsync", VM_STAT(mmu_unsync) },
214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
215 { "largepages", VM_STAT(lpages) },
216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
221 u64 __read_mostly host_xcr0;
223 struct kmem_cache *x86_fpu_cache;
224 EXPORT_SYMBOL_GPL(x86_fpu_cache);
226 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
228 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
235 static void kvm_on_user_return(struct user_return_notifier *urn)
238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
240 struct kvm_shared_msr_values *values;
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
252 local_irq_restore(flags);
253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
262 static void shared_msr_update(unsigned slot, u32 msr)
265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
279 void kvm_define_shared_msr(unsigned slot, u32 msr)
281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
282 shared_msrs_global.msrs[slot] = msr;
283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
286 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
288 static void kvm_shared_msr_cpu_online(void)
292 for (i = 0; i < shared_msrs_global.nr; ++i)
293 shared_msr_update(i, shared_msrs_global.msrs[i]);
296 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
304 smsr->values[slot].curr = value;
305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
316 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
318 static void drop_user_return_notifiers(void)
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
327 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
329 return vcpu->arch.apic_base;
331 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
333 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
337 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
339 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
355 kvm_lapic_set_base(vcpu, msr_info->data);
358 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
360 asmlinkage __visible void kvm_spurious_fault(void)
362 /* Fault while not rebooting. We want the trace. */
365 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
367 #define EXCPT_BENIGN 0
368 #define EXCPT_CONTRIBUTORY 1
371 static int exception_class(int vector)
381 return EXCPT_CONTRIBUTORY;
388 #define EXCPT_FAULT 0
390 #define EXCPT_ABORT 2
391 #define EXCPT_INTERRUPT 3
393 static int exception_type(int vector)
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
409 /* Reserved exceptions will result in fault */
413 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
446 vcpu->arch.cr2 = payload;
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
453 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
455 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
456 unsigned nr, bool has_error, u32 error_code,
457 bool has_payload, unsigned long payload, bool reinject)
462 kvm_make_request(KVM_REQ_EVENT, vcpu);
464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
466 if (has_error && !is_protmode(vcpu))
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
479 if (WARN_ON_ONCE(has_payload)) {
481 * A reinjected event has already
482 * delivered its payload.
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
529 vcpu->arch.exception.pending = true;
530 vcpu->arch.exception.injected = false;
531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
543 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
547 EXPORT_SYMBOL_GPL(kvm_queue_exception);
549 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
553 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
555 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
561 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
568 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
571 kvm_inject_gp(vcpu, 0);
573 return kvm_skip_emulated_instruction(vcpu);
577 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
579 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
581 ++vcpu->stat.pf_guest;
582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
584 if (vcpu->arch.exception.nested_apf) {
585 vcpu->arch.apf.nested_apf_token = fault->address;
586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
592 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
594 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
601 return fault->nested_page_fault;
604 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
609 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
611 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
615 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
617 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
621 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
627 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
634 EXPORT_SYMBOL_GPL(kvm_require_cpl);
636 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
641 kvm_queue_exception(vcpu, UD_VECTOR);
644 EXPORT_SYMBOL_GPL(kvm_require_dr);
647 * This function will be used to read from the physical memory of the currently
648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
649 * can read from guest physical or from the guest's guest physical memory.
651 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
655 struct x86_exception exception;
659 ngpa = gfn_to_gpa(ngfn);
660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
661 if (real_gfn == UNMAPPED_GVA)
664 real_gfn = gpa_to_gfn(real_gfn);
666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
668 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
670 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
671 void *data, int offset, int len, u32 access)
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
678 * Load the pae pdptrs. Return true is they are all valid.
680 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
682 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
683 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
686 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
688 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
689 offset * sizeof(u64), sizeof(pdpte),
690 PFERR_USER_MASK|PFERR_WRITE_MASK);
695 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
696 if ((pdpte[i] & PT_PRESENT_MASK) &&
698 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
705 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_avail);
708 __set_bit(VCPU_EXREG_PDPTR,
709 (unsigned long *)&vcpu->arch.regs_dirty);
714 EXPORT_SYMBOL_GPL(load_pdptrs);
716 bool pdptrs_changed(struct kvm_vcpu *vcpu)
718 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
724 if (!is_pae_paging(vcpu))
727 if (!test_bit(VCPU_EXREG_PDPTR,
728 (unsigned long *)&vcpu->arch.regs_avail))
731 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
732 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
733 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
734 PFERR_USER_MASK | PFERR_WRITE_MASK);
737 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
742 EXPORT_SYMBOL_GPL(pdptrs_changed);
744 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
746 unsigned long old_cr0 = kvm_read_cr0(vcpu);
747 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
752 if (cr0 & 0xffffffff00000000UL)
756 cr0 &= ~CR0_RESERVED_BITS;
758 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
761 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
764 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
766 if ((vcpu->arch.efer & EFER_LME)) {
771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
776 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
781 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
784 kvm_x86_ops->set_cr0(vcpu, cr0);
786 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
787 kvm_clear_async_pf_completion_queue(vcpu);
788 kvm_async_pf_hash_reset(vcpu);
791 if ((cr0 ^ old_cr0) & update_bits)
792 kvm_mmu_reset_context(vcpu);
794 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
795 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
796 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
797 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
801 EXPORT_SYMBOL_GPL(kvm_set_cr0);
803 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
805 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
807 EXPORT_SYMBOL_GPL(kvm_lmsw);
809 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
811 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
812 !vcpu->guest_xcr0_loaded) {
813 /* kvm_set_xcr() also depends on this */
814 if (vcpu->arch.xcr0 != host_xcr0)
815 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
816 vcpu->guest_xcr0_loaded = 1;
819 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
821 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
823 if (vcpu->guest_xcr0_loaded) {
824 if (vcpu->arch.xcr0 != host_xcr0)
825 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
826 vcpu->guest_xcr0_loaded = 0;
829 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
831 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
834 u64 old_xcr0 = vcpu->arch.xcr0;
837 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
838 if (index != XCR_XFEATURE_ENABLED_MASK)
840 if (!(xcr0 & XFEATURE_MASK_FP))
842 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
846 * Do not allow the guest to set bits that we do not support
847 * saving. However, xcr0 bit 0 is always set, even if the
848 * emulated CPU does not support XSAVE (see fx_init).
850 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
851 if (xcr0 & ~valid_bits)
854 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
855 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
858 if (xcr0 & XFEATURE_MASK_AVX512) {
859 if (!(xcr0 & XFEATURE_MASK_YMM))
861 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
864 vcpu->arch.xcr0 = xcr0;
866 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
867 kvm_update_cpuid(vcpu);
871 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
873 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
874 __kvm_set_xcr(vcpu, index, xcr)) {
875 kvm_inject_gp(vcpu, 0);
880 EXPORT_SYMBOL_GPL(kvm_set_xcr);
882 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
884 unsigned long old_cr4 = kvm_read_cr4(vcpu);
885 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
886 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
888 if (cr4 & CR4_RESERVED_BITS)
891 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
894 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
897 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
900 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
903 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
906 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
909 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
912 if (is_long_mode(vcpu)) {
913 if (!(cr4 & X86_CR4_PAE))
915 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
916 && ((cr4 ^ old_cr4) & pdptr_bits)
917 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
921 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
922 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
925 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
926 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
930 if (kvm_x86_ops->set_cr4(vcpu, cr4))
933 if (((cr4 ^ old_cr4) & pdptr_bits) ||
934 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
935 kvm_mmu_reset_context(vcpu);
937 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
938 kvm_update_cpuid(vcpu);
942 EXPORT_SYMBOL_GPL(kvm_set_cr4);
944 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
946 bool skip_tlb_flush = false;
948 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
951 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
952 cr3 &= ~X86_CR3_PCID_NOFLUSH;
956 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
957 if (!skip_tlb_flush) {
958 kvm_mmu_sync_roots(vcpu);
959 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
964 if (is_long_mode(vcpu) &&
965 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
967 else if (is_pae_paging(vcpu) &&
968 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
971 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
972 vcpu->arch.cr3 = cr3;
973 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
977 EXPORT_SYMBOL_GPL(kvm_set_cr3);
979 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
981 if (cr8 & CR8_RESERVED_BITS)
983 if (lapic_in_kernel(vcpu))
984 kvm_lapic_set_tpr(vcpu, cr8);
986 vcpu->arch.cr8 = cr8;
989 EXPORT_SYMBOL_GPL(kvm_set_cr8);
991 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
993 if (lapic_in_kernel(vcpu))
994 return kvm_lapic_get_cr8(vcpu);
996 return vcpu->arch.cr8;
998 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1000 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1004 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1005 for (i = 0; i < KVM_NR_DB_REGS; i++)
1006 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1007 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1011 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1013 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1014 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1017 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022 dr7 = vcpu->arch.guest_debug_dr7;
1024 dr7 = vcpu->arch.dr7;
1025 kvm_x86_ops->set_dr7(vcpu, dr7);
1026 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1027 if (dr7 & DR7_BP_EN_MASK)
1028 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1031 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1033 u64 fixed = DR6_FIXED_1;
1035 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1040 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1044 vcpu->arch.db[dr] = val;
1045 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1046 vcpu->arch.eff_db[dr] = val;
1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
1053 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1054 kvm_update_dr6(vcpu);
1059 if (val & 0xffffffff00000000ULL)
1060 return -1; /* #GP */
1061 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1062 kvm_update_dr7(vcpu);
1069 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1071 if (__kvm_set_dr(vcpu, dr, val)) {
1072 kvm_inject_gp(vcpu, 0);
1077 EXPORT_SYMBOL_GPL(kvm_set_dr);
1079 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1083 *val = vcpu->arch.db[dr];
1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 *val = vcpu->arch.dr6;
1091 *val = kvm_x86_ops->get_dr6(vcpu);
1096 *val = vcpu->arch.dr7;
1101 EXPORT_SYMBOL_GPL(kvm_get_dr);
1103 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1105 u32 ecx = kvm_rcx_read(vcpu);
1109 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1112 kvm_rax_write(vcpu, (u32)data);
1113 kvm_rdx_write(vcpu, data >> 32);
1116 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1119 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1120 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1122 * This list is modified at module load time to reflect the
1123 * capabilities of the host cpu. This capabilities test skips MSRs that are
1124 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1125 * may depend on host virtualization features rather than host cpu features.
1128 static u32 msrs_to_save[] = {
1129 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1131 #ifdef CONFIG_X86_64
1132 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1134 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1135 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1137 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1138 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1139 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1140 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1141 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1142 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1145 static unsigned num_msrs_to_save;
1147 static u32 emulated_msrs[] = {
1148 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1149 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1150 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1151 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1152 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1153 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1154 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1156 HV_X64_MSR_VP_INDEX,
1157 HV_X64_MSR_VP_RUNTIME,
1158 HV_X64_MSR_SCONTROL,
1159 HV_X64_MSR_STIMER0_CONFIG,
1160 HV_X64_MSR_VP_ASSIST_PAGE,
1161 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1162 HV_X64_MSR_TSC_EMULATION_STATUS,
1164 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1167 MSR_IA32_TSC_ADJUST,
1168 MSR_IA32_TSCDEADLINE,
1169 MSR_IA32_ARCH_CAPABILITIES,
1170 MSR_IA32_MISC_ENABLE,
1171 MSR_IA32_MCG_STATUS,
1173 MSR_IA32_MCG_EXT_CTL,
1177 MSR_MISC_FEATURES_ENABLES,
1178 MSR_AMD64_VIRT_SPEC_CTRL,
1182 * The following list leaves out MSRs whose values are determined
1183 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1184 * We always support the "true" VMX control MSRs, even if the host
1185 * processor does not, so I am putting these registers here rather
1186 * than in msrs_to_save.
1189 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1191 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1194 MSR_IA32_VMX_CR0_FIXED0,
1195 MSR_IA32_VMX_CR4_FIXED0,
1196 MSR_IA32_VMX_VMCS_ENUM,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 MSR_IA32_VMX_EPT_VPID_CAP,
1199 MSR_IA32_VMX_VMFUNC,
1202 MSR_KVM_POLL_CONTROL,
1205 static unsigned num_emulated_msrs;
1208 * List of msr numbers which are used to expose MSR-based features that
1209 * can be used by a hypervisor to validate requested CPU features.
1211 static u32 msr_based_features[] = {
1213 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1214 MSR_IA32_VMX_PINBASED_CTLS,
1215 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1216 MSR_IA32_VMX_PROCBASED_CTLS,
1217 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 MSR_IA32_VMX_EXIT_CTLS,
1219 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1220 MSR_IA32_VMX_ENTRY_CTLS,
1222 MSR_IA32_VMX_CR0_FIXED0,
1223 MSR_IA32_VMX_CR0_FIXED1,
1224 MSR_IA32_VMX_CR4_FIXED0,
1225 MSR_IA32_VMX_CR4_FIXED1,
1226 MSR_IA32_VMX_VMCS_ENUM,
1227 MSR_IA32_VMX_PROCBASED_CTLS2,
1228 MSR_IA32_VMX_EPT_VPID_CAP,
1229 MSR_IA32_VMX_VMFUNC,
1233 MSR_IA32_ARCH_CAPABILITIES,
1236 static unsigned int num_msr_based_features;
1238 static u64 kvm_get_arch_capabilities(void)
1242 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1243 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1246 * If we're doing cache flushes (either "always" or "cond")
1247 * we will do one whenever the guest does a vmlaunch/vmresume.
1248 * If an outer hypervisor is doing the cache flush for us
1249 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1250 * capability to the guest too, and if EPT is disabled we're not
1251 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1252 * require a nested hypervisor to do a flush of its own.
1254 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1255 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1260 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1262 switch (msr->index) {
1263 case MSR_IA32_ARCH_CAPABILITIES:
1264 msr->data = kvm_get_arch_capabilities();
1266 case MSR_IA32_UCODE_REV:
1267 rdmsrl_safe(msr->index, &msr->data);
1270 if (kvm_x86_ops->get_msr_feature(msr))
1276 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1278 struct kvm_msr_entry msr;
1282 r = kvm_get_msr_feature(&msr);
1291 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1293 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1296 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1299 if (efer & (EFER_LME | EFER_LMA) &&
1300 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1303 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1309 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1311 if (efer & efer_reserved_bits)
1314 return __kvm_valid_efer(vcpu, efer);
1316 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1318 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1320 u64 old_efer = vcpu->arch.efer;
1321 u64 efer = msr_info->data;
1323 if (efer & efer_reserved_bits)
1326 if (!msr_info->host_initiated) {
1327 if (!__kvm_valid_efer(vcpu, efer))
1330 if (is_paging(vcpu) &&
1331 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1336 efer |= vcpu->arch.efer & EFER_LMA;
1338 kvm_x86_ops->set_efer(vcpu, efer);
1340 /* Update reserved bits */
1341 if ((efer ^ old_efer) & EFER_NX)
1342 kvm_mmu_reset_context(vcpu);
1347 void kvm_enable_efer_bits(u64 mask)
1349 efer_reserved_bits &= ~mask;
1351 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1354 * Writes msr value into into the appropriate "register".
1355 * Returns 0 on success, non-0 otherwise.
1356 * Assumes vcpu_load() was already called.
1358 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1360 switch (msr->index) {
1363 case MSR_KERNEL_GS_BASE:
1366 if (is_noncanonical_address(msr->data, vcpu))
1369 case MSR_IA32_SYSENTER_EIP:
1370 case MSR_IA32_SYSENTER_ESP:
1372 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1373 * non-canonical address is written on Intel but not on
1374 * AMD (which ignores the top 32-bits, because it does
1375 * not implement 64-bit SYSENTER).
1377 * 64-bit code should hence be able to write a non-canonical
1378 * value on AMD. Making the address canonical ensures that
1379 * vmentry does not fail on Intel after writing a non-canonical
1380 * value, and that something deterministic happens if the guest
1381 * invokes 64-bit SYSENTER.
1383 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1385 return kvm_x86_ops->set_msr(vcpu, msr);
1387 EXPORT_SYMBOL_GPL(kvm_set_msr);
1390 * Adapt set_msr() to msr_io()'s calling convention
1392 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1394 struct msr_data msr;
1398 msr.host_initiated = true;
1399 r = kvm_get_msr(vcpu, &msr);
1407 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1409 struct msr_data msr;
1413 msr.host_initiated = true;
1414 return kvm_set_msr(vcpu, &msr);
1417 #ifdef CONFIG_X86_64
1418 struct pvclock_gtod_data {
1421 struct { /* extract of a clocksource struct */
1434 static struct pvclock_gtod_data pvclock_gtod_data;
1436 static void update_pvclock_gtod(struct timekeeper *tk)
1438 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1441 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1443 write_seqcount_begin(&vdata->seq);
1445 /* copy pvclock gtod data */
1446 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1447 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1448 vdata->clock.mask = tk->tkr_mono.mask;
1449 vdata->clock.mult = tk->tkr_mono.mult;
1450 vdata->clock.shift = tk->tkr_mono.shift;
1452 vdata->boot_ns = boot_ns;
1453 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1455 vdata->wall_time_sec = tk->xtime_sec;
1457 write_seqcount_end(&vdata->seq);
1461 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1463 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1464 kvm_vcpu_kick(vcpu);
1467 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1471 struct pvclock_wall_clock wc;
1472 struct timespec64 boot;
1477 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1482 ++version; /* first time write, random junk */
1486 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1490 * The guest calculates current wall clock time by adding
1491 * system time (updated by kvm_guest_time_update below) to the
1492 * wall clock specified here. guest system time equals host
1493 * system time for us, thus we must fill in host boot time here.
1495 getboottime64(&boot);
1497 if (kvm->arch.kvmclock_offset) {
1498 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1499 boot = timespec64_sub(boot, ts);
1501 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1502 wc.nsec = boot.tv_nsec;
1503 wc.version = version;
1505 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1508 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1511 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1513 do_shl32_div32(dividend, divisor);
1517 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1518 s8 *pshift, u32 *pmultiplier)
1526 scaled64 = scaled_hz;
1527 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1532 tps32 = (uint32_t)tps64;
1533 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1534 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1542 *pmultiplier = div_frac(scaled64, tps32);
1545 #ifdef CONFIG_X86_64
1546 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1549 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1550 static unsigned long max_tsc_khz;
1552 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1554 u64 v = (u64)khz * (1000000 + ppm);
1559 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1563 /* Guest TSC same frequency as host TSC? */
1565 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1569 /* TSC scaling supported? */
1570 if (!kvm_has_tsc_control) {
1571 if (user_tsc_khz > tsc_khz) {
1572 vcpu->arch.tsc_catchup = 1;
1573 vcpu->arch.tsc_always_catchup = 1;
1576 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1581 /* TSC scaling required - calculate ratio */
1582 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1583 user_tsc_khz, tsc_khz);
1585 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1586 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1591 vcpu->arch.tsc_scaling_ratio = ratio;
1595 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1597 u32 thresh_lo, thresh_hi;
1598 int use_scaling = 0;
1600 /* tsc_khz can be zero if TSC calibration fails */
1601 if (user_tsc_khz == 0) {
1602 /* set tsc_scaling_ratio to a safe value */
1603 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1607 /* Compute a scale to convert nanoseconds in TSC cycles */
1608 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1609 &vcpu->arch.virtual_tsc_shift,
1610 &vcpu->arch.virtual_tsc_mult);
1611 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1614 * Compute the variation in TSC rate which is acceptable
1615 * within the range of tolerance and decide if the
1616 * rate being applied is within that bounds of the hardware
1617 * rate. If so, no scaling or compensation need be done.
1619 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1620 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1621 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1622 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1625 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1628 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1630 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1631 vcpu->arch.virtual_tsc_mult,
1632 vcpu->arch.virtual_tsc_shift);
1633 tsc += vcpu->arch.this_tsc_write;
1637 static inline int gtod_is_based_on_tsc(int mode)
1639 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1642 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1644 #ifdef CONFIG_X86_64
1646 struct kvm_arch *ka = &vcpu->kvm->arch;
1647 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1649 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1650 atomic_read(&vcpu->kvm->online_vcpus));
1653 * Once the masterclock is enabled, always perform request in
1654 * order to update it.
1656 * In order to enable masterclock, the host clocksource must be TSC
1657 * and the vcpus need to have matched TSCs. When that happens,
1658 * perform request to enable masterclock.
1660 if (ka->use_master_clock ||
1661 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1662 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1664 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1665 atomic_read(&vcpu->kvm->online_vcpus),
1666 ka->use_master_clock, gtod->clock.vclock_mode);
1670 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1672 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1673 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1677 * Multiply tsc by a fixed point number represented by ratio.
1679 * The most significant 64-N bits (mult) of ratio represent the
1680 * integral part of the fixed point number; the remaining N bits
1681 * (frac) represent the fractional part, ie. ratio represents a fixed
1682 * point number (mult + frac * 2^(-N)).
1684 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1686 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1688 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1691 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1694 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1696 if (ratio != kvm_default_tsc_scaling_ratio)
1697 _tsc = __scale_tsc(ratio, tsc);
1701 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1703 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1707 tsc = kvm_scale_tsc(vcpu, rdtsc());
1709 return target_tsc - tsc;
1712 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1714 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1716 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1718 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1720 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1722 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1725 static inline bool kvm_check_tsc_unstable(void)
1727 #ifdef CONFIG_X86_64
1729 * TSC is marked unstable when we're running on Hyper-V,
1730 * 'TSC page' clocksource is good.
1732 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1735 return check_tsc_unstable();
1738 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1740 struct kvm *kvm = vcpu->kvm;
1741 u64 offset, ns, elapsed;
1742 unsigned long flags;
1744 bool already_matched;
1745 u64 data = msr->data;
1746 bool synchronizing = false;
1748 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1749 offset = kvm_compute_tsc_offset(vcpu, data);
1750 ns = ktime_get_boottime_ns();
1751 elapsed = ns - kvm->arch.last_tsc_nsec;
1753 if (vcpu->arch.virtual_tsc_khz) {
1754 if (data == 0 && msr->host_initiated) {
1756 * detection of vcpu initialization -- need to sync
1757 * with other vCPUs. This particularly helps to keep
1758 * kvm_clock stable after CPU hotplug
1760 synchronizing = true;
1762 u64 tsc_exp = kvm->arch.last_tsc_write +
1763 nsec_to_cycles(vcpu, elapsed);
1764 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1766 * Special case: TSC write with a small delta (1 second)
1767 * of virtual cycle time against real time is
1768 * interpreted as an attempt to synchronize the CPU.
1770 synchronizing = data < tsc_exp + tsc_hz &&
1771 data + tsc_hz > tsc_exp;
1776 * For a reliable TSC, we can match TSC offsets, and for an unstable
1777 * TSC, we add elapsed time in this computation. We could let the
1778 * compensation code attempt to catch up if we fall behind, but
1779 * it's better to try to match offsets from the beginning.
1781 if (synchronizing &&
1782 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1783 if (!kvm_check_tsc_unstable()) {
1784 offset = kvm->arch.cur_tsc_offset;
1786 u64 delta = nsec_to_cycles(vcpu, elapsed);
1788 offset = kvm_compute_tsc_offset(vcpu, data);
1791 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1794 * We split periods of matched TSC writes into generations.
1795 * For each generation, we track the original measured
1796 * nanosecond time, offset, and write, so if TSCs are in
1797 * sync, we can match exact offset, and if not, we can match
1798 * exact software computation in compute_guest_tsc()
1800 * These values are tracked in kvm->arch.cur_xxx variables.
1802 kvm->arch.cur_tsc_generation++;
1803 kvm->arch.cur_tsc_nsec = ns;
1804 kvm->arch.cur_tsc_write = data;
1805 kvm->arch.cur_tsc_offset = offset;
1810 * We also track th most recent recorded KHZ, write and time to
1811 * allow the matching interval to be extended at each write.
1813 kvm->arch.last_tsc_nsec = ns;
1814 kvm->arch.last_tsc_write = data;
1815 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1817 vcpu->arch.last_guest_tsc = data;
1819 /* Keep track of which generation this VCPU has synchronized to */
1820 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1821 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1822 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1824 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1825 update_ia32_tsc_adjust_msr(vcpu, offset);
1827 kvm_vcpu_write_tsc_offset(vcpu, offset);
1828 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1830 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1832 kvm->arch.nr_vcpus_matched_tsc = 0;
1833 } else if (!already_matched) {
1834 kvm->arch.nr_vcpus_matched_tsc++;
1837 kvm_track_tsc_matching(vcpu);
1838 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1841 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1843 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1846 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1847 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1850 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1852 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1853 WARN_ON(adjustment < 0);
1854 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1855 adjust_tsc_offset_guest(vcpu, adjustment);
1858 #ifdef CONFIG_X86_64
1860 static u64 read_tsc(void)
1862 u64 ret = (u64)rdtsc_ordered();
1863 u64 last = pvclock_gtod_data.clock.cycle_last;
1865 if (likely(ret >= last))
1869 * GCC likes to generate cmov here, but this branch is extremely
1870 * predictable (it's just a function of time and the likely is
1871 * very likely) and there's a data dependence, so force GCC
1872 * to generate a branch instead. I don't barrier() because
1873 * we don't actually need a barrier, and if this function
1874 * ever gets inlined it will generate worse code.
1880 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1883 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1886 switch (gtod->clock.vclock_mode) {
1887 case VCLOCK_HVCLOCK:
1888 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1890 if (tsc_pg_val != U64_MAX) {
1891 /* TSC page valid */
1892 *mode = VCLOCK_HVCLOCK;
1893 v = (tsc_pg_val - gtod->clock.cycle_last) &
1896 /* TSC page invalid */
1897 *mode = VCLOCK_NONE;
1902 *tsc_timestamp = read_tsc();
1903 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1907 *mode = VCLOCK_NONE;
1910 if (*mode == VCLOCK_NONE)
1911 *tsc_timestamp = v = 0;
1913 return v * gtod->clock.mult;
1916 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1918 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1924 seq = read_seqcount_begin(>od->seq);
1925 ns = gtod->nsec_base;
1926 ns += vgettsc(tsc_timestamp, &mode);
1927 ns >>= gtod->clock.shift;
1928 ns += gtod->boot_ns;
1929 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1935 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1937 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1943 seq = read_seqcount_begin(>od->seq);
1944 ts->tv_sec = gtod->wall_time_sec;
1945 ns = gtod->nsec_base;
1946 ns += vgettsc(tsc_timestamp, &mode);
1947 ns >>= gtod->clock.shift;
1948 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1950 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1956 /* returns true if host is using TSC based clocksource */
1957 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1959 /* checked again under seqlock below */
1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1963 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1967 /* returns true if host is using TSC based clocksource */
1968 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1971 /* checked again under seqlock below */
1972 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1975 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1981 * Assuming a stable TSC across physical CPUS, and a stable TSC
1982 * across virtual CPUs, the following condition is possible.
1983 * Each numbered line represents an event visible to both
1984 * CPUs at the next numbered event.
1986 * "timespecX" represents host monotonic time. "tscX" represents
1989 * VCPU0 on CPU0 | VCPU1 on CPU1
1991 * 1. read timespec0,tsc0
1992 * 2. | timespec1 = timespec0 + N
1994 * 3. transition to guest | transition to guest
1995 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1996 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1997 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1999 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2002 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2004 * - 0 < N - M => M < N
2006 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2007 * always the case (the difference between two distinct xtime instances
2008 * might be smaller then the difference between corresponding TSC reads,
2009 * when updating guest vcpus pvclock areas).
2011 * To avoid that problem, do not allow visibility of distinct
2012 * system_timestamp/tsc_timestamp values simultaneously: use a master
2013 * copy of host monotonic time values. Update that master copy
2016 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2020 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2022 #ifdef CONFIG_X86_64
2023 struct kvm_arch *ka = &kvm->arch;
2025 bool host_tsc_clocksource, vcpus_matched;
2027 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2028 atomic_read(&kvm->online_vcpus));
2031 * If the host uses TSC clock, then passthrough TSC as stable
2034 host_tsc_clocksource = kvm_get_time_and_clockread(
2035 &ka->master_kernel_ns,
2036 &ka->master_cycle_now);
2038 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2039 && !ka->backwards_tsc_observed
2040 && !ka->boot_vcpu_runs_old_kvmclock;
2042 if (ka->use_master_clock)
2043 atomic_set(&kvm_guest_has_master_clock, 1);
2045 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2046 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2051 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2053 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2056 static void kvm_gen_update_masterclock(struct kvm *kvm)
2058 #ifdef CONFIG_X86_64
2060 struct kvm_vcpu *vcpu;
2061 struct kvm_arch *ka = &kvm->arch;
2063 spin_lock(&ka->pvclock_gtod_sync_lock);
2064 kvm_make_mclock_inprogress_request(kvm);
2065 /* no guest entries from this point */
2066 pvclock_update_vm_gtod_copy(kvm);
2068 kvm_for_each_vcpu(i, vcpu, kvm)
2069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2071 /* guest entries allowed */
2072 kvm_for_each_vcpu(i, vcpu, kvm)
2073 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2075 spin_unlock(&ka->pvclock_gtod_sync_lock);
2079 u64 get_kvmclock_ns(struct kvm *kvm)
2081 struct kvm_arch *ka = &kvm->arch;
2082 struct pvclock_vcpu_time_info hv_clock;
2085 spin_lock(&ka->pvclock_gtod_sync_lock);
2086 if (!ka->use_master_clock) {
2087 spin_unlock(&ka->pvclock_gtod_sync_lock);
2088 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2091 hv_clock.tsc_timestamp = ka->master_cycle_now;
2092 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2093 spin_unlock(&ka->pvclock_gtod_sync_lock);
2095 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2098 if (__this_cpu_read(cpu_tsc_khz)) {
2099 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2100 &hv_clock.tsc_shift,
2101 &hv_clock.tsc_to_system_mul);
2102 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2104 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2111 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2113 struct kvm_vcpu_arch *vcpu = &v->arch;
2114 struct pvclock_vcpu_time_info guest_hv_clock;
2116 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2117 &guest_hv_clock, sizeof(guest_hv_clock))))
2120 /* This VCPU is paused, but it's legal for a guest to read another
2121 * VCPU's kvmclock, so we really have to follow the specification where
2122 * it says that version is odd if data is being modified, and even after
2125 * Version field updates must be kept separate. This is because
2126 * kvm_write_guest_cached might use a "rep movs" instruction, and
2127 * writes within a string instruction are weakly ordered. So there
2128 * are three writes overall.
2130 * As a small optimization, only write the version field in the first
2131 * and third write. The vcpu->pv_time cache is still valid, because the
2132 * version field is the first in the struct.
2134 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2136 if (guest_hv_clock.version & 1)
2137 ++guest_hv_clock.version; /* first time write, random junk */
2139 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2140 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2142 sizeof(vcpu->hv_clock.version));
2146 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2147 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2149 if (vcpu->pvclock_set_guest_stopped_request) {
2150 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2151 vcpu->pvclock_set_guest_stopped_request = false;
2154 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2156 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2158 sizeof(vcpu->hv_clock));
2162 vcpu->hv_clock.version++;
2163 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2165 sizeof(vcpu->hv_clock.version));
2168 static int kvm_guest_time_update(struct kvm_vcpu *v)
2170 unsigned long flags, tgt_tsc_khz;
2171 struct kvm_vcpu_arch *vcpu = &v->arch;
2172 struct kvm_arch *ka = &v->kvm->arch;
2174 u64 tsc_timestamp, host_tsc;
2176 bool use_master_clock;
2182 * If the host uses TSC clock, then passthrough TSC as stable
2185 spin_lock(&ka->pvclock_gtod_sync_lock);
2186 use_master_clock = ka->use_master_clock;
2187 if (use_master_clock) {
2188 host_tsc = ka->master_cycle_now;
2189 kernel_ns = ka->master_kernel_ns;
2191 spin_unlock(&ka->pvclock_gtod_sync_lock);
2193 /* Keep irq disabled to prevent changes to the clock */
2194 local_irq_save(flags);
2195 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2196 if (unlikely(tgt_tsc_khz == 0)) {
2197 local_irq_restore(flags);
2198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2201 if (!use_master_clock) {
2203 kernel_ns = ktime_get_boottime_ns();
2206 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2209 * We may have to catch up the TSC to match elapsed wall clock
2210 * time for two reasons, even if kvmclock is used.
2211 * 1) CPU could have been running below the maximum TSC rate
2212 * 2) Broken TSC compensation resets the base at each VCPU
2213 * entry to avoid unknown leaps of TSC even when running
2214 * again on the same CPU. This may cause apparent elapsed
2215 * time to disappear, and the guest to stand still or run
2218 if (vcpu->tsc_catchup) {
2219 u64 tsc = compute_guest_tsc(v, kernel_ns);
2220 if (tsc > tsc_timestamp) {
2221 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2222 tsc_timestamp = tsc;
2226 local_irq_restore(flags);
2228 /* With all the info we got, fill in the values */
2230 if (kvm_has_tsc_control)
2231 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2233 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2234 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2235 &vcpu->hv_clock.tsc_shift,
2236 &vcpu->hv_clock.tsc_to_system_mul);
2237 vcpu->hw_tsc_khz = tgt_tsc_khz;
2240 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2241 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2242 vcpu->last_guest_tsc = tsc_timestamp;
2244 /* If the host uses TSC clocksource, then it is stable */
2246 if (use_master_clock)
2247 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2249 vcpu->hv_clock.flags = pvclock_flags;
2251 if (vcpu->pv_time_enabled)
2252 kvm_setup_pvclock_page(v);
2253 if (v == kvm_get_vcpu(v->kvm, 0))
2254 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2259 * kvmclock updates which are isolated to a given vcpu, such as
2260 * vcpu->cpu migration, should not allow system_timestamp from
2261 * the rest of the vcpus to remain static. Otherwise ntp frequency
2262 * correction applies to one vcpu's system_timestamp but not
2265 * So in those cases, request a kvmclock update for all vcpus.
2266 * We need to rate-limit these requests though, as they can
2267 * considerably slow guests that have a large number of vcpus.
2268 * The time for a remote vcpu to update its kvmclock is bound
2269 * by the delay we use to rate-limit the updates.
2272 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2274 static void kvmclock_update_fn(struct work_struct *work)
2277 struct delayed_work *dwork = to_delayed_work(work);
2278 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2279 kvmclock_update_work);
2280 struct kvm *kvm = container_of(ka, struct kvm, arch);
2281 struct kvm_vcpu *vcpu;
2283 kvm_for_each_vcpu(i, vcpu, kvm) {
2284 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2285 kvm_vcpu_kick(vcpu);
2289 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2291 struct kvm *kvm = v->kvm;
2293 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2294 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2295 KVMCLOCK_UPDATE_DELAY);
2298 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2300 static void kvmclock_sync_fn(struct work_struct *work)
2302 struct delayed_work *dwork = to_delayed_work(work);
2303 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2304 kvmclock_sync_work);
2305 struct kvm *kvm = container_of(ka, struct kvm, arch);
2307 if (!kvmclock_periodic_sync)
2310 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2311 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2312 KVMCLOCK_SYNC_PERIOD);
2316 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2318 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2320 /* McStatusWrEn enabled? */
2321 if (guest_cpuid_is_amd(vcpu))
2322 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2327 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2329 u64 mcg_cap = vcpu->arch.mcg_cap;
2330 unsigned bank_num = mcg_cap & 0xff;
2331 u32 msr = msr_info->index;
2332 u64 data = msr_info->data;
2335 case MSR_IA32_MCG_STATUS:
2336 vcpu->arch.mcg_status = data;
2338 case MSR_IA32_MCG_CTL:
2339 if (!(mcg_cap & MCG_CTL_P) &&
2340 (data || !msr_info->host_initiated))
2342 if (data != 0 && data != ~(u64)0)
2344 vcpu->arch.mcg_ctl = data;
2347 if (msr >= MSR_IA32_MC0_CTL &&
2348 msr < MSR_IA32_MCx_CTL(bank_num)) {
2349 u32 offset = msr - MSR_IA32_MC0_CTL;
2350 /* only 0 or all 1s can be written to IA32_MCi_CTL
2351 * some Linux kernels though clear bit 10 in bank 4 to
2352 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2353 * this to avoid an uncatched #GP in the guest
2355 if ((offset & 0x3) == 0 &&
2356 data != 0 && (data | (1 << 10)) != ~(u64)0)
2360 if (!msr_info->host_initiated &&
2361 (offset & 0x3) == 1 && data != 0) {
2362 if (!can_set_mci_status(vcpu))
2366 vcpu->arch.mce_banks[offset] = data;
2374 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2376 struct kvm *kvm = vcpu->kvm;
2377 int lm = is_long_mode(vcpu);
2378 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2379 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2380 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2381 : kvm->arch.xen_hvm_config.blob_size_32;
2382 u32 page_num = data & ~PAGE_MASK;
2383 u64 page_addr = data & PAGE_MASK;
2388 if (page_num >= blob_size)
2391 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2396 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2405 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2407 gpa_t gpa = data & ~0x3f;
2409 /* Bits 3:5 are reserved, Should be zero */
2413 vcpu->arch.apf.msr_val = data;
2415 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2416 kvm_clear_async_pf_completion_queue(vcpu);
2417 kvm_async_pf_hash_reset(vcpu);
2421 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2425 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2426 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2427 kvm_async_pf_wakeup_all(vcpu);
2431 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2433 vcpu->arch.pv_time_enabled = false;
2436 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2438 ++vcpu->stat.tlb_flush;
2439 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2442 static void record_steal_time(struct kvm_vcpu *vcpu)
2444 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2447 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2448 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2452 * Doing a TLB flush here, on the guest's behalf, can avoid
2455 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2456 kvm_vcpu_flush_tlb(vcpu, false);
2458 if (vcpu->arch.st.steal.version & 1)
2459 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2461 vcpu->arch.st.steal.version += 1;
2463 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2464 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2468 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2469 vcpu->arch.st.last_steal;
2470 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2472 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2473 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2477 vcpu->arch.st.steal.version += 1;
2479 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2480 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2483 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2486 u32 msr = msr_info->index;
2487 u64 data = msr_info->data;
2490 case MSR_AMD64_NB_CFG:
2491 case MSR_IA32_UCODE_WRITE:
2492 case MSR_VM_HSAVE_PA:
2493 case MSR_AMD64_PATCH_LOADER:
2494 case MSR_AMD64_BU_CFG2:
2495 case MSR_AMD64_DC_CFG:
2496 case MSR_F15H_EX_CFG:
2499 case MSR_IA32_UCODE_REV:
2500 if (msr_info->host_initiated)
2501 vcpu->arch.microcode_version = data;
2503 case MSR_IA32_ARCH_CAPABILITIES:
2504 if (!msr_info->host_initiated)
2506 vcpu->arch.arch_capabilities = data;
2509 return set_efer(vcpu, msr_info);
2511 data &= ~(u64)0x40; /* ignore flush filter disable */
2512 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2513 data &= ~(u64)0x8; /* ignore TLB cache disable */
2515 /* Handle McStatusWrEn */
2516 if (data == BIT_ULL(18)) {
2517 vcpu->arch.msr_hwcr = data;
2518 } else if (data != 0) {
2519 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2524 case MSR_FAM10H_MMIO_CONF_BASE:
2526 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2531 case MSR_IA32_DEBUGCTLMSR:
2533 /* We support the non-activated case already */
2535 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2536 /* Values other than LBR and BTF are vendor-specific,
2537 thus reserved and should throw a #GP */
2540 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2543 case 0x200 ... 0x2ff:
2544 return kvm_mtrr_set_msr(vcpu, msr, data);
2545 case MSR_IA32_APICBASE:
2546 return kvm_set_apic_base(vcpu, msr_info);
2547 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2548 return kvm_x2apic_msr_write(vcpu, msr, data);
2549 case MSR_IA32_TSCDEADLINE:
2550 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2552 case MSR_IA32_TSC_ADJUST:
2553 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2554 if (!msr_info->host_initiated) {
2555 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2556 adjust_tsc_offset_guest(vcpu, adj);
2558 vcpu->arch.ia32_tsc_adjust_msr = data;
2561 case MSR_IA32_MISC_ENABLE:
2562 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2563 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2564 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2566 vcpu->arch.ia32_misc_enable_msr = data;
2567 kvm_update_cpuid(vcpu);
2569 vcpu->arch.ia32_misc_enable_msr = data;
2572 case MSR_IA32_SMBASE:
2573 if (!msr_info->host_initiated)
2575 vcpu->arch.smbase = data;
2577 case MSR_IA32_POWER_CTL:
2578 vcpu->arch.msr_ia32_power_ctl = data;
2581 kvm_write_tsc(vcpu, msr_info);
2584 if (!msr_info->host_initiated)
2586 vcpu->arch.smi_count = data;
2588 case MSR_KVM_WALL_CLOCK_NEW:
2589 case MSR_KVM_WALL_CLOCK:
2590 vcpu->kvm->arch.wall_clock = data;
2591 kvm_write_wall_clock(vcpu->kvm, data);
2593 case MSR_KVM_SYSTEM_TIME_NEW:
2594 case MSR_KVM_SYSTEM_TIME: {
2595 struct kvm_arch *ka = &vcpu->kvm->arch;
2597 kvmclock_reset(vcpu);
2599 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2600 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2602 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2603 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2605 ka->boot_vcpu_runs_old_kvmclock = tmp;
2608 vcpu->arch.time = data;
2609 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2611 /* we verify if the enable bit is set... */
2615 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2616 &vcpu->arch.pv_time, data & ~1ULL,
2617 sizeof(struct pvclock_vcpu_time_info)))
2618 vcpu->arch.pv_time_enabled = false;
2620 vcpu->arch.pv_time_enabled = true;
2624 case MSR_KVM_ASYNC_PF_EN:
2625 if (kvm_pv_enable_async_pf(vcpu, data))
2628 case MSR_KVM_STEAL_TIME:
2630 if (unlikely(!sched_info_on()))
2633 if (data & KVM_STEAL_RESERVED_MASK)
2636 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2637 data & KVM_STEAL_VALID_BITS,
2638 sizeof(struct kvm_steal_time)))
2641 vcpu->arch.st.msr_val = data;
2643 if (!(data & KVM_MSR_ENABLED))
2646 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2649 case MSR_KVM_PV_EOI_EN:
2650 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2654 case MSR_KVM_POLL_CONTROL:
2655 /* only enable bit supported */
2656 if (data & (-1ULL << 1))
2659 vcpu->arch.msr_kvm_poll_control = data;
2662 case MSR_IA32_MCG_CTL:
2663 case MSR_IA32_MCG_STATUS:
2664 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2665 return set_msr_mce(vcpu, msr_info);
2667 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2668 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2669 pr = true; /* fall through */
2670 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2671 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2672 if (kvm_pmu_is_valid_msr(vcpu, msr))
2673 return kvm_pmu_set_msr(vcpu, msr_info);
2675 if (pr || data != 0)
2676 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2677 "0x%x data 0x%llx\n", msr, data);
2679 case MSR_K7_CLK_CTL:
2681 * Ignore all writes to this no longer documented MSR.
2682 * Writes are only relevant for old K7 processors,
2683 * all pre-dating SVM, but a recommended workaround from
2684 * AMD for these chips. It is possible to specify the
2685 * affected processor models on the command line, hence
2686 * the need to ignore the workaround.
2689 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2690 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2691 case HV_X64_MSR_CRASH_CTL:
2692 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2693 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2694 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2695 case HV_X64_MSR_TSC_EMULATION_STATUS:
2696 return kvm_hv_set_msr_common(vcpu, msr, data,
2697 msr_info->host_initiated);
2698 case MSR_IA32_BBL_CR_CTL3:
2699 /* Drop writes to this legacy MSR -- see rdmsr
2700 * counterpart for further detail.
2702 if (report_ignored_msrs)
2703 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2706 case MSR_AMD64_OSVW_ID_LENGTH:
2707 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2709 vcpu->arch.osvw.length = data;
2711 case MSR_AMD64_OSVW_STATUS:
2712 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2714 vcpu->arch.osvw.status = data;
2716 case MSR_PLATFORM_INFO:
2717 if (!msr_info->host_initiated ||
2718 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2719 cpuid_fault_enabled(vcpu)))
2721 vcpu->arch.msr_platform_info = data;
2723 case MSR_MISC_FEATURES_ENABLES:
2724 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2725 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2726 !supports_cpuid_fault(vcpu)))
2728 vcpu->arch.msr_misc_features_enables = data;
2731 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2732 return xen_hvm_config(vcpu, data);
2733 if (kvm_pmu_is_valid_msr(vcpu, msr))
2734 return kvm_pmu_set_msr(vcpu, msr_info);
2736 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2740 if (report_ignored_msrs)
2742 "ignored wrmsr: 0x%x data 0x%llx\n",
2749 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2753 * Reads an msr value (of 'msr_index') into 'pdata'.
2754 * Returns 0 on success, non-0 otherwise.
2755 * Assumes vcpu_load() was already called.
2757 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2759 return kvm_x86_ops->get_msr(vcpu, msr);
2761 EXPORT_SYMBOL_GPL(kvm_get_msr);
2763 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2766 u64 mcg_cap = vcpu->arch.mcg_cap;
2767 unsigned bank_num = mcg_cap & 0xff;
2770 case MSR_IA32_P5_MC_ADDR:
2771 case MSR_IA32_P5_MC_TYPE:
2774 case MSR_IA32_MCG_CAP:
2775 data = vcpu->arch.mcg_cap;
2777 case MSR_IA32_MCG_CTL:
2778 if (!(mcg_cap & MCG_CTL_P) && !host)
2780 data = vcpu->arch.mcg_ctl;
2782 case MSR_IA32_MCG_STATUS:
2783 data = vcpu->arch.mcg_status;
2786 if (msr >= MSR_IA32_MC0_CTL &&
2787 msr < MSR_IA32_MCx_CTL(bank_num)) {
2788 u32 offset = msr - MSR_IA32_MC0_CTL;
2789 data = vcpu->arch.mce_banks[offset];
2798 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2800 switch (msr_info->index) {
2801 case MSR_IA32_PLATFORM_ID:
2802 case MSR_IA32_EBL_CR_POWERON:
2803 case MSR_IA32_DEBUGCTLMSR:
2804 case MSR_IA32_LASTBRANCHFROMIP:
2805 case MSR_IA32_LASTBRANCHTOIP:
2806 case MSR_IA32_LASTINTFROMIP:
2807 case MSR_IA32_LASTINTTOIP:
2809 case MSR_K8_TSEG_ADDR:
2810 case MSR_K8_TSEG_MASK:
2811 case MSR_VM_HSAVE_PA:
2812 case MSR_K8_INT_PENDING_MSG:
2813 case MSR_AMD64_NB_CFG:
2814 case MSR_FAM10H_MMIO_CONF_BASE:
2815 case MSR_AMD64_BU_CFG2:
2816 case MSR_IA32_PERF_CTL:
2817 case MSR_AMD64_DC_CFG:
2818 case MSR_F15H_EX_CFG:
2821 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2822 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2823 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2824 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2825 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2826 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2827 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2830 case MSR_IA32_UCODE_REV:
2831 msr_info->data = vcpu->arch.microcode_version;
2833 case MSR_IA32_ARCH_CAPABILITIES:
2834 if (!msr_info->host_initiated &&
2835 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2837 msr_info->data = vcpu->arch.arch_capabilities;
2839 case MSR_IA32_POWER_CTL:
2840 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2843 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2846 case 0x200 ... 0x2ff:
2847 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2848 case 0xcd: /* fsb frequency */
2852 * MSR_EBC_FREQUENCY_ID
2853 * Conservative value valid for even the basic CPU models.
2854 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2855 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2856 * and 266MHz for model 3, or 4. Set Core Clock
2857 * Frequency to System Bus Frequency Ratio to 1 (bits
2858 * 31:24) even though these are only valid for CPU
2859 * models > 2, however guests may end up dividing or
2860 * multiplying by zero otherwise.
2862 case MSR_EBC_FREQUENCY_ID:
2863 msr_info->data = 1 << 24;
2865 case MSR_IA32_APICBASE:
2866 msr_info->data = kvm_get_apic_base(vcpu);
2868 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2869 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2871 case MSR_IA32_TSCDEADLINE:
2872 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2874 case MSR_IA32_TSC_ADJUST:
2875 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2877 case MSR_IA32_MISC_ENABLE:
2878 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2880 case MSR_IA32_SMBASE:
2881 if (!msr_info->host_initiated)
2883 msr_info->data = vcpu->arch.smbase;
2886 msr_info->data = vcpu->arch.smi_count;
2888 case MSR_IA32_PERF_STATUS:
2889 /* TSC increment by tick */
2890 msr_info->data = 1000ULL;
2891 /* CPU multiplier */
2892 msr_info->data |= (((uint64_t)4ULL) << 40);
2895 msr_info->data = vcpu->arch.efer;
2897 case MSR_KVM_WALL_CLOCK:
2898 case MSR_KVM_WALL_CLOCK_NEW:
2899 msr_info->data = vcpu->kvm->arch.wall_clock;
2901 case MSR_KVM_SYSTEM_TIME:
2902 case MSR_KVM_SYSTEM_TIME_NEW:
2903 msr_info->data = vcpu->arch.time;
2905 case MSR_KVM_ASYNC_PF_EN:
2906 msr_info->data = vcpu->arch.apf.msr_val;
2908 case MSR_KVM_STEAL_TIME:
2909 msr_info->data = vcpu->arch.st.msr_val;
2911 case MSR_KVM_PV_EOI_EN:
2912 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2914 case MSR_KVM_POLL_CONTROL:
2915 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2917 case MSR_IA32_P5_MC_ADDR:
2918 case MSR_IA32_P5_MC_TYPE:
2919 case MSR_IA32_MCG_CAP:
2920 case MSR_IA32_MCG_CTL:
2921 case MSR_IA32_MCG_STATUS:
2922 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2923 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2924 msr_info->host_initiated);
2925 case MSR_K7_CLK_CTL:
2927 * Provide expected ramp-up count for K7. All other
2928 * are set to zero, indicating minimum divisors for
2931 * This prevents guest kernels on AMD host with CPU
2932 * type 6, model 8 and higher from exploding due to
2933 * the rdmsr failing.
2935 msr_info->data = 0x20000000;
2937 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2938 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2939 case HV_X64_MSR_CRASH_CTL:
2940 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2941 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2942 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2943 case HV_X64_MSR_TSC_EMULATION_STATUS:
2944 return kvm_hv_get_msr_common(vcpu,
2945 msr_info->index, &msr_info->data,
2946 msr_info->host_initiated);
2948 case MSR_IA32_BBL_CR_CTL3:
2949 /* This legacy MSR exists but isn't fully documented in current
2950 * silicon. It is however accessed by winxp in very narrow
2951 * scenarios where it sets bit #19, itself documented as
2952 * a "reserved" bit. Best effort attempt to source coherent
2953 * read data here should the balance of the register be
2954 * interpreted by the guest:
2956 * L2 cache control register 3: 64GB range, 256KB size,
2957 * enabled, latency 0x1, configured
2959 msr_info->data = 0xbe702111;
2961 case MSR_AMD64_OSVW_ID_LENGTH:
2962 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2964 msr_info->data = vcpu->arch.osvw.length;
2966 case MSR_AMD64_OSVW_STATUS:
2967 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2969 msr_info->data = vcpu->arch.osvw.status;
2971 case MSR_PLATFORM_INFO:
2972 if (!msr_info->host_initiated &&
2973 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2975 msr_info->data = vcpu->arch.msr_platform_info;
2977 case MSR_MISC_FEATURES_ENABLES:
2978 msr_info->data = vcpu->arch.msr_misc_features_enables;
2981 msr_info->data = vcpu->arch.msr_hwcr;
2984 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2985 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2987 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2991 if (report_ignored_msrs)
2992 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3000 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3003 * Read or write a bunch of msrs. All parameters are kernel addresses.
3005 * @return number of msrs set successfully.
3007 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3008 struct kvm_msr_entry *entries,
3009 int (*do_msr)(struct kvm_vcpu *vcpu,
3010 unsigned index, u64 *data))
3014 for (i = 0; i < msrs->nmsrs; ++i)
3015 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3022 * Read or write a bunch of msrs. Parameters are user addresses.
3024 * @return number of msrs set successfully.
3026 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3027 int (*do_msr)(struct kvm_vcpu *vcpu,
3028 unsigned index, u64 *data),
3031 struct kvm_msrs msrs;
3032 struct kvm_msr_entry *entries;
3037 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3041 if (msrs.nmsrs >= MAX_IO_MSRS)
3044 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3045 entries = memdup_user(user_msrs->entries, size);
3046 if (IS_ERR(entries)) {
3047 r = PTR_ERR(entries);
3051 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3056 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3067 static inline bool kvm_can_mwait_in_guest(void)
3069 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3070 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3071 boot_cpu_has(X86_FEATURE_ARAT);
3074 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3079 case KVM_CAP_IRQCHIP:
3081 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3082 case KVM_CAP_SET_TSS_ADDR:
3083 case KVM_CAP_EXT_CPUID:
3084 case KVM_CAP_EXT_EMUL_CPUID:
3085 case KVM_CAP_CLOCKSOURCE:
3087 case KVM_CAP_NOP_IO_DELAY:
3088 case KVM_CAP_MP_STATE:
3089 case KVM_CAP_SYNC_MMU:
3090 case KVM_CAP_USER_NMI:
3091 case KVM_CAP_REINJECT_CONTROL:
3092 case KVM_CAP_IRQ_INJECT_STATUS:
3093 case KVM_CAP_IOEVENTFD:
3094 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3096 case KVM_CAP_PIT_STATE2:
3097 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3098 case KVM_CAP_XEN_HVM:
3099 case KVM_CAP_VCPU_EVENTS:
3100 case KVM_CAP_HYPERV:
3101 case KVM_CAP_HYPERV_VAPIC:
3102 case KVM_CAP_HYPERV_SPIN:
3103 case KVM_CAP_HYPERV_SYNIC:
3104 case KVM_CAP_HYPERV_SYNIC2:
3105 case KVM_CAP_HYPERV_VP_INDEX:
3106 case KVM_CAP_HYPERV_EVENTFD:
3107 case KVM_CAP_HYPERV_TLBFLUSH:
3108 case KVM_CAP_HYPERV_SEND_IPI:
3109 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3110 case KVM_CAP_HYPERV_CPUID:
3111 case KVM_CAP_PCI_SEGMENT:
3112 case KVM_CAP_DEBUGREGS:
3113 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3115 case KVM_CAP_ASYNC_PF:
3116 case KVM_CAP_GET_TSC_KHZ:
3117 case KVM_CAP_KVMCLOCK_CTRL:
3118 case KVM_CAP_READONLY_MEM:
3119 case KVM_CAP_HYPERV_TIME:
3120 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3121 case KVM_CAP_TSC_DEADLINE_TIMER:
3122 case KVM_CAP_DISABLE_QUIRKS:
3123 case KVM_CAP_SET_BOOT_CPU_ID:
3124 case KVM_CAP_SPLIT_IRQCHIP:
3125 case KVM_CAP_IMMEDIATE_EXIT:
3126 case KVM_CAP_PMU_EVENT_FILTER:
3127 case KVM_CAP_GET_MSR_FEATURES:
3128 case KVM_CAP_MSR_PLATFORM_INFO:
3129 case KVM_CAP_EXCEPTION_PAYLOAD:
3132 case KVM_CAP_SYNC_REGS:
3133 r = KVM_SYNC_X86_VALID_FIELDS;
3135 case KVM_CAP_ADJUST_CLOCK:
3136 r = KVM_CLOCK_TSC_STABLE;
3138 case KVM_CAP_X86_DISABLE_EXITS:
3139 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3140 KVM_X86_DISABLE_EXITS_CSTATE;
3141 if(kvm_can_mwait_in_guest())
3142 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3144 case KVM_CAP_X86_SMM:
3145 /* SMBASE is usually relocated above 1M on modern chipsets,
3146 * and SMM handlers might indeed rely on 4G segment limits,
3147 * so do not report SMM to be available if real mode is
3148 * emulated via vm86 mode. Still, do not go to great lengths
3149 * to avoid userspace's usage of the feature, because it is a
3150 * fringe case that is not enabled except via specific settings
3151 * of the module parameters.
3153 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3156 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3158 case KVM_CAP_NR_VCPUS:
3159 r = KVM_SOFT_MAX_VCPUS;
3161 case KVM_CAP_MAX_VCPUS:
3164 case KVM_CAP_MAX_VCPU_ID:
3165 r = KVM_MAX_VCPU_ID;
3167 case KVM_CAP_PV_MMU: /* obsolete */
3171 r = KVM_MAX_MCE_BANKS;
3174 r = boot_cpu_has(X86_FEATURE_XSAVE);
3176 case KVM_CAP_TSC_CONTROL:
3177 r = kvm_has_tsc_control;
3179 case KVM_CAP_X2APIC_API:
3180 r = KVM_X2APIC_API_VALID_FLAGS;
3182 case KVM_CAP_NESTED_STATE:
3183 r = kvm_x86_ops->get_nested_state ?
3184 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3193 long kvm_arch_dev_ioctl(struct file *filp,
3194 unsigned int ioctl, unsigned long arg)
3196 void __user *argp = (void __user *)arg;
3200 case KVM_GET_MSR_INDEX_LIST: {
3201 struct kvm_msr_list __user *user_msr_list = argp;
3202 struct kvm_msr_list msr_list;
3206 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3209 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3210 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3213 if (n < msr_list.nmsrs)
3216 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3217 num_msrs_to_save * sizeof(u32)))
3219 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3221 num_emulated_msrs * sizeof(u32)))
3226 case KVM_GET_SUPPORTED_CPUID:
3227 case KVM_GET_EMULATED_CPUID: {
3228 struct kvm_cpuid2 __user *cpuid_arg = argp;
3229 struct kvm_cpuid2 cpuid;
3232 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3235 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3246 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3248 if (copy_to_user(argp, &kvm_mce_cap_supported,
3249 sizeof(kvm_mce_cap_supported)))
3253 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3254 struct kvm_msr_list __user *user_msr_list = argp;
3255 struct kvm_msr_list msr_list;
3259 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3262 msr_list.nmsrs = num_msr_based_features;
3263 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3266 if (n < msr_list.nmsrs)
3269 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3270 num_msr_based_features * sizeof(u32)))
3276 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3286 static void wbinvd_ipi(void *garbage)
3291 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3293 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3296 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3298 /* Address WBINVD may be executed by guest */
3299 if (need_emulate_wbinvd(vcpu)) {
3300 if (kvm_x86_ops->has_wbinvd_exit())
3301 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3302 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3303 smp_call_function_single(vcpu->cpu,
3304 wbinvd_ipi, NULL, 1);
3307 kvm_x86_ops->vcpu_load(vcpu, cpu);
3309 /* Apply any externally detected TSC adjustments (due to suspend) */
3310 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3311 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3312 vcpu->arch.tsc_offset_adjustment = 0;
3313 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3316 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3317 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3318 rdtsc() - vcpu->arch.last_host_tsc;
3320 mark_tsc_unstable("KVM discovered backwards TSC");
3322 if (kvm_check_tsc_unstable()) {
3323 u64 offset = kvm_compute_tsc_offset(vcpu,
3324 vcpu->arch.last_guest_tsc);
3325 kvm_vcpu_write_tsc_offset(vcpu, offset);
3326 vcpu->arch.tsc_catchup = 1;
3329 if (kvm_lapic_hv_timer_in_use(vcpu))
3330 kvm_lapic_restart_hv_timer(vcpu);
3333 * On a host with synchronized TSC, there is no need to update
3334 * kvmclock on vcpu->cpu migration
3336 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3337 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3338 if (vcpu->cpu != cpu)
3339 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3343 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3346 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3348 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3351 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3353 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3354 &vcpu->arch.st.steal.preempted,
3355 offsetof(struct kvm_steal_time, preempted),
3356 sizeof(vcpu->arch.st.steal.preempted));
3359 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3363 if (vcpu->preempted)
3364 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3367 * Disable page faults because we're in atomic context here.
3368 * kvm_write_guest_offset_cached() would call might_fault()
3369 * that relies on pagefault_disable() to tell if there's a
3370 * bug. NOTE: the write to guest memory may not go through if
3371 * during postcopy live migration or if there's heavy guest
3374 pagefault_disable();
3376 * kvm_memslots() will be called by
3377 * kvm_write_guest_offset_cached() so take the srcu lock.
3379 idx = srcu_read_lock(&vcpu->kvm->srcu);
3380 kvm_steal_time_set_preempted(vcpu);
3381 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3383 kvm_x86_ops->vcpu_put(vcpu);
3384 vcpu->arch.last_host_tsc = rdtsc();
3386 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3387 * on every vmexit, but if not, we might have a stale dr6 from the
3388 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3393 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3394 struct kvm_lapic_state *s)
3396 if (vcpu->arch.apicv_active)
3397 kvm_x86_ops->sync_pir_to_irr(vcpu);
3399 return kvm_apic_get_state(vcpu, s);
3402 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3403 struct kvm_lapic_state *s)
3407 r = kvm_apic_set_state(vcpu, s);
3410 update_cr8_intercept(vcpu);
3415 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3417 return (!lapic_in_kernel(vcpu) ||
3418 kvm_apic_accept_pic_intr(vcpu));
3422 * if userspace requested an interrupt window, check that the
3423 * interrupt window is open.
3425 * No need to exit to userspace if we already have an interrupt queued.
3427 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3429 return kvm_arch_interrupt_allowed(vcpu) &&
3430 !kvm_cpu_has_interrupt(vcpu) &&
3431 !kvm_event_needs_reinjection(vcpu) &&
3432 kvm_cpu_accept_dm_intr(vcpu);
3435 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3436 struct kvm_interrupt *irq)
3438 if (irq->irq >= KVM_NR_INTERRUPTS)
3441 if (!irqchip_in_kernel(vcpu->kvm)) {
3442 kvm_queue_interrupt(vcpu, irq->irq, false);
3443 kvm_make_request(KVM_REQ_EVENT, vcpu);
3448 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3449 * fail for in-kernel 8259.
3451 if (pic_in_kernel(vcpu->kvm))
3454 if (vcpu->arch.pending_external_vector != -1)
3457 vcpu->arch.pending_external_vector = irq->irq;
3458 kvm_make_request(KVM_REQ_EVENT, vcpu);
3462 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3464 kvm_inject_nmi(vcpu);
3469 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3471 kvm_make_request(KVM_REQ_SMI, vcpu);
3476 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3477 struct kvm_tpr_access_ctl *tac)
3481 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3485 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3489 unsigned bank_num = mcg_cap & 0xff, bank;
3492 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3494 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3497 vcpu->arch.mcg_cap = mcg_cap;
3498 /* Init IA32_MCG_CTL to all 1s */
3499 if (mcg_cap & MCG_CTL_P)
3500 vcpu->arch.mcg_ctl = ~(u64)0;
3501 /* Init IA32_MCi_CTL to all 1s */
3502 for (bank = 0; bank < bank_num; bank++)
3503 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3505 if (kvm_x86_ops->setup_mce)
3506 kvm_x86_ops->setup_mce(vcpu);
3511 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3512 struct kvm_x86_mce *mce)
3514 u64 mcg_cap = vcpu->arch.mcg_cap;
3515 unsigned bank_num = mcg_cap & 0xff;
3516 u64 *banks = vcpu->arch.mce_banks;
3518 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3521 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3522 * reporting is disabled
3524 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3525 vcpu->arch.mcg_ctl != ~(u64)0)
3527 banks += 4 * mce->bank;
3529 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3530 * reporting is disabled for the bank
3532 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3534 if (mce->status & MCI_STATUS_UC) {
3535 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3536 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3537 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3540 if (banks[1] & MCI_STATUS_VAL)
3541 mce->status |= MCI_STATUS_OVER;
3542 banks[2] = mce->addr;
3543 banks[3] = mce->misc;
3544 vcpu->arch.mcg_status = mce->mcg_status;
3545 banks[1] = mce->status;
3546 kvm_queue_exception(vcpu, MC_VECTOR);
3547 } else if (!(banks[1] & MCI_STATUS_VAL)
3548 || !(banks[1] & MCI_STATUS_UC)) {
3549 if (banks[1] & MCI_STATUS_VAL)
3550 mce->status |= MCI_STATUS_OVER;
3551 banks[2] = mce->addr;
3552 banks[3] = mce->misc;
3553 banks[1] = mce->status;
3555 banks[1] |= MCI_STATUS_OVER;
3559 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3560 struct kvm_vcpu_events *events)
3565 * The API doesn't provide the instruction length for software
3566 * exceptions, so don't report them. As long as the guest RIP
3567 * isn't advanced, we should expect to encounter the exception
3570 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3571 events->exception.injected = 0;
3572 events->exception.pending = 0;
3574 events->exception.injected = vcpu->arch.exception.injected;
3575 events->exception.pending = vcpu->arch.exception.pending;
3577 * For ABI compatibility, deliberately conflate
3578 * pending and injected exceptions when
3579 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3581 if (!vcpu->kvm->arch.exception_payload_enabled)
3582 events->exception.injected |=
3583 vcpu->arch.exception.pending;
3585 events->exception.nr = vcpu->arch.exception.nr;
3586 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3587 events->exception.error_code = vcpu->arch.exception.error_code;
3588 events->exception_has_payload = vcpu->arch.exception.has_payload;
3589 events->exception_payload = vcpu->arch.exception.payload;
3591 events->interrupt.injected =
3592 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3593 events->interrupt.nr = vcpu->arch.interrupt.nr;
3594 events->interrupt.soft = 0;
3595 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3597 events->nmi.injected = vcpu->arch.nmi_injected;
3598 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3599 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3600 events->nmi.pad = 0;
3602 events->sipi_vector = 0; /* never valid when reporting to user space */
3604 events->smi.smm = is_smm(vcpu);
3605 events->smi.pending = vcpu->arch.smi_pending;
3606 events->smi.smm_inside_nmi =
3607 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3608 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3610 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3611 | KVM_VCPUEVENT_VALID_SHADOW
3612 | KVM_VCPUEVENT_VALID_SMM);
3613 if (vcpu->kvm->arch.exception_payload_enabled)
3614 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3616 memset(&events->reserved, 0, sizeof(events->reserved));
3619 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3621 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3622 struct kvm_vcpu_events *events)
3624 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3625 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3626 | KVM_VCPUEVENT_VALID_SHADOW
3627 | KVM_VCPUEVENT_VALID_SMM
3628 | KVM_VCPUEVENT_VALID_PAYLOAD))
3631 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3632 if (!vcpu->kvm->arch.exception_payload_enabled)
3634 if (events->exception.pending)
3635 events->exception.injected = 0;
3637 events->exception_has_payload = 0;
3639 events->exception.pending = 0;
3640 events->exception_has_payload = 0;
3643 if ((events->exception.injected || events->exception.pending) &&
3644 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3647 /* INITs are latched while in SMM */
3648 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3649 (events->smi.smm || events->smi.pending) &&
3650 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3654 vcpu->arch.exception.injected = events->exception.injected;
3655 vcpu->arch.exception.pending = events->exception.pending;
3656 vcpu->arch.exception.nr = events->exception.nr;
3657 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3658 vcpu->arch.exception.error_code = events->exception.error_code;
3659 vcpu->arch.exception.has_payload = events->exception_has_payload;
3660 vcpu->arch.exception.payload = events->exception_payload;
3662 vcpu->arch.interrupt.injected = events->interrupt.injected;
3663 vcpu->arch.interrupt.nr = events->interrupt.nr;
3664 vcpu->arch.interrupt.soft = events->interrupt.soft;
3665 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3666 kvm_x86_ops->set_interrupt_shadow(vcpu,
3667 events->interrupt.shadow);
3669 vcpu->arch.nmi_injected = events->nmi.injected;
3670 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3671 vcpu->arch.nmi_pending = events->nmi.pending;
3672 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3674 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3675 lapic_in_kernel(vcpu))
3676 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3678 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3679 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3680 if (events->smi.smm)
3681 vcpu->arch.hflags |= HF_SMM_MASK;
3683 vcpu->arch.hflags &= ~HF_SMM_MASK;
3684 kvm_smm_changed(vcpu);
3687 vcpu->arch.smi_pending = events->smi.pending;
3689 if (events->smi.smm) {
3690 if (events->smi.smm_inside_nmi)
3691 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3693 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3694 if (lapic_in_kernel(vcpu)) {
3695 if (events->smi.latched_init)
3696 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3698 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3703 kvm_make_request(KVM_REQ_EVENT, vcpu);
3708 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3709 struct kvm_debugregs *dbgregs)
3713 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3714 kvm_get_dr(vcpu, 6, &val);
3716 dbgregs->dr7 = vcpu->arch.dr7;
3718 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3721 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3722 struct kvm_debugregs *dbgregs)
3727 if (dbgregs->dr6 & ~0xffffffffull)
3729 if (dbgregs->dr7 & ~0xffffffffull)
3732 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3733 kvm_update_dr0123(vcpu);
3734 vcpu->arch.dr6 = dbgregs->dr6;
3735 kvm_update_dr6(vcpu);
3736 vcpu->arch.dr7 = dbgregs->dr7;
3737 kvm_update_dr7(vcpu);
3742 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3744 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3746 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3747 u64 xstate_bv = xsave->header.xfeatures;
3751 * Copy legacy XSAVE area, to avoid complications with CPUID
3752 * leaves 0 and 1 in the loop below.
3754 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3757 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3758 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3761 * Copy each region from the possibly compacted offset to the
3762 * non-compacted offset.
3764 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3766 u64 xfeature_mask = valid & -valid;
3767 int xfeature_nr = fls64(xfeature_mask) - 1;
3768 void *src = get_xsave_addr(xsave, xfeature_nr);
3771 u32 size, offset, ecx, edx;
3772 cpuid_count(XSTATE_CPUID, xfeature_nr,
3773 &size, &offset, &ecx, &edx);
3774 if (xfeature_nr == XFEATURE_PKRU)
3775 memcpy(dest + offset, &vcpu->arch.pkru,
3776 sizeof(vcpu->arch.pkru));
3778 memcpy(dest + offset, src, size);
3782 valid -= xfeature_mask;
3786 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3788 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3789 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3793 * Copy legacy XSAVE area, to avoid complications with CPUID
3794 * leaves 0 and 1 in the loop below.
3796 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3798 /* Set XSTATE_BV and possibly XCOMP_BV. */
3799 xsave->header.xfeatures = xstate_bv;
3800 if (boot_cpu_has(X86_FEATURE_XSAVES))
3801 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3804 * Copy each region from the non-compacted offset to the
3805 * possibly compacted offset.
3807 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3809 u64 xfeature_mask = valid & -valid;
3810 int xfeature_nr = fls64(xfeature_mask) - 1;
3811 void *dest = get_xsave_addr(xsave, xfeature_nr);
3814 u32 size, offset, ecx, edx;
3815 cpuid_count(XSTATE_CPUID, xfeature_nr,
3816 &size, &offset, &ecx, &edx);
3817 if (xfeature_nr == XFEATURE_PKRU)
3818 memcpy(&vcpu->arch.pkru, src + offset,
3819 sizeof(vcpu->arch.pkru));
3821 memcpy(dest, src + offset, size);
3824 valid -= xfeature_mask;
3828 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3829 struct kvm_xsave *guest_xsave)
3831 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3832 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3833 fill_xsave((u8 *) guest_xsave->region, vcpu);
3835 memcpy(guest_xsave->region,
3836 &vcpu->arch.guest_fpu->state.fxsave,
3837 sizeof(struct fxregs_state));
3838 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3839 XFEATURE_MASK_FPSSE;
3843 #define XSAVE_MXCSR_OFFSET 24
3845 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3846 struct kvm_xsave *guest_xsave)
3849 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3850 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3852 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3854 * Here we allow setting states that are not present in
3855 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3856 * with old userspace.
3858 if (xstate_bv & ~kvm_supported_xcr0() ||
3859 mxcsr & ~mxcsr_feature_mask)
3861 load_xsave(vcpu, (u8 *)guest_xsave->region);
3863 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3864 mxcsr & ~mxcsr_feature_mask)
3866 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3867 guest_xsave->region, sizeof(struct fxregs_state));
3872 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3873 struct kvm_xcrs *guest_xcrs)
3875 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3876 guest_xcrs->nr_xcrs = 0;
3880 guest_xcrs->nr_xcrs = 1;
3881 guest_xcrs->flags = 0;
3882 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3883 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3886 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3887 struct kvm_xcrs *guest_xcrs)
3891 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3894 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3897 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3898 /* Only support XCR0 currently */
3899 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3900 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3901 guest_xcrs->xcrs[i].value);
3910 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3911 * stopped by the hypervisor. This function will be called from the host only.
3912 * EINVAL is returned when the host attempts to set the flag for a guest that
3913 * does not support pv clocks.
3915 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3917 if (!vcpu->arch.pv_time_enabled)
3919 vcpu->arch.pvclock_set_guest_stopped_request = true;
3920 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3924 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3925 struct kvm_enable_cap *cap)
3928 uint16_t vmcs_version;
3929 void __user *user_ptr;
3935 case KVM_CAP_HYPERV_SYNIC2:
3940 case KVM_CAP_HYPERV_SYNIC:
3941 if (!irqchip_in_kernel(vcpu->kvm))
3943 return kvm_hv_activate_synic(vcpu, cap->cap ==
3944 KVM_CAP_HYPERV_SYNIC2);
3945 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3946 if (!kvm_x86_ops->nested_enable_evmcs)
3948 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3950 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3951 if (copy_to_user(user_ptr, &vmcs_version,
3952 sizeof(vmcs_version)))
3962 long kvm_arch_vcpu_ioctl(struct file *filp,
3963 unsigned int ioctl, unsigned long arg)
3965 struct kvm_vcpu *vcpu = filp->private_data;
3966 void __user *argp = (void __user *)arg;
3969 struct kvm_lapic_state *lapic;
3970 struct kvm_xsave *xsave;
3971 struct kvm_xcrs *xcrs;
3979 case KVM_GET_LAPIC: {
3981 if (!lapic_in_kernel(vcpu))
3983 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3984 GFP_KERNEL_ACCOUNT);
3989 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3993 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3998 case KVM_SET_LAPIC: {
4000 if (!lapic_in_kernel(vcpu))
4002 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4003 if (IS_ERR(u.lapic)) {
4004 r = PTR_ERR(u.lapic);
4008 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4011 case KVM_INTERRUPT: {
4012 struct kvm_interrupt irq;
4015 if (copy_from_user(&irq, argp, sizeof(irq)))
4017 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4021 r = kvm_vcpu_ioctl_nmi(vcpu);
4025 r = kvm_vcpu_ioctl_smi(vcpu);
4028 case KVM_SET_CPUID: {
4029 struct kvm_cpuid __user *cpuid_arg = argp;
4030 struct kvm_cpuid cpuid;
4033 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4035 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4038 case KVM_SET_CPUID2: {
4039 struct kvm_cpuid2 __user *cpuid_arg = argp;
4040 struct kvm_cpuid2 cpuid;
4043 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4045 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4046 cpuid_arg->entries);
4049 case KVM_GET_CPUID2: {
4050 struct kvm_cpuid2 __user *cpuid_arg = argp;
4051 struct kvm_cpuid2 cpuid;
4054 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4056 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4057 cpuid_arg->entries);
4061 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4066 case KVM_GET_MSRS: {
4067 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4068 r = msr_io(vcpu, argp, do_get_msr, 1);
4069 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4072 case KVM_SET_MSRS: {
4073 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4074 r = msr_io(vcpu, argp, do_set_msr, 0);
4075 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4078 case KVM_TPR_ACCESS_REPORTING: {
4079 struct kvm_tpr_access_ctl tac;
4082 if (copy_from_user(&tac, argp, sizeof(tac)))
4084 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4088 if (copy_to_user(argp, &tac, sizeof(tac)))
4093 case KVM_SET_VAPIC_ADDR: {
4094 struct kvm_vapic_addr va;
4098 if (!lapic_in_kernel(vcpu))
4101 if (copy_from_user(&va, argp, sizeof(va)))
4103 idx = srcu_read_lock(&vcpu->kvm->srcu);
4104 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4105 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4108 case KVM_X86_SETUP_MCE: {
4112 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4114 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4117 case KVM_X86_SET_MCE: {
4118 struct kvm_x86_mce mce;
4121 if (copy_from_user(&mce, argp, sizeof(mce)))
4123 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4126 case KVM_GET_VCPU_EVENTS: {
4127 struct kvm_vcpu_events events;
4129 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4132 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4137 case KVM_SET_VCPU_EVENTS: {
4138 struct kvm_vcpu_events events;
4141 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4144 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4147 case KVM_GET_DEBUGREGS: {
4148 struct kvm_debugregs dbgregs;
4150 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4153 if (copy_to_user(argp, &dbgregs,
4154 sizeof(struct kvm_debugregs)))
4159 case KVM_SET_DEBUGREGS: {
4160 struct kvm_debugregs dbgregs;
4163 if (copy_from_user(&dbgregs, argp,
4164 sizeof(struct kvm_debugregs)))
4167 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4170 case KVM_GET_XSAVE: {
4171 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4176 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4179 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4184 case KVM_SET_XSAVE: {
4185 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4186 if (IS_ERR(u.xsave)) {
4187 r = PTR_ERR(u.xsave);
4191 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4194 case KVM_GET_XCRS: {
4195 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4200 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4203 if (copy_to_user(argp, u.xcrs,
4204 sizeof(struct kvm_xcrs)))
4209 case KVM_SET_XCRS: {
4210 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4211 if (IS_ERR(u.xcrs)) {
4212 r = PTR_ERR(u.xcrs);
4216 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4219 case KVM_SET_TSC_KHZ: {
4223 user_tsc_khz = (u32)arg;
4225 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4228 if (user_tsc_khz == 0)
4229 user_tsc_khz = tsc_khz;
4231 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4236 case KVM_GET_TSC_KHZ: {
4237 r = vcpu->arch.virtual_tsc_khz;
4240 case KVM_KVMCLOCK_CTRL: {
4241 r = kvm_set_guest_paused(vcpu);
4244 case KVM_ENABLE_CAP: {
4245 struct kvm_enable_cap cap;
4248 if (copy_from_user(&cap, argp, sizeof(cap)))
4250 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4253 case KVM_GET_NESTED_STATE: {
4254 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4258 if (!kvm_x86_ops->get_nested_state)
4261 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4263 if (get_user(user_data_size, &user_kvm_nested_state->size))
4266 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4271 if (r > user_data_size) {
4272 if (put_user(r, &user_kvm_nested_state->size))
4282 case KVM_SET_NESTED_STATE: {
4283 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4284 struct kvm_nested_state kvm_state;
4287 if (!kvm_x86_ops->set_nested_state)
4291 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4295 if (kvm_state.size < sizeof(kvm_state))
4298 if (kvm_state.flags &
4299 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4300 | KVM_STATE_NESTED_EVMCS))
4303 /* nested_run_pending implies guest_mode. */
4304 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4305 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4308 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4311 case KVM_GET_SUPPORTED_HV_CPUID: {
4312 struct kvm_cpuid2 __user *cpuid_arg = argp;
4313 struct kvm_cpuid2 cpuid;
4316 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4319 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4320 cpuid_arg->entries);
4325 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4340 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4342 return VM_FAULT_SIGBUS;
4345 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4349 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4351 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4355 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4358 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4361 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4362 unsigned long kvm_nr_mmu_pages)
4364 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4367 mutex_lock(&kvm->slots_lock);
4369 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4370 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4372 mutex_unlock(&kvm->slots_lock);
4376 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4378 return kvm->arch.n_max_mmu_pages;
4381 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4383 struct kvm_pic *pic = kvm->arch.vpic;
4387 switch (chip->chip_id) {
4388 case KVM_IRQCHIP_PIC_MASTER:
4389 memcpy(&chip->chip.pic, &pic->pics[0],
4390 sizeof(struct kvm_pic_state));
4392 case KVM_IRQCHIP_PIC_SLAVE:
4393 memcpy(&chip->chip.pic, &pic->pics[1],
4394 sizeof(struct kvm_pic_state));
4396 case KVM_IRQCHIP_IOAPIC:
4397 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4406 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4408 struct kvm_pic *pic = kvm->arch.vpic;
4412 switch (chip->chip_id) {
4413 case KVM_IRQCHIP_PIC_MASTER:
4414 spin_lock(&pic->lock);
4415 memcpy(&pic->pics[0], &chip->chip.pic,
4416 sizeof(struct kvm_pic_state));
4417 spin_unlock(&pic->lock);
4419 case KVM_IRQCHIP_PIC_SLAVE:
4420 spin_lock(&pic->lock);
4421 memcpy(&pic->pics[1], &chip->chip.pic,
4422 sizeof(struct kvm_pic_state));
4423 spin_unlock(&pic->lock);
4425 case KVM_IRQCHIP_IOAPIC:
4426 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4432 kvm_pic_update_irq(pic);
4436 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4438 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4440 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4442 mutex_lock(&kps->lock);
4443 memcpy(ps, &kps->channels, sizeof(*ps));
4444 mutex_unlock(&kps->lock);
4448 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4451 struct kvm_pit *pit = kvm->arch.vpit;
4453 mutex_lock(&pit->pit_state.lock);
4454 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4455 for (i = 0; i < 3; i++)
4456 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4457 mutex_unlock(&pit->pit_state.lock);
4461 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4463 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4464 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4465 sizeof(ps->channels));
4466 ps->flags = kvm->arch.vpit->pit_state.flags;
4467 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4468 memset(&ps->reserved, 0, sizeof(ps->reserved));
4472 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4476 u32 prev_legacy, cur_legacy;
4477 struct kvm_pit *pit = kvm->arch.vpit;
4479 mutex_lock(&pit->pit_state.lock);
4480 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4481 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4482 if (!prev_legacy && cur_legacy)
4484 memcpy(&pit->pit_state.channels, &ps->channels,
4485 sizeof(pit->pit_state.channels));
4486 pit->pit_state.flags = ps->flags;
4487 for (i = 0; i < 3; i++)
4488 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4490 mutex_unlock(&pit->pit_state.lock);
4494 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4495 struct kvm_reinject_control *control)
4497 struct kvm_pit *pit = kvm->arch.vpit;
4502 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4503 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4504 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4506 mutex_lock(&pit->pit_state.lock);
4507 kvm_pit_set_reinject(pit, control->pit_reinject);
4508 mutex_unlock(&pit->pit_state.lock);
4514 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4515 * @kvm: kvm instance
4516 * @log: slot id and address to which we copy the log
4518 * Steps 1-4 below provide general overview of dirty page logging. See
4519 * kvm_get_dirty_log_protect() function description for additional details.
4521 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4522 * always flush the TLB (step 4) even if previous step failed and the dirty
4523 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4524 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4525 * writes will be marked dirty for next log read.
4527 * 1. Take a snapshot of the bit and clear it if needed.
4528 * 2. Write protect the corresponding page.
4529 * 3. Copy the snapshot to the userspace.
4530 * 4. Flush TLB's if needed.
4532 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4537 mutex_lock(&kvm->slots_lock);
4540 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4542 if (kvm_x86_ops->flush_log_dirty)
4543 kvm_x86_ops->flush_log_dirty(kvm);
4545 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4548 * All the TLBs can be flushed out of mmu lock, see the comments in
4549 * kvm_mmu_slot_remove_write_access().
4551 lockdep_assert_held(&kvm->slots_lock);
4553 kvm_flush_remote_tlbs(kvm);
4555 mutex_unlock(&kvm->slots_lock);
4559 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4564 mutex_lock(&kvm->slots_lock);
4567 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4569 if (kvm_x86_ops->flush_log_dirty)
4570 kvm_x86_ops->flush_log_dirty(kvm);
4572 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4575 * All the TLBs can be flushed out of mmu lock, see the comments in
4576 * kvm_mmu_slot_remove_write_access().
4578 lockdep_assert_held(&kvm->slots_lock);
4580 kvm_flush_remote_tlbs(kvm);
4582 mutex_unlock(&kvm->slots_lock);
4586 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4589 if (!irqchip_in_kernel(kvm))
4592 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4593 irq_event->irq, irq_event->level,
4598 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4599 struct kvm_enable_cap *cap)
4607 case KVM_CAP_DISABLE_QUIRKS:
4608 kvm->arch.disabled_quirks = cap->args[0];
4611 case KVM_CAP_SPLIT_IRQCHIP: {
4612 mutex_lock(&kvm->lock);
4614 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4615 goto split_irqchip_unlock;
4617 if (irqchip_in_kernel(kvm))
4618 goto split_irqchip_unlock;
4619 if (kvm->created_vcpus)
4620 goto split_irqchip_unlock;
4621 r = kvm_setup_empty_irq_routing(kvm);
4623 goto split_irqchip_unlock;
4624 /* Pairs with irqchip_in_kernel. */
4626 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4627 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4629 split_irqchip_unlock:
4630 mutex_unlock(&kvm->lock);
4633 case KVM_CAP_X2APIC_API:
4635 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4638 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4639 kvm->arch.x2apic_format = true;
4640 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4641 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4645 case KVM_CAP_X86_DISABLE_EXITS:
4647 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4650 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4651 kvm_can_mwait_in_guest())
4652 kvm->arch.mwait_in_guest = true;
4653 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4654 kvm->arch.hlt_in_guest = true;
4655 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4656 kvm->arch.pause_in_guest = true;
4657 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4658 kvm->arch.cstate_in_guest = true;
4661 case KVM_CAP_MSR_PLATFORM_INFO:
4662 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4665 case KVM_CAP_EXCEPTION_PAYLOAD:
4666 kvm->arch.exception_payload_enabled = cap->args[0];
4676 long kvm_arch_vm_ioctl(struct file *filp,
4677 unsigned int ioctl, unsigned long arg)
4679 struct kvm *kvm = filp->private_data;
4680 void __user *argp = (void __user *)arg;
4683 * This union makes it completely explicit to gcc-3.x
4684 * that these two variables' stack usage should be
4685 * combined, not added together.
4688 struct kvm_pit_state ps;
4689 struct kvm_pit_state2 ps2;
4690 struct kvm_pit_config pit_config;
4694 case KVM_SET_TSS_ADDR:
4695 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4697 case KVM_SET_IDENTITY_MAP_ADDR: {
4700 mutex_lock(&kvm->lock);
4702 if (kvm->created_vcpus)
4703 goto set_identity_unlock;
4705 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4706 goto set_identity_unlock;
4707 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4708 set_identity_unlock:
4709 mutex_unlock(&kvm->lock);
4712 case KVM_SET_NR_MMU_PAGES:
4713 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4715 case KVM_GET_NR_MMU_PAGES:
4716 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4718 case KVM_CREATE_IRQCHIP: {
4719 mutex_lock(&kvm->lock);
4722 if (irqchip_in_kernel(kvm))
4723 goto create_irqchip_unlock;
4726 if (kvm->created_vcpus)
4727 goto create_irqchip_unlock;
4729 r = kvm_pic_init(kvm);
4731 goto create_irqchip_unlock;
4733 r = kvm_ioapic_init(kvm);
4735 kvm_pic_destroy(kvm);
4736 goto create_irqchip_unlock;
4739 r = kvm_setup_default_irq_routing(kvm);
4741 kvm_ioapic_destroy(kvm);
4742 kvm_pic_destroy(kvm);
4743 goto create_irqchip_unlock;
4745 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4747 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4748 create_irqchip_unlock:
4749 mutex_unlock(&kvm->lock);
4752 case KVM_CREATE_PIT:
4753 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4755 case KVM_CREATE_PIT2:
4757 if (copy_from_user(&u.pit_config, argp,
4758 sizeof(struct kvm_pit_config)))
4761 mutex_lock(&kvm->lock);
4764 goto create_pit_unlock;
4766 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4770 mutex_unlock(&kvm->lock);
4772 case KVM_GET_IRQCHIP: {
4773 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4774 struct kvm_irqchip *chip;
4776 chip = memdup_user(argp, sizeof(*chip));
4783 if (!irqchip_kernel(kvm))
4784 goto get_irqchip_out;
4785 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4787 goto get_irqchip_out;
4789 if (copy_to_user(argp, chip, sizeof(*chip)))
4790 goto get_irqchip_out;
4796 case KVM_SET_IRQCHIP: {
4797 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4798 struct kvm_irqchip *chip;
4800 chip = memdup_user(argp, sizeof(*chip));
4807 if (!irqchip_kernel(kvm))
4808 goto set_irqchip_out;
4809 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4811 goto set_irqchip_out;
4819 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4822 if (!kvm->arch.vpit)
4824 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4828 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4835 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4838 if (!kvm->arch.vpit)
4840 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4843 case KVM_GET_PIT2: {
4845 if (!kvm->arch.vpit)
4847 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4851 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4856 case KVM_SET_PIT2: {
4858 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4861 if (!kvm->arch.vpit)
4863 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4866 case KVM_REINJECT_CONTROL: {
4867 struct kvm_reinject_control control;
4869 if (copy_from_user(&control, argp, sizeof(control)))
4871 r = kvm_vm_ioctl_reinject(kvm, &control);
4874 case KVM_SET_BOOT_CPU_ID:
4876 mutex_lock(&kvm->lock);
4877 if (kvm->created_vcpus)
4880 kvm->arch.bsp_vcpu_id = arg;
4881 mutex_unlock(&kvm->lock);
4883 case KVM_XEN_HVM_CONFIG: {
4884 struct kvm_xen_hvm_config xhc;
4886 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4891 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4895 case KVM_SET_CLOCK: {
4896 struct kvm_clock_data user_ns;
4900 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4909 * TODO: userspace has to take care of races with VCPU_RUN, so
4910 * kvm_gen_update_masterclock() can be cut down to locked
4911 * pvclock_update_vm_gtod_copy().
4913 kvm_gen_update_masterclock(kvm);
4914 now_ns = get_kvmclock_ns(kvm);
4915 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4916 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4919 case KVM_GET_CLOCK: {
4920 struct kvm_clock_data user_ns;
4923 now_ns = get_kvmclock_ns(kvm);
4924 user_ns.clock = now_ns;
4925 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4926 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4929 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4934 case KVM_MEMORY_ENCRYPT_OP: {
4936 if (kvm_x86_ops->mem_enc_op)
4937 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4940 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4941 struct kvm_enc_region region;
4944 if (copy_from_user(®ion, argp, sizeof(region)))
4948 if (kvm_x86_ops->mem_enc_reg_region)
4949 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4952 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4953 struct kvm_enc_region region;
4956 if (copy_from_user(®ion, argp, sizeof(region)))
4960 if (kvm_x86_ops->mem_enc_unreg_region)
4961 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4964 case KVM_HYPERV_EVENTFD: {
4965 struct kvm_hyperv_eventfd hvevfd;
4968 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4970 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4973 case KVM_SET_PMU_EVENT_FILTER:
4974 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
4983 static void kvm_init_msr_list(void)
4988 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4989 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4993 * Even MSRs that are valid in the host may not be exposed
4994 * to the guests in some cases.
4996 switch (msrs_to_save[i]) {
4997 case MSR_IA32_BNDCFGS:
4998 if (!kvm_mpx_supported())
5002 if (!kvm_x86_ops->rdtscp_supported())
5005 case MSR_IA32_RTIT_CTL:
5006 case MSR_IA32_RTIT_STATUS:
5007 if (!kvm_x86_ops->pt_supported())
5010 case MSR_IA32_RTIT_CR3_MATCH:
5011 if (!kvm_x86_ops->pt_supported() ||
5012 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5015 case MSR_IA32_RTIT_OUTPUT_BASE:
5016 case MSR_IA32_RTIT_OUTPUT_MASK:
5017 if (!kvm_x86_ops->pt_supported() ||
5018 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5019 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5022 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5023 if (!kvm_x86_ops->pt_supported() ||
5024 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5025 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5034 msrs_to_save[j] = msrs_to_save[i];
5037 num_msrs_to_save = j;
5039 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5040 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5044 emulated_msrs[j] = emulated_msrs[i];
5047 num_emulated_msrs = j;
5049 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5050 struct kvm_msr_entry msr;
5052 msr.index = msr_based_features[i];
5053 if (kvm_get_msr_feature(&msr))
5057 msr_based_features[j] = msr_based_features[i];
5060 num_msr_based_features = j;
5063 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5071 if (!(lapic_in_kernel(vcpu) &&
5072 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5073 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5084 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5091 if (!(lapic_in_kernel(vcpu) &&
5092 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5094 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5096 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5106 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5107 struct kvm_segment *var, int seg)
5109 kvm_x86_ops->set_segment(vcpu, var, seg);
5112 void kvm_get_segment(struct kvm_vcpu *vcpu,
5113 struct kvm_segment *var, int seg)
5115 kvm_x86_ops->get_segment(vcpu, var, seg);
5118 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5119 struct x86_exception *exception)
5123 BUG_ON(!mmu_is_nested(vcpu));
5125 /* NPT walks are always user-walks */
5126 access |= PFERR_USER_MASK;
5127 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5132 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5133 struct x86_exception *exception)
5135 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5136 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5139 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5140 struct x86_exception *exception)
5142 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5143 access |= PFERR_FETCH_MASK;
5144 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5147 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5148 struct x86_exception *exception)
5150 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5151 access |= PFERR_WRITE_MASK;
5152 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5155 /* uses this to access any guest's mapped memory without checking CPL */
5156 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5157 struct x86_exception *exception)
5159 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5162 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5163 struct kvm_vcpu *vcpu, u32 access,
5164 struct x86_exception *exception)
5167 int r = X86EMUL_CONTINUE;
5170 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5172 unsigned offset = addr & (PAGE_SIZE-1);
5173 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5176 if (gpa == UNMAPPED_GVA)
5177 return X86EMUL_PROPAGATE_FAULT;
5178 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5181 r = X86EMUL_IO_NEEDED;
5193 /* used for instruction fetching */
5194 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5195 gva_t addr, void *val, unsigned int bytes,
5196 struct x86_exception *exception)
5198 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5199 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5203 /* Inline kvm_read_guest_virt_helper for speed. */
5204 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5206 if (unlikely(gpa == UNMAPPED_GVA))
5207 return X86EMUL_PROPAGATE_FAULT;
5209 offset = addr & (PAGE_SIZE-1);
5210 if (WARN_ON(offset + bytes > PAGE_SIZE))
5211 bytes = (unsigned)PAGE_SIZE - offset;
5212 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5214 if (unlikely(ret < 0))
5215 return X86EMUL_IO_NEEDED;
5217 return X86EMUL_CONTINUE;
5220 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5221 gva_t addr, void *val, unsigned int bytes,
5222 struct x86_exception *exception)
5224 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5227 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5228 * is returned, but our callers are not ready for that and they blindly
5229 * call kvm_inject_page_fault. Ensure that they at least do not leak
5230 * uninitialized kernel stack memory into cr2 and error code.
5232 memset(exception, 0, sizeof(*exception));
5233 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5236 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5238 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5239 gva_t addr, void *val, unsigned int bytes,
5240 struct x86_exception *exception, bool system)
5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5245 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5246 access |= PFERR_USER_MASK;
5248 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5251 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5252 unsigned long addr, void *val, unsigned int bytes)
5254 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5255 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5257 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5260 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5261 struct kvm_vcpu *vcpu, u32 access,
5262 struct x86_exception *exception)
5265 int r = X86EMUL_CONTINUE;
5268 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5271 unsigned offset = addr & (PAGE_SIZE-1);
5272 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5275 if (gpa == UNMAPPED_GVA)
5276 return X86EMUL_PROPAGATE_FAULT;
5277 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5279 r = X86EMUL_IO_NEEDED;
5291 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5292 unsigned int bytes, struct x86_exception *exception,
5295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5296 u32 access = PFERR_WRITE_MASK;
5298 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5299 access |= PFERR_USER_MASK;
5301 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5305 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5306 unsigned int bytes, struct x86_exception *exception)
5308 /* kvm_write_guest_virt_system can pull in tons of pages. */
5309 vcpu->arch.l1tf_flush_l1d = true;
5311 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5312 PFERR_WRITE_MASK, exception);
5314 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5316 int handle_ud(struct kvm_vcpu *vcpu)
5318 int emul_type = EMULTYPE_TRAP_UD;
5319 enum emulation_result er;
5320 char sig[5]; /* ud2; .ascii "kvm" */
5321 struct x86_exception e;
5323 if (force_emulation_prefix &&
5324 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5325 sig, sizeof(sig), &e) == 0 &&
5326 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5327 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5331 er = kvm_emulate_instruction(vcpu, emul_type);
5332 if (er == EMULATE_USER_EXIT)
5334 if (er != EMULATE_DONE)
5335 kvm_queue_exception(vcpu, UD_VECTOR);
5338 EXPORT_SYMBOL_GPL(handle_ud);
5340 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5341 gpa_t gpa, bool write)
5343 /* For APIC access vmexit */
5344 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5347 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5348 trace_vcpu_match_mmio(gva, gpa, write, true);
5355 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5356 gpa_t *gpa, struct x86_exception *exception,
5359 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5360 | (write ? PFERR_WRITE_MASK : 0);
5363 * currently PKRU is only applied to ept enabled guest so
5364 * there is no pkey in EPT page table for L1 guest or EPT
5365 * shadow page table for L2 guest.
5367 if (vcpu_match_mmio_gva(vcpu, gva)
5368 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5369 vcpu->arch.access, 0, access)) {
5370 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5371 (gva & (PAGE_SIZE - 1));
5372 trace_vcpu_match_mmio(gva, *gpa, write, false);
5376 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5378 if (*gpa == UNMAPPED_GVA)
5381 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5384 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5385 const void *val, int bytes)
5389 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5392 kvm_page_track_write(vcpu, gpa, val, bytes);
5396 struct read_write_emulator_ops {
5397 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5399 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5400 void *val, int bytes);
5401 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5402 int bytes, void *val);
5403 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5404 void *val, int bytes);
5408 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5410 if (vcpu->mmio_read_completed) {
5411 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5412 vcpu->mmio_fragments[0].gpa, val);
5413 vcpu->mmio_read_completed = 0;
5420 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5421 void *val, int bytes)
5423 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5426 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5427 void *val, int bytes)
5429 return emulator_write_phys(vcpu, gpa, val, bytes);
5432 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5434 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5435 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5438 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5439 void *val, int bytes)
5441 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5442 return X86EMUL_IO_NEEDED;
5445 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5446 void *val, int bytes)
5448 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5450 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5451 return X86EMUL_CONTINUE;
5454 static const struct read_write_emulator_ops read_emultor = {
5455 .read_write_prepare = read_prepare,
5456 .read_write_emulate = read_emulate,
5457 .read_write_mmio = vcpu_mmio_read,
5458 .read_write_exit_mmio = read_exit_mmio,
5461 static const struct read_write_emulator_ops write_emultor = {
5462 .read_write_emulate = write_emulate,
5463 .read_write_mmio = write_mmio,
5464 .read_write_exit_mmio = write_exit_mmio,
5468 static int emulator_read_write_onepage(unsigned long addr, void *val,
5470 struct x86_exception *exception,
5471 struct kvm_vcpu *vcpu,
5472 const struct read_write_emulator_ops *ops)
5476 bool write = ops->write;
5477 struct kvm_mmio_fragment *frag;
5478 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5481 * If the exit was due to a NPF we may already have a GPA.
5482 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5483 * Note, this cannot be used on string operations since string
5484 * operation using rep will only have the initial GPA from the NPF
5487 if (vcpu->arch.gpa_available &&
5488 emulator_can_use_gpa(ctxt) &&
5489 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5490 gpa = vcpu->arch.gpa_val;
5491 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5493 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5495 return X86EMUL_PROPAGATE_FAULT;
5498 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5499 return X86EMUL_CONTINUE;
5502 * Is this MMIO handled locally?
5504 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5505 if (handled == bytes)
5506 return X86EMUL_CONTINUE;
5512 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5513 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5517 return X86EMUL_CONTINUE;
5520 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5522 void *val, unsigned int bytes,
5523 struct x86_exception *exception,
5524 const struct read_write_emulator_ops *ops)
5526 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5530 if (ops->read_write_prepare &&
5531 ops->read_write_prepare(vcpu, val, bytes))
5532 return X86EMUL_CONTINUE;
5534 vcpu->mmio_nr_fragments = 0;
5536 /* Crossing a page boundary? */
5537 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5540 now = -addr & ~PAGE_MASK;
5541 rc = emulator_read_write_onepage(addr, val, now, exception,
5544 if (rc != X86EMUL_CONTINUE)
5547 if (ctxt->mode != X86EMUL_MODE_PROT64)
5553 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5555 if (rc != X86EMUL_CONTINUE)
5558 if (!vcpu->mmio_nr_fragments)
5561 gpa = vcpu->mmio_fragments[0].gpa;
5563 vcpu->mmio_needed = 1;
5564 vcpu->mmio_cur_fragment = 0;
5566 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5567 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5568 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5569 vcpu->run->mmio.phys_addr = gpa;
5571 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5574 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5578 struct x86_exception *exception)
5580 return emulator_read_write(ctxt, addr, val, bytes,
5581 exception, &read_emultor);
5584 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5588 struct x86_exception *exception)
5590 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5591 exception, &write_emultor);
5594 #define CMPXCHG_TYPE(t, ptr, old, new) \
5595 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5597 #ifdef CONFIG_X86_64
5598 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5600 # define CMPXCHG64(ptr, old, new) \
5601 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5604 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5609 struct x86_exception *exception)
5611 struct kvm_host_map map;
5612 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5617 /* guests cmpxchg8b have to be emulated atomically */
5618 if (bytes > 8 || (bytes & (bytes - 1)))
5621 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5623 if (gpa == UNMAPPED_GVA ||
5624 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5627 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5630 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5633 kaddr = map.hva + offset_in_page(gpa);
5637 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5640 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5643 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5646 exchanged = CMPXCHG64(kaddr, old, new);
5652 kvm_vcpu_unmap(vcpu, &map, true);
5655 return X86EMUL_CMPXCHG_FAILED;
5657 kvm_page_track_write(vcpu, gpa, new, bytes);
5659 return X86EMUL_CONTINUE;
5662 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5664 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5667 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5671 for (i = 0; i < vcpu->arch.pio.count; i++) {
5672 if (vcpu->arch.pio.in)
5673 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5674 vcpu->arch.pio.size, pd);
5676 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5677 vcpu->arch.pio.port, vcpu->arch.pio.size,
5681 pd += vcpu->arch.pio.size;
5686 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5687 unsigned short port, void *val,
5688 unsigned int count, bool in)
5690 vcpu->arch.pio.port = port;
5691 vcpu->arch.pio.in = in;
5692 vcpu->arch.pio.count = count;
5693 vcpu->arch.pio.size = size;
5695 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5696 vcpu->arch.pio.count = 0;
5700 vcpu->run->exit_reason = KVM_EXIT_IO;
5701 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5702 vcpu->run->io.size = size;
5703 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5704 vcpu->run->io.count = count;
5705 vcpu->run->io.port = port;
5710 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5711 int size, unsigned short port, void *val,
5714 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5717 if (vcpu->arch.pio.count)
5720 memset(vcpu->arch.pio_data, 0, size * count);
5722 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5725 memcpy(val, vcpu->arch.pio_data, size * count);
5726 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5727 vcpu->arch.pio.count = 0;
5734 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5735 int size, unsigned short port,
5736 const void *val, unsigned int count)
5738 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5740 memcpy(vcpu->arch.pio_data, val, size * count);
5741 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5742 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5745 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5747 return kvm_x86_ops->get_segment_base(vcpu, seg);
5750 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5752 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5755 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5757 if (!need_emulate_wbinvd(vcpu))
5758 return X86EMUL_CONTINUE;
5760 if (kvm_x86_ops->has_wbinvd_exit()) {
5761 int cpu = get_cpu();
5763 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5764 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5765 wbinvd_ipi, NULL, 1);
5767 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5770 return X86EMUL_CONTINUE;
5773 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5775 kvm_emulate_wbinvd_noskip(vcpu);
5776 return kvm_skip_emulated_instruction(vcpu);
5778 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5782 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5784 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5787 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5788 unsigned long *dest)
5790 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5793 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5794 unsigned long value)
5797 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5800 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5802 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5805 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5807 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5808 unsigned long value;
5812 value = kvm_read_cr0(vcpu);
5815 value = vcpu->arch.cr2;
5818 value = kvm_read_cr3(vcpu);
5821 value = kvm_read_cr4(vcpu);
5824 value = kvm_get_cr8(vcpu);
5827 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5834 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5841 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5844 vcpu->arch.cr2 = val;
5847 res = kvm_set_cr3(vcpu, val);
5850 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5853 res = kvm_set_cr8(vcpu, val);
5856 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5863 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5865 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5868 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5870 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5873 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5875 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5878 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5880 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5883 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5885 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5888 static unsigned long emulator_get_cached_segment_base(
5889 struct x86_emulate_ctxt *ctxt, int seg)
5891 return get_segment_base(emul_to_vcpu(ctxt), seg);
5894 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5895 struct desc_struct *desc, u32 *base3,
5898 struct kvm_segment var;
5900 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5901 *selector = var.selector;
5904 memset(desc, 0, sizeof(*desc));
5912 set_desc_limit(desc, var.limit);
5913 set_desc_base(desc, (unsigned long)var.base);
5914 #ifdef CONFIG_X86_64
5916 *base3 = var.base >> 32;
5918 desc->type = var.type;
5920 desc->dpl = var.dpl;
5921 desc->p = var.present;
5922 desc->avl = var.avl;
5930 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5931 struct desc_struct *desc, u32 base3,
5934 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5935 struct kvm_segment var;
5937 var.selector = selector;
5938 var.base = get_desc_base(desc);
5939 #ifdef CONFIG_X86_64
5940 var.base |= ((u64)base3) << 32;
5942 var.limit = get_desc_limit(desc);
5944 var.limit = (var.limit << 12) | 0xfff;
5945 var.type = desc->type;
5946 var.dpl = desc->dpl;
5951 var.avl = desc->avl;
5952 var.present = desc->p;
5953 var.unusable = !var.present;
5956 kvm_set_segment(vcpu, &var, seg);
5960 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5961 u32 msr_index, u64 *pdata)
5963 struct msr_data msr;
5966 msr.index = msr_index;
5967 msr.host_initiated = false;
5968 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5976 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5977 u32 msr_index, u64 data)
5979 struct msr_data msr;
5982 msr.index = msr_index;
5983 msr.host_initiated = false;
5984 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5987 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5991 return vcpu->arch.smbase;
5994 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5998 vcpu->arch.smbase = smbase;
6001 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6004 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6007 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6008 u32 pmc, u64 *pdata)
6010 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6013 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6015 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6018 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6019 struct x86_instruction_info *info,
6020 enum x86_intercept_stage stage)
6022 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6025 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6026 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6028 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6031 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6033 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6036 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6038 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6041 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6043 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6046 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6048 return emul_to_vcpu(ctxt)->arch.hflags;
6051 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6053 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6056 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6057 const char *smstate)
6059 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6062 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6064 kvm_smm_changed(emul_to_vcpu(ctxt));
6067 static const struct x86_emulate_ops emulate_ops = {
6068 .read_gpr = emulator_read_gpr,
6069 .write_gpr = emulator_write_gpr,
6070 .read_std = emulator_read_std,
6071 .write_std = emulator_write_std,
6072 .read_phys = kvm_read_guest_phys_system,
6073 .fetch = kvm_fetch_guest_virt,
6074 .read_emulated = emulator_read_emulated,
6075 .write_emulated = emulator_write_emulated,
6076 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6077 .invlpg = emulator_invlpg,
6078 .pio_in_emulated = emulator_pio_in_emulated,
6079 .pio_out_emulated = emulator_pio_out_emulated,
6080 .get_segment = emulator_get_segment,
6081 .set_segment = emulator_set_segment,
6082 .get_cached_segment_base = emulator_get_cached_segment_base,
6083 .get_gdt = emulator_get_gdt,
6084 .get_idt = emulator_get_idt,
6085 .set_gdt = emulator_set_gdt,
6086 .set_idt = emulator_set_idt,
6087 .get_cr = emulator_get_cr,
6088 .set_cr = emulator_set_cr,
6089 .cpl = emulator_get_cpl,
6090 .get_dr = emulator_get_dr,
6091 .set_dr = emulator_set_dr,
6092 .get_smbase = emulator_get_smbase,
6093 .set_smbase = emulator_set_smbase,
6094 .set_msr = emulator_set_msr,
6095 .get_msr = emulator_get_msr,
6096 .check_pmc = emulator_check_pmc,
6097 .read_pmc = emulator_read_pmc,
6098 .halt = emulator_halt,
6099 .wbinvd = emulator_wbinvd,
6100 .fix_hypercall = emulator_fix_hypercall,
6101 .intercept = emulator_intercept,
6102 .get_cpuid = emulator_get_cpuid,
6103 .set_nmi_mask = emulator_set_nmi_mask,
6104 .get_hflags = emulator_get_hflags,
6105 .set_hflags = emulator_set_hflags,
6106 .pre_leave_smm = emulator_pre_leave_smm,
6107 .post_leave_smm = emulator_post_leave_smm,
6110 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6112 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6114 * an sti; sti; sequence only disable interrupts for the first
6115 * instruction. So, if the last instruction, be it emulated or
6116 * not, left the system with the INT_STI flag enabled, it
6117 * means that the last instruction is an sti. We should not
6118 * leave the flag on in this case. The same goes for mov ss
6120 if (int_shadow & mask)
6122 if (unlikely(int_shadow || mask)) {
6123 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6125 kvm_make_request(KVM_REQ_EVENT, vcpu);
6129 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6131 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6132 if (ctxt->exception.vector == PF_VECTOR)
6133 return kvm_propagate_fault(vcpu, &ctxt->exception);
6135 if (ctxt->exception.error_code_valid)
6136 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6137 ctxt->exception.error_code);
6139 kvm_queue_exception(vcpu, ctxt->exception.vector);
6143 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6145 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6148 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6150 ctxt->eflags = kvm_get_rflags(vcpu);
6151 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6153 ctxt->eip = kvm_rip_read(vcpu);
6154 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6155 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6156 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6157 cs_db ? X86EMUL_MODE_PROT32 :
6158 X86EMUL_MODE_PROT16;
6159 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6160 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6161 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6163 init_decode_cache(ctxt);
6164 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6167 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6169 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6172 init_emulate_ctxt(vcpu);
6176 ctxt->_eip = ctxt->eip + inc_eip;
6177 ret = emulate_int_real(ctxt, irq);
6179 if (ret != X86EMUL_CONTINUE)
6180 return EMULATE_FAIL;
6182 ctxt->eip = ctxt->_eip;
6183 kvm_rip_write(vcpu, ctxt->eip);
6184 kvm_set_rflags(vcpu, ctxt->eflags);
6186 return EMULATE_DONE;
6188 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6190 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6192 int r = EMULATE_DONE;
6194 ++vcpu->stat.insn_emulation_fail;
6195 trace_kvm_emulate_insn_failed(vcpu);
6197 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6198 return EMULATE_FAIL;
6200 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6201 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6202 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6203 vcpu->run->internal.ndata = 0;
6204 r = EMULATE_USER_EXIT;
6207 kvm_queue_exception(vcpu, UD_VECTOR);
6212 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6213 bool write_fault_to_shadow_pgtable,
6219 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6222 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6225 if (!vcpu->arch.mmu->direct_map) {
6227 * Write permission should be allowed since only
6228 * write access need to be emulated.
6230 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6233 * If the mapping is invalid in guest, let cpu retry
6234 * it to generate fault.
6236 if (gpa == UNMAPPED_GVA)
6241 * Do not retry the unhandleable instruction if it faults on the
6242 * readonly host memory, otherwise it will goto a infinite loop:
6243 * retry instruction -> write #PF -> emulation fail -> retry
6244 * instruction -> ...
6246 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6249 * If the instruction failed on the error pfn, it can not be fixed,
6250 * report the error to userspace.
6252 if (is_error_noslot_pfn(pfn))
6255 kvm_release_pfn_clean(pfn);
6257 /* The instructions are well-emulated on direct mmu. */
6258 if (vcpu->arch.mmu->direct_map) {
6259 unsigned int indirect_shadow_pages;
6261 spin_lock(&vcpu->kvm->mmu_lock);
6262 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6263 spin_unlock(&vcpu->kvm->mmu_lock);
6265 if (indirect_shadow_pages)
6266 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6272 * if emulation was due to access to shadowed page table
6273 * and it failed try to unshadow page and re-enter the
6274 * guest to let CPU execute the instruction.
6276 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6279 * If the access faults on its page table, it can not
6280 * be fixed by unprotecting shadow page and it should
6281 * be reported to userspace.
6283 return !write_fault_to_shadow_pgtable;
6286 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6287 unsigned long cr2, int emulation_type)
6289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6290 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6292 last_retry_eip = vcpu->arch.last_retry_eip;
6293 last_retry_addr = vcpu->arch.last_retry_addr;
6296 * If the emulation is caused by #PF and it is non-page_table
6297 * writing instruction, it means the VM-EXIT is caused by shadow
6298 * page protected, we can zap the shadow page and retry this
6299 * instruction directly.
6301 * Note: if the guest uses a non-page-table modifying instruction
6302 * on the PDE that points to the instruction, then we will unmap
6303 * the instruction and go to an infinite loop. So, we cache the
6304 * last retried eip and the last fault address, if we meet the eip
6305 * and the address again, we can break out of the potential infinite
6308 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6310 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6313 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6316 if (x86_page_table_writing_insn(ctxt))
6319 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6322 vcpu->arch.last_retry_eip = ctxt->eip;
6323 vcpu->arch.last_retry_addr = cr2;
6325 if (!vcpu->arch.mmu->direct_map)
6326 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6328 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6333 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6334 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6336 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6338 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6339 /* This is a good place to trace that we are exiting SMM. */
6340 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6342 /* Process a latched INIT or SMI, if any. */
6343 kvm_make_request(KVM_REQ_EVENT, vcpu);
6346 kvm_mmu_reset_context(vcpu);
6349 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6358 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6359 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6364 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6366 struct kvm_run *kvm_run = vcpu->run;
6368 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6369 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6370 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6371 kvm_run->debug.arch.exception = DB_VECTOR;
6372 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6373 *r = EMULATE_USER_EXIT;
6375 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6379 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6381 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6382 int r = EMULATE_DONE;
6384 kvm_x86_ops->skip_emulated_instruction(vcpu);
6387 * rflags is the old, "raw" value of the flags. The new value has
6388 * not been saved yet.
6390 * This is correct even for TF set by the guest, because "the
6391 * processor will not generate this exception after the instruction
6392 * that sets the TF flag".
6394 if (unlikely(rflags & X86_EFLAGS_TF))
6395 kvm_vcpu_do_singlestep(vcpu, &r);
6396 return r == EMULATE_DONE;
6398 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6400 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6402 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6403 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6404 struct kvm_run *kvm_run = vcpu->run;
6405 unsigned long eip = kvm_get_linear_rip(vcpu);
6406 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6407 vcpu->arch.guest_debug_dr7,
6411 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6412 kvm_run->debug.arch.pc = eip;
6413 kvm_run->debug.arch.exception = DB_VECTOR;
6414 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6415 *r = EMULATE_USER_EXIT;
6420 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6421 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6422 unsigned long eip = kvm_get_linear_rip(vcpu);
6423 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6428 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6429 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6430 kvm_queue_exception(vcpu, DB_VECTOR);
6439 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6441 switch (ctxt->opcode_len) {
6448 case 0xe6: /* OUT */
6452 case 0x6c: /* INS */
6454 case 0x6e: /* OUTS */
6461 case 0x33: /* RDPMC */
6470 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6477 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6478 bool writeback = true;
6479 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6481 vcpu->arch.l1tf_flush_l1d = true;
6484 * Clear write_fault_to_shadow_pgtable here to ensure it is
6487 vcpu->arch.write_fault_to_shadow_pgtable = false;
6488 kvm_clear_exception_queue(vcpu);
6490 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6491 init_emulate_ctxt(vcpu);
6494 * We will reenter on the same instruction since
6495 * we do not set complete_userspace_io. This does not
6496 * handle watchpoints yet, those would be handled in
6499 if (!(emulation_type & EMULTYPE_SKIP) &&
6500 kvm_vcpu_check_breakpoint(vcpu, &r))
6503 ctxt->interruptibility = 0;
6504 ctxt->have_exception = false;
6505 ctxt->exception.vector = -1;
6506 ctxt->perm_ok = false;
6508 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6510 r = x86_decode_insn(ctxt, insn, insn_len);
6512 trace_kvm_emulate_insn_start(vcpu);
6513 ++vcpu->stat.insn_emulation;
6514 if (r != EMULATION_OK) {
6515 if (emulation_type & EMULTYPE_TRAP_UD)
6516 return EMULATE_FAIL;
6517 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6519 return EMULATE_DONE;
6520 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6521 return EMULATE_DONE;
6522 if (emulation_type & EMULTYPE_SKIP)
6523 return EMULATE_FAIL;
6524 return handle_emulation_failure(vcpu, emulation_type);
6528 if ((emulation_type & EMULTYPE_VMWARE) &&
6529 !is_vmware_backdoor_opcode(ctxt))
6530 return EMULATE_FAIL;
6532 if (emulation_type & EMULTYPE_SKIP) {
6533 kvm_rip_write(vcpu, ctxt->_eip);
6534 if (ctxt->eflags & X86_EFLAGS_RF)
6535 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6536 return EMULATE_DONE;
6539 if (retry_instruction(ctxt, cr2, emulation_type))
6540 return EMULATE_DONE;
6542 /* this is needed for vmware backdoor interface to work since it
6543 changes registers values during IO operation */
6544 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6545 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6546 emulator_invalidate_register_cache(ctxt);
6550 /* Save the faulting GPA (cr2) in the address field */
6551 ctxt->exception.address = cr2;
6553 r = x86_emulate_insn(ctxt);
6555 if (r == EMULATION_INTERCEPTED)
6556 return EMULATE_DONE;
6558 if (r == EMULATION_FAILED) {
6559 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6561 return EMULATE_DONE;
6563 return handle_emulation_failure(vcpu, emulation_type);
6566 if (ctxt->have_exception) {
6568 if (inject_emulated_exception(vcpu))
6570 } else if (vcpu->arch.pio.count) {
6571 if (!vcpu->arch.pio.in) {
6572 /* FIXME: return into emulator if single-stepping. */
6573 vcpu->arch.pio.count = 0;
6576 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6578 r = EMULATE_USER_EXIT;
6579 } else if (vcpu->mmio_needed) {
6580 if (!vcpu->mmio_is_write)
6582 r = EMULATE_USER_EXIT;
6583 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6584 } else if (r == EMULATION_RESTART)
6590 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6591 toggle_interruptibility(vcpu, ctxt->interruptibility);
6592 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6593 kvm_rip_write(vcpu, ctxt->eip);
6594 if (r == EMULATE_DONE && ctxt->tf)
6595 kvm_vcpu_do_singlestep(vcpu, &r);
6596 if (!ctxt->have_exception ||
6597 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6598 __kvm_set_rflags(vcpu, ctxt->eflags);
6601 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6602 * do nothing, and it will be requested again as soon as
6603 * the shadow expires. But we still need to check here,
6604 * because POPF has no interrupt shadow.
6606 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6607 kvm_make_request(KVM_REQ_EVENT, vcpu);
6609 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6614 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6616 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6618 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6620 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6621 void *insn, int insn_len)
6623 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6625 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6627 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6629 vcpu->arch.pio.count = 0;
6633 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6635 vcpu->arch.pio.count = 0;
6637 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6640 return kvm_skip_emulated_instruction(vcpu);
6643 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6644 unsigned short port)
6646 unsigned long val = kvm_rax_read(vcpu);
6647 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6648 size, port, &val, 1);
6653 * Workaround userspace that relies on old KVM behavior of %rip being
6654 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6657 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6658 vcpu->arch.complete_userspace_io =
6659 complete_fast_pio_out_port_0x7e;
6660 kvm_skip_emulated_instruction(vcpu);
6662 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6663 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6668 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6672 /* We should only ever be called with arch.pio.count equal to 1 */
6673 BUG_ON(vcpu->arch.pio.count != 1);
6675 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6676 vcpu->arch.pio.count = 0;
6680 /* For size less than 4 we merge, else we zero extend */
6681 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6684 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6685 * the copy and tracing
6687 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6688 vcpu->arch.pio.port, &val, 1);
6689 kvm_rax_write(vcpu, val);
6691 return kvm_skip_emulated_instruction(vcpu);
6694 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6695 unsigned short port)
6700 /* For size less than 4 we merge, else we zero extend */
6701 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6703 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6706 kvm_rax_write(vcpu, val);
6710 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6711 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6716 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6721 ret = kvm_fast_pio_in(vcpu, size, port);
6723 ret = kvm_fast_pio_out(vcpu, size, port);
6724 return ret && kvm_skip_emulated_instruction(vcpu);
6726 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6728 static int kvmclock_cpu_down_prep(unsigned int cpu)
6730 __this_cpu_write(cpu_tsc_khz, 0);
6734 static void tsc_khz_changed(void *data)
6736 struct cpufreq_freqs *freq = data;
6737 unsigned long khz = 0;
6741 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6742 khz = cpufreq_quick_get(raw_smp_processor_id());
6745 __this_cpu_write(cpu_tsc_khz, khz);
6748 #ifdef CONFIG_X86_64
6749 static void kvm_hyperv_tsc_notifier(void)
6752 struct kvm_vcpu *vcpu;
6755 mutex_lock(&kvm_lock);
6756 list_for_each_entry(kvm, &vm_list, vm_list)
6757 kvm_make_mclock_inprogress_request(kvm);
6759 hyperv_stop_tsc_emulation();
6761 /* TSC frequency always matches when on Hyper-V */
6762 for_each_present_cpu(cpu)
6763 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6764 kvm_max_guest_tsc_khz = tsc_khz;
6766 list_for_each_entry(kvm, &vm_list, vm_list) {
6767 struct kvm_arch *ka = &kvm->arch;
6769 spin_lock(&ka->pvclock_gtod_sync_lock);
6771 pvclock_update_vm_gtod_copy(kvm);
6773 kvm_for_each_vcpu(cpu, vcpu, kvm)
6774 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6776 kvm_for_each_vcpu(cpu, vcpu, kvm)
6777 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6779 spin_unlock(&ka->pvclock_gtod_sync_lock);
6781 mutex_unlock(&kvm_lock);
6785 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6788 struct kvm_vcpu *vcpu;
6789 int i, send_ipi = 0;
6792 * We allow guests to temporarily run on slowing clocks,
6793 * provided we notify them after, or to run on accelerating
6794 * clocks, provided we notify them before. Thus time never
6797 * However, we have a problem. We can't atomically update
6798 * the frequency of a given CPU from this function; it is
6799 * merely a notifier, which can be called from any CPU.
6800 * Changing the TSC frequency at arbitrary points in time
6801 * requires a recomputation of local variables related to
6802 * the TSC for each VCPU. We must flag these local variables
6803 * to be updated and be sure the update takes place with the
6804 * new frequency before any guests proceed.
6806 * Unfortunately, the combination of hotplug CPU and frequency
6807 * change creates an intractable locking scenario; the order
6808 * of when these callouts happen is undefined with respect to
6809 * CPU hotplug, and they can race with each other. As such,
6810 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6811 * undefined; you can actually have a CPU frequency change take
6812 * place in between the computation of X and the setting of the
6813 * variable. To protect against this problem, all updates of
6814 * the per_cpu tsc_khz variable are done in an interrupt
6815 * protected IPI, and all callers wishing to update the value
6816 * must wait for a synchronous IPI to complete (which is trivial
6817 * if the caller is on the CPU already). This establishes the
6818 * necessary total order on variable updates.
6820 * Note that because a guest time update may take place
6821 * anytime after the setting of the VCPU's request bit, the
6822 * correct TSC value must be set before the request. However,
6823 * to ensure the update actually makes it to any guest which
6824 * starts running in hardware virtualization between the set
6825 * and the acquisition of the spinlock, we must also ping the
6826 * CPU after setting the request bit.
6830 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6832 mutex_lock(&kvm_lock);
6833 list_for_each_entry(kvm, &vm_list, vm_list) {
6834 kvm_for_each_vcpu(i, vcpu, kvm) {
6835 if (vcpu->cpu != cpu)
6837 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6838 if (vcpu->cpu != raw_smp_processor_id())
6842 mutex_unlock(&kvm_lock);
6844 if (freq->old < freq->new && send_ipi) {
6846 * We upscale the frequency. Must make the guest
6847 * doesn't see old kvmclock values while running with
6848 * the new frequency, otherwise we risk the guest sees
6849 * time go backwards.
6851 * In case we update the frequency for another cpu
6852 * (which might be in guest context) send an interrupt
6853 * to kick the cpu out of guest context. Next time
6854 * guest context is entered kvmclock will be updated,
6855 * so the guest will not see stale values.
6857 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6861 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6864 struct cpufreq_freqs *freq = data;
6867 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6869 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6872 for_each_cpu(cpu, freq->policy->cpus)
6873 __kvmclock_cpufreq_notifier(freq, cpu);
6878 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6879 .notifier_call = kvmclock_cpufreq_notifier
6882 static int kvmclock_cpu_online(unsigned int cpu)
6884 tsc_khz_changed(NULL);
6888 static void kvm_timer_init(void)
6890 max_tsc_khz = tsc_khz;
6892 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6893 #ifdef CONFIG_CPU_FREQ
6894 struct cpufreq_policy policy;
6897 memset(&policy, 0, sizeof(policy));
6899 cpufreq_get_policy(&policy, cpu);
6900 if (policy.cpuinfo.max_freq)
6901 max_tsc_khz = policy.cpuinfo.max_freq;
6904 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6905 CPUFREQ_TRANSITION_NOTIFIER);
6908 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6909 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6912 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6913 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6915 int kvm_is_in_guest(void)
6917 return __this_cpu_read(current_vcpu) != NULL;
6920 static int kvm_is_user_mode(void)
6924 if (__this_cpu_read(current_vcpu))
6925 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6927 return user_mode != 0;
6930 static unsigned long kvm_get_guest_ip(void)
6932 unsigned long ip = 0;
6934 if (__this_cpu_read(current_vcpu))
6935 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6940 static void kvm_handle_intel_pt_intr(void)
6942 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6944 kvm_make_request(KVM_REQ_PMI, vcpu);
6945 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6946 (unsigned long *)&vcpu->arch.pmu.global_status);
6949 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6950 .is_in_guest = kvm_is_in_guest,
6951 .is_user_mode = kvm_is_user_mode,
6952 .get_guest_ip = kvm_get_guest_ip,
6953 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
6956 #ifdef CONFIG_X86_64
6957 static void pvclock_gtod_update_fn(struct work_struct *work)
6961 struct kvm_vcpu *vcpu;
6964 mutex_lock(&kvm_lock);
6965 list_for_each_entry(kvm, &vm_list, vm_list)
6966 kvm_for_each_vcpu(i, vcpu, kvm)
6967 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6968 atomic_set(&kvm_guest_has_master_clock, 0);
6969 mutex_unlock(&kvm_lock);
6972 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6975 * Notification about pvclock gtod data update.
6977 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6980 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6981 struct timekeeper *tk = priv;
6983 update_pvclock_gtod(tk);
6985 /* disable master clock if host does not trust, or does not
6986 * use, TSC based clocksource.
6988 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6989 atomic_read(&kvm_guest_has_master_clock) != 0)
6990 queue_work(system_long_wq, &pvclock_gtod_work);
6995 static struct notifier_block pvclock_gtod_notifier = {
6996 .notifier_call = pvclock_gtod_notify,
7000 int kvm_arch_init(void *opaque)
7003 struct kvm_x86_ops *ops = opaque;
7006 printk(KERN_ERR "kvm: already loaded the other module\n");
7011 if (!ops->cpu_has_kvm_support()) {
7012 printk(KERN_ERR "kvm: no hardware support\n");
7016 if (ops->disabled_by_bios()) {
7017 printk(KERN_ERR "kvm: disabled by bios\n");
7023 * KVM explicitly assumes that the guest has an FPU and
7024 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7025 * vCPU's FPU state as a fxregs_state struct.
7027 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7028 printk(KERN_ERR "kvm: inadequate fpu\n");
7034 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7035 __alignof__(struct fpu), SLAB_ACCOUNT,
7037 if (!x86_fpu_cache) {
7038 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7042 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7044 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7045 goto out_free_x86_fpu_cache;
7048 r = kvm_mmu_module_init();
7050 goto out_free_percpu;
7054 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7055 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7056 PT_PRESENT_MASK, 0, sme_me_mask);
7059 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7061 if (boot_cpu_has(X86_FEATURE_XSAVE))
7062 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7065 if (pi_inject_timer == -1)
7066 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7067 #ifdef CONFIG_X86_64
7068 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7070 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7071 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7077 free_percpu(shared_msrs);
7078 out_free_x86_fpu_cache:
7079 kmem_cache_destroy(x86_fpu_cache);
7084 void kvm_arch_exit(void)
7086 #ifdef CONFIG_X86_64
7087 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7088 clear_hv_tscchange_cb();
7091 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7093 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7094 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7095 CPUFREQ_TRANSITION_NOTIFIER);
7096 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7097 #ifdef CONFIG_X86_64
7098 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7101 kvm_mmu_module_exit();
7102 free_percpu(shared_msrs);
7103 kmem_cache_destroy(x86_fpu_cache);
7106 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7108 ++vcpu->stat.halt_exits;
7109 if (lapic_in_kernel(vcpu)) {
7110 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7113 vcpu->run->exit_reason = KVM_EXIT_HLT;
7117 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7119 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7121 int ret = kvm_skip_emulated_instruction(vcpu);
7123 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7124 * KVM_EXIT_DEBUG here.
7126 return kvm_vcpu_halt(vcpu) && ret;
7128 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7130 #ifdef CONFIG_X86_64
7131 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7132 unsigned long clock_type)
7134 struct kvm_clock_pairing clock_pairing;
7135 struct timespec64 ts;
7139 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7140 return -KVM_EOPNOTSUPP;
7142 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7143 return -KVM_EOPNOTSUPP;
7145 clock_pairing.sec = ts.tv_sec;
7146 clock_pairing.nsec = ts.tv_nsec;
7147 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7148 clock_pairing.flags = 0;
7149 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7152 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7153 sizeof(struct kvm_clock_pairing)))
7161 * kvm_pv_kick_cpu_op: Kick a vcpu.
7163 * @apicid - apicid of vcpu to be kicked.
7165 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7167 struct kvm_lapic_irq lapic_irq;
7169 lapic_irq.shorthand = 0;
7170 lapic_irq.dest_mode = 0;
7171 lapic_irq.level = 0;
7172 lapic_irq.dest_id = apicid;
7173 lapic_irq.msi_redir_hint = false;
7175 lapic_irq.delivery_mode = APIC_DM_REMRD;
7176 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7179 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7181 if (!lapic_in_kernel(vcpu)) {
7182 WARN_ON_ONCE(vcpu->arch.apicv_active);
7185 if (!vcpu->arch.apicv_active)
7188 vcpu->arch.apicv_active = false;
7189 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7192 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7194 struct kvm_vcpu *target = NULL;
7195 struct kvm_apic_map *map;
7198 map = rcu_dereference(kvm->arch.apic_map);
7200 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7201 target = map->phys_map[dest_id]->vcpu;
7206 kvm_vcpu_yield_to(target);
7209 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7211 unsigned long nr, a0, a1, a2, a3, ret;
7214 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7215 return kvm_hv_hypercall(vcpu);
7217 nr = kvm_rax_read(vcpu);
7218 a0 = kvm_rbx_read(vcpu);
7219 a1 = kvm_rcx_read(vcpu);
7220 a2 = kvm_rdx_read(vcpu);
7221 a3 = kvm_rsi_read(vcpu);
7223 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7225 op_64_bit = is_64_bit_mode(vcpu);
7234 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7240 case KVM_HC_VAPIC_POLL_IRQ:
7243 case KVM_HC_KICK_CPU:
7244 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7247 #ifdef CONFIG_X86_64
7248 case KVM_HC_CLOCK_PAIRING:
7249 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7252 case KVM_HC_SEND_IPI:
7253 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7255 case KVM_HC_SCHED_YIELD:
7256 kvm_sched_yield(vcpu->kvm, a0);
7266 kvm_rax_write(vcpu, ret);
7268 ++vcpu->stat.hypercalls;
7269 return kvm_skip_emulated_instruction(vcpu);
7271 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7273 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7276 char instruction[3];
7277 unsigned long rip = kvm_rip_read(vcpu);
7279 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7281 return emulator_write_emulated(ctxt, rip, instruction, 3,
7285 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7287 return vcpu->run->request_interrupt_window &&
7288 likely(!pic_in_kernel(vcpu->kvm));
7291 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7293 struct kvm_run *kvm_run = vcpu->run;
7295 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7296 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7297 kvm_run->cr8 = kvm_get_cr8(vcpu);
7298 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7299 kvm_run->ready_for_interrupt_injection =
7300 pic_in_kernel(vcpu->kvm) ||
7301 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7304 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7308 if (!kvm_x86_ops->update_cr8_intercept)
7311 if (!lapic_in_kernel(vcpu))
7314 if (vcpu->arch.apicv_active)
7317 if (!vcpu->arch.apic->vapic_addr)
7318 max_irr = kvm_lapic_find_highest_irr(vcpu);
7325 tpr = kvm_lapic_get_cr8(vcpu);
7327 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7330 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7334 /* try to reinject previous events if any */
7336 if (vcpu->arch.exception.injected)
7337 kvm_x86_ops->queue_exception(vcpu);
7339 * Do not inject an NMI or interrupt if there is a pending
7340 * exception. Exceptions and interrupts are recognized at
7341 * instruction boundaries, i.e. the start of an instruction.
7342 * Trap-like exceptions, e.g. #DB, have higher priority than
7343 * NMIs and interrupts, i.e. traps are recognized before an
7344 * NMI/interrupt that's pending on the same instruction.
7345 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7346 * priority, but are only generated (pended) during instruction
7347 * execution, i.e. a pending fault-like exception means the
7348 * fault occurred on the *previous* instruction and must be
7349 * serviced prior to recognizing any new events in order to
7350 * fully complete the previous instruction.
7352 else if (!vcpu->arch.exception.pending) {
7353 if (vcpu->arch.nmi_injected)
7354 kvm_x86_ops->set_nmi(vcpu);
7355 else if (vcpu->arch.interrupt.injected)
7356 kvm_x86_ops->set_irq(vcpu);
7360 * Call check_nested_events() even if we reinjected a previous event
7361 * in order for caller to determine if it should require immediate-exit
7362 * from L2 to L1 due to pending L1 events which require exit
7365 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7366 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7371 /* try to inject new event if pending */
7372 if (vcpu->arch.exception.pending) {
7373 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7374 vcpu->arch.exception.has_error_code,
7375 vcpu->arch.exception.error_code);
7377 WARN_ON_ONCE(vcpu->arch.exception.injected);
7378 vcpu->arch.exception.pending = false;
7379 vcpu->arch.exception.injected = true;
7381 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7382 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7385 if (vcpu->arch.exception.nr == DB_VECTOR) {
7387 * This code assumes that nSVM doesn't use
7388 * check_nested_events(). If it does, the
7389 * DR6/DR7 changes should happen before L1
7390 * gets a #VMEXIT for an intercepted #DB in
7391 * L2. (Under VMX, on the other hand, the
7392 * DR6/DR7 changes should not happen in the
7393 * event of a VM-exit to L1 for an intercepted
7396 kvm_deliver_exception_payload(vcpu);
7397 if (vcpu->arch.dr7 & DR7_GD) {
7398 vcpu->arch.dr7 &= ~DR7_GD;
7399 kvm_update_dr7(vcpu);
7403 kvm_x86_ops->queue_exception(vcpu);
7406 /* Don't consider new event if we re-injected an event */
7407 if (kvm_event_needs_reinjection(vcpu))
7410 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7411 kvm_x86_ops->smi_allowed(vcpu)) {
7412 vcpu->arch.smi_pending = false;
7413 ++vcpu->arch.smi_count;
7415 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7416 --vcpu->arch.nmi_pending;
7417 vcpu->arch.nmi_injected = true;
7418 kvm_x86_ops->set_nmi(vcpu);
7419 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7421 * Because interrupts can be injected asynchronously, we are
7422 * calling check_nested_events again here to avoid a race condition.
7423 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7424 * proposal and current concerns. Perhaps we should be setting
7425 * KVM_REQ_EVENT only on certain events and not unconditionally?
7427 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7428 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7432 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7433 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7435 kvm_x86_ops->set_irq(vcpu);
7442 static void process_nmi(struct kvm_vcpu *vcpu)
7447 * x86 is limited to one NMI running, and one NMI pending after it.
7448 * If an NMI is already in progress, limit further NMIs to just one.
7449 * Otherwise, allow two (and we'll inject the first one immediately).
7451 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7454 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7455 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7456 kvm_make_request(KVM_REQ_EVENT, vcpu);
7459 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7462 flags |= seg->g << 23;
7463 flags |= seg->db << 22;
7464 flags |= seg->l << 21;
7465 flags |= seg->avl << 20;
7466 flags |= seg->present << 15;
7467 flags |= seg->dpl << 13;
7468 flags |= seg->s << 12;
7469 flags |= seg->type << 8;
7473 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7475 struct kvm_segment seg;
7478 kvm_get_segment(vcpu, &seg, n);
7479 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7482 offset = 0x7f84 + n * 12;
7484 offset = 0x7f2c + (n - 3) * 12;
7486 put_smstate(u32, buf, offset + 8, seg.base);
7487 put_smstate(u32, buf, offset + 4, seg.limit);
7488 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7491 #ifdef CONFIG_X86_64
7492 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7494 struct kvm_segment seg;
7498 kvm_get_segment(vcpu, &seg, n);
7499 offset = 0x7e00 + n * 16;
7501 flags = enter_smm_get_segment_flags(&seg) >> 8;
7502 put_smstate(u16, buf, offset, seg.selector);
7503 put_smstate(u16, buf, offset + 2, flags);
7504 put_smstate(u32, buf, offset + 4, seg.limit);
7505 put_smstate(u64, buf, offset + 8, seg.base);
7509 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7512 struct kvm_segment seg;
7516 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7517 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7518 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7519 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7521 for (i = 0; i < 8; i++)
7522 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7524 kvm_get_dr(vcpu, 6, &val);
7525 put_smstate(u32, buf, 0x7fcc, (u32)val);
7526 kvm_get_dr(vcpu, 7, &val);
7527 put_smstate(u32, buf, 0x7fc8, (u32)val);
7529 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7530 put_smstate(u32, buf, 0x7fc4, seg.selector);
7531 put_smstate(u32, buf, 0x7f64, seg.base);
7532 put_smstate(u32, buf, 0x7f60, seg.limit);
7533 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7535 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7536 put_smstate(u32, buf, 0x7fc0, seg.selector);
7537 put_smstate(u32, buf, 0x7f80, seg.base);
7538 put_smstate(u32, buf, 0x7f7c, seg.limit);
7539 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7541 kvm_x86_ops->get_gdt(vcpu, &dt);
7542 put_smstate(u32, buf, 0x7f74, dt.address);
7543 put_smstate(u32, buf, 0x7f70, dt.size);
7545 kvm_x86_ops->get_idt(vcpu, &dt);
7546 put_smstate(u32, buf, 0x7f58, dt.address);
7547 put_smstate(u32, buf, 0x7f54, dt.size);
7549 for (i = 0; i < 6; i++)
7550 enter_smm_save_seg_32(vcpu, buf, i);
7552 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7555 put_smstate(u32, buf, 0x7efc, 0x00020000);
7556 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7559 #ifdef CONFIG_X86_64
7560 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7563 struct kvm_segment seg;
7567 for (i = 0; i < 16; i++)
7568 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7570 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7571 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7573 kvm_get_dr(vcpu, 6, &val);
7574 put_smstate(u64, buf, 0x7f68, val);
7575 kvm_get_dr(vcpu, 7, &val);
7576 put_smstate(u64, buf, 0x7f60, val);
7578 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7579 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7580 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7582 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7585 put_smstate(u32, buf, 0x7efc, 0x00020064);
7587 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7589 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7590 put_smstate(u16, buf, 0x7e90, seg.selector);
7591 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7592 put_smstate(u32, buf, 0x7e94, seg.limit);
7593 put_smstate(u64, buf, 0x7e98, seg.base);
7595 kvm_x86_ops->get_idt(vcpu, &dt);
7596 put_smstate(u32, buf, 0x7e84, dt.size);
7597 put_smstate(u64, buf, 0x7e88, dt.address);
7599 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7600 put_smstate(u16, buf, 0x7e70, seg.selector);
7601 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7602 put_smstate(u32, buf, 0x7e74, seg.limit);
7603 put_smstate(u64, buf, 0x7e78, seg.base);
7605 kvm_x86_ops->get_gdt(vcpu, &dt);
7606 put_smstate(u32, buf, 0x7e64, dt.size);
7607 put_smstate(u64, buf, 0x7e68, dt.address);
7609 for (i = 0; i < 6; i++)
7610 enter_smm_save_seg_64(vcpu, buf, i);
7614 static void enter_smm(struct kvm_vcpu *vcpu)
7616 struct kvm_segment cs, ds;
7621 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7622 memset(buf, 0, 512);
7623 #ifdef CONFIG_X86_64
7624 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7625 enter_smm_save_state_64(vcpu, buf);
7628 enter_smm_save_state_32(vcpu, buf);
7631 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7632 * vCPU state (e.g. leave guest mode) after we've saved the state into
7633 * the SMM state-save area.
7635 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7637 vcpu->arch.hflags |= HF_SMM_MASK;
7638 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7640 if (kvm_x86_ops->get_nmi_mask(vcpu))
7641 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7643 kvm_x86_ops->set_nmi_mask(vcpu, true);
7645 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7646 kvm_rip_write(vcpu, 0x8000);
7648 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7649 kvm_x86_ops->set_cr0(vcpu, cr0);
7650 vcpu->arch.cr0 = cr0;
7652 kvm_x86_ops->set_cr4(vcpu, 0);
7654 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7655 dt.address = dt.size = 0;
7656 kvm_x86_ops->set_idt(vcpu, &dt);
7658 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7660 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7661 cs.base = vcpu->arch.smbase;
7666 cs.limit = ds.limit = 0xffffffff;
7667 cs.type = ds.type = 0x3;
7668 cs.dpl = ds.dpl = 0;
7673 cs.avl = ds.avl = 0;
7674 cs.present = ds.present = 1;
7675 cs.unusable = ds.unusable = 0;
7676 cs.padding = ds.padding = 0;
7678 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7679 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7680 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7681 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7682 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7683 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7685 #ifdef CONFIG_X86_64
7686 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7687 kvm_x86_ops->set_efer(vcpu, 0);
7690 kvm_update_cpuid(vcpu);
7691 kvm_mmu_reset_context(vcpu);
7694 static void process_smi(struct kvm_vcpu *vcpu)
7696 vcpu->arch.smi_pending = true;
7697 kvm_make_request(KVM_REQ_EVENT, vcpu);
7700 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7702 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7705 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7707 if (!kvm_apic_present(vcpu))
7710 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7712 if (irqchip_split(vcpu->kvm))
7713 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7715 if (vcpu->arch.apicv_active)
7716 kvm_x86_ops->sync_pir_to_irr(vcpu);
7717 if (ioapic_in_kernel(vcpu->kvm))
7718 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7721 if (is_guest_mode(vcpu))
7722 vcpu->arch.load_eoi_exitmap_pending = true;
7724 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7727 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7729 u64 eoi_exit_bitmap[4];
7731 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7734 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7735 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7736 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7739 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7740 unsigned long start, unsigned long end,
7743 unsigned long apic_address;
7746 * The physical address of apic access page is stored in the VMCS.
7747 * Update it when it becomes invalid.
7749 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7750 if (start <= apic_address && apic_address < end)
7751 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7756 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7758 struct page *page = NULL;
7760 if (!lapic_in_kernel(vcpu))
7763 if (!kvm_x86_ops->set_apic_access_page_addr)
7766 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7767 if (is_error_page(page))
7769 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7772 * Do not pin apic access page in memory, the MMU notifier
7773 * will call us again if it is migrated or swapped out.
7777 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7779 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7781 smp_send_reschedule(vcpu->cpu);
7783 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7786 * Returns 1 to let vcpu_run() continue the guest execution loop without
7787 * exiting to the userspace. Otherwise, the value will be returned to the
7790 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7794 dm_request_for_irq_injection(vcpu) &&
7795 kvm_cpu_accept_dm_intr(vcpu);
7797 bool req_immediate_exit = false;
7799 if (kvm_request_pending(vcpu)) {
7800 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7801 kvm_x86_ops->get_vmcs12_pages(vcpu);
7802 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7803 kvm_mmu_unload(vcpu);
7804 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7805 __kvm_migrate_timers(vcpu);
7806 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7807 kvm_gen_update_masterclock(vcpu->kvm);
7808 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7809 kvm_gen_kvmclock_update(vcpu);
7810 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7811 r = kvm_guest_time_update(vcpu);
7815 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7816 kvm_mmu_sync_roots(vcpu);
7817 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7818 kvm_mmu_load_cr3(vcpu);
7819 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7820 kvm_vcpu_flush_tlb(vcpu, true);
7821 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7822 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7826 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7827 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7828 vcpu->mmio_needed = 0;
7832 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7833 /* Page is swapped out. Do synthetic halt */
7834 vcpu->arch.apf.halted = true;
7838 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7839 record_steal_time(vcpu);
7840 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7842 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7844 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7845 kvm_pmu_handle_event(vcpu);
7846 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7847 kvm_pmu_deliver_pmi(vcpu);
7848 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7849 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7850 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7851 vcpu->arch.ioapic_handled_vectors)) {
7852 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7853 vcpu->run->eoi.vector =
7854 vcpu->arch.pending_ioapic_eoi;
7859 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7860 vcpu_scan_ioapic(vcpu);
7861 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7862 vcpu_load_eoi_exitmap(vcpu);
7863 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7864 kvm_vcpu_reload_apic_access_page(vcpu);
7865 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7866 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7867 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7871 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7872 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7873 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7877 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7878 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7879 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7885 * KVM_REQ_HV_STIMER has to be processed after
7886 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7887 * depend on the guest clock being up-to-date
7889 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7890 kvm_hv_process_stimers(vcpu);
7893 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7894 ++vcpu->stat.req_event;
7895 kvm_apic_accept_events(vcpu);
7896 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7901 if (inject_pending_event(vcpu, req_int_win) != 0)
7902 req_immediate_exit = true;
7904 /* Enable SMI/NMI/IRQ window open exits if needed.
7906 * SMIs have three cases:
7907 * 1) They can be nested, and then there is nothing to
7908 * do here because RSM will cause a vmexit anyway.
7909 * 2) There is an ISA-specific reason why SMI cannot be
7910 * injected, and the moment when this changes can be
7912 * 3) Or the SMI can be pending because
7913 * inject_pending_event has completed the injection
7914 * of an IRQ or NMI from the previous vmexit, and
7915 * then we request an immediate exit to inject the
7918 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7919 if (!kvm_x86_ops->enable_smi_window(vcpu))
7920 req_immediate_exit = true;
7921 if (vcpu->arch.nmi_pending)
7922 kvm_x86_ops->enable_nmi_window(vcpu);
7923 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7924 kvm_x86_ops->enable_irq_window(vcpu);
7925 WARN_ON(vcpu->arch.exception.pending);
7928 if (kvm_lapic_enabled(vcpu)) {
7929 update_cr8_intercept(vcpu);
7930 kvm_lapic_sync_to_vapic(vcpu);
7934 r = kvm_mmu_reload(vcpu);
7936 goto cancel_injection;
7941 kvm_x86_ops->prepare_guest_switch(vcpu);
7944 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7945 * IPI are then delayed after guest entry, which ensures that they
7946 * result in virtual interrupt delivery.
7948 local_irq_disable();
7949 vcpu->mode = IN_GUEST_MODE;
7951 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7954 * 1) We should set ->mode before checking ->requests. Please see
7955 * the comment in kvm_vcpu_exiting_guest_mode().
7957 * 2) For APICv, we should set ->mode before checking PID.ON. This
7958 * pairs with the memory barrier implicit in pi_test_and_set_on
7959 * (see vmx_deliver_posted_interrupt).
7961 * 3) This also orders the write to mode from any reads to the page
7962 * tables done while the VCPU is running. Please see the comment
7963 * in kvm_flush_remote_tlbs.
7965 smp_mb__after_srcu_read_unlock();
7968 * This handles the case where a posted interrupt was
7969 * notified with kvm_vcpu_kick.
7971 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7972 kvm_x86_ops->sync_pir_to_irr(vcpu);
7974 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7975 || need_resched() || signal_pending(current)) {
7976 vcpu->mode = OUTSIDE_GUEST_MODE;
7980 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7982 goto cancel_injection;
7985 if (req_immediate_exit) {
7986 kvm_make_request(KVM_REQ_EVENT, vcpu);
7987 kvm_x86_ops->request_immediate_exit(vcpu);
7990 trace_kvm_entry(vcpu->vcpu_id);
7991 guest_enter_irqoff();
7993 fpregs_assert_state_consistent();
7994 if (test_thread_flag(TIF_NEED_FPU_LOAD))
7995 switch_fpu_return();
7997 if (unlikely(vcpu->arch.switch_db_regs)) {
7999 set_debugreg(vcpu->arch.eff_db[0], 0);
8000 set_debugreg(vcpu->arch.eff_db[1], 1);
8001 set_debugreg(vcpu->arch.eff_db[2], 2);
8002 set_debugreg(vcpu->arch.eff_db[3], 3);
8003 set_debugreg(vcpu->arch.dr6, 6);
8004 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8007 kvm_x86_ops->run(vcpu);
8010 * Do this here before restoring debug registers on the host. And
8011 * since we do this before handling the vmexit, a DR access vmexit
8012 * can (a) read the correct value of the debug registers, (b) set
8013 * KVM_DEBUGREG_WONT_EXIT again.
8015 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8016 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8017 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8018 kvm_update_dr0123(vcpu);
8019 kvm_update_dr6(vcpu);
8020 kvm_update_dr7(vcpu);
8021 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8025 * If the guest has used debug registers, at least dr7
8026 * will be disabled while returning to the host.
8027 * If we don't have active breakpoints in the host, we don't
8028 * care about the messed up debug address registers. But if
8029 * we have some of them active, restore the old state.
8031 if (hw_breakpoint_active())
8032 hw_breakpoint_restore();
8034 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8036 vcpu->mode = OUTSIDE_GUEST_MODE;
8039 kvm_x86_ops->handle_exit_irqoff(vcpu);
8042 * Consume any pending interrupts, including the possible source of
8043 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8044 * An instruction is required after local_irq_enable() to fully unblock
8045 * interrupts on processors that implement an interrupt shadow, the
8046 * stat.exits increment will do nicely.
8048 kvm_before_interrupt(vcpu);
8051 local_irq_disable();
8052 kvm_after_interrupt(vcpu);
8054 guest_exit_irqoff();
8055 if (lapic_in_kernel(vcpu)) {
8056 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8057 if (delta != S64_MIN) {
8058 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8059 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8066 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8069 * Profile KVM exit RIPs:
8071 if (unlikely(prof_on == KVM_PROFILING)) {
8072 unsigned long rip = kvm_rip_read(vcpu);
8073 profile_hit(KVM_PROFILING, (void *)rip);
8076 if (unlikely(vcpu->arch.tsc_always_catchup))
8077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8079 if (vcpu->arch.apic_attention)
8080 kvm_lapic_sync_from_vapic(vcpu);
8082 vcpu->arch.gpa_available = false;
8083 r = kvm_x86_ops->handle_exit(vcpu);
8087 kvm_x86_ops->cancel_injection(vcpu);
8088 if (unlikely(vcpu->arch.apic_attention))
8089 kvm_lapic_sync_from_vapic(vcpu);
8094 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8096 if (!kvm_arch_vcpu_runnable(vcpu) &&
8097 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8098 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8099 kvm_vcpu_block(vcpu);
8100 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8102 if (kvm_x86_ops->post_block)
8103 kvm_x86_ops->post_block(vcpu);
8105 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8109 kvm_apic_accept_events(vcpu);
8110 switch(vcpu->arch.mp_state) {
8111 case KVM_MP_STATE_HALTED:
8112 vcpu->arch.pv.pv_unhalted = false;
8113 vcpu->arch.mp_state =
8114 KVM_MP_STATE_RUNNABLE;
8116 case KVM_MP_STATE_RUNNABLE:
8117 vcpu->arch.apf.halted = false;
8119 case KVM_MP_STATE_INIT_RECEIVED:
8128 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8130 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8131 kvm_x86_ops->check_nested_events(vcpu, false);
8133 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8134 !vcpu->arch.apf.halted);
8137 static int vcpu_run(struct kvm_vcpu *vcpu)
8140 struct kvm *kvm = vcpu->kvm;
8142 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8143 vcpu->arch.l1tf_flush_l1d = true;
8146 if (kvm_vcpu_running(vcpu)) {
8147 r = vcpu_enter_guest(vcpu);
8149 r = vcpu_block(kvm, vcpu);
8155 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8156 if (kvm_cpu_has_pending_timer(vcpu))
8157 kvm_inject_pending_timer_irqs(vcpu);
8159 if (dm_request_for_irq_injection(vcpu) &&
8160 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8162 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8163 ++vcpu->stat.request_irq_exits;
8167 kvm_check_async_pf_completion(vcpu);
8169 if (signal_pending(current)) {
8171 vcpu->run->exit_reason = KVM_EXIT_INTR;
8172 ++vcpu->stat.signal_exits;
8175 if (need_resched()) {
8176 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8178 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8182 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8187 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8190 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8191 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8192 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8193 if (r != EMULATE_DONE)
8198 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8200 BUG_ON(!vcpu->arch.pio.count);
8202 return complete_emulated_io(vcpu);
8206 * Implements the following, as a state machine:
8210 * for each mmio piece in the fragment
8218 * for each mmio piece in the fragment
8223 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8225 struct kvm_run *run = vcpu->run;
8226 struct kvm_mmio_fragment *frag;
8229 BUG_ON(!vcpu->mmio_needed);
8231 /* Complete previous fragment */
8232 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8233 len = min(8u, frag->len);
8234 if (!vcpu->mmio_is_write)
8235 memcpy(frag->data, run->mmio.data, len);
8237 if (frag->len <= 8) {
8238 /* Switch to the next fragment. */
8240 vcpu->mmio_cur_fragment++;
8242 /* Go forward to the next mmio piece. */
8248 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8249 vcpu->mmio_needed = 0;
8251 /* FIXME: return into emulator if single-stepping. */
8252 if (vcpu->mmio_is_write)
8254 vcpu->mmio_read_completed = 1;
8255 return complete_emulated_io(vcpu);
8258 run->exit_reason = KVM_EXIT_MMIO;
8259 run->mmio.phys_addr = frag->gpa;
8260 if (vcpu->mmio_is_write)
8261 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8262 run->mmio.len = min(8u, frag->len);
8263 run->mmio.is_write = vcpu->mmio_is_write;
8264 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8268 /* Swap (qemu) user FPU context for the guest FPU context. */
8269 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8273 copy_fpregs_to_fpstate(¤t->thread.fpu);
8274 /* PKRU is separately restored in kvm_x86_ops->run. */
8275 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8276 ~XFEATURE_MASK_PKRU);
8278 fpregs_mark_activate();
8284 /* When vcpu_run ends, restore user space FPU context. */
8285 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8289 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8290 copy_kernel_to_fpregs(¤t->thread.fpu.state);
8292 fpregs_mark_activate();
8295 ++vcpu->stat.fpu_reload;
8299 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8304 kvm_sigset_activate(vcpu);
8305 kvm_load_guest_fpu(vcpu);
8307 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8308 if (kvm_run->immediate_exit) {
8312 kvm_vcpu_block(vcpu);
8313 kvm_apic_accept_events(vcpu);
8314 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8316 if (signal_pending(current)) {
8318 vcpu->run->exit_reason = KVM_EXIT_INTR;
8319 ++vcpu->stat.signal_exits;
8324 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8329 if (vcpu->run->kvm_dirty_regs) {
8330 r = sync_regs(vcpu);
8335 /* re-sync apic's tpr */
8336 if (!lapic_in_kernel(vcpu)) {
8337 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8343 if (unlikely(vcpu->arch.complete_userspace_io)) {
8344 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8345 vcpu->arch.complete_userspace_io = NULL;
8350 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8352 if (kvm_run->immediate_exit)
8358 kvm_put_guest_fpu(vcpu);
8359 if (vcpu->run->kvm_valid_regs)
8361 post_kvm_run_save(vcpu);
8362 kvm_sigset_deactivate(vcpu);
8368 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8370 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8372 * We are here if userspace calls get_regs() in the middle of
8373 * instruction emulation. Registers state needs to be copied
8374 * back from emulation context to vcpu. Userspace shouldn't do
8375 * that usually, but some bad designed PV devices (vmware
8376 * backdoor interface) need this to work
8378 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8379 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8381 regs->rax = kvm_rax_read(vcpu);
8382 regs->rbx = kvm_rbx_read(vcpu);
8383 regs->rcx = kvm_rcx_read(vcpu);
8384 regs->rdx = kvm_rdx_read(vcpu);
8385 regs->rsi = kvm_rsi_read(vcpu);
8386 regs->rdi = kvm_rdi_read(vcpu);
8387 regs->rsp = kvm_rsp_read(vcpu);
8388 regs->rbp = kvm_rbp_read(vcpu);
8389 #ifdef CONFIG_X86_64
8390 regs->r8 = kvm_r8_read(vcpu);
8391 regs->r9 = kvm_r9_read(vcpu);
8392 regs->r10 = kvm_r10_read(vcpu);
8393 regs->r11 = kvm_r11_read(vcpu);
8394 regs->r12 = kvm_r12_read(vcpu);
8395 regs->r13 = kvm_r13_read(vcpu);
8396 regs->r14 = kvm_r14_read(vcpu);
8397 regs->r15 = kvm_r15_read(vcpu);
8400 regs->rip = kvm_rip_read(vcpu);
8401 regs->rflags = kvm_get_rflags(vcpu);
8404 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8407 __get_regs(vcpu, regs);
8412 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8414 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8415 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8417 kvm_rax_write(vcpu, regs->rax);
8418 kvm_rbx_write(vcpu, regs->rbx);
8419 kvm_rcx_write(vcpu, regs->rcx);
8420 kvm_rdx_write(vcpu, regs->rdx);
8421 kvm_rsi_write(vcpu, regs->rsi);
8422 kvm_rdi_write(vcpu, regs->rdi);
8423 kvm_rsp_write(vcpu, regs->rsp);
8424 kvm_rbp_write(vcpu, regs->rbp);
8425 #ifdef CONFIG_X86_64
8426 kvm_r8_write(vcpu, regs->r8);
8427 kvm_r9_write(vcpu, regs->r9);
8428 kvm_r10_write(vcpu, regs->r10);
8429 kvm_r11_write(vcpu, regs->r11);
8430 kvm_r12_write(vcpu, regs->r12);
8431 kvm_r13_write(vcpu, regs->r13);
8432 kvm_r14_write(vcpu, regs->r14);
8433 kvm_r15_write(vcpu, regs->r15);
8436 kvm_rip_write(vcpu, regs->rip);
8437 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8439 vcpu->arch.exception.pending = false;
8441 kvm_make_request(KVM_REQ_EVENT, vcpu);
8444 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8447 __set_regs(vcpu, regs);
8452 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8454 struct kvm_segment cs;
8456 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8460 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8462 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8466 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8467 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8468 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8469 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8470 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8471 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8473 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8474 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8476 kvm_x86_ops->get_idt(vcpu, &dt);
8477 sregs->idt.limit = dt.size;
8478 sregs->idt.base = dt.address;
8479 kvm_x86_ops->get_gdt(vcpu, &dt);
8480 sregs->gdt.limit = dt.size;
8481 sregs->gdt.base = dt.address;
8483 sregs->cr0 = kvm_read_cr0(vcpu);
8484 sregs->cr2 = vcpu->arch.cr2;
8485 sregs->cr3 = kvm_read_cr3(vcpu);
8486 sregs->cr4 = kvm_read_cr4(vcpu);
8487 sregs->cr8 = kvm_get_cr8(vcpu);
8488 sregs->efer = vcpu->arch.efer;
8489 sregs->apic_base = kvm_get_apic_base(vcpu);
8491 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8493 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8494 set_bit(vcpu->arch.interrupt.nr,
8495 (unsigned long *)sregs->interrupt_bitmap);
8498 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8499 struct kvm_sregs *sregs)
8502 __get_sregs(vcpu, sregs);
8507 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8508 struct kvm_mp_state *mp_state)
8512 kvm_apic_accept_events(vcpu);
8513 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8514 vcpu->arch.pv.pv_unhalted)
8515 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8517 mp_state->mp_state = vcpu->arch.mp_state;
8523 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8524 struct kvm_mp_state *mp_state)
8530 if (!lapic_in_kernel(vcpu) &&
8531 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8534 /* INITs are latched while in SMM */
8535 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8536 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8537 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8540 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8541 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8542 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8544 vcpu->arch.mp_state = mp_state->mp_state;
8545 kvm_make_request(KVM_REQ_EVENT, vcpu);
8553 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8554 int reason, bool has_error_code, u32 error_code)
8556 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8559 init_emulate_ctxt(vcpu);
8561 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8562 has_error_code, error_code);
8565 return EMULATE_FAIL;
8567 kvm_rip_write(vcpu, ctxt->eip);
8568 kvm_set_rflags(vcpu, ctxt->eflags);
8569 kvm_make_request(KVM_REQ_EVENT, vcpu);
8570 return EMULATE_DONE;
8572 EXPORT_SYMBOL_GPL(kvm_task_switch);
8574 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8576 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8577 (sregs->cr4 & X86_CR4_OSXSAVE))
8580 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8582 * When EFER.LME and CR0.PG are set, the processor is in
8583 * 64-bit mode (though maybe in a 32-bit code segment).
8584 * CR4.PAE and EFER.LMA must be set.
8586 if (!(sregs->cr4 & X86_CR4_PAE)
8587 || !(sregs->efer & EFER_LMA))
8591 * Not in 64-bit mode: EFER.LMA is clear and the code
8592 * segment cannot be 64-bit.
8594 if (sregs->efer & EFER_LMA || sregs->cs.l)
8601 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8603 struct msr_data apic_base_msr;
8604 int mmu_reset_needed = 0;
8605 int cpuid_update_needed = 0;
8606 int pending_vec, max_bits, idx;
8610 if (kvm_valid_sregs(vcpu, sregs))
8613 apic_base_msr.data = sregs->apic_base;
8614 apic_base_msr.host_initiated = true;
8615 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8618 dt.size = sregs->idt.limit;
8619 dt.address = sregs->idt.base;
8620 kvm_x86_ops->set_idt(vcpu, &dt);
8621 dt.size = sregs->gdt.limit;
8622 dt.address = sregs->gdt.base;
8623 kvm_x86_ops->set_gdt(vcpu, &dt);
8625 vcpu->arch.cr2 = sregs->cr2;
8626 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8627 vcpu->arch.cr3 = sregs->cr3;
8628 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8630 kvm_set_cr8(vcpu, sregs->cr8);
8632 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8633 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8635 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8636 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8637 vcpu->arch.cr0 = sregs->cr0;
8639 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8640 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8641 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8642 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8643 if (cpuid_update_needed)
8644 kvm_update_cpuid(vcpu);
8646 idx = srcu_read_lock(&vcpu->kvm->srcu);
8647 if (is_pae_paging(vcpu)) {
8648 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8649 mmu_reset_needed = 1;
8651 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8653 if (mmu_reset_needed)
8654 kvm_mmu_reset_context(vcpu);
8656 max_bits = KVM_NR_INTERRUPTS;
8657 pending_vec = find_first_bit(
8658 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8659 if (pending_vec < max_bits) {
8660 kvm_queue_interrupt(vcpu, pending_vec, false);
8661 pr_debug("Set back pending irq %d\n", pending_vec);
8664 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8665 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8666 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8667 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8668 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8669 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8671 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8672 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8674 update_cr8_intercept(vcpu);
8676 /* Older userspace won't unhalt the vcpu on reset. */
8677 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8678 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8680 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8682 kvm_make_request(KVM_REQ_EVENT, vcpu);
8689 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8690 struct kvm_sregs *sregs)
8695 ret = __set_sregs(vcpu, sregs);
8700 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8701 struct kvm_guest_debug *dbg)
8703 unsigned long rflags;
8708 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8710 if (vcpu->arch.exception.pending)
8712 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8713 kvm_queue_exception(vcpu, DB_VECTOR);
8715 kvm_queue_exception(vcpu, BP_VECTOR);
8719 * Read rflags as long as potentially injected trace flags are still
8722 rflags = kvm_get_rflags(vcpu);
8724 vcpu->guest_debug = dbg->control;
8725 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8726 vcpu->guest_debug = 0;
8728 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8729 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8730 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8731 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8733 for (i = 0; i < KVM_NR_DB_REGS; i++)
8734 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8736 kvm_update_dr7(vcpu);
8738 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8739 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8740 get_segment_base(vcpu, VCPU_SREG_CS);
8743 * Trigger an rflags update that will inject or remove the trace
8746 kvm_set_rflags(vcpu, rflags);
8748 kvm_x86_ops->update_bp_intercept(vcpu);
8758 * Translate a guest virtual address to a guest physical address.
8760 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8761 struct kvm_translation *tr)
8763 unsigned long vaddr = tr->linear_address;
8769 idx = srcu_read_lock(&vcpu->kvm->srcu);
8770 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8771 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8772 tr->physical_address = gpa;
8773 tr->valid = gpa != UNMAPPED_GVA;
8781 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8783 struct fxregs_state *fxsave;
8787 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8788 memcpy(fpu->fpr, fxsave->st_space, 128);
8789 fpu->fcw = fxsave->cwd;
8790 fpu->fsw = fxsave->swd;
8791 fpu->ftwx = fxsave->twd;
8792 fpu->last_opcode = fxsave->fop;
8793 fpu->last_ip = fxsave->rip;
8794 fpu->last_dp = fxsave->rdp;
8795 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8801 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8803 struct fxregs_state *fxsave;
8807 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8809 memcpy(fxsave->st_space, fpu->fpr, 128);
8810 fxsave->cwd = fpu->fcw;
8811 fxsave->swd = fpu->fsw;
8812 fxsave->twd = fpu->ftwx;
8813 fxsave->fop = fpu->last_opcode;
8814 fxsave->rip = fpu->last_ip;
8815 fxsave->rdp = fpu->last_dp;
8816 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8822 static void store_regs(struct kvm_vcpu *vcpu)
8824 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8826 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8827 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8829 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8830 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8832 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8833 kvm_vcpu_ioctl_x86_get_vcpu_events(
8834 vcpu, &vcpu->run->s.regs.events);
8837 static int sync_regs(struct kvm_vcpu *vcpu)
8839 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8842 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8843 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8844 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8846 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8847 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8849 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8851 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8852 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8853 vcpu, &vcpu->run->s.regs.events))
8855 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8861 static void fx_init(struct kvm_vcpu *vcpu)
8863 fpstate_init(&vcpu->arch.guest_fpu->state);
8864 if (boot_cpu_has(X86_FEATURE_XSAVES))
8865 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8866 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8869 * Ensure guest xcr0 is valid for loading
8871 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8873 vcpu->arch.cr0 |= X86_CR0_ET;
8876 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8878 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8880 kvmclock_reset(vcpu);
8882 kvm_x86_ops->vcpu_free(vcpu);
8883 free_cpumask_var(wbinvd_dirty_mask);
8886 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8889 struct kvm_vcpu *vcpu;
8891 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8892 printk_once(KERN_WARNING
8893 "kvm: SMP vm created on host with unstable TSC; "
8894 "guest TSC will not be reliable\n");
8896 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8901 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8903 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8904 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8905 kvm_vcpu_mtrr_init(vcpu);
8907 kvm_vcpu_reset(vcpu, false);
8908 kvm_init_mmu(vcpu, false);
8913 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8915 struct msr_data msr;
8916 struct kvm *kvm = vcpu->kvm;
8918 kvm_hv_vcpu_postcreate(vcpu);
8920 if (mutex_lock_killable(&vcpu->mutex))
8924 msr.index = MSR_IA32_TSC;
8925 msr.host_initiated = true;
8926 kvm_write_tsc(vcpu, &msr);
8929 /* poll control enabled by default */
8930 vcpu->arch.msr_kvm_poll_control = 1;
8932 mutex_unlock(&vcpu->mutex);
8934 if (!kvmclock_periodic_sync)
8937 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8938 KVMCLOCK_SYNC_PERIOD);
8941 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8943 vcpu->arch.apf.msr_val = 0;
8946 kvm_mmu_unload(vcpu);
8949 kvm_x86_ops->vcpu_free(vcpu);
8952 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8954 kvm_lapic_reset(vcpu, init_event);
8956 vcpu->arch.hflags = 0;
8958 vcpu->arch.smi_pending = 0;
8959 vcpu->arch.smi_count = 0;
8960 atomic_set(&vcpu->arch.nmi_queued, 0);
8961 vcpu->arch.nmi_pending = 0;
8962 vcpu->arch.nmi_injected = false;
8963 kvm_clear_interrupt_queue(vcpu);
8964 kvm_clear_exception_queue(vcpu);
8965 vcpu->arch.exception.pending = false;
8967 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8968 kvm_update_dr0123(vcpu);
8969 vcpu->arch.dr6 = DR6_INIT;
8970 kvm_update_dr6(vcpu);
8971 vcpu->arch.dr7 = DR7_FIXED_1;
8972 kvm_update_dr7(vcpu);
8976 kvm_make_request(KVM_REQ_EVENT, vcpu);
8977 vcpu->arch.apf.msr_val = 0;
8978 vcpu->arch.st.msr_val = 0;
8980 kvmclock_reset(vcpu);
8982 kvm_clear_async_pf_completion_queue(vcpu);
8983 kvm_async_pf_hash_reset(vcpu);
8984 vcpu->arch.apf.halted = false;
8986 if (kvm_mpx_supported()) {
8987 void *mpx_state_buffer;
8990 * To avoid have the INIT path from kvm_apic_has_events() that be
8991 * called with loaded FPU and does not let userspace fix the state.
8994 kvm_put_guest_fpu(vcpu);
8995 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8997 if (mpx_state_buffer)
8998 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8999 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9001 if (mpx_state_buffer)
9002 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9004 kvm_load_guest_fpu(vcpu);
9008 kvm_pmu_reset(vcpu);
9009 vcpu->arch.smbase = 0x30000;
9011 vcpu->arch.msr_misc_features_enables = 0;
9013 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9016 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9017 vcpu->arch.regs_avail = ~0;
9018 vcpu->arch.regs_dirty = ~0;
9020 vcpu->arch.ia32_xss = 0;
9022 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9025 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9027 struct kvm_segment cs;
9029 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9030 cs.selector = vector << 8;
9031 cs.base = vector << 12;
9032 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9033 kvm_rip_write(vcpu, 0);
9036 int kvm_arch_hardware_enable(void)
9039 struct kvm_vcpu *vcpu;
9044 bool stable, backwards_tsc = false;
9046 kvm_shared_msr_cpu_online();
9047 ret = kvm_x86_ops->hardware_enable();
9051 local_tsc = rdtsc();
9052 stable = !kvm_check_tsc_unstable();
9053 list_for_each_entry(kvm, &vm_list, vm_list) {
9054 kvm_for_each_vcpu(i, vcpu, kvm) {
9055 if (!stable && vcpu->cpu == smp_processor_id())
9056 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9057 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9058 backwards_tsc = true;
9059 if (vcpu->arch.last_host_tsc > max_tsc)
9060 max_tsc = vcpu->arch.last_host_tsc;
9066 * Sometimes, even reliable TSCs go backwards. This happens on
9067 * platforms that reset TSC during suspend or hibernate actions, but
9068 * maintain synchronization. We must compensate. Fortunately, we can
9069 * detect that condition here, which happens early in CPU bringup,
9070 * before any KVM threads can be running. Unfortunately, we can't
9071 * bring the TSCs fully up to date with real time, as we aren't yet far
9072 * enough into CPU bringup that we know how much real time has actually
9073 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9074 * variables that haven't been updated yet.
9076 * So we simply find the maximum observed TSC above, then record the
9077 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9078 * the adjustment will be applied. Note that we accumulate
9079 * adjustments, in case multiple suspend cycles happen before some VCPU
9080 * gets a chance to run again. In the event that no KVM threads get a
9081 * chance to run, we will miss the entire elapsed period, as we'll have
9082 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9083 * loose cycle time. This isn't too big a deal, since the loss will be
9084 * uniform across all VCPUs (not to mention the scenario is extremely
9085 * unlikely). It is possible that a second hibernate recovery happens
9086 * much faster than a first, causing the observed TSC here to be
9087 * smaller; this would require additional padding adjustment, which is
9088 * why we set last_host_tsc to the local tsc observed here.
9090 * N.B. - this code below runs only on platforms with reliable TSC,
9091 * as that is the only way backwards_tsc is set above. Also note
9092 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9093 * have the same delta_cyc adjustment applied if backwards_tsc
9094 * is detected. Note further, this adjustment is only done once,
9095 * as we reset last_host_tsc on all VCPUs to stop this from being
9096 * called multiple times (one for each physical CPU bringup).
9098 * Platforms with unreliable TSCs don't have to deal with this, they
9099 * will be compensated by the logic in vcpu_load, which sets the TSC to
9100 * catchup mode. This will catchup all VCPUs to real time, but cannot
9101 * guarantee that they stay in perfect synchronization.
9103 if (backwards_tsc) {
9104 u64 delta_cyc = max_tsc - local_tsc;
9105 list_for_each_entry(kvm, &vm_list, vm_list) {
9106 kvm->arch.backwards_tsc_observed = true;
9107 kvm_for_each_vcpu(i, vcpu, kvm) {
9108 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9109 vcpu->arch.last_host_tsc = local_tsc;
9110 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9114 * We have to disable TSC offset matching.. if you were
9115 * booting a VM while issuing an S4 host suspend....
9116 * you may have some problem. Solving this issue is
9117 * left as an exercise to the reader.
9119 kvm->arch.last_tsc_nsec = 0;
9120 kvm->arch.last_tsc_write = 0;
9127 void kvm_arch_hardware_disable(void)
9129 kvm_x86_ops->hardware_disable();
9130 drop_user_return_notifiers();
9133 int kvm_arch_hardware_setup(void)
9137 r = kvm_x86_ops->hardware_setup();
9141 if (kvm_has_tsc_control) {
9143 * Make sure the user can only configure tsc_khz values that
9144 * fit into a signed integer.
9145 * A min value is not calculated because it will always
9146 * be 1 on all machines.
9148 u64 max = min(0x7fffffffULL,
9149 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9150 kvm_max_guest_tsc_khz = max;
9152 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9155 kvm_init_msr_list();
9159 void kvm_arch_hardware_unsetup(void)
9161 kvm_x86_ops->hardware_unsetup();
9164 int kvm_arch_check_processor_compat(void)
9166 return kvm_x86_ops->check_processor_compatibility();
9169 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9171 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9173 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9175 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9177 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9180 struct static_key kvm_no_apic_vcpu __read_mostly;
9181 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9183 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9188 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9189 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9190 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9192 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9194 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9199 vcpu->arch.pio_data = page_address(page);
9201 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9203 r = kvm_mmu_create(vcpu);
9205 goto fail_free_pio_data;
9207 if (irqchip_in_kernel(vcpu->kvm)) {
9208 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9209 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9211 goto fail_mmu_destroy;
9213 static_key_slow_inc(&kvm_no_apic_vcpu);
9215 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9216 GFP_KERNEL_ACCOUNT);
9217 if (!vcpu->arch.mce_banks) {
9219 goto fail_free_lapic;
9221 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9223 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9224 GFP_KERNEL_ACCOUNT)) {
9226 goto fail_free_mce_banks;
9231 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9233 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9235 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9237 kvm_async_pf_hash_reset(vcpu);
9240 vcpu->arch.pending_external_vector = -1;
9241 vcpu->arch.preempted_in_kernel = false;
9243 kvm_hv_vcpu_init(vcpu);
9247 fail_free_mce_banks:
9248 kfree(vcpu->arch.mce_banks);
9250 kvm_free_lapic(vcpu);
9252 kvm_mmu_destroy(vcpu);
9254 free_page((unsigned long)vcpu->arch.pio_data);
9259 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9263 kvm_hv_vcpu_uninit(vcpu);
9264 kvm_pmu_destroy(vcpu);
9265 kfree(vcpu->arch.mce_banks);
9266 kvm_free_lapic(vcpu);
9267 idx = srcu_read_lock(&vcpu->kvm->srcu);
9268 kvm_mmu_destroy(vcpu);
9269 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9270 free_page((unsigned long)vcpu->arch.pio_data);
9271 if (!lapic_in_kernel(vcpu))
9272 static_key_slow_dec(&kvm_no_apic_vcpu);
9275 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9277 vcpu->arch.l1tf_flush_l1d = true;
9278 kvm_x86_ops->sched_in(vcpu, cpu);
9281 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9286 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9287 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9288 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9289 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9291 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9292 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9293 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9294 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9295 &kvm->arch.irq_sources_bitmap);
9297 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9298 mutex_init(&kvm->arch.apic_map_lock);
9299 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9301 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9302 pvclock_update_vm_gtod_copy(kvm);
9304 kvm->arch.guest_can_read_msr_platform_info = true;
9306 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9307 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9309 kvm_hv_init_vm(kvm);
9310 kvm_page_track_init(kvm);
9311 kvm_mmu_init_vm(kvm);
9313 if (kvm_x86_ops->vm_init)
9314 return kvm_x86_ops->vm_init(kvm);
9319 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9322 kvm_mmu_unload(vcpu);
9326 static void kvm_free_vcpus(struct kvm *kvm)
9329 struct kvm_vcpu *vcpu;
9332 * Unpin any mmu pages first.
9334 kvm_for_each_vcpu(i, vcpu, kvm) {
9335 kvm_clear_async_pf_completion_queue(vcpu);
9336 kvm_unload_vcpu_mmu(vcpu);
9338 kvm_for_each_vcpu(i, vcpu, kvm)
9339 kvm_arch_vcpu_free(vcpu);
9341 mutex_lock(&kvm->lock);
9342 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9343 kvm->vcpus[i] = NULL;
9345 atomic_set(&kvm->online_vcpus, 0);
9346 mutex_unlock(&kvm->lock);
9349 void kvm_arch_sync_events(struct kvm *kvm)
9351 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9352 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9356 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9360 struct kvm_memslots *slots = kvm_memslots(kvm);
9361 struct kvm_memory_slot *slot, old;
9363 /* Called with kvm->slots_lock held. */
9364 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9367 slot = id_to_memslot(slots, id);
9373 * MAP_SHARED to prevent internal slot pages from being moved
9376 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9377 MAP_SHARED | MAP_ANONYMOUS, 0);
9378 if (IS_ERR((void *)hva))
9379 return PTR_ERR((void *)hva);
9388 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9389 struct kvm_userspace_memory_region m;
9391 m.slot = id | (i << 16);
9393 m.guest_phys_addr = gpa;
9394 m.userspace_addr = hva;
9395 m.memory_size = size;
9396 r = __kvm_set_memory_region(kvm, &m);
9402 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9406 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9408 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9412 mutex_lock(&kvm->slots_lock);
9413 r = __x86_set_memory_region(kvm, id, gpa, size);
9414 mutex_unlock(&kvm->slots_lock);
9418 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9420 void kvm_arch_destroy_vm(struct kvm *kvm)
9422 if (current->mm == kvm->mm) {
9424 * Free memory regions allocated on behalf of userspace,
9425 * unless the the memory map has changed due to process exit
9428 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9429 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9430 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9432 if (kvm_x86_ops->vm_destroy)
9433 kvm_x86_ops->vm_destroy(kvm);
9434 kvm_pic_destroy(kvm);
9435 kvm_ioapic_destroy(kvm);
9436 kvm_free_vcpus(kvm);
9437 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9438 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9439 kvm_mmu_uninit_vm(kvm);
9440 kvm_page_track_cleanup(kvm);
9441 kvm_hv_destroy_vm(kvm);
9444 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9445 struct kvm_memory_slot *dont)
9449 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9450 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9451 kvfree(free->arch.rmap[i]);
9452 free->arch.rmap[i] = NULL;
9457 if (!dont || free->arch.lpage_info[i - 1] !=
9458 dont->arch.lpage_info[i - 1]) {
9459 kvfree(free->arch.lpage_info[i - 1]);
9460 free->arch.lpage_info[i - 1] = NULL;
9464 kvm_page_track_free_memslot(free, dont);
9467 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9468 unsigned long npages)
9472 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9473 struct kvm_lpage_info *linfo;
9478 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9479 slot->base_gfn, level) + 1;
9481 slot->arch.rmap[i] =
9482 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9483 GFP_KERNEL_ACCOUNT);
9484 if (!slot->arch.rmap[i])
9489 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9493 slot->arch.lpage_info[i - 1] = linfo;
9495 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9496 linfo[0].disallow_lpage = 1;
9497 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9498 linfo[lpages - 1].disallow_lpage = 1;
9499 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9501 * If the gfn and userspace address are not aligned wrt each
9502 * other, or if explicitly asked to, disable large page
9503 * support for this slot
9505 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9506 !kvm_largepages_enabled()) {
9509 for (j = 0; j < lpages; ++j)
9510 linfo[j].disallow_lpage = 1;
9514 if (kvm_page_track_create_memslot(slot, npages))
9520 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9521 kvfree(slot->arch.rmap[i]);
9522 slot->arch.rmap[i] = NULL;
9526 kvfree(slot->arch.lpage_info[i - 1]);
9527 slot->arch.lpage_info[i - 1] = NULL;
9532 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9535 * memslots->generation has been incremented.
9536 * mmio generation may have reached its maximum value.
9538 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9541 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9542 struct kvm_memory_slot *memslot,
9543 const struct kvm_userspace_memory_region *mem,
9544 enum kvm_mr_change change)
9549 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9550 struct kvm_memory_slot *new)
9552 /* Still write protect RO slot */
9553 if (new->flags & KVM_MEM_READONLY) {
9554 kvm_mmu_slot_remove_write_access(kvm, new);
9559 * Call kvm_x86_ops dirty logging hooks when they are valid.
9561 * kvm_x86_ops->slot_disable_log_dirty is called when:
9563 * - KVM_MR_CREATE with dirty logging is disabled
9564 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9566 * The reason is, in case of PML, we need to set D-bit for any slots
9567 * with dirty logging disabled in order to eliminate unnecessary GPA
9568 * logging in PML buffer (and potential PML buffer full VMEXT). This
9569 * guarantees leaving PML enabled during guest's lifetime won't have
9570 * any additional overhead from PML when guest is running with dirty
9571 * logging disabled for memory slots.
9573 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9574 * to dirty logging mode.
9576 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9578 * In case of write protect:
9580 * Write protect all pages for dirty logging.
9582 * All the sptes including the large sptes which point to this
9583 * slot are set to readonly. We can not create any new large
9584 * spte on this slot until the end of the logging.
9586 * See the comments in fast_page_fault().
9588 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9589 if (kvm_x86_ops->slot_enable_log_dirty)
9590 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9592 kvm_mmu_slot_remove_write_access(kvm, new);
9594 if (kvm_x86_ops->slot_disable_log_dirty)
9595 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9599 void kvm_arch_commit_memory_region(struct kvm *kvm,
9600 const struct kvm_userspace_memory_region *mem,
9601 const struct kvm_memory_slot *old,
9602 const struct kvm_memory_slot *new,
9603 enum kvm_mr_change change)
9605 if (!kvm->arch.n_requested_mmu_pages)
9606 kvm_mmu_change_mmu_pages(kvm,
9607 kvm_mmu_calculate_default_mmu_pages(kvm));
9610 * Dirty logging tracks sptes in 4k granularity, meaning that large
9611 * sptes have to be split. If live migration is successful, the guest
9612 * in the source machine will be destroyed and large sptes will be
9613 * created in the destination. However, if the guest continues to run
9614 * in the source machine (for example if live migration fails), small
9615 * sptes will remain around and cause bad performance.
9617 * Scan sptes if dirty logging has been stopped, dropping those
9618 * which can be collapsed into a single large-page spte. Later
9619 * page faults will create the large-page sptes.
9621 if ((change != KVM_MR_DELETE) &&
9622 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9623 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9624 kvm_mmu_zap_collapsible_sptes(kvm, new);
9627 * Set up write protection and/or dirty logging for the new slot.
9629 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9630 * been zapped so no dirty logging staff is needed for old slot. For
9631 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9632 * new and it's also covered when dealing with the new slot.
9634 * FIXME: const-ify all uses of struct kvm_memory_slot.
9636 if (change != KVM_MR_DELETE)
9637 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9640 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9642 kvm_mmu_zap_all(kvm);
9645 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9646 struct kvm_memory_slot *slot)
9648 kvm_page_track_flush_slot(kvm, slot);
9651 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9653 return (is_guest_mode(vcpu) &&
9654 kvm_x86_ops->guest_apic_has_interrupt &&
9655 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9658 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9660 if (!list_empty_careful(&vcpu->async_pf.done))
9663 if (kvm_apic_has_events(vcpu))
9666 if (vcpu->arch.pv.pv_unhalted)
9669 if (vcpu->arch.exception.pending)
9672 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9673 (vcpu->arch.nmi_pending &&
9674 kvm_x86_ops->nmi_allowed(vcpu)))
9677 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9678 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9681 if (kvm_arch_interrupt_allowed(vcpu) &&
9682 (kvm_cpu_has_interrupt(vcpu) ||
9683 kvm_guest_apic_has_interrupt(vcpu)))
9686 if (kvm_hv_has_stimer_pending(vcpu))
9692 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9694 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9697 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9699 return vcpu->arch.preempted_in_kernel;
9702 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9704 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9707 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9709 return kvm_x86_ops->interrupt_allowed(vcpu);
9712 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9714 if (is_64_bit_mode(vcpu))
9715 return kvm_rip_read(vcpu);
9716 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9717 kvm_rip_read(vcpu));
9719 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9721 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9723 return kvm_get_linear_rip(vcpu) == linear_rip;
9725 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9727 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9729 unsigned long rflags;
9731 rflags = kvm_x86_ops->get_rflags(vcpu);
9732 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9733 rflags &= ~X86_EFLAGS_TF;
9736 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9738 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9740 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9741 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9742 rflags |= X86_EFLAGS_TF;
9743 kvm_x86_ops->set_rflags(vcpu, rflags);
9746 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9748 __kvm_set_rflags(vcpu, rflags);
9749 kvm_make_request(KVM_REQ_EVENT, vcpu);
9751 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9753 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9757 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9761 r = kvm_mmu_reload(vcpu);
9765 if (!vcpu->arch.mmu->direct_map &&
9766 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9769 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9772 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9774 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9777 static inline u32 kvm_async_pf_next_probe(u32 key)
9779 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9782 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9784 u32 key = kvm_async_pf_hash_fn(gfn);
9786 while (vcpu->arch.apf.gfns[key] != ~0)
9787 key = kvm_async_pf_next_probe(key);
9789 vcpu->arch.apf.gfns[key] = gfn;
9792 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9795 u32 key = kvm_async_pf_hash_fn(gfn);
9797 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9798 (vcpu->arch.apf.gfns[key] != gfn &&
9799 vcpu->arch.apf.gfns[key] != ~0); i++)
9800 key = kvm_async_pf_next_probe(key);
9805 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9807 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9810 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9814 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9816 vcpu->arch.apf.gfns[i] = ~0;
9818 j = kvm_async_pf_next_probe(j);
9819 if (vcpu->arch.apf.gfns[j] == ~0)
9821 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9823 * k lies cyclically in ]i,j]
9825 * |....j i.k.| or |.k..j i...|
9827 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9828 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9833 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9836 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9840 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9843 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9847 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9849 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9852 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9853 (vcpu->arch.apf.send_user_only &&
9854 kvm_x86_ops->get_cpl(vcpu) == 0))
9860 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9862 if (unlikely(!lapic_in_kernel(vcpu) ||
9863 kvm_event_needs_reinjection(vcpu) ||
9864 vcpu->arch.exception.pending))
9867 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9871 * If interrupts are off we cannot even use an artificial
9874 return kvm_x86_ops->interrupt_allowed(vcpu);
9877 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9878 struct kvm_async_pf *work)
9880 struct x86_exception fault;
9882 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9883 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9885 if (kvm_can_deliver_async_pf(vcpu) &&
9886 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9887 fault.vector = PF_VECTOR;
9888 fault.error_code_valid = true;
9889 fault.error_code = 0;
9890 fault.nested_page_fault = false;
9891 fault.address = work->arch.token;
9892 fault.async_page_fault = true;
9893 kvm_inject_page_fault(vcpu, &fault);
9896 * It is not possible to deliver a paravirtualized asynchronous
9897 * page fault, but putting the guest in an artificial halt state
9898 * can be beneficial nevertheless: if an interrupt arrives, we
9899 * can deliver it timely and perhaps the guest will schedule
9900 * another process. When the instruction that triggered a page
9901 * fault is retried, hopefully the page will be ready in the host.
9903 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9907 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9908 struct kvm_async_pf *work)
9910 struct x86_exception fault;
9913 if (work->wakeup_all)
9914 work->arch.token = ~0; /* broadcast wakeup */
9916 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9917 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9919 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9920 !apf_get_user(vcpu, &val)) {
9921 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9922 vcpu->arch.exception.pending &&
9923 vcpu->arch.exception.nr == PF_VECTOR &&
9924 !apf_put_user(vcpu, 0)) {
9925 vcpu->arch.exception.injected = false;
9926 vcpu->arch.exception.pending = false;
9927 vcpu->arch.exception.nr = 0;
9928 vcpu->arch.exception.has_error_code = false;
9929 vcpu->arch.exception.error_code = 0;
9930 vcpu->arch.exception.has_payload = false;
9931 vcpu->arch.exception.payload = 0;
9932 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9933 fault.vector = PF_VECTOR;
9934 fault.error_code_valid = true;
9935 fault.error_code = 0;
9936 fault.nested_page_fault = false;
9937 fault.address = work->arch.token;
9938 fault.async_page_fault = true;
9939 kvm_inject_page_fault(vcpu, &fault);
9942 vcpu->arch.apf.halted = false;
9943 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9946 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9948 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9951 return kvm_can_do_async_pf(vcpu);
9954 void kvm_arch_start_assignment(struct kvm *kvm)
9956 atomic_inc(&kvm->arch.assigned_device_count);
9958 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9960 void kvm_arch_end_assignment(struct kvm *kvm)
9962 atomic_dec(&kvm->arch.assigned_device_count);
9964 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9966 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9968 return atomic_read(&kvm->arch.assigned_device_count);
9970 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9972 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9974 atomic_inc(&kvm->arch.noncoherent_dma_count);
9976 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9978 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9980 atomic_dec(&kvm->arch.noncoherent_dma_count);
9982 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9984 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9986 return atomic_read(&kvm->arch.noncoherent_dma_count);
9988 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9990 bool kvm_arch_has_irq_bypass(void)
9992 return kvm_x86_ops->update_pi_irte != NULL;
9995 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9996 struct irq_bypass_producer *prod)
9998 struct kvm_kernel_irqfd *irqfd =
9999 container_of(cons, struct kvm_kernel_irqfd, consumer);
10001 irqfd->producer = prod;
10003 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10004 prod->irq, irqfd->gsi, 1);
10007 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10008 struct irq_bypass_producer *prod)
10011 struct kvm_kernel_irqfd *irqfd =
10012 container_of(cons, struct kvm_kernel_irqfd, consumer);
10014 WARN_ON(irqfd->producer != prod);
10015 irqfd->producer = NULL;
10018 * When producer of consumer is unregistered, we change back to
10019 * remapped mode, so we can re-use the current implementation
10020 * when the irq is masked/disabled or the consumer side (KVM
10021 * int this case doesn't want to receive the interrupts.
10023 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10025 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10026 " fails: %d\n", irqfd->consumer.token, ret);
10029 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10030 uint32_t guest_irq, bool set)
10032 if (!kvm_x86_ops->update_pi_irte)
10035 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10038 bool kvm_vector_hashing_enabled(void)
10040 return vector_hashing;
10042 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10044 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10046 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10048 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10051 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10052 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10053 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10054 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10055 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10056 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10057 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10058 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10059 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10060 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10061 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10062 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10063 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10064 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10065 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
10066 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10067 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10068 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10069 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);