1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/export.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <linux/kvm_irqfd.h>
52 #include <linux/irqbypass.h>
53 #include <linux/sched/stat.h>
54 #include <linux/sched/isolation.h>
55 #include <linux/mem_encrypt.h>
57 #include <trace/events/kvm.h>
59 #include <asm/debugreg.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68 #include <asm/mshyperv.h>
69 #include <asm/hypervisor.h>
70 #include <asm/intel_pt.h>
71 #include <clocksource/hyperv_timer.h>
73 #define CREATE_TRACE_POINTS
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 #define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32 __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64 __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
144 static int __read_mostly lapic_timer_advance_ns = -1;
145 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
147 static bool __read_mostly vector_hashing = true;
148 module_param(vector_hashing, bool, S_IRUGO);
150 bool __read_mostly enable_vmware_backdoor = false;
151 module_param(enable_vmware_backdoor, bool, S_IRUGO);
152 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
154 static bool __read_mostly force_emulation_prefix = false;
155 module_param(force_emulation_prefix, bool, S_IRUGO);
157 int __read_mostly pi_inject_timer = -1;
158 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
160 #define KVM_NR_SHARED_MSRS 16
162 struct kvm_shared_msrs_global {
164 u32 msrs[KVM_NR_SHARED_MSRS];
167 struct kvm_shared_msrs {
168 struct user_return_notifier urn;
170 struct kvm_shared_msr_values {
173 } values[KVM_NR_SHARED_MSRS];
176 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
177 static struct kvm_shared_msrs __percpu *shared_msrs;
179 struct kvm_stats_debugfs_item debugfs_entries[] = {
180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
190 { "halt_exits", VCPU_STAT(halt_exits) },
191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
195 { "hypercalls", VCPU_STAT(hypercalls) },
196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
202 { "irq_injections", VCPU_STAT(irq_injections) },
203 { "nmi_injections", VCPU_STAT(nmi_injections) },
204 { "req_event", VCPU_STAT(req_event) },
205 { "l1d_flush", VCPU_STAT(l1d_flush) },
206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
213 { "mmu_unsync", VM_STAT(mmu_unsync) },
214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
215 { "largepages", VM_STAT(lpages) },
216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
221 u64 __read_mostly host_xcr0;
223 struct kmem_cache *x86_fpu_cache;
224 EXPORT_SYMBOL_GPL(x86_fpu_cache);
226 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
228 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
235 static void kvm_on_user_return(struct user_return_notifier *urn)
238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
240 struct kvm_shared_msr_values *values;
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
252 local_irq_restore(flags);
253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
262 static void shared_msr_update(unsigned slot, u32 msr)
265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
279 void kvm_define_shared_msr(unsigned slot, u32 msr)
281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
282 shared_msrs_global.msrs[slot] = msr;
283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
286 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
288 static void kvm_shared_msr_cpu_online(void)
292 for (i = 0; i < shared_msrs_global.nr; ++i)
293 shared_msr_update(i, shared_msrs_global.msrs[i]);
296 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
304 smsr->values[slot].curr = value;
305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
316 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
318 static void drop_user_return_notifiers(void)
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
327 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
329 return vcpu->arch.apic_base;
331 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
333 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
337 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
339 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
355 kvm_lapic_set_base(vcpu, msr_info->data);
358 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
360 asmlinkage __visible void kvm_spurious_fault(void)
362 /* Fault while not rebooting. We want the trace. */
365 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
367 #define EXCPT_BENIGN 0
368 #define EXCPT_CONTRIBUTORY 1
371 static int exception_class(int vector)
381 return EXCPT_CONTRIBUTORY;
388 #define EXCPT_FAULT 0
390 #define EXCPT_ABORT 2
391 #define EXCPT_INTERRUPT 3
393 static int exception_type(int vector)
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
409 /* Reserved exceptions will result in fault */
413 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
446 vcpu->arch.cr2 = payload;
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
453 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
455 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
456 unsigned nr, bool has_error, u32 error_code,
457 bool has_payload, unsigned long payload, bool reinject)
462 kvm_make_request(KVM_REQ_EVENT, vcpu);
464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
466 if (has_error && !is_protmode(vcpu))
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
479 if (WARN_ON_ONCE(has_payload)) {
481 * A reinjected event has already
482 * delivered its payload.
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
529 vcpu->arch.exception.pending = true;
530 vcpu->arch.exception.injected = false;
531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
543 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
547 EXPORT_SYMBOL_GPL(kvm_queue_exception);
549 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
553 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
555 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
561 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
568 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
571 kvm_inject_gp(vcpu, 0);
573 return kvm_skip_emulated_instruction(vcpu);
577 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
579 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
581 ++vcpu->stat.pf_guest;
582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
584 if (vcpu->arch.exception.nested_apf) {
585 vcpu->arch.apf.nested_apf_token = fault->address;
586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
592 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
594 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
601 return fault->nested_page_fault;
604 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
609 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
611 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
615 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
617 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
621 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
627 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
634 EXPORT_SYMBOL_GPL(kvm_require_cpl);
636 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
641 kvm_queue_exception(vcpu, UD_VECTOR);
644 EXPORT_SYMBOL_GPL(kvm_require_dr);
647 * This function will be used to read from the physical memory of the currently
648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
649 * can read from guest physical or from the guest's guest physical memory.
651 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
655 struct x86_exception exception;
659 ngpa = gfn_to_gpa(ngfn);
660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
661 if (real_gfn == UNMAPPED_GVA)
664 real_gfn = gpa_to_gfn(real_gfn);
666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
668 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
670 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
671 void *data, int offset, int len, u32 access)
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
678 * Load the pae pdptrs. Return true is they are all valid.
680 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
682 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
683 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
686 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
688 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
689 offset * sizeof(u64), sizeof(pdpte),
690 PFERR_USER_MASK|PFERR_WRITE_MASK);
695 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
696 if ((pdpte[i] & PT_PRESENT_MASK) &&
698 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
705 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_avail);
708 __set_bit(VCPU_EXREG_PDPTR,
709 (unsigned long *)&vcpu->arch.regs_dirty);
714 EXPORT_SYMBOL_GPL(load_pdptrs);
716 bool pdptrs_changed(struct kvm_vcpu *vcpu)
718 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
724 if (!is_pae_paging(vcpu))
727 if (!test_bit(VCPU_EXREG_PDPTR,
728 (unsigned long *)&vcpu->arch.regs_avail))
731 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
732 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
733 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
734 PFERR_USER_MASK | PFERR_WRITE_MASK);
737 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
742 EXPORT_SYMBOL_GPL(pdptrs_changed);
744 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
746 unsigned long old_cr0 = kvm_read_cr0(vcpu);
747 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
752 if (cr0 & 0xffffffff00000000UL)
756 cr0 &= ~CR0_RESERVED_BITS;
758 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
761 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
764 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
766 if ((vcpu->arch.efer & EFER_LME)) {
771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
776 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
781 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
784 kvm_x86_ops->set_cr0(vcpu, cr0);
786 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
787 kvm_clear_async_pf_completion_queue(vcpu);
788 kvm_async_pf_hash_reset(vcpu);
791 if ((cr0 ^ old_cr0) & update_bits)
792 kvm_mmu_reset_context(vcpu);
794 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
795 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
796 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
797 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
801 EXPORT_SYMBOL_GPL(kvm_set_cr0);
803 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
805 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
807 EXPORT_SYMBOL_GPL(kvm_lmsw);
809 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
811 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
812 !vcpu->guest_xcr0_loaded) {
813 /* kvm_set_xcr() also depends on this */
814 if (vcpu->arch.xcr0 != host_xcr0)
815 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
816 vcpu->guest_xcr0_loaded = 1;
819 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
821 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
823 if (vcpu->guest_xcr0_loaded) {
824 if (vcpu->arch.xcr0 != host_xcr0)
825 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
826 vcpu->guest_xcr0_loaded = 0;
829 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
831 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
834 u64 old_xcr0 = vcpu->arch.xcr0;
837 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
838 if (index != XCR_XFEATURE_ENABLED_MASK)
840 if (!(xcr0 & XFEATURE_MASK_FP))
842 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
846 * Do not allow the guest to set bits that we do not support
847 * saving. However, xcr0 bit 0 is always set, even if the
848 * emulated CPU does not support XSAVE (see fx_init).
850 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
851 if (xcr0 & ~valid_bits)
854 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
855 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
858 if (xcr0 & XFEATURE_MASK_AVX512) {
859 if (!(xcr0 & XFEATURE_MASK_YMM))
861 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
864 vcpu->arch.xcr0 = xcr0;
866 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
867 kvm_update_cpuid(vcpu);
871 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
873 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
874 __kvm_set_xcr(vcpu, index, xcr)) {
875 kvm_inject_gp(vcpu, 0);
880 EXPORT_SYMBOL_GPL(kvm_set_xcr);
882 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
884 unsigned long old_cr4 = kvm_read_cr4(vcpu);
885 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
886 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
888 if (cr4 & CR4_RESERVED_BITS)
891 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
894 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
897 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
900 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
903 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
906 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
909 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
912 if (is_long_mode(vcpu)) {
913 if (!(cr4 & X86_CR4_PAE))
915 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
916 && ((cr4 ^ old_cr4) & pdptr_bits)
917 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
921 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
922 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
925 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
926 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
930 if (kvm_x86_ops->set_cr4(vcpu, cr4))
933 if (((cr4 ^ old_cr4) & pdptr_bits) ||
934 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
935 kvm_mmu_reset_context(vcpu);
937 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
938 kvm_update_cpuid(vcpu);
942 EXPORT_SYMBOL_GPL(kvm_set_cr4);
944 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
946 bool skip_tlb_flush = false;
948 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
951 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
952 cr3 &= ~X86_CR3_PCID_NOFLUSH;
956 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
957 if (!skip_tlb_flush) {
958 kvm_mmu_sync_roots(vcpu);
959 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
964 if (is_long_mode(vcpu) &&
965 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
967 else if (is_pae_paging(vcpu) &&
968 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
971 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
972 vcpu->arch.cr3 = cr3;
973 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
977 EXPORT_SYMBOL_GPL(kvm_set_cr3);
979 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
981 if (cr8 & CR8_RESERVED_BITS)
983 if (lapic_in_kernel(vcpu))
984 kvm_lapic_set_tpr(vcpu, cr8);
986 vcpu->arch.cr8 = cr8;
989 EXPORT_SYMBOL_GPL(kvm_set_cr8);
991 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
993 if (lapic_in_kernel(vcpu))
994 return kvm_lapic_get_cr8(vcpu);
996 return vcpu->arch.cr8;
998 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1000 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1004 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1005 for (i = 0; i < KVM_NR_DB_REGS; i++)
1006 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1007 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1011 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1013 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1014 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1017 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022 dr7 = vcpu->arch.guest_debug_dr7;
1024 dr7 = vcpu->arch.dr7;
1025 kvm_x86_ops->set_dr7(vcpu, dr7);
1026 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1027 if (dr7 & DR7_BP_EN_MASK)
1028 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1031 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1033 u64 fixed = DR6_FIXED_1;
1035 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1040 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1044 vcpu->arch.db[dr] = val;
1045 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1046 vcpu->arch.eff_db[dr] = val;
1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
1053 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1054 kvm_update_dr6(vcpu);
1059 if (val & 0xffffffff00000000ULL)
1060 return -1; /* #GP */
1061 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1062 kvm_update_dr7(vcpu);
1069 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1071 if (__kvm_set_dr(vcpu, dr, val)) {
1072 kvm_inject_gp(vcpu, 0);
1077 EXPORT_SYMBOL_GPL(kvm_set_dr);
1079 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1083 *val = vcpu->arch.db[dr];
1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 *val = vcpu->arch.dr6;
1091 *val = kvm_x86_ops->get_dr6(vcpu);
1096 *val = vcpu->arch.dr7;
1101 EXPORT_SYMBOL_GPL(kvm_get_dr);
1103 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1105 u32 ecx = kvm_rcx_read(vcpu);
1109 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1112 kvm_rax_write(vcpu, (u32)data);
1113 kvm_rdx_write(vcpu, data >> 32);
1116 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1119 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1120 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1122 * This list is modified at module load time to reflect the
1123 * capabilities of the host cpu. This capabilities test skips MSRs that are
1124 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1125 * may depend on host virtualization features rather than host cpu features.
1128 static u32 msrs_to_save[] = {
1129 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1131 #ifdef CONFIG_X86_64
1132 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1134 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1135 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1137 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1138 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1139 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1140 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1141 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1142 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1145 static unsigned num_msrs_to_save;
1147 static u32 emulated_msrs[] = {
1148 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1149 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1150 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1151 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1152 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1153 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1154 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1156 HV_X64_MSR_VP_INDEX,
1157 HV_X64_MSR_VP_RUNTIME,
1158 HV_X64_MSR_SCONTROL,
1159 HV_X64_MSR_STIMER0_CONFIG,
1160 HV_X64_MSR_VP_ASSIST_PAGE,
1161 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1162 HV_X64_MSR_TSC_EMULATION_STATUS,
1164 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1167 MSR_IA32_TSC_ADJUST,
1168 MSR_IA32_TSCDEADLINE,
1169 MSR_IA32_ARCH_CAPABILITIES,
1170 MSR_IA32_MISC_ENABLE,
1171 MSR_IA32_MCG_STATUS,
1173 MSR_IA32_MCG_EXT_CTL,
1177 MSR_MISC_FEATURES_ENABLES,
1178 MSR_AMD64_VIRT_SPEC_CTRL,
1182 * The following list leaves out MSRs whose values are determined
1183 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1184 * We always support the "true" VMX control MSRs, even if the host
1185 * processor does not, so I am putting these registers here rather
1186 * than in msrs_to_save.
1189 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1191 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1194 MSR_IA32_VMX_CR0_FIXED0,
1195 MSR_IA32_VMX_CR4_FIXED0,
1196 MSR_IA32_VMX_VMCS_ENUM,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 MSR_IA32_VMX_EPT_VPID_CAP,
1199 MSR_IA32_VMX_VMFUNC,
1202 MSR_KVM_POLL_CONTROL,
1205 static unsigned num_emulated_msrs;
1208 * List of msr numbers which are used to expose MSR-based features that
1209 * can be used by a hypervisor to validate requested CPU features.
1211 static u32 msr_based_features[] = {
1213 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1214 MSR_IA32_VMX_PINBASED_CTLS,
1215 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1216 MSR_IA32_VMX_PROCBASED_CTLS,
1217 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 MSR_IA32_VMX_EXIT_CTLS,
1219 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1220 MSR_IA32_VMX_ENTRY_CTLS,
1222 MSR_IA32_VMX_CR0_FIXED0,
1223 MSR_IA32_VMX_CR0_FIXED1,
1224 MSR_IA32_VMX_CR4_FIXED0,
1225 MSR_IA32_VMX_CR4_FIXED1,
1226 MSR_IA32_VMX_VMCS_ENUM,
1227 MSR_IA32_VMX_PROCBASED_CTLS2,
1228 MSR_IA32_VMX_EPT_VPID_CAP,
1229 MSR_IA32_VMX_VMFUNC,
1233 MSR_IA32_ARCH_CAPABILITIES,
1236 static unsigned int num_msr_based_features;
1238 static u64 kvm_get_arch_capabilities(void)
1242 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1243 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1246 * If we're doing cache flushes (either "always" or "cond")
1247 * we will do one whenever the guest does a vmlaunch/vmresume.
1248 * If an outer hypervisor is doing the cache flush for us
1249 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1250 * capability to the guest too, and if EPT is disabled we're not
1251 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1252 * require a nested hypervisor to do a flush of its own.
1254 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1255 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1260 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1262 switch (msr->index) {
1263 case MSR_IA32_ARCH_CAPABILITIES:
1264 msr->data = kvm_get_arch_capabilities();
1266 case MSR_IA32_UCODE_REV:
1267 rdmsrl_safe(msr->index, &msr->data);
1270 if (kvm_x86_ops->get_msr_feature(msr))
1276 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1278 struct kvm_msr_entry msr;
1282 r = kvm_get_msr_feature(&msr);
1291 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1293 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1296 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1299 if (efer & (EFER_LME | EFER_LMA) &&
1300 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1303 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1309 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1311 if (efer & efer_reserved_bits)
1314 return __kvm_valid_efer(vcpu, efer);
1316 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1318 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1320 u64 old_efer = vcpu->arch.efer;
1321 u64 efer = msr_info->data;
1323 if (efer & efer_reserved_bits)
1326 if (!msr_info->host_initiated) {
1327 if (!__kvm_valid_efer(vcpu, efer))
1330 if (is_paging(vcpu) &&
1331 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1336 efer |= vcpu->arch.efer & EFER_LMA;
1338 kvm_x86_ops->set_efer(vcpu, efer);
1340 /* Update reserved bits */
1341 if ((efer ^ old_efer) & EFER_NX)
1342 kvm_mmu_reset_context(vcpu);
1347 void kvm_enable_efer_bits(u64 mask)
1349 efer_reserved_bits &= ~mask;
1351 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1354 * Writes msr value into into the appropriate "register".
1355 * Returns 0 on success, non-0 otherwise.
1356 * Assumes vcpu_load() was already called.
1358 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1360 switch (msr->index) {
1363 case MSR_KERNEL_GS_BASE:
1366 if (is_noncanonical_address(msr->data, vcpu))
1369 case MSR_IA32_SYSENTER_EIP:
1370 case MSR_IA32_SYSENTER_ESP:
1372 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1373 * non-canonical address is written on Intel but not on
1374 * AMD (which ignores the top 32-bits, because it does
1375 * not implement 64-bit SYSENTER).
1377 * 64-bit code should hence be able to write a non-canonical
1378 * value on AMD. Making the address canonical ensures that
1379 * vmentry does not fail on Intel after writing a non-canonical
1380 * value, and that something deterministic happens if the guest
1381 * invokes 64-bit SYSENTER.
1383 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1385 return kvm_x86_ops->set_msr(vcpu, msr);
1387 EXPORT_SYMBOL_GPL(kvm_set_msr);
1390 * Adapt set_msr() to msr_io()'s calling convention
1392 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1394 struct msr_data msr;
1398 msr.host_initiated = true;
1399 r = kvm_get_msr(vcpu, &msr);
1407 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1409 struct msr_data msr;
1413 msr.host_initiated = true;
1414 return kvm_set_msr(vcpu, &msr);
1417 #ifdef CONFIG_X86_64
1418 struct pvclock_gtod_data {
1421 struct { /* extract of a clocksource struct */
1434 static struct pvclock_gtod_data pvclock_gtod_data;
1436 static void update_pvclock_gtod(struct timekeeper *tk)
1438 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1441 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1443 write_seqcount_begin(&vdata->seq);
1445 /* copy pvclock gtod data */
1446 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1447 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1448 vdata->clock.mask = tk->tkr_mono.mask;
1449 vdata->clock.mult = tk->tkr_mono.mult;
1450 vdata->clock.shift = tk->tkr_mono.shift;
1452 vdata->boot_ns = boot_ns;
1453 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1455 vdata->wall_time_sec = tk->xtime_sec;
1457 write_seqcount_end(&vdata->seq);
1461 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1463 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1464 kvm_vcpu_kick(vcpu);
1467 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1471 struct pvclock_wall_clock wc;
1472 struct timespec64 boot;
1477 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1482 ++version; /* first time write, random junk */
1486 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1490 * The guest calculates current wall clock time by adding
1491 * system time (updated by kvm_guest_time_update below) to the
1492 * wall clock specified here. guest system time equals host
1493 * system time for us, thus we must fill in host boot time here.
1495 getboottime64(&boot);
1497 if (kvm->arch.kvmclock_offset) {
1498 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1499 boot = timespec64_sub(boot, ts);
1501 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1502 wc.nsec = boot.tv_nsec;
1503 wc.version = version;
1505 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1508 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1511 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1513 do_shl32_div32(dividend, divisor);
1517 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1518 s8 *pshift, u32 *pmultiplier)
1526 scaled64 = scaled_hz;
1527 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1532 tps32 = (uint32_t)tps64;
1533 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1534 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1542 *pmultiplier = div_frac(scaled64, tps32);
1545 #ifdef CONFIG_X86_64
1546 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1549 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1550 static unsigned long max_tsc_khz;
1552 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1554 u64 v = (u64)khz * (1000000 + ppm);
1559 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1563 /* Guest TSC same frequency as host TSC? */
1565 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1569 /* TSC scaling supported? */
1570 if (!kvm_has_tsc_control) {
1571 if (user_tsc_khz > tsc_khz) {
1572 vcpu->arch.tsc_catchup = 1;
1573 vcpu->arch.tsc_always_catchup = 1;
1576 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1581 /* TSC scaling required - calculate ratio */
1582 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1583 user_tsc_khz, tsc_khz);
1585 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1586 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1591 vcpu->arch.tsc_scaling_ratio = ratio;
1595 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1597 u32 thresh_lo, thresh_hi;
1598 int use_scaling = 0;
1600 /* tsc_khz can be zero if TSC calibration fails */
1601 if (user_tsc_khz == 0) {
1602 /* set tsc_scaling_ratio to a safe value */
1603 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1607 /* Compute a scale to convert nanoseconds in TSC cycles */
1608 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1609 &vcpu->arch.virtual_tsc_shift,
1610 &vcpu->arch.virtual_tsc_mult);
1611 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1614 * Compute the variation in TSC rate which is acceptable
1615 * within the range of tolerance and decide if the
1616 * rate being applied is within that bounds of the hardware
1617 * rate. If so, no scaling or compensation need be done.
1619 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1620 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1621 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1622 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1625 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1628 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1630 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1631 vcpu->arch.virtual_tsc_mult,
1632 vcpu->arch.virtual_tsc_shift);
1633 tsc += vcpu->arch.this_tsc_write;
1637 static inline int gtod_is_based_on_tsc(int mode)
1639 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1642 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1644 #ifdef CONFIG_X86_64
1646 struct kvm_arch *ka = &vcpu->kvm->arch;
1647 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1649 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1650 atomic_read(&vcpu->kvm->online_vcpus));
1653 * Once the masterclock is enabled, always perform request in
1654 * order to update it.
1656 * In order to enable masterclock, the host clocksource must be TSC
1657 * and the vcpus need to have matched TSCs. When that happens,
1658 * perform request to enable masterclock.
1660 if (ka->use_master_clock ||
1661 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1662 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1664 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1665 atomic_read(&vcpu->kvm->online_vcpus),
1666 ka->use_master_clock, gtod->clock.vclock_mode);
1670 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1672 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1673 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1677 * Multiply tsc by a fixed point number represented by ratio.
1679 * The most significant 64-N bits (mult) of ratio represent the
1680 * integral part of the fixed point number; the remaining N bits
1681 * (frac) represent the fractional part, ie. ratio represents a fixed
1682 * point number (mult + frac * 2^(-N)).
1684 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1686 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1688 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1691 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1694 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1696 if (ratio != kvm_default_tsc_scaling_ratio)
1697 _tsc = __scale_tsc(ratio, tsc);
1701 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1703 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1707 tsc = kvm_scale_tsc(vcpu, rdtsc());
1709 return target_tsc - tsc;
1712 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1714 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1716 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1718 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1720 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1722 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1725 static inline bool kvm_check_tsc_unstable(void)
1727 #ifdef CONFIG_X86_64
1729 * TSC is marked unstable when we're running on Hyper-V,
1730 * 'TSC page' clocksource is good.
1732 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1735 return check_tsc_unstable();
1738 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1740 struct kvm *kvm = vcpu->kvm;
1741 u64 offset, ns, elapsed;
1742 unsigned long flags;
1744 bool already_matched;
1745 u64 data = msr->data;
1746 bool synchronizing = false;
1748 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1749 offset = kvm_compute_tsc_offset(vcpu, data);
1750 ns = ktime_get_boottime_ns();
1751 elapsed = ns - kvm->arch.last_tsc_nsec;
1753 if (vcpu->arch.virtual_tsc_khz) {
1754 if (data == 0 && msr->host_initiated) {
1756 * detection of vcpu initialization -- need to sync
1757 * with other vCPUs. This particularly helps to keep
1758 * kvm_clock stable after CPU hotplug
1760 synchronizing = true;
1762 u64 tsc_exp = kvm->arch.last_tsc_write +
1763 nsec_to_cycles(vcpu, elapsed);
1764 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1766 * Special case: TSC write with a small delta (1 second)
1767 * of virtual cycle time against real time is
1768 * interpreted as an attempt to synchronize the CPU.
1770 synchronizing = data < tsc_exp + tsc_hz &&
1771 data + tsc_hz > tsc_exp;
1776 * For a reliable TSC, we can match TSC offsets, and for an unstable
1777 * TSC, we add elapsed time in this computation. We could let the
1778 * compensation code attempt to catch up if we fall behind, but
1779 * it's better to try to match offsets from the beginning.
1781 if (synchronizing &&
1782 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1783 if (!kvm_check_tsc_unstable()) {
1784 offset = kvm->arch.cur_tsc_offset;
1786 u64 delta = nsec_to_cycles(vcpu, elapsed);
1788 offset = kvm_compute_tsc_offset(vcpu, data);
1791 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1794 * We split periods of matched TSC writes into generations.
1795 * For each generation, we track the original measured
1796 * nanosecond time, offset, and write, so if TSCs are in
1797 * sync, we can match exact offset, and if not, we can match
1798 * exact software computation in compute_guest_tsc()
1800 * These values are tracked in kvm->arch.cur_xxx variables.
1802 kvm->arch.cur_tsc_generation++;
1803 kvm->arch.cur_tsc_nsec = ns;
1804 kvm->arch.cur_tsc_write = data;
1805 kvm->arch.cur_tsc_offset = offset;
1810 * We also track th most recent recorded KHZ, write and time to
1811 * allow the matching interval to be extended at each write.
1813 kvm->arch.last_tsc_nsec = ns;
1814 kvm->arch.last_tsc_write = data;
1815 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1817 vcpu->arch.last_guest_tsc = data;
1819 /* Keep track of which generation this VCPU has synchronized to */
1820 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1821 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1822 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1824 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1825 update_ia32_tsc_adjust_msr(vcpu, offset);
1827 kvm_vcpu_write_tsc_offset(vcpu, offset);
1828 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1830 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1832 kvm->arch.nr_vcpus_matched_tsc = 0;
1833 } else if (!already_matched) {
1834 kvm->arch.nr_vcpus_matched_tsc++;
1837 kvm_track_tsc_matching(vcpu);
1838 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1841 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1843 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1846 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1847 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1850 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1852 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1853 WARN_ON(adjustment < 0);
1854 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1855 adjust_tsc_offset_guest(vcpu, adjustment);
1858 #ifdef CONFIG_X86_64
1860 static u64 read_tsc(void)
1862 u64 ret = (u64)rdtsc_ordered();
1863 u64 last = pvclock_gtod_data.clock.cycle_last;
1865 if (likely(ret >= last))
1869 * GCC likes to generate cmov here, but this branch is extremely
1870 * predictable (it's just a function of time and the likely is
1871 * very likely) and there's a data dependence, so force GCC
1872 * to generate a branch instead. I don't barrier() because
1873 * we don't actually need a barrier, and if this function
1874 * ever gets inlined it will generate worse code.
1880 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1883 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1886 switch (gtod->clock.vclock_mode) {
1887 case VCLOCK_HVCLOCK:
1888 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1890 if (tsc_pg_val != U64_MAX) {
1891 /* TSC page valid */
1892 *mode = VCLOCK_HVCLOCK;
1893 v = (tsc_pg_val - gtod->clock.cycle_last) &
1896 /* TSC page invalid */
1897 *mode = VCLOCK_NONE;
1902 *tsc_timestamp = read_tsc();
1903 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1907 *mode = VCLOCK_NONE;
1910 if (*mode == VCLOCK_NONE)
1911 *tsc_timestamp = v = 0;
1913 return v * gtod->clock.mult;
1916 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1918 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1924 seq = read_seqcount_begin(>od->seq);
1925 ns = gtod->nsec_base;
1926 ns += vgettsc(tsc_timestamp, &mode);
1927 ns >>= gtod->clock.shift;
1928 ns += gtod->boot_ns;
1929 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1935 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1937 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1943 seq = read_seqcount_begin(>od->seq);
1944 ts->tv_sec = gtod->wall_time_sec;
1945 ns = gtod->nsec_base;
1946 ns += vgettsc(tsc_timestamp, &mode);
1947 ns >>= gtod->clock.shift;
1948 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1950 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1956 /* returns true if host is using TSC based clocksource */
1957 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1959 /* checked again under seqlock below */
1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1963 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1967 /* returns true if host is using TSC based clocksource */
1968 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1971 /* checked again under seqlock below */
1972 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1975 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1981 * Assuming a stable TSC across physical CPUS, and a stable TSC
1982 * across virtual CPUs, the following condition is possible.
1983 * Each numbered line represents an event visible to both
1984 * CPUs at the next numbered event.
1986 * "timespecX" represents host monotonic time. "tscX" represents
1989 * VCPU0 on CPU0 | VCPU1 on CPU1
1991 * 1. read timespec0,tsc0
1992 * 2. | timespec1 = timespec0 + N
1994 * 3. transition to guest | transition to guest
1995 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1996 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1997 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1999 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2002 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2004 * - 0 < N - M => M < N
2006 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2007 * always the case (the difference between two distinct xtime instances
2008 * might be smaller then the difference between corresponding TSC reads,
2009 * when updating guest vcpus pvclock areas).
2011 * To avoid that problem, do not allow visibility of distinct
2012 * system_timestamp/tsc_timestamp values simultaneously: use a master
2013 * copy of host monotonic time values. Update that master copy
2016 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2020 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2022 #ifdef CONFIG_X86_64
2023 struct kvm_arch *ka = &kvm->arch;
2025 bool host_tsc_clocksource, vcpus_matched;
2027 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2028 atomic_read(&kvm->online_vcpus));
2031 * If the host uses TSC clock, then passthrough TSC as stable
2034 host_tsc_clocksource = kvm_get_time_and_clockread(
2035 &ka->master_kernel_ns,
2036 &ka->master_cycle_now);
2038 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2039 && !ka->backwards_tsc_observed
2040 && !ka->boot_vcpu_runs_old_kvmclock;
2042 if (ka->use_master_clock)
2043 atomic_set(&kvm_guest_has_master_clock, 1);
2045 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2046 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2051 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2053 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2056 static void kvm_gen_update_masterclock(struct kvm *kvm)
2058 #ifdef CONFIG_X86_64
2060 struct kvm_vcpu *vcpu;
2061 struct kvm_arch *ka = &kvm->arch;
2063 spin_lock(&ka->pvclock_gtod_sync_lock);
2064 kvm_make_mclock_inprogress_request(kvm);
2065 /* no guest entries from this point */
2066 pvclock_update_vm_gtod_copy(kvm);
2068 kvm_for_each_vcpu(i, vcpu, kvm)
2069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2071 /* guest entries allowed */
2072 kvm_for_each_vcpu(i, vcpu, kvm)
2073 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2075 spin_unlock(&ka->pvclock_gtod_sync_lock);
2079 u64 get_kvmclock_ns(struct kvm *kvm)
2081 struct kvm_arch *ka = &kvm->arch;
2082 struct pvclock_vcpu_time_info hv_clock;
2085 spin_lock(&ka->pvclock_gtod_sync_lock);
2086 if (!ka->use_master_clock) {
2087 spin_unlock(&ka->pvclock_gtod_sync_lock);
2088 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2091 hv_clock.tsc_timestamp = ka->master_cycle_now;
2092 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2093 spin_unlock(&ka->pvclock_gtod_sync_lock);
2095 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2098 if (__this_cpu_read(cpu_tsc_khz)) {
2099 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2100 &hv_clock.tsc_shift,
2101 &hv_clock.tsc_to_system_mul);
2102 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2104 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2111 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2113 struct kvm_vcpu_arch *vcpu = &v->arch;
2114 struct pvclock_vcpu_time_info guest_hv_clock;
2116 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2117 &guest_hv_clock, sizeof(guest_hv_clock))))
2120 /* This VCPU is paused, but it's legal for a guest to read another
2121 * VCPU's kvmclock, so we really have to follow the specification where
2122 * it says that version is odd if data is being modified, and even after
2125 * Version field updates must be kept separate. This is because
2126 * kvm_write_guest_cached might use a "rep movs" instruction, and
2127 * writes within a string instruction are weakly ordered. So there
2128 * are three writes overall.
2130 * As a small optimization, only write the version field in the first
2131 * and third write. The vcpu->pv_time cache is still valid, because the
2132 * version field is the first in the struct.
2134 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2136 if (guest_hv_clock.version & 1)
2137 ++guest_hv_clock.version; /* first time write, random junk */
2139 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2140 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2142 sizeof(vcpu->hv_clock.version));
2146 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2147 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2149 if (vcpu->pvclock_set_guest_stopped_request) {
2150 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2151 vcpu->pvclock_set_guest_stopped_request = false;
2154 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2156 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2158 sizeof(vcpu->hv_clock));
2162 vcpu->hv_clock.version++;
2163 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2165 sizeof(vcpu->hv_clock.version));
2168 static int kvm_guest_time_update(struct kvm_vcpu *v)
2170 unsigned long flags, tgt_tsc_khz;
2171 struct kvm_vcpu_arch *vcpu = &v->arch;
2172 struct kvm_arch *ka = &v->kvm->arch;
2174 u64 tsc_timestamp, host_tsc;
2176 bool use_master_clock;
2182 * If the host uses TSC clock, then passthrough TSC as stable
2185 spin_lock(&ka->pvclock_gtod_sync_lock);
2186 use_master_clock = ka->use_master_clock;
2187 if (use_master_clock) {
2188 host_tsc = ka->master_cycle_now;
2189 kernel_ns = ka->master_kernel_ns;
2191 spin_unlock(&ka->pvclock_gtod_sync_lock);
2193 /* Keep irq disabled to prevent changes to the clock */
2194 local_irq_save(flags);
2195 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2196 if (unlikely(tgt_tsc_khz == 0)) {
2197 local_irq_restore(flags);
2198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2201 if (!use_master_clock) {
2203 kernel_ns = ktime_get_boottime_ns();
2206 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2209 * We may have to catch up the TSC to match elapsed wall clock
2210 * time for two reasons, even if kvmclock is used.
2211 * 1) CPU could have been running below the maximum TSC rate
2212 * 2) Broken TSC compensation resets the base at each VCPU
2213 * entry to avoid unknown leaps of TSC even when running
2214 * again on the same CPU. This may cause apparent elapsed
2215 * time to disappear, and the guest to stand still or run
2218 if (vcpu->tsc_catchup) {
2219 u64 tsc = compute_guest_tsc(v, kernel_ns);
2220 if (tsc > tsc_timestamp) {
2221 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2222 tsc_timestamp = tsc;
2226 local_irq_restore(flags);
2228 /* With all the info we got, fill in the values */
2230 if (kvm_has_tsc_control)
2231 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2233 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2234 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2235 &vcpu->hv_clock.tsc_shift,
2236 &vcpu->hv_clock.tsc_to_system_mul);
2237 vcpu->hw_tsc_khz = tgt_tsc_khz;
2240 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2241 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2242 vcpu->last_guest_tsc = tsc_timestamp;
2244 /* If the host uses TSC clocksource, then it is stable */
2246 if (use_master_clock)
2247 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2249 vcpu->hv_clock.flags = pvclock_flags;
2251 if (vcpu->pv_time_enabled)
2252 kvm_setup_pvclock_page(v);
2253 if (v == kvm_get_vcpu(v->kvm, 0))
2254 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2259 * kvmclock updates which are isolated to a given vcpu, such as
2260 * vcpu->cpu migration, should not allow system_timestamp from
2261 * the rest of the vcpus to remain static. Otherwise ntp frequency
2262 * correction applies to one vcpu's system_timestamp but not
2265 * So in those cases, request a kvmclock update for all vcpus.
2266 * We need to rate-limit these requests though, as they can
2267 * considerably slow guests that have a large number of vcpus.
2268 * The time for a remote vcpu to update its kvmclock is bound
2269 * by the delay we use to rate-limit the updates.
2272 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2274 static void kvmclock_update_fn(struct work_struct *work)
2277 struct delayed_work *dwork = to_delayed_work(work);
2278 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2279 kvmclock_update_work);
2280 struct kvm *kvm = container_of(ka, struct kvm, arch);
2281 struct kvm_vcpu *vcpu;
2283 kvm_for_each_vcpu(i, vcpu, kvm) {
2284 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2285 kvm_vcpu_kick(vcpu);
2289 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2291 struct kvm *kvm = v->kvm;
2293 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2294 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2295 KVMCLOCK_UPDATE_DELAY);
2298 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2300 static void kvmclock_sync_fn(struct work_struct *work)
2302 struct delayed_work *dwork = to_delayed_work(work);
2303 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2304 kvmclock_sync_work);
2305 struct kvm *kvm = container_of(ka, struct kvm, arch);
2307 if (!kvmclock_periodic_sync)
2310 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2311 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2312 KVMCLOCK_SYNC_PERIOD);
2316 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2318 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2320 /* McStatusWrEn enabled? */
2321 if (guest_cpuid_is_amd(vcpu))
2322 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2327 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2329 u64 mcg_cap = vcpu->arch.mcg_cap;
2330 unsigned bank_num = mcg_cap & 0xff;
2331 u32 msr = msr_info->index;
2332 u64 data = msr_info->data;
2335 case MSR_IA32_MCG_STATUS:
2336 vcpu->arch.mcg_status = data;
2338 case MSR_IA32_MCG_CTL:
2339 if (!(mcg_cap & MCG_CTL_P) &&
2340 (data || !msr_info->host_initiated))
2342 if (data != 0 && data != ~(u64)0)
2344 vcpu->arch.mcg_ctl = data;
2347 if (msr >= MSR_IA32_MC0_CTL &&
2348 msr < MSR_IA32_MCx_CTL(bank_num)) {
2349 u32 offset = msr - MSR_IA32_MC0_CTL;
2350 /* only 0 or all 1s can be written to IA32_MCi_CTL
2351 * some Linux kernels though clear bit 10 in bank 4 to
2352 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2353 * this to avoid an uncatched #GP in the guest
2355 if ((offset & 0x3) == 0 &&
2356 data != 0 && (data | (1 << 10)) != ~(u64)0)
2360 if (!msr_info->host_initiated &&
2361 (offset & 0x3) == 1 && data != 0) {
2362 if (!can_set_mci_status(vcpu))
2366 vcpu->arch.mce_banks[offset] = data;
2374 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2376 struct kvm *kvm = vcpu->kvm;
2377 int lm = is_long_mode(vcpu);
2378 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2379 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2380 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2381 : kvm->arch.xen_hvm_config.blob_size_32;
2382 u32 page_num = data & ~PAGE_MASK;
2383 u64 page_addr = data & PAGE_MASK;
2388 if (page_num >= blob_size)
2391 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2396 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2405 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2407 gpa_t gpa = data & ~0x3f;
2409 /* Bits 3:5 are reserved, Should be zero */
2413 vcpu->arch.apf.msr_val = data;
2415 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2416 kvm_clear_async_pf_completion_queue(vcpu);
2417 kvm_async_pf_hash_reset(vcpu);
2421 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2425 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2426 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2427 kvm_async_pf_wakeup_all(vcpu);
2431 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2433 vcpu->arch.pv_time_enabled = false;
2436 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2438 ++vcpu->stat.tlb_flush;
2439 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2442 static void record_steal_time(struct kvm_vcpu *vcpu)
2444 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2447 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2448 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2452 * Doing a TLB flush here, on the guest's behalf, can avoid
2455 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2456 kvm_vcpu_flush_tlb(vcpu, false);
2458 if (vcpu->arch.st.steal.version & 1)
2459 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2461 vcpu->arch.st.steal.version += 1;
2463 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2464 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2468 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2469 vcpu->arch.st.last_steal;
2470 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2472 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2473 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2477 vcpu->arch.st.steal.version += 1;
2479 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2480 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2483 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2486 u32 msr = msr_info->index;
2487 u64 data = msr_info->data;
2490 case MSR_AMD64_NB_CFG:
2491 case MSR_IA32_UCODE_WRITE:
2492 case MSR_VM_HSAVE_PA:
2493 case MSR_AMD64_PATCH_LOADER:
2494 case MSR_AMD64_BU_CFG2:
2495 case MSR_AMD64_DC_CFG:
2496 case MSR_F15H_EX_CFG:
2499 case MSR_IA32_UCODE_REV:
2500 if (msr_info->host_initiated)
2501 vcpu->arch.microcode_version = data;
2503 case MSR_IA32_ARCH_CAPABILITIES:
2504 if (!msr_info->host_initiated)
2506 vcpu->arch.arch_capabilities = data;
2509 return set_efer(vcpu, msr_info);
2511 data &= ~(u64)0x40; /* ignore flush filter disable */
2512 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2513 data &= ~(u64)0x8; /* ignore TLB cache disable */
2515 /* Handle McStatusWrEn */
2516 if (data == BIT_ULL(18)) {
2517 vcpu->arch.msr_hwcr = data;
2518 } else if (data != 0) {
2519 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2524 case MSR_FAM10H_MMIO_CONF_BASE:
2526 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2531 case MSR_IA32_DEBUGCTLMSR:
2533 /* We support the non-activated case already */
2535 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2536 /* Values other than LBR and BTF are vendor-specific,
2537 thus reserved and should throw a #GP */
2540 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2543 case 0x200 ... 0x2ff:
2544 return kvm_mtrr_set_msr(vcpu, msr, data);
2545 case MSR_IA32_APICBASE:
2546 return kvm_set_apic_base(vcpu, msr_info);
2547 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2548 return kvm_x2apic_msr_write(vcpu, msr, data);
2549 case MSR_IA32_TSCDEADLINE:
2550 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2552 case MSR_IA32_TSC_ADJUST:
2553 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2554 if (!msr_info->host_initiated) {
2555 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2556 adjust_tsc_offset_guest(vcpu, adj);
2558 vcpu->arch.ia32_tsc_adjust_msr = data;
2561 case MSR_IA32_MISC_ENABLE:
2562 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2563 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2564 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2566 vcpu->arch.ia32_misc_enable_msr = data;
2567 kvm_update_cpuid(vcpu);
2569 vcpu->arch.ia32_misc_enable_msr = data;
2572 case MSR_IA32_SMBASE:
2573 if (!msr_info->host_initiated)
2575 vcpu->arch.smbase = data;
2577 case MSR_IA32_POWER_CTL:
2578 vcpu->arch.msr_ia32_power_ctl = data;
2581 kvm_write_tsc(vcpu, msr_info);
2584 if (!msr_info->host_initiated)
2586 vcpu->arch.smi_count = data;
2588 case MSR_KVM_WALL_CLOCK_NEW:
2589 case MSR_KVM_WALL_CLOCK:
2590 vcpu->kvm->arch.wall_clock = data;
2591 kvm_write_wall_clock(vcpu->kvm, data);
2593 case MSR_KVM_SYSTEM_TIME_NEW:
2594 case MSR_KVM_SYSTEM_TIME: {
2595 struct kvm_arch *ka = &vcpu->kvm->arch;
2597 kvmclock_reset(vcpu);
2599 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2600 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2602 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2603 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2605 ka->boot_vcpu_runs_old_kvmclock = tmp;
2608 vcpu->arch.time = data;
2609 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2611 /* we verify if the enable bit is set... */
2615 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2616 &vcpu->arch.pv_time, data & ~1ULL,
2617 sizeof(struct pvclock_vcpu_time_info)))
2618 vcpu->arch.pv_time_enabled = false;
2620 vcpu->arch.pv_time_enabled = true;
2624 case MSR_KVM_ASYNC_PF_EN:
2625 if (kvm_pv_enable_async_pf(vcpu, data))
2628 case MSR_KVM_STEAL_TIME:
2630 if (unlikely(!sched_info_on()))
2633 if (data & KVM_STEAL_RESERVED_MASK)
2636 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2637 data & KVM_STEAL_VALID_BITS,
2638 sizeof(struct kvm_steal_time)))
2641 vcpu->arch.st.msr_val = data;
2643 if (!(data & KVM_MSR_ENABLED))
2646 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2649 case MSR_KVM_PV_EOI_EN:
2650 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2654 case MSR_KVM_POLL_CONTROL:
2655 /* only enable bit supported */
2656 if (data & (-1ULL << 1))
2659 vcpu->arch.msr_kvm_poll_control = data;
2662 case MSR_IA32_MCG_CTL:
2663 case MSR_IA32_MCG_STATUS:
2664 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2665 return set_msr_mce(vcpu, msr_info);
2667 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2668 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2669 pr = true; /* fall through */
2670 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2671 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2672 if (kvm_pmu_is_valid_msr(vcpu, msr))
2673 return kvm_pmu_set_msr(vcpu, msr_info);
2675 if (pr || data != 0)
2676 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2677 "0x%x data 0x%llx\n", msr, data);
2679 case MSR_K7_CLK_CTL:
2681 * Ignore all writes to this no longer documented MSR.
2682 * Writes are only relevant for old K7 processors,
2683 * all pre-dating SVM, but a recommended workaround from
2684 * AMD for these chips. It is possible to specify the
2685 * affected processor models on the command line, hence
2686 * the need to ignore the workaround.
2689 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2690 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2691 case HV_X64_MSR_CRASH_CTL:
2692 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2693 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2694 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2695 case HV_X64_MSR_TSC_EMULATION_STATUS:
2696 return kvm_hv_set_msr_common(vcpu, msr, data,
2697 msr_info->host_initiated);
2698 case MSR_IA32_BBL_CR_CTL3:
2699 /* Drop writes to this legacy MSR -- see rdmsr
2700 * counterpart for further detail.
2702 if (report_ignored_msrs)
2703 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2706 case MSR_AMD64_OSVW_ID_LENGTH:
2707 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2709 vcpu->arch.osvw.length = data;
2711 case MSR_AMD64_OSVW_STATUS:
2712 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2714 vcpu->arch.osvw.status = data;
2716 case MSR_PLATFORM_INFO:
2717 if (!msr_info->host_initiated ||
2718 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2719 cpuid_fault_enabled(vcpu)))
2721 vcpu->arch.msr_platform_info = data;
2723 case MSR_MISC_FEATURES_ENABLES:
2724 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2725 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2726 !supports_cpuid_fault(vcpu)))
2728 vcpu->arch.msr_misc_features_enables = data;
2731 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2732 return xen_hvm_config(vcpu, data);
2733 if (kvm_pmu_is_valid_msr(vcpu, msr))
2734 return kvm_pmu_set_msr(vcpu, msr_info);
2736 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2740 if (report_ignored_msrs)
2742 "ignored wrmsr: 0x%x data 0x%llx\n",
2749 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2753 * Reads an msr value (of 'msr_index') into 'pdata'.
2754 * Returns 0 on success, non-0 otherwise.
2755 * Assumes vcpu_load() was already called.
2757 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2759 return kvm_x86_ops->get_msr(vcpu, msr);
2761 EXPORT_SYMBOL_GPL(kvm_get_msr);
2763 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2766 u64 mcg_cap = vcpu->arch.mcg_cap;
2767 unsigned bank_num = mcg_cap & 0xff;
2770 case MSR_IA32_P5_MC_ADDR:
2771 case MSR_IA32_P5_MC_TYPE:
2774 case MSR_IA32_MCG_CAP:
2775 data = vcpu->arch.mcg_cap;
2777 case MSR_IA32_MCG_CTL:
2778 if (!(mcg_cap & MCG_CTL_P) && !host)
2780 data = vcpu->arch.mcg_ctl;
2782 case MSR_IA32_MCG_STATUS:
2783 data = vcpu->arch.mcg_status;
2786 if (msr >= MSR_IA32_MC0_CTL &&
2787 msr < MSR_IA32_MCx_CTL(bank_num)) {
2788 u32 offset = msr - MSR_IA32_MC0_CTL;
2789 data = vcpu->arch.mce_banks[offset];
2798 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2800 switch (msr_info->index) {
2801 case MSR_IA32_PLATFORM_ID:
2802 case MSR_IA32_EBL_CR_POWERON:
2803 case MSR_IA32_DEBUGCTLMSR:
2804 case MSR_IA32_LASTBRANCHFROMIP:
2805 case MSR_IA32_LASTBRANCHTOIP:
2806 case MSR_IA32_LASTINTFROMIP:
2807 case MSR_IA32_LASTINTTOIP:
2809 case MSR_K8_TSEG_ADDR:
2810 case MSR_K8_TSEG_MASK:
2811 case MSR_VM_HSAVE_PA:
2812 case MSR_K8_INT_PENDING_MSG:
2813 case MSR_AMD64_NB_CFG:
2814 case MSR_FAM10H_MMIO_CONF_BASE:
2815 case MSR_AMD64_BU_CFG2:
2816 case MSR_IA32_PERF_CTL:
2817 case MSR_AMD64_DC_CFG:
2818 case MSR_F15H_EX_CFG:
2821 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2822 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2823 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2824 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2825 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2826 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2827 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2830 case MSR_IA32_UCODE_REV:
2831 msr_info->data = vcpu->arch.microcode_version;
2833 case MSR_IA32_ARCH_CAPABILITIES:
2834 if (!msr_info->host_initiated &&
2835 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2837 msr_info->data = vcpu->arch.arch_capabilities;
2839 case MSR_IA32_POWER_CTL:
2840 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2843 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2846 case 0x200 ... 0x2ff:
2847 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2848 case 0xcd: /* fsb frequency */
2852 * MSR_EBC_FREQUENCY_ID
2853 * Conservative value valid for even the basic CPU models.
2854 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2855 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2856 * and 266MHz for model 3, or 4. Set Core Clock
2857 * Frequency to System Bus Frequency Ratio to 1 (bits
2858 * 31:24) even though these are only valid for CPU
2859 * models > 2, however guests may end up dividing or
2860 * multiplying by zero otherwise.
2862 case MSR_EBC_FREQUENCY_ID:
2863 msr_info->data = 1 << 24;
2865 case MSR_IA32_APICBASE:
2866 msr_info->data = kvm_get_apic_base(vcpu);
2868 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2869 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2871 case MSR_IA32_TSCDEADLINE:
2872 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2874 case MSR_IA32_TSC_ADJUST:
2875 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2877 case MSR_IA32_MISC_ENABLE:
2878 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2880 case MSR_IA32_SMBASE:
2881 if (!msr_info->host_initiated)
2883 msr_info->data = vcpu->arch.smbase;
2886 msr_info->data = vcpu->arch.smi_count;
2888 case MSR_IA32_PERF_STATUS:
2889 /* TSC increment by tick */
2890 msr_info->data = 1000ULL;
2891 /* CPU multiplier */
2892 msr_info->data |= (((uint64_t)4ULL) << 40);
2895 msr_info->data = vcpu->arch.efer;
2897 case MSR_KVM_WALL_CLOCK:
2898 case MSR_KVM_WALL_CLOCK_NEW:
2899 msr_info->data = vcpu->kvm->arch.wall_clock;
2901 case MSR_KVM_SYSTEM_TIME:
2902 case MSR_KVM_SYSTEM_TIME_NEW:
2903 msr_info->data = vcpu->arch.time;
2905 case MSR_KVM_ASYNC_PF_EN:
2906 msr_info->data = vcpu->arch.apf.msr_val;
2908 case MSR_KVM_STEAL_TIME:
2909 msr_info->data = vcpu->arch.st.msr_val;
2911 case MSR_KVM_PV_EOI_EN:
2912 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2914 case MSR_KVM_POLL_CONTROL:
2915 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2917 case MSR_IA32_P5_MC_ADDR:
2918 case MSR_IA32_P5_MC_TYPE:
2919 case MSR_IA32_MCG_CAP:
2920 case MSR_IA32_MCG_CTL:
2921 case MSR_IA32_MCG_STATUS:
2922 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2923 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2924 msr_info->host_initiated);
2925 case MSR_K7_CLK_CTL:
2927 * Provide expected ramp-up count for K7. All other
2928 * are set to zero, indicating minimum divisors for
2931 * This prevents guest kernels on AMD host with CPU
2932 * type 6, model 8 and higher from exploding due to
2933 * the rdmsr failing.
2935 msr_info->data = 0x20000000;
2937 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2938 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2939 case HV_X64_MSR_CRASH_CTL:
2940 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2941 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2942 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2943 case HV_X64_MSR_TSC_EMULATION_STATUS:
2944 return kvm_hv_get_msr_common(vcpu,
2945 msr_info->index, &msr_info->data,
2946 msr_info->host_initiated);
2948 case MSR_IA32_BBL_CR_CTL3:
2949 /* This legacy MSR exists but isn't fully documented in current
2950 * silicon. It is however accessed by winxp in very narrow
2951 * scenarios where it sets bit #19, itself documented as
2952 * a "reserved" bit. Best effort attempt to source coherent
2953 * read data here should the balance of the register be
2954 * interpreted by the guest:
2956 * L2 cache control register 3: 64GB range, 256KB size,
2957 * enabled, latency 0x1, configured
2959 msr_info->data = 0xbe702111;
2961 case MSR_AMD64_OSVW_ID_LENGTH:
2962 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2964 msr_info->data = vcpu->arch.osvw.length;
2966 case MSR_AMD64_OSVW_STATUS:
2967 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2969 msr_info->data = vcpu->arch.osvw.status;
2971 case MSR_PLATFORM_INFO:
2972 if (!msr_info->host_initiated &&
2973 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2975 msr_info->data = vcpu->arch.msr_platform_info;
2977 case MSR_MISC_FEATURES_ENABLES:
2978 msr_info->data = vcpu->arch.msr_misc_features_enables;
2981 msr_info->data = vcpu->arch.msr_hwcr;
2984 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2985 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2987 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2991 if (report_ignored_msrs)
2992 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3000 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3003 * Read or write a bunch of msrs. All parameters are kernel addresses.
3005 * @return number of msrs set successfully.
3007 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3008 struct kvm_msr_entry *entries,
3009 int (*do_msr)(struct kvm_vcpu *vcpu,
3010 unsigned index, u64 *data))
3014 for (i = 0; i < msrs->nmsrs; ++i)
3015 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3022 * Read or write a bunch of msrs. Parameters are user addresses.
3024 * @return number of msrs set successfully.
3026 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3027 int (*do_msr)(struct kvm_vcpu *vcpu,
3028 unsigned index, u64 *data),
3031 struct kvm_msrs msrs;
3032 struct kvm_msr_entry *entries;
3037 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3041 if (msrs.nmsrs >= MAX_IO_MSRS)
3044 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3045 entries = memdup_user(user_msrs->entries, size);
3046 if (IS_ERR(entries)) {
3047 r = PTR_ERR(entries);
3051 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3056 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3067 static inline bool kvm_can_mwait_in_guest(void)
3069 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3070 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3071 boot_cpu_has(X86_FEATURE_ARAT);
3074 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3079 case KVM_CAP_IRQCHIP:
3081 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3082 case KVM_CAP_SET_TSS_ADDR:
3083 case KVM_CAP_EXT_CPUID:
3084 case KVM_CAP_EXT_EMUL_CPUID:
3085 case KVM_CAP_CLOCKSOURCE:
3087 case KVM_CAP_NOP_IO_DELAY:
3088 case KVM_CAP_MP_STATE:
3089 case KVM_CAP_SYNC_MMU:
3090 case KVM_CAP_USER_NMI:
3091 case KVM_CAP_REINJECT_CONTROL:
3092 case KVM_CAP_IRQ_INJECT_STATUS:
3093 case KVM_CAP_IOEVENTFD:
3094 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3096 case KVM_CAP_PIT_STATE2:
3097 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3098 case KVM_CAP_XEN_HVM:
3099 case KVM_CAP_VCPU_EVENTS:
3100 case KVM_CAP_HYPERV:
3101 case KVM_CAP_HYPERV_VAPIC:
3102 case KVM_CAP_HYPERV_SPIN:
3103 case KVM_CAP_HYPERV_SYNIC:
3104 case KVM_CAP_HYPERV_SYNIC2:
3105 case KVM_CAP_HYPERV_VP_INDEX:
3106 case KVM_CAP_HYPERV_EVENTFD:
3107 case KVM_CAP_HYPERV_TLBFLUSH:
3108 case KVM_CAP_HYPERV_SEND_IPI:
3109 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3110 case KVM_CAP_HYPERV_CPUID:
3111 case KVM_CAP_PCI_SEGMENT:
3112 case KVM_CAP_DEBUGREGS:
3113 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3115 case KVM_CAP_ASYNC_PF:
3116 case KVM_CAP_GET_TSC_KHZ:
3117 case KVM_CAP_KVMCLOCK_CTRL:
3118 case KVM_CAP_READONLY_MEM:
3119 case KVM_CAP_HYPERV_TIME:
3120 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3121 case KVM_CAP_TSC_DEADLINE_TIMER:
3122 case KVM_CAP_DISABLE_QUIRKS:
3123 case KVM_CAP_SET_BOOT_CPU_ID:
3124 case KVM_CAP_SPLIT_IRQCHIP:
3125 case KVM_CAP_IMMEDIATE_EXIT:
3126 case KVM_CAP_PMU_EVENT_FILTER:
3127 case KVM_CAP_GET_MSR_FEATURES:
3128 case KVM_CAP_MSR_PLATFORM_INFO:
3129 case KVM_CAP_EXCEPTION_PAYLOAD:
3132 case KVM_CAP_SYNC_REGS:
3133 r = KVM_SYNC_X86_VALID_FIELDS;
3135 case KVM_CAP_ADJUST_CLOCK:
3136 r = KVM_CLOCK_TSC_STABLE;
3138 case KVM_CAP_X86_DISABLE_EXITS:
3139 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3140 KVM_X86_DISABLE_EXITS_CSTATE;
3141 if(kvm_can_mwait_in_guest())
3142 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3144 case KVM_CAP_X86_SMM:
3145 /* SMBASE is usually relocated above 1M on modern chipsets,
3146 * and SMM handlers might indeed rely on 4G segment limits,
3147 * so do not report SMM to be available if real mode is
3148 * emulated via vm86 mode. Still, do not go to great lengths
3149 * to avoid userspace's usage of the feature, because it is a
3150 * fringe case that is not enabled except via specific settings
3151 * of the module parameters.
3153 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3156 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3158 case KVM_CAP_NR_VCPUS:
3159 r = KVM_SOFT_MAX_VCPUS;
3161 case KVM_CAP_MAX_VCPUS:
3164 case KVM_CAP_MAX_VCPU_ID:
3165 r = KVM_MAX_VCPU_ID;
3167 case KVM_CAP_PV_MMU: /* obsolete */
3171 r = KVM_MAX_MCE_BANKS;
3174 r = boot_cpu_has(X86_FEATURE_XSAVE);
3176 case KVM_CAP_TSC_CONTROL:
3177 r = kvm_has_tsc_control;
3179 case KVM_CAP_X2APIC_API:
3180 r = KVM_X2APIC_API_VALID_FLAGS;
3182 case KVM_CAP_NESTED_STATE:
3183 r = kvm_x86_ops->get_nested_state ?
3184 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3193 long kvm_arch_dev_ioctl(struct file *filp,
3194 unsigned int ioctl, unsigned long arg)
3196 void __user *argp = (void __user *)arg;
3200 case KVM_GET_MSR_INDEX_LIST: {
3201 struct kvm_msr_list __user *user_msr_list = argp;
3202 struct kvm_msr_list msr_list;
3206 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3209 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3210 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3213 if (n < msr_list.nmsrs)
3216 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3217 num_msrs_to_save * sizeof(u32)))
3219 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3221 num_emulated_msrs * sizeof(u32)))
3226 case KVM_GET_SUPPORTED_CPUID:
3227 case KVM_GET_EMULATED_CPUID: {
3228 struct kvm_cpuid2 __user *cpuid_arg = argp;
3229 struct kvm_cpuid2 cpuid;
3232 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3235 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3246 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3248 if (copy_to_user(argp, &kvm_mce_cap_supported,
3249 sizeof(kvm_mce_cap_supported)))
3253 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3254 struct kvm_msr_list __user *user_msr_list = argp;
3255 struct kvm_msr_list msr_list;
3259 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3262 msr_list.nmsrs = num_msr_based_features;
3263 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3266 if (n < msr_list.nmsrs)
3269 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3270 num_msr_based_features * sizeof(u32)))
3276 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3286 static void wbinvd_ipi(void *garbage)
3291 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3293 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3296 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3298 /* Address WBINVD may be executed by guest */
3299 if (need_emulate_wbinvd(vcpu)) {
3300 if (kvm_x86_ops->has_wbinvd_exit())
3301 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3302 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3303 smp_call_function_single(vcpu->cpu,
3304 wbinvd_ipi, NULL, 1);
3307 kvm_x86_ops->vcpu_load(vcpu, cpu);
3309 fpregs_assert_state_consistent();
3310 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3311 switch_fpu_return();
3313 /* Apply any externally detected TSC adjustments (due to suspend) */
3314 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3315 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3316 vcpu->arch.tsc_offset_adjustment = 0;
3317 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3320 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3321 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3322 rdtsc() - vcpu->arch.last_host_tsc;
3324 mark_tsc_unstable("KVM discovered backwards TSC");
3326 if (kvm_check_tsc_unstable()) {
3327 u64 offset = kvm_compute_tsc_offset(vcpu,
3328 vcpu->arch.last_guest_tsc);
3329 kvm_vcpu_write_tsc_offset(vcpu, offset);
3330 vcpu->arch.tsc_catchup = 1;
3333 if (kvm_lapic_hv_timer_in_use(vcpu))
3334 kvm_lapic_restart_hv_timer(vcpu);
3337 * On a host with synchronized TSC, there is no need to update
3338 * kvmclock on vcpu->cpu migration
3340 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3341 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3342 if (vcpu->cpu != cpu)
3343 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3347 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3350 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3352 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3355 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3357 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3358 &vcpu->arch.st.steal.preempted,
3359 offsetof(struct kvm_steal_time, preempted),
3360 sizeof(vcpu->arch.st.steal.preempted));
3363 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3367 if (vcpu->preempted)
3368 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3371 * Disable page faults because we're in atomic context here.
3372 * kvm_write_guest_offset_cached() would call might_fault()
3373 * that relies on pagefault_disable() to tell if there's a
3374 * bug. NOTE: the write to guest memory may not go through if
3375 * during postcopy live migration or if there's heavy guest
3378 pagefault_disable();
3380 * kvm_memslots() will be called by
3381 * kvm_write_guest_offset_cached() so take the srcu lock.
3383 idx = srcu_read_lock(&vcpu->kvm->srcu);
3384 kvm_steal_time_set_preempted(vcpu);
3385 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3387 kvm_x86_ops->vcpu_put(vcpu);
3388 vcpu->arch.last_host_tsc = rdtsc();
3390 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3391 * on every vmexit, but if not, we might have a stale dr6 from the
3392 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3397 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3398 struct kvm_lapic_state *s)
3400 if (vcpu->arch.apicv_active)
3401 kvm_x86_ops->sync_pir_to_irr(vcpu);
3403 return kvm_apic_get_state(vcpu, s);
3406 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3407 struct kvm_lapic_state *s)
3411 r = kvm_apic_set_state(vcpu, s);
3414 update_cr8_intercept(vcpu);
3419 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3421 return (!lapic_in_kernel(vcpu) ||
3422 kvm_apic_accept_pic_intr(vcpu));
3426 * if userspace requested an interrupt window, check that the
3427 * interrupt window is open.
3429 * No need to exit to userspace if we already have an interrupt queued.
3431 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3433 return kvm_arch_interrupt_allowed(vcpu) &&
3434 !kvm_cpu_has_interrupt(vcpu) &&
3435 !kvm_event_needs_reinjection(vcpu) &&
3436 kvm_cpu_accept_dm_intr(vcpu);
3439 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3440 struct kvm_interrupt *irq)
3442 if (irq->irq >= KVM_NR_INTERRUPTS)
3445 if (!irqchip_in_kernel(vcpu->kvm)) {
3446 kvm_queue_interrupt(vcpu, irq->irq, false);
3447 kvm_make_request(KVM_REQ_EVENT, vcpu);
3452 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3453 * fail for in-kernel 8259.
3455 if (pic_in_kernel(vcpu->kvm))
3458 if (vcpu->arch.pending_external_vector != -1)
3461 vcpu->arch.pending_external_vector = irq->irq;
3462 kvm_make_request(KVM_REQ_EVENT, vcpu);
3466 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3468 kvm_inject_nmi(vcpu);
3473 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3475 kvm_make_request(KVM_REQ_SMI, vcpu);
3480 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3481 struct kvm_tpr_access_ctl *tac)
3485 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3489 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3493 unsigned bank_num = mcg_cap & 0xff, bank;
3496 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3498 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3501 vcpu->arch.mcg_cap = mcg_cap;
3502 /* Init IA32_MCG_CTL to all 1s */
3503 if (mcg_cap & MCG_CTL_P)
3504 vcpu->arch.mcg_ctl = ~(u64)0;
3505 /* Init IA32_MCi_CTL to all 1s */
3506 for (bank = 0; bank < bank_num; bank++)
3507 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3509 if (kvm_x86_ops->setup_mce)
3510 kvm_x86_ops->setup_mce(vcpu);
3515 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3516 struct kvm_x86_mce *mce)
3518 u64 mcg_cap = vcpu->arch.mcg_cap;
3519 unsigned bank_num = mcg_cap & 0xff;
3520 u64 *banks = vcpu->arch.mce_banks;
3522 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3525 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3526 * reporting is disabled
3528 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3529 vcpu->arch.mcg_ctl != ~(u64)0)
3531 banks += 4 * mce->bank;
3533 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3534 * reporting is disabled for the bank
3536 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3538 if (mce->status & MCI_STATUS_UC) {
3539 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3540 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3541 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3544 if (banks[1] & MCI_STATUS_VAL)
3545 mce->status |= MCI_STATUS_OVER;
3546 banks[2] = mce->addr;
3547 banks[3] = mce->misc;
3548 vcpu->arch.mcg_status = mce->mcg_status;
3549 banks[1] = mce->status;
3550 kvm_queue_exception(vcpu, MC_VECTOR);
3551 } else if (!(banks[1] & MCI_STATUS_VAL)
3552 || !(banks[1] & MCI_STATUS_UC)) {
3553 if (banks[1] & MCI_STATUS_VAL)
3554 mce->status |= MCI_STATUS_OVER;
3555 banks[2] = mce->addr;
3556 banks[3] = mce->misc;
3557 banks[1] = mce->status;
3559 banks[1] |= MCI_STATUS_OVER;
3563 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3564 struct kvm_vcpu_events *events)
3569 * The API doesn't provide the instruction length for software
3570 * exceptions, so don't report them. As long as the guest RIP
3571 * isn't advanced, we should expect to encounter the exception
3574 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3575 events->exception.injected = 0;
3576 events->exception.pending = 0;
3578 events->exception.injected = vcpu->arch.exception.injected;
3579 events->exception.pending = vcpu->arch.exception.pending;
3581 * For ABI compatibility, deliberately conflate
3582 * pending and injected exceptions when
3583 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3585 if (!vcpu->kvm->arch.exception_payload_enabled)
3586 events->exception.injected |=
3587 vcpu->arch.exception.pending;
3589 events->exception.nr = vcpu->arch.exception.nr;
3590 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3591 events->exception.error_code = vcpu->arch.exception.error_code;
3592 events->exception_has_payload = vcpu->arch.exception.has_payload;
3593 events->exception_payload = vcpu->arch.exception.payload;
3595 events->interrupt.injected =
3596 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3597 events->interrupt.nr = vcpu->arch.interrupt.nr;
3598 events->interrupt.soft = 0;
3599 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3601 events->nmi.injected = vcpu->arch.nmi_injected;
3602 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3603 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3604 events->nmi.pad = 0;
3606 events->sipi_vector = 0; /* never valid when reporting to user space */
3608 events->smi.smm = is_smm(vcpu);
3609 events->smi.pending = vcpu->arch.smi_pending;
3610 events->smi.smm_inside_nmi =
3611 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3612 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3614 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3615 | KVM_VCPUEVENT_VALID_SHADOW
3616 | KVM_VCPUEVENT_VALID_SMM);
3617 if (vcpu->kvm->arch.exception_payload_enabled)
3618 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3620 memset(&events->reserved, 0, sizeof(events->reserved));
3623 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3625 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3626 struct kvm_vcpu_events *events)
3628 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3629 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3630 | KVM_VCPUEVENT_VALID_SHADOW
3631 | KVM_VCPUEVENT_VALID_SMM
3632 | KVM_VCPUEVENT_VALID_PAYLOAD))
3635 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3636 if (!vcpu->kvm->arch.exception_payload_enabled)
3638 if (events->exception.pending)
3639 events->exception.injected = 0;
3641 events->exception_has_payload = 0;
3643 events->exception.pending = 0;
3644 events->exception_has_payload = 0;
3647 if ((events->exception.injected || events->exception.pending) &&
3648 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3651 /* INITs are latched while in SMM */
3652 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3653 (events->smi.smm || events->smi.pending) &&
3654 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3658 vcpu->arch.exception.injected = events->exception.injected;
3659 vcpu->arch.exception.pending = events->exception.pending;
3660 vcpu->arch.exception.nr = events->exception.nr;
3661 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3662 vcpu->arch.exception.error_code = events->exception.error_code;
3663 vcpu->arch.exception.has_payload = events->exception_has_payload;
3664 vcpu->arch.exception.payload = events->exception_payload;
3666 vcpu->arch.interrupt.injected = events->interrupt.injected;
3667 vcpu->arch.interrupt.nr = events->interrupt.nr;
3668 vcpu->arch.interrupt.soft = events->interrupt.soft;
3669 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3670 kvm_x86_ops->set_interrupt_shadow(vcpu,
3671 events->interrupt.shadow);
3673 vcpu->arch.nmi_injected = events->nmi.injected;
3674 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3675 vcpu->arch.nmi_pending = events->nmi.pending;
3676 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3678 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3679 lapic_in_kernel(vcpu))
3680 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3682 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3683 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3684 if (events->smi.smm)
3685 vcpu->arch.hflags |= HF_SMM_MASK;
3687 vcpu->arch.hflags &= ~HF_SMM_MASK;
3688 kvm_smm_changed(vcpu);
3691 vcpu->arch.smi_pending = events->smi.pending;
3693 if (events->smi.smm) {
3694 if (events->smi.smm_inside_nmi)
3695 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3697 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3698 if (lapic_in_kernel(vcpu)) {
3699 if (events->smi.latched_init)
3700 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3702 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3707 kvm_make_request(KVM_REQ_EVENT, vcpu);
3712 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3713 struct kvm_debugregs *dbgregs)
3717 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3718 kvm_get_dr(vcpu, 6, &val);
3720 dbgregs->dr7 = vcpu->arch.dr7;
3722 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3725 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3726 struct kvm_debugregs *dbgregs)
3731 if (dbgregs->dr6 & ~0xffffffffull)
3733 if (dbgregs->dr7 & ~0xffffffffull)
3736 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3737 kvm_update_dr0123(vcpu);
3738 vcpu->arch.dr6 = dbgregs->dr6;
3739 kvm_update_dr6(vcpu);
3740 vcpu->arch.dr7 = dbgregs->dr7;
3741 kvm_update_dr7(vcpu);
3746 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3748 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3750 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3751 u64 xstate_bv = xsave->header.xfeatures;
3755 * Copy legacy XSAVE area, to avoid complications with CPUID
3756 * leaves 0 and 1 in the loop below.
3758 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3761 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3762 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3765 * Copy each region from the possibly compacted offset to the
3766 * non-compacted offset.
3768 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3770 u64 xfeature_mask = valid & -valid;
3771 int xfeature_nr = fls64(xfeature_mask) - 1;
3772 void *src = get_xsave_addr(xsave, xfeature_nr);
3775 u32 size, offset, ecx, edx;
3776 cpuid_count(XSTATE_CPUID, xfeature_nr,
3777 &size, &offset, &ecx, &edx);
3778 if (xfeature_nr == XFEATURE_PKRU)
3779 memcpy(dest + offset, &vcpu->arch.pkru,
3780 sizeof(vcpu->arch.pkru));
3782 memcpy(dest + offset, src, size);
3786 valid -= xfeature_mask;
3790 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3792 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3793 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3797 * Copy legacy XSAVE area, to avoid complications with CPUID
3798 * leaves 0 and 1 in the loop below.
3800 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3802 /* Set XSTATE_BV and possibly XCOMP_BV. */
3803 xsave->header.xfeatures = xstate_bv;
3804 if (boot_cpu_has(X86_FEATURE_XSAVES))
3805 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3808 * Copy each region from the non-compacted offset to the
3809 * possibly compacted offset.
3811 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3813 u64 xfeature_mask = valid & -valid;
3814 int xfeature_nr = fls64(xfeature_mask) - 1;
3815 void *dest = get_xsave_addr(xsave, xfeature_nr);
3818 u32 size, offset, ecx, edx;
3819 cpuid_count(XSTATE_CPUID, xfeature_nr,
3820 &size, &offset, &ecx, &edx);
3821 if (xfeature_nr == XFEATURE_PKRU)
3822 memcpy(&vcpu->arch.pkru, src + offset,
3823 sizeof(vcpu->arch.pkru));
3825 memcpy(dest, src + offset, size);
3828 valid -= xfeature_mask;
3832 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3833 struct kvm_xsave *guest_xsave)
3835 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3836 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3837 fill_xsave((u8 *) guest_xsave->region, vcpu);
3839 memcpy(guest_xsave->region,
3840 &vcpu->arch.guest_fpu->state.fxsave,
3841 sizeof(struct fxregs_state));
3842 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3843 XFEATURE_MASK_FPSSE;
3847 #define XSAVE_MXCSR_OFFSET 24
3849 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3850 struct kvm_xsave *guest_xsave)
3853 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3854 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3856 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3858 * Here we allow setting states that are not present in
3859 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3860 * with old userspace.
3862 if (xstate_bv & ~kvm_supported_xcr0() ||
3863 mxcsr & ~mxcsr_feature_mask)
3865 load_xsave(vcpu, (u8 *)guest_xsave->region);
3867 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3868 mxcsr & ~mxcsr_feature_mask)
3870 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3871 guest_xsave->region, sizeof(struct fxregs_state));
3876 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3877 struct kvm_xcrs *guest_xcrs)
3879 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3880 guest_xcrs->nr_xcrs = 0;
3884 guest_xcrs->nr_xcrs = 1;
3885 guest_xcrs->flags = 0;
3886 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3887 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3890 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3891 struct kvm_xcrs *guest_xcrs)
3895 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3898 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3901 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3902 /* Only support XCR0 currently */
3903 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3904 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3905 guest_xcrs->xcrs[i].value);
3914 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3915 * stopped by the hypervisor. This function will be called from the host only.
3916 * EINVAL is returned when the host attempts to set the flag for a guest that
3917 * does not support pv clocks.
3919 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3921 if (!vcpu->arch.pv_time_enabled)
3923 vcpu->arch.pvclock_set_guest_stopped_request = true;
3924 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3928 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3929 struct kvm_enable_cap *cap)
3932 uint16_t vmcs_version;
3933 void __user *user_ptr;
3939 case KVM_CAP_HYPERV_SYNIC2:
3944 case KVM_CAP_HYPERV_SYNIC:
3945 if (!irqchip_in_kernel(vcpu->kvm))
3947 return kvm_hv_activate_synic(vcpu, cap->cap ==
3948 KVM_CAP_HYPERV_SYNIC2);
3949 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3950 if (!kvm_x86_ops->nested_enable_evmcs)
3952 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3954 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3955 if (copy_to_user(user_ptr, &vmcs_version,
3956 sizeof(vmcs_version)))
3966 long kvm_arch_vcpu_ioctl(struct file *filp,
3967 unsigned int ioctl, unsigned long arg)
3969 struct kvm_vcpu *vcpu = filp->private_data;
3970 void __user *argp = (void __user *)arg;
3973 struct kvm_lapic_state *lapic;
3974 struct kvm_xsave *xsave;
3975 struct kvm_xcrs *xcrs;
3983 case KVM_GET_LAPIC: {
3985 if (!lapic_in_kernel(vcpu))
3987 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3988 GFP_KERNEL_ACCOUNT);
3993 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3997 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4002 case KVM_SET_LAPIC: {
4004 if (!lapic_in_kernel(vcpu))
4006 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4007 if (IS_ERR(u.lapic)) {
4008 r = PTR_ERR(u.lapic);
4012 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4015 case KVM_INTERRUPT: {
4016 struct kvm_interrupt irq;
4019 if (copy_from_user(&irq, argp, sizeof(irq)))
4021 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4025 r = kvm_vcpu_ioctl_nmi(vcpu);
4029 r = kvm_vcpu_ioctl_smi(vcpu);
4032 case KVM_SET_CPUID: {
4033 struct kvm_cpuid __user *cpuid_arg = argp;
4034 struct kvm_cpuid cpuid;
4037 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4039 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4042 case KVM_SET_CPUID2: {
4043 struct kvm_cpuid2 __user *cpuid_arg = argp;
4044 struct kvm_cpuid2 cpuid;
4047 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4049 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4050 cpuid_arg->entries);
4053 case KVM_GET_CPUID2: {
4054 struct kvm_cpuid2 __user *cpuid_arg = argp;
4055 struct kvm_cpuid2 cpuid;
4058 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4060 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4061 cpuid_arg->entries);
4065 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4070 case KVM_GET_MSRS: {
4071 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4072 r = msr_io(vcpu, argp, do_get_msr, 1);
4073 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4076 case KVM_SET_MSRS: {
4077 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4078 r = msr_io(vcpu, argp, do_set_msr, 0);
4079 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4082 case KVM_TPR_ACCESS_REPORTING: {
4083 struct kvm_tpr_access_ctl tac;
4086 if (copy_from_user(&tac, argp, sizeof(tac)))
4088 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4092 if (copy_to_user(argp, &tac, sizeof(tac)))
4097 case KVM_SET_VAPIC_ADDR: {
4098 struct kvm_vapic_addr va;
4102 if (!lapic_in_kernel(vcpu))
4105 if (copy_from_user(&va, argp, sizeof(va)))
4107 idx = srcu_read_lock(&vcpu->kvm->srcu);
4108 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4109 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4112 case KVM_X86_SETUP_MCE: {
4116 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4118 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4121 case KVM_X86_SET_MCE: {
4122 struct kvm_x86_mce mce;
4125 if (copy_from_user(&mce, argp, sizeof(mce)))
4127 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4130 case KVM_GET_VCPU_EVENTS: {
4131 struct kvm_vcpu_events events;
4133 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4136 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4141 case KVM_SET_VCPU_EVENTS: {
4142 struct kvm_vcpu_events events;
4145 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4148 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4151 case KVM_GET_DEBUGREGS: {
4152 struct kvm_debugregs dbgregs;
4154 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4157 if (copy_to_user(argp, &dbgregs,
4158 sizeof(struct kvm_debugregs)))
4163 case KVM_SET_DEBUGREGS: {
4164 struct kvm_debugregs dbgregs;
4167 if (copy_from_user(&dbgregs, argp,
4168 sizeof(struct kvm_debugregs)))
4171 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4174 case KVM_GET_XSAVE: {
4175 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4180 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4183 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4188 case KVM_SET_XSAVE: {
4189 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4190 if (IS_ERR(u.xsave)) {
4191 r = PTR_ERR(u.xsave);
4195 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4198 case KVM_GET_XCRS: {
4199 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4204 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4207 if (copy_to_user(argp, u.xcrs,
4208 sizeof(struct kvm_xcrs)))
4213 case KVM_SET_XCRS: {
4214 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4215 if (IS_ERR(u.xcrs)) {
4216 r = PTR_ERR(u.xcrs);
4220 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4223 case KVM_SET_TSC_KHZ: {
4227 user_tsc_khz = (u32)arg;
4229 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4232 if (user_tsc_khz == 0)
4233 user_tsc_khz = tsc_khz;
4235 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4240 case KVM_GET_TSC_KHZ: {
4241 r = vcpu->arch.virtual_tsc_khz;
4244 case KVM_KVMCLOCK_CTRL: {
4245 r = kvm_set_guest_paused(vcpu);
4248 case KVM_ENABLE_CAP: {
4249 struct kvm_enable_cap cap;
4252 if (copy_from_user(&cap, argp, sizeof(cap)))
4254 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4257 case KVM_GET_NESTED_STATE: {
4258 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4262 if (!kvm_x86_ops->get_nested_state)
4265 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4267 if (get_user(user_data_size, &user_kvm_nested_state->size))
4270 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4275 if (r > user_data_size) {
4276 if (put_user(r, &user_kvm_nested_state->size))
4286 case KVM_SET_NESTED_STATE: {
4287 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4288 struct kvm_nested_state kvm_state;
4291 if (!kvm_x86_ops->set_nested_state)
4295 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4299 if (kvm_state.size < sizeof(kvm_state))
4302 if (kvm_state.flags &
4303 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4304 | KVM_STATE_NESTED_EVMCS))
4307 /* nested_run_pending implies guest_mode. */
4308 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4309 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4312 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4315 case KVM_GET_SUPPORTED_HV_CPUID: {
4316 struct kvm_cpuid2 __user *cpuid_arg = argp;
4317 struct kvm_cpuid2 cpuid;
4320 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4323 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4324 cpuid_arg->entries);
4329 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4344 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4346 return VM_FAULT_SIGBUS;
4349 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4353 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4355 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4359 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4362 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4365 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4366 unsigned long kvm_nr_mmu_pages)
4368 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4371 mutex_lock(&kvm->slots_lock);
4373 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4374 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4376 mutex_unlock(&kvm->slots_lock);
4380 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4382 return kvm->arch.n_max_mmu_pages;
4385 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4387 struct kvm_pic *pic = kvm->arch.vpic;
4391 switch (chip->chip_id) {
4392 case KVM_IRQCHIP_PIC_MASTER:
4393 memcpy(&chip->chip.pic, &pic->pics[0],
4394 sizeof(struct kvm_pic_state));
4396 case KVM_IRQCHIP_PIC_SLAVE:
4397 memcpy(&chip->chip.pic, &pic->pics[1],
4398 sizeof(struct kvm_pic_state));
4400 case KVM_IRQCHIP_IOAPIC:
4401 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4410 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4412 struct kvm_pic *pic = kvm->arch.vpic;
4416 switch (chip->chip_id) {
4417 case KVM_IRQCHIP_PIC_MASTER:
4418 spin_lock(&pic->lock);
4419 memcpy(&pic->pics[0], &chip->chip.pic,
4420 sizeof(struct kvm_pic_state));
4421 spin_unlock(&pic->lock);
4423 case KVM_IRQCHIP_PIC_SLAVE:
4424 spin_lock(&pic->lock);
4425 memcpy(&pic->pics[1], &chip->chip.pic,
4426 sizeof(struct kvm_pic_state));
4427 spin_unlock(&pic->lock);
4429 case KVM_IRQCHIP_IOAPIC:
4430 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4436 kvm_pic_update_irq(pic);
4440 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4442 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4444 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4446 mutex_lock(&kps->lock);
4447 memcpy(ps, &kps->channels, sizeof(*ps));
4448 mutex_unlock(&kps->lock);
4452 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4455 struct kvm_pit *pit = kvm->arch.vpit;
4457 mutex_lock(&pit->pit_state.lock);
4458 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4459 for (i = 0; i < 3; i++)
4460 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4461 mutex_unlock(&pit->pit_state.lock);
4465 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4467 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4468 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4469 sizeof(ps->channels));
4470 ps->flags = kvm->arch.vpit->pit_state.flags;
4471 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4472 memset(&ps->reserved, 0, sizeof(ps->reserved));
4476 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4480 u32 prev_legacy, cur_legacy;
4481 struct kvm_pit *pit = kvm->arch.vpit;
4483 mutex_lock(&pit->pit_state.lock);
4484 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4485 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4486 if (!prev_legacy && cur_legacy)
4488 memcpy(&pit->pit_state.channels, &ps->channels,
4489 sizeof(pit->pit_state.channels));
4490 pit->pit_state.flags = ps->flags;
4491 for (i = 0; i < 3; i++)
4492 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4494 mutex_unlock(&pit->pit_state.lock);
4498 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4499 struct kvm_reinject_control *control)
4501 struct kvm_pit *pit = kvm->arch.vpit;
4506 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4507 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4508 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4510 mutex_lock(&pit->pit_state.lock);
4511 kvm_pit_set_reinject(pit, control->pit_reinject);
4512 mutex_unlock(&pit->pit_state.lock);
4518 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4519 * @kvm: kvm instance
4520 * @log: slot id and address to which we copy the log
4522 * Steps 1-4 below provide general overview of dirty page logging. See
4523 * kvm_get_dirty_log_protect() function description for additional details.
4525 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4526 * always flush the TLB (step 4) even if previous step failed and the dirty
4527 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4528 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4529 * writes will be marked dirty for next log read.
4531 * 1. Take a snapshot of the bit and clear it if needed.
4532 * 2. Write protect the corresponding page.
4533 * 3. Copy the snapshot to the userspace.
4534 * 4. Flush TLB's if needed.
4536 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4541 mutex_lock(&kvm->slots_lock);
4544 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4546 if (kvm_x86_ops->flush_log_dirty)
4547 kvm_x86_ops->flush_log_dirty(kvm);
4549 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4552 * All the TLBs can be flushed out of mmu lock, see the comments in
4553 * kvm_mmu_slot_remove_write_access().
4555 lockdep_assert_held(&kvm->slots_lock);
4557 kvm_flush_remote_tlbs(kvm);
4559 mutex_unlock(&kvm->slots_lock);
4563 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4568 mutex_lock(&kvm->slots_lock);
4571 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4573 if (kvm_x86_ops->flush_log_dirty)
4574 kvm_x86_ops->flush_log_dirty(kvm);
4576 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4579 * All the TLBs can be flushed out of mmu lock, see the comments in
4580 * kvm_mmu_slot_remove_write_access().
4582 lockdep_assert_held(&kvm->slots_lock);
4584 kvm_flush_remote_tlbs(kvm);
4586 mutex_unlock(&kvm->slots_lock);
4590 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4593 if (!irqchip_in_kernel(kvm))
4596 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4597 irq_event->irq, irq_event->level,
4602 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4603 struct kvm_enable_cap *cap)
4611 case KVM_CAP_DISABLE_QUIRKS:
4612 kvm->arch.disabled_quirks = cap->args[0];
4615 case KVM_CAP_SPLIT_IRQCHIP: {
4616 mutex_lock(&kvm->lock);
4618 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4619 goto split_irqchip_unlock;
4621 if (irqchip_in_kernel(kvm))
4622 goto split_irqchip_unlock;
4623 if (kvm->created_vcpus)
4624 goto split_irqchip_unlock;
4625 r = kvm_setup_empty_irq_routing(kvm);
4627 goto split_irqchip_unlock;
4628 /* Pairs with irqchip_in_kernel. */
4630 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4631 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4633 split_irqchip_unlock:
4634 mutex_unlock(&kvm->lock);
4637 case KVM_CAP_X2APIC_API:
4639 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4642 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4643 kvm->arch.x2apic_format = true;
4644 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4645 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4649 case KVM_CAP_X86_DISABLE_EXITS:
4651 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4654 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4655 kvm_can_mwait_in_guest())
4656 kvm->arch.mwait_in_guest = true;
4657 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4658 kvm->arch.hlt_in_guest = true;
4659 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4660 kvm->arch.pause_in_guest = true;
4661 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4662 kvm->arch.cstate_in_guest = true;
4665 case KVM_CAP_MSR_PLATFORM_INFO:
4666 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4669 case KVM_CAP_EXCEPTION_PAYLOAD:
4670 kvm->arch.exception_payload_enabled = cap->args[0];
4680 long kvm_arch_vm_ioctl(struct file *filp,
4681 unsigned int ioctl, unsigned long arg)
4683 struct kvm *kvm = filp->private_data;
4684 void __user *argp = (void __user *)arg;
4687 * This union makes it completely explicit to gcc-3.x
4688 * that these two variables' stack usage should be
4689 * combined, not added together.
4692 struct kvm_pit_state ps;
4693 struct kvm_pit_state2 ps2;
4694 struct kvm_pit_config pit_config;
4698 case KVM_SET_TSS_ADDR:
4699 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4701 case KVM_SET_IDENTITY_MAP_ADDR: {
4704 mutex_lock(&kvm->lock);
4706 if (kvm->created_vcpus)
4707 goto set_identity_unlock;
4709 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4710 goto set_identity_unlock;
4711 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4712 set_identity_unlock:
4713 mutex_unlock(&kvm->lock);
4716 case KVM_SET_NR_MMU_PAGES:
4717 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4719 case KVM_GET_NR_MMU_PAGES:
4720 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4722 case KVM_CREATE_IRQCHIP: {
4723 mutex_lock(&kvm->lock);
4726 if (irqchip_in_kernel(kvm))
4727 goto create_irqchip_unlock;
4730 if (kvm->created_vcpus)
4731 goto create_irqchip_unlock;
4733 r = kvm_pic_init(kvm);
4735 goto create_irqchip_unlock;
4737 r = kvm_ioapic_init(kvm);
4739 kvm_pic_destroy(kvm);
4740 goto create_irqchip_unlock;
4743 r = kvm_setup_default_irq_routing(kvm);
4745 kvm_ioapic_destroy(kvm);
4746 kvm_pic_destroy(kvm);
4747 goto create_irqchip_unlock;
4749 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4751 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4752 create_irqchip_unlock:
4753 mutex_unlock(&kvm->lock);
4756 case KVM_CREATE_PIT:
4757 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4759 case KVM_CREATE_PIT2:
4761 if (copy_from_user(&u.pit_config, argp,
4762 sizeof(struct kvm_pit_config)))
4765 mutex_lock(&kvm->lock);
4768 goto create_pit_unlock;
4770 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4774 mutex_unlock(&kvm->lock);
4776 case KVM_GET_IRQCHIP: {
4777 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4778 struct kvm_irqchip *chip;
4780 chip = memdup_user(argp, sizeof(*chip));
4787 if (!irqchip_kernel(kvm))
4788 goto get_irqchip_out;
4789 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4791 goto get_irqchip_out;
4793 if (copy_to_user(argp, chip, sizeof(*chip)))
4794 goto get_irqchip_out;
4800 case KVM_SET_IRQCHIP: {
4801 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4802 struct kvm_irqchip *chip;
4804 chip = memdup_user(argp, sizeof(*chip));
4811 if (!irqchip_kernel(kvm))
4812 goto set_irqchip_out;
4813 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4815 goto set_irqchip_out;
4823 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4826 if (!kvm->arch.vpit)
4828 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4832 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4839 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4842 if (!kvm->arch.vpit)
4844 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4847 case KVM_GET_PIT2: {
4849 if (!kvm->arch.vpit)
4851 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4855 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4860 case KVM_SET_PIT2: {
4862 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4865 if (!kvm->arch.vpit)
4867 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4870 case KVM_REINJECT_CONTROL: {
4871 struct kvm_reinject_control control;
4873 if (copy_from_user(&control, argp, sizeof(control)))
4875 r = kvm_vm_ioctl_reinject(kvm, &control);
4878 case KVM_SET_BOOT_CPU_ID:
4880 mutex_lock(&kvm->lock);
4881 if (kvm->created_vcpus)
4884 kvm->arch.bsp_vcpu_id = arg;
4885 mutex_unlock(&kvm->lock);
4887 case KVM_XEN_HVM_CONFIG: {
4888 struct kvm_xen_hvm_config xhc;
4890 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4895 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4899 case KVM_SET_CLOCK: {
4900 struct kvm_clock_data user_ns;
4904 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4913 * TODO: userspace has to take care of races with VCPU_RUN, so
4914 * kvm_gen_update_masterclock() can be cut down to locked
4915 * pvclock_update_vm_gtod_copy().
4917 kvm_gen_update_masterclock(kvm);
4918 now_ns = get_kvmclock_ns(kvm);
4919 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4920 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4923 case KVM_GET_CLOCK: {
4924 struct kvm_clock_data user_ns;
4927 now_ns = get_kvmclock_ns(kvm);
4928 user_ns.clock = now_ns;
4929 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4930 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4933 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4938 case KVM_MEMORY_ENCRYPT_OP: {
4940 if (kvm_x86_ops->mem_enc_op)
4941 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4944 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4945 struct kvm_enc_region region;
4948 if (copy_from_user(®ion, argp, sizeof(region)))
4952 if (kvm_x86_ops->mem_enc_reg_region)
4953 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4956 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4957 struct kvm_enc_region region;
4960 if (copy_from_user(®ion, argp, sizeof(region)))
4964 if (kvm_x86_ops->mem_enc_unreg_region)
4965 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4968 case KVM_HYPERV_EVENTFD: {
4969 struct kvm_hyperv_eventfd hvevfd;
4972 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4974 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4977 case KVM_SET_PMU_EVENT_FILTER:
4978 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
4987 static void kvm_init_msr_list(void)
4992 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4993 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4997 * Even MSRs that are valid in the host may not be exposed
4998 * to the guests in some cases.
5000 switch (msrs_to_save[i]) {
5001 case MSR_IA32_BNDCFGS:
5002 if (!kvm_mpx_supported())
5006 if (!kvm_x86_ops->rdtscp_supported())
5009 case MSR_IA32_RTIT_CTL:
5010 case MSR_IA32_RTIT_STATUS:
5011 if (!kvm_x86_ops->pt_supported())
5014 case MSR_IA32_RTIT_CR3_MATCH:
5015 if (!kvm_x86_ops->pt_supported() ||
5016 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5019 case MSR_IA32_RTIT_OUTPUT_BASE:
5020 case MSR_IA32_RTIT_OUTPUT_MASK:
5021 if (!kvm_x86_ops->pt_supported() ||
5022 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5023 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5026 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5027 if (!kvm_x86_ops->pt_supported() ||
5028 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5029 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5038 msrs_to_save[j] = msrs_to_save[i];
5041 num_msrs_to_save = j;
5043 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5044 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5048 emulated_msrs[j] = emulated_msrs[i];
5051 num_emulated_msrs = j;
5053 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5054 struct kvm_msr_entry msr;
5056 msr.index = msr_based_features[i];
5057 if (kvm_get_msr_feature(&msr))
5061 msr_based_features[j] = msr_based_features[i];
5064 num_msr_based_features = j;
5067 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5075 if (!(lapic_in_kernel(vcpu) &&
5076 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5077 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5088 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5095 if (!(lapic_in_kernel(vcpu) &&
5096 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5098 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5100 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5110 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5111 struct kvm_segment *var, int seg)
5113 kvm_x86_ops->set_segment(vcpu, var, seg);
5116 void kvm_get_segment(struct kvm_vcpu *vcpu,
5117 struct kvm_segment *var, int seg)
5119 kvm_x86_ops->get_segment(vcpu, var, seg);
5122 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5123 struct x86_exception *exception)
5127 BUG_ON(!mmu_is_nested(vcpu));
5129 /* NPT walks are always user-walks */
5130 access |= PFERR_USER_MASK;
5131 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5136 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5137 struct x86_exception *exception)
5139 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5140 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5143 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5144 struct x86_exception *exception)
5146 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5147 access |= PFERR_FETCH_MASK;
5148 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5151 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5152 struct x86_exception *exception)
5154 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5155 access |= PFERR_WRITE_MASK;
5156 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5159 /* uses this to access any guest's mapped memory without checking CPL */
5160 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5161 struct x86_exception *exception)
5163 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5166 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5167 struct kvm_vcpu *vcpu, u32 access,
5168 struct x86_exception *exception)
5171 int r = X86EMUL_CONTINUE;
5174 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5176 unsigned offset = addr & (PAGE_SIZE-1);
5177 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5180 if (gpa == UNMAPPED_GVA)
5181 return X86EMUL_PROPAGATE_FAULT;
5182 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5185 r = X86EMUL_IO_NEEDED;
5197 /* used for instruction fetching */
5198 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5199 gva_t addr, void *val, unsigned int bytes,
5200 struct x86_exception *exception)
5202 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5203 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5207 /* Inline kvm_read_guest_virt_helper for speed. */
5208 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5210 if (unlikely(gpa == UNMAPPED_GVA))
5211 return X86EMUL_PROPAGATE_FAULT;
5213 offset = addr & (PAGE_SIZE-1);
5214 if (WARN_ON(offset + bytes > PAGE_SIZE))
5215 bytes = (unsigned)PAGE_SIZE - offset;
5216 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5218 if (unlikely(ret < 0))
5219 return X86EMUL_IO_NEEDED;
5221 return X86EMUL_CONTINUE;
5224 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5225 gva_t addr, void *val, unsigned int bytes,
5226 struct x86_exception *exception)
5228 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5231 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5232 * is returned, but our callers are not ready for that and they blindly
5233 * call kvm_inject_page_fault. Ensure that they at least do not leak
5234 * uninitialized kernel stack memory into cr2 and error code.
5236 memset(exception, 0, sizeof(*exception));
5237 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5240 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5242 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5243 gva_t addr, void *val, unsigned int bytes,
5244 struct x86_exception *exception, bool system)
5246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5249 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5250 access |= PFERR_USER_MASK;
5252 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5255 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5256 unsigned long addr, void *val, unsigned int bytes)
5258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5259 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5261 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5264 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5265 struct kvm_vcpu *vcpu, u32 access,
5266 struct x86_exception *exception)
5269 int r = X86EMUL_CONTINUE;
5272 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5275 unsigned offset = addr & (PAGE_SIZE-1);
5276 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5279 if (gpa == UNMAPPED_GVA)
5280 return X86EMUL_PROPAGATE_FAULT;
5281 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5283 r = X86EMUL_IO_NEEDED;
5295 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5296 unsigned int bytes, struct x86_exception *exception,
5299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5300 u32 access = PFERR_WRITE_MASK;
5302 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5303 access |= PFERR_USER_MASK;
5305 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5309 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5310 unsigned int bytes, struct x86_exception *exception)
5312 /* kvm_write_guest_virt_system can pull in tons of pages. */
5313 vcpu->arch.l1tf_flush_l1d = true;
5315 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5316 PFERR_WRITE_MASK, exception);
5318 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5320 int handle_ud(struct kvm_vcpu *vcpu)
5322 int emul_type = EMULTYPE_TRAP_UD;
5323 enum emulation_result er;
5324 char sig[5]; /* ud2; .ascii "kvm" */
5325 struct x86_exception e;
5327 if (force_emulation_prefix &&
5328 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5329 sig, sizeof(sig), &e) == 0 &&
5330 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5331 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5335 er = kvm_emulate_instruction(vcpu, emul_type);
5336 if (er == EMULATE_USER_EXIT)
5338 if (er != EMULATE_DONE)
5339 kvm_queue_exception(vcpu, UD_VECTOR);
5342 EXPORT_SYMBOL_GPL(handle_ud);
5344 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5345 gpa_t gpa, bool write)
5347 /* For APIC access vmexit */
5348 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5351 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5352 trace_vcpu_match_mmio(gva, gpa, write, true);
5359 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5360 gpa_t *gpa, struct x86_exception *exception,
5363 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5364 | (write ? PFERR_WRITE_MASK : 0);
5367 * currently PKRU is only applied to ept enabled guest so
5368 * there is no pkey in EPT page table for L1 guest or EPT
5369 * shadow page table for L2 guest.
5371 if (vcpu_match_mmio_gva(vcpu, gva)
5372 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5373 vcpu->arch.access, 0, access)) {
5374 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5375 (gva & (PAGE_SIZE - 1));
5376 trace_vcpu_match_mmio(gva, *gpa, write, false);
5380 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5382 if (*gpa == UNMAPPED_GVA)
5385 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5388 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5389 const void *val, int bytes)
5393 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5396 kvm_page_track_write(vcpu, gpa, val, bytes);
5400 struct read_write_emulator_ops {
5401 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5403 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5404 void *val, int bytes);
5405 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5406 int bytes, void *val);
5407 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5408 void *val, int bytes);
5412 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5414 if (vcpu->mmio_read_completed) {
5415 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5416 vcpu->mmio_fragments[0].gpa, val);
5417 vcpu->mmio_read_completed = 0;
5424 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5425 void *val, int bytes)
5427 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5430 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5431 void *val, int bytes)
5433 return emulator_write_phys(vcpu, gpa, val, bytes);
5436 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5438 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5439 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5442 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5443 void *val, int bytes)
5445 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5446 return X86EMUL_IO_NEEDED;
5449 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5450 void *val, int bytes)
5452 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5454 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5455 return X86EMUL_CONTINUE;
5458 static const struct read_write_emulator_ops read_emultor = {
5459 .read_write_prepare = read_prepare,
5460 .read_write_emulate = read_emulate,
5461 .read_write_mmio = vcpu_mmio_read,
5462 .read_write_exit_mmio = read_exit_mmio,
5465 static const struct read_write_emulator_ops write_emultor = {
5466 .read_write_emulate = write_emulate,
5467 .read_write_mmio = write_mmio,
5468 .read_write_exit_mmio = write_exit_mmio,
5472 static int emulator_read_write_onepage(unsigned long addr, void *val,
5474 struct x86_exception *exception,
5475 struct kvm_vcpu *vcpu,
5476 const struct read_write_emulator_ops *ops)
5480 bool write = ops->write;
5481 struct kvm_mmio_fragment *frag;
5482 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5485 * If the exit was due to a NPF we may already have a GPA.
5486 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5487 * Note, this cannot be used on string operations since string
5488 * operation using rep will only have the initial GPA from the NPF
5491 if (vcpu->arch.gpa_available &&
5492 emulator_can_use_gpa(ctxt) &&
5493 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5494 gpa = vcpu->arch.gpa_val;
5495 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5497 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5499 return X86EMUL_PROPAGATE_FAULT;
5502 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5503 return X86EMUL_CONTINUE;
5506 * Is this MMIO handled locally?
5508 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5509 if (handled == bytes)
5510 return X86EMUL_CONTINUE;
5516 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5517 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5521 return X86EMUL_CONTINUE;
5524 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5526 void *val, unsigned int bytes,
5527 struct x86_exception *exception,
5528 const struct read_write_emulator_ops *ops)
5530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5534 if (ops->read_write_prepare &&
5535 ops->read_write_prepare(vcpu, val, bytes))
5536 return X86EMUL_CONTINUE;
5538 vcpu->mmio_nr_fragments = 0;
5540 /* Crossing a page boundary? */
5541 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5544 now = -addr & ~PAGE_MASK;
5545 rc = emulator_read_write_onepage(addr, val, now, exception,
5548 if (rc != X86EMUL_CONTINUE)
5551 if (ctxt->mode != X86EMUL_MODE_PROT64)
5557 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5559 if (rc != X86EMUL_CONTINUE)
5562 if (!vcpu->mmio_nr_fragments)
5565 gpa = vcpu->mmio_fragments[0].gpa;
5567 vcpu->mmio_needed = 1;
5568 vcpu->mmio_cur_fragment = 0;
5570 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5571 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5572 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5573 vcpu->run->mmio.phys_addr = gpa;
5575 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5578 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5582 struct x86_exception *exception)
5584 return emulator_read_write(ctxt, addr, val, bytes,
5585 exception, &read_emultor);
5588 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5592 struct x86_exception *exception)
5594 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5595 exception, &write_emultor);
5598 #define CMPXCHG_TYPE(t, ptr, old, new) \
5599 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5601 #ifdef CONFIG_X86_64
5602 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5604 # define CMPXCHG64(ptr, old, new) \
5605 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5608 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5613 struct x86_exception *exception)
5615 struct kvm_host_map map;
5616 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5621 /* guests cmpxchg8b have to be emulated atomically */
5622 if (bytes > 8 || (bytes & (bytes - 1)))
5625 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5627 if (gpa == UNMAPPED_GVA ||
5628 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5631 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5634 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5637 kaddr = map.hva + offset_in_page(gpa);
5641 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5644 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5647 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5650 exchanged = CMPXCHG64(kaddr, old, new);
5656 kvm_vcpu_unmap(vcpu, &map, true);
5659 return X86EMUL_CMPXCHG_FAILED;
5661 kvm_page_track_write(vcpu, gpa, new, bytes);
5663 return X86EMUL_CONTINUE;
5666 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5668 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5671 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5675 for (i = 0; i < vcpu->arch.pio.count; i++) {
5676 if (vcpu->arch.pio.in)
5677 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5678 vcpu->arch.pio.size, pd);
5680 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5681 vcpu->arch.pio.port, vcpu->arch.pio.size,
5685 pd += vcpu->arch.pio.size;
5690 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5691 unsigned short port, void *val,
5692 unsigned int count, bool in)
5694 vcpu->arch.pio.port = port;
5695 vcpu->arch.pio.in = in;
5696 vcpu->arch.pio.count = count;
5697 vcpu->arch.pio.size = size;
5699 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5700 vcpu->arch.pio.count = 0;
5704 vcpu->run->exit_reason = KVM_EXIT_IO;
5705 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5706 vcpu->run->io.size = size;
5707 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5708 vcpu->run->io.count = count;
5709 vcpu->run->io.port = port;
5714 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5715 int size, unsigned short port, void *val,
5718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5721 if (vcpu->arch.pio.count)
5724 memset(vcpu->arch.pio_data, 0, size * count);
5726 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5729 memcpy(val, vcpu->arch.pio_data, size * count);
5730 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5731 vcpu->arch.pio.count = 0;
5738 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5739 int size, unsigned short port,
5740 const void *val, unsigned int count)
5742 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5744 memcpy(vcpu->arch.pio_data, val, size * count);
5745 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5746 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5749 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5751 return kvm_x86_ops->get_segment_base(vcpu, seg);
5754 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5756 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5759 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5761 if (!need_emulate_wbinvd(vcpu))
5762 return X86EMUL_CONTINUE;
5764 if (kvm_x86_ops->has_wbinvd_exit()) {
5765 int cpu = get_cpu();
5767 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5768 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5769 wbinvd_ipi, NULL, 1);
5771 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5774 return X86EMUL_CONTINUE;
5777 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5779 kvm_emulate_wbinvd_noskip(vcpu);
5780 return kvm_skip_emulated_instruction(vcpu);
5782 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5786 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5788 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5791 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5792 unsigned long *dest)
5794 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5797 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5798 unsigned long value)
5801 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5804 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5806 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5809 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5811 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5812 unsigned long value;
5816 value = kvm_read_cr0(vcpu);
5819 value = vcpu->arch.cr2;
5822 value = kvm_read_cr3(vcpu);
5825 value = kvm_read_cr4(vcpu);
5828 value = kvm_get_cr8(vcpu);
5831 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5838 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5845 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5848 vcpu->arch.cr2 = val;
5851 res = kvm_set_cr3(vcpu, val);
5854 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5857 res = kvm_set_cr8(vcpu, val);
5860 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5867 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5869 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5872 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5874 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5877 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5879 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5882 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5884 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5887 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5889 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5892 static unsigned long emulator_get_cached_segment_base(
5893 struct x86_emulate_ctxt *ctxt, int seg)
5895 return get_segment_base(emul_to_vcpu(ctxt), seg);
5898 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5899 struct desc_struct *desc, u32 *base3,
5902 struct kvm_segment var;
5904 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5905 *selector = var.selector;
5908 memset(desc, 0, sizeof(*desc));
5916 set_desc_limit(desc, var.limit);
5917 set_desc_base(desc, (unsigned long)var.base);
5918 #ifdef CONFIG_X86_64
5920 *base3 = var.base >> 32;
5922 desc->type = var.type;
5924 desc->dpl = var.dpl;
5925 desc->p = var.present;
5926 desc->avl = var.avl;
5934 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5935 struct desc_struct *desc, u32 base3,
5938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5939 struct kvm_segment var;
5941 var.selector = selector;
5942 var.base = get_desc_base(desc);
5943 #ifdef CONFIG_X86_64
5944 var.base |= ((u64)base3) << 32;
5946 var.limit = get_desc_limit(desc);
5948 var.limit = (var.limit << 12) | 0xfff;
5949 var.type = desc->type;
5950 var.dpl = desc->dpl;
5955 var.avl = desc->avl;
5956 var.present = desc->p;
5957 var.unusable = !var.present;
5960 kvm_set_segment(vcpu, &var, seg);
5964 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5965 u32 msr_index, u64 *pdata)
5967 struct msr_data msr;
5970 msr.index = msr_index;
5971 msr.host_initiated = false;
5972 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5980 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5981 u32 msr_index, u64 data)
5983 struct msr_data msr;
5986 msr.index = msr_index;
5987 msr.host_initiated = false;
5988 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5991 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5993 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5995 return vcpu->arch.smbase;
5998 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6002 vcpu->arch.smbase = smbase;
6005 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6008 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6011 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6012 u32 pmc, u64 *pdata)
6014 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6017 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6019 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6022 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6023 struct x86_instruction_info *info,
6024 enum x86_intercept_stage stage)
6026 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6029 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6030 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6032 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6035 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6037 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6040 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6042 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6045 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6047 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6050 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6052 return emul_to_vcpu(ctxt)->arch.hflags;
6055 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6057 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6060 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6061 const char *smstate)
6063 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6066 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6068 kvm_smm_changed(emul_to_vcpu(ctxt));
6071 static const struct x86_emulate_ops emulate_ops = {
6072 .read_gpr = emulator_read_gpr,
6073 .write_gpr = emulator_write_gpr,
6074 .read_std = emulator_read_std,
6075 .write_std = emulator_write_std,
6076 .read_phys = kvm_read_guest_phys_system,
6077 .fetch = kvm_fetch_guest_virt,
6078 .read_emulated = emulator_read_emulated,
6079 .write_emulated = emulator_write_emulated,
6080 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6081 .invlpg = emulator_invlpg,
6082 .pio_in_emulated = emulator_pio_in_emulated,
6083 .pio_out_emulated = emulator_pio_out_emulated,
6084 .get_segment = emulator_get_segment,
6085 .set_segment = emulator_set_segment,
6086 .get_cached_segment_base = emulator_get_cached_segment_base,
6087 .get_gdt = emulator_get_gdt,
6088 .get_idt = emulator_get_idt,
6089 .set_gdt = emulator_set_gdt,
6090 .set_idt = emulator_set_idt,
6091 .get_cr = emulator_get_cr,
6092 .set_cr = emulator_set_cr,
6093 .cpl = emulator_get_cpl,
6094 .get_dr = emulator_get_dr,
6095 .set_dr = emulator_set_dr,
6096 .get_smbase = emulator_get_smbase,
6097 .set_smbase = emulator_set_smbase,
6098 .set_msr = emulator_set_msr,
6099 .get_msr = emulator_get_msr,
6100 .check_pmc = emulator_check_pmc,
6101 .read_pmc = emulator_read_pmc,
6102 .halt = emulator_halt,
6103 .wbinvd = emulator_wbinvd,
6104 .fix_hypercall = emulator_fix_hypercall,
6105 .intercept = emulator_intercept,
6106 .get_cpuid = emulator_get_cpuid,
6107 .set_nmi_mask = emulator_set_nmi_mask,
6108 .get_hflags = emulator_get_hflags,
6109 .set_hflags = emulator_set_hflags,
6110 .pre_leave_smm = emulator_pre_leave_smm,
6111 .post_leave_smm = emulator_post_leave_smm,
6114 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6116 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6118 * an sti; sti; sequence only disable interrupts for the first
6119 * instruction. So, if the last instruction, be it emulated or
6120 * not, left the system with the INT_STI flag enabled, it
6121 * means that the last instruction is an sti. We should not
6122 * leave the flag on in this case. The same goes for mov ss
6124 if (int_shadow & mask)
6126 if (unlikely(int_shadow || mask)) {
6127 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6129 kvm_make_request(KVM_REQ_EVENT, vcpu);
6133 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6135 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6136 if (ctxt->exception.vector == PF_VECTOR)
6137 return kvm_propagate_fault(vcpu, &ctxt->exception);
6139 if (ctxt->exception.error_code_valid)
6140 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6141 ctxt->exception.error_code);
6143 kvm_queue_exception(vcpu, ctxt->exception.vector);
6147 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6149 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6152 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6154 ctxt->eflags = kvm_get_rflags(vcpu);
6155 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6157 ctxt->eip = kvm_rip_read(vcpu);
6158 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6159 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6160 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6161 cs_db ? X86EMUL_MODE_PROT32 :
6162 X86EMUL_MODE_PROT16;
6163 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6164 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6165 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6167 init_decode_cache(ctxt);
6168 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6171 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6173 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6176 init_emulate_ctxt(vcpu);
6180 ctxt->_eip = ctxt->eip + inc_eip;
6181 ret = emulate_int_real(ctxt, irq);
6183 if (ret != X86EMUL_CONTINUE)
6184 return EMULATE_FAIL;
6186 ctxt->eip = ctxt->_eip;
6187 kvm_rip_write(vcpu, ctxt->eip);
6188 kvm_set_rflags(vcpu, ctxt->eflags);
6190 return EMULATE_DONE;
6192 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6194 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6196 int r = EMULATE_DONE;
6198 ++vcpu->stat.insn_emulation_fail;
6199 trace_kvm_emulate_insn_failed(vcpu);
6201 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6202 return EMULATE_FAIL;
6204 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6205 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6206 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6207 vcpu->run->internal.ndata = 0;
6208 r = EMULATE_USER_EXIT;
6211 kvm_queue_exception(vcpu, UD_VECTOR);
6216 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6217 bool write_fault_to_shadow_pgtable,
6223 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6226 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6229 if (!vcpu->arch.mmu->direct_map) {
6231 * Write permission should be allowed since only
6232 * write access need to be emulated.
6234 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6237 * If the mapping is invalid in guest, let cpu retry
6238 * it to generate fault.
6240 if (gpa == UNMAPPED_GVA)
6245 * Do not retry the unhandleable instruction if it faults on the
6246 * readonly host memory, otherwise it will goto a infinite loop:
6247 * retry instruction -> write #PF -> emulation fail -> retry
6248 * instruction -> ...
6250 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6253 * If the instruction failed on the error pfn, it can not be fixed,
6254 * report the error to userspace.
6256 if (is_error_noslot_pfn(pfn))
6259 kvm_release_pfn_clean(pfn);
6261 /* The instructions are well-emulated on direct mmu. */
6262 if (vcpu->arch.mmu->direct_map) {
6263 unsigned int indirect_shadow_pages;
6265 spin_lock(&vcpu->kvm->mmu_lock);
6266 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6267 spin_unlock(&vcpu->kvm->mmu_lock);
6269 if (indirect_shadow_pages)
6270 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6276 * if emulation was due to access to shadowed page table
6277 * and it failed try to unshadow page and re-enter the
6278 * guest to let CPU execute the instruction.
6280 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6283 * If the access faults on its page table, it can not
6284 * be fixed by unprotecting shadow page and it should
6285 * be reported to userspace.
6287 return !write_fault_to_shadow_pgtable;
6290 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6291 unsigned long cr2, int emulation_type)
6293 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6294 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6296 last_retry_eip = vcpu->arch.last_retry_eip;
6297 last_retry_addr = vcpu->arch.last_retry_addr;
6300 * If the emulation is caused by #PF and it is non-page_table
6301 * writing instruction, it means the VM-EXIT is caused by shadow
6302 * page protected, we can zap the shadow page and retry this
6303 * instruction directly.
6305 * Note: if the guest uses a non-page-table modifying instruction
6306 * on the PDE that points to the instruction, then we will unmap
6307 * the instruction and go to an infinite loop. So, we cache the
6308 * last retried eip and the last fault address, if we meet the eip
6309 * and the address again, we can break out of the potential infinite
6312 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6314 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6317 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6320 if (x86_page_table_writing_insn(ctxt))
6323 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6326 vcpu->arch.last_retry_eip = ctxt->eip;
6327 vcpu->arch.last_retry_addr = cr2;
6329 if (!vcpu->arch.mmu->direct_map)
6330 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6332 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6337 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6338 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6340 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6342 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6343 /* This is a good place to trace that we are exiting SMM. */
6344 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6346 /* Process a latched INIT or SMI, if any. */
6347 kvm_make_request(KVM_REQ_EVENT, vcpu);
6350 kvm_mmu_reset_context(vcpu);
6353 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6362 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6363 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6368 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6370 struct kvm_run *kvm_run = vcpu->run;
6372 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6373 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6374 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6375 kvm_run->debug.arch.exception = DB_VECTOR;
6376 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6377 *r = EMULATE_USER_EXIT;
6379 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6383 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6385 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6386 int r = EMULATE_DONE;
6388 kvm_x86_ops->skip_emulated_instruction(vcpu);
6391 * rflags is the old, "raw" value of the flags. The new value has
6392 * not been saved yet.
6394 * This is correct even for TF set by the guest, because "the
6395 * processor will not generate this exception after the instruction
6396 * that sets the TF flag".
6398 if (unlikely(rflags & X86_EFLAGS_TF))
6399 kvm_vcpu_do_singlestep(vcpu, &r);
6400 return r == EMULATE_DONE;
6402 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6404 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6406 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6407 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6408 struct kvm_run *kvm_run = vcpu->run;
6409 unsigned long eip = kvm_get_linear_rip(vcpu);
6410 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6411 vcpu->arch.guest_debug_dr7,
6415 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6416 kvm_run->debug.arch.pc = eip;
6417 kvm_run->debug.arch.exception = DB_VECTOR;
6418 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6419 *r = EMULATE_USER_EXIT;
6424 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6425 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6426 unsigned long eip = kvm_get_linear_rip(vcpu);
6427 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6432 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6433 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6434 kvm_queue_exception(vcpu, DB_VECTOR);
6443 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6445 switch (ctxt->opcode_len) {
6452 case 0xe6: /* OUT */
6456 case 0x6c: /* INS */
6458 case 0x6e: /* OUTS */
6465 case 0x33: /* RDPMC */
6474 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6481 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6482 bool writeback = true;
6483 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6485 vcpu->arch.l1tf_flush_l1d = true;
6488 * Clear write_fault_to_shadow_pgtable here to ensure it is
6491 vcpu->arch.write_fault_to_shadow_pgtable = false;
6492 kvm_clear_exception_queue(vcpu);
6494 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6495 init_emulate_ctxt(vcpu);
6498 * We will reenter on the same instruction since
6499 * we do not set complete_userspace_io. This does not
6500 * handle watchpoints yet, those would be handled in
6503 if (!(emulation_type & EMULTYPE_SKIP) &&
6504 kvm_vcpu_check_breakpoint(vcpu, &r))
6507 ctxt->interruptibility = 0;
6508 ctxt->have_exception = false;
6509 ctxt->exception.vector = -1;
6510 ctxt->perm_ok = false;
6512 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6514 r = x86_decode_insn(ctxt, insn, insn_len);
6516 trace_kvm_emulate_insn_start(vcpu);
6517 ++vcpu->stat.insn_emulation;
6518 if (r != EMULATION_OK) {
6519 if (emulation_type & EMULTYPE_TRAP_UD)
6520 return EMULATE_FAIL;
6521 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6523 return EMULATE_DONE;
6524 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6525 return EMULATE_DONE;
6526 if (emulation_type & EMULTYPE_SKIP)
6527 return EMULATE_FAIL;
6528 return handle_emulation_failure(vcpu, emulation_type);
6532 if ((emulation_type & EMULTYPE_VMWARE) &&
6533 !is_vmware_backdoor_opcode(ctxt))
6534 return EMULATE_FAIL;
6536 if (emulation_type & EMULTYPE_SKIP) {
6537 kvm_rip_write(vcpu, ctxt->_eip);
6538 if (ctxt->eflags & X86_EFLAGS_RF)
6539 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6540 return EMULATE_DONE;
6543 if (retry_instruction(ctxt, cr2, emulation_type))
6544 return EMULATE_DONE;
6546 /* this is needed for vmware backdoor interface to work since it
6547 changes registers values during IO operation */
6548 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6549 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6550 emulator_invalidate_register_cache(ctxt);
6554 /* Save the faulting GPA (cr2) in the address field */
6555 ctxt->exception.address = cr2;
6557 r = x86_emulate_insn(ctxt);
6559 if (r == EMULATION_INTERCEPTED)
6560 return EMULATE_DONE;
6562 if (r == EMULATION_FAILED) {
6563 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6565 return EMULATE_DONE;
6567 return handle_emulation_failure(vcpu, emulation_type);
6570 if (ctxt->have_exception) {
6572 if (inject_emulated_exception(vcpu))
6574 } else if (vcpu->arch.pio.count) {
6575 if (!vcpu->arch.pio.in) {
6576 /* FIXME: return into emulator if single-stepping. */
6577 vcpu->arch.pio.count = 0;
6580 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6582 r = EMULATE_USER_EXIT;
6583 } else if (vcpu->mmio_needed) {
6584 if (!vcpu->mmio_is_write)
6586 r = EMULATE_USER_EXIT;
6587 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6588 } else if (r == EMULATION_RESTART)
6594 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6595 toggle_interruptibility(vcpu, ctxt->interruptibility);
6596 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6597 kvm_rip_write(vcpu, ctxt->eip);
6598 if (r == EMULATE_DONE && ctxt->tf)
6599 kvm_vcpu_do_singlestep(vcpu, &r);
6600 if (!ctxt->have_exception ||
6601 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6602 __kvm_set_rflags(vcpu, ctxt->eflags);
6605 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6606 * do nothing, and it will be requested again as soon as
6607 * the shadow expires. But we still need to check here,
6608 * because POPF has no interrupt shadow.
6610 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6611 kvm_make_request(KVM_REQ_EVENT, vcpu);
6613 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6618 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6620 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6622 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6624 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6625 void *insn, int insn_len)
6627 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6629 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6631 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6633 vcpu->arch.pio.count = 0;
6637 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6639 vcpu->arch.pio.count = 0;
6641 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6644 return kvm_skip_emulated_instruction(vcpu);
6647 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6648 unsigned short port)
6650 unsigned long val = kvm_rax_read(vcpu);
6651 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6652 size, port, &val, 1);
6657 * Workaround userspace that relies on old KVM behavior of %rip being
6658 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6661 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6662 vcpu->arch.complete_userspace_io =
6663 complete_fast_pio_out_port_0x7e;
6664 kvm_skip_emulated_instruction(vcpu);
6666 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6667 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6672 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6676 /* We should only ever be called with arch.pio.count equal to 1 */
6677 BUG_ON(vcpu->arch.pio.count != 1);
6679 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6680 vcpu->arch.pio.count = 0;
6684 /* For size less than 4 we merge, else we zero extend */
6685 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6688 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6689 * the copy and tracing
6691 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6692 vcpu->arch.pio.port, &val, 1);
6693 kvm_rax_write(vcpu, val);
6695 return kvm_skip_emulated_instruction(vcpu);
6698 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6699 unsigned short port)
6704 /* For size less than 4 we merge, else we zero extend */
6705 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6707 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6710 kvm_rax_write(vcpu, val);
6714 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6715 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6720 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6725 ret = kvm_fast_pio_in(vcpu, size, port);
6727 ret = kvm_fast_pio_out(vcpu, size, port);
6728 return ret && kvm_skip_emulated_instruction(vcpu);
6730 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6732 static int kvmclock_cpu_down_prep(unsigned int cpu)
6734 __this_cpu_write(cpu_tsc_khz, 0);
6738 static void tsc_khz_changed(void *data)
6740 struct cpufreq_freqs *freq = data;
6741 unsigned long khz = 0;
6745 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6746 khz = cpufreq_quick_get(raw_smp_processor_id());
6749 __this_cpu_write(cpu_tsc_khz, khz);
6752 #ifdef CONFIG_X86_64
6753 static void kvm_hyperv_tsc_notifier(void)
6756 struct kvm_vcpu *vcpu;
6759 mutex_lock(&kvm_lock);
6760 list_for_each_entry(kvm, &vm_list, vm_list)
6761 kvm_make_mclock_inprogress_request(kvm);
6763 hyperv_stop_tsc_emulation();
6765 /* TSC frequency always matches when on Hyper-V */
6766 for_each_present_cpu(cpu)
6767 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6768 kvm_max_guest_tsc_khz = tsc_khz;
6770 list_for_each_entry(kvm, &vm_list, vm_list) {
6771 struct kvm_arch *ka = &kvm->arch;
6773 spin_lock(&ka->pvclock_gtod_sync_lock);
6775 pvclock_update_vm_gtod_copy(kvm);
6777 kvm_for_each_vcpu(cpu, vcpu, kvm)
6778 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6780 kvm_for_each_vcpu(cpu, vcpu, kvm)
6781 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6783 spin_unlock(&ka->pvclock_gtod_sync_lock);
6785 mutex_unlock(&kvm_lock);
6789 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6792 struct kvm_vcpu *vcpu;
6793 int i, send_ipi = 0;
6796 * We allow guests to temporarily run on slowing clocks,
6797 * provided we notify them after, or to run on accelerating
6798 * clocks, provided we notify them before. Thus time never
6801 * However, we have a problem. We can't atomically update
6802 * the frequency of a given CPU from this function; it is
6803 * merely a notifier, which can be called from any CPU.
6804 * Changing the TSC frequency at arbitrary points in time
6805 * requires a recomputation of local variables related to
6806 * the TSC for each VCPU. We must flag these local variables
6807 * to be updated and be sure the update takes place with the
6808 * new frequency before any guests proceed.
6810 * Unfortunately, the combination of hotplug CPU and frequency
6811 * change creates an intractable locking scenario; the order
6812 * of when these callouts happen is undefined with respect to
6813 * CPU hotplug, and they can race with each other. As such,
6814 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6815 * undefined; you can actually have a CPU frequency change take
6816 * place in between the computation of X and the setting of the
6817 * variable. To protect against this problem, all updates of
6818 * the per_cpu tsc_khz variable are done in an interrupt
6819 * protected IPI, and all callers wishing to update the value
6820 * must wait for a synchronous IPI to complete (which is trivial
6821 * if the caller is on the CPU already). This establishes the
6822 * necessary total order on variable updates.
6824 * Note that because a guest time update may take place
6825 * anytime after the setting of the VCPU's request bit, the
6826 * correct TSC value must be set before the request. However,
6827 * to ensure the update actually makes it to any guest which
6828 * starts running in hardware virtualization between the set
6829 * and the acquisition of the spinlock, we must also ping the
6830 * CPU after setting the request bit.
6834 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6836 mutex_lock(&kvm_lock);
6837 list_for_each_entry(kvm, &vm_list, vm_list) {
6838 kvm_for_each_vcpu(i, vcpu, kvm) {
6839 if (vcpu->cpu != cpu)
6841 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6842 if (vcpu->cpu != raw_smp_processor_id())
6846 mutex_unlock(&kvm_lock);
6848 if (freq->old < freq->new && send_ipi) {
6850 * We upscale the frequency. Must make the guest
6851 * doesn't see old kvmclock values while running with
6852 * the new frequency, otherwise we risk the guest sees
6853 * time go backwards.
6855 * In case we update the frequency for another cpu
6856 * (which might be in guest context) send an interrupt
6857 * to kick the cpu out of guest context. Next time
6858 * guest context is entered kvmclock will be updated,
6859 * so the guest will not see stale values.
6861 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6865 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6868 struct cpufreq_freqs *freq = data;
6871 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6873 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6876 for_each_cpu(cpu, freq->policy->cpus)
6877 __kvmclock_cpufreq_notifier(freq, cpu);
6882 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6883 .notifier_call = kvmclock_cpufreq_notifier
6886 static int kvmclock_cpu_online(unsigned int cpu)
6888 tsc_khz_changed(NULL);
6892 static void kvm_timer_init(void)
6894 max_tsc_khz = tsc_khz;
6896 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6897 #ifdef CONFIG_CPU_FREQ
6898 struct cpufreq_policy policy;
6901 memset(&policy, 0, sizeof(policy));
6903 cpufreq_get_policy(&policy, cpu);
6904 if (policy.cpuinfo.max_freq)
6905 max_tsc_khz = policy.cpuinfo.max_freq;
6908 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6909 CPUFREQ_TRANSITION_NOTIFIER);
6912 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6913 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6916 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6917 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6919 int kvm_is_in_guest(void)
6921 return __this_cpu_read(current_vcpu) != NULL;
6924 static int kvm_is_user_mode(void)
6928 if (__this_cpu_read(current_vcpu))
6929 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6931 return user_mode != 0;
6934 static unsigned long kvm_get_guest_ip(void)
6936 unsigned long ip = 0;
6938 if (__this_cpu_read(current_vcpu))
6939 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6944 static void kvm_handle_intel_pt_intr(void)
6946 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6948 kvm_make_request(KVM_REQ_PMI, vcpu);
6949 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6950 (unsigned long *)&vcpu->arch.pmu.global_status);
6953 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6954 .is_in_guest = kvm_is_in_guest,
6955 .is_user_mode = kvm_is_user_mode,
6956 .get_guest_ip = kvm_get_guest_ip,
6957 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
6960 #ifdef CONFIG_X86_64
6961 static void pvclock_gtod_update_fn(struct work_struct *work)
6965 struct kvm_vcpu *vcpu;
6968 mutex_lock(&kvm_lock);
6969 list_for_each_entry(kvm, &vm_list, vm_list)
6970 kvm_for_each_vcpu(i, vcpu, kvm)
6971 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6972 atomic_set(&kvm_guest_has_master_clock, 0);
6973 mutex_unlock(&kvm_lock);
6976 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6979 * Notification about pvclock gtod data update.
6981 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6984 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6985 struct timekeeper *tk = priv;
6987 update_pvclock_gtod(tk);
6989 /* disable master clock if host does not trust, or does not
6990 * use, TSC based clocksource.
6992 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6993 atomic_read(&kvm_guest_has_master_clock) != 0)
6994 queue_work(system_long_wq, &pvclock_gtod_work);
6999 static struct notifier_block pvclock_gtod_notifier = {
7000 .notifier_call = pvclock_gtod_notify,
7004 int kvm_arch_init(void *opaque)
7007 struct kvm_x86_ops *ops = opaque;
7010 printk(KERN_ERR "kvm: already loaded the other module\n");
7015 if (!ops->cpu_has_kvm_support()) {
7016 printk(KERN_ERR "kvm: no hardware support\n");
7020 if (ops->disabled_by_bios()) {
7021 printk(KERN_ERR "kvm: disabled by bios\n");
7027 * KVM explicitly assumes that the guest has an FPU and
7028 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7029 * vCPU's FPU state as a fxregs_state struct.
7031 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7032 printk(KERN_ERR "kvm: inadequate fpu\n");
7038 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7039 __alignof__(struct fpu), SLAB_ACCOUNT,
7041 if (!x86_fpu_cache) {
7042 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7046 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7048 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7049 goto out_free_x86_fpu_cache;
7052 r = kvm_mmu_module_init();
7054 goto out_free_percpu;
7058 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7059 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7060 PT_PRESENT_MASK, 0, sme_me_mask);
7063 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7065 if (boot_cpu_has(X86_FEATURE_XSAVE))
7066 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7069 if (pi_inject_timer == -1)
7070 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7071 #ifdef CONFIG_X86_64
7072 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7074 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7075 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7081 free_percpu(shared_msrs);
7082 out_free_x86_fpu_cache:
7083 kmem_cache_destroy(x86_fpu_cache);
7088 void kvm_arch_exit(void)
7090 #ifdef CONFIG_X86_64
7091 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7092 clear_hv_tscchange_cb();
7095 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7097 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7098 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7099 CPUFREQ_TRANSITION_NOTIFIER);
7100 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7101 #ifdef CONFIG_X86_64
7102 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7105 kvm_mmu_module_exit();
7106 free_percpu(shared_msrs);
7107 kmem_cache_destroy(x86_fpu_cache);
7110 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7112 ++vcpu->stat.halt_exits;
7113 if (lapic_in_kernel(vcpu)) {
7114 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7117 vcpu->run->exit_reason = KVM_EXIT_HLT;
7121 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7123 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7125 int ret = kvm_skip_emulated_instruction(vcpu);
7127 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7128 * KVM_EXIT_DEBUG here.
7130 return kvm_vcpu_halt(vcpu) && ret;
7132 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7134 #ifdef CONFIG_X86_64
7135 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7136 unsigned long clock_type)
7138 struct kvm_clock_pairing clock_pairing;
7139 struct timespec64 ts;
7143 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7144 return -KVM_EOPNOTSUPP;
7146 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7147 return -KVM_EOPNOTSUPP;
7149 clock_pairing.sec = ts.tv_sec;
7150 clock_pairing.nsec = ts.tv_nsec;
7151 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7152 clock_pairing.flags = 0;
7153 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7156 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7157 sizeof(struct kvm_clock_pairing)))
7165 * kvm_pv_kick_cpu_op: Kick a vcpu.
7167 * @apicid - apicid of vcpu to be kicked.
7169 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7171 struct kvm_lapic_irq lapic_irq;
7173 lapic_irq.shorthand = 0;
7174 lapic_irq.dest_mode = 0;
7175 lapic_irq.level = 0;
7176 lapic_irq.dest_id = apicid;
7177 lapic_irq.msi_redir_hint = false;
7179 lapic_irq.delivery_mode = APIC_DM_REMRD;
7180 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7183 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7185 if (!lapic_in_kernel(vcpu)) {
7186 WARN_ON_ONCE(vcpu->arch.apicv_active);
7189 if (!vcpu->arch.apicv_active)
7192 vcpu->arch.apicv_active = false;
7193 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7196 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7198 struct kvm_vcpu *target = NULL;
7199 struct kvm_apic_map *map;
7202 map = rcu_dereference(kvm->arch.apic_map);
7204 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7205 target = map->phys_map[dest_id]->vcpu;
7209 if (target && READ_ONCE(target->ready))
7210 kvm_vcpu_yield_to(target);
7213 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7215 unsigned long nr, a0, a1, a2, a3, ret;
7218 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7219 return kvm_hv_hypercall(vcpu);
7221 nr = kvm_rax_read(vcpu);
7222 a0 = kvm_rbx_read(vcpu);
7223 a1 = kvm_rcx_read(vcpu);
7224 a2 = kvm_rdx_read(vcpu);
7225 a3 = kvm_rsi_read(vcpu);
7227 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7229 op_64_bit = is_64_bit_mode(vcpu);
7238 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7244 case KVM_HC_VAPIC_POLL_IRQ:
7247 case KVM_HC_KICK_CPU:
7248 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7249 kvm_sched_yield(vcpu->kvm, a1);
7252 #ifdef CONFIG_X86_64
7253 case KVM_HC_CLOCK_PAIRING:
7254 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7257 case KVM_HC_SEND_IPI:
7258 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7260 case KVM_HC_SCHED_YIELD:
7261 kvm_sched_yield(vcpu->kvm, a0);
7271 kvm_rax_write(vcpu, ret);
7273 ++vcpu->stat.hypercalls;
7274 return kvm_skip_emulated_instruction(vcpu);
7276 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7278 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7281 char instruction[3];
7282 unsigned long rip = kvm_rip_read(vcpu);
7284 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7286 return emulator_write_emulated(ctxt, rip, instruction, 3,
7290 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7292 return vcpu->run->request_interrupt_window &&
7293 likely(!pic_in_kernel(vcpu->kvm));
7296 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7298 struct kvm_run *kvm_run = vcpu->run;
7300 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7301 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7302 kvm_run->cr8 = kvm_get_cr8(vcpu);
7303 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7304 kvm_run->ready_for_interrupt_injection =
7305 pic_in_kernel(vcpu->kvm) ||
7306 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7309 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7313 if (!kvm_x86_ops->update_cr8_intercept)
7316 if (!lapic_in_kernel(vcpu))
7319 if (vcpu->arch.apicv_active)
7322 if (!vcpu->arch.apic->vapic_addr)
7323 max_irr = kvm_lapic_find_highest_irr(vcpu);
7330 tpr = kvm_lapic_get_cr8(vcpu);
7332 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7335 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7339 /* try to reinject previous events if any */
7341 if (vcpu->arch.exception.injected)
7342 kvm_x86_ops->queue_exception(vcpu);
7344 * Do not inject an NMI or interrupt if there is a pending
7345 * exception. Exceptions and interrupts are recognized at
7346 * instruction boundaries, i.e. the start of an instruction.
7347 * Trap-like exceptions, e.g. #DB, have higher priority than
7348 * NMIs and interrupts, i.e. traps are recognized before an
7349 * NMI/interrupt that's pending on the same instruction.
7350 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7351 * priority, but are only generated (pended) during instruction
7352 * execution, i.e. a pending fault-like exception means the
7353 * fault occurred on the *previous* instruction and must be
7354 * serviced prior to recognizing any new events in order to
7355 * fully complete the previous instruction.
7357 else if (!vcpu->arch.exception.pending) {
7358 if (vcpu->arch.nmi_injected)
7359 kvm_x86_ops->set_nmi(vcpu);
7360 else if (vcpu->arch.interrupt.injected)
7361 kvm_x86_ops->set_irq(vcpu);
7365 * Call check_nested_events() even if we reinjected a previous event
7366 * in order for caller to determine if it should require immediate-exit
7367 * from L2 to L1 due to pending L1 events which require exit
7370 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7371 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7376 /* try to inject new event if pending */
7377 if (vcpu->arch.exception.pending) {
7378 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7379 vcpu->arch.exception.has_error_code,
7380 vcpu->arch.exception.error_code);
7382 WARN_ON_ONCE(vcpu->arch.exception.injected);
7383 vcpu->arch.exception.pending = false;
7384 vcpu->arch.exception.injected = true;
7386 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7387 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7390 if (vcpu->arch.exception.nr == DB_VECTOR) {
7392 * This code assumes that nSVM doesn't use
7393 * check_nested_events(). If it does, the
7394 * DR6/DR7 changes should happen before L1
7395 * gets a #VMEXIT for an intercepted #DB in
7396 * L2. (Under VMX, on the other hand, the
7397 * DR6/DR7 changes should not happen in the
7398 * event of a VM-exit to L1 for an intercepted
7401 kvm_deliver_exception_payload(vcpu);
7402 if (vcpu->arch.dr7 & DR7_GD) {
7403 vcpu->arch.dr7 &= ~DR7_GD;
7404 kvm_update_dr7(vcpu);
7408 kvm_x86_ops->queue_exception(vcpu);
7411 /* Don't consider new event if we re-injected an event */
7412 if (kvm_event_needs_reinjection(vcpu))
7415 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7416 kvm_x86_ops->smi_allowed(vcpu)) {
7417 vcpu->arch.smi_pending = false;
7418 ++vcpu->arch.smi_count;
7420 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7421 --vcpu->arch.nmi_pending;
7422 vcpu->arch.nmi_injected = true;
7423 kvm_x86_ops->set_nmi(vcpu);
7424 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7426 * Because interrupts can be injected asynchronously, we are
7427 * calling check_nested_events again here to avoid a race condition.
7428 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7429 * proposal and current concerns. Perhaps we should be setting
7430 * KVM_REQ_EVENT only on certain events and not unconditionally?
7432 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7433 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7437 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7438 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7440 kvm_x86_ops->set_irq(vcpu);
7447 static void process_nmi(struct kvm_vcpu *vcpu)
7452 * x86 is limited to one NMI running, and one NMI pending after it.
7453 * If an NMI is already in progress, limit further NMIs to just one.
7454 * Otherwise, allow two (and we'll inject the first one immediately).
7456 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7459 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7460 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7461 kvm_make_request(KVM_REQ_EVENT, vcpu);
7464 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7467 flags |= seg->g << 23;
7468 flags |= seg->db << 22;
7469 flags |= seg->l << 21;
7470 flags |= seg->avl << 20;
7471 flags |= seg->present << 15;
7472 flags |= seg->dpl << 13;
7473 flags |= seg->s << 12;
7474 flags |= seg->type << 8;
7478 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7480 struct kvm_segment seg;
7483 kvm_get_segment(vcpu, &seg, n);
7484 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7487 offset = 0x7f84 + n * 12;
7489 offset = 0x7f2c + (n - 3) * 12;
7491 put_smstate(u32, buf, offset + 8, seg.base);
7492 put_smstate(u32, buf, offset + 4, seg.limit);
7493 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7496 #ifdef CONFIG_X86_64
7497 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7499 struct kvm_segment seg;
7503 kvm_get_segment(vcpu, &seg, n);
7504 offset = 0x7e00 + n * 16;
7506 flags = enter_smm_get_segment_flags(&seg) >> 8;
7507 put_smstate(u16, buf, offset, seg.selector);
7508 put_smstate(u16, buf, offset + 2, flags);
7509 put_smstate(u32, buf, offset + 4, seg.limit);
7510 put_smstate(u64, buf, offset + 8, seg.base);
7514 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7517 struct kvm_segment seg;
7521 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7522 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7523 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7524 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7526 for (i = 0; i < 8; i++)
7527 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7529 kvm_get_dr(vcpu, 6, &val);
7530 put_smstate(u32, buf, 0x7fcc, (u32)val);
7531 kvm_get_dr(vcpu, 7, &val);
7532 put_smstate(u32, buf, 0x7fc8, (u32)val);
7534 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7535 put_smstate(u32, buf, 0x7fc4, seg.selector);
7536 put_smstate(u32, buf, 0x7f64, seg.base);
7537 put_smstate(u32, buf, 0x7f60, seg.limit);
7538 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7540 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7541 put_smstate(u32, buf, 0x7fc0, seg.selector);
7542 put_smstate(u32, buf, 0x7f80, seg.base);
7543 put_smstate(u32, buf, 0x7f7c, seg.limit);
7544 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7546 kvm_x86_ops->get_gdt(vcpu, &dt);
7547 put_smstate(u32, buf, 0x7f74, dt.address);
7548 put_smstate(u32, buf, 0x7f70, dt.size);
7550 kvm_x86_ops->get_idt(vcpu, &dt);
7551 put_smstate(u32, buf, 0x7f58, dt.address);
7552 put_smstate(u32, buf, 0x7f54, dt.size);
7554 for (i = 0; i < 6; i++)
7555 enter_smm_save_seg_32(vcpu, buf, i);
7557 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7560 put_smstate(u32, buf, 0x7efc, 0x00020000);
7561 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7564 #ifdef CONFIG_X86_64
7565 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7568 struct kvm_segment seg;
7572 for (i = 0; i < 16; i++)
7573 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7575 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7576 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7578 kvm_get_dr(vcpu, 6, &val);
7579 put_smstate(u64, buf, 0x7f68, val);
7580 kvm_get_dr(vcpu, 7, &val);
7581 put_smstate(u64, buf, 0x7f60, val);
7583 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7584 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7585 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7587 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7590 put_smstate(u32, buf, 0x7efc, 0x00020064);
7592 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7594 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7595 put_smstate(u16, buf, 0x7e90, seg.selector);
7596 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7597 put_smstate(u32, buf, 0x7e94, seg.limit);
7598 put_smstate(u64, buf, 0x7e98, seg.base);
7600 kvm_x86_ops->get_idt(vcpu, &dt);
7601 put_smstate(u32, buf, 0x7e84, dt.size);
7602 put_smstate(u64, buf, 0x7e88, dt.address);
7604 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7605 put_smstate(u16, buf, 0x7e70, seg.selector);
7606 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7607 put_smstate(u32, buf, 0x7e74, seg.limit);
7608 put_smstate(u64, buf, 0x7e78, seg.base);
7610 kvm_x86_ops->get_gdt(vcpu, &dt);
7611 put_smstate(u32, buf, 0x7e64, dt.size);
7612 put_smstate(u64, buf, 0x7e68, dt.address);
7614 for (i = 0; i < 6; i++)
7615 enter_smm_save_seg_64(vcpu, buf, i);
7619 static void enter_smm(struct kvm_vcpu *vcpu)
7621 struct kvm_segment cs, ds;
7626 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7627 memset(buf, 0, 512);
7628 #ifdef CONFIG_X86_64
7629 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7630 enter_smm_save_state_64(vcpu, buf);
7633 enter_smm_save_state_32(vcpu, buf);
7636 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7637 * vCPU state (e.g. leave guest mode) after we've saved the state into
7638 * the SMM state-save area.
7640 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7642 vcpu->arch.hflags |= HF_SMM_MASK;
7643 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7645 if (kvm_x86_ops->get_nmi_mask(vcpu))
7646 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7648 kvm_x86_ops->set_nmi_mask(vcpu, true);
7650 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7651 kvm_rip_write(vcpu, 0x8000);
7653 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7654 kvm_x86_ops->set_cr0(vcpu, cr0);
7655 vcpu->arch.cr0 = cr0;
7657 kvm_x86_ops->set_cr4(vcpu, 0);
7659 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7660 dt.address = dt.size = 0;
7661 kvm_x86_ops->set_idt(vcpu, &dt);
7663 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7665 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7666 cs.base = vcpu->arch.smbase;
7671 cs.limit = ds.limit = 0xffffffff;
7672 cs.type = ds.type = 0x3;
7673 cs.dpl = ds.dpl = 0;
7678 cs.avl = ds.avl = 0;
7679 cs.present = ds.present = 1;
7680 cs.unusable = ds.unusable = 0;
7681 cs.padding = ds.padding = 0;
7683 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7684 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7685 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7686 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7687 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7688 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7690 #ifdef CONFIG_X86_64
7691 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7692 kvm_x86_ops->set_efer(vcpu, 0);
7695 kvm_update_cpuid(vcpu);
7696 kvm_mmu_reset_context(vcpu);
7699 static void process_smi(struct kvm_vcpu *vcpu)
7701 vcpu->arch.smi_pending = true;
7702 kvm_make_request(KVM_REQ_EVENT, vcpu);
7705 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7707 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7710 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7712 if (!kvm_apic_present(vcpu))
7715 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7717 if (irqchip_split(vcpu->kvm))
7718 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7720 if (vcpu->arch.apicv_active)
7721 kvm_x86_ops->sync_pir_to_irr(vcpu);
7722 if (ioapic_in_kernel(vcpu->kvm))
7723 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7726 if (is_guest_mode(vcpu))
7727 vcpu->arch.load_eoi_exitmap_pending = true;
7729 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7732 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7734 u64 eoi_exit_bitmap[4];
7736 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7739 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7740 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7741 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7744 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7745 unsigned long start, unsigned long end,
7748 unsigned long apic_address;
7751 * The physical address of apic access page is stored in the VMCS.
7752 * Update it when it becomes invalid.
7754 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7755 if (start <= apic_address && apic_address < end)
7756 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7761 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7763 struct page *page = NULL;
7765 if (!lapic_in_kernel(vcpu))
7768 if (!kvm_x86_ops->set_apic_access_page_addr)
7771 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7772 if (is_error_page(page))
7774 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7777 * Do not pin apic access page in memory, the MMU notifier
7778 * will call us again if it is migrated or swapped out.
7782 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7784 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7786 smp_send_reschedule(vcpu->cpu);
7788 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7791 * Returns 1 to let vcpu_run() continue the guest execution loop without
7792 * exiting to the userspace. Otherwise, the value will be returned to the
7795 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7799 dm_request_for_irq_injection(vcpu) &&
7800 kvm_cpu_accept_dm_intr(vcpu);
7802 bool req_immediate_exit = false;
7804 if (kvm_request_pending(vcpu)) {
7805 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7806 kvm_x86_ops->get_vmcs12_pages(vcpu);
7807 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7808 kvm_mmu_unload(vcpu);
7809 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7810 __kvm_migrate_timers(vcpu);
7811 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7812 kvm_gen_update_masterclock(vcpu->kvm);
7813 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7814 kvm_gen_kvmclock_update(vcpu);
7815 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7816 r = kvm_guest_time_update(vcpu);
7820 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7821 kvm_mmu_sync_roots(vcpu);
7822 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7823 kvm_mmu_load_cr3(vcpu);
7824 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7825 kvm_vcpu_flush_tlb(vcpu, true);
7826 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7827 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7831 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7832 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7833 vcpu->mmio_needed = 0;
7837 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7838 /* Page is swapped out. Do synthetic halt */
7839 vcpu->arch.apf.halted = true;
7843 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7844 record_steal_time(vcpu);
7845 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7847 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7849 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7850 kvm_pmu_handle_event(vcpu);
7851 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7852 kvm_pmu_deliver_pmi(vcpu);
7853 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7854 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7855 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7856 vcpu->arch.ioapic_handled_vectors)) {
7857 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7858 vcpu->run->eoi.vector =
7859 vcpu->arch.pending_ioapic_eoi;
7864 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7865 vcpu_scan_ioapic(vcpu);
7866 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7867 vcpu_load_eoi_exitmap(vcpu);
7868 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7869 kvm_vcpu_reload_apic_access_page(vcpu);
7870 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7871 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7872 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7876 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7877 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7878 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7882 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7883 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7884 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7890 * KVM_REQ_HV_STIMER has to be processed after
7891 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7892 * depend on the guest clock being up-to-date
7894 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7895 kvm_hv_process_stimers(vcpu);
7898 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7899 ++vcpu->stat.req_event;
7900 kvm_apic_accept_events(vcpu);
7901 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7906 if (inject_pending_event(vcpu, req_int_win) != 0)
7907 req_immediate_exit = true;
7909 /* Enable SMI/NMI/IRQ window open exits if needed.
7911 * SMIs have three cases:
7912 * 1) They can be nested, and then there is nothing to
7913 * do here because RSM will cause a vmexit anyway.
7914 * 2) There is an ISA-specific reason why SMI cannot be
7915 * injected, and the moment when this changes can be
7917 * 3) Or the SMI can be pending because
7918 * inject_pending_event has completed the injection
7919 * of an IRQ or NMI from the previous vmexit, and
7920 * then we request an immediate exit to inject the
7923 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7924 if (!kvm_x86_ops->enable_smi_window(vcpu))
7925 req_immediate_exit = true;
7926 if (vcpu->arch.nmi_pending)
7927 kvm_x86_ops->enable_nmi_window(vcpu);
7928 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7929 kvm_x86_ops->enable_irq_window(vcpu);
7930 WARN_ON(vcpu->arch.exception.pending);
7933 if (kvm_lapic_enabled(vcpu)) {
7934 update_cr8_intercept(vcpu);
7935 kvm_lapic_sync_to_vapic(vcpu);
7939 r = kvm_mmu_reload(vcpu);
7941 goto cancel_injection;
7946 kvm_x86_ops->prepare_guest_switch(vcpu);
7949 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7950 * IPI are then delayed after guest entry, which ensures that they
7951 * result in virtual interrupt delivery.
7953 local_irq_disable();
7954 vcpu->mode = IN_GUEST_MODE;
7956 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7959 * 1) We should set ->mode before checking ->requests. Please see
7960 * the comment in kvm_vcpu_exiting_guest_mode().
7962 * 2) For APICv, we should set ->mode before checking PID.ON. This
7963 * pairs with the memory barrier implicit in pi_test_and_set_on
7964 * (see vmx_deliver_posted_interrupt).
7966 * 3) This also orders the write to mode from any reads to the page
7967 * tables done while the VCPU is running. Please see the comment
7968 * in kvm_flush_remote_tlbs.
7970 smp_mb__after_srcu_read_unlock();
7973 * This handles the case where a posted interrupt was
7974 * notified with kvm_vcpu_kick.
7976 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7977 kvm_x86_ops->sync_pir_to_irr(vcpu);
7979 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7980 || need_resched() || signal_pending(current)) {
7981 vcpu->mode = OUTSIDE_GUEST_MODE;
7985 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7987 goto cancel_injection;
7990 if (req_immediate_exit) {
7991 kvm_make_request(KVM_REQ_EVENT, vcpu);
7992 kvm_x86_ops->request_immediate_exit(vcpu);
7995 trace_kvm_entry(vcpu->vcpu_id);
7996 guest_enter_irqoff();
7998 /* The preempt notifier should have taken care of the FPU already. */
7999 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8001 if (unlikely(vcpu->arch.switch_db_regs)) {
8003 set_debugreg(vcpu->arch.eff_db[0], 0);
8004 set_debugreg(vcpu->arch.eff_db[1], 1);
8005 set_debugreg(vcpu->arch.eff_db[2], 2);
8006 set_debugreg(vcpu->arch.eff_db[3], 3);
8007 set_debugreg(vcpu->arch.dr6, 6);
8008 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8011 kvm_x86_ops->run(vcpu);
8014 * Do this here before restoring debug registers on the host. And
8015 * since we do this before handling the vmexit, a DR access vmexit
8016 * can (a) read the correct value of the debug registers, (b) set
8017 * KVM_DEBUGREG_WONT_EXIT again.
8019 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8020 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8021 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8022 kvm_update_dr0123(vcpu);
8023 kvm_update_dr6(vcpu);
8024 kvm_update_dr7(vcpu);
8025 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8029 * If the guest has used debug registers, at least dr7
8030 * will be disabled while returning to the host.
8031 * If we don't have active breakpoints in the host, we don't
8032 * care about the messed up debug address registers. But if
8033 * we have some of them active, restore the old state.
8035 if (hw_breakpoint_active())
8036 hw_breakpoint_restore();
8038 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8040 vcpu->mode = OUTSIDE_GUEST_MODE;
8043 kvm_x86_ops->handle_exit_irqoff(vcpu);
8046 * Consume any pending interrupts, including the possible source of
8047 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8048 * An instruction is required after local_irq_enable() to fully unblock
8049 * interrupts on processors that implement an interrupt shadow, the
8050 * stat.exits increment will do nicely.
8052 kvm_before_interrupt(vcpu);
8055 local_irq_disable();
8056 kvm_after_interrupt(vcpu);
8058 guest_exit_irqoff();
8059 if (lapic_in_kernel(vcpu)) {
8060 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8061 if (delta != S64_MIN) {
8062 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8063 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8070 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8073 * Profile KVM exit RIPs:
8075 if (unlikely(prof_on == KVM_PROFILING)) {
8076 unsigned long rip = kvm_rip_read(vcpu);
8077 profile_hit(KVM_PROFILING, (void *)rip);
8080 if (unlikely(vcpu->arch.tsc_always_catchup))
8081 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8083 if (vcpu->arch.apic_attention)
8084 kvm_lapic_sync_from_vapic(vcpu);
8086 vcpu->arch.gpa_available = false;
8087 r = kvm_x86_ops->handle_exit(vcpu);
8091 kvm_x86_ops->cancel_injection(vcpu);
8092 if (unlikely(vcpu->arch.apic_attention))
8093 kvm_lapic_sync_from_vapic(vcpu);
8098 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8100 if (!kvm_arch_vcpu_runnable(vcpu) &&
8101 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8102 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8103 kvm_vcpu_block(vcpu);
8104 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8106 if (kvm_x86_ops->post_block)
8107 kvm_x86_ops->post_block(vcpu);
8109 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8113 kvm_apic_accept_events(vcpu);
8114 switch(vcpu->arch.mp_state) {
8115 case KVM_MP_STATE_HALTED:
8116 vcpu->arch.pv.pv_unhalted = false;
8117 vcpu->arch.mp_state =
8118 KVM_MP_STATE_RUNNABLE;
8120 case KVM_MP_STATE_RUNNABLE:
8121 vcpu->arch.apf.halted = false;
8123 case KVM_MP_STATE_INIT_RECEIVED:
8132 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8134 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8135 kvm_x86_ops->check_nested_events(vcpu, false);
8137 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8138 !vcpu->arch.apf.halted);
8141 static int vcpu_run(struct kvm_vcpu *vcpu)
8144 struct kvm *kvm = vcpu->kvm;
8146 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8147 vcpu->arch.l1tf_flush_l1d = true;
8150 if (kvm_vcpu_running(vcpu)) {
8151 r = vcpu_enter_guest(vcpu);
8153 r = vcpu_block(kvm, vcpu);
8159 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8160 if (kvm_cpu_has_pending_timer(vcpu))
8161 kvm_inject_pending_timer_irqs(vcpu);
8163 if (dm_request_for_irq_injection(vcpu) &&
8164 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8166 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8167 ++vcpu->stat.request_irq_exits;
8171 kvm_check_async_pf_completion(vcpu);
8173 if (signal_pending(current)) {
8175 vcpu->run->exit_reason = KVM_EXIT_INTR;
8176 ++vcpu->stat.signal_exits;
8179 if (need_resched()) {
8180 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8182 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8186 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8191 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8194 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8195 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8196 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8197 if (r != EMULATE_DONE)
8202 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8204 BUG_ON(!vcpu->arch.pio.count);
8206 return complete_emulated_io(vcpu);
8210 * Implements the following, as a state machine:
8214 * for each mmio piece in the fragment
8222 * for each mmio piece in the fragment
8227 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8229 struct kvm_run *run = vcpu->run;
8230 struct kvm_mmio_fragment *frag;
8233 BUG_ON(!vcpu->mmio_needed);
8235 /* Complete previous fragment */
8236 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8237 len = min(8u, frag->len);
8238 if (!vcpu->mmio_is_write)
8239 memcpy(frag->data, run->mmio.data, len);
8241 if (frag->len <= 8) {
8242 /* Switch to the next fragment. */
8244 vcpu->mmio_cur_fragment++;
8246 /* Go forward to the next mmio piece. */
8252 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8253 vcpu->mmio_needed = 0;
8255 /* FIXME: return into emulator if single-stepping. */
8256 if (vcpu->mmio_is_write)
8258 vcpu->mmio_read_completed = 1;
8259 return complete_emulated_io(vcpu);
8262 run->exit_reason = KVM_EXIT_MMIO;
8263 run->mmio.phys_addr = frag->gpa;
8264 if (vcpu->mmio_is_write)
8265 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8266 run->mmio.len = min(8u, frag->len);
8267 run->mmio.is_write = vcpu->mmio_is_write;
8268 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8272 /* Swap (qemu) user FPU context for the guest FPU context. */
8273 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8277 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8278 /* PKRU is separately restored in kvm_x86_ops->run. */
8279 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8280 ~XFEATURE_MASK_PKRU);
8282 fpregs_mark_activate();
8288 /* When vcpu_run ends, restore user space FPU context. */
8289 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8293 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8294 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8296 fpregs_mark_activate();
8299 ++vcpu->stat.fpu_reload;
8303 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8308 kvm_sigset_activate(vcpu);
8309 kvm_load_guest_fpu(vcpu);
8311 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8312 if (kvm_run->immediate_exit) {
8316 kvm_vcpu_block(vcpu);
8317 kvm_apic_accept_events(vcpu);
8318 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8320 if (signal_pending(current)) {
8322 vcpu->run->exit_reason = KVM_EXIT_INTR;
8323 ++vcpu->stat.signal_exits;
8328 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8333 if (vcpu->run->kvm_dirty_regs) {
8334 r = sync_regs(vcpu);
8339 /* re-sync apic's tpr */
8340 if (!lapic_in_kernel(vcpu)) {
8341 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8347 if (unlikely(vcpu->arch.complete_userspace_io)) {
8348 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8349 vcpu->arch.complete_userspace_io = NULL;
8354 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8356 if (kvm_run->immediate_exit)
8362 kvm_put_guest_fpu(vcpu);
8363 if (vcpu->run->kvm_valid_regs)
8365 post_kvm_run_save(vcpu);
8366 kvm_sigset_deactivate(vcpu);
8372 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8374 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8376 * We are here if userspace calls get_regs() in the middle of
8377 * instruction emulation. Registers state needs to be copied
8378 * back from emulation context to vcpu. Userspace shouldn't do
8379 * that usually, but some bad designed PV devices (vmware
8380 * backdoor interface) need this to work
8382 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8383 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8385 regs->rax = kvm_rax_read(vcpu);
8386 regs->rbx = kvm_rbx_read(vcpu);
8387 regs->rcx = kvm_rcx_read(vcpu);
8388 regs->rdx = kvm_rdx_read(vcpu);
8389 regs->rsi = kvm_rsi_read(vcpu);
8390 regs->rdi = kvm_rdi_read(vcpu);
8391 regs->rsp = kvm_rsp_read(vcpu);
8392 regs->rbp = kvm_rbp_read(vcpu);
8393 #ifdef CONFIG_X86_64
8394 regs->r8 = kvm_r8_read(vcpu);
8395 regs->r9 = kvm_r9_read(vcpu);
8396 regs->r10 = kvm_r10_read(vcpu);
8397 regs->r11 = kvm_r11_read(vcpu);
8398 regs->r12 = kvm_r12_read(vcpu);
8399 regs->r13 = kvm_r13_read(vcpu);
8400 regs->r14 = kvm_r14_read(vcpu);
8401 regs->r15 = kvm_r15_read(vcpu);
8404 regs->rip = kvm_rip_read(vcpu);
8405 regs->rflags = kvm_get_rflags(vcpu);
8408 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8411 __get_regs(vcpu, regs);
8416 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8418 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8419 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8421 kvm_rax_write(vcpu, regs->rax);
8422 kvm_rbx_write(vcpu, regs->rbx);
8423 kvm_rcx_write(vcpu, regs->rcx);
8424 kvm_rdx_write(vcpu, regs->rdx);
8425 kvm_rsi_write(vcpu, regs->rsi);
8426 kvm_rdi_write(vcpu, regs->rdi);
8427 kvm_rsp_write(vcpu, regs->rsp);
8428 kvm_rbp_write(vcpu, regs->rbp);
8429 #ifdef CONFIG_X86_64
8430 kvm_r8_write(vcpu, regs->r8);
8431 kvm_r9_write(vcpu, regs->r9);
8432 kvm_r10_write(vcpu, regs->r10);
8433 kvm_r11_write(vcpu, regs->r11);
8434 kvm_r12_write(vcpu, regs->r12);
8435 kvm_r13_write(vcpu, regs->r13);
8436 kvm_r14_write(vcpu, regs->r14);
8437 kvm_r15_write(vcpu, regs->r15);
8440 kvm_rip_write(vcpu, regs->rip);
8441 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8443 vcpu->arch.exception.pending = false;
8445 kvm_make_request(KVM_REQ_EVENT, vcpu);
8448 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8451 __set_regs(vcpu, regs);
8456 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8458 struct kvm_segment cs;
8460 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8464 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8466 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8470 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8471 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8472 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8473 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8474 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8475 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8477 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8478 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8480 kvm_x86_ops->get_idt(vcpu, &dt);
8481 sregs->idt.limit = dt.size;
8482 sregs->idt.base = dt.address;
8483 kvm_x86_ops->get_gdt(vcpu, &dt);
8484 sregs->gdt.limit = dt.size;
8485 sregs->gdt.base = dt.address;
8487 sregs->cr0 = kvm_read_cr0(vcpu);
8488 sregs->cr2 = vcpu->arch.cr2;
8489 sregs->cr3 = kvm_read_cr3(vcpu);
8490 sregs->cr4 = kvm_read_cr4(vcpu);
8491 sregs->cr8 = kvm_get_cr8(vcpu);
8492 sregs->efer = vcpu->arch.efer;
8493 sregs->apic_base = kvm_get_apic_base(vcpu);
8495 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8497 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8498 set_bit(vcpu->arch.interrupt.nr,
8499 (unsigned long *)sregs->interrupt_bitmap);
8502 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8503 struct kvm_sregs *sregs)
8506 __get_sregs(vcpu, sregs);
8511 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8512 struct kvm_mp_state *mp_state)
8516 kvm_apic_accept_events(vcpu);
8517 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8518 vcpu->arch.pv.pv_unhalted)
8519 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8521 mp_state->mp_state = vcpu->arch.mp_state;
8527 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8528 struct kvm_mp_state *mp_state)
8534 if (!lapic_in_kernel(vcpu) &&
8535 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8538 /* INITs are latched while in SMM */
8539 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8540 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8541 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8544 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8545 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8546 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8548 vcpu->arch.mp_state = mp_state->mp_state;
8549 kvm_make_request(KVM_REQ_EVENT, vcpu);
8557 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8558 int reason, bool has_error_code, u32 error_code)
8560 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8563 init_emulate_ctxt(vcpu);
8565 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8566 has_error_code, error_code);
8569 return EMULATE_FAIL;
8571 kvm_rip_write(vcpu, ctxt->eip);
8572 kvm_set_rflags(vcpu, ctxt->eflags);
8573 kvm_make_request(KVM_REQ_EVENT, vcpu);
8574 return EMULATE_DONE;
8576 EXPORT_SYMBOL_GPL(kvm_task_switch);
8578 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8580 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8581 (sregs->cr4 & X86_CR4_OSXSAVE))
8584 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8586 * When EFER.LME and CR0.PG are set, the processor is in
8587 * 64-bit mode (though maybe in a 32-bit code segment).
8588 * CR4.PAE and EFER.LMA must be set.
8590 if (!(sregs->cr4 & X86_CR4_PAE)
8591 || !(sregs->efer & EFER_LMA))
8595 * Not in 64-bit mode: EFER.LMA is clear and the code
8596 * segment cannot be 64-bit.
8598 if (sregs->efer & EFER_LMA || sregs->cs.l)
8605 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8607 struct msr_data apic_base_msr;
8608 int mmu_reset_needed = 0;
8609 int cpuid_update_needed = 0;
8610 int pending_vec, max_bits, idx;
8614 if (kvm_valid_sregs(vcpu, sregs))
8617 apic_base_msr.data = sregs->apic_base;
8618 apic_base_msr.host_initiated = true;
8619 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8622 dt.size = sregs->idt.limit;
8623 dt.address = sregs->idt.base;
8624 kvm_x86_ops->set_idt(vcpu, &dt);
8625 dt.size = sregs->gdt.limit;
8626 dt.address = sregs->gdt.base;
8627 kvm_x86_ops->set_gdt(vcpu, &dt);
8629 vcpu->arch.cr2 = sregs->cr2;
8630 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8631 vcpu->arch.cr3 = sregs->cr3;
8632 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8634 kvm_set_cr8(vcpu, sregs->cr8);
8636 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8637 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8639 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8640 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8641 vcpu->arch.cr0 = sregs->cr0;
8643 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8644 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8645 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8646 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8647 if (cpuid_update_needed)
8648 kvm_update_cpuid(vcpu);
8650 idx = srcu_read_lock(&vcpu->kvm->srcu);
8651 if (is_pae_paging(vcpu)) {
8652 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8653 mmu_reset_needed = 1;
8655 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8657 if (mmu_reset_needed)
8658 kvm_mmu_reset_context(vcpu);
8660 max_bits = KVM_NR_INTERRUPTS;
8661 pending_vec = find_first_bit(
8662 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8663 if (pending_vec < max_bits) {
8664 kvm_queue_interrupt(vcpu, pending_vec, false);
8665 pr_debug("Set back pending irq %d\n", pending_vec);
8668 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8669 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8670 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8671 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8672 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8673 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8675 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8676 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8678 update_cr8_intercept(vcpu);
8680 /* Older userspace won't unhalt the vcpu on reset. */
8681 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8682 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8684 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8686 kvm_make_request(KVM_REQ_EVENT, vcpu);
8693 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8694 struct kvm_sregs *sregs)
8699 ret = __set_sregs(vcpu, sregs);
8704 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8705 struct kvm_guest_debug *dbg)
8707 unsigned long rflags;
8712 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8714 if (vcpu->arch.exception.pending)
8716 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8717 kvm_queue_exception(vcpu, DB_VECTOR);
8719 kvm_queue_exception(vcpu, BP_VECTOR);
8723 * Read rflags as long as potentially injected trace flags are still
8726 rflags = kvm_get_rflags(vcpu);
8728 vcpu->guest_debug = dbg->control;
8729 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8730 vcpu->guest_debug = 0;
8732 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8733 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8734 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8735 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8737 for (i = 0; i < KVM_NR_DB_REGS; i++)
8738 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8740 kvm_update_dr7(vcpu);
8742 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8743 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8744 get_segment_base(vcpu, VCPU_SREG_CS);
8747 * Trigger an rflags update that will inject or remove the trace
8750 kvm_set_rflags(vcpu, rflags);
8752 kvm_x86_ops->update_bp_intercept(vcpu);
8762 * Translate a guest virtual address to a guest physical address.
8764 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8765 struct kvm_translation *tr)
8767 unsigned long vaddr = tr->linear_address;
8773 idx = srcu_read_lock(&vcpu->kvm->srcu);
8774 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8775 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8776 tr->physical_address = gpa;
8777 tr->valid = gpa != UNMAPPED_GVA;
8785 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8787 struct fxregs_state *fxsave;
8791 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8792 memcpy(fpu->fpr, fxsave->st_space, 128);
8793 fpu->fcw = fxsave->cwd;
8794 fpu->fsw = fxsave->swd;
8795 fpu->ftwx = fxsave->twd;
8796 fpu->last_opcode = fxsave->fop;
8797 fpu->last_ip = fxsave->rip;
8798 fpu->last_dp = fxsave->rdp;
8799 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8805 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8807 struct fxregs_state *fxsave;
8811 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8813 memcpy(fxsave->st_space, fpu->fpr, 128);
8814 fxsave->cwd = fpu->fcw;
8815 fxsave->swd = fpu->fsw;
8816 fxsave->twd = fpu->ftwx;
8817 fxsave->fop = fpu->last_opcode;
8818 fxsave->rip = fpu->last_ip;
8819 fxsave->rdp = fpu->last_dp;
8820 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8826 static void store_regs(struct kvm_vcpu *vcpu)
8828 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8830 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8831 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8833 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8834 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8836 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8837 kvm_vcpu_ioctl_x86_get_vcpu_events(
8838 vcpu, &vcpu->run->s.regs.events);
8841 static int sync_regs(struct kvm_vcpu *vcpu)
8843 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8846 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8847 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8848 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8850 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8851 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8853 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8855 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8856 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8857 vcpu, &vcpu->run->s.regs.events))
8859 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8865 static void fx_init(struct kvm_vcpu *vcpu)
8867 fpstate_init(&vcpu->arch.guest_fpu->state);
8868 if (boot_cpu_has(X86_FEATURE_XSAVES))
8869 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8870 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8873 * Ensure guest xcr0 is valid for loading
8875 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8877 vcpu->arch.cr0 |= X86_CR0_ET;
8880 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8882 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8884 kvmclock_reset(vcpu);
8886 kvm_x86_ops->vcpu_free(vcpu);
8887 free_cpumask_var(wbinvd_dirty_mask);
8890 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8893 struct kvm_vcpu *vcpu;
8895 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8896 printk_once(KERN_WARNING
8897 "kvm: SMP vm created on host with unstable TSC; "
8898 "guest TSC will not be reliable\n");
8900 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8905 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8907 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8908 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8909 kvm_vcpu_mtrr_init(vcpu);
8911 kvm_vcpu_reset(vcpu, false);
8912 kvm_init_mmu(vcpu, false);
8917 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8919 struct msr_data msr;
8920 struct kvm *kvm = vcpu->kvm;
8922 kvm_hv_vcpu_postcreate(vcpu);
8924 if (mutex_lock_killable(&vcpu->mutex))
8928 msr.index = MSR_IA32_TSC;
8929 msr.host_initiated = true;
8930 kvm_write_tsc(vcpu, &msr);
8933 /* poll control enabled by default */
8934 vcpu->arch.msr_kvm_poll_control = 1;
8936 mutex_unlock(&vcpu->mutex);
8938 if (!kvmclock_periodic_sync)
8941 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8942 KVMCLOCK_SYNC_PERIOD);
8945 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8947 vcpu->arch.apf.msr_val = 0;
8950 kvm_mmu_unload(vcpu);
8953 kvm_x86_ops->vcpu_free(vcpu);
8956 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8958 kvm_lapic_reset(vcpu, init_event);
8960 vcpu->arch.hflags = 0;
8962 vcpu->arch.smi_pending = 0;
8963 vcpu->arch.smi_count = 0;
8964 atomic_set(&vcpu->arch.nmi_queued, 0);
8965 vcpu->arch.nmi_pending = 0;
8966 vcpu->arch.nmi_injected = false;
8967 kvm_clear_interrupt_queue(vcpu);
8968 kvm_clear_exception_queue(vcpu);
8969 vcpu->arch.exception.pending = false;
8971 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8972 kvm_update_dr0123(vcpu);
8973 vcpu->arch.dr6 = DR6_INIT;
8974 kvm_update_dr6(vcpu);
8975 vcpu->arch.dr7 = DR7_FIXED_1;
8976 kvm_update_dr7(vcpu);
8980 kvm_make_request(KVM_REQ_EVENT, vcpu);
8981 vcpu->arch.apf.msr_val = 0;
8982 vcpu->arch.st.msr_val = 0;
8984 kvmclock_reset(vcpu);
8986 kvm_clear_async_pf_completion_queue(vcpu);
8987 kvm_async_pf_hash_reset(vcpu);
8988 vcpu->arch.apf.halted = false;
8990 if (kvm_mpx_supported()) {
8991 void *mpx_state_buffer;
8994 * To avoid have the INIT path from kvm_apic_has_events() that be
8995 * called with loaded FPU and does not let userspace fix the state.
8998 kvm_put_guest_fpu(vcpu);
8999 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9001 if (mpx_state_buffer)
9002 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9003 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9005 if (mpx_state_buffer)
9006 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9008 kvm_load_guest_fpu(vcpu);
9012 kvm_pmu_reset(vcpu);
9013 vcpu->arch.smbase = 0x30000;
9015 vcpu->arch.msr_misc_features_enables = 0;
9017 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9020 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9021 vcpu->arch.regs_avail = ~0;
9022 vcpu->arch.regs_dirty = ~0;
9024 vcpu->arch.ia32_xss = 0;
9026 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9029 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9031 struct kvm_segment cs;
9033 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9034 cs.selector = vector << 8;
9035 cs.base = vector << 12;
9036 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9037 kvm_rip_write(vcpu, 0);
9040 int kvm_arch_hardware_enable(void)
9043 struct kvm_vcpu *vcpu;
9048 bool stable, backwards_tsc = false;
9050 kvm_shared_msr_cpu_online();
9051 ret = kvm_x86_ops->hardware_enable();
9055 local_tsc = rdtsc();
9056 stable = !kvm_check_tsc_unstable();
9057 list_for_each_entry(kvm, &vm_list, vm_list) {
9058 kvm_for_each_vcpu(i, vcpu, kvm) {
9059 if (!stable && vcpu->cpu == smp_processor_id())
9060 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9061 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9062 backwards_tsc = true;
9063 if (vcpu->arch.last_host_tsc > max_tsc)
9064 max_tsc = vcpu->arch.last_host_tsc;
9070 * Sometimes, even reliable TSCs go backwards. This happens on
9071 * platforms that reset TSC during suspend or hibernate actions, but
9072 * maintain synchronization. We must compensate. Fortunately, we can
9073 * detect that condition here, which happens early in CPU bringup,
9074 * before any KVM threads can be running. Unfortunately, we can't
9075 * bring the TSCs fully up to date with real time, as we aren't yet far
9076 * enough into CPU bringup that we know how much real time has actually
9077 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9078 * variables that haven't been updated yet.
9080 * So we simply find the maximum observed TSC above, then record the
9081 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9082 * the adjustment will be applied. Note that we accumulate
9083 * adjustments, in case multiple suspend cycles happen before some VCPU
9084 * gets a chance to run again. In the event that no KVM threads get a
9085 * chance to run, we will miss the entire elapsed period, as we'll have
9086 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9087 * loose cycle time. This isn't too big a deal, since the loss will be
9088 * uniform across all VCPUs (not to mention the scenario is extremely
9089 * unlikely). It is possible that a second hibernate recovery happens
9090 * much faster than a first, causing the observed TSC here to be
9091 * smaller; this would require additional padding adjustment, which is
9092 * why we set last_host_tsc to the local tsc observed here.
9094 * N.B. - this code below runs only on platforms with reliable TSC,
9095 * as that is the only way backwards_tsc is set above. Also note
9096 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9097 * have the same delta_cyc adjustment applied if backwards_tsc
9098 * is detected. Note further, this adjustment is only done once,
9099 * as we reset last_host_tsc on all VCPUs to stop this from being
9100 * called multiple times (one for each physical CPU bringup).
9102 * Platforms with unreliable TSCs don't have to deal with this, they
9103 * will be compensated by the logic in vcpu_load, which sets the TSC to
9104 * catchup mode. This will catchup all VCPUs to real time, but cannot
9105 * guarantee that they stay in perfect synchronization.
9107 if (backwards_tsc) {
9108 u64 delta_cyc = max_tsc - local_tsc;
9109 list_for_each_entry(kvm, &vm_list, vm_list) {
9110 kvm->arch.backwards_tsc_observed = true;
9111 kvm_for_each_vcpu(i, vcpu, kvm) {
9112 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9113 vcpu->arch.last_host_tsc = local_tsc;
9114 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9118 * We have to disable TSC offset matching.. if you were
9119 * booting a VM while issuing an S4 host suspend....
9120 * you may have some problem. Solving this issue is
9121 * left as an exercise to the reader.
9123 kvm->arch.last_tsc_nsec = 0;
9124 kvm->arch.last_tsc_write = 0;
9131 void kvm_arch_hardware_disable(void)
9133 kvm_x86_ops->hardware_disable();
9134 drop_user_return_notifiers();
9137 int kvm_arch_hardware_setup(void)
9141 r = kvm_x86_ops->hardware_setup();
9145 if (kvm_has_tsc_control) {
9147 * Make sure the user can only configure tsc_khz values that
9148 * fit into a signed integer.
9149 * A min value is not calculated because it will always
9150 * be 1 on all machines.
9152 u64 max = min(0x7fffffffULL,
9153 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9154 kvm_max_guest_tsc_khz = max;
9156 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9159 kvm_init_msr_list();
9163 void kvm_arch_hardware_unsetup(void)
9165 kvm_x86_ops->hardware_unsetup();
9168 int kvm_arch_check_processor_compat(void)
9170 return kvm_x86_ops->check_processor_compatibility();
9173 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9175 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9177 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9179 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9181 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9184 struct static_key kvm_no_apic_vcpu __read_mostly;
9185 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9187 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9192 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9193 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9194 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9196 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9198 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9203 vcpu->arch.pio_data = page_address(page);
9205 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9207 r = kvm_mmu_create(vcpu);
9209 goto fail_free_pio_data;
9211 if (irqchip_in_kernel(vcpu->kvm)) {
9212 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9213 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9215 goto fail_mmu_destroy;
9217 static_key_slow_inc(&kvm_no_apic_vcpu);
9219 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9220 GFP_KERNEL_ACCOUNT);
9221 if (!vcpu->arch.mce_banks) {
9223 goto fail_free_lapic;
9225 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9227 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9228 GFP_KERNEL_ACCOUNT)) {
9230 goto fail_free_mce_banks;
9235 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9237 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9239 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9241 kvm_async_pf_hash_reset(vcpu);
9244 vcpu->arch.pending_external_vector = -1;
9245 vcpu->arch.preempted_in_kernel = false;
9247 kvm_hv_vcpu_init(vcpu);
9251 fail_free_mce_banks:
9252 kfree(vcpu->arch.mce_banks);
9254 kvm_free_lapic(vcpu);
9256 kvm_mmu_destroy(vcpu);
9258 free_page((unsigned long)vcpu->arch.pio_data);
9263 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9267 kvm_hv_vcpu_uninit(vcpu);
9268 kvm_pmu_destroy(vcpu);
9269 kfree(vcpu->arch.mce_banks);
9270 kvm_free_lapic(vcpu);
9271 idx = srcu_read_lock(&vcpu->kvm->srcu);
9272 kvm_mmu_destroy(vcpu);
9273 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9274 free_page((unsigned long)vcpu->arch.pio_data);
9275 if (!lapic_in_kernel(vcpu))
9276 static_key_slow_dec(&kvm_no_apic_vcpu);
9279 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9281 vcpu->arch.l1tf_flush_l1d = true;
9282 kvm_x86_ops->sched_in(vcpu, cpu);
9285 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9290 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9291 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9292 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9293 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9295 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9296 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9297 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9298 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9299 &kvm->arch.irq_sources_bitmap);
9301 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9302 mutex_init(&kvm->arch.apic_map_lock);
9303 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9305 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9306 pvclock_update_vm_gtod_copy(kvm);
9308 kvm->arch.guest_can_read_msr_platform_info = true;
9310 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9311 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9313 kvm_hv_init_vm(kvm);
9314 kvm_page_track_init(kvm);
9315 kvm_mmu_init_vm(kvm);
9317 if (kvm_x86_ops->vm_init)
9318 return kvm_x86_ops->vm_init(kvm);
9323 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9326 kvm_mmu_unload(vcpu);
9330 static void kvm_free_vcpus(struct kvm *kvm)
9333 struct kvm_vcpu *vcpu;
9336 * Unpin any mmu pages first.
9338 kvm_for_each_vcpu(i, vcpu, kvm) {
9339 kvm_clear_async_pf_completion_queue(vcpu);
9340 kvm_unload_vcpu_mmu(vcpu);
9342 kvm_for_each_vcpu(i, vcpu, kvm)
9343 kvm_arch_vcpu_free(vcpu);
9345 mutex_lock(&kvm->lock);
9346 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9347 kvm->vcpus[i] = NULL;
9349 atomic_set(&kvm->online_vcpus, 0);
9350 mutex_unlock(&kvm->lock);
9353 void kvm_arch_sync_events(struct kvm *kvm)
9355 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9356 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9360 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9364 struct kvm_memslots *slots = kvm_memslots(kvm);
9365 struct kvm_memory_slot *slot, old;
9367 /* Called with kvm->slots_lock held. */
9368 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9371 slot = id_to_memslot(slots, id);
9377 * MAP_SHARED to prevent internal slot pages from being moved
9380 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9381 MAP_SHARED | MAP_ANONYMOUS, 0);
9382 if (IS_ERR((void *)hva))
9383 return PTR_ERR((void *)hva);
9392 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9393 struct kvm_userspace_memory_region m;
9395 m.slot = id | (i << 16);
9397 m.guest_phys_addr = gpa;
9398 m.userspace_addr = hva;
9399 m.memory_size = size;
9400 r = __kvm_set_memory_region(kvm, &m);
9406 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9410 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9412 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9416 mutex_lock(&kvm->slots_lock);
9417 r = __x86_set_memory_region(kvm, id, gpa, size);
9418 mutex_unlock(&kvm->slots_lock);
9422 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9424 void kvm_arch_destroy_vm(struct kvm *kvm)
9426 if (current->mm == kvm->mm) {
9428 * Free memory regions allocated on behalf of userspace,
9429 * unless the the memory map has changed due to process exit
9432 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9433 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9434 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9436 if (kvm_x86_ops->vm_destroy)
9437 kvm_x86_ops->vm_destroy(kvm);
9438 kvm_pic_destroy(kvm);
9439 kvm_ioapic_destroy(kvm);
9440 kvm_free_vcpus(kvm);
9441 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9442 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9443 kvm_mmu_uninit_vm(kvm);
9444 kvm_page_track_cleanup(kvm);
9445 kvm_hv_destroy_vm(kvm);
9448 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9449 struct kvm_memory_slot *dont)
9453 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9454 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9455 kvfree(free->arch.rmap[i]);
9456 free->arch.rmap[i] = NULL;
9461 if (!dont || free->arch.lpage_info[i - 1] !=
9462 dont->arch.lpage_info[i - 1]) {
9463 kvfree(free->arch.lpage_info[i - 1]);
9464 free->arch.lpage_info[i - 1] = NULL;
9468 kvm_page_track_free_memslot(free, dont);
9471 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9472 unsigned long npages)
9476 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9477 struct kvm_lpage_info *linfo;
9482 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9483 slot->base_gfn, level) + 1;
9485 slot->arch.rmap[i] =
9486 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9487 GFP_KERNEL_ACCOUNT);
9488 if (!slot->arch.rmap[i])
9493 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9497 slot->arch.lpage_info[i - 1] = linfo;
9499 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9500 linfo[0].disallow_lpage = 1;
9501 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9502 linfo[lpages - 1].disallow_lpage = 1;
9503 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9505 * If the gfn and userspace address are not aligned wrt each
9506 * other, or if explicitly asked to, disable large page
9507 * support for this slot
9509 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9510 !kvm_largepages_enabled()) {
9513 for (j = 0; j < lpages; ++j)
9514 linfo[j].disallow_lpage = 1;
9518 if (kvm_page_track_create_memslot(slot, npages))
9524 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9525 kvfree(slot->arch.rmap[i]);
9526 slot->arch.rmap[i] = NULL;
9530 kvfree(slot->arch.lpage_info[i - 1]);
9531 slot->arch.lpage_info[i - 1] = NULL;
9536 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9539 * memslots->generation has been incremented.
9540 * mmio generation may have reached its maximum value.
9542 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9545 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9546 struct kvm_memory_slot *memslot,
9547 const struct kvm_userspace_memory_region *mem,
9548 enum kvm_mr_change change)
9553 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9554 struct kvm_memory_slot *new)
9556 /* Still write protect RO slot */
9557 if (new->flags & KVM_MEM_READONLY) {
9558 kvm_mmu_slot_remove_write_access(kvm, new);
9563 * Call kvm_x86_ops dirty logging hooks when they are valid.
9565 * kvm_x86_ops->slot_disable_log_dirty is called when:
9567 * - KVM_MR_CREATE with dirty logging is disabled
9568 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9570 * The reason is, in case of PML, we need to set D-bit for any slots
9571 * with dirty logging disabled in order to eliminate unnecessary GPA
9572 * logging in PML buffer (and potential PML buffer full VMEXT). This
9573 * guarantees leaving PML enabled during guest's lifetime won't have
9574 * any additional overhead from PML when guest is running with dirty
9575 * logging disabled for memory slots.
9577 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9578 * to dirty logging mode.
9580 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9582 * In case of write protect:
9584 * Write protect all pages for dirty logging.
9586 * All the sptes including the large sptes which point to this
9587 * slot are set to readonly. We can not create any new large
9588 * spte on this slot until the end of the logging.
9590 * See the comments in fast_page_fault().
9592 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9593 if (kvm_x86_ops->slot_enable_log_dirty)
9594 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9596 kvm_mmu_slot_remove_write_access(kvm, new);
9598 if (kvm_x86_ops->slot_disable_log_dirty)
9599 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9603 void kvm_arch_commit_memory_region(struct kvm *kvm,
9604 const struct kvm_userspace_memory_region *mem,
9605 const struct kvm_memory_slot *old,
9606 const struct kvm_memory_slot *new,
9607 enum kvm_mr_change change)
9609 if (!kvm->arch.n_requested_mmu_pages)
9610 kvm_mmu_change_mmu_pages(kvm,
9611 kvm_mmu_calculate_default_mmu_pages(kvm));
9614 * Dirty logging tracks sptes in 4k granularity, meaning that large
9615 * sptes have to be split. If live migration is successful, the guest
9616 * in the source machine will be destroyed and large sptes will be
9617 * created in the destination. However, if the guest continues to run
9618 * in the source machine (for example if live migration fails), small
9619 * sptes will remain around and cause bad performance.
9621 * Scan sptes if dirty logging has been stopped, dropping those
9622 * which can be collapsed into a single large-page spte. Later
9623 * page faults will create the large-page sptes.
9625 if ((change != KVM_MR_DELETE) &&
9626 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9627 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9628 kvm_mmu_zap_collapsible_sptes(kvm, new);
9631 * Set up write protection and/or dirty logging for the new slot.
9633 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9634 * been zapped so no dirty logging staff is needed for old slot. For
9635 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9636 * new and it's also covered when dealing with the new slot.
9638 * FIXME: const-ify all uses of struct kvm_memory_slot.
9640 if (change != KVM_MR_DELETE)
9641 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9644 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9646 kvm_mmu_zap_all(kvm);
9649 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9650 struct kvm_memory_slot *slot)
9652 kvm_page_track_flush_slot(kvm, slot);
9655 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9657 return (is_guest_mode(vcpu) &&
9658 kvm_x86_ops->guest_apic_has_interrupt &&
9659 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9662 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9664 if (!list_empty_careful(&vcpu->async_pf.done))
9667 if (kvm_apic_has_events(vcpu))
9670 if (vcpu->arch.pv.pv_unhalted)
9673 if (vcpu->arch.exception.pending)
9676 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9677 (vcpu->arch.nmi_pending &&
9678 kvm_x86_ops->nmi_allowed(vcpu)))
9681 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9682 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9685 if (kvm_arch_interrupt_allowed(vcpu) &&
9686 (kvm_cpu_has_interrupt(vcpu) ||
9687 kvm_guest_apic_has_interrupt(vcpu)))
9690 if (kvm_hv_has_stimer_pending(vcpu))
9696 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9698 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9701 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9703 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9706 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9707 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9708 kvm_test_request(KVM_REQ_EVENT, vcpu))
9711 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9717 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9719 return vcpu->arch.preempted_in_kernel;
9722 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9724 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9727 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9729 return kvm_x86_ops->interrupt_allowed(vcpu);
9732 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9734 if (is_64_bit_mode(vcpu))
9735 return kvm_rip_read(vcpu);
9736 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9737 kvm_rip_read(vcpu));
9739 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9741 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9743 return kvm_get_linear_rip(vcpu) == linear_rip;
9745 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9747 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9749 unsigned long rflags;
9751 rflags = kvm_x86_ops->get_rflags(vcpu);
9752 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9753 rflags &= ~X86_EFLAGS_TF;
9756 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9758 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9760 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9761 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9762 rflags |= X86_EFLAGS_TF;
9763 kvm_x86_ops->set_rflags(vcpu, rflags);
9766 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9768 __kvm_set_rflags(vcpu, rflags);
9769 kvm_make_request(KVM_REQ_EVENT, vcpu);
9771 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9773 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9777 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9781 r = kvm_mmu_reload(vcpu);
9785 if (!vcpu->arch.mmu->direct_map &&
9786 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9789 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9792 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9794 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9797 static inline u32 kvm_async_pf_next_probe(u32 key)
9799 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9802 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9804 u32 key = kvm_async_pf_hash_fn(gfn);
9806 while (vcpu->arch.apf.gfns[key] != ~0)
9807 key = kvm_async_pf_next_probe(key);
9809 vcpu->arch.apf.gfns[key] = gfn;
9812 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9815 u32 key = kvm_async_pf_hash_fn(gfn);
9817 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9818 (vcpu->arch.apf.gfns[key] != gfn &&
9819 vcpu->arch.apf.gfns[key] != ~0); i++)
9820 key = kvm_async_pf_next_probe(key);
9825 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9827 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9830 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9834 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9836 vcpu->arch.apf.gfns[i] = ~0;
9838 j = kvm_async_pf_next_probe(j);
9839 if (vcpu->arch.apf.gfns[j] == ~0)
9841 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9843 * k lies cyclically in ]i,j]
9845 * |....j i.k.| or |.k..j i...|
9847 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9848 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9853 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9856 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9860 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9863 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9867 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9869 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9872 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9873 (vcpu->arch.apf.send_user_only &&
9874 kvm_x86_ops->get_cpl(vcpu) == 0))
9880 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9882 if (unlikely(!lapic_in_kernel(vcpu) ||
9883 kvm_event_needs_reinjection(vcpu) ||
9884 vcpu->arch.exception.pending))
9887 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9891 * If interrupts are off we cannot even use an artificial
9894 return kvm_x86_ops->interrupt_allowed(vcpu);
9897 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9898 struct kvm_async_pf *work)
9900 struct x86_exception fault;
9902 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9903 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9905 if (kvm_can_deliver_async_pf(vcpu) &&
9906 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9907 fault.vector = PF_VECTOR;
9908 fault.error_code_valid = true;
9909 fault.error_code = 0;
9910 fault.nested_page_fault = false;
9911 fault.address = work->arch.token;
9912 fault.async_page_fault = true;
9913 kvm_inject_page_fault(vcpu, &fault);
9916 * It is not possible to deliver a paravirtualized asynchronous
9917 * page fault, but putting the guest in an artificial halt state
9918 * can be beneficial nevertheless: if an interrupt arrives, we
9919 * can deliver it timely and perhaps the guest will schedule
9920 * another process. When the instruction that triggered a page
9921 * fault is retried, hopefully the page will be ready in the host.
9923 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9927 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9928 struct kvm_async_pf *work)
9930 struct x86_exception fault;
9933 if (work->wakeup_all)
9934 work->arch.token = ~0; /* broadcast wakeup */
9936 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9937 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9939 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9940 !apf_get_user(vcpu, &val)) {
9941 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9942 vcpu->arch.exception.pending &&
9943 vcpu->arch.exception.nr == PF_VECTOR &&
9944 !apf_put_user(vcpu, 0)) {
9945 vcpu->arch.exception.injected = false;
9946 vcpu->arch.exception.pending = false;
9947 vcpu->arch.exception.nr = 0;
9948 vcpu->arch.exception.has_error_code = false;
9949 vcpu->arch.exception.error_code = 0;
9950 vcpu->arch.exception.has_payload = false;
9951 vcpu->arch.exception.payload = 0;
9952 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9953 fault.vector = PF_VECTOR;
9954 fault.error_code_valid = true;
9955 fault.error_code = 0;
9956 fault.nested_page_fault = false;
9957 fault.address = work->arch.token;
9958 fault.async_page_fault = true;
9959 kvm_inject_page_fault(vcpu, &fault);
9962 vcpu->arch.apf.halted = false;
9963 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9966 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9968 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9971 return kvm_can_do_async_pf(vcpu);
9974 void kvm_arch_start_assignment(struct kvm *kvm)
9976 atomic_inc(&kvm->arch.assigned_device_count);
9978 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9980 void kvm_arch_end_assignment(struct kvm *kvm)
9982 atomic_dec(&kvm->arch.assigned_device_count);
9984 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9986 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9988 return atomic_read(&kvm->arch.assigned_device_count);
9990 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9992 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9994 atomic_inc(&kvm->arch.noncoherent_dma_count);
9996 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9998 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10000 atomic_dec(&kvm->arch.noncoherent_dma_count);
10002 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10004 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10006 return atomic_read(&kvm->arch.noncoherent_dma_count);
10008 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10010 bool kvm_arch_has_irq_bypass(void)
10012 return kvm_x86_ops->update_pi_irte != NULL;
10015 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10016 struct irq_bypass_producer *prod)
10018 struct kvm_kernel_irqfd *irqfd =
10019 container_of(cons, struct kvm_kernel_irqfd, consumer);
10021 irqfd->producer = prod;
10023 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10024 prod->irq, irqfd->gsi, 1);
10027 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10028 struct irq_bypass_producer *prod)
10031 struct kvm_kernel_irqfd *irqfd =
10032 container_of(cons, struct kvm_kernel_irqfd, consumer);
10034 WARN_ON(irqfd->producer != prod);
10035 irqfd->producer = NULL;
10038 * When producer of consumer is unregistered, we change back to
10039 * remapped mode, so we can re-use the current implementation
10040 * when the irq is masked/disabled or the consumer side (KVM
10041 * int this case doesn't want to receive the interrupts.
10043 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10045 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10046 " fails: %d\n", irqfd->consumer.token, ret);
10049 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10050 uint32_t guest_irq, bool set)
10052 if (!kvm_x86_ops->update_pi_irte)
10055 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10058 bool kvm_vector_hashing_enabled(void)
10060 return vector_hashing;
10062 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10064 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10066 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10068 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10071 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10072 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10073 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10074 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10075 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10076 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10077 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10078 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10079 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10080 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10081 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10082 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10083 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10084 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10085 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
10086 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10087 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10088 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10089 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);