1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/export.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <linux/kvm_irqfd.h>
52 #include <linux/irqbypass.h>
53 #include <linux/sched/stat.h>
54 #include <linux/sched/isolation.h>
55 #include <linux/mem_encrypt.h>
57 #include <trace/events/kvm.h>
59 #include <asm/debugreg.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68 #include <asm/mshyperv.h>
69 #include <asm/hypervisor.h>
70 #include <asm/intel_pt.h>
71 #include <clocksource/hyperv_timer.h>
73 #define CREATE_TRACE_POINTS
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 #define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32 __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64 __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
144 static int __read_mostly lapic_timer_advance_ns = -1;
145 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
147 static bool __read_mostly vector_hashing = true;
148 module_param(vector_hashing, bool, S_IRUGO);
150 bool __read_mostly enable_vmware_backdoor = false;
151 module_param(enable_vmware_backdoor, bool, S_IRUGO);
152 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
154 static bool __read_mostly force_emulation_prefix = false;
155 module_param(force_emulation_prefix, bool, S_IRUGO);
157 int __read_mostly pi_inject_timer = -1;
158 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
160 #define KVM_NR_SHARED_MSRS 16
162 struct kvm_shared_msrs_global {
164 u32 msrs[KVM_NR_SHARED_MSRS];
167 struct kvm_shared_msrs {
168 struct user_return_notifier urn;
170 struct kvm_shared_msr_values {
173 } values[KVM_NR_SHARED_MSRS];
176 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
177 static struct kvm_shared_msrs __percpu *shared_msrs;
179 struct kvm_stats_debugfs_item debugfs_entries[] = {
180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
190 { "halt_exits", VCPU_STAT(halt_exits) },
191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
195 { "hypercalls", VCPU_STAT(hypercalls) },
196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
202 { "irq_injections", VCPU_STAT(irq_injections) },
203 { "nmi_injections", VCPU_STAT(nmi_injections) },
204 { "req_event", VCPU_STAT(req_event) },
205 { "l1d_flush", VCPU_STAT(l1d_flush) },
206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
213 { "mmu_unsync", VM_STAT(mmu_unsync) },
214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
215 { "largepages", VM_STAT(lpages) },
216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
221 u64 __read_mostly host_xcr0;
223 struct kmem_cache *x86_fpu_cache;
224 EXPORT_SYMBOL_GPL(x86_fpu_cache);
226 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
228 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
235 static void kvm_on_user_return(struct user_return_notifier *urn)
238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
240 struct kvm_shared_msr_values *values;
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
252 local_irq_restore(flags);
253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
262 static void shared_msr_update(unsigned slot, u32 msr)
265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
279 void kvm_define_shared_msr(unsigned slot, u32 msr)
281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
282 shared_msrs_global.msrs[slot] = msr;
283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
286 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
288 static void kvm_shared_msr_cpu_online(void)
292 for (i = 0; i < shared_msrs_global.nr; ++i)
293 shared_msr_update(i, shared_msrs_global.msrs[i]);
296 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
304 smsr->values[slot].curr = value;
305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
316 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
318 static void drop_user_return_notifiers(void)
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
327 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
329 return vcpu->arch.apic_base;
331 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
333 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
337 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
339 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
355 kvm_lapic_set_base(vcpu, msr_info->data);
358 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
360 asmlinkage __visible void kvm_spurious_fault(void)
362 /* Fault while not rebooting. We want the trace. */
365 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
367 #define EXCPT_BENIGN 0
368 #define EXCPT_CONTRIBUTORY 1
371 static int exception_class(int vector)
381 return EXCPT_CONTRIBUTORY;
388 #define EXCPT_FAULT 0
390 #define EXCPT_ABORT 2
391 #define EXCPT_INTERRUPT 3
393 static int exception_type(int vector)
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
409 /* Reserved exceptions will result in fault */
413 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
446 vcpu->arch.cr2 = payload;
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
453 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
455 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
456 unsigned nr, bool has_error, u32 error_code,
457 bool has_payload, unsigned long payload, bool reinject)
462 kvm_make_request(KVM_REQ_EVENT, vcpu);
464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
466 if (has_error && !is_protmode(vcpu))
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
479 if (WARN_ON_ONCE(has_payload)) {
481 * A reinjected event has already
482 * delivered its payload.
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
529 vcpu->arch.exception.pending = true;
530 vcpu->arch.exception.injected = false;
531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
543 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
547 EXPORT_SYMBOL_GPL(kvm_queue_exception);
549 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
553 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
555 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
561 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
568 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
571 kvm_inject_gp(vcpu, 0);
573 return kvm_skip_emulated_instruction(vcpu);
577 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
579 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
581 ++vcpu->stat.pf_guest;
582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
584 if (vcpu->arch.exception.nested_apf) {
585 vcpu->arch.apf.nested_apf_token = fault->address;
586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
592 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
594 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
601 return fault->nested_page_fault;
604 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
609 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
611 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
615 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
617 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
621 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
627 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
634 EXPORT_SYMBOL_GPL(kvm_require_cpl);
636 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
641 kvm_queue_exception(vcpu, UD_VECTOR);
644 EXPORT_SYMBOL_GPL(kvm_require_dr);
647 * This function will be used to read from the physical memory of the currently
648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
649 * can read from guest physical or from the guest's guest physical memory.
651 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
655 struct x86_exception exception;
659 ngpa = gfn_to_gpa(ngfn);
660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
661 if (real_gfn == UNMAPPED_GVA)
664 real_gfn = gpa_to_gfn(real_gfn);
666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
668 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
670 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
671 void *data, int offset, int len, u32 access)
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
678 * Load the pae pdptrs. Return true is they are all valid.
680 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
682 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
683 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
686 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
688 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
689 offset * sizeof(u64), sizeof(pdpte),
690 PFERR_USER_MASK|PFERR_WRITE_MASK);
695 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
696 if ((pdpte[i] & PT_PRESENT_MASK) &&
698 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
705 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_avail);
708 __set_bit(VCPU_EXREG_PDPTR,
709 (unsigned long *)&vcpu->arch.regs_dirty);
714 EXPORT_SYMBOL_GPL(load_pdptrs);
716 bool pdptrs_changed(struct kvm_vcpu *vcpu)
718 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
724 if (!is_pae_paging(vcpu))
727 if (!test_bit(VCPU_EXREG_PDPTR,
728 (unsigned long *)&vcpu->arch.regs_avail))
731 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
732 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
733 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
734 PFERR_USER_MASK | PFERR_WRITE_MASK);
737 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
742 EXPORT_SYMBOL_GPL(pdptrs_changed);
744 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
746 unsigned long old_cr0 = kvm_read_cr0(vcpu);
747 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
752 if (cr0 & 0xffffffff00000000UL)
756 cr0 &= ~CR0_RESERVED_BITS;
758 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
761 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
764 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
766 if ((vcpu->arch.efer & EFER_LME)) {
771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
776 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
781 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
784 kvm_x86_ops->set_cr0(vcpu, cr0);
786 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
787 kvm_clear_async_pf_completion_queue(vcpu);
788 kvm_async_pf_hash_reset(vcpu);
791 if ((cr0 ^ old_cr0) & update_bits)
792 kvm_mmu_reset_context(vcpu);
794 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
795 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
796 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
797 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
801 EXPORT_SYMBOL_GPL(kvm_set_cr0);
803 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
805 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
807 EXPORT_SYMBOL_GPL(kvm_lmsw);
809 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
811 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
812 !vcpu->guest_xcr0_loaded) {
813 /* kvm_set_xcr() also depends on this */
814 if (vcpu->arch.xcr0 != host_xcr0)
815 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
816 vcpu->guest_xcr0_loaded = 1;
819 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
821 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
823 if (vcpu->guest_xcr0_loaded) {
824 if (vcpu->arch.xcr0 != host_xcr0)
825 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
826 vcpu->guest_xcr0_loaded = 0;
829 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
831 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
834 u64 old_xcr0 = vcpu->arch.xcr0;
837 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
838 if (index != XCR_XFEATURE_ENABLED_MASK)
840 if (!(xcr0 & XFEATURE_MASK_FP))
842 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
846 * Do not allow the guest to set bits that we do not support
847 * saving. However, xcr0 bit 0 is always set, even if the
848 * emulated CPU does not support XSAVE (see fx_init).
850 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
851 if (xcr0 & ~valid_bits)
854 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
855 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
858 if (xcr0 & XFEATURE_MASK_AVX512) {
859 if (!(xcr0 & XFEATURE_MASK_YMM))
861 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
864 vcpu->arch.xcr0 = xcr0;
866 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
867 kvm_update_cpuid(vcpu);
871 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
873 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
874 __kvm_set_xcr(vcpu, index, xcr)) {
875 kvm_inject_gp(vcpu, 0);
880 EXPORT_SYMBOL_GPL(kvm_set_xcr);
882 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
884 unsigned long old_cr4 = kvm_read_cr4(vcpu);
885 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
886 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
888 if (cr4 & CR4_RESERVED_BITS)
891 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
894 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
897 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
900 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
903 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
906 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
909 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
912 if (is_long_mode(vcpu)) {
913 if (!(cr4 & X86_CR4_PAE))
915 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
916 && ((cr4 ^ old_cr4) & pdptr_bits)
917 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
921 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
922 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
925 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
926 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
930 if (kvm_x86_ops->set_cr4(vcpu, cr4))
933 if (((cr4 ^ old_cr4) & pdptr_bits) ||
934 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
935 kvm_mmu_reset_context(vcpu);
937 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
938 kvm_update_cpuid(vcpu);
942 EXPORT_SYMBOL_GPL(kvm_set_cr4);
944 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
946 bool skip_tlb_flush = false;
948 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
951 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
952 cr3 &= ~X86_CR3_PCID_NOFLUSH;
956 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
957 if (!skip_tlb_flush) {
958 kvm_mmu_sync_roots(vcpu);
959 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
964 if (is_long_mode(vcpu) &&
965 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
967 else if (is_pae_paging(vcpu) &&
968 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
971 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
972 vcpu->arch.cr3 = cr3;
973 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
977 EXPORT_SYMBOL_GPL(kvm_set_cr3);
979 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
981 if (cr8 & CR8_RESERVED_BITS)
983 if (lapic_in_kernel(vcpu))
984 kvm_lapic_set_tpr(vcpu, cr8);
986 vcpu->arch.cr8 = cr8;
989 EXPORT_SYMBOL_GPL(kvm_set_cr8);
991 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
993 if (lapic_in_kernel(vcpu))
994 return kvm_lapic_get_cr8(vcpu);
996 return vcpu->arch.cr8;
998 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1000 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1004 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1005 for (i = 0; i < KVM_NR_DB_REGS; i++)
1006 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1007 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1011 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1013 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1014 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1017 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022 dr7 = vcpu->arch.guest_debug_dr7;
1024 dr7 = vcpu->arch.dr7;
1025 kvm_x86_ops->set_dr7(vcpu, dr7);
1026 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1027 if (dr7 & DR7_BP_EN_MASK)
1028 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1031 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1033 u64 fixed = DR6_FIXED_1;
1035 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1040 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1044 vcpu->arch.db[dr] = val;
1045 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1046 vcpu->arch.eff_db[dr] = val;
1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
1053 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1054 kvm_update_dr6(vcpu);
1059 if (val & 0xffffffff00000000ULL)
1060 return -1; /* #GP */
1061 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1062 kvm_update_dr7(vcpu);
1069 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1071 if (__kvm_set_dr(vcpu, dr, val)) {
1072 kvm_inject_gp(vcpu, 0);
1077 EXPORT_SYMBOL_GPL(kvm_set_dr);
1079 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1083 *val = vcpu->arch.db[dr];
1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 *val = vcpu->arch.dr6;
1091 *val = kvm_x86_ops->get_dr6(vcpu);
1096 *val = vcpu->arch.dr7;
1101 EXPORT_SYMBOL_GPL(kvm_get_dr);
1103 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1105 u32 ecx = kvm_rcx_read(vcpu);
1109 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1112 kvm_rax_write(vcpu, (u32)data);
1113 kvm_rdx_write(vcpu, data >> 32);
1116 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1119 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1120 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1122 * This list is modified at module load time to reflect the
1123 * capabilities of the host cpu. This capabilities test skips MSRs that are
1124 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1125 * may depend on host virtualization features rather than host cpu features.
1128 static u32 msrs_to_save[] = {
1129 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1131 #ifdef CONFIG_X86_64
1132 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1134 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1135 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1137 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1138 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1139 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1140 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1141 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1142 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1145 static unsigned num_msrs_to_save;
1147 static u32 emulated_msrs[] = {
1148 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1149 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1150 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1151 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1152 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1153 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1154 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1156 HV_X64_MSR_VP_INDEX,
1157 HV_X64_MSR_VP_RUNTIME,
1158 HV_X64_MSR_SCONTROL,
1159 HV_X64_MSR_STIMER0_CONFIG,
1160 HV_X64_MSR_VP_ASSIST_PAGE,
1161 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1162 HV_X64_MSR_TSC_EMULATION_STATUS,
1164 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1167 MSR_IA32_TSC_ADJUST,
1168 MSR_IA32_TSCDEADLINE,
1169 MSR_IA32_ARCH_CAPABILITIES,
1170 MSR_IA32_MISC_ENABLE,
1171 MSR_IA32_MCG_STATUS,
1173 MSR_IA32_MCG_EXT_CTL,
1177 MSR_MISC_FEATURES_ENABLES,
1178 MSR_AMD64_VIRT_SPEC_CTRL,
1182 * The following list leaves out MSRs whose values are determined
1183 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1184 * We always support the "true" VMX control MSRs, even if the host
1185 * processor does not, so I am putting these registers here rather
1186 * than in msrs_to_save.
1189 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1191 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1194 MSR_IA32_VMX_CR0_FIXED0,
1195 MSR_IA32_VMX_CR4_FIXED0,
1196 MSR_IA32_VMX_VMCS_ENUM,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 MSR_IA32_VMX_EPT_VPID_CAP,
1199 MSR_IA32_VMX_VMFUNC,
1202 MSR_KVM_POLL_CONTROL,
1205 static unsigned num_emulated_msrs;
1208 * List of msr numbers which are used to expose MSR-based features that
1209 * can be used by a hypervisor to validate requested CPU features.
1211 static u32 msr_based_features[] = {
1213 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1214 MSR_IA32_VMX_PINBASED_CTLS,
1215 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1216 MSR_IA32_VMX_PROCBASED_CTLS,
1217 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 MSR_IA32_VMX_EXIT_CTLS,
1219 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1220 MSR_IA32_VMX_ENTRY_CTLS,
1222 MSR_IA32_VMX_CR0_FIXED0,
1223 MSR_IA32_VMX_CR0_FIXED1,
1224 MSR_IA32_VMX_CR4_FIXED0,
1225 MSR_IA32_VMX_CR4_FIXED1,
1226 MSR_IA32_VMX_VMCS_ENUM,
1227 MSR_IA32_VMX_PROCBASED_CTLS2,
1228 MSR_IA32_VMX_EPT_VPID_CAP,
1229 MSR_IA32_VMX_VMFUNC,
1233 MSR_IA32_ARCH_CAPABILITIES,
1236 static unsigned int num_msr_based_features;
1238 static u64 kvm_get_arch_capabilities(void)
1242 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1243 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1246 * If we're doing cache flushes (either "always" or "cond")
1247 * we will do one whenever the guest does a vmlaunch/vmresume.
1248 * If an outer hypervisor is doing the cache flush for us
1249 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1250 * capability to the guest too, and if EPT is disabled we're not
1251 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1252 * require a nested hypervisor to do a flush of its own.
1254 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1255 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1257 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1258 data |= ARCH_CAP_RDCL_NO;
1259 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1260 data |= ARCH_CAP_SSB_NO;
1261 if (!boot_cpu_has_bug(X86_BUG_MDS))
1262 data |= ARCH_CAP_MDS_NO;
1267 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1269 switch (msr->index) {
1270 case MSR_IA32_ARCH_CAPABILITIES:
1271 msr->data = kvm_get_arch_capabilities();
1273 case MSR_IA32_UCODE_REV:
1274 rdmsrl_safe(msr->index, &msr->data);
1277 if (kvm_x86_ops->get_msr_feature(msr))
1283 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1285 struct kvm_msr_entry msr;
1289 r = kvm_get_msr_feature(&msr);
1298 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1300 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1303 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1306 if (efer & (EFER_LME | EFER_LMA) &&
1307 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1310 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1316 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1318 if (efer & efer_reserved_bits)
1321 return __kvm_valid_efer(vcpu, efer);
1323 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1325 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1327 u64 old_efer = vcpu->arch.efer;
1328 u64 efer = msr_info->data;
1330 if (efer & efer_reserved_bits)
1333 if (!msr_info->host_initiated) {
1334 if (!__kvm_valid_efer(vcpu, efer))
1337 if (is_paging(vcpu) &&
1338 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1343 efer |= vcpu->arch.efer & EFER_LMA;
1345 kvm_x86_ops->set_efer(vcpu, efer);
1347 /* Update reserved bits */
1348 if ((efer ^ old_efer) & EFER_NX)
1349 kvm_mmu_reset_context(vcpu);
1354 void kvm_enable_efer_bits(u64 mask)
1356 efer_reserved_bits &= ~mask;
1358 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1361 * Writes msr value into into the appropriate "register".
1362 * Returns 0 on success, non-0 otherwise.
1363 * Assumes vcpu_load() was already called.
1365 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1367 switch (msr->index) {
1370 case MSR_KERNEL_GS_BASE:
1373 if (is_noncanonical_address(msr->data, vcpu))
1376 case MSR_IA32_SYSENTER_EIP:
1377 case MSR_IA32_SYSENTER_ESP:
1379 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1380 * non-canonical address is written on Intel but not on
1381 * AMD (which ignores the top 32-bits, because it does
1382 * not implement 64-bit SYSENTER).
1384 * 64-bit code should hence be able to write a non-canonical
1385 * value on AMD. Making the address canonical ensures that
1386 * vmentry does not fail on Intel after writing a non-canonical
1387 * value, and that something deterministic happens if the guest
1388 * invokes 64-bit SYSENTER.
1390 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1392 return kvm_x86_ops->set_msr(vcpu, msr);
1394 EXPORT_SYMBOL_GPL(kvm_set_msr);
1397 * Adapt set_msr() to msr_io()'s calling convention
1399 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1401 struct msr_data msr;
1405 msr.host_initiated = true;
1406 r = kvm_get_msr(vcpu, &msr);
1414 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1416 struct msr_data msr;
1420 msr.host_initiated = true;
1421 return kvm_set_msr(vcpu, &msr);
1424 #ifdef CONFIG_X86_64
1425 struct pvclock_gtod_data {
1428 struct { /* extract of a clocksource struct */
1441 static struct pvclock_gtod_data pvclock_gtod_data;
1443 static void update_pvclock_gtod(struct timekeeper *tk)
1445 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1448 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1450 write_seqcount_begin(&vdata->seq);
1452 /* copy pvclock gtod data */
1453 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1454 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1455 vdata->clock.mask = tk->tkr_mono.mask;
1456 vdata->clock.mult = tk->tkr_mono.mult;
1457 vdata->clock.shift = tk->tkr_mono.shift;
1459 vdata->boot_ns = boot_ns;
1460 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1462 vdata->wall_time_sec = tk->xtime_sec;
1464 write_seqcount_end(&vdata->seq);
1468 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1470 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1471 kvm_vcpu_kick(vcpu);
1474 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1478 struct pvclock_wall_clock wc;
1479 struct timespec64 boot;
1484 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1489 ++version; /* first time write, random junk */
1493 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1497 * The guest calculates current wall clock time by adding
1498 * system time (updated by kvm_guest_time_update below) to the
1499 * wall clock specified here. guest system time equals host
1500 * system time for us, thus we must fill in host boot time here.
1502 getboottime64(&boot);
1504 if (kvm->arch.kvmclock_offset) {
1505 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1506 boot = timespec64_sub(boot, ts);
1508 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1509 wc.nsec = boot.tv_nsec;
1510 wc.version = version;
1512 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1515 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1518 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1520 do_shl32_div32(dividend, divisor);
1524 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1525 s8 *pshift, u32 *pmultiplier)
1533 scaled64 = scaled_hz;
1534 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1539 tps32 = (uint32_t)tps64;
1540 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1541 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1549 *pmultiplier = div_frac(scaled64, tps32);
1552 #ifdef CONFIG_X86_64
1553 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1556 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1557 static unsigned long max_tsc_khz;
1559 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1561 u64 v = (u64)khz * (1000000 + ppm);
1566 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1570 /* Guest TSC same frequency as host TSC? */
1572 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1576 /* TSC scaling supported? */
1577 if (!kvm_has_tsc_control) {
1578 if (user_tsc_khz > tsc_khz) {
1579 vcpu->arch.tsc_catchup = 1;
1580 vcpu->arch.tsc_always_catchup = 1;
1583 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1588 /* TSC scaling required - calculate ratio */
1589 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1590 user_tsc_khz, tsc_khz);
1592 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1593 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1598 vcpu->arch.tsc_scaling_ratio = ratio;
1602 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1604 u32 thresh_lo, thresh_hi;
1605 int use_scaling = 0;
1607 /* tsc_khz can be zero if TSC calibration fails */
1608 if (user_tsc_khz == 0) {
1609 /* set tsc_scaling_ratio to a safe value */
1610 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1614 /* Compute a scale to convert nanoseconds in TSC cycles */
1615 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1616 &vcpu->arch.virtual_tsc_shift,
1617 &vcpu->arch.virtual_tsc_mult);
1618 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1621 * Compute the variation in TSC rate which is acceptable
1622 * within the range of tolerance and decide if the
1623 * rate being applied is within that bounds of the hardware
1624 * rate. If so, no scaling or compensation need be done.
1626 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1627 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1628 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1629 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1632 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1635 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1637 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1638 vcpu->arch.virtual_tsc_mult,
1639 vcpu->arch.virtual_tsc_shift);
1640 tsc += vcpu->arch.this_tsc_write;
1644 static inline int gtod_is_based_on_tsc(int mode)
1646 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1649 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1651 #ifdef CONFIG_X86_64
1653 struct kvm_arch *ka = &vcpu->kvm->arch;
1654 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1656 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1657 atomic_read(&vcpu->kvm->online_vcpus));
1660 * Once the masterclock is enabled, always perform request in
1661 * order to update it.
1663 * In order to enable masterclock, the host clocksource must be TSC
1664 * and the vcpus need to have matched TSCs. When that happens,
1665 * perform request to enable masterclock.
1667 if (ka->use_master_clock ||
1668 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1669 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1671 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1672 atomic_read(&vcpu->kvm->online_vcpus),
1673 ka->use_master_clock, gtod->clock.vclock_mode);
1677 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1679 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1680 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1684 * Multiply tsc by a fixed point number represented by ratio.
1686 * The most significant 64-N bits (mult) of ratio represent the
1687 * integral part of the fixed point number; the remaining N bits
1688 * (frac) represent the fractional part, ie. ratio represents a fixed
1689 * point number (mult + frac * 2^(-N)).
1691 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1693 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1695 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1698 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1701 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1703 if (ratio != kvm_default_tsc_scaling_ratio)
1704 _tsc = __scale_tsc(ratio, tsc);
1708 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1710 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1714 tsc = kvm_scale_tsc(vcpu, rdtsc());
1716 return target_tsc - tsc;
1719 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1721 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1723 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1725 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1727 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1729 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1732 static inline bool kvm_check_tsc_unstable(void)
1734 #ifdef CONFIG_X86_64
1736 * TSC is marked unstable when we're running on Hyper-V,
1737 * 'TSC page' clocksource is good.
1739 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1742 return check_tsc_unstable();
1745 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1747 struct kvm *kvm = vcpu->kvm;
1748 u64 offset, ns, elapsed;
1749 unsigned long flags;
1751 bool already_matched;
1752 u64 data = msr->data;
1753 bool synchronizing = false;
1755 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1756 offset = kvm_compute_tsc_offset(vcpu, data);
1757 ns = ktime_get_boottime_ns();
1758 elapsed = ns - kvm->arch.last_tsc_nsec;
1760 if (vcpu->arch.virtual_tsc_khz) {
1761 if (data == 0 && msr->host_initiated) {
1763 * detection of vcpu initialization -- need to sync
1764 * with other vCPUs. This particularly helps to keep
1765 * kvm_clock stable after CPU hotplug
1767 synchronizing = true;
1769 u64 tsc_exp = kvm->arch.last_tsc_write +
1770 nsec_to_cycles(vcpu, elapsed);
1771 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1773 * Special case: TSC write with a small delta (1 second)
1774 * of virtual cycle time against real time is
1775 * interpreted as an attempt to synchronize the CPU.
1777 synchronizing = data < tsc_exp + tsc_hz &&
1778 data + tsc_hz > tsc_exp;
1783 * For a reliable TSC, we can match TSC offsets, and for an unstable
1784 * TSC, we add elapsed time in this computation. We could let the
1785 * compensation code attempt to catch up if we fall behind, but
1786 * it's better to try to match offsets from the beginning.
1788 if (synchronizing &&
1789 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1790 if (!kvm_check_tsc_unstable()) {
1791 offset = kvm->arch.cur_tsc_offset;
1793 u64 delta = nsec_to_cycles(vcpu, elapsed);
1795 offset = kvm_compute_tsc_offset(vcpu, data);
1798 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1801 * We split periods of matched TSC writes into generations.
1802 * For each generation, we track the original measured
1803 * nanosecond time, offset, and write, so if TSCs are in
1804 * sync, we can match exact offset, and if not, we can match
1805 * exact software computation in compute_guest_tsc()
1807 * These values are tracked in kvm->arch.cur_xxx variables.
1809 kvm->arch.cur_tsc_generation++;
1810 kvm->arch.cur_tsc_nsec = ns;
1811 kvm->arch.cur_tsc_write = data;
1812 kvm->arch.cur_tsc_offset = offset;
1817 * We also track th most recent recorded KHZ, write and time to
1818 * allow the matching interval to be extended at each write.
1820 kvm->arch.last_tsc_nsec = ns;
1821 kvm->arch.last_tsc_write = data;
1822 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1824 vcpu->arch.last_guest_tsc = data;
1826 /* Keep track of which generation this VCPU has synchronized to */
1827 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1828 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1829 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1831 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1832 update_ia32_tsc_adjust_msr(vcpu, offset);
1834 kvm_vcpu_write_tsc_offset(vcpu, offset);
1835 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1837 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1839 kvm->arch.nr_vcpus_matched_tsc = 0;
1840 } else if (!already_matched) {
1841 kvm->arch.nr_vcpus_matched_tsc++;
1844 kvm_track_tsc_matching(vcpu);
1845 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1848 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1850 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1853 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1854 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1857 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1859 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1860 WARN_ON(adjustment < 0);
1861 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1862 adjust_tsc_offset_guest(vcpu, adjustment);
1865 #ifdef CONFIG_X86_64
1867 static u64 read_tsc(void)
1869 u64 ret = (u64)rdtsc_ordered();
1870 u64 last = pvclock_gtod_data.clock.cycle_last;
1872 if (likely(ret >= last))
1876 * GCC likes to generate cmov here, but this branch is extremely
1877 * predictable (it's just a function of time and the likely is
1878 * very likely) and there's a data dependence, so force GCC
1879 * to generate a branch instead. I don't barrier() because
1880 * we don't actually need a barrier, and if this function
1881 * ever gets inlined it will generate worse code.
1887 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1890 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1893 switch (gtod->clock.vclock_mode) {
1894 case VCLOCK_HVCLOCK:
1895 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1897 if (tsc_pg_val != U64_MAX) {
1898 /* TSC page valid */
1899 *mode = VCLOCK_HVCLOCK;
1900 v = (tsc_pg_val - gtod->clock.cycle_last) &
1903 /* TSC page invalid */
1904 *mode = VCLOCK_NONE;
1909 *tsc_timestamp = read_tsc();
1910 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1914 *mode = VCLOCK_NONE;
1917 if (*mode == VCLOCK_NONE)
1918 *tsc_timestamp = v = 0;
1920 return v * gtod->clock.mult;
1923 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1925 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1931 seq = read_seqcount_begin(>od->seq);
1932 ns = gtod->nsec_base;
1933 ns += vgettsc(tsc_timestamp, &mode);
1934 ns >>= gtod->clock.shift;
1935 ns += gtod->boot_ns;
1936 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1942 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1944 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1950 seq = read_seqcount_begin(>od->seq);
1951 ts->tv_sec = gtod->wall_time_sec;
1952 ns = gtod->nsec_base;
1953 ns += vgettsc(tsc_timestamp, &mode);
1954 ns >>= gtod->clock.shift;
1955 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1957 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1963 /* returns true if host is using TSC based clocksource */
1964 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1966 /* checked again under seqlock below */
1967 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1970 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1974 /* returns true if host is using TSC based clocksource */
1975 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1978 /* checked again under seqlock below */
1979 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1982 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1988 * Assuming a stable TSC across physical CPUS, and a stable TSC
1989 * across virtual CPUs, the following condition is possible.
1990 * Each numbered line represents an event visible to both
1991 * CPUs at the next numbered event.
1993 * "timespecX" represents host monotonic time. "tscX" represents
1996 * VCPU0 on CPU0 | VCPU1 on CPU1
1998 * 1. read timespec0,tsc0
1999 * 2. | timespec1 = timespec0 + N
2001 * 3. transition to guest | transition to guest
2002 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2003 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2004 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2006 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2009 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2011 * - 0 < N - M => M < N
2013 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2014 * always the case (the difference between two distinct xtime instances
2015 * might be smaller then the difference between corresponding TSC reads,
2016 * when updating guest vcpus pvclock areas).
2018 * To avoid that problem, do not allow visibility of distinct
2019 * system_timestamp/tsc_timestamp values simultaneously: use a master
2020 * copy of host monotonic time values. Update that master copy
2023 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2027 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2029 #ifdef CONFIG_X86_64
2030 struct kvm_arch *ka = &kvm->arch;
2032 bool host_tsc_clocksource, vcpus_matched;
2034 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2035 atomic_read(&kvm->online_vcpus));
2038 * If the host uses TSC clock, then passthrough TSC as stable
2041 host_tsc_clocksource = kvm_get_time_and_clockread(
2042 &ka->master_kernel_ns,
2043 &ka->master_cycle_now);
2045 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2046 && !ka->backwards_tsc_observed
2047 && !ka->boot_vcpu_runs_old_kvmclock;
2049 if (ka->use_master_clock)
2050 atomic_set(&kvm_guest_has_master_clock, 1);
2052 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2053 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2058 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2060 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2063 static void kvm_gen_update_masterclock(struct kvm *kvm)
2065 #ifdef CONFIG_X86_64
2067 struct kvm_vcpu *vcpu;
2068 struct kvm_arch *ka = &kvm->arch;
2070 spin_lock(&ka->pvclock_gtod_sync_lock);
2071 kvm_make_mclock_inprogress_request(kvm);
2072 /* no guest entries from this point */
2073 pvclock_update_vm_gtod_copy(kvm);
2075 kvm_for_each_vcpu(i, vcpu, kvm)
2076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2078 /* guest entries allowed */
2079 kvm_for_each_vcpu(i, vcpu, kvm)
2080 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2082 spin_unlock(&ka->pvclock_gtod_sync_lock);
2086 u64 get_kvmclock_ns(struct kvm *kvm)
2088 struct kvm_arch *ka = &kvm->arch;
2089 struct pvclock_vcpu_time_info hv_clock;
2092 spin_lock(&ka->pvclock_gtod_sync_lock);
2093 if (!ka->use_master_clock) {
2094 spin_unlock(&ka->pvclock_gtod_sync_lock);
2095 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2098 hv_clock.tsc_timestamp = ka->master_cycle_now;
2099 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2100 spin_unlock(&ka->pvclock_gtod_sync_lock);
2102 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2105 if (__this_cpu_read(cpu_tsc_khz)) {
2106 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2107 &hv_clock.tsc_shift,
2108 &hv_clock.tsc_to_system_mul);
2109 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2111 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2118 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2120 struct kvm_vcpu_arch *vcpu = &v->arch;
2121 struct pvclock_vcpu_time_info guest_hv_clock;
2123 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2124 &guest_hv_clock, sizeof(guest_hv_clock))))
2127 /* This VCPU is paused, but it's legal for a guest to read another
2128 * VCPU's kvmclock, so we really have to follow the specification where
2129 * it says that version is odd if data is being modified, and even after
2132 * Version field updates must be kept separate. This is because
2133 * kvm_write_guest_cached might use a "rep movs" instruction, and
2134 * writes within a string instruction are weakly ordered. So there
2135 * are three writes overall.
2137 * As a small optimization, only write the version field in the first
2138 * and third write. The vcpu->pv_time cache is still valid, because the
2139 * version field is the first in the struct.
2141 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2143 if (guest_hv_clock.version & 1)
2144 ++guest_hv_clock.version; /* first time write, random junk */
2146 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2147 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2149 sizeof(vcpu->hv_clock.version));
2153 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2154 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2156 if (vcpu->pvclock_set_guest_stopped_request) {
2157 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2158 vcpu->pvclock_set_guest_stopped_request = false;
2161 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2163 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2165 sizeof(vcpu->hv_clock));
2169 vcpu->hv_clock.version++;
2170 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2172 sizeof(vcpu->hv_clock.version));
2175 static int kvm_guest_time_update(struct kvm_vcpu *v)
2177 unsigned long flags, tgt_tsc_khz;
2178 struct kvm_vcpu_arch *vcpu = &v->arch;
2179 struct kvm_arch *ka = &v->kvm->arch;
2181 u64 tsc_timestamp, host_tsc;
2183 bool use_master_clock;
2189 * If the host uses TSC clock, then passthrough TSC as stable
2192 spin_lock(&ka->pvclock_gtod_sync_lock);
2193 use_master_clock = ka->use_master_clock;
2194 if (use_master_clock) {
2195 host_tsc = ka->master_cycle_now;
2196 kernel_ns = ka->master_kernel_ns;
2198 spin_unlock(&ka->pvclock_gtod_sync_lock);
2200 /* Keep irq disabled to prevent changes to the clock */
2201 local_irq_save(flags);
2202 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2203 if (unlikely(tgt_tsc_khz == 0)) {
2204 local_irq_restore(flags);
2205 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2208 if (!use_master_clock) {
2210 kernel_ns = ktime_get_boottime_ns();
2213 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2216 * We may have to catch up the TSC to match elapsed wall clock
2217 * time for two reasons, even if kvmclock is used.
2218 * 1) CPU could have been running below the maximum TSC rate
2219 * 2) Broken TSC compensation resets the base at each VCPU
2220 * entry to avoid unknown leaps of TSC even when running
2221 * again on the same CPU. This may cause apparent elapsed
2222 * time to disappear, and the guest to stand still or run
2225 if (vcpu->tsc_catchup) {
2226 u64 tsc = compute_guest_tsc(v, kernel_ns);
2227 if (tsc > tsc_timestamp) {
2228 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2229 tsc_timestamp = tsc;
2233 local_irq_restore(flags);
2235 /* With all the info we got, fill in the values */
2237 if (kvm_has_tsc_control)
2238 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2240 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2241 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2242 &vcpu->hv_clock.tsc_shift,
2243 &vcpu->hv_clock.tsc_to_system_mul);
2244 vcpu->hw_tsc_khz = tgt_tsc_khz;
2247 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2248 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2249 vcpu->last_guest_tsc = tsc_timestamp;
2251 /* If the host uses TSC clocksource, then it is stable */
2253 if (use_master_clock)
2254 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2256 vcpu->hv_clock.flags = pvclock_flags;
2258 if (vcpu->pv_time_enabled)
2259 kvm_setup_pvclock_page(v);
2260 if (v == kvm_get_vcpu(v->kvm, 0))
2261 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2266 * kvmclock updates which are isolated to a given vcpu, such as
2267 * vcpu->cpu migration, should not allow system_timestamp from
2268 * the rest of the vcpus to remain static. Otherwise ntp frequency
2269 * correction applies to one vcpu's system_timestamp but not
2272 * So in those cases, request a kvmclock update for all vcpus.
2273 * We need to rate-limit these requests though, as they can
2274 * considerably slow guests that have a large number of vcpus.
2275 * The time for a remote vcpu to update its kvmclock is bound
2276 * by the delay we use to rate-limit the updates.
2279 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2281 static void kvmclock_update_fn(struct work_struct *work)
2284 struct delayed_work *dwork = to_delayed_work(work);
2285 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2286 kvmclock_update_work);
2287 struct kvm *kvm = container_of(ka, struct kvm, arch);
2288 struct kvm_vcpu *vcpu;
2290 kvm_for_each_vcpu(i, vcpu, kvm) {
2291 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2292 kvm_vcpu_kick(vcpu);
2296 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2298 struct kvm *kvm = v->kvm;
2300 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2301 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2302 KVMCLOCK_UPDATE_DELAY);
2305 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2307 static void kvmclock_sync_fn(struct work_struct *work)
2309 struct delayed_work *dwork = to_delayed_work(work);
2310 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2311 kvmclock_sync_work);
2312 struct kvm *kvm = container_of(ka, struct kvm, arch);
2314 if (!kvmclock_periodic_sync)
2317 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2318 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2319 KVMCLOCK_SYNC_PERIOD);
2323 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2325 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2327 /* McStatusWrEn enabled? */
2328 if (guest_cpuid_is_amd(vcpu))
2329 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2334 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2336 u64 mcg_cap = vcpu->arch.mcg_cap;
2337 unsigned bank_num = mcg_cap & 0xff;
2338 u32 msr = msr_info->index;
2339 u64 data = msr_info->data;
2342 case MSR_IA32_MCG_STATUS:
2343 vcpu->arch.mcg_status = data;
2345 case MSR_IA32_MCG_CTL:
2346 if (!(mcg_cap & MCG_CTL_P) &&
2347 (data || !msr_info->host_initiated))
2349 if (data != 0 && data != ~(u64)0)
2351 vcpu->arch.mcg_ctl = data;
2354 if (msr >= MSR_IA32_MC0_CTL &&
2355 msr < MSR_IA32_MCx_CTL(bank_num)) {
2356 u32 offset = msr - MSR_IA32_MC0_CTL;
2357 /* only 0 or all 1s can be written to IA32_MCi_CTL
2358 * some Linux kernels though clear bit 10 in bank 4 to
2359 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2360 * this to avoid an uncatched #GP in the guest
2362 if ((offset & 0x3) == 0 &&
2363 data != 0 && (data | (1 << 10)) != ~(u64)0)
2367 if (!msr_info->host_initiated &&
2368 (offset & 0x3) == 1 && data != 0) {
2369 if (!can_set_mci_status(vcpu))
2373 vcpu->arch.mce_banks[offset] = data;
2381 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2383 struct kvm *kvm = vcpu->kvm;
2384 int lm = is_long_mode(vcpu);
2385 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2386 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2387 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2388 : kvm->arch.xen_hvm_config.blob_size_32;
2389 u32 page_num = data & ~PAGE_MASK;
2390 u64 page_addr = data & PAGE_MASK;
2395 if (page_num >= blob_size)
2398 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2403 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2412 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2414 gpa_t gpa = data & ~0x3f;
2416 /* Bits 3:5 are reserved, Should be zero */
2420 vcpu->arch.apf.msr_val = data;
2422 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2423 kvm_clear_async_pf_completion_queue(vcpu);
2424 kvm_async_pf_hash_reset(vcpu);
2428 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2432 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2433 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2434 kvm_async_pf_wakeup_all(vcpu);
2438 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2440 vcpu->arch.pv_time_enabled = false;
2443 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2445 ++vcpu->stat.tlb_flush;
2446 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2449 static void record_steal_time(struct kvm_vcpu *vcpu)
2451 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2454 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2455 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2459 * Doing a TLB flush here, on the guest's behalf, can avoid
2462 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2463 kvm_vcpu_flush_tlb(vcpu, false);
2465 if (vcpu->arch.st.steal.version & 1)
2466 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2468 vcpu->arch.st.steal.version += 1;
2470 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2471 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2475 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2476 vcpu->arch.st.last_steal;
2477 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2479 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2480 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2484 vcpu->arch.st.steal.version += 1;
2486 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2487 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2490 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2493 u32 msr = msr_info->index;
2494 u64 data = msr_info->data;
2497 case MSR_AMD64_NB_CFG:
2498 case MSR_IA32_UCODE_WRITE:
2499 case MSR_VM_HSAVE_PA:
2500 case MSR_AMD64_PATCH_LOADER:
2501 case MSR_AMD64_BU_CFG2:
2502 case MSR_AMD64_DC_CFG:
2503 case MSR_F15H_EX_CFG:
2506 case MSR_IA32_UCODE_REV:
2507 if (msr_info->host_initiated)
2508 vcpu->arch.microcode_version = data;
2510 case MSR_IA32_ARCH_CAPABILITIES:
2511 if (!msr_info->host_initiated)
2513 vcpu->arch.arch_capabilities = data;
2516 return set_efer(vcpu, msr_info);
2518 data &= ~(u64)0x40; /* ignore flush filter disable */
2519 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2520 data &= ~(u64)0x8; /* ignore TLB cache disable */
2522 /* Handle McStatusWrEn */
2523 if (data == BIT_ULL(18)) {
2524 vcpu->arch.msr_hwcr = data;
2525 } else if (data != 0) {
2526 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2531 case MSR_FAM10H_MMIO_CONF_BASE:
2533 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2538 case MSR_IA32_DEBUGCTLMSR:
2540 /* We support the non-activated case already */
2542 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2543 /* Values other than LBR and BTF are vendor-specific,
2544 thus reserved and should throw a #GP */
2547 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2550 case 0x200 ... 0x2ff:
2551 return kvm_mtrr_set_msr(vcpu, msr, data);
2552 case MSR_IA32_APICBASE:
2553 return kvm_set_apic_base(vcpu, msr_info);
2554 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2555 return kvm_x2apic_msr_write(vcpu, msr, data);
2556 case MSR_IA32_TSCDEADLINE:
2557 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2559 case MSR_IA32_TSC_ADJUST:
2560 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2561 if (!msr_info->host_initiated) {
2562 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2563 adjust_tsc_offset_guest(vcpu, adj);
2565 vcpu->arch.ia32_tsc_adjust_msr = data;
2568 case MSR_IA32_MISC_ENABLE:
2569 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2570 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2571 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2573 vcpu->arch.ia32_misc_enable_msr = data;
2574 kvm_update_cpuid(vcpu);
2576 vcpu->arch.ia32_misc_enable_msr = data;
2579 case MSR_IA32_SMBASE:
2580 if (!msr_info->host_initiated)
2582 vcpu->arch.smbase = data;
2584 case MSR_IA32_POWER_CTL:
2585 vcpu->arch.msr_ia32_power_ctl = data;
2588 kvm_write_tsc(vcpu, msr_info);
2591 if (!msr_info->host_initiated)
2593 vcpu->arch.smi_count = data;
2595 case MSR_KVM_WALL_CLOCK_NEW:
2596 case MSR_KVM_WALL_CLOCK:
2597 vcpu->kvm->arch.wall_clock = data;
2598 kvm_write_wall_clock(vcpu->kvm, data);
2600 case MSR_KVM_SYSTEM_TIME_NEW:
2601 case MSR_KVM_SYSTEM_TIME: {
2602 struct kvm_arch *ka = &vcpu->kvm->arch;
2604 kvmclock_reset(vcpu);
2606 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2607 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2609 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2610 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2612 ka->boot_vcpu_runs_old_kvmclock = tmp;
2615 vcpu->arch.time = data;
2616 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2618 /* we verify if the enable bit is set... */
2622 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2623 &vcpu->arch.pv_time, data & ~1ULL,
2624 sizeof(struct pvclock_vcpu_time_info)))
2625 vcpu->arch.pv_time_enabled = false;
2627 vcpu->arch.pv_time_enabled = true;
2631 case MSR_KVM_ASYNC_PF_EN:
2632 if (kvm_pv_enable_async_pf(vcpu, data))
2635 case MSR_KVM_STEAL_TIME:
2637 if (unlikely(!sched_info_on()))
2640 if (data & KVM_STEAL_RESERVED_MASK)
2643 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2644 data & KVM_STEAL_VALID_BITS,
2645 sizeof(struct kvm_steal_time)))
2648 vcpu->arch.st.msr_val = data;
2650 if (!(data & KVM_MSR_ENABLED))
2653 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2656 case MSR_KVM_PV_EOI_EN:
2657 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2661 case MSR_KVM_POLL_CONTROL:
2662 /* only enable bit supported */
2663 if (data & (-1ULL << 1))
2666 vcpu->arch.msr_kvm_poll_control = data;
2669 case MSR_IA32_MCG_CTL:
2670 case MSR_IA32_MCG_STATUS:
2671 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2672 return set_msr_mce(vcpu, msr_info);
2674 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2675 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2676 pr = true; /* fall through */
2677 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2678 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2679 if (kvm_pmu_is_valid_msr(vcpu, msr))
2680 return kvm_pmu_set_msr(vcpu, msr_info);
2682 if (pr || data != 0)
2683 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2684 "0x%x data 0x%llx\n", msr, data);
2686 case MSR_K7_CLK_CTL:
2688 * Ignore all writes to this no longer documented MSR.
2689 * Writes are only relevant for old K7 processors,
2690 * all pre-dating SVM, but a recommended workaround from
2691 * AMD for these chips. It is possible to specify the
2692 * affected processor models on the command line, hence
2693 * the need to ignore the workaround.
2696 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2697 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2698 case HV_X64_MSR_CRASH_CTL:
2699 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2700 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2701 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2702 case HV_X64_MSR_TSC_EMULATION_STATUS:
2703 return kvm_hv_set_msr_common(vcpu, msr, data,
2704 msr_info->host_initiated);
2705 case MSR_IA32_BBL_CR_CTL3:
2706 /* Drop writes to this legacy MSR -- see rdmsr
2707 * counterpart for further detail.
2709 if (report_ignored_msrs)
2710 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2713 case MSR_AMD64_OSVW_ID_LENGTH:
2714 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2716 vcpu->arch.osvw.length = data;
2718 case MSR_AMD64_OSVW_STATUS:
2719 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2721 vcpu->arch.osvw.status = data;
2723 case MSR_PLATFORM_INFO:
2724 if (!msr_info->host_initiated ||
2725 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2726 cpuid_fault_enabled(vcpu)))
2728 vcpu->arch.msr_platform_info = data;
2730 case MSR_MISC_FEATURES_ENABLES:
2731 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2732 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2733 !supports_cpuid_fault(vcpu)))
2735 vcpu->arch.msr_misc_features_enables = data;
2738 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2739 return xen_hvm_config(vcpu, data);
2740 if (kvm_pmu_is_valid_msr(vcpu, msr))
2741 return kvm_pmu_set_msr(vcpu, msr_info);
2743 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2747 if (report_ignored_msrs)
2749 "ignored wrmsr: 0x%x data 0x%llx\n",
2756 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2760 * Reads an msr value (of 'msr_index') into 'pdata'.
2761 * Returns 0 on success, non-0 otherwise.
2762 * Assumes vcpu_load() was already called.
2764 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2766 return kvm_x86_ops->get_msr(vcpu, msr);
2768 EXPORT_SYMBOL_GPL(kvm_get_msr);
2770 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2773 u64 mcg_cap = vcpu->arch.mcg_cap;
2774 unsigned bank_num = mcg_cap & 0xff;
2777 case MSR_IA32_P5_MC_ADDR:
2778 case MSR_IA32_P5_MC_TYPE:
2781 case MSR_IA32_MCG_CAP:
2782 data = vcpu->arch.mcg_cap;
2784 case MSR_IA32_MCG_CTL:
2785 if (!(mcg_cap & MCG_CTL_P) && !host)
2787 data = vcpu->arch.mcg_ctl;
2789 case MSR_IA32_MCG_STATUS:
2790 data = vcpu->arch.mcg_status;
2793 if (msr >= MSR_IA32_MC0_CTL &&
2794 msr < MSR_IA32_MCx_CTL(bank_num)) {
2795 u32 offset = msr - MSR_IA32_MC0_CTL;
2796 data = vcpu->arch.mce_banks[offset];
2805 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2807 switch (msr_info->index) {
2808 case MSR_IA32_PLATFORM_ID:
2809 case MSR_IA32_EBL_CR_POWERON:
2810 case MSR_IA32_DEBUGCTLMSR:
2811 case MSR_IA32_LASTBRANCHFROMIP:
2812 case MSR_IA32_LASTBRANCHTOIP:
2813 case MSR_IA32_LASTINTFROMIP:
2814 case MSR_IA32_LASTINTTOIP:
2816 case MSR_K8_TSEG_ADDR:
2817 case MSR_K8_TSEG_MASK:
2818 case MSR_VM_HSAVE_PA:
2819 case MSR_K8_INT_PENDING_MSG:
2820 case MSR_AMD64_NB_CFG:
2821 case MSR_FAM10H_MMIO_CONF_BASE:
2822 case MSR_AMD64_BU_CFG2:
2823 case MSR_IA32_PERF_CTL:
2824 case MSR_AMD64_DC_CFG:
2825 case MSR_F15H_EX_CFG:
2828 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2829 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2830 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2831 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2832 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2833 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2834 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2837 case MSR_IA32_UCODE_REV:
2838 msr_info->data = vcpu->arch.microcode_version;
2840 case MSR_IA32_ARCH_CAPABILITIES:
2841 if (!msr_info->host_initiated &&
2842 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2844 msr_info->data = vcpu->arch.arch_capabilities;
2846 case MSR_IA32_POWER_CTL:
2847 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2850 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2853 case 0x200 ... 0x2ff:
2854 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2855 case 0xcd: /* fsb frequency */
2859 * MSR_EBC_FREQUENCY_ID
2860 * Conservative value valid for even the basic CPU models.
2861 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2862 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2863 * and 266MHz for model 3, or 4. Set Core Clock
2864 * Frequency to System Bus Frequency Ratio to 1 (bits
2865 * 31:24) even though these are only valid for CPU
2866 * models > 2, however guests may end up dividing or
2867 * multiplying by zero otherwise.
2869 case MSR_EBC_FREQUENCY_ID:
2870 msr_info->data = 1 << 24;
2872 case MSR_IA32_APICBASE:
2873 msr_info->data = kvm_get_apic_base(vcpu);
2875 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2876 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2878 case MSR_IA32_TSCDEADLINE:
2879 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2881 case MSR_IA32_TSC_ADJUST:
2882 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2884 case MSR_IA32_MISC_ENABLE:
2885 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2887 case MSR_IA32_SMBASE:
2888 if (!msr_info->host_initiated)
2890 msr_info->data = vcpu->arch.smbase;
2893 msr_info->data = vcpu->arch.smi_count;
2895 case MSR_IA32_PERF_STATUS:
2896 /* TSC increment by tick */
2897 msr_info->data = 1000ULL;
2898 /* CPU multiplier */
2899 msr_info->data |= (((uint64_t)4ULL) << 40);
2902 msr_info->data = vcpu->arch.efer;
2904 case MSR_KVM_WALL_CLOCK:
2905 case MSR_KVM_WALL_CLOCK_NEW:
2906 msr_info->data = vcpu->kvm->arch.wall_clock;
2908 case MSR_KVM_SYSTEM_TIME:
2909 case MSR_KVM_SYSTEM_TIME_NEW:
2910 msr_info->data = vcpu->arch.time;
2912 case MSR_KVM_ASYNC_PF_EN:
2913 msr_info->data = vcpu->arch.apf.msr_val;
2915 case MSR_KVM_STEAL_TIME:
2916 msr_info->data = vcpu->arch.st.msr_val;
2918 case MSR_KVM_PV_EOI_EN:
2919 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2921 case MSR_KVM_POLL_CONTROL:
2922 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2924 case MSR_IA32_P5_MC_ADDR:
2925 case MSR_IA32_P5_MC_TYPE:
2926 case MSR_IA32_MCG_CAP:
2927 case MSR_IA32_MCG_CTL:
2928 case MSR_IA32_MCG_STATUS:
2929 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2930 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2931 msr_info->host_initiated);
2932 case MSR_K7_CLK_CTL:
2934 * Provide expected ramp-up count for K7. All other
2935 * are set to zero, indicating minimum divisors for
2938 * This prevents guest kernels on AMD host with CPU
2939 * type 6, model 8 and higher from exploding due to
2940 * the rdmsr failing.
2942 msr_info->data = 0x20000000;
2944 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2945 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2946 case HV_X64_MSR_CRASH_CTL:
2947 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2948 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2949 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2950 case HV_X64_MSR_TSC_EMULATION_STATUS:
2951 return kvm_hv_get_msr_common(vcpu,
2952 msr_info->index, &msr_info->data,
2953 msr_info->host_initiated);
2955 case MSR_IA32_BBL_CR_CTL3:
2956 /* This legacy MSR exists but isn't fully documented in current
2957 * silicon. It is however accessed by winxp in very narrow
2958 * scenarios where it sets bit #19, itself documented as
2959 * a "reserved" bit. Best effort attempt to source coherent
2960 * read data here should the balance of the register be
2961 * interpreted by the guest:
2963 * L2 cache control register 3: 64GB range, 256KB size,
2964 * enabled, latency 0x1, configured
2966 msr_info->data = 0xbe702111;
2968 case MSR_AMD64_OSVW_ID_LENGTH:
2969 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2971 msr_info->data = vcpu->arch.osvw.length;
2973 case MSR_AMD64_OSVW_STATUS:
2974 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2976 msr_info->data = vcpu->arch.osvw.status;
2978 case MSR_PLATFORM_INFO:
2979 if (!msr_info->host_initiated &&
2980 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2982 msr_info->data = vcpu->arch.msr_platform_info;
2984 case MSR_MISC_FEATURES_ENABLES:
2985 msr_info->data = vcpu->arch.msr_misc_features_enables;
2988 msr_info->data = vcpu->arch.msr_hwcr;
2991 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2992 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2994 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2998 if (report_ignored_msrs)
2999 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3007 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3010 * Read or write a bunch of msrs. All parameters are kernel addresses.
3012 * @return number of msrs set successfully.
3014 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3015 struct kvm_msr_entry *entries,
3016 int (*do_msr)(struct kvm_vcpu *vcpu,
3017 unsigned index, u64 *data))
3021 for (i = 0; i < msrs->nmsrs; ++i)
3022 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3029 * Read or write a bunch of msrs. Parameters are user addresses.
3031 * @return number of msrs set successfully.
3033 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3034 int (*do_msr)(struct kvm_vcpu *vcpu,
3035 unsigned index, u64 *data),
3038 struct kvm_msrs msrs;
3039 struct kvm_msr_entry *entries;
3044 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3048 if (msrs.nmsrs >= MAX_IO_MSRS)
3051 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3052 entries = memdup_user(user_msrs->entries, size);
3053 if (IS_ERR(entries)) {
3054 r = PTR_ERR(entries);
3058 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3063 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3074 static inline bool kvm_can_mwait_in_guest(void)
3076 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3077 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3078 boot_cpu_has(X86_FEATURE_ARAT);
3081 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3086 case KVM_CAP_IRQCHIP:
3088 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3089 case KVM_CAP_SET_TSS_ADDR:
3090 case KVM_CAP_EXT_CPUID:
3091 case KVM_CAP_EXT_EMUL_CPUID:
3092 case KVM_CAP_CLOCKSOURCE:
3094 case KVM_CAP_NOP_IO_DELAY:
3095 case KVM_CAP_MP_STATE:
3096 case KVM_CAP_SYNC_MMU:
3097 case KVM_CAP_USER_NMI:
3098 case KVM_CAP_REINJECT_CONTROL:
3099 case KVM_CAP_IRQ_INJECT_STATUS:
3100 case KVM_CAP_IOEVENTFD:
3101 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3103 case KVM_CAP_PIT_STATE2:
3104 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3105 case KVM_CAP_XEN_HVM:
3106 case KVM_CAP_VCPU_EVENTS:
3107 case KVM_CAP_HYPERV:
3108 case KVM_CAP_HYPERV_VAPIC:
3109 case KVM_CAP_HYPERV_SPIN:
3110 case KVM_CAP_HYPERV_SYNIC:
3111 case KVM_CAP_HYPERV_SYNIC2:
3112 case KVM_CAP_HYPERV_VP_INDEX:
3113 case KVM_CAP_HYPERV_EVENTFD:
3114 case KVM_CAP_HYPERV_TLBFLUSH:
3115 case KVM_CAP_HYPERV_SEND_IPI:
3116 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3117 case KVM_CAP_HYPERV_CPUID:
3118 case KVM_CAP_PCI_SEGMENT:
3119 case KVM_CAP_DEBUGREGS:
3120 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3122 case KVM_CAP_ASYNC_PF:
3123 case KVM_CAP_GET_TSC_KHZ:
3124 case KVM_CAP_KVMCLOCK_CTRL:
3125 case KVM_CAP_READONLY_MEM:
3126 case KVM_CAP_HYPERV_TIME:
3127 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3128 case KVM_CAP_TSC_DEADLINE_TIMER:
3129 case KVM_CAP_DISABLE_QUIRKS:
3130 case KVM_CAP_SET_BOOT_CPU_ID:
3131 case KVM_CAP_SPLIT_IRQCHIP:
3132 case KVM_CAP_IMMEDIATE_EXIT:
3133 case KVM_CAP_PMU_EVENT_FILTER:
3134 case KVM_CAP_GET_MSR_FEATURES:
3135 case KVM_CAP_MSR_PLATFORM_INFO:
3136 case KVM_CAP_EXCEPTION_PAYLOAD:
3139 case KVM_CAP_SYNC_REGS:
3140 r = KVM_SYNC_X86_VALID_FIELDS;
3142 case KVM_CAP_ADJUST_CLOCK:
3143 r = KVM_CLOCK_TSC_STABLE;
3145 case KVM_CAP_X86_DISABLE_EXITS:
3146 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3147 KVM_X86_DISABLE_EXITS_CSTATE;
3148 if(kvm_can_mwait_in_guest())
3149 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3151 case KVM_CAP_X86_SMM:
3152 /* SMBASE is usually relocated above 1M on modern chipsets,
3153 * and SMM handlers might indeed rely on 4G segment limits,
3154 * so do not report SMM to be available if real mode is
3155 * emulated via vm86 mode. Still, do not go to great lengths
3156 * to avoid userspace's usage of the feature, because it is a
3157 * fringe case that is not enabled except via specific settings
3158 * of the module parameters.
3160 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3163 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3165 case KVM_CAP_NR_VCPUS:
3166 r = KVM_SOFT_MAX_VCPUS;
3168 case KVM_CAP_MAX_VCPUS:
3171 case KVM_CAP_MAX_VCPU_ID:
3172 r = KVM_MAX_VCPU_ID;
3174 case KVM_CAP_PV_MMU: /* obsolete */
3178 r = KVM_MAX_MCE_BANKS;
3181 r = boot_cpu_has(X86_FEATURE_XSAVE);
3183 case KVM_CAP_TSC_CONTROL:
3184 r = kvm_has_tsc_control;
3186 case KVM_CAP_X2APIC_API:
3187 r = KVM_X2APIC_API_VALID_FLAGS;
3189 case KVM_CAP_NESTED_STATE:
3190 r = kvm_x86_ops->get_nested_state ?
3191 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3200 long kvm_arch_dev_ioctl(struct file *filp,
3201 unsigned int ioctl, unsigned long arg)
3203 void __user *argp = (void __user *)arg;
3207 case KVM_GET_MSR_INDEX_LIST: {
3208 struct kvm_msr_list __user *user_msr_list = argp;
3209 struct kvm_msr_list msr_list;
3213 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3216 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3217 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3220 if (n < msr_list.nmsrs)
3223 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3224 num_msrs_to_save * sizeof(u32)))
3226 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3228 num_emulated_msrs * sizeof(u32)))
3233 case KVM_GET_SUPPORTED_CPUID:
3234 case KVM_GET_EMULATED_CPUID: {
3235 struct kvm_cpuid2 __user *cpuid_arg = argp;
3236 struct kvm_cpuid2 cpuid;
3239 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3242 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3248 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3253 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3255 if (copy_to_user(argp, &kvm_mce_cap_supported,
3256 sizeof(kvm_mce_cap_supported)))
3260 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3261 struct kvm_msr_list __user *user_msr_list = argp;
3262 struct kvm_msr_list msr_list;
3266 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3269 msr_list.nmsrs = num_msr_based_features;
3270 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3273 if (n < msr_list.nmsrs)
3276 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3277 num_msr_based_features * sizeof(u32)))
3283 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3293 static void wbinvd_ipi(void *garbage)
3298 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3300 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3303 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3305 /* Address WBINVD may be executed by guest */
3306 if (need_emulate_wbinvd(vcpu)) {
3307 if (kvm_x86_ops->has_wbinvd_exit())
3308 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3309 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3310 smp_call_function_single(vcpu->cpu,
3311 wbinvd_ipi, NULL, 1);
3314 kvm_x86_ops->vcpu_load(vcpu, cpu);
3316 fpregs_assert_state_consistent();
3317 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3318 switch_fpu_return();
3320 /* Apply any externally detected TSC adjustments (due to suspend) */
3321 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3322 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3323 vcpu->arch.tsc_offset_adjustment = 0;
3324 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3327 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3328 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3329 rdtsc() - vcpu->arch.last_host_tsc;
3331 mark_tsc_unstable("KVM discovered backwards TSC");
3333 if (kvm_check_tsc_unstable()) {
3334 u64 offset = kvm_compute_tsc_offset(vcpu,
3335 vcpu->arch.last_guest_tsc);
3336 kvm_vcpu_write_tsc_offset(vcpu, offset);
3337 vcpu->arch.tsc_catchup = 1;
3340 if (kvm_lapic_hv_timer_in_use(vcpu))
3341 kvm_lapic_restart_hv_timer(vcpu);
3344 * On a host with synchronized TSC, there is no need to update
3345 * kvmclock on vcpu->cpu migration
3347 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3348 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3349 if (vcpu->cpu != cpu)
3350 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3354 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3357 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3359 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3362 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3364 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3365 &vcpu->arch.st.steal.preempted,
3366 offsetof(struct kvm_steal_time, preempted),
3367 sizeof(vcpu->arch.st.steal.preempted));
3370 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3374 if (vcpu->preempted)
3375 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3378 * Disable page faults because we're in atomic context here.
3379 * kvm_write_guest_offset_cached() would call might_fault()
3380 * that relies on pagefault_disable() to tell if there's a
3381 * bug. NOTE: the write to guest memory may not go through if
3382 * during postcopy live migration or if there's heavy guest
3385 pagefault_disable();
3387 * kvm_memslots() will be called by
3388 * kvm_write_guest_offset_cached() so take the srcu lock.
3390 idx = srcu_read_lock(&vcpu->kvm->srcu);
3391 kvm_steal_time_set_preempted(vcpu);
3392 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3394 kvm_x86_ops->vcpu_put(vcpu);
3395 vcpu->arch.last_host_tsc = rdtsc();
3397 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3398 * on every vmexit, but if not, we might have a stale dr6 from the
3399 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3404 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3405 struct kvm_lapic_state *s)
3407 if (vcpu->arch.apicv_active)
3408 kvm_x86_ops->sync_pir_to_irr(vcpu);
3410 return kvm_apic_get_state(vcpu, s);
3413 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3414 struct kvm_lapic_state *s)
3418 r = kvm_apic_set_state(vcpu, s);
3421 update_cr8_intercept(vcpu);
3426 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3428 return (!lapic_in_kernel(vcpu) ||
3429 kvm_apic_accept_pic_intr(vcpu));
3433 * if userspace requested an interrupt window, check that the
3434 * interrupt window is open.
3436 * No need to exit to userspace if we already have an interrupt queued.
3438 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3440 return kvm_arch_interrupt_allowed(vcpu) &&
3441 !kvm_cpu_has_interrupt(vcpu) &&
3442 !kvm_event_needs_reinjection(vcpu) &&
3443 kvm_cpu_accept_dm_intr(vcpu);
3446 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3447 struct kvm_interrupt *irq)
3449 if (irq->irq >= KVM_NR_INTERRUPTS)
3452 if (!irqchip_in_kernel(vcpu->kvm)) {
3453 kvm_queue_interrupt(vcpu, irq->irq, false);
3454 kvm_make_request(KVM_REQ_EVENT, vcpu);
3459 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3460 * fail for in-kernel 8259.
3462 if (pic_in_kernel(vcpu->kvm))
3465 if (vcpu->arch.pending_external_vector != -1)
3468 vcpu->arch.pending_external_vector = irq->irq;
3469 kvm_make_request(KVM_REQ_EVENT, vcpu);
3473 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3475 kvm_inject_nmi(vcpu);
3480 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3482 kvm_make_request(KVM_REQ_SMI, vcpu);
3487 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3488 struct kvm_tpr_access_ctl *tac)
3492 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3496 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3500 unsigned bank_num = mcg_cap & 0xff, bank;
3503 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3505 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3508 vcpu->arch.mcg_cap = mcg_cap;
3509 /* Init IA32_MCG_CTL to all 1s */
3510 if (mcg_cap & MCG_CTL_P)
3511 vcpu->arch.mcg_ctl = ~(u64)0;
3512 /* Init IA32_MCi_CTL to all 1s */
3513 for (bank = 0; bank < bank_num; bank++)
3514 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3516 if (kvm_x86_ops->setup_mce)
3517 kvm_x86_ops->setup_mce(vcpu);
3522 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3523 struct kvm_x86_mce *mce)
3525 u64 mcg_cap = vcpu->arch.mcg_cap;
3526 unsigned bank_num = mcg_cap & 0xff;
3527 u64 *banks = vcpu->arch.mce_banks;
3529 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3532 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3533 * reporting is disabled
3535 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3536 vcpu->arch.mcg_ctl != ~(u64)0)
3538 banks += 4 * mce->bank;
3540 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3541 * reporting is disabled for the bank
3543 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3545 if (mce->status & MCI_STATUS_UC) {
3546 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3547 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3548 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3551 if (banks[1] & MCI_STATUS_VAL)
3552 mce->status |= MCI_STATUS_OVER;
3553 banks[2] = mce->addr;
3554 banks[3] = mce->misc;
3555 vcpu->arch.mcg_status = mce->mcg_status;
3556 banks[1] = mce->status;
3557 kvm_queue_exception(vcpu, MC_VECTOR);
3558 } else if (!(banks[1] & MCI_STATUS_VAL)
3559 || !(banks[1] & MCI_STATUS_UC)) {
3560 if (banks[1] & MCI_STATUS_VAL)
3561 mce->status |= MCI_STATUS_OVER;
3562 banks[2] = mce->addr;
3563 banks[3] = mce->misc;
3564 banks[1] = mce->status;
3566 banks[1] |= MCI_STATUS_OVER;
3570 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3571 struct kvm_vcpu_events *events)
3576 * The API doesn't provide the instruction length for software
3577 * exceptions, so don't report them. As long as the guest RIP
3578 * isn't advanced, we should expect to encounter the exception
3581 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3582 events->exception.injected = 0;
3583 events->exception.pending = 0;
3585 events->exception.injected = vcpu->arch.exception.injected;
3586 events->exception.pending = vcpu->arch.exception.pending;
3588 * For ABI compatibility, deliberately conflate
3589 * pending and injected exceptions when
3590 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3592 if (!vcpu->kvm->arch.exception_payload_enabled)
3593 events->exception.injected |=
3594 vcpu->arch.exception.pending;
3596 events->exception.nr = vcpu->arch.exception.nr;
3597 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3598 events->exception.error_code = vcpu->arch.exception.error_code;
3599 events->exception_has_payload = vcpu->arch.exception.has_payload;
3600 events->exception_payload = vcpu->arch.exception.payload;
3602 events->interrupt.injected =
3603 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3604 events->interrupt.nr = vcpu->arch.interrupt.nr;
3605 events->interrupt.soft = 0;
3606 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3608 events->nmi.injected = vcpu->arch.nmi_injected;
3609 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3610 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3611 events->nmi.pad = 0;
3613 events->sipi_vector = 0; /* never valid when reporting to user space */
3615 events->smi.smm = is_smm(vcpu);
3616 events->smi.pending = vcpu->arch.smi_pending;
3617 events->smi.smm_inside_nmi =
3618 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3619 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3621 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3622 | KVM_VCPUEVENT_VALID_SHADOW
3623 | KVM_VCPUEVENT_VALID_SMM);
3624 if (vcpu->kvm->arch.exception_payload_enabled)
3625 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3627 memset(&events->reserved, 0, sizeof(events->reserved));
3630 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3632 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3633 struct kvm_vcpu_events *events)
3635 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3636 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3637 | KVM_VCPUEVENT_VALID_SHADOW
3638 | KVM_VCPUEVENT_VALID_SMM
3639 | KVM_VCPUEVENT_VALID_PAYLOAD))
3642 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3643 if (!vcpu->kvm->arch.exception_payload_enabled)
3645 if (events->exception.pending)
3646 events->exception.injected = 0;
3648 events->exception_has_payload = 0;
3650 events->exception.pending = 0;
3651 events->exception_has_payload = 0;
3654 if ((events->exception.injected || events->exception.pending) &&
3655 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3658 /* INITs are latched while in SMM */
3659 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3660 (events->smi.smm || events->smi.pending) &&
3661 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3665 vcpu->arch.exception.injected = events->exception.injected;
3666 vcpu->arch.exception.pending = events->exception.pending;
3667 vcpu->arch.exception.nr = events->exception.nr;
3668 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3669 vcpu->arch.exception.error_code = events->exception.error_code;
3670 vcpu->arch.exception.has_payload = events->exception_has_payload;
3671 vcpu->arch.exception.payload = events->exception_payload;
3673 vcpu->arch.interrupt.injected = events->interrupt.injected;
3674 vcpu->arch.interrupt.nr = events->interrupt.nr;
3675 vcpu->arch.interrupt.soft = events->interrupt.soft;
3676 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3677 kvm_x86_ops->set_interrupt_shadow(vcpu,
3678 events->interrupt.shadow);
3680 vcpu->arch.nmi_injected = events->nmi.injected;
3681 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3682 vcpu->arch.nmi_pending = events->nmi.pending;
3683 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3685 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3686 lapic_in_kernel(vcpu))
3687 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3689 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3690 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3691 if (events->smi.smm)
3692 vcpu->arch.hflags |= HF_SMM_MASK;
3694 vcpu->arch.hflags &= ~HF_SMM_MASK;
3695 kvm_smm_changed(vcpu);
3698 vcpu->arch.smi_pending = events->smi.pending;
3700 if (events->smi.smm) {
3701 if (events->smi.smm_inside_nmi)
3702 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3704 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3705 if (lapic_in_kernel(vcpu)) {
3706 if (events->smi.latched_init)
3707 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3709 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3714 kvm_make_request(KVM_REQ_EVENT, vcpu);
3719 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3720 struct kvm_debugregs *dbgregs)
3724 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3725 kvm_get_dr(vcpu, 6, &val);
3727 dbgregs->dr7 = vcpu->arch.dr7;
3729 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3732 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3733 struct kvm_debugregs *dbgregs)
3738 if (dbgregs->dr6 & ~0xffffffffull)
3740 if (dbgregs->dr7 & ~0xffffffffull)
3743 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3744 kvm_update_dr0123(vcpu);
3745 vcpu->arch.dr6 = dbgregs->dr6;
3746 kvm_update_dr6(vcpu);
3747 vcpu->arch.dr7 = dbgregs->dr7;
3748 kvm_update_dr7(vcpu);
3753 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3755 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3757 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3758 u64 xstate_bv = xsave->header.xfeatures;
3762 * Copy legacy XSAVE area, to avoid complications with CPUID
3763 * leaves 0 and 1 in the loop below.
3765 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3768 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3769 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3772 * Copy each region from the possibly compacted offset to the
3773 * non-compacted offset.
3775 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3777 u64 xfeature_mask = valid & -valid;
3778 int xfeature_nr = fls64(xfeature_mask) - 1;
3779 void *src = get_xsave_addr(xsave, xfeature_nr);
3782 u32 size, offset, ecx, edx;
3783 cpuid_count(XSTATE_CPUID, xfeature_nr,
3784 &size, &offset, &ecx, &edx);
3785 if (xfeature_nr == XFEATURE_PKRU)
3786 memcpy(dest + offset, &vcpu->arch.pkru,
3787 sizeof(vcpu->arch.pkru));
3789 memcpy(dest + offset, src, size);
3793 valid -= xfeature_mask;
3797 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3799 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3800 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3804 * Copy legacy XSAVE area, to avoid complications with CPUID
3805 * leaves 0 and 1 in the loop below.
3807 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3809 /* Set XSTATE_BV and possibly XCOMP_BV. */
3810 xsave->header.xfeatures = xstate_bv;
3811 if (boot_cpu_has(X86_FEATURE_XSAVES))
3812 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3815 * Copy each region from the non-compacted offset to the
3816 * possibly compacted offset.
3818 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3820 u64 xfeature_mask = valid & -valid;
3821 int xfeature_nr = fls64(xfeature_mask) - 1;
3822 void *dest = get_xsave_addr(xsave, xfeature_nr);
3825 u32 size, offset, ecx, edx;
3826 cpuid_count(XSTATE_CPUID, xfeature_nr,
3827 &size, &offset, &ecx, &edx);
3828 if (xfeature_nr == XFEATURE_PKRU)
3829 memcpy(&vcpu->arch.pkru, src + offset,
3830 sizeof(vcpu->arch.pkru));
3832 memcpy(dest, src + offset, size);
3835 valid -= xfeature_mask;
3839 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3840 struct kvm_xsave *guest_xsave)
3842 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3843 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3844 fill_xsave((u8 *) guest_xsave->region, vcpu);
3846 memcpy(guest_xsave->region,
3847 &vcpu->arch.guest_fpu->state.fxsave,
3848 sizeof(struct fxregs_state));
3849 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3850 XFEATURE_MASK_FPSSE;
3854 #define XSAVE_MXCSR_OFFSET 24
3856 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3857 struct kvm_xsave *guest_xsave)
3860 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3861 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3863 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3865 * Here we allow setting states that are not present in
3866 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3867 * with old userspace.
3869 if (xstate_bv & ~kvm_supported_xcr0() ||
3870 mxcsr & ~mxcsr_feature_mask)
3872 load_xsave(vcpu, (u8 *)guest_xsave->region);
3874 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3875 mxcsr & ~mxcsr_feature_mask)
3877 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3878 guest_xsave->region, sizeof(struct fxregs_state));
3883 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3884 struct kvm_xcrs *guest_xcrs)
3886 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3887 guest_xcrs->nr_xcrs = 0;
3891 guest_xcrs->nr_xcrs = 1;
3892 guest_xcrs->flags = 0;
3893 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3894 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3897 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3898 struct kvm_xcrs *guest_xcrs)
3902 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3905 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3908 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3909 /* Only support XCR0 currently */
3910 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3911 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3912 guest_xcrs->xcrs[i].value);
3921 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3922 * stopped by the hypervisor. This function will be called from the host only.
3923 * EINVAL is returned when the host attempts to set the flag for a guest that
3924 * does not support pv clocks.
3926 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3928 if (!vcpu->arch.pv_time_enabled)
3930 vcpu->arch.pvclock_set_guest_stopped_request = true;
3931 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3935 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3936 struct kvm_enable_cap *cap)
3939 uint16_t vmcs_version;
3940 void __user *user_ptr;
3946 case KVM_CAP_HYPERV_SYNIC2:
3951 case KVM_CAP_HYPERV_SYNIC:
3952 if (!irqchip_in_kernel(vcpu->kvm))
3954 return kvm_hv_activate_synic(vcpu, cap->cap ==
3955 KVM_CAP_HYPERV_SYNIC2);
3956 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3957 if (!kvm_x86_ops->nested_enable_evmcs)
3959 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3961 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3962 if (copy_to_user(user_ptr, &vmcs_version,
3963 sizeof(vmcs_version)))
3973 long kvm_arch_vcpu_ioctl(struct file *filp,
3974 unsigned int ioctl, unsigned long arg)
3976 struct kvm_vcpu *vcpu = filp->private_data;
3977 void __user *argp = (void __user *)arg;
3980 struct kvm_lapic_state *lapic;
3981 struct kvm_xsave *xsave;
3982 struct kvm_xcrs *xcrs;
3990 case KVM_GET_LAPIC: {
3992 if (!lapic_in_kernel(vcpu))
3994 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3995 GFP_KERNEL_ACCOUNT);
4000 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4004 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4009 case KVM_SET_LAPIC: {
4011 if (!lapic_in_kernel(vcpu))
4013 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4014 if (IS_ERR(u.lapic)) {
4015 r = PTR_ERR(u.lapic);
4019 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4022 case KVM_INTERRUPT: {
4023 struct kvm_interrupt irq;
4026 if (copy_from_user(&irq, argp, sizeof(irq)))
4028 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4032 r = kvm_vcpu_ioctl_nmi(vcpu);
4036 r = kvm_vcpu_ioctl_smi(vcpu);
4039 case KVM_SET_CPUID: {
4040 struct kvm_cpuid __user *cpuid_arg = argp;
4041 struct kvm_cpuid cpuid;
4044 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4046 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4049 case KVM_SET_CPUID2: {
4050 struct kvm_cpuid2 __user *cpuid_arg = argp;
4051 struct kvm_cpuid2 cpuid;
4054 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4056 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4057 cpuid_arg->entries);
4060 case KVM_GET_CPUID2: {
4061 struct kvm_cpuid2 __user *cpuid_arg = argp;
4062 struct kvm_cpuid2 cpuid;
4065 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4067 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4068 cpuid_arg->entries);
4072 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4077 case KVM_GET_MSRS: {
4078 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4079 r = msr_io(vcpu, argp, do_get_msr, 1);
4080 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4083 case KVM_SET_MSRS: {
4084 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4085 r = msr_io(vcpu, argp, do_set_msr, 0);
4086 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4089 case KVM_TPR_ACCESS_REPORTING: {
4090 struct kvm_tpr_access_ctl tac;
4093 if (copy_from_user(&tac, argp, sizeof(tac)))
4095 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4099 if (copy_to_user(argp, &tac, sizeof(tac)))
4104 case KVM_SET_VAPIC_ADDR: {
4105 struct kvm_vapic_addr va;
4109 if (!lapic_in_kernel(vcpu))
4112 if (copy_from_user(&va, argp, sizeof(va)))
4114 idx = srcu_read_lock(&vcpu->kvm->srcu);
4115 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4116 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4119 case KVM_X86_SETUP_MCE: {
4123 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4125 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4128 case KVM_X86_SET_MCE: {
4129 struct kvm_x86_mce mce;
4132 if (copy_from_user(&mce, argp, sizeof(mce)))
4134 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4137 case KVM_GET_VCPU_EVENTS: {
4138 struct kvm_vcpu_events events;
4140 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4143 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4148 case KVM_SET_VCPU_EVENTS: {
4149 struct kvm_vcpu_events events;
4152 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4155 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4158 case KVM_GET_DEBUGREGS: {
4159 struct kvm_debugregs dbgregs;
4161 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4164 if (copy_to_user(argp, &dbgregs,
4165 sizeof(struct kvm_debugregs)))
4170 case KVM_SET_DEBUGREGS: {
4171 struct kvm_debugregs dbgregs;
4174 if (copy_from_user(&dbgregs, argp,
4175 sizeof(struct kvm_debugregs)))
4178 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4181 case KVM_GET_XSAVE: {
4182 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4187 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4190 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4195 case KVM_SET_XSAVE: {
4196 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4197 if (IS_ERR(u.xsave)) {
4198 r = PTR_ERR(u.xsave);
4202 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4205 case KVM_GET_XCRS: {
4206 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4211 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4214 if (copy_to_user(argp, u.xcrs,
4215 sizeof(struct kvm_xcrs)))
4220 case KVM_SET_XCRS: {
4221 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4222 if (IS_ERR(u.xcrs)) {
4223 r = PTR_ERR(u.xcrs);
4227 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4230 case KVM_SET_TSC_KHZ: {
4234 user_tsc_khz = (u32)arg;
4236 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4239 if (user_tsc_khz == 0)
4240 user_tsc_khz = tsc_khz;
4242 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4247 case KVM_GET_TSC_KHZ: {
4248 r = vcpu->arch.virtual_tsc_khz;
4251 case KVM_KVMCLOCK_CTRL: {
4252 r = kvm_set_guest_paused(vcpu);
4255 case KVM_ENABLE_CAP: {
4256 struct kvm_enable_cap cap;
4259 if (copy_from_user(&cap, argp, sizeof(cap)))
4261 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4264 case KVM_GET_NESTED_STATE: {
4265 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4269 if (!kvm_x86_ops->get_nested_state)
4272 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4274 if (get_user(user_data_size, &user_kvm_nested_state->size))
4277 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4282 if (r > user_data_size) {
4283 if (put_user(r, &user_kvm_nested_state->size))
4293 case KVM_SET_NESTED_STATE: {
4294 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4295 struct kvm_nested_state kvm_state;
4298 if (!kvm_x86_ops->set_nested_state)
4302 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4306 if (kvm_state.size < sizeof(kvm_state))
4309 if (kvm_state.flags &
4310 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4311 | KVM_STATE_NESTED_EVMCS))
4314 /* nested_run_pending implies guest_mode. */
4315 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4316 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4319 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4322 case KVM_GET_SUPPORTED_HV_CPUID: {
4323 struct kvm_cpuid2 __user *cpuid_arg = argp;
4324 struct kvm_cpuid2 cpuid;
4327 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4330 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4331 cpuid_arg->entries);
4336 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4351 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4353 return VM_FAULT_SIGBUS;
4356 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4360 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4362 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4366 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4369 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4372 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4373 unsigned long kvm_nr_mmu_pages)
4375 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4378 mutex_lock(&kvm->slots_lock);
4380 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4381 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4383 mutex_unlock(&kvm->slots_lock);
4387 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4389 return kvm->arch.n_max_mmu_pages;
4392 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4394 struct kvm_pic *pic = kvm->arch.vpic;
4398 switch (chip->chip_id) {
4399 case KVM_IRQCHIP_PIC_MASTER:
4400 memcpy(&chip->chip.pic, &pic->pics[0],
4401 sizeof(struct kvm_pic_state));
4403 case KVM_IRQCHIP_PIC_SLAVE:
4404 memcpy(&chip->chip.pic, &pic->pics[1],
4405 sizeof(struct kvm_pic_state));
4407 case KVM_IRQCHIP_IOAPIC:
4408 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4417 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4419 struct kvm_pic *pic = kvm->arch.vpic;
4423 switch (chip->chip_id) {
4424 case KVM_IRQCHIP_PIC_MASTER:
4425 spin_lock(&pic->lock);
4426 memcpy(&pic->pics[0], &chip->chip.pic,
4427 sizeof(struct kvm_pic_state));
4428 spin_unlock(&pic->lock);
4430 case KVM_IRQCHIP_PIC_SLAVE:
4431 spin_lock(&pic->lock);
4432 memcpy(&pic->pics[1], &chip->chip.pic,
4433 sizeof(struct kvm_pic_state));
4434 spin_unlock(&pic->lock);
4436 case KVM_IRQCHIP_IOAPIC:
4437 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4443 kvm_pic_update_irq(pic);
4447 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4449 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4451 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4453 mutex_lock(&kps->lock);
4454 memcpy(ps, &kps->channels, sizeof(*ps));
4455 mutex_unlock(&kps->lock);
4459 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4462 struct kvm_pit *pit = kvm->arch.vpit;
4464 mutex_lock(&pit->pit_state.lock);
4465 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4466 for (i = 0; i < 3; i++)
4467 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4468 mutex_unlock(&pit->pit_state.lock);
4472 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4474 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4475 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4476 sizeof(ps->channels));
4477 ps->flags = kvm->arch.vpit->pit_state.flags;
4478 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4479 memset(&ps->reserved, 0, sizeof(ps->reserved));
4483 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4487 u32 prev_legacy, cur_legacy;
4488 struct kvm_pit *pit = kvm->arch.vpit;
4490 mutex_lock(&pit->pit_state.lock);
4491 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4492 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4493 if (!prev_legacy && cur_legacy)
4495 memcpy(&pit->pit_state.channels, &ps->channels,
4496 sizeof(pit->pit_state.channels));
4497 pit->pit_state.flags = ps->flags;
4498 for (i = 0; i < 3; i++)
4499 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4501 mutex_unlock(&pit->pit_state.lock);
4505 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4506 struct kvm_reinject_control *control)
4508 struct kvm_pit *pit = kvm->arch.vpit;
4513 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4514 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4515 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4517 mutex_lock(&pit->pit_state.lock);
4518 kvm_pit_set_reinject(pit, control->pit_reinject);
4519 mutex_unlock(&pit->pit_state.lock);
4525 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4526 * @kvm: kvm instance
4527 * @log: slot id and address to which we copy the log
4529 * Steps 1-4 below provide general overview of dirty page logging. See
4530 * kvm_get_dirty_log_protect() function description for additional details.
4532 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4533 * always flush the TLB (step 4) even if previous step failed and the dirty
4534 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4535 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4536 * writes will be marked dirty for next log read.
4538 * 1. Take a snapshot of the bit and clear it if needed.
4539 * 2. Write protect the corresponding page.
4540 * 3. Copy the snapshot to the userspace.
4541 * 4. Flush TLB's if needed.
4543 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4548 mutex_lock(&kvm->slots_lock);
4551 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4553 if (kvm_x86_ops->flush_log_dirty)
4554 kvm_x86_ops->flush_log_dirty(kvm);
4556 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4559 * All the TLBs can be flushed out of mmu lock, see the comments in
4560 * kvm_mmu_slot_remove_write_access().
4562 lockdep_assert_held(&kvm->slots_lock);
4564 kvm_flush_remote_tlbs(kvm);
4566 mutex_unlock(&kvm->slots_lock);
4570 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4575 mutex_lock(&kvm->slots_lock);
4578 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4580 if (kvm_x86_ops->flush_log_dirty)
4581 kvm_x86_ops->flush_log_dirty(kvm);
4583 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4586 * All the TLBs can be flushed out of mmu lock, see the comments in
4587 * kvm_mmu_slot_remove_write_access().
4589 lockdep_assert_held(&kvm->slots_lock);
4591 kvm_flush_remote_tlbs(kvm);
4593 mutex_unlock(&kvm->slots_lock);
4597 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4600 if (!irqchip_in_kernel(kvm))
4603 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4604 irq_event->irq, irq_event->level,
4609 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4610 struct kvm_enable_cap *cap)
4618 case KVM_CAP_DISABLE_QUIRKS:
4619 kvm->arch.disabled_quirks = cap->args[0];
4622 case KVM_CAP_SPLIT_IRQCHIP: {
4623 mutex_lock(&kvm->lock);
4625 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4626 goto split_irqchip_unlock;
4628 if (irqchip_in_kernel(kvm))
4629 goto split_irqchip_unlock;
4630 if (kvm->created_vcpus)
4631 goto split_irqchip_unlock;
4632 r = kvm_setup_empty_irq_routing(kvm);
4634 goto split_irqchip_unlock;
4635 /* Pairs with irqchip_in_kernel. */
4637 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4638 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4640 split_irqchip_unlock:
4641 mutex_unlock(&kvm->lock);
4644 case KVM_CAP_X2APIC_API:
4646 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4649 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4650 kvm->arch.x2apic_format = true;
4651 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4652 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4656 case KVM_CAP_X86_DISABLE_EXITS:
4658 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4661 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4662 kvm_can_mwait_in_guest())
4663 kvm->arch.mwait_in_guest = true;
4664 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4665 kvm->arch.hlt_in_guest = true;
4666 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4667 kvm->arch.pause_in_guest = true;
4668 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4669 kvm->arch.cstate_in_guest = true;
4672 case KVM_CAP_MSR_PLATFORM_INFO:
4673 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4676 case KVM_CAP_EXCEPTION_PAYLOAD:
4677 kvm->arch.exception_payload_enabled = cap->args[0];
4687 long kvm_arch_vm_ioctl(struct file *filp,
4688 unsigned int ioctl, unsigned long arg)
4690 struct kvm *kvm = filp->private_data;
4691 void __user *argp = (void __user *)arg;
4694 * This union makes it completely explicit to gcc-3.x
4695 * that these two variables' stack usage should be
4696 * combined, not added together.
4699 struct kvm_pit_state ps;
4700 struct kvm_pit_state2 ps2;
4701 struct kvm_pit_config pit_config;
4705 case KVM_SET_TSS_ADDR:
4706 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4708 case KVM_SET_IDENTITY_MAP_ADDR: {
4711 mutex_lock(&kvm->lock);
4713 if (kvm->created_vcpus)
4714 goto set_identity_unlock;
4716 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4717 goto set_identity_unlock;
4718 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4719 set_identity_unlock:
4720 mutex_unlock(&kvm->lock);
4723 case KVM_SET_NR_MMU_PAGES:
4724 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4726 case KVM_GET_NR_MMU_PAGES:
4727 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4729 case KVM_CREATE_IRQCHIP: {
4730 mutex_lock(&kvm->lock);
4733 if (irqchip_in_kernel(kvm))
4734 goto create_irqchip_unlock;
4737 if (kvm->created_vcpus)
4738 goto create_irqchip_unlock;
4740 r = kvm_pic_init(kvm);
4742 goto create_irqchip_unlock;
4744 r = kvm_ioapic_init(kvm);
4746 kvm_pic_destroy(kvm);
4747 goto create_irqchip_unlock;
4750 r = kvm_setup_default_irq_routing(kvm);
4752 kvm_ioapic_destroy(kvm);
4753 kvm_pic_destroy(kvm);
4754 goto create_irqchip_unlock;
4756 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4758 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4759 create_irqchip_unlock:
4760 mutex_unlock(&kvm->lock);
4763 case KVM_CREATE_PIT:
4764 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4766 case KVM_CREATE_PIT2:
4768 if (copy_from_user(&u.pit_config, argp,
4769 sizeof(struct kvm_pit_config)))
4772 mutex_lock(&kvm->lock);
4775 goto create_pit_unlock;
4777 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4781 mutex_unlock(&kvm->lock);
4783 case KVM_GET_IRQCHIP: {
4784 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4785 struct kvm_irqchip *chip;
4787 chip = memdup_user(argp, sizeof(*chip));
4794 if (!irqchip_kernel(kvm))
4795 goto get_irqchip_out;
4796 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4798 goto get_irqchip_out;
4800 if (copy_to_user(argp, chip, sizeof(*chip)))
4801 goto get_irqchip_out;
4807 case KVM_SET_IRQCHIP: {
4808 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4809 struct kvm_irqchip *chip;
4811 chip = memdup_user(argp, sizeof(*chip));
4818 if (!irqchip_kernel(kvm))
4819 goto set_irqchip_out;
4820 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4822 goto set_irqchip_out;
4830 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4833 if (!kvm->arch.vpit)
4835 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4839 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4846 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4849 if (!kvm->arch.vpit)
4851 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4854 case KVM_GET_PIT2: {
4856 if (!kvm->arch.vpit)
4858 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4862 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4867 case KVM_SET_PIT2: {
4869 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4872 if (!kvm->arch.vpit)
4874 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4877 case KVM_REINJECT_CONTROL: {
4878 struct kvm_reinject_control control;
4880 if (copy_from_user(&control, argp, sizeof(control)))
4882 r = kvm_vm_ioctl_reinject(kvm, &control);
4885 case KVM_SET_BOOT_CPU_ID:
4887 mutex_lock(&kvm->lock);
4888 if (kvm->created_vcpus)
4891 kvm->arch.bsp_vcpu_id = arg;
4892 mutex_unlock(&kvm->lock);
4894 case KVM_XEN_HVM_CONFIG: {
4895 struct kvm_xen_hvm_config xhc;
4897 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4902 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4906 case KVM_SET_CLOCK: {
4907 struct kvm_clock_data user_ns;
4911 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4920 * TODO: userspace has to take care of races with VCPU_RUN, so
4921 * kvm_gen_update_masterclock() can be cut down to locked
4922 * pvclock_update_vm_gtod_copy().
4924 kvm_gen_update_masterclock(kvm);
4925 now_ns = get_kvmclock_ns(kvm);
4926 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4927 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4930 case KVM_GET_CLOCK: {
4931 struct kvm_clock_data user_ns;
4934 now_ns = get_kvmclock_ns(kvm);
4935 user_ns.clock = now_ns;
4936 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4937 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4940 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4945 case KVM_MEMORY_ENCRYPT_OP: {
4947 if (kvm_x86_ops->mem_enc_op)
4948 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4951 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4952 struct kvm_enc_region region;
4955 if (copy_from_user(®ion, argp, sizeof(region)))
4959 if (kvm_x86_ops->mem_enc_reg_region)
4960 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4963 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4964 struct kvm_enc_region region;
4967 if (copy_from_user(®ion, argp, sizeof(region)))
4971 if (kvm_x86_ops->mem_enc_unreg_region)
4972 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4975 case KVM_HYPERV_EVENTFD: {
4976 struct kvm_hyperv_eventfd hvevfd;
4979 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4981 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4984 case KVM_SET_PMU_EVENT_FILTER:
4985 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
4994 static void kvm_init_msr_list(void)
4999 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
5000 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5004 * Even MSRs that are valid in the host may not be exposed
5005 * to the guests in some cases.
5007 switch (msrs_to_save[i]) {
5008 case MSR_IA32_BNDCFGS:
5009 if (!kvm_mpx_supported())
5013 if (!kvm_x86_ops->rdtscp_supported())
5016 case MSR_IA32_RTIT_CTL:
5017 case MSR_IA32_RTIT_STATUS:
5018 if (!kvm_x86_ops->pt_supported())
5021 case MSR_IA32_RTIT_CR3_MATCH:
5022 if (!kvm_x86_ops->pt_supported() ||
5023 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5026 case MSR_IA32_RTIT_OUTPUT_BASE:
5027 case MSR_IA32_RTIT_OUTPUT_MASK:
5028 if (!kvm_x86_ops->pt_supported() ||
5029 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5030 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5033 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5034 if (!kvm_x86_ops->pt_supported() ||
5035 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5036 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5045 msrs_to_save[j] = msrs_to_save[i];
5048 num_msrs_to_save = j;
5050 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5051 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5055 emulated_msrs[j] = emulated_msrs[i];
5058 num_emulated_msrs = j;
5060 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5061 struct kvm_msr_entry msr;
5063 msr.index = msr_based_features[i];
5064 if (kvm_get_msr_feature(&msr))
5068 msr_based_features[j] = msr_based_features[i];
5071 num_msr_based_features = j;
5074 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5082 if (!(lapic_in_kernel(vcpu) &&
5083 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5084 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5095 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5102 if (!(lapic_in_kernel(vcpu) &&
5103 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5105 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5107 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5117 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5118 struct kvm_segment *var, int seg)
5120 kvm_x86_ops->set_segment(vcpu, var, seg);
5123 void kvm_get_segment(struct kvm_vcpu *vcpu,
5124 struct kvm_segment *var, int seg)
5126 kvm_x86_ops->get_segment(vcpu, var, seg);
5129 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5130 struct x86_exception *exception)
5134 BUG_ON(!mmu_is_nested(vcpu));
5136 /* NPT walks are always user-walks */
5137 access |= PFERR_USER_MASK;
5138 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5143 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5144 struct x86_exception *exception)
5146 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5147 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5150 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5151 struct x86_exception *exception)
5153 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5154 access |= PFERR_FETCH_MASK;
5155 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5158 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5159 struct x86_exception *exception)
5161 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5162 access |= PFERR_WRITE_MASK;
5163 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5166 /* uses this to access any guest's mapped memory without checking CPL */
5167 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5168 struct x86_exception *exception)
5170 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5173 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5174 struct kvm_vcpu *vcpu, u32 access,
5175 struct x86_exception *exception)
5178 int r = X86EMUL_CONTINUE;
5181 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5183 unsigned offset = addr & (PAGE_SIZE-1);
5184 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5187 if (gpa == UNMAPPED_GVA)
5188 return X86EMUL_PROPAGATE_FAULT;
5189 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5192 r = X86EMUL_IO_NEEDED;
5204 /* used for instruction fetching */
5205 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5206 gva_t addr, void *val, unsigned int bytes,
5207 struct x86_exception *exception)
5209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5210 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5214 /* Inline kvm_read_guest_virt_helper for speed. */
5215 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5217 if (unlikely(gpa == UNMAPPED_GVA))
5218 return X86EMUL_PROPAGATE_FAULT;
5220 offset = addr & (PAGE_SIZE-1);
5221 if (WARN_ON(offset + bytes > PAGE_SIZE))
5222 bytes = (unsigned)PAGE_SIZE - offset;
5223 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5225 if (unlikely(ret < 0))
5226 return X86EMUL_IO_NEEDED;
5228 return X86EMUL_CONTINUE;
5231 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5232 gva_t addr, void *val, unsigned int bytes,
5233 struct x86_exception *exception)
5235 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5238 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5239 * is returned, but our callers are not ready for that and they blindly
5240 * call kvm_inject_page_fault. Ensure that they at least do not leak
5241 * uninitialized kernel stack memory into cr2 and error code.
5243 memset(exception, 0, sizeof(*exception));
5244 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5247 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5249 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5250 gva_t addr, void *val, unsigned int bytes,
5251 struct x86_exception *exception, bool system)
5253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5256 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5257 access |= PFERR_USER_MASK;
5259 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5262 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5263 unsigned long addr, void *val, unsigned int bytes)
5265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5266 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5268 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5271 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5272 struct kvm_vcpu *vcpu, u32 access,
5273 struct x86_exception *exception)
5276 int r = X86EMUL_CONTINUE;
5279 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5282 unsigned offset = addr & (PAGE_SIZE-1);
5283 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5286 if (gpa == UNMAPPED_GVA)
5287 return X86EMUL_PROPAGATE_FAULT;
5288 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5290 r = X86EMUL_IO_NEEDED;
5302 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5303 unsigned int bytes, struct x86_exception *exception,
5306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5307 u32 access = PFERR_WRITE_MASK;
5309 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5310 access |= PFERR_USER_MASK;
5312 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5316 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5317 unsigned int bytes, struct x86_exception *exception)
5319 /* kvm_write_guest_virt_system can pull in tons of pages. */
5320 vcpu->arch.l1tf_flush_l1d = true;
5322 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5323 PFERR_WRITE_MASK, exception);
5325 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5327 int handle_ud(struct kvm_vcpu *vcpu)
5329 int emul_type = EMULTYPE_TRAP_UD;
5330 enum emulation_result er;
5331 char sig[5]; /* ud2; .ascii "kvm" */
5332 struct x86_exception e;
5334 if (force_emulation_prefix &&
5335 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5336 sig, sizeof(sig), &e) == 0 &&
5337 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5338 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5342 er = kvm_emulate_instruction(vcpu, emul_type);
5343 if (er == EMULATE_USER_EXIT)
5345 if (er != EMULATE_DONE)
5346 kvm_queue_exception(vcpu, UD_VECTOR);
5349 EXPORT_SYMBOL_GPL(handle_ud);
5351 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5352 gpa_t gpa, bool write)
5354 /* For APIC access vmexit */
5355 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5358 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5359 trace_vcpu_match_mmio(gva, gpa, write, true);
5366 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5367 gpa_t *gpa, struct x86_exception *exception,
5370 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5371 | (write ? PFERR_WRITE_MASK : 0);
5374 * currently PKRU is only applied to ept enabled guest so
5375 * there is no pkey in EPT page table for L1 guest or EPT
5376 * shadow page table for L2 guest.
5378 if (vcpu_match_mmio_gva(vcpu, gva)
5379 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5380 vcpu->arch.mmio_access, 0, access)) {
5381 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5382 (gva & (PAGE_SIZE - 1));
5383 trace_vcpu_match_mmio(gva, *gpa, write, false);
5387 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5389 if (*gpa == UNMAPPED_GVA)
5392 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5395 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5396 const void *val, int bytes)
5400 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5403 kvm_page_track_write(vcpu, gpa, val, bytes);
5407 struct read_write_emulator_ops {
5408 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5410 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5411 void *val, int bytes);
5412 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5413 int bytes, void *val);
5414 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5415 void *val, int bytes);
5419 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5421 if (vcpu->mmio_read_completed) {
5422 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5423 vcpu->mmio_fragments[0].gpa, val);
5424 vcpu->mmio_read_completed = 0;
5431 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5432 void *val, int bytes)
5434 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5437 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5438 void *val, int bytes)
5440 return emulator_write_phys(vcpu, gpa, val, bytes);
5443 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5445 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5446 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5449 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5450 void *val, int bytes)
5452 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5453 return X86EMUL_IO_NEEDED;
5456 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5457 void *val, int bytes)
5459 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5461 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5462 return X86EMUL_CONTINUE;
5465 static const struct read_write_emulator_ops read_emultor = {
5466 .read_write_prepare = read_prepare,
5467 .read_write_emulate = read_emulate,
5468 .read_write_mmio = vcpu_mmio_read,
5469 .read_write_exit_mmio = read_exit_mmio,
5472 static const struct read_write_emulator_ops write_emultor = {
5473 .read_write_emulate = write_emulate,
5474 .read_write_mmio = write_mmio,
5475 .read_write_exit_mmio = write_exit_mmio,
5479 static int emulator_read_write_onepage(unsigned long addr, void *val,
5481 struct x86_exception *exception,
5482 struct kvm_vcpu *vcpu,
5483 const struct read_write_emulator_ops *ops)
5487 bool write = ops->write;
5488 struct kvm_mmio_fragment *frag;
5489 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5492 * If the exit was due to a NPF we may already have a GPA.
5493 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5494 * Note, this cannot be used on string operations since string
5495 * operation using rep will only have the initial GPA from the NPF
5498 if (vcpu->arch.gpa_available &&
5499 emulator_can_use_gpa(ctxt) &&
5500 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5501 gpa = vcpu->arch.gpa_val;
5502 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5504 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5506 return X86EMUL_PROPAGATE_FAULT;
5509 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5510 return X86EMUL_CONTINUE;
5513 * Is this MMIO handled locally?
5515 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5516 if (handled == bytes)
5517 return X86EMUL_CONTINUE;
5523 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5524 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5528 return X86EMUL_CONTINUE;
5531 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5533 void *val, unsigned int bytes,
5534 struct x86_exception *exception,
5535 const struct read_write_emulator_ops *ops)
5537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5541 if (ops->read_write_prepare &&
5542 ops->read_write_prepare(vcpu, val, bytes))
5543 return X86EMUL_CONTINUE;
5545 vcpu->mmio_nr_fragments = 0;
5547 /* Crossing a page boundary? */
5548 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5551 now = -addr & ~PAGE_MASK;
5552 rc = emulator_read_write_onepage(addr, val, now, exception,
5555 if (rc != X86EMUL_CONTINUE)
5558 if (ctxt->mode != X86EMUL_MODE_PROT64)
5564 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5566 if (rc != X86EMUL_CONTINUE)
5569 if (!vcpu->mmio_nr_fragments)
5572 gpa = vcpu->mmio_fragments[0].gpa;
5574 vcpu->mmio_needed = 1;
5575 vcpu->mmio_cur_fragment = 0;
5577 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5578 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5579 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5580 vcpu->run->mmio.phys_addr = gpa;
5582 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5585 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5589 struct x86_exception *exception)
5591 return emulator_read_write(ctxt, addr, val, bytes,
5592 exception, &read_emultor);
5595 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5599 struct x86_exception *exception)
5601 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5602 exception, &write_emultor);
5605 #define CMPXCHG_TYPE(t, ptr, old, new) \
5606 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5608 #ifdef CONFIG_X86_64
5609 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5611 # define CMPXCHG64(ptr, old, new) \
5612 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5615 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5620 struct x86_exception *exception)
5622 struct kvm_host_map map;
5623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5628 /* guests cmpxchg8b have to be emulated atomically */
5629 if (bytes > 8 || (bytes & (bytes - 1)))
5632 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5634 if (gpa == UNMAPPED_GVA ||
5635 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5638 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5641 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5644 kaddr = map.hva + offset_in_page(gpa);
5648 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5651 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5654 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5657 exchanged = CMPXCHG64(kaddr, old, new);
5663 kvm_vcpu_unmap(vcpu, &map, true);
5666 return X86EMUL_CMPXCHG_FAILED;
5668 kvm_page_track_write(vcpu, gpa, new, bytes);
5670 return X86EMUL_CONTINUE;
5673 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5675 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5678 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5682 for (i = 0; i < vcpu->arch.pio.count; i++) {
5683 if (vcpu->arch.pio.in)
5684 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5685 vcpu->arch.pio.size, pd);
5687 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5688 vcpu->arch.pio.port, vcpu->arch.pio.size,
5692 pd += vcpu->arch.pio.size;
5697 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5698 unsigned short port, void *val,
5699 unsigned int count, bool in)
5701 vcpu->arch.pio.port = port;
5702 vcpu->arch.pio.in = in;
5703 vcpu->arch.pio.count = count;
5704 vcpu->arch.pio.size = size;
5706 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5707 vcpu->arch.pio.count = 0;
5711 vcpu->run->exit_reason = KVM_EXIT_IO;
5712 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5713 vcpu->run->io.size = size;
5714 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5715 vcpu->run->io.count = count;
5716 vcpu->run->io.port = port;
5721 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5722 int size, unsigned short port, void *val,
5725 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5728 if (vcpu->arch.pio.count)
5731 memset(vcpu->arch.pio_data, 0, size * count);
5733 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5736 memcpy(val, vcpu->arch.pio_data, size * count);
5737 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5738 vcpu->arch.pio.count = 0;
5745 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5746 int size, unsigned short port,
5747 const void *val, unsigned int count)
5749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5751 memcpy(vcpu->arch.pio_data, val, size * count);
5752 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5753 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5756 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5758 return kvm_x86_ops->get_segment_base(vcpu, seg);
5761 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5763 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5766 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5768 if (!need_emulate_wbinvd(vcpu))
5769 return X86EMUL_CONTINUE;
5771 if (kvm_x86_ops->has_wbinvd_exit()) {
5772 int cpu = get_cpu();
5774 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5775 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5776 wbinvd_ipi, NULL, 1);
5778 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5781 return X86EMUL_CONTINUE;
5784 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5786 kvm_emulate_wbinvd_noskip(vcpu);
5787 return kvm_skip_emulated_instruction(vcpu);
5789 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5793 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5795 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5798 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5799 unsigned long *dest)
5801 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5804 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5805 unsigned long value)
5808 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5811 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5813 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5816 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5819 unsigned long value;
5823 value = kvm_read_cr0(vcpu);
5826 value = vcpu->arch.cr2;
5829 value = kvm_read_cr3(vcpu);
5832 value = kvm_read_cr4(vcpu);
5835 value = kvm_get_cr8(vcpu);
5838 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5845 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5847 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5852 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5855 vcpu->arch.cr2 = val;
5858 res = kvm_set_cr3(vcpu, val);
5861 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5864 res = kvm_set_cr8(vcpu, val);
5867 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5874 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5876 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5879 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5881 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5884 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5886 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5889 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5891 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5894 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5896 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5899 static unsigned long emulator_get_cached_segment_base(
5900 struct x86_emulate_ctxt *ctxt, int seg)
5902 return get_segment_base(emul_to_vcpu(ctxt), seg);
5905 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5906 struct desc_struct *desc, u32 *base3,
5909 struct kvm_segment var;
5911 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5912 *selector = var.selector;
5915 memset(desc, 0, sizeof(*desc));
5923 set_desc_limit(desc, var.limit);
5924 set_desc_base(desc, (unsigned long)var.base);
5925 #ifdef CONFIG_X86_64
5927 *base3 = var.base >> 32;
5929 desc->type = var.type;
5931 desc->dpl = var.dpl;
5932 desc->p = var.present;
5933 desc->avl = var.avl;
5941 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5942 struct desc_struct *desc, u32 base3,
5945 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5946 struct kvm_segment var;
5948 var.selector = selector;
5949 var.base = get_desc_base(desc);
5950 #ifdef CONFIG_X86_64
5951 var.base |= ((u64)base3) << 32;
5953 var.limit = get_desc_limit(desc);
5955 var.limit = (var.limit << 12) | 0xfff;
5956 var.type = desc->type;
5957 var.dpl = desc->dpl;
5962 var.avl = desc->avl;
5963 var.present = desc->p;
5964 var.unusable = !var.present;
5967 kvm_set_segment(vcpu, &var, seg);
5971 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5972 u32 msr_index, u64 *pdata)
5974 struct msr_data msr;
5977 msr.index = msr_index;
5978 msr.host_initiated = false;
5979 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5987 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5988 u32 msr_index, u64 data)
5990 struct msr_data msr;
5993 msr.index = msr_index;
5994 msr.host_initiated = false;
5995 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5998 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6002 return vcpu->arch.smbase;
6005 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6007 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6009 vcpu->arch.smbase = smbase;
6012 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6015 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6018 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6019 u32 pmc, u64 *pdata)
6021 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6024 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6026 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6029 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6030 struct x86_instruction_info *info,
6031 enum x86_intercept_stage stage)
6033 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6036 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6037 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6039 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6042 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6044 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6047 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6049 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6052 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6054 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6057 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6059 return emul_to_vcpu(ctxt)->arch.hflags;
6062 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6064 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6067 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6068 const char *smstate)
6070 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6073 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6075 kvm_smm_changed(emul_to_vcpu(ctxt));
6078 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6080 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6083 static const struct x86_emulate_ops emulate_ops = {
6084 .read_gpr = emulator_read_gpr,
6085 .write_gpr = emulator_write_gpr,
6086 .read_std = emulator_read_std,
6087 .write_std = emulator_write_std,
6088 .read_phys = kvm_read_guest_phys_system,
6089 .fetch = kvm_fetch_guest_virt,
6090 .read_emulated = emulator_read_emulated,
6091 .write_emulated = emulator_write_emulated,
6092 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6093 .invlpg = emulator_invlpg,
6094 .pio_in_emulated = emulator_pio_in_emulated,
6095 .pio_out_emulated = emulator_pio_out_emulated,
6096 .get_segment = emulator_get_segment,
6097 .set_segment = emulator_set_segment,
6098 .get_cached_segment_base = emulator_get_cached_segment_base,
6099 .get_gdt = emulator_get_gdt,
6100 .get_idt = emulator_get_idt,
6101 .set_gdt = emulator_set_gdt,
6102 .set_idt = emulator_set_idt,
6103 .get_cr = emulator_get_cr,
6104 .set_cr = emulator_set_cr,
6105 .cpl = emulator_get_cpl,
6106 .get_dr = emulator_get_dr,
6107 .set_dr = emulator_set_dr,
6108 .get_smbase = emulator_get_smbase,
6109 .set_smbase = emulator_set_smbase,
6110 .set_msr = emulator_set_msr,
6111 .get_msr = emulator_get_msr,
6112 .check_pmc = emulator_check_pmc,
6113 .read_pmc = emulator_read_pmc,
6114 .halt = emulator_halt,
6115 .wbinvd = emulator_wbinvd,
6116 .fix_hypercall = emulator_fix_hypercall,
6117 .intercept = emulator_intercept,
6118 .get_cpuid = emulator_get_cpuid,
6119 .set_nmi_mask = emulator_set_nmi_mask,
6120 .get_hflags = emulator_get_hflags,
6121 .set_hflags = emulator_set_hflags,
6122 .pre_leave_smm = emulator_pre_leave_smm,
6123 .post_leave_smm = emulator_post_leave_smm,
6124 .set_xcr = emulator_set_xcr,
6127 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6129 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6131 * an sti; sti; sequence only disable interrupts for the first
6132 * instruction. So, if the last instruction, be it emulated or
6133 * not, left the system with the INT_STI flag enabled, it
6134 * means that the last instruction is an sti. We should not
6135 * leave the flag on in this case. The same goes for mov ss
6137 if (int_shadow & mask)
6139 if (unlikely(int_shadow || mask)) {
6140 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6142 kvm_make_request(KVM_REQ_EVENT, vcpu);
6146 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6148 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6149 if (ctxt->exception.vector == PF_VECTOR)
6150 return kvm_propagate_fault(vcpu, &ctxt->exception);
6152 if (ctxt->exception.error_code_valid)
6153 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6154 ctxt->exception.error_code);
6156 kvm_queue_exception(vcpu, ctxt->exception.vector);
6160 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6162 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6165 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6167 ctxt->eflags = kvm_get_rflags(vcpu);
6168 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6170 ctxt->eip = kvm_rip_read(vcpu);
6171 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6172 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6173 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6174 cs_db ? X86EMUL_MODE_PROT32 :
6175 X86EMUL_MODE_PROT16;
6176 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6177 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6178 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6180 init_decode_cache(ctxt);
6181 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6184 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6186 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6189 init_emulate_ctxt(vcpu);
6193 ctxt->_eip = ctxt->eip + inc_eip;
6194 ret = emulate_int_real(ctxt, irq);
6196 if (ret != X86EMUL_CONTINUE)
6197 return EMULATE_FAIL;
6199 ctxt->eip = ctxt->_eip;
6200 kvm_rip_write(vcpu, ctxt->eip);
6201 kvm_set_rflags(vcpu, ctxt->eflags);
6203 return EMULATE_DONE;
6205 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6207 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6209 int r = EMULATE_DONE;
6211 ++vcpu->stat.insn_emulation_fail;
6212 trace_kvm_emulate_insn_failed(vcpu);
6214 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6215 return EMULATE_FAIL;
6217 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6218 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6219 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6220 vcpu->run->internal.ndata = 0;
6221 r = EMULATE_USER_EXIT;
6224 kvm_queue_exception(vcpu, UD_VECTOR);
6229 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6230 bool write_fault_to_shadow_pgtable,
6236 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6239 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6242 if (!vcpu->arch.mmu->direct_map) {
6244 * Write permission should be allowed since only
6245 * write access need to be emulated.
6247 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6250 * If the mapping is invalid in guest, let cpu retry
6251 * it to generate fault.
6253 if (gpa == UNMAPPED_GVA)
6258 * Do not retry the unhandleable instruction if it faults on the
6259 * readonly host memory, otherwise it will goto a infinite loop:
6260 * retry instruction -> write #PF -> emulation fail -> retry
6261 * instruction -> ...
6263 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6266 * If the instruction failed on the error pfn, it can not be fixed,
6267 * report the error to userspace.
6269 if (is_error_noslot_pfn(pfn))
6272 kvm_release_pfn_clean(pfn);
6274 /* The instructions are well-emulated on direct mmu. */
6275 if (vcpu->arch.mmu->direct_map) {
6276 unsigned int indirect_shadow_pages;
6278 spin_lock(&vcpu->kvm->mmu_lock);
6279 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6280 spin_unlock(&vcpu->kvm->mmu_lock);
6282 if (indirect_shadow_pages)
6283 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6289 * if emulation was due to access to shadowed page table
6290 * and it failed try to unshadow page and re-enter the
6291 * guest to let CPU execute the instruction.
6293 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6296 * If the access faults on its page table, it can not
6297 * be fixed by unprotecting shadow page and it should
6298 * be reported to userspace.
6300 return !write_fault_to_shadow_pgtable;
6303 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6304 unsigned long cr2, int emulation_type)
6306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6307 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6309 last_retry_eip = vcpu->arch.last_retry_eip;
6310 last_retry_addr = vcpu->arch.last_retry_addr;
6313 * If the emulation is caused by #PF and it is non-page_table
6314 * writing instruction, it means the VM-EXIT is caused by shadow
6315 * page protected, we can zap the shadow page and retry this
6316 * instruction directly.
6318 * Note: if the guest uses a non-page-table modifying instruction
6319 * on the PDE that points to the instruction, then we will unmap
6320 * the instruction and go to an infinite loop. So, we cache the
6321 * last retried eip and the last fault address, if we meet the eip
6322 * and the address again, we can break out of the potential infinite
6325 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6327 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6330 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6333 if (x86_page_table_writing_insn(ctxt))
6336 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6339 vcpu->arch.last_retry_eip = ctxt->eip;
6340 vcpu->arch.last_retry_addr = cr2;
6342 if (!vcpu->arch.mmu->direct_map)
6343 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6345 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6350 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6351 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6353 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6355 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6356 /* This is a good place to trace that we are exiting SMM. */
6357 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6359 /* Process a latched INIT or SMI, if any. */
6360 kvm_make_request(KVM_REQ_EVENT, vcpu);
6363 kvm_mmu_reset_context(vcpu);
6366 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6375 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6376 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6381 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6383 struct kvm_run *kvm_run = vcpu->run;
6385 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6386 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6387 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6388 kvm_run->debug.arch.exception = DB_VECTOR;
6389 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6390 *r = EMULATE_USER_EXIT;
6392 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6396 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6398 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6401 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6402 if (unlikely(r != EMULATE_DONE))
6406 * rflags is the old, "raw" value of the flags. The new value has
6407 * not been saved yet.
6409 * This is correct even for TF set by the guest, because "the
6410 * processor will not generate this exception after the instruction
6411 * that sets the TF flag".
6413 if (unlikely(rflags & X86_EFLAGS_TF))
6414 kvm_vcpu_do_singlestep(vcpu, &r);
6415 return r == EMULATE_DONE;
6417 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6419 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6421 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6422 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6423 struct kvm_run *kvm_run = vcpu->run;
6424 unsigned long eip = kvm_get_linear_rip(vcpu);
6425 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6426 vcpu->arch.guest_debug_dr7,
6430 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6431 kvm_run->debug.arch.pc = eip;
6432 kvm_run->debug.arch.exception = DB_VECTOR;
6433 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6434 *r = EMULATE_USER_EXIT;
6439 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6440 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6441 unsigned long eip = kvm_get_linear_rip(vcpu);
6442 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6447 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6448 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6449 kvm_queue_exception(vcpu, DB_VECTOR);
6458 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6460 switch (ctxt->opcode_len) {
6467 case 0xe6: /* OUT */
6471 case 0x6c: /* INS */
6473 case 0x6e: /* OUTS */
6480 case 0x33: /* RDPMC */
6489 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6496 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6497 bool writeback = true;
6498 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6500 vcpu->arch.l1tf_flush_l1d = true;
6503 * Clear write_fault_to_shadow_pgtable here to ensure it is
6506 vcpu->arch.write_fault_to_shadow_pgtable = false;
6507 kvm_clear_exception_queue(vcpu);
6509 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6510 init_emulate_ctxt(vcpu);
6513 * We will reenter on the same instruction since
6514 * we do not set complete_userspace_io. This does not
6515 * handle watchpoints yet, those would be handled in
6518 if (!(emulation_type & EMULTYPE_SKIP) &&
6519 kvm_vcpu_check_breakpoint(vcpu, &r))
6522 ctxt->interruptibility = 0;
6523 ctxt->have_exception = false;
6524 ctxt->exception.vector = -1;
6525 ctxt->perm_ok = false;
6527 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6529 r = x86_decode_insn(ctxt, insn, insn_len);
6531 trace_kvm_emulate_insn_start(vcpu);
6532 ++vcpu->stat.insn_emulation;
6533 if (r != EMULATION_OK) {
6534 if (emulation_type & EMULTYPE_TRAP_UD)
6535 return EMULATE_FAIL;
6536 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6538 return EMULATE_DONE;
6539 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6540 return EMULATE_DONE;
6541 if (emulation_type & EMULTYPE_SKIP)
6542 return EMULATE_FAIL;
6543 return handle_emulation_failure(vcpu, emulation_type);
6547 if ((emulation_type & EMULTYPE_VMWARE) &&
6548 !is_vmware_backdoor_opcode(ctxt))
6549 return EMULATE_FAIL;
6551 if (emulation_type & EMULTYPE_SKIP) {
6552 kvm_rip_write(vcpu, ctxt->_eip);
6553 if (ctxt->eflags & X86_EFLAGS_RF)
6554 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6555 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
6556 return EMULATE_DONE;
6559 if (retry_instruction(ctxt, cr2, emulation_type))
6560 return EMULATE_DONE;
6562 /* this is needed for vmware backdoor interface to work since it
6563 changes registers values during IO operation */
6564 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6565 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6566 emulator_invalidate_register_cache(ctxt);
6570 /* Save the faulting GPA (cr2) in the address field */
6571 ctxt->exception.address = cr2;
6573 r = x86_emulate_insn(ctxt);
6575 if (r == EMULATION_INTERCEPTED)
6576 return EMULATE_DONE;
6578 if (r == EMULATION_FAILED) {
6579 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6581 return EMULATE_DONE;
6583 return handle_emulation_failure(vcpu, emulation_type);
6586 if (ctxt->have_exception) {
6588 if (inject_emulated_exception(vcpu))
6590 } else if (vcpu->arch.pio.count) {
6591 if (!vcpu->arch.pio.in) {
6592 /* FIXME: return into emulator if single-stepping. */
6593 vcpu->arch.pio.count = 0;
6596 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6598 r = EMULATE_USER_EXIT;
6599 } else if (vcpu->mmio_needed) {
6600 if (!vcpu->mmio_is_write)
6602 r = EMULATE_USER_EXIT;
6603 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6604 } else if (r == EMULATION_RESTART)
6610 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6611 toggle_interruptibility(vcpu, ctxt->interruptibility);
6612 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6613 kvm_rip_write(vcpu, ctxt->eip);
6614 if (r == EMULATE_DONE && ctxt->tf)
6615 kvm_vcpu_do_singlestep(vcpu, &r);
6616 if (!ctxt->have_exception ||
6617 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6618 __kvm_set_rflags(vcpu, ctxt->eflags);
6621 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6622 * do nothing, and it will be requested again as soon as
6623 * the shadow expires. But we still need to check here,
6624 * because POPF has no interrupt shadow.
6626 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6627 kvm_make_request(KVM_REQ_EVENT, vcpu);
6629 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6634 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6636 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6638 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6640 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6641 void *insn, int insn_len)
6643 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6645 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6647 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6649 vcpu->arch.pio.count = 0;
6653 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6655 vcpu->arch.pio.count = 0;
6657 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6660 return kvm_skip_emulated_instruction(vcpu);
6663 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6664 unsigned short port)
6666 unsigned long val = kvm_rax_read(vcpu);
6667 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6668 size, port, &val, 1);
6673 * Workaround userspace that relies on old KVM behavior of %rip being
6674 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6677 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6678 vcpu->arch.complete_userspace_io =
6679 complete_fast_pio_out_port_0x7e;
6680 kvm_skip_emulated_instruction(vcpu);
6682 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6683 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6688 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6692 /* We should only ever be called with arch.pio.count equal to 1 */
6693 BUG_ON(vcpu->arch.pio.count != 1);
6695 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6696 vcpu->arch.pio.count = 0;
6700 /* For size less than 4 we merge, else we zero extend */
6701 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6704 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6705 * the copy and tracing
6707 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6708 vcpu->arch.pio.port, &val, 1);
6709 kvm_rax_write(vcpu, val);
6711 return kvm_skip_emulated_instruction(vcpu);
6714 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6715 unsigned short port)
6720 /* For size less than 4 we merge, else we zero extend */
6721 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6723 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6726 kvm_rax_write(vcpu, val);
6730 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6731 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6736 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6741 ret = kvm_fast_pio_in(vcpu, size, port);
6743 ret = kvm_fast_pio_out(vcpu, size, port);
6744 return ret && kvm_skip_emulated_instruction(vcpu);
6746 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6748 static int kvmclock_cpu_down_prep(unsigned int cpu)
6750 __this_cpu_write(cpu_tsc_khz, 0);
6754 static void tsc_khz_changed(void *data)
6756 struct cpufreq_freqs *freq = data;
6757 unsigned long khz = 0;
6761 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6762 khz = cpufreq_quick_get(raw_smp_processor_id());
6765 __this_cpu_write(cpu_tsc_khz, khz);
6768 #ifdef CONFIG_X86_64
6769 static void kvm_hyperv_tsc_notifier(void)
6772 struct kvm_vcpu *vcpu;
6775 mutex_lock(&kvm_lock);
6776 list_for_each_entry(kvm, &vm_list, vm_list)
6777 kvm_make_mclock_inprogress_request(kvm);
6779 hyperv_stop_tsc_emulation();
6781 /* TSC frequency always matches when on Hyper-V */
6782 for_each_present_cpu(cpu)
6783 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6784 kvm_max_guest_tsc_khz = tsc_khz;
6786 list_for_each_entry(kvm, &vm_list, vm_list) {
6787 struct kvm_arch *ka = &kvm->arch;
6789 spin_lock(&ka->pvclock_gtod_sync_lock);
6791 pvclock_update_vm_gtod_copy(kvm);
6793 kvm_for_each_vcpu(cpu, vcpu, kvm)
6794 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6796 kvm_for_each_vcpu(cpu, vcpu, kvm)
6797 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6799 spin_unlock(&ka->pvclock_gtod_sync_lock);
6801 mutex_unlock(&kvm_lock);
6805 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6808 struct kvm_vcpu *vcpu;
6809 int i, send_ipi = 0;
6812 * We allow guests to temporarily run on slowing clocks,
6813 * provided we notify them after, or to run on accelerating
6814 * clocks, provided we notify them before. Thus time never
6817 * However, we have a problem. We can't atomically update
6818 * the frequency of a given CPU from this function; it is
6819 * merely a notifier, which can be called from any CPU.
6820 * Changing the TSC frequency at arbitrary points in time
6821 * requires a recomputation of local variables related to
6822 * the TSC for each VCPU. We must flag these local variables
6823 * to be updated and be sure the update takes place with the
6824 * new frequency before any guests proceed.
6826 * Unfortunately, the combination of hotplug CPU and frequency
6827 * change creates an intractable locking scenario; the order
6828 * of when these callouts happen is undefined with respect to
6829 * CPU hotplug, and they can race with each other. As such,
6830 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6831 * undefined; you can actually have a CPU frequency change take
6832 * place in between the computation of X and the setting of the
6833 * variable. To protect against this problem, all updates of
6834 * the per_cpu tsc_khz variable are done in an interrupt
6835 * protected IPI, and all callers wishing to update the value
6836 * must wait for a synchronous IPI to complete (which is trivial
6837 * if the caller is on the CPU already). This establishes the
6838 * necessary total order on variable updates.
6840 * Note that because a guest time update may take place
6841 * anytime after the setting of the VCPU's request bit, the
6842 * correct TSC value must be set before the request. However,
6843 * to ensure the update actually makes it to any guest which
6844 * starts running in hardware virtualization between the set
6845 * and the acquisition of the spinlock, we must also ping the
6846 * CPU after setting the request bit.
6850 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6852 mutex_lock(&kvm_lock);
6853 list_for_each_entry(kvm, &vm_list, vm_list) {
6854 kvm_for_each_vcpu(i, vcpu, kvm) {
6855 if (vcpu->cpu != cpu)
6857 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6858 if (vcpu->cpu != raw_smp_processor_id())
6862 mutex_unlock(&kvm_lock);
6864 if (freq->old < freq->new && send_ipi) {
6866 * We upscale the frequency. Must make the guest
6867 * doesn't see old kvmclock values while running with
6868 * the new frequency, otherwise we risk the guest sees
6869 * time go backwards.
6871 * In case we update the frequency for another cpu
6872 * (which might be in guest context) send an interrupt
6873 * to kick the cpu out of guest context. Next time
6874 * guest context is entered kvmclock will be updated,
6875 * so the guest will not see stale values.
6877 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6881 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6884 struct cpufreq_freqs *freq = data;
6887 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6889 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6892 for_each_cpu(cpu, freq->policy->cpus)
6893 __kvmclock_cpufreq_notifier(freq, cpu);
6898 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6899 .notifier_call = kvmclock_cpufreq_notifier
6902 static int kvmclock_cpu_online(unsigned int cpu)
6904 tsc_khz_changed(NULL);
6908 static void kvm_timer_init(void)
6910 max_tsc_khz = tsc_khz;
6912 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6913 #ifdef CONFIG_CPU_FREQ
6914 struct cpufreq_policy policy;
6917 memset(&policy, 0, sizeof(policy));
6919 cpufreq_get_policy(&policy, cpu);
6920 if (policy.cpuinfo.max_freq)
6921 max_tsc_khz = policy.cpuinfo.max_freq;
6924 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6925 CPUFREQ_TRANSITION_NOTIFIER);
6928 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6929 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6932 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6933 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6935 int kvm_is_in_guest(void)
6937 return __this_cpu_read(current_vcpu) != NULL;
6940 static int kvm_is_user_mode(void)
6944 if (__this_cpu_read(current_vcpu))
6945 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6947 return user_mode != 0;
6950 static unsigned long kvm_get_guest_ip(void)
6952 unsigned long ip = 0;
6954 if (__this_cpu_read(current_vcpu))
6955 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6960 static void kvm_handle_intel_pt_intr(void)
6962 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6964 kvm_make_request(KVM_REQ_PMI, vcpu);
6965 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6966 (unsigned long *)&vcpu->arch.pmu.global_status);
6969 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6970 .is_in_guest = kvm_is_in_guest,
6971 .is_user_mode = kvm_is_user_mode,
6972 .get_guest_ip = kvm_get_guest_ip,
6973 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
6976 #ifdef CONFIG_X86_64
6977 static void pvclock_gtod_update_fn(struct work_struct *work)
6981 struct kvm_vcpu *vcpu;
6984 mutex_lock(&kvm_lock);
6985 list_for_each_entry(kvm, &vm_list, vm_list)
6986 kvm_for_each_vcpu(i, vcpu, kvm)
6987 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6988 atomic_set(&kvm_guest_has_master_clock, 0);
6989 mutex_unlock(&kvm_lock);
6992 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6995 * Notification about pvclock gtod data update.
6997 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7000 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7001 struct timekeeper *tk = priv;
7003 update_pvclock_gtod(tk);
7005 /* disable master clock if host does not trust, or does not
7006 * use, TSC based clocksource.
7008 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7009 atomic_read(&kvm_guest_has_master_clock) != 0)
7010 queue_work(system_long_wq, &pvclock_gtod_work);
7015 static struct notifier_block pvclock_gtod_notifier = {
7016 .notifier_call = pvclock_gtod_notify,
7020 int kvm_arch_init(void *opaque)
7023 struct kvm_x86_ops *ops = opaque;
7026 printk(KERN_ERR "kvm: already loaded the other module\n");
7031 if (!ops->cpu_has_kvm_support()) {
7032 printk(KERN_ERR "kvm: no hardware support\n");
7036 if (ops->disabled_by_bios()) {
7037 printk(KERN_ERR "kvm: disabled by bios\n");
7043 * KVM explicitly assumes that the guest has an FPU and
7044 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7045 * vCPU's FPU state as a fxregs_state struct.
7047 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7048 printk(KERN_ERR "kvm: inadequate fpu\n");
7054 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7055 __alignof__(struct fpu), SLAB_ACCOUNT,
7057 if (!x86_fpu_cache) {
7058 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7062 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7064 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7065 goto out_free_x86_fpu_cache;
7068 r = kvm_mmu_module_init();
7070 goto out_free_percpu;
7074 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7075 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7076 PT_PRESENT_MASK, 0, sme_me_mask);
7079 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7081 if (boot_cpu_has(X86_FEATURE_XSAVE))
7082 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7085 if (pi_inject_timer == -1)
7086 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7087 #ifdef CONFIG_X86_64
7088 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7090 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7091 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7097 free_percpu(shared_msrs);
7098 out_free_x86_fpu_cache:
7099 kmem_cache_destroy(x86_fpu_cache);
7104 void kvm_arch_exit(void)
7106 #ifdef CONFIG_X86_64
7107 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7108 clear_hv_tscchange_cb();
7111 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7113 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7114 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7115 CPUFREQ_TRANSITION_NOTIFIER);
7116 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7117 #ifdef CONFIG_X86_64
7118 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7121 kvm_mmu_module_exit();
7122 free_percpu(shared_msrs);
7123 kmem_cache_destroy(x86_fpu_cache);
7126 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7128 ++vcpu->stat.halt_exits;
7129 if (lapic_in_kernel(vcpu)) {
7130 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7133 vcpu->run->exit_reason = KVM_EXIT_HLT;
7137 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7139 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7141 int ret = kvm_skip_emulated_instruction(vcpu);
7143 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7144 * KVM_EXIT_DEBUG here.
7146 return kvm_vcpu_halt(vcpu) && ret;
7148 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7150 #ifdef CONFIG_X86_64
7151 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7152 unsigned long clock_type)
7154 struct kvm_clock_pairing clock_pairing;
7155 struct timespec64 ts;
7159 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7160 return -KVM_EOPNOTSUPP;
7162 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7163 return -KVM_EOPNOTSUPP;
7165 clock_pairing.sec = ts.tv_sec;
7166 clock_pairing.nsec = ts.tv_nsec;
7167 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7168 clock_pairing.flags = 0;
7169 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7172 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7173 sizeof(struct kvm_clock_pairing)))
7181 * kvm_pv_kick_cpu_op: Kick a vcpu.
7183 * @apicid - apicid of vcpu to be kicked.
7185 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7187 struct kvm_lapic_irq lapic_irq;
7189 lapic_irq.shorthand = 0;
7190 lapic_irq.dest_mode = 0;
7191 lapic_irq.level = 0;
7192 lapic_irq.dest_id = apicid;
7193 lapic_irq.msi_redir_hint = false;
7195 lapic_irq.delivery_mode = APIC_DM_REMRD;
7196 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7199 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7201 if (!lapic_in_kernel(vcpu)) {
7202 WARN_ON_ONCE(vcpu->arch.apicv_active);
7205 if (!vcpu->arch.apicv_active)
7208 vcpu->arch.apicv_active = false;
7209 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7212 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7214 struct kvm_vcpu *target = NULL;
7215 struct kvm_apic_map *map;
7218 map = rcu_dereference(kvm->arch.apic_map);
7220 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7221 target = map->phys_map[dest_id]->vcpu;
7225 if (target && READ_ONCE(target->ready))
7226 kvm_vcpu_yield_to(target);
7229 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7231 unsigned long nr, a0, a1, a2, a3, ret;
7234 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7235 return kvm_hv_hypercall(vcpu);
7237 nr = kvm_rax_read(vcpu);
7238 a0 = kvm_rbx_read(vcpu);
7239 a1 = kvm_rcx_read(vcpu);
7240 a2 = kvm_rdx_read(vcpu);
7241 a3 = kvm_rsi_read(vcpu);
7243 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7245 op_64_bit = is_64_bit_mode(vcpu);
7254 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7260 case KVM_HC_VAPIC_POLL_IRQ:
7263 case KVM_HC_KICK_CPU:
7264 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7265 kvm_sched_yield(vcpu->kvm, a1);
7268 #ifdef CONFIG_X86_64
7269 case KVM_HC_CLOCK_PAIRING:
7270 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7273 case KVM_HC_SEND_IPI:
7274 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7276 case KVM_HC_SCHED_YIELD:
7277 kvm_sched_yield(vcpu->kvm, a0);
7287 kvm_rax_write(vcpu, ret);
7289 ++vcpu->stat.hypercalls;
7290 return kvm_skip_emulated_instruction(vcpu);
7292 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7294 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7297 char instruction[3];
7298 unsigned long rip = kvm_rip_read(vcpu);
7300 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7302 return emulator_write_emulated(ctxt, rip, instruction, 3,
7306 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7308 return vcpu->run->request_interrupt_window &&
7309 likely(!pic_in_kernel(vcpu->kvm));
7312 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7314 struct kvm_run *kvm_run = vcpu->run;
7316 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7317 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7318 kvm_run->cr8 = kvm_get_cr8(vcpu);
7319 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7320 kvm_run->ready_for_interrupt_injection =
7321 pic_in_kernel(vcpu->kvm) ||
7322 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7325 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7329 if (!kvm_x86_ops->update_cr8_intercept)
7332 if (!lapic_in_kernel(vcpu))
7335 if (vcpu->arch.apicv_active)
7338 if (!vcpu->arch.apic->vapic_addr)
7339 max_irr = kvm_lapic_find_highest_irr(vcpu);
7346 tpr = kvm_lapic_get_cr8(vcpu);
7348 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7351 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7355 /* try to reinject previous events if any */
7357 if (vcpu->arch.exception.injected)
7358 kvm_x86_ops->queue_exception(vcpu);
7360 * Do not inject an NMI or interrupt if there is a pending
7361 * exception. Exceptions and interrupts are recognized at
7362 * instruction boundaries, i.e. the start of an instruction.
7363 * Trap-like exceptions, e.g. #DB, have higher priority than
7364 * NMIs and interrupts, i.e. traps are recognized before an
7365 * NMI/interrupt that's pending on the same instruction.
7366 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7367 * priority, but are only generated (pended) during instruction
7368 * execution, i.e. a pending fault-like exception means the
7369 * fault occurred on the *previous* instruction and must be
7370 * serviced prior to recognizing any new events in order to
7371 * fully complete the previous instruction.
7373 else if (!vcpu->arch.exception.pending) {
7374 if (vcpu->arch.nmi_injected)
7375 kvm_x86_ops->set_nmi(vcpu);
7376 else if (vcpu->arch.interrupt.injected)
7377 kvm_x86_ops->set_irq(vcpu);
7381 * Call check_nested_events() even if we reinjected a previous event
7382 * in order for caller to determine if it should require immediate-exit
7383 * from L2 to L1 due to pending L1 events which require exit
7386 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7387 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7392 /* try to inject new event if pending */
7393 if (vcpu->arch.exception.pending) {
7394 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7395 vcpu->arch.exception.has_error_code,
7396 vcpu->arch.exception.error_code);
7398 WARN_ON_ONCE(vcpu->arch.exception.injected);
7399 vcpu->arch.exception.pending = false;
7400 vcpu->arch.exception.injected = true;
7402 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7403 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7406 if (vcpu->arch.exception.nr == DB_VECTOR) {
7408 * This code assumes that nSVM doesn't use
7409 * check_nested_events(). If it does, the
7410 * DR6/DR7 changes should happen before L1
7411 * gets a #VMEXIT for an intercepted #DB in
7412 * L2. (Under VMX, on the other hand, the
7413 * DR6/DR7 changes should not happen in the
7414 * event of a VM-exit to L1 for an intercepted
7417 kvm_deliver_exception_payload(vcpu);
7418 if (vcpu->arch.dr7 & DR7_GD) {
7419 vcpu->arch.dr7 &= ~DR7_GD;
7420 kvm_update_dr7(vcpu);
7424 kvm_x86_ops->queue_exception(vcpu);
7427 /* Don't consider new event if we re-injected an event */
7428 if (kvm_event_needs_reinjection(vcpu))
7431 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7432 kvm_x86_ops->smi_allowed(vcpu)) {
7433 vcpu->arch.smi_pending = false;
7434 ++vcpu->arch.smi_count;
7436 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7437 --vcpu->arch.nmi_pending;
7438 vcpu->arch.nmi_injected = true;
7439 kvm_x86_ops->set_nmi(vcpu);
7440 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7442 * Because interrupts can be injected asynchronously, we are
7443 * calling check_nested_events again here to avoid a race condition.
7444 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7445 * proposal and current concerns. Perhaps we should be setting
7446 * KVM_REQ_EVENT only on certain events and not unconditionally?
7448 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7449 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7453 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7454 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7456 kvm_x86_ops->set_irq(vcpu);
7463 static void process_nmi(struct kvm_vcpu *vcpu)
7468 * x86 is limited to one NMI running, and one NMI pending after it.
7469 * If an NMI is already in progress, limit further NMIs to just one.
7470 * Otherwise, allow two (and we'll inject the first one immediately).
7472 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7475 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7476 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7477 kvm_make_request(KVM_REQ_EVENT, vcpu);
7480 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7483 flags |= seg->g << 23;
7484 flags |= seg->db << 22;
7485 flags |= seg->l << 21;
7486 flags |= seg->avl << 20;
7487 flags |= seg->present << 15;
7488 flags |= seg->dpl << 13;
7489 flags |= seg->s << 12;
7490 flags |= seg->type << 8;
7494 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7496 struct kvm_segment seg;
7499 kvm_get_segment(vcpu, &seg, n);
7500 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7503 offset = 0x7f84 + n * 12;
7505 offset = 0x7f2c + (n - 3) * 12;
7507 put_smstate(u32, buf, offset + 8, seg.base);
7508 put_smstate(u32, buf, offset + 4, seg.limit);
7509 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7512 #ifdef CONFIG_X86_64
7513 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7515 struct kvm_segment seg;
7519 kvm_get_segment(vcpu, &seg, n);
7520 offset = 0x7e00 + n * 16;
7522 flags = enter_smm_get_segment_flags(&seg) >> 8;
7523 put_smstate(u16, buf, offset, seg.selector);
7524 put_smstate(u16, buf, offset + 2, flags);
7525 put_smstate(u32, buf, offset + 4, seg.limit);
7526 put_smstate(u64, buf, offset + 8, seg.base);
7530 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7533 struct kvm_segment seg;
7537 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7538 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7539 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7540 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7542 for (i = 0; i < 8; i++)
7543 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7545 kvm_get_dr(vcpu, 6, &val);
7546 put_smstate(u32, buf, 0x7fcc, (u32)val);
7547 kvm_get_dr(vcpu, 7, &val);
7548 put_smstate(u32, buf, 0x7fc8, (u32)val);
7550 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7551 put_smstate(u32, buf, 0x7fc4, seg.selector);
7552 put_smstate(u32, buf, 0x7f64, seg.base);
7553 put_smstate(u32, buf, 0x7f60, seg.limit);
7554 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7556 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7557 put_smstate(u32, buf, 0x7fc0, seg.selector);
7558 put_smstate(u32, buf, 0x7f80, seg.base);
7559 put_smstate(u32, buf, 0x7f7c, seg.limit);
7560 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7562 kvm_x86_ops->get_gdt(vcpu, &dt);
7563 put_smstate(u32, buf, 0x7f74, dt.address);
7564 put_smstate(u32, buf, 0x7f70, dt.size);
7566 kvm_x86_ops->get_idt(vcpu, &dt);
7567 put_smstate(u32, buf, 0x7f58, dt.address);
7568 put_smstate(u32, buf, 0x7f54, dt.size);
7570 for (i = 0; i < 6; i++)
7571 enter_smm_save_seg_32(vcpu, buf, i);
7573 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7576 put_smstate(u32, buf, 0x7efc, 0x00020000);
7577 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7580 #ifdef CONFIG_X86_64
7581 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7584 struct kvm_segment seg;
7588 for (i = 0; i < 16; i++)
7589 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7591 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7592 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7594 kvm_get_dr(vcpu, 6, &val);
7595 put_smstate(u64, buf, 0x7f68, val);
7596 kvm_get_dr(vcpu, 7, &val);
7597 put_smstate(u64, buf, 0x7f60, val);
7599 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7600 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7601 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7603 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7606 put_smstate(u32, buf, 0x7efc, 0x00020064);
7608 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7610 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7611 put_smstate(u16, buf, 0x7e90, seg.selector);
7612 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7613 put_smstate(u32, buf, 0x7e94, seg.limit);
7614 put_smstate(u64, buf, 0x7e98, seg.base);
7616 kvm_x86_ops->get_idt(vcpu, &dt);
7617 put_smstate(u32, buf, 0x7e84, dt.size);
7618 put_smstate(u64, buf, 0x7e88, dt.address);
7620 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7621 put_smstate(u16, buf, 0x7e70, seg.selector);
7622 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7623 put_smstate(u32, buf, 0x7e74, seg.limit);
7624 put_smstate(u64, buf, 0x7e78, seg.base);
7626 kvm_x86_ops->get_gdt(vcpu, &dt);
7627 put_smstate(u32, buf, 0x7e64, dt.size);
7628 put_smstate(u64, buf, 0x7e68, dt.address);
7630 for (i = 0; i < 6; i++)
7631 enter_smm_save_seg_64(vcpu, buf, i);
7635 static void enter_smm(struct kvm_vcpu *vcpu)
7637 struct kvm_segment cs, ds;
7642 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7643 memset(buf, 0, 512);
7644 #ifdef CONFIG_X86_64
7645 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7646 enter_smm_save_state_64(vcpu, buf);
7649 enter_smm_save_state_32(vcpu, buf);
7652 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7653 * vCPU state (e.g. leave guest mode) after we've saved the state into
7654 * the SMM state-save area.
7656 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7658 vcpu->arch.hflags |= HF_SMM_MASK;
7659 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7661 if (kvm_x86_ops->get_nmi_mask(vcpu))
7662 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7664 kvm_x86_ops->set_nmi_mask(vcpu, true);
7666 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7667 kvm_rip_write(vcpu, 0x8000);
7669 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7670 kvm_x86_ops->set_cr0(vcpu, cr0);
7671 vcpu->arch.cr0 = cr0;
7673 kvm_x86_ops->set_cr4(vcpu, 0);
7675 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7676 dt.address = dt.size = 0;
7677 kvm_x86_ops->set_idt(vcpu, &dt);
7679 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7681 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7682 cs.base = vcpu->arch.smbase;
7687 cs.limit = ds.limit = 0xffffffff;
7688 cs.type = ds.type = 0x3;
7689 cs.dpl = ds.dpl = 0;
7694 cs.avl = ds.avl = 0;
7695 cs.present = ds.present = 1;
7696 cs.unusable = ds.unusable = 0;
7697 cs.padding = ds.padding = 0;
7699 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7700 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7701 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7702 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7703 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7704 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7706 #ifdef CONFIG_X86_64
7707 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7708 kvm_x86_ops->set_efer(vcpu, 0);
7711 kvm_update_cpuid(vcpu);
7712 kvm_mmu_reset_context(vcpu);
7715 static void process_smi(struct kvm_vcpu *vcpu)
7717 vcpu->arch.smi_pending = true;
7718 kvm_make_request(KVM_REQ_EVENT, vcpu);
7721 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7723 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7726 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7728 if (!kvm_apic_present(vcpu))
7731 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7733 if (irqchip_split(vcpu->kvm))
7734 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7736 if (vcpu->arch.apicv_active)
7737 kvm_x86_ops->sync_pir_to_irr(vcpu);
7738 if (ioapic_in_kernel(vcpu->kvm))
7739 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7742 if (is_guest_mode(vcpu))
7743 vcpu->arch.load_eoi_exitmap_pending = true;
7745 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7748 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7750 u64 eoi_exit_bitmap[4];
7752 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7755 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7756 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7757 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7760 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7761 unsigned long start, unsigned long end,
7764 unsigned long apic_address;
7767 * The physical address of apic access page is stored in the VMCS.
7768 * Update it when it becomes invalid.
7770 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7771 if (start <= apic_address && apic_address < end)
7772 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7777 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7779 struct page *page = NULL;
7781 if (!lapic_in_kernel(vcpu))
7784 if (!kvm_x86_ops->set_apic_access_page_addr)
7787 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7788 if (is_error_page(page))
7790 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7793 * Do not pin apic access page in memory, the MMU notifier
7794 * will call us again if it is migrated or swapped out.
7798 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7800 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7802 smp_send_reschedule(vcpu->cpu);
7804 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7807 * Returns 1 to let vcpu_run() continue the guest execution loop without
7808 * exiting to the userspace. Otherwise, the value will be returned to the
7811 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7815 dm_request_for_irq_injection(vcpu) &&
7816 kvm_cpu_accept_dm_intr(vcpu);
7818 bool req_immediate_exit = false;
7820 if (kvm_request_pending(vcpu)) {
7821 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7822 kvm_x86_ops->get_vmcs12_pages(vcpu);
7823 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7824 kvm_mmu_unload(vcpu);
7825 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7826 __kvm_migrate_timers(vcpu);
7827 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7828 kvm_gen_update_masterclock(vcpu->kvm);
7829 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7830 kvm_gen_kvmclock_update(vcpu);
7831 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7832 r = kvm_guest_time_update(vcpu);
7836 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7837 kvm_mmu_sync_roots(vcpu);
7838 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7839 kvm_mmu_load_cr3(vcpu);
7840 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7841 kvm_vcpu_flush_tlb(vcpu, true);
7842 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7843 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7847 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7848 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7849 vcpu->mmio_needed = 0;
7853 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7854 /* Page is swapped out. Do synthetic halt */
7855 vcpu->arch.apf.halted = true;
7859 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7860 record_steal_time(vcpu);
7861 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7863 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7865 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7866 kvm_pmu_handle_event(vcpu);
7867 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7868 kvm_pmu_deliver_pmi(vcpu);
7869 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7870 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7871 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7872 vcpu->arch.ioapic_handled_vectors)) {
7873 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7874 vcpu->run->eoi.vector =
7875 vcpu->arch.pending_ioapic_eoi;
7880 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7881 vcpu_scan_ioapic(vcpu);
7882 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7883 vcpu_load_eoi_exitmap(vcpu);
7884 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7885 kvm_vcpu_reload_apic_access_page(vcpu);
7886 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7887 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7888 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7892 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7893 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7894 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7898 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7899 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7900 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7906 * KVM_REQ_HV_STIMER has to be processed after
7907 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7908 * depend on the guest clock being up-to-date
7910 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7911 kvm_hv_process_stimers(vcpu);
7914 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7915 ++vcpu->stat.req_event;
7916 kvm_apic_accept_events(vcpu);
7917 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7922 if (inject_pending_event(vcpu, req_int_win) != 0)
7923 req_immediate_exit = true;
7925 /* Enable SMI/NMI/IRQ window open exits if needed.
7927 * SMIs have three cases:
7928 * 1) They can be nested, and then there is nothing to
7929 * do here because RSM will cause a vmexit anyway.
7930 * 2) There is an ISA-specific reason why SMI cannot be
7931 * injected, and the moment when this changes can be
7933 * 3) Or the SMI can be pending because
7934 * inject_pending_event has completed the injection
7935 * of an IRQ or NMI from the previous vmexit, and
7936 * then we request an immediate exit to inject the
7939 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7940 if (!kvm_x86_ops->enable_smi_window(vcpu))
7941 req_immediate_exit = true;
7942 if (vcpu->arch.nmi_pending)
7943 kvm_x86_ops->enable_nmi_window(vcpu);
7944 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7945 kvm_x86_ops->enable_irq_window(vcpu);
7946 WARN_ON(vcpu->arch.exception.pending);
7949 if (kvm_lapic_enabled(vcpu)) {
7950 update_cr8_intercept(vcpu);
7951 kvm_lapic_sync_to_vapic(vcpu);
7955 r = kvm_mmu_reload(vcpu);
7957 goto cancel_injection;
7962 kvm_x86_ops->prepare_guest_switch(vcpu);
7965 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7966 * IPI are then delayed after guest entry, which ensures that they
7967 * result in virtual interrupt delivery.
7969 local_irq_disable();
7970 vcpu->mode = IN_GUEST_MODE;
7972 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7975 * 1) We should set ->mode before checking ->requests. Please see
7976 * the comment in kvm_vcpu_exiting_guest_mode().
7978 * 2) For APICv, we should set ->mode before checking PID.ON. This
7979 * pairs with the memory barrier implicit in pi_test_and_set_on
7980 * (see vmx_deliver_posted_interrupt).
7982 * 3) This also orders the write to mode from any reads to the page
7983 * tables done while the VCPU is running. Please see the comment
7984 * in kvm_flush_remote_tlbs.
7986 smp_mb__after_srcu_read_unlock();
7989 * This handles the case where a posted interrupt was
7990 * notified with kvm_vcpu_kick.
7992 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7993 kvm_x86_ops->sync_pir_to_irr(vcpu);
7995 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7996 || need_resched() || signal_pending(current)) {
7997 vcpu->mode = OUTSIDE_GUEST_MODE;
8001 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8003 goto cancel_injection;
8006 if (req_immediate_exit) {
8007 kvm_make_request(KVM_REQ_EVENT, vcpu);
8008 kvm_x86_ops->request_immediate_exit(vcpu);
8011 trace_kvm_entry(vcpu->vcpu_id);
8012 guest_enter_irqoff();
8014 /* The preempt notifier should have taken care of the FPU already. */
8015 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8017 if (unlikely(vcpu->arch.switch_db_regs)) {
8019 set_debugreg(vcpu->arch.eff_db[0], 0);
8020 set_debugreg(vcpu->arch.eff_db[1], 1);
8021 set_debugreg(vcpu->arch.eff_db[2], 2);
8022 set_debugreg(vcpu->arch.eff_db[3], 3);
8023 set_debugreg(vcpu->arch.dr6, 6);
8024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8027 kvm_x86_ops->run(vcpu);
8030 * Do this here before restoring debug registers on the host. And
8031 * since we do this before handling the vmexit, a DR access vmexit
8032 * can (a) read the correct value of the debug registers, (b) set
8033 * KVM_DEBUGREG_WONT_EXIT again.
8035 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8036 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8037 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8038 kvm_update_dr0123(vcpu);
8039 kvm_update_dr6(vcpu);
8040 kvm_update_dr7(vcpu);
8041 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8045 * If the guest has used debug registers, at least dr7
8046 * will be disabled while returning to the host.
8047 * If we don't have active breakpoints in the host, we don't
8048 * care about the messed up debug address registers. But if
8049 * we have some of them active, restore the old state.
8051 if (hw_breakpoint_active())
8052 hw_breakpoint_restore();
8054 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8056 vcpu->mode = OUTSIDE_GUEST_MODE;
8059 kvm_x86_ops->handle_exit_irqoff(vcpu);
8062 * Consume any pending interrupts, including the possible source of
8063 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8064 * An instruction is required after local_irq_enable() to fully unblock
8065 * interrupts on processors that implement an interrupt shadow, the
8066 * stat.exits increment will do nicely.
8068 kvm_before_interrupt(vcpu);
8071 local_irq_disable();
8072 kvm_after_interrupt(vcpu);
8074 guest_exit_irqoff();
8075 if (lapic_in_kernel(vcpu)) {
8076 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8077 if (delta != S64_MIN) {
8078 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8079 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8086 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8089 * Profile KVM exit RIPs:
8091 if (unlikely(prof_on == KVM_PROFILING)) {
8092 unsigned long rip = kvm_rip_read(vcpu);
8093 profile_hit(KVM_PROFILING, (void *)rip);
8096 if (unlikely(vcpu->arch.tsc_always_catchup))
8097 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8099 if (vcpu->arch.apic_attention)
8100 kvm_lapic_sync_from_vapic(vcpu);
8102 vcpu->arch.gpa_available = false;
8103 r = kvm_x86_ops->handle_exit(vcpu);
8107 kvm_x86_ops->cancel_injection(vcpu);
8108 if (unlikely(vcpu->arch.apic_attention))
8109 kvm_lapic_sync_from_vapic(vcpu);
8114 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8116 if (!kvm_arch_vcpu_runnable(vcpu) &&
8117 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8118 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8119 kvm_vcpu_block(vcpu);
8120 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8122 if (kvm_x86_ops->post_block)
8123 kvm_x86_ops->post_block(vcpu);
8125 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8129 kvm_apic_accept_events(vcpu);
8130 switch(vcpu->arch.mp_state) {
8131 case KVM_MP_STATE_HALTED:
8132 vcpu->arch.pv.pv_unhalted = false;
8133 vcpu->arch.mp_state =
8134 KVM_MP_STATE_RUNNABLE;
8136 case KVM_MP_STATE_RUNNABLE:
8137 vcpu->arch.apf.halted = false;
8139 case KVM_MP_STATE_INIT_RECEIVED:
8148 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8150 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8151 kvm_x86_ops->check_nested_events(vcpu, false);
8153 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8154 !vcpu->arch.apf.halted);
8157 static int vcpu_run(struct kvm_vcpu *vcpu)
8160 struct kvm *kvm = vcpu->kvm;
8162 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8163 vcpu->arch.l1tf_flush_l1d = true;
8166 if (kvm_vcpu_running(vcpu)) {
8167 r = vcpu_enter_guest(vcpu);
8169 r = vcpu_block(kvm, vcpu);
8175 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8176 if (kvm_cpu_has_pending_timer(vcpu))
8177 kvm_inject_pending_timer_irqs(vcpu);
8179 if (dm_request_for_irq_injection(vcpu) &&
8180 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8182 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8183 ++vcpu->stat.request_irq_exits;
8187 kvm_check_async_pf_completion(vcpu);
8189 if (signal_pending(current)) {
8191 vcpu->run->exit_reason = KVM_EXIT_INTR;
8192 ++vcpu->stat.signal_exits;
8195 if (need_resched()) {
8196 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8198 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8202 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8207 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8210 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8211 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8212 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8213 if (r != EMULATE_DONE)
8218 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8220 BUG_ON(!vcpu->arch.pio.count);
8222 return complete_emulated_io(vcpu);
8226 * Implements the following, as a state machine:
8230 * for each mmio piece in the fragment
8238 * for each mmio piece in the fragment
8243 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8245 struct kvm_run *run = vcpu->run;
8246 struct kvm_mmio_fragment *frag;
8249 BUG_ON(!vcpu->mmio_needed);
8251 /* Complete previous fragment */
8252 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8253 len = min(8u, frag->len);
8254 if (!vcpu->mmio_is_write)
8255 memcpy(frag->data, run->mmio.data, len);
8257 if (frag->len <= 8) {
8258 /* Switch to the next fragment. */
8260 vcpu->mmio_cur_fragment++;
8262 /* Go forward to the next mmio piece. */
8268 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8269 vcpu->mmio_needed = 0;
8271 /* FIXME: return into emulator if single-stepping. */
8272 if (vcpu->mmio_is_write)
8274 vcpu->mmio_read_completed = 1;
8275 return complete_emulated_io(vcpu);
8278 run->exit_reason = KVM_EXIT_MMIO;
8279 run->mmio.phys_addr = frag->gpa;
8280 if (vcpu->mmio_is_write)
8281 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8282 run->mmio.len = min(8u, frag->len);
8283 run->mmio.is_write = vcpu->mmio_is_write;
8284 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8288 /* Swap (qemu) user FPU context for the guest FPU context. */
8289 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8293 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8294 /* PKRU is separately restored in kvm_x86_ops->run. */
8295 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8296 ~XFEATURE_MASK_PKRU);
8298 fpregs_mark_activate();
8304 /* When vcpu_run ends, restore user space FPU context. */
8305 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8309 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8310 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8312 fpregs_mark_activate();
8315 ++vcpu->stat.fpu_reload;
8319 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8324 kvm_sigset_activate(vcpu);
8325 kvm_load_guest_fpu(vcpu);
8327 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8328 if (kvm_run->immediate_exit) {
8332 kvm_vcpu_block(vcpu);
8333 kvm_apic_accept_events(vcpu);
8334 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8336 if (signal_pending(current)) {
8338 vcpu->run->exit_reason = KVM_EXIT_INTR;
8339 ++vcpu->stat.signal_exits;
8344 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8349 if (vcpu->run->kvm_dirty_regs) {
8350 r = sync_regs(vcpu);
8355 /* re-sync apic's tpr */
8356 if (!lapic_in_kernel(vcpu)) {
8357 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8363 if (unlikely(vcpu->arch.complete_userspace_io)) {
8364 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8365 vcpu->arch.complete_userspace_io = NULL;
8370 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8372 if (kvm_run->immediate_exit)
8378 kvm_put_guest_fpu(vcpu);
8379 if (vcpu->run->kvm_valid_regs)
8381 post_kvm_run_save(vcpu);
8382 kvm_sigset_deactivate(vcpu);
8388 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8390 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8392 * We are here if userspace calls get_regs() in the middle of
8393 * instruction emulation. Registers state needs to be copied
8394 * back from emulation context to vcpu. Userspace shouldn't do
8395 * that usually, but some bad designed PV devices (vmware
8396 * backdoor interface) need this to work
8398 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8399 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8401 regs->rax = kvm_rax_read(vcpu);
8402 regs->rbx = kvm_rbx_read(vcpu);
8403 regs->rcx = kvm_rcx_read(vcpu);
8404 regs->rdx = kvm_rdx_read(vcpu);
8405 regs->rsi = kvm_rsi_read(vcpu);
8406 regs->rdi = kvm_rdi_read(vcpu);
8407 regs->rsp = kvm_rsp_read(vcpu);
8408 regs->rbp = kvm_rbp_read(vcpu);
8409 #ifdef CONFIG_X86_64
8410 regs->r8 = kvm_r8_read(vcpu);
8411 regs->r9 = kvm_r9_read(vcpu);
8412 regs->r10 = kvm_r10_read(vcpu);
8413 regs->r11 = kvm_r11_read(vcpu);
8414 regs->r12 = kvm_r12_read(vcpu);
8415 regs->r13 = kvm_r13_read(vcpu);
8416 regs->r14 = kvm_r14_read(vcpu);
8417 regs->r15 = kvm_r15_read(vcpu);
8420 regs->rip = kvm_rip_read(vcpu);
8421 regs->rflags = kvm_get_rflags(vcpu);
8424 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8427 __get_regs(vcpu, regs);
8432 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8434 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8435 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8437 kvm_rax_write(vcpu, regs->rax);
8438 kvm_rbx_write(vcpu, regs->rbx);
8439 kvm_rcx_write(vcpu, regs->rcx);
8440 kvm_rdx_write(vcpu, regs->rdx);
8441 kvm_rsi_write(vcpu, regs->rsi);
8442 kvm_rdi_write(vcpu, regs->rdi);
8443 kvm_rsp_write(vcpu, regs->rsp);
8444 kvm_rbp_write(vcpu, regs->rbp);
8445 #ifdef CONFIG_X86_64
8446 kvm_r8_write(vcpu, regs->r8);
8447 kvm_r9_write(vcpu, regs->r9);
8448 kvm_r10_write(vcpu, regs->r10);
8449 kvm_r11_write(vcpu, regs->r11);
8450 kvm_r12_write(vcpu, regs->r12);
8451 kvm_r13_write(vcpu, regs->r13);
8452 kvm_r14_write(vcpu, regs->r14);
8453 kvm_r15_write(vcpu, regs->r15);
8456 kvm_rip_write(vcpu, regs->rip);
8457 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8459 vcpu->arch.exception.pending = false;
8461 kvm_make_request(KVM_REQ_EVENT, vcpu);
8464 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8467 __set_regs(vcpu, regs);
8472 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8474 struct kvm_segment cs;
8476 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8480 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8482 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8486 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8487 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8488 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8489 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8490 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8491 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8493 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8494 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8496 kvm_x86_ops->get_idt(vcpu, &dt);
8497 sregs->idt.limit = dt.size;
8498 sregs->idt.base = dt.address;
8499 kvm_x86_ops->get_gdt(vcpu, &dt);
8500 sregs->gdt.limit = dt.size;
8501 sregs->gdt.base = dt.address;
8503 sregs->cr0 = kvm_read_cr0(vcpu);
8504 sregs->cr2 = vcpu->arch.cr2;
8505 sregs->cr3 = kvm_read_cr3(vcpu);
8506 sregs->cr4 = kvm_read_cr4(vcpu);
8507 sregs->cr8 = kvm_get_cr8(vcpu);
8508 sregs->efer = vcpu->arch.efer;
8509 sregs->apic_base = kvm_get_apic_base(vcpu);
8511 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8513 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8514 set_bit(vcpu->arch.interrupt.nr,
8515 (unsigned long *)sregs->interrupt_bitmap);
8518 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8519 struct kvm_sregs *sregs)
8522 __get_sregs(vcpu, sregs);
8527 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8528 struct kvm_mp_state *mp_state)
8532 kvm_apic_accept_events(vcpu);
8533 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8534 vcpu->arch.pv.pv_unhalted)
8535 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8537 mp_state->mp_state = vcpu->arch.mp_state;
8543 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8544 struct kvm_mp_state *mp_state)
8550 if (!lapic_in_kernel(vcpu) &&
8551 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8554 /* INITs are latched while in SMM */
8555 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8556 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8557 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8560 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8561 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8562 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8564 vcpu->arch.mp_state = mp_state->mp_state;
8565 kvm_make_request(KVM_REQ_EVENT, vcpu);
8573 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8574 int reason, bool has_error_code, u32 error_code)
8576 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8579 init_emulate_ctxt(vcpu);
8581 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8582 has_error_code, error_code);
8585 return EMULATE_FAIL;
8587 kvm_rip_write(vcpu, ctxt->eip);
8588 kvm_set_rflags(vcpu, ctxt->eflags);
8589 kvm_make_request(KVM_REQ_EVENT, vcpu);
8590 return EMULATE_DONE;
8592 EXPORT_SYMBOL_GPL(kvm_task_switch);
8594 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8596 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8597 (sregs->cr4 & X86_CR4_OSXSAVE))
8600 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8602 * When EFER.LME and CR0.PG are set, the processor is in
8603 * 64-bit mode (though maybe in a 32-bit code segment).
8604 * CR4.PAE and EFER.LMA must be set.
8606 if (!(sregs->cr4 & X86_CR4_PAE)
8607 || !(sregs->efer & EFER_LMA))
8611 * Not in 64-bit mode: EFER.LMA is clear and the code
8612 * segment cannot be 64-bit.
8614 if (sregs->efer & EFER_LMA || sregs->cs.l)
8621 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8623 struct msr_data apic_base_msr;
8624 int mmu_reset_needed = 0;
8625 int cpuid_update_needed = 0;
8626 int pending_vec, max_bits, idx;
8630 if (kvm_valid_sregs(vcpu, sregs))
8633 apic_base_msr.data = sregs->apic_base;
8634 apic_base_msr.host_initiated = true;
8635 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8638 dt.size = sregs->idt.limit;
8639 dt.address = sregs->idt.base;
8640 kvm_x86_ops->set_idt(vcpu, &dt);
8641 dt.size = sregs->gdt.limit;
8642 dt.address = sregs->gdt.base;
8643 kvm_x86_ops->set_gdt(vcpu, &dt);
8645 vcpu->arch.cr2 = sregs->cr2;
8646 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8647 vcpu->arch.cr3 = sregs->cr3;
8648 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8650 kvm_set_cr8(vcpu, sregs->cr8);
8652 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8653 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8655 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8656 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8657 vcpu->arch.cr0 = sregs->cr0;
8659 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8660 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8661 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8662 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8663 if (cpuid_update_needed)
8664 kvm_update_cpuid(vcpu);
8666 idx = srcu_read_lock(&vcpu->kvm->srcu);
8667 if (is_pae_paging(vcpu)) {
8668 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8669 mmu_reset_needed = 1;
8671 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8673 if (mmu_reset_needed)
8674 kvm_mmu_reset_context(vcpu);
8676 max_bits = KVM_NR_INTERRUPTS;
8677 pending_vec = find_first_bit(
8678 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8679 if (pending_vec < max_bits) {
8680 kvm_queue_interrupt(vcpu, pending_vec, false);
8681 pr_debug("Set back pending irq %d\n", pending_vec);
8684 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8685 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8686 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8687 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8688 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8689 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8691 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8692 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8694 update_cr8_intercept(vcpu);
8696 /* Older userspace won't unhalt the vcpu on reset. */
8697 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8698 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8700 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8702 kvm_make_request(KVM_REQ_EVENT, vcpu);
8709 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8710 struct kvm_sregs *sregs)
8715 ret = __set_sregs(vcpu, sregs);
8720 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8721 struct kvm_guest_debug *dbg)
8723 unsigned long rflags;
8728 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8730 if (vcpu->arch.exception.pending)
8732 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8733 kvm_queue_exception(vcpu, DB_VECTOR);
8735 kvm_queue_exception(vcpu, BP_VECTOR);
8739 * Read rflags as long as potentially injected trace flags are still
8742 rflags = kvm_get_rflags(vcpu);
8744 vcpu->guest_debug = dbg->control;
8745 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8746 vcpu->guest_debug = 0;
8748 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8749 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8750 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8751 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8753 for (i = 0; i < KVM_NR_DB_REGS; i++)
8754 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8756 kvm_update_dr7(vcpu);
8758 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8759 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8760 get_segment_base(vcpu, VCPU_SREG_CS);
8763 * Trigger an rflags update that will inject or remove the trace
8766 kvm_set_rflags(vcpu, rflags);
8768 kvm_x86_ops->update_bp_intercept(vcpu);
8778 * Translate a guest virtual address to a guest physical address.
8780 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8781 struct kvm_translation *tr)
8783 unsigned long vaddr = tr->linear_address;
8789 idx = srcu_read_lock(&vcpu->kvm->srcu);
8790 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8791 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8792 tr->physical_address = gpa;
8793 tr->valid = gpa != UNMAPPED_GVA;
8801 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8803 struct fxregs_state *fxsave;
8807 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8808 memcpy(fpu->fpr, fxsave->st_space, 128);
8809 fpu->fcw = fxsave->cwd;
8810 fpu->fsw = fxsave->swd;
8811 fpu->ftwx = fxsave->twd;
8812 fpu->last_opcode = fxsave->fop;
8813 fpu->last_ip = fxsave->rip;
8814 fpu->last_dp = fxsave->rdp;
8815 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8821 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8823 struct fxregs_state *fxsave;
8827 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8829 memcpy(fxsave->st_space, fpu->fpr, 128);
8830 fxsave->cwd = fpu->fcw;
8831 fxsave->swd = fpu->fsw;
8832 fxsave->twd = fpu->ftwx;
8833 fxsave->fop = fpu->last_opcode;
8834 fxsave->rip = fpu->last_ip;
8835 fxsave->rdp = fpu->last_dp;
8836 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8842 static void store_regs(struct kvm_vcpu *vcpu)
8844 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8846 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8847 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8849 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8850 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8852 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8853 kvm_vcpu_ioctl_x86_get_vcpu_events(
8854 vcpu, &vcpu->run->s.regs.events);
8857 static int sync_regs(struct kvm_vcpu *vcpu)
8859 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8862 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8863 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8864 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8866 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8867 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8869 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8871 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8872 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8873 vcpu, &vcpu->run->s.regs.events))
8875 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8881 static void fx_init(struct kvm_vcpu *vcpu)
8883 fpstate_init(&vcpu->arch.guest_fpu->state);
8884 if (boot_cpu_has(X86_FEATURE_XSAVES))
8885 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8886 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8889 * Ensure guest xcr0 is valid for loading
8891 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8893 vcpu->arch.cr0 |= X86_CR0_ET;
8896 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8898 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8900 kvmclock_reset(vcpu);
8902 kvm_x86_ops->vcpu_free(vcpu);
8903 free_cpumask_var(wbinvd_dirty_mask);
8906 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8909 struct kvm_vcpu *vcpu;
8911 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8912 printk_once(KERN_WARNING
8913 "kvm: SMP vm created on host with unstable TSC; "
8914 "guest TSC will not be reliable\n");
8916 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8921 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8923 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8924 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8925 kvm_vcpu_mtrr_init(vcpu);
8927 kvm_vcpu_reset(vcpu, false);
8928 kvm_init_mmu(vcpu, false);
8933 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8935 struct msr_data msr;
8936 struct kvm *kvm = vcpu->kvm;
8938 kvm_hv_vcpu_postcreate(vcpu);
8940 if (mutex_lock_killable(&vcpu->mutex))
8944 msr.index = MSR_IA32_TSC;
8945 msr.host_initiated = true;
8946 kvm_write_tsc(vcpu, &msr);
8949 /* poll control enabled by default */
8950 vcpu->arch.msr_kvm_poll_control = 1;
8952 mutex_unlock(&vcpu->mutex);
8954 if (!kvmclock_periodic_sync)
8957 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8958 KVMCLOCK_SYNC_PERIOD);
8961 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8963 vcpu->arch.apf.msr_val = 0;
8966 kvm_mmu_unload(vcpu);
8969 kvm_x86_ops->vcpu_free(vcpu);
8972 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8974 kvm_lapic_reset(vcpu, init_event);
8976 vcpu->arch.hflags = 0;
8978 vcpu->arch.smi_pending = 0;
8979 vcpu->arch.smi_count = 0;
8980 atomic_set(&vcpu->arch.nmi_queued, 0);
8981 vcpu->arch.nmi_pending = 0;
8982 vcpu->arch.nmi_injected = false;
8983 kvm_clear_interrupt_queue(vcpu);
8984 kvm_clear_exception_queue(vcpu);
8985 vcpu->arch.exception.pending = false;
8987 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8988 kvm_update_dr0123(vcpu);
8989 vcpu->arch.dr6 = DR6_INIT;
8990 kvm_update_dr6(vcpu);
8991 vcpu->arch.dr7 = DR7_FIXED_1;
8992 kvm_update_dr7(vcpu);
8996 kvm_make_request(KVM_REQ_EVENT, vcpu);
8997 vcpu->arch.apf.msr_val = 0;
8998 vcpu->arch.st.msr_val = 0;
9000 kvmclock_reset(vcpu);
9002 kvm_clear_async_pf_completion_queue(vcpu);
9003 kvm_async_pf_hash_reset(vcpu);
9004 vcpu->arch.apf.halted = false;
9006 if (kvm_mpx_supported()) {
9007 void *mpx_state_buffer;
9010 * To avoid have the INIT path from kvm_apic_has_events() that be
9011 * called with loaded FPU and does not let userspace fix the state.
9014 kvm_put_guest_fpu(vcpu);
9015 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9017 if (mpx_state_buffer)
9018 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9019 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9021 if (mpx_state_buffer)
9022 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9024 kvm_load_guest_fpu(vcpu);
9028 kvm_pmu_reset(vcpu);
9029 vcpu->arch.smbase = 0x30000;
9031 vcpu->arch.msr_misc_features_enables = 0;
9033 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9036 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9037 vcpu->arch.regs_avail = ~0;
9038 vcpu->arch.regs_dirty = ~0;
9040 vcpu->arch.ia32_xss = 0;
9042 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9045 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9047 struct kvm_segment cs;
9049 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9050 cs.selector = vector << 8;
9051 cs.base = vector << 12;
9052 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9053 kvm_rip_write(vcpu, 0);
9056 int kvm_arch_hardware_enable(void)
9059 struct kvm_vcpu *vcpu;
9064 bool stable, backwards_tsc = false;
9066 kvm_shared_msr_cpu_online();
9067 ret = kvm_x86_ops->hardware_enable();
9071 local_tsc = rdtsc();
9072 stable = !kvm_check_tsc_unstable();
9073 list_for_each_entry(kvm, &vm_list, vm_list) {
9074 kvm_for_each_vcpu(i, vcpu, kvm) {
9075 if (!stable && vcpu->cpu == smp_processor_id())
9076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9077 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9078 backwards_tsc = true;
9079 if (vcpu->arch.last_host_tsc > max_tsc)
9080 max_tsc = vcpu->arch.last_host_tsc;
9086 * Sometimes, even reliable TSCs go backwards. This happens on
9087 * platforms that reset TSC during suspend or hibernate actions, but
9088 * maintain synchronization. We must compensate. Fortunately, we can
9089 * detect that condition here, which happens early in CPU bringup,
9090 * before any KVM threads can be running. Unfortunately, we can't
9091 * bring the TSCs fully up to date with real time, as we aren't yet far
9092 * enough into CPU bringup that we know how much real time has actually
9093 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9094 * variables that haven't been updated yet.
9096 * So we simply find the maximum observed TSC above, then record the
9097 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9098 * the adjustment will be applied. Note that we accumulate
9099 * adjustments, in case multiple suspend cycles happen before some VCPU
9100 * gets a chance to run again. In the event that no KVM threads get a
9101 * chance to run, we will miss the entire elapsed period, as we'll have
9102 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9103 * loose cycle time. This isn't too big a deal, since the loss will be
9104 * uniform across all VCPUs (not to mention the scenario is extremely
9105 * unlikely). It is possible that a second hibernate recovery happens
9106 * much faster than a first, causing the observed TSC here to be
9107 * smaller; this would require additional padding adjustment, which is
9108 * why we set last_host_tsc to the local tsc observed here.
9110 * N.B. - this code below runs only on platforms with reliable TSC,
9111 * as that is the only way backwards_tsc is set above. Also note
9112 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9113 * have the same delta_cyc adjustment applied if backwards_tsc
9114 * is detected. Note further, this adjustment is only done once,
9115 * as we reset last_host_tsc on all VCPUs to stop this from being
9116 * called multiple times (one for each physical CPU bringup).
9118 * Platforms with unreliable TSCs don't have to deal with this, they
9119 * will be compensated by the logic in vcpu_load, which sets the TSC to
9120 * catchup mode. This will catchup all VCPUs to real time, but cannot
9121 * guarantee that they stay in perfect synchronization.
9123 if (backwards_tsc) {
9124 u64 delta_cyc = max_tsc - local_tsc;
9125 list_for_each_entry(kvm, &vm_list, vm_list) {
9126 kvm->arch.backwards_tsc_observed = true;
9127 kvm_for_each_vcpu(i, vcpu, kvm) {
9128 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9129 vcpu->arch.last_host_tsc = local_tsc;
9130 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9134 * We have to disable TSC offset matching.. if you were
9135 * booting a VM while issuing an S4 host suspend....
9136 * you may have some problem. Solving this issue is
9137 * left as an exercise to the reader.
9139 kvm->arch.last_tsc_nsec = 0;
9140 kvm->arch.last_tsc_write = 0;
9147 void kvm_arch_hardware_disable(void)
9149 kvm_x86_ops->hardware_disable();
9150 drop_user_return_notifiers();
9153 int kvm_arch_hardware_setup(void)
9157 r = kvm_x86_ops->hardware_setup();
9161 if (kvm_has_tsc_control) {
9163 * Make sure the user can only configure tsc_khz values that
9164 * fit into a signed integer.
9165 * A min value is not calculated because it will always
9166 * be 1 on all machines.
9168 u64 max = min(0x7fffffffULL,
9169 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9170 kvm_max_guest_tsc_khz = max;
9172 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9175 kvm_init_msr_list();
9179 void kvm_arch_hardware_unsetup(void)
9181 kvm_x86_ops->hardware_unsetup();
9184 int kvm_arch_check_processor_compat(void)
9186 return kvm_x86_ops->check_processor_compatibility();
9189 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9191 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9193 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9195 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9197 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9200 struct static_key kvm_no_apic_vcpu __read_mostly;
9201 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9203 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9208 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9209 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9210 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9212 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9214 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9219 vcpu->arch.pio_data = page_address(page);
9221 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9223 r = kvm_mmu_create(vcpu);
9225 goto fail_free_pio_data;
9227 if (irqchip_in_kernel(vcpu->kvm)) {
9228 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9229 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9231 goto fail_mmu_destroy;
9233 static_key_slow_inc(&kvm_no_apic_vcpu);
9235 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9236 GFP_KERNEL_ACCOUNT);
9237 if (!vcpu->arch.mce_banks) {
9239 goto fail_free_lapic;
9241 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9243 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9244 GFP_KERNEL_ACCOUNT)) {
9246 goto fail_free_mce_banks;
9251 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9253 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9255 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9257 kvm_async_pf_hash_reset(vcpu);
9260 vcpu->arch.pending_external_vector = -1;
9261 vcpu->arch.preempted_in_kernel = false;
9263 kvm_hv_vcpu_init(vcpu);
9267 fail_free_mce_banks:
9268 kfree(vcpu->arch.mce_banks);
9270 kvm_free_lapic(vcpu);
9272 kvm_mmu_destroy(vcpu);
9274 free_page((unsigned long)vcpu->arch.pio_data);
9279 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9283 kvm_hv_vcpu_uninit(vcpu);
9284 kvm_pmu_destroy(vcpu);
9285 kfree(vcpu->arch.mce_banks);
9286 kvm_free_lapic(vcpu);
9287 idx = srcu_read_lock(&vcpu->kvm->srcu);
9288 kvm_mmu_destroy(vcpu);
9289 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9290 free_page((unsigned long)vcpu->arch.pio_data);
9291 if (!lapic_in_kernel(vcpu))
9292 static_key_slow_dec(&kvm_no_apic_vcpu);
9295 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9297 vcpu->arch.l1tf_flush_l1d = true;
9298 kvm_x86_ops->sched_in(vcpu, cpu);
9301 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9306 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9307 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9308 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9309 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9311 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9312 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9313 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9314 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9315 &kvm->arch.irq_sources_bitmap);
9317 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9318 mutex_init(&kvm->arch.apic_map_lock);
9319 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9321 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9322 pvclock_update_vm_gtod_copy(kvm);
9324 kvm->arch.guest_can_read_msr_platform_info = true;
9326 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9327 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9329 kvm_hv_init_vm(kvm);
9330 kvm_page_track_init(kvm);
9331 kvm_mmu_init_vm(kvm);
9333 if (kvm_x86_ops->vm_init)
9334 return kvm_x86_ops->vm_init(kvm);
9339 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9342 kvm_mmu_unload(vcpu);
9346 static void kvm_free_vcpus(struct kvm *kvm)
9349 struct kvm_vcpu *vcpu;
9352 * Unpin any mmu pages first.
9354 kvm_for_each_vcpu(i, vcpu, kvm) {
9355 kvm_clear_async_pf_completion_queue(vcpu);
9356 kvm_unload_vcpu_mmu(vcpu);
9358 kvm_for_each_vcpu(i, vcpu, kvm)
9359 kvm_arch_vcpu_free(vcpu);
9361 mutex_lock(&kvm->lock);
9362 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9363 kvm->vcpus[i] = NULL;
9365 atomic_set(&kvm->online_vcpus, 0);
9366 mutex_unlock(&kvm->lock);
9369 void kvm_arch_sync_events(struct kvm *kvm)
9371 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9372 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9376 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9380 struct kvm_memslots *slots = kvm_memslots(kvm);
9381 struct kvm_memory_slot *slot, old;
9383 /* Called with kvm->slots_lock held. */
9384 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9387 slot = id_to_memslot(slots, id);
9393 * MAP_SHARED to prevent internal slot pages from being moved
9396 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9397 MAP_SHARED | MAP_ANONYMOUS, 0);
9398 if (IS_ERR((void *)hva))
9399 return PTR_ERR((void *)hva);
9408 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9409 struct kvm_userspace_memory_region m;
9411 m.slot = id | (i << 16);
9413 m.guest_phys_addr = gpa;
9414 m.userspace_addr = hva;
9415 m.memory_size = size;
9416 r = __kvm_set_memory_region(kvm, &m);
9422 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9426 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9428 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9432 mutex_lock(&kvm->slots_lock);
9433 r = __x86_set_memory_region(kvm, id, gpa, size);
9434 mutex_unlock(&kvm->slots_lock);
9438 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9440 void kvm_arch_destroy_vm(struct kvm *kvm)
9442 if (current->mm == kvm->mm) {
9444 * Free memory regions allocated on behalf of userspace,
9445 * unless the the memory map has changed due to process exit
9448 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9449 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9450 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9452 if (kvm_x86_ops->vm_destroy)
9453 kvm_x86_ops->vm_destroy(kvm);
9454 kvm_pic_destroy(kvm);
9455 kvm_ioapic_destroy(kvm);
9456 kvm_free_vcpus(kvm);
9457 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9458 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9459 kvm_mmu_uninit_vm(kvm);
9460 kvm_page_track_cleanup(kvm);
9461 kvm_hv_destroy_vm(kvm);
9464 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9465 struct kvm_memory_slot *dont)
9469 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9470 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9471 kvfree(free->arch.rmap[i]);
9472 free->arch.rmap[i] = NULL;
9477 if (!dont || free->arch.lpage_info[i - 1] !=
9478 dont->arch.lpage_info[i - 1]) {
9479 kvfree(free->arch.lpage_info[i - 1]);
9480 free->arch.lpage_info[i - 1] = NULL;
9484 kvm_page_track_free_memslot(free, dont);
9487 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9488 unsigned long npages)
9492 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9493 struct kvm_lpage_info *linfo;
9498 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9499 slot->base_gfn, level) + 1;
9501 slot->arch.rmap[i] =
9502 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9503 GFP_KERNEL_ACCOUNT);
9504 if (!slot->arch.rmap[i])
9509 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9513 slot->arch.lpage_info[i - 1] = linfo;
9515 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9516 linfo[0].disallow_lpage = 1;
9517 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9518 linfo[lpages - 1].disallow_lpage = 1;
9519 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9521 * If the gfn and userspace address are not aligned wrt each
9522 * other, or if explicitly asked to, disable large page
9523 * support for this slot
9525 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9526 !kvm_largepages_enabled()) {
9529 for (j = 0; j < lpages; ++j)
9530 linfo[j].disallow_lpage = 1;
9534 if (kvm_page_track_create_memslot(slot, npages))
9540 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9541 kvfree(slot->arch.rmap[i]);
9542 slot->arch.rmap[i] = NULL;
9546 kvfree(slot->arch.lpage_info[i - 1]);
9547 slot->arch.lpage_info[i - 1] = NULL;
9552 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9555 * memslots->generation has been incremented.
9556 * mmio generation may have reached its maximum value.
9558 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9561 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9562 struct kvm_memory_slot *memslot,
9563 const struct kvm_userspace_memory_region *mem,
9564 enum kvm_mr_change change)
9569 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9570 struct kvm_memory_slot *new)
9572 /* Still write protect RO slot */
9573 if (new->flags & KVM_MEM_READONLY) {
9574 kvm_mmu_slot_remove_write_access(kvm, new);
9579 * Call kvm_x86_ops dirty logging hooks when they are valid.
9581 * kvm_x86_ops->slot_disable_log_dirty is called when:
9583 * - KVM_MR_CREATE with dirty logging is disabled
9584 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9586 * The reason is, in case of PML, we need to set D-bit for any slots
9587 * with dirty logging disabled in order to eliminate unnecessary GPA
9588 * logging in PML buffer (and potential PML buffer full VMEXT). This
9589 * guarantees leaving PML enabled during guest's lifetime won't have
9590 * any additional overhead from PML when guest is running with dirty
9591 * logging disabled for memory slots.
9593 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9594 * to dirty logging mode.
9596 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9598 * In case of write protect:
9600 * Write protect all pages for dirty logging.
9602 * All the sptes including the large sptes which point to this
9603 * slot are set to readonly. We can not create any new large
9604 * spte on this slot until the end of the logging.
9606 * See the comments in fast_page_fault().
9608 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9609 if (kvm_x86_ops->slot_enable_log_dirty)
9610 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9612 kvm_mmu_slot_remove_write_access(kvm, new);
9614 if (kvm_x86_ops->slot_disable_log_dirty)
9615 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9619 void kvm_arch_commit_memory_region(struct kvm *kvm,
9620 const struct kvm_userspace_memory_region *mem,
9621 const struct kvm_memory_slot *old,
9622 const struct kvm_memory_slot *new,
9623 enum kvm_mr_change change)
9625 if (!kvm->arch.n_requested_mmu_pages)
9626 kvm_mmu_change_mmu_pages(kvm,
9627 kvm_mmu_calculate_default_mmu_pages(kvm));
9630 * Dirty logging tracks sptes in 4k granularity, meaning that large
9631 * sptes have to be split. If live migration is successful, the guest
9632 * in the source machine will be destroyed and large sptes will be
9633 * created in the destination. However, if the guest continues to run
9634 * in the source machine (for example if live migration fails), small
9635 * sptes will remain around and cause bad performance.
9637 * Scan sptes if dirty logging has been stopped, dropping those
9638 * which can be collapsed into a single large-page spte. Later
9639 * page faults will create the large-page sptes.
9641 if ((change != KVM_MR_DELETE) &&
9642 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9643 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9644 kvm_mmu_zap_collapsible_sptes(kvm, new);
9647 * Set up write protection and/or dirty logging for the new slot.
9649 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9650 * been zapped so no dirty logging staff is needed for old slot. For
9651 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9652 * new and it's also covered when dealing with the new slot.
9654 * FIXME: const-ify all uses of struct kvm_memory_slot.
9656 if (change != KVM_MR_DELETE)
9657 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9660 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9662 kvm_mmu_zap_all(kvm);
9665 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9666 struct kvm_memory_slot *slot)
9668 kvm_page_track_flush_slot(kvm, slot);
9671 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9673 return (is_guest_mode(vcpu) &&
9674 kvm_x86_ops->guest_apic_has_interrupt &&
9675 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9678 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9680 if (!list_empty_careful(&vcpu->async_pf.done))
9683 if (kvm_apic_has_events(vcpu))
9686 if (vcpu->arch.pv.pv_unhalted)
9689 if (vcpu->arch.exception.pending)
9692 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9693 (vcpu->arch.nmi_pending &&
9694 kvm_x86_ops->nmi_allowed(vcpu)))
9697 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9698 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9701 if (kvm_arch_interrupt_allowed(vcpu) &&
9702 (kvm_cpu_has_interrupt(vcpu) ||
9703 kvm_guest_apic_has_interrupt(vcpu)))
9706 if (kvm_hv_has_stimer_pending(vcpu))
9712 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9714 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9717 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9719 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9722 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9723 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9724 kvm_test_request(KVM_REQ_EVENT, vcpu))
9727 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9733 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9735 return vcpu->arch.preempted_in_kernel;
9738 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9740 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9743 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9745 return kvm_x86_ops->interrupt_allowed(vcpu);
9748 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9750 if (is_64_bit_mode(vcpu))
9751 return kvm_rip_read(vcpu);
9752 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9753 kvm_rip_read(vcpu));
9755 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9757 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9759 return kvm_get_linear_rip(vcpu) == linear_rip;
9761 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9763 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9765 unsigned long rflags;
9767 rflags = kvm_x86_ops->get_rflags(vcpu);
9768 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9769 rflags &= ~X86_EFLAGS_TF;
9772 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9774 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9776 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9777 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9778 rflags |= X86_EFLAGS_TF;
9779 kvm_x86_ops->set_rflags(vcpu, rflags);
9782 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9784 __kvm_set_rflags(vcpu, rflags);
9785 kvm_make_request(KVM_REQ_EVENT, vcpu);
9787 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9789 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9793 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9797 r = kvm_mmu_reload(vcpu);
9801 if (!vcpu->arch.mmu->direct_map &&
9802 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9805 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9808 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9810 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9813 static inline u32 kvm_async_pf_next_probe(u32 key)
9815 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9818 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9820 u32 key = kvm_async_pf_hash_fn(gfn);
9822 while (vcpu->arch.apf.gfns[key] != ~0)
9823 key = kvm_async_pf_next_probe(key);
9825 vcpu->arch.apf.gfns[key] = gfn;
9828 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9831 u32 key = kvm_async_pf_hash_fn(gfn);
9833 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9834 (vcpu->arch.apf.gfns[key] != gfn &&
9835 vcpu->arch.apf.gfns[key] != ~0); i++)
9836 key = kvm_async_pf_next_probe(key);
9841 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9843 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9846 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9850 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9852 vcpu->arch.apf.gfns[i] = ~0;
9854 j = kvm_async_pf_next_probe(j);
9855 if (vcpu->arch.apf.gfns[j] == ~0)
9857 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9859 * k lies cyclically in ]i,j]
9861 * |....j i.k.| or |.k..j i...|
9863 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9864 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9869 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9872 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9876 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9879 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9883 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9885 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9888 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9889 (vcpu->arch.apf.send_user_only &&
9890 kvm_x86_ops->get_cpl(vcpu) == 0))
9896 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9898 if (unlikely(!lapic_in_kernel(vcpu) ||
9899 kvm_event_needs_reinjection(vcpu) ||
9900 vcpu->arch.exception.pending))
9903 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9907 * If interrupts are off we cannot even use an artificial
9910 return kvm_x86_ops->interrupt_allowed(vcpu);
9913 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9914 struct kvm_async_pf *work)
9916 struct x86_exception fault;
9918 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9919 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9921 if (kvm_can_deliver_async_pf(vcpu) &&
9922 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9923 fault.vector = PF_VECTOR;
9924 fault.error_code_valid = true;
9925 fault.error_code = 0;
9926 fault.nested_page_fault = false;
9927 fault.address = work->arch.token;
9928 fault.async_page_fault = true;
9929 kvm_inject_page_fault(vcpu, &fault);
9932 * It is not possible to deliver a paravirtualized asynchronous
9933 * page fault, but putting the guest in an artificial halt state
9934 * can be beneficial nevertheless: if an interrupt arrives, we
9935 * can deliver it timely and perhaps the guest will schedule
9936 * another process. When the instruction that triggered a page
9937 * fault is retried, hopefully the page will be ready in the host.
9939 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9943 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9944 struct kvm_async_pf *work)
9946 struct x86_exception fault;
9949 if (work->wakeup_all)
9950 work->arch.token = ~0; /* broadcast wakeup */
9952 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9953 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9955 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9956 !apf_get_user(vcpu, &val)) {
9957 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9958 vcpu->arch.exception.pending &&
9959 vcpu->arch.exception.nr == PF_VECTOR &&
9960 !apf_put_user(vcpu, 0)) {
9961 vcpu->arch.exception.injected = false;
9962 vcpu->arch.exception.pending = false;
9963 vcpu->arch.exception.nr = 0;
9964 vcpu->arch.exception.has_error_code = false;
9965 vcpu->arch.exception.error_code = 0;
9966 vcpu->arch.exception.has_payload = false;
9967 vcpu->arch.exception.payload = 0;
9968 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9969 fault.vector = PF_VECTOR;
9970 fault.error_code_valid = true;
9971 fault.error_code = 0;
9972 fault.nested_page_fault = false;
9973 fault.address = work->arch.token;
9974 fault.async_page_fault = true;
9975 kvm_inject_page_fault(vcpu, &fault);
9978 vcpu->arch.apf.halted = false;
9979 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9982 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9984 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9987 return kvm_can_do_async_pf(vcpu);
9990 void kvm_arch_start_assignment(struct kvm *kvm)
9992 atomic_inc(&kvm->arch.assigned_device_count);
9994 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9996 void kvm_arch_end_assignment(struct kvm *kvm)
9998 atomic_dec(&kvm->arch.assigned_device_count);
10000 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10002 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10004 return atomic_read(&kvm->arch.assigned_device_count);
10006 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10008 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10010 atomic_inc(&kvm->arch.noncoherent_dma_count);
10012 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10014 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10016 atomic_dec(&kvm->arch.noncoherent_dma_count);
10018 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10020 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10022 return atomic_read(&kvm->arch.noncoherent_dma_count);
10024 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10026 bool kvm_arch_has_irq_bypass(void)
10028 return kvm_x86_ops->update_pi_irte != NULL;
10031 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10032 struct irq_bypass_producer *prod)
10034 struct kvm_kernel_irqfd *irqfd =
10035 container_of(cons, struct kvm_kernel_irqfd, consumer);
10037 irqfd->producer = prod;
10039 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10040 prod->irq, irqfd->gsi, 1);
10043 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10044 struct irq_bypass_producer *prod)
10047 struct kvm_kernel_irqfd *irqfd =
10048 container_of(cons, struct kvm_kernel_irqfd, consumer);
10050 WARN_ON(irqfd->producer != prod);
10051 irqfd->producer = NULL;
10054 * When producer of consumer is unregistered, we change back to
10055 * remapped mode, so we can re-use the current implementation
10056 * when the irq is masked/disabled or the consumer side (KVM
10057 * int this case doesn't want to receive the interrupts.
10059 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10061 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10062 " fails: %d\n", irqfd->consumer.token, ret);
10065 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10066 uint32_t guest_irq, bool set)
10068 if (!kvm_x86_ops->update_pi_irte)
10071 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10074 bool kvm_vector_hashing_enabled(void)
10076 return vector_hashing;
10078 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10080 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10082 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10084 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10087 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10088 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10089 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10090 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10091 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10092 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10093 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10094 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10095 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10096 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10097 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10098 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10099 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10100 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10101 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
10102 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10103 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10104 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10105 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);