2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
71 #define CREATE_TRACE_POINTS
74 #define MAX_IO_MSRS 256
75 #define KVM_MAX_MCE_BANKS 32
76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
79 #define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
99 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
100 static void process_nmi(struct kvm_vcpu *vcpu);
101 static void enter_smm(struct kvm_vcpu *vcpu);
102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
104 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
105 EXPORT_SYMBOL_GPL(kvm_x86_ops);
107 static bool __read_mostly ignore_msrs = 0;
108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
110 static bool __read_mostly report_ignored_msrs = true;
111 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
113 unsigned int min_timer_period_us = 500;
114 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
116 static bool __read_mostly kvmclock_periodic_sync = true;
117 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
119 bool __read_mostly kvm_has_tsc_control;
120 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
121 u32 __read_mostly kvm_max_guest_tsc_khz;
122 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
123 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125 u64 __read_mostly kvm_max_tsc_scaling_ratio;
126 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
127 u64 __read_mostly kvm_default_tsc_scaling_ratio;
128 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
130 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
131 static u32 __read_mostly tsc_tolerance_ppm = 250;
132 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
134 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
135 unsigned int __read_mostly lapic_timer_advance_ns = 0;
136 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
138 static bool __read_mostly vector_hashing = true;
139 module_param(vector_hashing, bool, S_IRUGO);
141 #define KVM_NR_SHARED_MSRS 16
143 struct kvm_shared_msrs_global {
145 u32 msrs[KVM_NR_SHARED_MSRS];
148 struct kvm_shared_msrs {
149 struct user_return_notifier urn;
151 struct kvm_shared_msr_values {
154 } values[KVM_NR_SHARED_MSRS];
157 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
158 static struct kvm_shared_msrs __percpu *shared_msrs;
160 struct kvm_stats_debugfs_item debugfs_entries[] = {
161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
171 { "halt_exits", VCPU_STAT(halt_exits) },
172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
176 { "hypercalls", VCPU_STAT(hypercalls) },
177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
184 { "irq_injections", VCPU_STAT(irq_injections) },
185 { "nmi_injections", VCPU_STAT(nmi_injections) },
186 { "req_event", VCPU_STAT(req_event) },
187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
194 { "mmu_unsync", VM_STAT(mmu_unsync) },
195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
196 { "largepages", VM_STAT(lpages) },
197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
202 u64 __read_mostly host_xcr0;
204 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
206 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
213 static void kvm_on_user_return(struct user_return_notifier *urn)
216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
218 struct kvm_shared_msr_values *values;
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
230 local_irq_restore(flags);
231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
240 static void shared_msr_update(unsigned slot, u32 msr)
243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
257 void kvm_define_shared_msr(unsigned slot, u32 msr)
259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
260 shared_msrs_global.msrs[slot] = msr;
261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
264 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266 static void kvm_shared_msr_cpu_online(void)
270 for (i = 0; i < shared_msrs_global.nr; ++i)
271 shared_msr_update(i, shared_msrs_global.msrs[i]);
274 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
282 smsr->values[slot].curr = value;
283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
294 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296 static void drop_user_return_notifiers(void)
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
305 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307 return vcpu->arch.apic_base;
309 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 if (!msr_info->host_initiated &&
323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
329 kvm_lapic_set_base(vcpu, msr_info->data);
332 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334 asmlinkage __visible void kvm_spurious_fault(void)
336 /* Fault while not rebooting. We want the trace. */
339 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341 #define EXCPT_BENIGN 0
342 #define EXCPT_CONTRIBUTORY 1
345 static int exception_class(int vector)
355 return EXCPT_CONTRIBUTORY;
362 #define EXCPT_FAULT 0
364 #define EXCPT_ABORT 2
365 #define EXCPT_INTERRUPT 3
367 static int exception_type(int vector)
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
383 /* Reserved exceptions will result in fault */
387 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
388 unsigned nr, bool has_error, u32 error_code,
394 kvm_make_request(KVM_REQ_EVENT, vcpu);
396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
398 if (has_error && !is_protmode(vcpu))
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
437 vcpu->arch.exception.pending = true;
438 vcpu->arch.exception.injected = false;
439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
449 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451 kvm_multiple_exception(vcpu, nr, false, 0, false);
453 EXPORT_SYMBOL_GPL(kvm_queue_exception);
455 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
459 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
464 kvm_inject_gp(vcpu, 0);
466 return kvm_skip_emulated_instruction(vcpu);
470 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
472 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
474 ++vcpu->stat.pf_guest;
475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
480 vcpu->arch.cr2 = fault->address;
481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
483 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
485 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
492 return fault->nested_page_fault;
495 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
500 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
506 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
518 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
525 EXPORT_SYMBOL_GPL(kvm_require_cpl);
527 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
532 kvm_queue_exception(vcpu, UD_VECTOR);
535 EXPORT_SYMBOL_GPL(kvm_require_dr);
538 * This function will be used to read from the physical memory of the currently
539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
540 * can read from guest physical or from the guest's guest physical memory.
542 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
546 struct x86_exception exception;
550 ngpa = gfn_to_gpa(ngfn);
551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
552 if (real_gfn == UNMAPPED_GVA)
555 real_gfn = gpa_to_gfn(real_gfn);
557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
559 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
562 void *data, int offset, int len, u32 access)
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
569 * Load the pae pdptrs. Return true is they are all valid.
571 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
587 if ((pdpte[i] & PT_PRESENT_MASK) &&
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
605 EXPORT_SYMBOL_GPL(load_pdptrs);
607 bool pdptrs_changed(struct kvm_vcpu *vcpu)
609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
633 EXPORT_SYMBOL_GPL(pdptrs_changed);
635 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
643 if (cr0 & 0xffffffff00000000UL)
647 cr0 &= ~CR0_RESERVED_BITS;
649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657 if ((vcpu->arch.efer & EFER_LME)) {
662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
675 kvm_x86_ops->set_cr0(vcpu, cr0);
677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
678 kvm_clear_async_pf_completion_queue(vcpu);
679 kvm_async_pf_hash_reset(vcpu);
682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
692 EXPORT_SYMBOL_GPL(kvm_set_cr0);
694 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
698 EXPORT_SYMBOL_GPL(kvm_lmsw);
700 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
710 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
719 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
722 u64 old_xcr0 = vcpu->arch.xcr0;
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
728 if (!(xcr0 & XFEATURE_MASK_FP))
730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
739 if (xcr0 & ~valid_bits)
742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
752 vcpu->arch.xcr0 = xcr0;
754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
755 kvm_update_cpuid(vcpu);
759 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
763 kvm_inject_gp(vcpu, 0);
768 EXPORT_SYMBOL_GPL(kvm_set_xcr);
770 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
776 if (cr4 & CR4_RESERVED_BITS)
779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
797 if (is_long_mode(vcpu)) {
798 if (!(cr4 & X86_CR4_PAE))
800 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
801 && ((cr4 ^ old_cr4) & pdptr_bits)
802 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
806 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
810 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
811 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
815 if (kvm_x86_ops->set_cr4(vcpu, cr4))
818 if (((cr4 ^ old_cr4) & pdptr_bits) ||
819 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
820 kvm_mmu_reset_context(vcpu);
822 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
823 kvm_update_cpuid(vcpu);
827 EXPORT_SYMBOL_GPL(kvm_set_cr4);
829 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
832 cr3 &= ~CR3_PCID_INVD;
835 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
836 kvm_mmu_sync_roots(vcpu);
837 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
841 if (is_long_mode(vcpu) &&
842 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
844 else if (is_pae(vcpu) && is_paging(vcpu) &&
845 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
848 vcpu->arch.cr3 = cr3;
849 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
850 kvm_mmu_new_cr3(vcpu);
853 EXPORT_SYMBOL_GPL(kvm_set_cr3);
855 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
857 if (cr8 & CR8_RESERVED_BITS)
859 if (lapic_in_kernel(vcpu))
860 kvm_lapic_set_tpr(vcpu, cr8);
862 vcpu->arch.cr8 = cr8;
865 EXPORT_SYMBOL_GPL(kvm_set_cr8);
867 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
869 if (lapic_in_kernel(vcpu))
870 return kvm_lapic_get_cr8(vcpu);
872 return vcpu->arch.cr8;
874 EXPORT_SYMBOL_GPL(kvm_get_cr8);
876 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
880 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
881 for (i = 0; i < KVM_NR_DB_REGS; i++)
882 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
883 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
887 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
889 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
890 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
893 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
897 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
898 dr7 = vcpu->arch.guest_debug_dr7;
900 dr7 = vcpu->arch.dr7;
901 kvm_x86_ops->set_dr7(vcpu, dr7);
902 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
903 if (dr7 & DR7_BP_EN_MASK)
904 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
907 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
909 u64 fixed = DR6_FIXED_1;
911 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
916 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
920 vcpu->arch.db[dr] = val;
921 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
922 vcpu->arch.eff_db[dr] = val;
927 if (val & 0xffffffff00000000ULL)
929 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
930 kvm_update_dr6(vcpu);
935 if (val & 0xffffffff00000000ULL)
937 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
938 kvm_update_dr7(vcpu);
945 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
947 if (__kvm_set_dr(vcpu, dr, val)) {
948 kvm_inject_gp(vcpu, 0);
953 EXPORT_SYMBOL_GPL(kvm_set_dr);
955 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
959 *val = vcpu->arch.db[dr];
964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
965 *val = vcpu->arch.dr6;
967 *val = kvm_x86_ops->get_dr6(vcpu);
972 *val = vcpu->arch.dr7;
977 EXPORT_SYMBOL_GPL(kvm_get_dr);
979 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
981 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
985 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
988 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
989 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
992 EXPORT_SYMBOL_GPL(kvm_rdpmc);
995 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
996 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
998 * This list is modified at module load time to reflect the
999 * capabilities of the host cpu. This capabilities test skips MSRs that are
1000 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1001 * may depend on host virtualization features rather than host cpu features.
1004 static u32 msrs_to_save[] = {
1005 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1007 #ifdef CONFIG_X86_64
1008 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1010 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1011 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1012 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1015 static unsigned num_msrs_to_save;
1017 static u32 emulated_msrs[] = {
1018 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1019 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1020 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1021 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1022 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1023 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1024 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1026 HV_X64_MSR_VP_INDEX,
1027 HV_X64_MSR_VP_RUNTIME,
1028 HV_X64_MSR_SCONTROL,
1029 HV_X64_MSR_STIMER0_CONFIG,
1030 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1033 MSR_IA32_TSC_ADJUST,
1034 MSR_IA32_TSCDEADLINE,
1035 MSR_IA32_MISC_ENABLE,
1036 MSR_IA32_MCG_STATUS,
1038 MSR_IA32_MCG_EXT_CTL,
1041 MSR_MISC_FEATURES_ENABLES,
1044 static unsigned num_emulated_msrs;
1046 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1048 if (efer & efer_reserved_bits)
1051 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1054 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1059 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1061 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1063 u64 old_efer = vcpu->arch.efer;
1065 if (!kvm_valid_efer(vcpu, efer))
1069 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1073 efer |= vcpu->arch.efer & EFER_LMA;
1075 kvm_x86_ops->set_efer(vcpu, efer);
1077 /* Update reserved bits */
1078 if ((efer ^ old_efer) & EFER_NX)
1079 kvm_mmu_reset_context(vcpu);
1084 void kvm_enable_efer_bits(u64 mask)
1086 efer_reserved_bits &= ~mask;
1088 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1091 * Writes msr value into into the appropriate "register".
1092 * Returns 0 on success, non-0 otherwise.
1093 * Assumes vcpu_load() was already called.
1095 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1097 switch (msr->index) {
1100 case MSR_KERNEL_GS_BASE:
1103 if (is_noncanonical_address(msr->data, vcpu))
1106 case MSR_IA32_SYSENTER_EIP:
1107 case MSR_IA32_SYSENTER_ESP:
1109 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1110 * non-canonical address is written on Intel but not on
1111 * AMD (which ignores the top 32-bits, because it does
1112 * not implement 64-bit SYSENTER).
1114 * 64-bit code should hence be able to write a non-canonical
1115 * value on AMD. Making the address canonical ensures that
1116 * vmentry does not fail on Intel after writing a non-canonical
1117 * value, and that something deterministic happens if the guest
1118 * invokes 64-bit SYSENTER.
1120 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1122 return kvm_x86_ops->set_msr(vcpu, msr);
1124 EXPORT_SYMBOL_GPL(kvm_set_msr);
1127 * Adapt set_msr() to msr_io()'s calling convention
1129 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1131 struct msr_data msr;
1135 msr.host_initiated = true;
1136 r = kvm_get_msr(vcpu, &msr);
1144 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1146 struct msr_data msr;
1150 msr.host_initiated = true;
1151 return kvm_set_msr(vcpu, &msr);
1154 #ifdef CONFIG_X86_64
1155 struct pvclock_gtod_data {
1158 struct { /* extract of a clocksource struct */
1171 static struct pvclock_gtod_data pvclock_gtod_data;
1173 static void update_pvclock_gtod(struct timekeeper *tk)
1175 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1178 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1180 write_seqcount_begin(&vdata->seq);
1182 /* copy pvclock gtod data */
1183 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1184 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1185 vdata->clock.mask = tk->tkr_mono.mask;
1186 vdata->clock.mult = tk->tkr_mono.mult;
1187 vdata->clock.shift = tk->tkr_mono.shift;
1189 vdata->boot_ns = boot_ns;
1190 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1192 vdata->wall_time_sec = tk->xtime_sec;
1194 write_seqcount_end(&vdata->seq);
1198 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1201 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1202 * vcpu_enter_guest. This function is only called from
1203 * the physical CPU that is running vcpu.
1205 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1208 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1212 struct pvclock_wall_clock wc;
1213 struct timespec64 boot;
1218 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1223 ++version; /* first time write, random junk */
1227 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1231 * The guest calculates current wall clock time by adding
1232 * system time (updated by kvm_guest_time_update below) to the
1233 * wall clock specified here. guest system time equals host
1234 * system time for us, thus we must fill in host boot time here.
1236 getboottime64(&boot);
1238 if (kvm->arch.kvmclock_offset) {
1239 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1240 boot = timespec64_sub(boot, ts);
1242 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1243 wc.nsec = boot.tv_nsec;
1244 wc.version = version;
1246 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1249 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1252 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1254 do_shl32_div32(dividend, divisor);
1258 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1259 s8 *pshift, u32 *pmultiplier)
1267 scaled64 = scaled_hz;
1268 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1273 tps32 = (uint32_t)tps64;
1274 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1275 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1283 *pmultiplier = div_frac(scaled64, tps32);
1285 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1286 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1289 #ifdef CONFIG_X86_64
1290 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1293 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1294 static unsigned long max_tsc_khz;
1296 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1298 u64 v = (u64)khz * (1000000 + ppm);
1303 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1307 /* Guest TSC same frequency as host TSC? */
1309 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1313 /* TSC scaling supported? */
1314 if (!kvm_has_tsc_control) {
1315 if (user_tsc_khz > tsc_khz) {
1316 vcpu->arch.tsc_catchup = 1;
1317 vcpu->arch.tsc_always_catchup = 1;
1320 WARN(1, "user requested TSC rate below hardware speed\n");
1325 /* TSC scaling required - calculate ratio */
1326 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1327 user_tsc_khz, tsc_khz);
1329 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1330 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1335 vcpu->arch.tsc_scaling_ratio = ratio;
1339 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1341 u32 thresh_lo, thresh_hi;
1342 int use_scaling = 0;
1344 /* tsc_khz can be zero if TSC calibration fails */
1345 if (user_tsc_khz == 0) {
1346 /* set tsc_scaling_ratio to a safe value */
1347 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1351 /* Compute a scale to convert nanoseconds in TSC cycles */
1352 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1353 &vcpu->arch.virtual_tsc_shift,
1354 &vcpu->arch.virtual_tsc_mult);
1355 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1358 * Compute the variation in TSC rate which is acceptable
1359 * within the range of tolerance and decide if the
1360 * rate being applied is within that bounds of the hardware
1361 * rate. If so, no scaling or compensation need be done.
1363 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1364 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1365 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1366 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1369 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1372 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1374 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1375 vcpu->arch.virtual_tsc_mult,
1376 vcpu->arch.virtual_tsc_shift);
1377 tsc += vcpu->arch.this_tsc_write;
1381 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1383 #ifdef CONFIG_X86_64
1385 struct kvm_arch *ka = &vcpu->kvm->arch;
1386 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1388 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1389 atomic_read(&vcpu->kvm->online_vcpus));
1392 * Once the masterclock is enabled, always perform request in
1393 * order to update it.
1395 * In order to enable masterclock, the host clocksource must be TSC
1396 * and the vcpus need to have matched TSCs. When that happens,
1397 * perform request to enable masterclock.
1399 if (ka->use_master_clock ||
1400 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1401 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1403 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1404 atomic_read(&vcpu->kvm->online_vcpus),
1405 ka->use_master_clock, gtod->clock.vclock_mode);
1409 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1411 u64 curr_offset = vcpu->arch.tsc_offset;
1412 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1416 * Multiply tsc by a fixed point number represented by ratio.
1418 * The most significant 64-N bits (mult) of ratio represent the
1419 * integral part of the fixed point number; the remaining N bits
1420 * (frac) represent the fractional part, ie. ratio represents a fixed
1421 * point number (mult + frac * 2^(-N)).
1423 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1425 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1427 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1430 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1433 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1435 if (ratio != kvm_default_tsc_scaling_ratio)
1436 _tsc = __scale_tsc(ratio, tsc);
1440 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1442 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1446 tsc = kvm_scale_tsc(vcpu, rdtsc());
1448 return target_tsc - tsc;
1451 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1453 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1455 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1457 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1459 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1460 vcpu->arch.tsc_offset = offset;
1463 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1465 struct kvm *kvm = vcpu->kvm;
1466 u64 offset, ns, elapsed;
1467 unsigned long flags;
1469 bool already_matched;
1470 u64 data = msr->data;
1471 bool synchronizing = false;
1473 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1474 offset = kvm_compute_tsc_offset(vcpu, data);
1475 ns = ktime_get_boot_ns();
1476 elapsed = ns - kvm->arch.last_tsc_nsec;
1478 if (vcpu->arch.virtual_tsc_khz) {
1479 if (data == 0 && msr->host_initiated) {
1481 * detection of vcpu initialization -- need to sync
1482 * with other vCPUs. This particularly helps to keep
1483 * kvm_clock stable after CPU hotplug
1485 synchronizing = true;
1487 u64 tsc_exp = kvm->arch.last_tsc_write +
1488 nsec_to_cycles(vcpu, elapsed);
1489 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1491 * Special case: TSC write with a small delta (1 second)
1492 * of virtual cycle time against real time is
1493 * interpreted as an attempt to synchronize the CPU.
1495 synchronizing = data < tsc_exp + tsc_hz &&
1496 data + tsc_hz > tsc_exp;
1501 * For a reliable TSC, we can match TSC offsets, and for an unstable
1502 * TSC, we add elapsed time in this computation. We could let the
1503 * compensation code attempt to catch up if we fall behind, but
1504 * it's better to try to match offsets from the beginning.
1506 if (synchronizing &&
1507 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1508 if (!check_tsc_unstable()) {
1509 offset = kvm->arch.cur_tsc_offset;
1510 pr_debug("kvm: matched tsc offset for %llu\n", data);
1512 u64 delta = nsec_to_cycles(vcpu, elapsed);
1514 offset = kvm_compute_tsc_offset(vcpu, data);
1515 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1518 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1521 * We split periods of matched TSC writes into generations.
1522 * For each generation, we track the original measured
1523 * nanosecond time, offset, and write, so if TSCs are in
1524 * sync, we can match exact offset, and if not, we can match
1525 * exact software computation in compute_guest_tsc()
1527 * These values are tracked in kvm->arch.cur_xxx variables.
1529 kvm->arch.cur_tsc_generation++;
1530 kvm->arch.cur_tsc_nsec = ns;
1531 kvm->arch.cur_tsc_write = data;
1532 kvm->arch.cur_tsc_offset = offset;
1534 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1535 kvm->arch.cur_tsc_generation, data);
1539 * We also track th most recent recorded KHZ, write and time to
1540 * allow the matching interval to be extended at each write.
1542 kvm->arch.last_tsc_nsec = ns;
1543 kvm->arch.last_tsc_write = data;
1544 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1546 vcpu->arch.last_guest_tsc = data;
1548 /* Keep track of which generation this VCPU has synchronized to */
1549 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1550 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1551 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1553 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1554 update_ia32_tsc_adjust_msr(vcpu, offset);
1556 kvm_vcpu_write_tsc_offset(vcpu, offset);
1557 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1559 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1561 kvm->arch.nr_vcpus_matched_tsc = 0;
1562 } else if (!already_matched) {
1563 kvm->arch.nr_vcpus_matched_tsc++;
1566 kvm_track_tsc_matching(vcpu);
1567 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1570 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1572 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1575 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1578 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1580 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1581 WARN_ON(adjustment < 0);
1582 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1583 adjust_tsc_offset_guest(vcpu, adjustment);
1586 #ifdef CONFIG_X86_64
1588 static u64 read_tsc(void)
1590 u64 ret = (u64)rdtsc_ordered();
1591 u64 last = pvclock_gtod_data.clock.cycle_last;
1593 if (likely(ret >= last))
1597 * GCC likes to generate cmov here, but this branch is extremely
1598 * predictable (it's just a function of time and the likely is
1599 * very likely) and there's a data dependence, so force GCC
1600 * to generate a branch instead. I don't barrier() because
1601 * we don't actually need a barrier, and if this function
1602 * ever gets inlined it will generate worse code.
1608 static inline u64 vgettsc(u64 *cycle_now)
1611 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1613 *cycle_now = read_tsc();
1615 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1616 return v * gtod->clock.mult;
1619 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1621 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1627 seq = read_seqcount_begin(>od->seq);
1628 mode = gtod->clock.vclock_mode;
1629 ns = gtod->nsec_base;
1630 ns += vgettsc(cycle_now);
1631 ns >>= gtod->clock.shift;
1632 ns += gtod->boot_ns;
1633 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1639 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1641 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1647 seq = read_seqcount_begin(>od->seq);
1648 mode = gtod->clock.vclock_mode;
1649 ts->tv_sec = gtod->wall_time_sec;
1650 ns = gtod->nsec_base;
1651 ns += vgettsc(cycle_now);
1652 ns >>= gtod->clock.shift;
1653 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1655 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1661 /* returns true if host is using tsc clocksource */
1662 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1664 /* checked again under seqlock below */
1665 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1668 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1671 /* returns true if host is using tsc clocksource */
1672 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1675 /* checked again under seqlock below */
1676 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1679 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1685 * Assuming a stable TSC across physical CPUS, and a stable TSC
1686 * across virtual CPUs, the following condition is possible.
1687 * Each numbered line represents an event visible to both
1688 * CPUs at the next numbered event.
1690 * "timespecX" represents host monotonic time. "tscX" represents
1693 * VCPU0 on CPU0 | VCPU1 on CPU1
1695 * 1. read timespec0,tsc0
1696 * 2. | timespec1 = timespec0 + N
1698 * 3. transition to guest | transition to guest
1699 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1700 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1701 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1703 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1706 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1708 * - 0 < N - M => M < N
1710 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1711 * always the case (the difference between two distinct xtime instances
1712 * might be smaller then the difference between corresponding TSC reads,
1713 * when updating guest vcpus pvclock areas).
1715 * To avoid that problem, do not allow visibility of distinct
1716 * system_timestamp/tsc_timestamp values simultaneously: use a master
1717 * copy of host monotonic time values. Update that master copy
1720 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1724 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1726 #ifdef CONFIG_X86_64
1727 struct kvm_arch *ka = &kvm->arch;
1729 bool host_tsc_clocksource, vcpus_matched;
1731 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1732 atomic_read(&kvm->online_vcpus));
1735 * If the host uses TSC clock, then passthrough TSC as stable
1738 host_tsc_clocksource = kvm_get_time_and_clockread(
1739 &ka->master_kernel_ns,
1740 &ka->master_cycle_now);
1742 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1743 && !ka->backwards_tsc_observed
1744 && !ka->boot_vcpu_runs_old_kvmclock;
1746 if (ka->use_master_clock)
1747 atomic_set(&kvm_guest_has_master_clock, 1);
1749 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1750 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1755 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1757 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1760 static void kvm_gen_update_masterclock(struct kvm *kvm)
1762 #ifdef CONFIG_X86_64
1764 struct kvm_vcpu *vcpu;
1765 struct kvm_arch *ka = &kvm->arch;
1767 spin_lock(&ka->pvclock_gtod_sync_lock);
1768 kvm_make_mclock_inprogress_request(kvm);
1769 /* no guest entries from this point */
1770 pvclock_update_vm_gtod_copy(kvm);
1772 kvm_for_each_vcpu(i, vcpu, kvm)
1773 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1775 /* guest entries allowed */
1776 kvm_for_each_vcpu(i, vcpu, kvm)
1777 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1779 spin_unlock(&ka->pvclock_gtod_sync_lock);
1783 u64 get_kvmclock_ns(struct kvm *kvm)
1785 struct kvm_arch *ka = &kvm->arch;
1786 struct pvclock_vcpu_time_info hv_clock;
1789 spin_lock(&ka->pvclock_gtod_sync_lock);
1790 if (!ka->use_master_clock) {
1791 spin_unlock(&ka->pvclock_gtod_sync_lock);
1792 return ktime_get_boot_ns() + ka->kvmclock_offset;
1795 hv_clock.tsc_timestamp = ka->master_cycle_now;
1796 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1797 spin_unlock(&ka->pvclock_gtod_sync_lock);
1799 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1802 if (__this_cpu_read(cpu_tsc_khz)) {
1803 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1804 &hv_clock.tsc_shift,
1805 &hv_clock.tsc_to_system_mul);
1806 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1808 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1815 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1817 struct kvm_vcpu_arch *vcpu = &v->arch;
1818 struct pvclock_vcpu_time_info guest_hv_clock;
1820 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1821 &guest_hv_clock, sizeof(guest_hv_clock))))
1824 /* This VCPU is paused, but it's legal for a guest to read another
1825 * VCPU's kvmclock, so we really have to follow the specification where
1826 * it says that version is odd if data is being modified, and even after
1829 * Version field updates must be kept separate. This is because
1830 * kvm_write_guest_cached might use a "rep movs" instruction, and
1831 * writes within a string instruction are weakly ordered. So there
1832 * are three writes overall.
1834 * As a small optimization, only write the version field in the first
1835 * and third write. The vcpu->pv_time cache is still valid, because the
1836 * version field is the first in the struct.
1838 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1840 if (guest_hv_clock.version & 1)
1841 ++guest_hv_clock.version; /* first time write, random junk */
1843 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1844 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 sizeof(vcpu->hv_clock.version));
1850 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1851 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1853 if (vcpu->pvclock_set_guest_stopped_request) {
1854 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1855 vcpu->pvclock_set_guest_stopped_request = false;
1858 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1860 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1862 sizeof(vcpu->hv_clock));
1866 vcpu->hv_clock.version++;
1867 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1869 sizeof(vcpu->hv_clock.version));
1872 static int kvm_guest_time_update(struct kvm_vcpu *v)
1874 unsigned long flags, tgt_tsc_khz;
1875 struct kvm_vcpu_arch *vcpu = &v->arch;
1876 struct kvm_arch *ka = &v->kvm->arch;
1878 u64 tsc_timestamp, host_tsc;
1880 bool use_master_clock;
1886 * If the host uses TSC clock, then passthrough TSC as stable
1889 spin_lock(&ka->pvclock_gtod_sync_lock);
1890 use_master_clock = ka->use_master_clock;
1891 if (use_master_clock) {
1892 host_tsc = ka->master_cycle_now;
1893 kernel_ns = ka->master_kernel_ns;
1895 spin_unlock(&ka->pvclock_gtod_sync_lock);
1897 /* Keep irq disabled to prevent changes to the clock */
1898 local_irq_save(flags);
1899 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1900 if (unlikely(tgt_tsc_khz == 0)) {
1901 local_irq_restore(flags);
1902 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1905 if (!use_master_clock) {
1907 kernel_ns = ktime_get_boot_ns();
1910 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1913 * We may have to catch up the TSC to match elapsed wall clock
1914 * time for two reasons, even if kvmclock is used.
1915 * 1) CPU could have been running below the maximum TSC rate
1916 * 2) Broken TSC compensation resets the base at each VCPU
1917 * entry to avoid unknown leaps of TSC even when running
1918 * again on the same CPU. This may cause apparent elapsed
1919 * time to disappear, and the guest to stand still or run
1922 if (vcpu->tsc_catchup) {
1923 u64 tsc = compute_guest_tsc(v, kernel_ns);
1924 if (tsc > tsc_timestamp) {
1925 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1926 tsc_timestamp = tsc;
1930 local_irq_restore(flags);
1932 /* With all the info we got, fill in the values */
1934 if (kvm_has_tsc_control)
1935 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1937 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1938 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1939 &vcpu->hv_clock.tsc_shift,
1940 &vcpu->hv_clock.tsc_to_system_mul);
1941 vcpu->hw_tsc_khz = tgt_tsc_khz;
1944 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1945 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1946 vcpu->last_guest_tsc = tsc_timestamp;
1948 /* If the host uses TSC clocksource, then it is stable */
1950 if (use_master_clock)
1951 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1953 vcpu->hv_clock.flags = pvclock_flags;
1955 if (vcpu->pv_time_enabled)
1956 kvm_setup_pvclock_page(v);
1957 if (v == kvm_get_vcpu(v->kvm, 0))
1958 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1963 * kvmclock updates which are isolated to a given vcpu, such as
1964 * vcpu->cpu migration, should not allow system_timestamp from
1965 * the rest of the vcpus to remain static. Otherwise ntp frequency
1966 * correction applies to one vcpu's system_timestamp but not
1969 * So in those cases, request a kvmclock update for all vcpus.
1970 * We need to rate-limit these requests though, as they can
1971 * considerably slow guests that have a large number of vcpus.
1972 * The time for a remote vcpu to update its kvmclock is bound
1973 * by the delay we use to rate-limit the updates.
1976 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1978 static void kvmclock_update_fn(struct work_struct *work)
1981 struct delayed_work *dwork = to_delayed_work(work);
1982 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1983 kvmclock_update_work);
1984 struct kvm *kvm = container_of(ka, struct kvm, arch);
1985 struct kvm_vcpu *vcpu;
1987 kvm_for_each_vcpu(i, vcpu, kvm) {
1988 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1989 kvm_vcpu_kick(vcpu);
1993 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1995 struct kvm *kvm = v->kvm;
1997 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1998 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1999 KVMCLOCK_UPDATE_DELAY);
2002 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2004 static void kvmclock_sync_fn(struct work_struct *work)
2006 struct delayed_work *dwork = to_delayed_work(work);
2007 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2008 kvmclock_sync_work);
2009 struct kvm *kvm = container_of(ka, struct kvm, arch);
2011 if (!kvmclock_periodic_sync)
2014 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2015 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2016 KVMCLOCK_SYNC_PERIOD);
2019 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2021 u64 mcg_cap = vcpu->arch.mcg_cap;
2022 unsigned bank_num = mcg_cap & 0xff;
2023 u32 msr = msr_info->index;
2024 u64 data = msr_info->data;
2027 case MSR_IA32_MCG_STATUS:
2028 vcpu->arch.mcg_status = data;
2030 case MSR_IA32_MCG_CTL:
2031 if (!(mcg_cap & MCG_CTL_P))
2033 if (data != 0 && data != ~(u64)0)
2035 vcpu->arch.mcg_ctl = data;
2038 if (msr >= MSR_IA32_MC0_CTL &&
2039 msr < MSR_IA32_MCx_CTL(bank_num)) {
2040 u32 offset = msr - MSR_IA32_MC0_CTL;
2041 /* only 0 or all 1s can be written to IA32_MCi_CTL
2042 * some Linux kernels though clear bit 10 in bank 4 to
2043 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2044 * this to avoid an uncatched #GP in the guest
2046 if ((offset & 0x3) == 0 &&
2047 data != 0 && (data | (1 << 10)) != ~(u64)0)
2049 if (!msr_info->host_initiated &&
2050 (offset & 0x3) == 1 && data != 0)
2052 vcpu->arch.mce_banks[offset] = data;
2060 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2062 struct kvm *kvm = vcpu->kvm;
2063 int lm = is_long_mode(vcpu);
2064 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2065 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2066 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2067 : kvm->arch.xen_hvm_config.blob_size_32;
2068 u32 page_num = data & ~PAGE_MASK;
2069 u64 page_addr = data & PAGE_MASK;
2074 if (page_num >= blob_size)
2077 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2082 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2091 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2093 gpa_t gpa = data & ~0x3f;
2095 /* Bits 3:5 are reserved, Should be zero */
2099 vcpu->arch.apf.msr_val = data;
2101 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2102 kvm_clear_async_pf_completion_queue(vcpu);
2103 kvm_async_pf_hash_reset(vcpu);
2107 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2111 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2112 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2113 kvm_async_pf_wakeup_all(vcpu);
2117 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2119 vcpu->arch.pv_time_enabled = false;
2122 static void record_steal_time(struct kvm_vcpu *vcpu)
2124 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2127 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2128 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2131 vcpu->arch.st.steal.preempted = 0;
2133 if (vcpu->arch.st.steal.version & 1)
2134 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2136 vcpu->arch.st.steal.version += 1;
2138 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2139 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2143 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2144 vcpu->arch.st.last_steal;
2145 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2147 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2148 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2152 vcpu->arch.st.steal.version += 1;
2154 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2155 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2158 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2161 u32 msr = msr_info->index;
2162 u64 data = msr_info->data;
2165 case MSR_AMD64_NB_CFG:
2166 case MSR_IA32_UCODE_REV:
2167 case MSR_IA32_UCODE_WRITE:
2168 case MSR_VM_HSAVE_PA:
2169 case MSR_AMD64_PATCH_LOADER:
2170 case MSR_AMD64_BU_CFG2:
2171 case MSR_AMD64_DC_CFG:
2175 return set_efer(vcpu, data);
2177 data &= ~(u64)0x40; /* ignore flush filter disable */
2178 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2179 data &= ~(u64)0x8; /* ignore TLB cache disable */
2180 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2182 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2187 case MSR_FAM10H_MMIO_CONF_BASE:
2189 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2194 case MSR_IA32_DEBUGCTLMSR:
2196 /* We support the non-activated case already */
2198 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2199 /* Values other than LBR and BTF are vendor-specific,
2200 thus reserved and should throw a #GP */
2203 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2206 case 0x200 ... 0x2ff:
2207 return kvm_mtrr_set_msr(vcpu, msr, data);
2208 case MSR_IA32_APICBASE:
2209 return kvm_set_apic_base(vcpu, msr_info);
2210 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2211 return kvm_x2apic_msr_write(vcpu, msr, data);
2212 case MSR_IA32_TSCDEADLINE:
2213 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2215 case MSR_IA32_TSC_ADJUST:
2216 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2217 if (!msr_info->host_initiated) {
2218 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2219 adjust_tsc_offset_guest(vcpu, adj);
2221 vcpu->arch.ia32_tsc_adjust_msr = data;
2224 case MSR_IA32_MISC_ENABLE:
2225 vcpu->arch.ia32_misc_enable_msr = data;
2227 case MSR_IA32_SMBASE:
2228 if (!msr_info->host_initiated)
2230 vcpu->arch.smbase = data;
2232 case MSR_KVM_WALL_CLOCK_NEW:
2233 case MSR_KVM_WALL_CLOCK:
2234 vcpu->kvm->arch.wall_clock = data;
2235 kvm_write_wall_clock(vcpu->kvm, data);
2237 case MSR_KVM_SYSTEM_TIME_NEW:
2238 case MSR_KVM_SYSTEM_TIME: {
2239 struct kvm_arch *ka = &vcpu->kvm->arch;
2241 kvmclock_reset(vcpu);
2243 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2244 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2246 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2247 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2249 ka->boot_vcpu_runs_old_kvmclock = tmp;
2252 vcpu->arch.time = data;
2253 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2255 /* we verify if the enable bit is set... */
2259 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2260 &vcpu->arch.pv_time, data & ~1ULL,
2261 sizeof(struct pvclock_vcpu_time_info)))
2262 vcpu->arch.pv_time_enabled = false;
2264 vcpu->arch.pv_time_enabled = true;
2268 case MSR_KVM_ASYNC_PF_EN:
2269 if (kvm_pv_enable_async_pf(vcpu, data))
2272 case MSR_KVM_STEAL_TIME:
2274 if (unlikely(!sched_info_on()))
2277 if (data & KVM_STEAL_RESERVED_MASK)
2280 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2281 data & KVM_STEAL_VALID_BITS,
2282 sizeof(struct kvm_steal_time)))
2285 vcpu->arch.st.msr_val = data;
2287 if (!(data & KVM_MSR_ENABLED))
2290 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2293 case MSR_KVM_PV_EOI_EN:
2294 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2298 case MSR_IA32_MCG_CTL:
2299 case MSR_IA32_MCG_STATUS:
2300 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2301 return set_msr_mce(vcpu, msr_info);
2303 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2304 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2305 pr = true; /* fall through */
2306 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2307 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2308 if (kvm_pmu_is_valid_msr(vcpu, msr))
2309 return kvm_pmu_set_msr(vcpu, msr_info);
2311 if (pr || data != 0)
2312 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2313 "0x%x data 0x%llx\n", msr, data);
2315 case MSR_K7_CLK_CTL:
2317 * Ignore all writes to this no longer documented MSR.
2318 * Writes are only relevant for old K7 processors,
2319 * all pre-dating SVM, but a recommended workaround from
2320 * AMD for these chips. It is possible to specify the
2321 * affected processor models on the command line, hence
2322 * the need to ignore the workaround.
2325 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2326 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2327 case HV_X64_MSR_CRASH_CTL:
2328 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2329 return kvm_hv_set_msr_common(vcpu, msr, data,
2330 msr_info->host_initiated);
2331 case MSR_IA32_BBL_CR_CTL3:
2332 /* Drop writes to this legacy MSR -- see rdmsr
2333 * counterpart for further detail.
2335 if (report_ignored_msrs)
2336 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2339 case MSR_AMD64_OSVW_ID_LENGTH:
2340 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2342 vcpu->arch.osvw.length = data;
2344 case MSR_AMD64_OSVW_STATUS:
2345 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2347 vcpu->arch.osvw.status = data;
2349 case MSR_PLATFORM_INFO:
2350 if (!msr_info->host_initiated ||
2351 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2352 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2353 cpuid_fault_enabled(vcpu)))
2355 vcpu->arch.msr_platform_info = data;
2357 case MSR_MISC_FEATURES_ENABLES:
2358 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2359 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2360 !supports_cpuid_fault(vcpu)))
2362 vcpu->arch.msr_misc_features_enables = data;
2365 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2366 return xen_hvm_config(vcpu, data);
2367 if (kvm_pmu_is_valid_msr(vcpu, msr))
2368 return kvm_pmu_set_msr(vcpu, msr_info);
2370 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2374 if (report_ignored_msrs)
2376 "ignored wrmsr: 0x%x data 0x%llx\n",
2383 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2387 * Reads an msr value (of 'msr_index') into 'pdata'.
2388 * Returns 0 on success, non-0 otherwise.
2389 * Assumes vcpu_load() was already called.
2391 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2393 return kvm_x86_ops->get_msr(vcpu, msr);
2395 EXPORT_SYMBOL_GPL(kvm_get_msr);
2397 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2400 u64 mcg_cap = vcpu->arch.mcg_cap;
2401 unsigned bank_num = mcg_cap & 0xff;
2404 case MSR_IA32_P5_MC_ADDR:
2405 case MSR_IA32_P5_MC_TYPE:
2408 case MSR_IA32_MCG_CAP:
2409 data = vcpu->arch.mcg_cap;
2411 case MSR_IA32_MCG_CTL:
2412 if (!(mcg_cap & MCG_CTL_P))
2414 data = vcpu->arch.mcg_ctl;
2416 case MSR_IA32_MCG_STATUS:
2417 data = vcpu->arch.mcg_status;
2420 if (msr >= MSR_IA32_MC0_CTL &&
2421 msr < MSR_IA32_MCx_CTL(bank_num)) {
2422 u32 offset = msr - MSR_IA32_MC0_CTL;
2423 data = vcpu->arch.mce_banks[offset];
2432 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2434 switch (msr_info->index) {
2435 case MSR_IA32_PLATFORM_ID:
2436 case MSR_IA32_EBL_CR_POWERON:
2437 case MSR_IA32_DEBUGCTLMSR:
2438 case MSR_IA32_LASTBRANCHFROMIP:
2439 case MSR_IA32_LASTBRANCHTOIP:
2440 case MSR_IA32_LASTINTFROMIP:
2441 case MSR_IA32_LASTINTTOIP:
2443 case MSR_K8_TSEG_ADDR:
2444 case MSR_K8_TSEG_MASK:
2446 case MSR_VM_HSAVE_PA:
2447 case MSR_K8_INT_PENDING_MSG:
2448 case MSR_AMD64_NB_CFG:
2449 case MSR_FAM10H_MMIO_CONF_BASE:
2450 case MSR_AMD64_BU_CFG2:
2451 case MSR_IA32_PERF_CTL:
2452 case MSR_AMD64_DC_CFG:
2455 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2456 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2457 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2458 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2459 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2460 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2463 case MSR_IA32_UCODE_REV:
2464 msr_info->data = 0x100000000ULL;
2467 case 0x200 ... 0x2ff:
2468 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2469 case 0xcd: /* fsb frequency */
2473 * MSR_EBC_FREQUENCY_ID
2474 * Conservative value valid for even the basic CPU models.
2475 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2476 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2477 * and 266MHz for model 3, or 4. Set Core Clock
2478 * Frequency to System Bus Frequency Ratio to 1 (bits
2479 * 31:24) even though these are only valid for CPU
2480 * models > 2, however guests may end up dividing or
2481 * multiplying by zero otherwise.
2483 case MSR_EBC_FREQUENCY_ID:
2484 msr_info->data = 1 << 24;
2486 case MSR_IA32_APICBASE:
2487 msr_info->data = kvm_get_apic_base(vcpu);
2489 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2490 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2492 case MSR_IA32_TSCDEADLINE:
2493 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2495 case MSR_IA32_TSC_ADJUST:
2496 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2498 case MSR_IA32_MISC_ENABLE:
2499 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2501 case MSR_IA32_SMBASE:
2502 if (!msr_info->host_initiated)
2504 msr_info->data = vcpu->arch.smbase;
2506 case MSR_IA32_PERF_STATUS:
2507 /* TSC increment by tick */
2508 msr_info->data = 1000ULL;
2509 /* CPU multiplier */
2510 msr_info->data |= (((uint64_t)4ULL) << 40);
2513 msr_info->data = vcpu->arch.efer;
2515 case MSR_KVM_WALL_CLOCK:
2516 case MSR_KVM_WALL_CLOCK_NEW:
2517 msr_info->data = vcpu->kvm->arch.wall_clock;
2519 case MSR_KVM_SYSTEM_TIME:
2520 case MSR_KVM_SYSTEM_TIME_NEW:
2521 msr_info->data = vcpu->arch.time;
2523 case MSR_KVM_ASYNC_PF_EN:
2524 msr_info->data = vcpu->arch.apf.msr_val;
2526 case MSR_KVM_STEAL_TIME:
2527 msr_info->data = vcpu->arch.st.msr_val;
2529 case MSR_KVM_PV_EOI_EN:
2530 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2532 case MSR_IA32_P5_MC_ADDR:
2533 case MSR_IA32_P5_MC_TYPE:
2534 case MSR_IA32_MCG_CAP:
2535 case MSR_IA32_MCG_CTL:
2536 case MSR_IA32_MCG_STATUS:
2537 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2538 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2539 case MSR_K7_CLK_CTL:
2541 * Provide expected ramp-up count for K7. All other
2542 * are set to zero, indicating minimum divisors for
2545 * This prevents guest kernels on AMD host with CPU
2546 * type 6, model 8 and higher from exploding due to
2547 * the rdmsr failing.
2549 msr_info->data = 0x20000000;
2551 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2552 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2553 case HV_X64_MSR_CRASH_CTL:
2554 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2555 return kvm_hv_get_msr_common(vcpu,
2556 msr_info->index, &msr_info->data);
2558 case MSR_IA32_BBL_CR_CTL3:
2559 /* This legacy MSR exists but isn't fully documented in current
2560 * silicon. It is however accessed by winxp in very narrow
2561 * scenarios where it sets bit #19, itself documented as
2562 * a "reserved" bit. Best effort attempt to source coherent
2563 * read data here should the balance of the register be
2564 * interpreted by the guest:
2566 * L2 cache control register 3: 64GB range, 256KB size,
2567 * enabled, latency 0x1, configured
2569 msr_info->data = 0xbe702111;
2571 case MSR_AMD64_OSVW_ID_LENGTH:
2572 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2574 msr_info->data = vcpu->arch.osvw.length;
2576 case MSR_AMD64_OSVW_STATUS:
2577 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2579 msr_info->data = vcpu->arch.osvw.status;
2581 case MSR_PLATFORM_INFO:
2582 msr_info->data = vcpu->arch.msr_platform_info;
2584 case MSR_MISC_FEATURES_ENABLES:
2585 msr_info->data = vcpu->arch.msr_misc_features_enables;
2588 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2589 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2591 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2595 if (report_ignored_msrs)
2596 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2604 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2607 * Read or write a bunch of msrs. All parameters are kernel addresses.
2609 * @return number of msrs set successfully.
2611 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2612 struct kvm_msr_entry *entries,
2613 int (*do_msr)(struct kvm_vcpu *vcpu,
2614 unsigned index, u64 *data))
2618 idx = srcu_read_lock(&vcpu->kvm->srcu);
2619 for (i = 0; i < msrs->nmsrs; ++i)
2620 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2622 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2628 * Read or write a bunch of msrs. Parameters are user addresses.
2630 * @return number of msrs set successfully.
2632 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2633 int (*do_msr)(struct kvm_vcpu *vcpu,
2634 unsigned index, u64 *data),
2637 struct kvm_msrs msrs;
2638 struct kvm_msr_entry *entries;
2643 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2647 if (msrs.nmsrs >= MAX_IO_MSRS)
2650 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2651 entries = memdup_user(user_msrs->entries, size);
2652 if (IS_ERR(entries)) {
2653 r = PTR_ERR(entries);
2657 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2662 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2673 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2678 case KVM_CAP_IRQCHIP:
2680 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2681 case KVM_CAP_SET_TSS_ADDR:
2682 case KVM_CAP_EXT_CPUID:
2683 case KVM_CAP_EXT_EMUL_CPUID:
2684 case KVM_CAP_CLOCKSOURCE:
2686 case KVM_CAP_NOP_IO_DELAY:
2687 case KVM_CAP_MP_STATE:
2688 case KVM_CAP_SYNC_MMU:
2689 case KVM_CAP_USER_NMI:
2690 case KVM_CAP_REINJECT_CONTROL:
2691 case KVM_CAP_IRQ_INJECT_STATUS:
2692 case KVM_CAP_IOEVENTFD:
2693 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2695 case KVM_CAP_PIT_STATE2:
2696 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2697 case KVM_CAP_XEN_HVM:
2698 case KVM_CAP_VCPU_EVENTS:
2699 case KVM_CAP_HYPERV:
2700 case KVM_CAP_HYPERV_VAPIC:
2701 case KVM_CAP_HYPERV_SPIN:
2702 case KVM_CAP_HYPERV_SYNIC:
2703 case KVM_CAP_HYPERV_SYNIC2:
2704 case KVM_CAP_HYPERV_VP_INDEX:
2705 case KVM_CAP_PCI_SEGMENT:
2706 case KVM_CAP_DEBUGREGS:
2707 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2709 case KVM_CAP_ASYNC_PF:
2710 case KVM_CAP_GET_TSC_KHZ:
2711 case KVM_CAP_KVMCLOCK_CTRL:
2712 case KVM_CAP_READONLY_MEM:
2713 case KVM_CAP_HYPERV_TIME:
2714 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2715 case KVM_CAP_TSC_DEADLINE_TIMER:
2716 case KVM_CAP_ENABLE_CAP_VM:
2717 case KVM_CAP_DISABLE_QUIRKS:
2718 case KVM_CAP_SET_BOOT_CPU_ID:
2719 case KVM_CAP_SPLIT_IRQCHIP:
2720 case KVM_CAP_IMMEDIATE_EXIT:
2723 case KVM_CAP_ADJUST_CLOCK:
2724 r = KVM_CLOCK_TSC_STABLE;
2726 case KVM_CAP_X86_GUEST_MWAIT:
2727 r = kvm_mwait_in_guest();
2729 case KVM_CAP_X86_SMM:
2730 /* SMBASE is usually relocated above 1M on modern chipsets,
2731 * and SMM handlers might indeed rely on 4G segment limits,
2732 * so do not report SMM to be available if real mode is
2733 * emulated via vm86 mode. Still, do not go to great lengths
2734 * to avoid userspace's usage of the feature, because it is a
2735 * fringe case that is not enabled except via specific settings
2736 * of the module parameters.
2738 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2741 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2743 case KVM_CAP_NR_VCPUS:
2744 r = KVM_SOFT_MAX_VCPUS;
2746 case KVM_CAP_MAX_VCPUS:
2749 case KVM_CAP_NR_MEMSLOTS:
2750 r = KVM_USER_MEM_SLOTS;
2752 case KVM_CAP_PV_MMU: /* obsolete */
2756 r = KVM_MAX_MCE_BANKS;
2759 r = boot_cpu_has(X86_FEATURE_XSAVE);
2761 case KVM_CAP_TSC_CONTROL:
2762 r = kvm_has_tsc_control;
2764 case KVM_CAP_X2APIC_API:
2765 r = KVM_X2APIC_API_VALID_FLAGS;
2775 long kvm_arch_dev_ioctl(struct file *filp,
2776 unsigned int ioctl, unsigned long arg)
2778 void __user *argp = (void __user *)arg;
2782 case KVM_GET_MSR_INDEX_LIST: {
2783 struct kvm_msr_list __user *user_msr_list = argp;
2784 struct kvm_msr_list msr_list;
2788 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2791 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2792 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2795 if (n < msr_list.nmsrs)
2798 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2799 num_msrs_to_save * sizeof(u32)))
2801 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2803 num_emulated_msrs * sizeof(u32)))
2808 case KVM_GET_SUPPORTED_CPUID:
2809 case KVM_GET_EMULATED_CPUID: {
2810 struct kvm_cpuid2 __user *cpuid_arg = argp;
2811 struct kvm_cpuid2 cpuid;
2814 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2817 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2823 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2828 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2830 if (copy_to_user(argp, &kvm_mce_cap_supported,
2831 sizeof(kvm_mce_cap_supported)))
2843 static void wbinvd_ipi(void *garbage)
2848 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2850 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2853 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2855 /* Address WBINVD may be executed by guest */
2856 if (need_emulate_wbinvd(vcpu)) {
2857 if (kvm_x86_ops->has_wbinvd_exit())
2858 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2859 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2860 smp_call_function_single(vcpu->cpu,
2861 wbinvd_ipi, NULL, 1);
2864 kvm_x86_ops->vcpu_load(vcpu, cpu);
2866 /* Apply any externally detected TSC adjustments (due to suspend) */
2867 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2868 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2869 vcpu->arch.tsc_offset_adjustment = 0;
2870 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2873 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2874 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2875 rdtsc() - vcpu->arch.last_host_tsc;
2877 mark_tsc_unstable("KVM discovered backwards TSC");
2879 if (check_tsc_unstable()) {
2880 u64 offset = kvm_compute_tsc_offset(vcpu,
2881 vcpu->arch.last_guest_tsc);
2882 kvm_vcpu_write_tsc_offset(vcpu, offset);
2883 vcpu->arch.tsc_catchup = 1;
2886 if (kvm_lapic_hv_timer_in_use(vcpu))
2887 kvm_lapic_restart_hv_timer(vcpu);
2890 * On a host with synchronized TSC, there is no need to update
2891 * kvmclock on vcpu->cpu migration
2893 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2894 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2895 if (vcpu->cpu != cpu)
2896 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
2900 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2903 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2905 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2908 vcpu->arch.st.steal.preempted = 1;
2910 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2911 &vcpu->arch.st.steal.preempted,
2912 offsetof(struct kvm_steal_time, preempted),
2913 sizeof(vcpu->arch.st.steal.preempted));
2916 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2920 if (vcpu->preempted)
2921 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2924 * Disable page faults because we're in atomic context here.
2925 * kvm_write_guest_offset_cached() would call might_fault()
2926 * that relies on pagefault_disable() to tell if there's a
2927 * bug. NOTE: the write to guest memory may not go through if
2928 * during postcopy live migration or if there's heavy guest
2931 pagefault_disable();
2933 * kvm_memslots() will be called by
2934 * kvm_write_guest_offset_cached() so take the srcu lock.
2936 idx = srcu_read_lock(&vcpu->kvm->srcu);
2937 kvm_steal_time_set_preempted(vcpu);
2938 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2940 kvm_x86_ops->vcpu_put(vcpu);
2941 vcpu->arch.last_host_tsc = rdtsc();
2944 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2945 struct kvm_lapic_state *s)
2947 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
2948 kvm_x86_ops->sync_pir_to_irr(vcpu);
2950 return kvm_apic_get_state(vcpu, s);
2953 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2954 struct kvm_lapic_state *s)
2958 r = kvm_apic_set_state(vcpu, s);
2961 update_cr8_intercept(vcpu);
2966 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2968 return (!lapic_in_kernel(vcpu) ||
2969 kvm_apic_accept_pic_intr(vcpu));
2973 * if userspace requested an interrupt window, check that the
2974 * interrupt window is open.
2976 * No need to exit to userspace if we already have an interrupt queued.
2978 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2980 return kvm_arch_interrupt_allowed(vcpu) &&
2981 !kvm_cpu_has_interrupt(vcpu) &&
2982 !kvm_event_needs_reinjection(vcpu) &&
2983 kvm_cpu_accept_dm_intr(vcpu);
2986 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2987 struct kvm_interrupt *irq)
2989 if (irq->irq >= KVM_NR_INTERRUPTS)
2992 if (!irqchip_in_kernel(vcpu->kvm)) {
2993 kvm_queue_interrupt(vcpu, irq->irq, false);
2994 kvm_make_request(KVM_REQ_EVENT, vcpu);
2999 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3000 * fail for in-kernel 8259.
3002 if (pic_in_kernel(vcpu->kvm))
3005 if (vcpu->arch.pending_external_vector != -1)
3008 vcpu->arch.pending_external_vector = irq->irq;
3009 kvm_make_request(KVM_REQ_EVENT, vcpu);
3013 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3015 kvm_inject_nmi(vcpu);
3020 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3022 kvm_make_request(KVM_REQ_SMI, vcpu);
3027 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3028 struct kvm_tpr_access_ctl *tac)
3032 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3036 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3040 unsigned bank_num = mcg_cap & 0xff, bank;
3043 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3045 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3048 vcpu->arch.mcg_cap = mcg_cap;
3049 /* Init IA32_MCG_CTL to all 1s */
3050 if (mcg_cap & MCG_CTL_P)
3051 vcpu->arch.mcg_ctl = ~(u64)0;
3052 /* Init IA32_MCi_CTL to all 1s */
3053 for (bank = 0; bank < bank_num; bank++)
3054 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3056 if (kvm_x86_ops->setup_mce)
3057 kvm_x86_ops->setup_mce(vcpu);
3062 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3063 struct kvm_x86_mce *mce)
3065 u64 mcg_cap = vcpu->arch.mcg_cap;
3066 unsigned bank_num = mcg_cap & 0xff;
3067 u64 *banks = vcpu->arch.mce_banks;
3069 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3072 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3073 * reporting is disabled
3075 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3076 vcpu->arch.mcg_ctl != ~(u64)0)
3078 banks += 4 * mce->bank;
3080 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3081 * reporting is disabled for the bank
3083 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3085 if (mce->status & MCI_STATUS_UC) {
3086 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3087 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3088 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3091 if (banks[1] & MCI_STATUS_VAL)
3092 mce->status |= MCI_STATUS_OVER;
3093 banks[2] = mce->addr;
3094 banks[3] = mce->misc;
3095 vcpu->arch.mcg_status = mce->mcg_status;
3096 banks[1] = mce->status;
3097 kvm_queue_exception(vcpu, MC_VECTOR);
3098 } else if (!(banks[1] & MCI_STATUS_VAL)
3099 || !(banks[1] & MCI_STATUS_UC)) {
3100 if (banks[1] & MCI_STATUS_VAL)
3101 mce->status |= MCI_STATUS_OVER;
3102 banks[2] = mce->addr;
3103 banks[3] = mce->misc;
3104 banks[1] = mce->status;
3106 banks[1] |= MCI_STATUS_OVER;
3110 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3111 struct kvm_vcpu_events *events)
3115 * FIXME: pass injected and pending separately. This is only
3116 * needed for nested virtualization, whose state cannot be
3117 * migrated yet. For now we can combine them.
3119 events->exception.injected =
3120 (vcpu->arch.exception.pending ||
3121 vcpu->arch.exception.injected) &&
3122 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3123 events->exception.nr = vcpu->arch.exception.nr;
3124 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3125 events->exception.pad = 0;
3126 events->exception.error_code = vcpu->arch.exception.error_code;
3128 events->interrupt.injected =
3129 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3130 events->interrupt.nr = vcpu->arch.interrupt.nr;
3131 events->interrupt.soft = 0;
3132 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3134 events->nmi.injected = vcpu->arch.nmi_injected;
3135 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3136 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3137 events->nmi.pad = 0;
3139 events->sipi_vector = 0; /* never valid when reporting to user space */
3141 events->smi.smm = is_smm(vcpu);
3142 events->smi.pending = vcpu->arch.smi_pending;
3143 events->smi.smm_inside_nmi =
3144 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3145 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3147 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3148 | KVM_VCPUEVENT_VALID_SHADOW
3149 | KVM_VCPUEVENT_VALID_SMM);
3150 memset(&events->reserved, 0, sizeof(events->reserved));
3153 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3155 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3156 struct kvm_vcpu_events *events)
3158 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3159 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3160 | KVM_VCPUEVENT_VALID_SHADOW
3161 | KVM_VCPUEVENT_VALID_SMM))
3164 if (events->exception.injected &&
3165 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3166 is_guest_mode(vcpu)))
3169 /* INITs are latched while in SMM */
3170 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3171 (events->smi.smm || events->smi.pending) &&
3172 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3176 vcpu->arch.exception.injected = false;
3177 vcpu->arch.exception.pending = events->exception.injected;
3178 vcpu->arch.exception.nr = events->exception.nr;
3179 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3180 vcpu->arch.exception.error_code = events->exception.error_code;
3182 vcpu->arch.interrupt.pending = events->interrupt.injected;
3183 vcpu->arch.interrupt.nr = events->interrupt.nr;
3184 vcpu->arch.interrupt.soft = events->interrupt.soft;
3185 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3186 kvm_x86_ops->set_interrupt_shadow(vcpu,
3187 events->interrupt.shadow);
3189 vcpu->arch.nmi_injected = events->nmi.injected;
3190 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3191 vcpu->arch.nmi_pending = events->nmi.pending;
3192 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3194 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3195 lapic_in_kernel(vcpu))
3196 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3198 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3199 u32 hflags = vcpu->arch.hflags;
3200 if (events->smi.smm)
3201 hflags |= HF_SMM_MASK;
3203 hflags &= ~HF_SMM_MASK;
3204 kvm_set_hflags(vcpu, hflags);
3206 vcpu->arch.smi_pending = events->smi.pending;
3208 if (events->smi.smm) {
3209 if (events->smi.smm_inside_nmi)
3210 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3212 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3213 if (lapic_in_kernel(vcpu)) {
3214 if (events->smi.latched_init)
3215 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3217 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3222 kvm_make_request(KVM_REQ_EVENT, vcpu);
3227 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3228 struct kvm_debugregs *dbgregs)
3232 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3233 kvm_get_dr(vcpu, 6, &val);
3235 dbgregs->dr7 = vcpu->arch.dr7;
3237 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3240 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3241 struct kvm_debugregs *dbgregs)
3246 if (dbgregs->dr6 & ~0xffffffffull)
3248 if (dbgregs->dr7 & ~0xffffffffull)
3251 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3252 kvm_update_dr0123(vcpu);
3253 vcpu->arch.dr6 = dbgregs->dr6;
3254 kvm_update_dr6(vcpu);
3255 vcpu->arch.dr7 = dbgregs->dr7;
3256 kvm_update_dr7(vcpu);
3261 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3263 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3265 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3266 u64 xstate_bv = xsave->header.xfeatures;
3270 * Copy legacy XSAVE area, to avoid complications with CPUID
3271 * leaves 0 and 1 in the loop below.
3273 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3276 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3277 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3280 * Copy each region from the possibly compacted offset to the
3281 * non-compacted offset.
3283 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3285 u64 feature = valid & -valid;
3286 int index = fls64(feature) - 1;
3287 void *src = get_xsave_addr(xsave, feature);
3290 u32 size, offset, ecx, edx;
3291 cpuid_count(XSTATE_CPUID, index,
3292 &size, &offset, &ecx, &edx);
3293 if (feature == XFEATURE_MASK_PKRU)
3294 memcpy(dest + offset, &vcpu->arch.pkru,
3295 sizeof(vcpu->arch.pkru));
3297 memcpy(dest + offset, src, size);
3305 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3307 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3308 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3312 * Copy legacy XSAVE area, to avoid complications with CPUID
3313 * leaves 0 and 1 in the loop below.
3315 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3317 /* Set XSTATE_BV and possibly XCOMP_BV. */
3318 xsave->header.xfeatures = xstate_bv;
3319 if (boot_cpu_has(X86_FEATURE_XSAVES))
3320 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3323 * Copy each region from the non-compacted offset to the
3324 * possibly compacted offset.
3326 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3328 u64 feature = valid & -valid;
3329 int index = fls64(feature) - 1;
3330 void *dest = get_xsave_addr(xsave, feature);
3333 u32 size, offset, ecx, edx;
3334 cpuid_count(XSTATE_CPUID, index,
3335 &size, &offset, &ecx, &edx);
3336 if (feature == XFEATURE_MASK_PKRU)
3337 memcpy(&vcpu->arch.pkru, src + offset,
3338 sizeof(vcpu->arch.pkru));
3340 memcpy(dest, src + offset, size);
3347 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3348 struct kvm_xsave *guest_xsave)
3350 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3351 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3352 fill_xsave((u8 *) guest_xsave->region, vcpu);
3354 memcpy(guest_xsave->region,
3355 &vcpu->arch.guest_fpu.state.fxsave,
3356 sizeof(struct fxregs_state));
3357 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3358 XFEATURE_MASK_FPSSE;
3362 #define XSAVE_MXCSR_OFFSET 24
3364 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3365 struct kvm_xsave *guest_xsave)
3368 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3369 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3371 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3373 * Here we allow setting states that are not present in
3374 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3375 * with old userspace.
3377 if (xstate_bv & ~kvm_supported_xcr0() ||
3378 mxcsr & ~mxcsr_feature_mask)
3380 load_xsave(vcpu, (u8 *)guest_xsave->region);
3382 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3383 mxcsr & ~mxcsr_feature_mask)
3385 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3386 guest_xsave->region, sizeof(struct fxregs_state));
3391 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3392 struct kvm_xcrs *guest_xcrs)
3394 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3395 guest_xcrs->nr_xcrs = 0;
3399 guest_xcrs->nr_xcrs = 1;
3400 guest_xcrs->flags = 0;
3401 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3402 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3405 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3406 struct kvm_xcrs *guest_xcrs)
3410 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3413 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3416 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3417 /* Only support XCR0 currently */
3418 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3419 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3420 guest_xcrs->xcrs[i].value);
3429 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3430 * stopped by the hypervisor. This function will be called from the host only.
3431 * EINVAL is returned when the host attempts to set the flag for a guest that
3432 * does not support pv clocks.
3434 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3436 if (!vcpu->arch.pv_time_enabled)
3438 vcpu->arch.pvclock_set_guest_stopped_request = true;
3439 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3443 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3444 struct kvm_enable_cap *cap)
3450 case KVM_CAP_HYPERV_SYNIC2:
3453 case KVM_CAP_HYPERV_SYNIC:
3454 if (!irqchip_in_kernel(vcpu->kvm))
3456 return kvm_hv_activate_synic(vcpu, cap->cap ==
3457 KVM_CAP_HYPERV_SYNIC2);
3463 long kvm_arch_vcpu_ioctl(struct file *filp,
3464 unsigned int ioctl, unsigned long arg)
3466 struct kvm_vcpu *vcpu = filp->private_data;
3467 void __user *argp = (void __user *)arg;
3470 struct kvm_lapic_state *lapic;
3471 struct kvm_xsave *xsave;
3472 struct kvm_xcrs *xcrs;
3478 case KVM_GET_LAPIC: {
3480 if (!lapic_in_kernel(vcpu))
3482 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3487 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3491 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3496 case KVM_SET_LAPIC: {
3498 if (!lapic_in_kernel(vcpu))
3500 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3501 if (IS_ERR(u.lapic))
3502 return PTR_ERR(u.lapic);
3504 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3507 case KVM_INTERRUPT: {
3508 struct kvm_interrupt irq;
3511 if (copy_from_user(&irq, argp, sizeof irq))
3513 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3517 r = kvm_vcpu_ioctl_nmi(vcpu);
3521 r = kvm_vcpu_ioctl_smi(vcpu);
3524 case KVM_SET_CPUID: {
3525 struct kvm_cpuid __user *cpuid_arg = argp;
3526 struct kvm_cpuid cpuid;
3529 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3531 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3534 case KVM_SET_CPUID2: {
3535 struct kvm_cpuid2 __user *cpuid_arg = argp;
3536 struct kvm_cpuid2 cpuid;
3539 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3541 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3542 cpuid_arg->entries);
3545 case KVM_GET_CPUID2: {
3546 struct kvm_cpuid2 __user *cpuid_arg = argp;
3547 struct kvm_cpuid2 cpuid;
3550 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3552 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3553 cpuid_arg->entries);
3557 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3563 r = msr_io(vcpu, argp, do_get_msr, 1);
3566 r = msr_io(vcpu, argp, do_set_msr, 0);
3568 case KVM_TPR_ACCESS_REPORTING: {
3569 struct kvm_tpr_access_ctl tac;
3572 if (copy_from_user(&tac, argp, sizeof tac))
3574 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3578 if (copy_to_user(argp, &tac, sizeof tac))
3583 case KVM_SET_VAPIC_ADDR: {
3584 struct kvm_vapic_addr va;
3588 if (!lapic_in_kernel(vcpu))
3591 if (copy_from_user(&va, argp, sizeof va))
3593 idx = srcu_read_lock(&vcpu->kvm->srcu);
3594 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3595 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3598 case KVM_X86_SETUP_MCE: {
3602 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3604 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3607 case KVM_X86_SET_MCE: {
3608 struct kvm_x86_mce mce;
3611 if (copy_from_user(&mce, argp, sizeof mce))
3613 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3616 case KVM_GET_VCPU_EVENTS: {
3617 struct kvm_vcpu_events events;
3619 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3622 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3627 case KVM_SET_VCPU_EVENTS: {
3628 struct kvm_vcpu_events events;
3631 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3634 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3637 case KVM_GET_DEBUGREGS: {
3638 struct kvm_debugregs dbgregs;
3640 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3643 if (copy_to_user(argp, &dbgregs,
3644 sizeof(struct kvm_debugregs)))
3649 case KVM_SET_DEBUGREGS: {
3650 struct kvm_debugregs dbgregs;
3653 if (copy_from_user(&dbgregs, argp,
3654 sizeof(struct kvm_debugregs)))
3657 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3660 case KVM_GET_XSAVE: {
3661 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3666 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3669 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3674 case KVM_SET_XSAVE: {
3675 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3676 if (IS_ERR(u.xsave))
3677 return PTR_ERR(u.xsave);
3679 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3682 case KVM_GET_XCRS: {
3683 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3688 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3691 if (copy_to_user(argp, u.xcrs,
3692 sizeof(struct kvm_xcrs)))
3697 case KVM_SET_XCRS: {
3698 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3700 return PTR_ERR(u.xcrs);
3702 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3705 case KVM_SET_TSC_KHZ: {
3709 user_tsc_khz = (u32)arg;
3711 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3714 if (user_tsc_khz == 0)
3715 user_tsc_khz = tsc_khz;
3717 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3722 case KVM_GET_TSC_KHZ: {
3723 r = vcpu->arch.virtual_tsc_khz;
3726 case KVM_KVMCLOCK_CTRL: {
3727 r = kvm_set_guest_paused(vcpu);
3730 case KVM_ENABLE_CAP: {
3731 struct kvm_enable_cap cap;
3734 if (copy_from_user(&cap, argp, sizeof(cap)))
3736 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3747 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3749 return VM_FAULT_SIGBUS;
3752 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3756 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3758 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3762 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3765 kvm->arch.ept_identity_map_addr = ident_addr;
3769 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3770 u32 kvm_nr_mmu_pages)
3772 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3775 mutex_lock(&kvm->slots_lock);
3777 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3778 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3780 mutex_unlock(&kvm->slots_lock);
3784 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3786 return kvm->arch.n_max_mmu_pages;
3789 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3791 struct kvm_pic *pic = kvm->arch.vpic;
3795 switch (chip->chip_id) {
3796 case KVM_IRQCHIP_PIC_MASTER:
3797 memcpy(&chip->chip.pic, &pic->pics[0],
3798 sizeof(struct kvm_pic_state));
3800 case KVM_IRQCHIP_PIC_SLAVE:
3801 memcpy(&chip->chip.pic, &pic->pics[1],
3802 sizeof(struct kvm_pic_state));
3804 case KVM_IRQCHIP_IOAPIC:
3805 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3814 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3816 struct kvm_pic *pic = kvm->arch.vpic;
3820 switch (chip->chip_id) {
3821 case KVM_IRQCHIP_PIC_MASTER:
3822 spin_lock(&pic->lock);
3823 memcpy(&pic->pics[0], &chip->chip.pic,
3824 sizeof(struct kvm_pic_state));
3825 spin_unlock(&pic->lock);
3827 case KVM_IRQCHIP_PIC_SLAVE:
3828 spin_lock(&pic->lock);
3829 memcpy(&pic->pics[1], &chip->chip.pic,
3830 sizeof(struct kvm_pic_state));
3831 spin_unlock(&pic->lock);
3833 case KVM_IRQCHIP_IOAPIC:
3834 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3840 kvm_pic_update_irq(pic);
3844 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3846 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3848 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3850 mutex_lock(&kps->lock);
3851 memcpy(ps, &kps->channels, sizeof(*ps));
3852 mutex_unlock(&kps->lock);
3856 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3859 struct kvm_pit *pit = kvm->arch.vpit;
3861 mutex_lock(&pit->pit_state.lock);
3862 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3863 for (i = 0; i < 3; i++)
3864 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3865 mutex_unlock(&pit->pit_state.lock);
3869 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3871 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3872 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3873 sizeof(ps->channels));
3874 ps->flags = kvm->arch.vpit->pit_state.flags;
3875 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3876 memset(&ps->reserved, 0, sizeof(ps->reserved));
3880 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3884 u32 prev_legacy, cur_legacy;
3885 struct kvm_pit *pit = kvm->arch.vpit;
3887 mutex_lock(&pit->pit_state.lock);
3888 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3889 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3890 if (!prev_legacy && cur_legacy)
3892 memcpy(&pit->pit_state.channels, &ps->channels,
3893 sizeof(pit->pit_state.channels));
3894 pit->pit_state.flags = ps->flags;
3895 for (i = 0; i < 3; i++)
3896 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3898 mutex_unlock(&pit->pit_state.lock);
3902 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3903 struct kvm_reinject_control *control)
3905 struct kvm_pit *pit = kvm->arch.vpit;
3910 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3911 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3912 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3914 mutex_lock(&pit->pit_state.lock);
3915 kvm_pit_set_reinject(pit, control->pit_reinject);
3916 mutex_unlock(&pit->pit_state.lock);
3922 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3923 * @kvm: kvm instance
3924 * @log: slot id and address to which we copy the log
3926 * Steps 1-4 below provide general overview of dirty page logging. See
3927 * kvm_get_dirty_log_protect() function description for additional details.
3929 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3930 * always flush the TLB (step 4) even if previous step failed and the dirty
3931 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3932 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3933 * writes will be marked dirty for next log read.
3935 * 1. Take a snapshot of the bit and clear it if needed.
3936 * 2. Write protect the corresponding page.
3937 * 3. Copy the snapshot to the userspace.
3938 * 4. Flush TLB's if needed.
3940 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3942 bool is_dirty = false;
3945 mutex_lock(&kvm->slots_lock);
3948 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3950 if (kvm_x86_ops->flush_log_dirty)
3951 kvm_x86_ops->flush_log_dirty(kvm);
3953 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3956 * All the TLBs can be flushed out of mmu lock, see the comments in
3957 * kvm_mmu_slot_remove_write_access().
3959 lockdep_assert_held(&kvm->slots_lock);
3961 kvm_flush_remote_tlbs(kvm);
3963 mutex_unlock(&kvm->slots_lock);
3967 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3970 if (!irqchip_in_kernel(kvm))
3973 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3974 irq_event->irq, irq_event->level,
3979 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3980 struct kvm_enable_cap *cap)
3988 case KVM_CAP_DISABLE_QUIRKS:
3989 kvm->arch.disabled_quirks = cap->args[0];
3992 case KVM_CAP_SPLIT_IRQCHIP: {
3993 mutex_lock(&kvm->lock);
3995 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3996 goto split_irqchip_unlock;
3998 if (irqchip_in_kernel(kvm))
3999 goto split_irqchip_unlock;
4000 if (kvm->created_vcpus)
4001 goto split_irqchip_unlock;
4002 r = kvm_setup_empty_irq_routing(kvm);
4004 goto split_irqchip_unlock;
4005 /* Pairs with irqchip_in_kernel. */
4007 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4008 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4010 split_irqchip_unlock:
4011 mutex_unlock(&kvm->lock);
4014 case KVM_CAP_X2APIC_API:
4016 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4019 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4020 kvm->arch.x2apic_format = true;
4021 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4022 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4033 long kvm_arch_vm_ioctl(struct file *filp,
4034 unsigned int ioctl, unsigned long arg)
4036 struct kvm *kvm = filp->private_data;
4037 void __user *argp = (void __user *)arg;
4040 * This union makes it completely explicit to gcc-3.x
4041 * that these two variables' stack usage should be
4042 * combined, not added together.
4045 struct kvm_pit_state ps;
4046 struct kvm_pit_state2 ps2;
4047 struct kvm_pit_config pit_config;
4051 case KVM_SET_TSS_ADDR:
4052 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4054 case KVM_SET_IDENTITY_MAP_ADDR: {
4057 mutex_lock(&kvm->lock);
4059 if (kvm->created_vcpus)
4060 goto set_identity_unlock;
4062 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4063 goto set_identity_unlock;
4064 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4065 set_identity_unlock:
4066 mutex_unlock(&kvm->lock);
4069 case KVM_SET_NR_MMU_PAGES:
4070 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4072 case KVM_GET_NR_MMU_PAGES:
4073 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4075 case KVM_CREATE_IRQCHIP: {
4076 mutex_lock(&kvm->lock);
4079 if (irqchip_in_kernel(kvm))
4080 goto create_irqchip_unlock;
4083 if (kvm->created_vcpus)
4084 goto create_irqchip_unlock;
4086 r = kvm_pic_init(kvm);
4088 goto create_irqchip_unlock;
4090 r = kvm_ioapic_init(kvm);
4092 kvm_pic_destroy(kvm);
4093 goto create_irqchip_unlock;
4096 r = kvm_setup_default_irq_routing(kvm);
4098 kvm_ioapic_destroy(kvm);
4099 kvm_pic_destroy(kvm);
4100 goto create_irqchip_unlock;
4102 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4104 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4105 create_irqchip_unlock:
4106 mutex_unlock(&kvm->lock);
4109 case KVM_CREATE_PIT:
4110 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4112 case KVM_CREATE_PIT2:
4114 if (copy_from_user(&u.pit_config, argp,
4115 sizeof(struct kvm_pit_config)))
4118 mutex_lock(&kvm->lock);
4121 goto create_pit_unlock;
4123 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4127 mutex_unlock(&kvm->lock);
4129 case KVM_GET_IRQCHIP: {
4130 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4131 struct kvm_irqchip *chip;
4133 chip = memdup_user(argp, sizeof(*chip));
4140 if (!irqchip_kernel(kvm))
4141 goto get_irqchip_out;
4142 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4144 goto get_irqchip_out;
4146 if (copy_to_user(argp, chip, sizeof *chip))
4147 goto get_irqchip_out;
4153 case KVM_SET_IRQCHIP: {
4154 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4155 struct kvm_irqchip *chip;
4157 chip = memdup_user(argp, sizeof(*chip));
4164 if (!irqchip_kernel(kvm))
4165 goto set_irqchip_out;
4166 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4168 goto set_irqchip_out;
4176 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4179 if (!kvm->arch.vpit)
4181 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4185 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4192 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4195 if (!kvm->arch.vpit)
4197 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4200 case KVM_GET_PIT2: {
4202 if (!kvm->arch.vpit)
4204 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4208 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4213 case KVM_SET_PIT2: {
4215 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4218 if (!kvm->arch.vpit)
4220 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4223 case KVM_REINJECT_CONTROL: {
4224 struct kvm_reinject_control control;
4226 if (copy_from_user(&control, argp, sizeof(control)))
4228 r = kvm_vm_ioctl_reinject(kvm, &control);
4231 case KVM_SET_BOOT_CPU_ID:
4233 mutex_lock(&kvm->lock);
4234 if (kvm->created_vcpus)
4237 kvm->arch.bsp_vcpu_id = arg;
4238 mutex_unlock(&kvm->lock);
4240 case KVM_XEN_HVM_CONFIG: {
4241 struct kvm_xen_hvm_config xhc;
4243 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4248 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4252 case KVM_SET_CLOCK: {
4253 struct kvm_clock_data user_ns;
4257 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4266 * TODO: userspace has to take care of races with VCPU_RUN, so
4267 * kvm_gen_update_masterclock() can be cut down to locked
4268 * pvclock_update_vm_gtod_copy().
4270 kvm_gen_update_masterclock(kvm);
4271 now_ns = get_kvmclock_ns(kvm);
4272 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4273 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4276 case KVM_GET_CLOCK: {
4277 struct kvm_clock_data user_ns;
4280 now_ns = get_kvmclock_ns(kvm);
4281 user_ns.clock = now_ns;
4282 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4283 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4286 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4291 case KVM_ENABLE_CAP: {
4292 struct kvm_enable_cap cap;
4295 if (copy_from_user(&cap, argp, sizeof(cap)))
4297 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4307 static void kvm_init_msr_list(void)
4312 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4313 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4317 * Even MSRs that are valid in the host may not be exposed
4318 * to the guests in some cases.
4320 switch (msrs_to_save[i]) {
4321 case MSR_IA32_BNDCFGS:
4322 if (!kvm_x86_ops->mpx_supported())
4326 if (!kvm_x86_ops->rdtscp_supported())
4334 msrs_to_save[j] = msrs_to_save[i];
4337 num_msrs_to_save = j;
4339 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4340 switch (emulated_msrs[i]) {
4341 case MSR_IA32_SMBASE:
4342 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4350 emulated_msrs[j] = emulated_msrs[i];
4353 num_emulated_msrs = j;
4356 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4364 if (!(lapic_in_kernel(vcpu) &&
4365 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4366 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4377 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4384 if (!(lapic_in_kernel(vcpu) &&
4385 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4387 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4389 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4399 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4400 struct kvm_segment *var, int seg)
4402 kvm_x86_ops->set_segment(vcpu, var, seg);
4405 void kvm_get_segment(struct kvm_vcpu *vcpu,
4406 struct kvm_segment *var, int seg)
4408 kvm_x86_ops->get_segment(vcpu, var, seg);
4411 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4412 struct x86_exception *exception)
4416 BUG_ON(!mmu_is_nested(vcpu));
4418 /* NPT walks are always user-walks */
4419 access |= PFERR_USER_MASK;
4420 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4425 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4426 struct x86_exception *exception)
4428 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4429 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4432 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4433 struct x86_exception *exception)
4435 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4436 access |= PFERR_FETCH_MASK;
4437 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4440 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4441 struct x86_exception *exception)
4443 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4444 access |= PFERR_WRITE_MASK;
4445 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4448 /* uses this to access any guest's mapped memory without checking CPL */
4449 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4450 struct x86_exception *exception)
4452 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4455 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4456 struct kvm_vcpu *vcpu, u32 access,
4457 struct x86_exception *exception)
4460 int r = X86EMUL_CONTINUE;
4463 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4465 unsigned offset = addr & (PAGE_SIZE-1);
4466 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4469 if (gpa == UNMAPPED_GVA)
4470 return X86EMUL_PROPAGATE_FAULT;
4471 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4474 r = X86EMUL_IO_NEEDED;
4486 /* used for instruction fetching */
4487 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4488 gva_t addr, void *val, unsigned int bytes,
4489 struct x86_exception *exception)
4491 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4492 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4496 /* Inline kvm_read_guest_virt_helper for speed. */
4497 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4499 if (unlikely(gpa == UNMAPPED_GVA))
4500 return X86EMUL_PROPAGATE_FAULT;
4502 offset = addr & (PAGE_SIZE-1);
4503 if (WARN_ON(offset + bytes > PAGE_SIZE))
4504 bytes = (unsigned)PAGE_SIZE - offset;
4505 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4507 if (unlikely(ret < 0))
4508 return X86EMUL_IO_NEEDED;
4510 return X86EMUL_CONTINUE;
4513 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4514 gva_t addr, void *val, unsigned int bytes,
4515 struct x86_exception *exception)
4517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4518 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4520 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4523 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4525 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4526 gva_t addr, void *val, unsigned int bytes,
4527 struct x86_exception *exception)
4529 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4530 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4533 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4534 unsigned long addr, void *val, unsigned int bytes)
4536 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4537 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4539 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4542 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4543 gva_t addr, void *val,
4545 struct x86_exception *exception)
4547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4549 int r = X86EMUL_CONTINUE;
4552 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4555 unsigned offset = addr & (PAGE_SIZE-1);
4556 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4559 if (gpa == UNMAPPED_GVA)
4560 return X86EMUL_PROPAGATE_FAULT;
4561 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4563 r = X86EMUL_IO_NEEDED;
4574 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4576 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4577 gpa_t gpa, bool write)
4579 /* For APIC access vmexit */
4580 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4583 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4584 trace_vcpu_match_mmio(gva, gpa, write, true);
4591 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4592 gpa_t *gpa, struct x86_exception *exception,
4595 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4596 | (write ? PFERR_WRITE_MASK : 0);
4599 * currently PKRU is only applied to ept enabled guest so
4600 * there is no pkey in EPT page table for L1 guest or EPT
4601 * shadow page table for L2 guest.
4603 if (vcpu_match_mmio_gva(vcpu, gva)
4604 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4605 vcpu->arch.access, 0, access)) {
4606 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4607 (gva & (PAGE_SIZE - 1));
4608 trace_vcpu_match_mmio(gva, *gpa, write, false);
4612 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4614 if (*gpa == UNMAPPED_GVA)
4617 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4620 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4621 const void *val, int bytes)
4625 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4628 kvm_page_track_write(vcpu, gpa, val, bytes);
4632 struct read_write_emulator_ops {
4633 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4635 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4636 void *val, int bytes);
4637 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4638 int bytes, void *val);
4639 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4640 void *val, int bytes);
4644 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4646 if (vcpu->mmio_read_completed) {
4647 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4648 vcpu->mmio_fragments[0].gpa, val);
4649 vcpu->mmio_read_completed = 0;
4656 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4657 void *val, int bytes)
4659 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4662 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4663 void *val, int bytes)
4665 return emulator_write_phys(vcpu, gpa, val, bytes);
4668 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4670 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
4671 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4674 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4675 void *val, int bytes)
4677 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
4678 return X86EMUL_IO_NEEDED;
4681 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4682 void *val, int bytes)
4684 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4686 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4687 return X86EMUL_CONTINUE;
4690 static const struct read_write_emulator_ops read_emultor = {
4691 .read_write_prepare = read_prepare,
4692 .read_write_emulate = read_emulate,
4693 .read_write_mmio = vcpu_mmio_read,
4694 .read_write_exit_mmio = read_exit_mmio,
4697 static const struct read_write_emulator_ops write_emultor = {
4698 .read_write_emulate = write_emulate,
4699 .read_write_mmio = write_mmio,
4700 .read_write_exit_mmio = write_exit_mmio,
4704 static int emulator_read_write_onepage(unsigned long addr, void *val,
4706 struct x86_exception *exception,
4707 struct kvm_vcpu *vcpu,
4708 const struct read_write_emulator_ops *ops)
4712 bool write = ops->write;
4713 struct kvm_mmio_fragment *frag;
4714 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4717 * If the exit was due to a NPF we may already have a GPA.
4718 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4719 * Note, this cannot be used on string operations since string
4720 * operation using rep will only have the initial GPA from the NPF
4723 if (vcpu->arch.gpa_available &&
4724 emulator_can_use_gpa(ctxt) &&
4725 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4726 gpa = vcpu->arch.gpa_val;
4727 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4729 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4731 return X86EMUL_PROPAGATE_FAULT;
4734 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
4735 return X86EMUL_CONTINUE;
4738 * Is this MMIO handled locally?
4740 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4741 if (handled == bytes)
4742 return X86EMUL_CONTINUE;
4748 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4749 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4753 return X86EMUL_CONTINUE;
4756 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4758 void *val, unsigned int bytes,
4759 struct x86_exception *exception,
4760 const struct read_write_emulator_ops *ops)
4762 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4766 if (ops->read_write_prepare &&
4767 ops->read_write_prepare(vcpu, val, bytes))
4768 return X86EMUL_CONTINUE;
4770 vcpu->mmio_nr_fragments = 0;
4772 /* Crossing a page boundary? */
4773 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4776 now = -addr & ~PAGE_MASK;
4777 rc = emulator_read_write_onepage(addr, val, now, exception,
4780 if (rc != X86EMUL_CONTINUE)
4783 if (ctxt->mode != X86EMUL_MODE_PROT64)
4789 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4791 if (rc != X86EMUL_CONTINUE)
4794 if (!vcpu->mmio_nr_fragments)
4797 gpa = vcpu->mmio_fragments[0].gpa;
4799 vcpu->mmio_needed = 1;
4800 vcpu->mmio_cur_fragment = 0;
4802 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4803 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4804 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4805 vcpu->run->mmio.phys_addr = gpa;
4807 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4810 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4814 struct x86_exception *exception)
4816 return emulator_read_write(ctxt, addr, val, bytes,
4817 exception, &read_emultor);
4820 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4824 struct x86_exception *exception)
4826 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4827 exception, &write_emultor);
4830 #define CMPXCHG_TYPE(t, ptr, old, new) \
4831 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4833 #ifdef CONFIG_X86_64
4834 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4836 # define CMPXCHG64(ptr, old, new) \
4837 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4840 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4845 struct x86_exception *exception)
4847 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4853 /* guests cmpxchg8b have to be emulated atomically */
4854 if (bytes > 8 || (bytes & (bytes - 1)))
4857 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4859 if (gpa == UNMAPPED_GVA ||
4860 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4863 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4866 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4867 if (is_error_page(page))
4870 kaddr = kmap_atomic(page);
4871 kaddr += offset_in_page(gpa);
4874 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4877 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4880 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4883 exchanged = CMPXCHG64(kaddr, old, new);
4888 kunmap_atomic(kaddr);
4889 kvm_release_page_dirty(page);
4892 return X86EMUL_CMPXCHG_FAILED;
4894 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4895 kvm_page_track_write(vcpu, gpa, new, bytes);
4897 return X86EMUL_CONTINUE;
4900 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4902 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4905 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4909 for (i = 0; i < vcpu->arch.pio.count; i++) {
4910 if (vcpu->arch.pio.in)
4911 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4912 vcpu->arch.pio.size, pd);
4914 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4915 vcpu->arch.pio.port, vcpu->arch.pio.size,
4919 pd += vcpu->arch.pio.size;
4924 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4925 unsigned short port, void *val,
4926 unsigned int count, bool in)
4928 vcpu->arch.pio.port = port;
4929 vcpu->arch.pio.in = in;
4930 vcpu->arch.pio.count = count;
4931 vcpu->arch.pio.size = size;
4933 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4934 vcpu->arch.pio.count = 0;
4938 vcpu->run->exit_reason = KVM_EXIT_IO;
4939 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4940 vcpu->run->io.size = size;
4941 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4942 vcpu->run->io.count = count;
4943 vcpu->run->io.port = port;
4948 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4949 int size, unsigned short port, void *val,
4952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4955 if (vcpu->arch.pio.count)
4958 memset(vcpu->arch.pio_data, 0, size * count);
4960 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4963 memcpy(val, vcpu->arch.pio_data, size * count);
4964 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4965 vcpu->arch.pio.count = 0;
4972 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4973 int size, unsigned short port,
4974 const void *val, unsigned int count)
4976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4978 memcpy(vcpu->arch.pio_data, val, size * count);
4979 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4980 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4983 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4985 return kvm_x86_ops->get_segment_base(vcpu, seg);
4988 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4990 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4993 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4995 if (!need_emulate_wbinvd(vcpu))
4996 return X86EMUL_CONTINUE;
4998 if (kvm_x86_ops->has_wbinvd_exit()) {
4999 int cpu = get_cpu();
5001 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5002 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5003 wbinvd_ipi, NULL, 1);
5005 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5008 return X86EMUL_CONTINUE;
5011 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5013 kvm_emulate_wbinvd_noskip(vcpu);
5014 return kvm_skip_emulated_instruction(vcpu);
5016 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5020 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5022 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5025 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5026 unsigned long *dest)
5028 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5031 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5032 unsigned long value)
5035 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5038 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5040 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5043 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5045 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5046 unsigned long value;
5050 value = kvm_read_cr0(vcpu);
5053 value = vcpu->arch.cr2;
5056 value = kvm_read_cr3(vcpu);
5059 value = kvm_read_cr4(vcpu);
5062 value = kvm_get_cr8(vcpu);
5065 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5072 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5074 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5079 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5082 vcpu->arch.cr2 = val;
5085 res = kvm_set_cr3(vcpu, val);
5088 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5091 res = kvm_set_cr8(vcpu, val);
5094 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5101 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5103 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5106 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5108 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5111 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5113 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5116 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5118 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5121 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5123 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5126 static unsigned long emulator_get_cached_segment_base(
5127 struct x86_emulate_ctxt *ctxt, int seg)
5129 return get_segment_base(emul_to_vcpu(ctxt), seg);
5132 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5133 struct desc_struct *desc, u32 *base3,
5136 struct kvm_segment var;
5138 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5139 *selector = var.selector;
5142 memset(desc, 0, sizeof(*desc));
5150 set_desc_limit(desc, var.limit);
5151 set_desc_base(desc, (unsigned long)var.base);
5152 #ifdef CONFIG_X86_64
5154 *base3 = var.base >> 32;
5156 desc->type = var.type;
5158 desc->dpl = var.dpl;
5159 desc->p = var.present;
5160 desc->avl = var.avl;
5168 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5169 struct desc_struct *desc, u32 base3,
5172 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5173 struct kvm_segment var;
5175 var.selector = selector;
5176 var.base = get_desc_base(desc);
5177 #ifdef CONFIG_X86_64
5178 var.base |= ((u64)base3) << 32;
5180 var.limit = get_desc_limit(desc);
5182 var.limit = (var.limit << 12) | 0xfff;
5183 var.type = desc->type;
5184 var.dpl = desc->dpl;
5189 var.avl = desc->avl;
5190 var.present = desc->p;
5191 var.unusable = !var.present;
5194 kvm_set_segment(vcpu, &var, seg);
5198 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5199 u32 msr_index, u64 *pdata)
5201 struct msr_data msr;
5204 msr.index = msr_index;
5205 msr.host_initiated = false;
5206 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5214 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5215 u32 msr_index, u64 data)
5217 struct msr_data msr;
5220 msr.index = msr_index;
5221 msr.host_initiated = false;
5222 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5225 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5227 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5229 return vcpu->arch.smbase;
5232 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5234 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5236 vcpu->arch.smbase = smbase;
5239 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5242 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5245 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5246 u32 pmc, u64 *pdata)
5248 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5251 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5253 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5256 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5257 struct x86_instruction_info *info,
5258 enum x86_intercept_stage stage)
5260 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5263 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5264 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5266 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5269 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5271 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5274 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5276 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5279 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5281 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5284 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5286 return emul_to_vcpu(ctxt)->arch.hflags;
5289 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5291 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5294 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5296 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5299 static const struct x86_emulate_ops emulate_ops = {
5300 .read_gpr = emulator_read_gpr,
5301 .write_gpr = emulator_write_gpr,
5302 .read_std = kvm_read_guest_virt_system,
5303 .write_std = kvm_write_guest_virt_system,
5304 .read_phys = kvm_read_guest_phys_system,
5305 .fetch = kvm_fetch_guest_virt,
5306 .read_emulated = emulator_read_emulated,
5307 .write_emulated = emulator_write_emulated,
5308 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5309 .invlpg = emulator_invlpg,
5310 .pio_in_emulated = emulator_pio_in_emulated,
5311 .pio_out_emulated = emulator_pio_out_emulated,
5312 .get_segment = emulator_get_segment,
5313 .set_segment = emulator_set_segment,
5314 .get_cached_segment_base = emulator_get_cached_segment_base,
5315 .get_gdt = emulator_get_gdt,
5316 .get_idt = emulator_get_idt,
5317 .set_gdt = emulator_set_gdt,
5318 .set_idt = emulator_set_idt,
5319 .get_cr = emulator_get_cr,
5320 .set_cr = emulator_set_cr,
5321 .cpl = emulator_get_cpl,
5322 .get_dr = emulator_get_dr,
5323 .set_dr = emulator_set_dr,
5324 .get_smbase = emulator_get_smbase,
5325 .set_smbase = emulator_set_smbase,
5326 .set_msr = emulator_set_msr,
5327 .get_msr = emulator_get_msr,
5328 .check_pmc = emulator_check_pmc,
5329 .read_pmc = emulator_read_pmc,
5330 .halt = emulator_halt,
5331 .wbinvd = emulator_wbinvd,
5332 .fix_hypercall = emulator_fix_hypercall,
5333 .intercept = emulator_intercept,
5334 .get_cpuid = emulator_get_cpuid,
5335 .set_nmi_mask = emulator_set_nmi_mask,
5336 .get_hflags = emulator_get_hflags,
5337 .set_hflags = emulator_set_hflags,
5338 .pre_leave_smm = emulator_pre_leave_smm,
5341 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5343 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5345 * an sti; sti; sequence only disable interrupts for the first
5346 * instruction. So, if the last instruction, be it emulated or
5347 * not, left the system with the INT_STI flag enabled, it
5348 * means that the last instruction is an sti. We should not
5349 * leave the flag on in this case. The same goes for mov ss
5351 if (int_shadow & mask)
5353 if (unlikely(int_shadow || mask)) {
5354 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5356 kvm_make_request(KVM_REQ_EVENT, vcpu);
5360 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5362 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5363 if (ctxt->exception.vector == PF_VECTOR)
5364 return kvm_propagate_fault(vcpu, &ctxt->exception);
5366 if (ctxt->exception.error_code_valid)
5367 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5368 ctxt->exception.error_code);
5370 kvm_queue_exception(vcpu, ctxt->exception.vector);
5374 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5376 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5379 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5381 ctxt->eflags = kvm_get_rflags(vcpu);
5382 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5384 ctxt->eip = kvm_rip_read(vcpu);
5385 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5386 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5387 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5388 cs_db ? X86EMUL_MODE_PROT32 :
5389 X86EMUL_MODE_PROT16;
5390 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5391 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5392 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5394 init_decode_cache(ctxt);
5395 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5398 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5400 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5403 init_emulate_ctxt(vcpu);
5407 ctxt->_eip = ctxt->eip + inc_eip;
5408 ret = emulate_int_real(ctxt, irq);
5410 if (ret != X86EMUL_CONTINUE)
5411 return EMULATE_FAIL;
5413 ctxt->eip = ctxt->_eip;
5414 kvm_rip_write(vcpu, ctxt->eip);
5415 kvm_set_rflags(vcpu, ctxt->eflags);
5417 if (irq == NMI_VECTOR)
5418 vcpu->arch.nmi_pending = 0;
5420 vcpu->arch.interrupt.pending = false;
5422 return EMULATE_DONE;
5424 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5426 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5428 int r = EMULATE_DONE;
5430 ++vcpu->stat.insn_emulation_fail;
5431 trace_kvm_emulate_insn_failed(vcpu);
5432 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5433 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5434 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5435 vcpu->run->internal.ndata = 0;
5436 r = EMULATE_USER_EXIT;
5438 kvm_queue_exception(vcpu, UD_VECTOR);
5443 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5444 bool write_fault_to_shadow_pgtable,
5450 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5453 if (!vcpu->arch.mmu.direct_map) {
5455 * Write permission should be allowed since only
5456 * write access need to be emulated.
5458 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5461 * If the mapping is invalid in guest, let cpu retry
5462 * it to generate fault.
5464 if (gpa == UNMAPPED_GVA)
5469 * Do not retry the unhandleable instruction if it faults on the
5470 * readonly host memory, otherwise it will goto a infinite loop:
5471 * retry instruction -> write #PF -> emulation fail -> retry
5472 * instruction -> ...
5474 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5477 * If the instruction failed on the error pfn, it can not be fixed,
5478 * report the error to userspace.
5480 if (is_error_noslot_pfn(pfn))
5483 kvm_release_pfn_clean(pfn);
5485 /* The instructions are well-emulated on direct mmu. */
5486 if (vcpu->arch.mmu.direct_map) {
5487 unsigned int indirect_shadow_pages;
5489 spin_lock(&vcpu->kvm->mmu_lock);
5490 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5491 spin_unlock(&vcpu->kvm->mmu_lock);
5493 if (indirect_shadow_pages)
5494 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5500 * if emulation was due to access to shadowed page table
5501 * and it failed try to unshadow page and re-enter the
5502 * guest to let CPU execute the instruction.
5504 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5507 * If the access faults on its page table, it can not
5508 * be fixed by unprotecting shadow page and it should
5509 * be reported to userspace.
5511 return !write_fault_to_shadow_pgtable;
5514 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5515 unsigned long cr2, int emulation_type)
5517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5518 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5520 last_retry_eip = vcpu->arch.last_retry_eip;
5521 last_retry_addr = vcpu->arch.last_retry_addr;
5524 * If the emulation is caused by #PF and it is non-page_table
5525 * writing instruction, it means the VM-EXIT is caused by shadow
5526 * page protected, we can zap the shadow page and retry this
5527 * instruction directly.
5529 * Note: if the guest uses a non-page-table modifying instruction
5530 * on the PDE that points to the instruction, then we will unmap
5531 * the instruction and go to an infinite loop. So, we cache the
5532 * last retried eip and the last fault address, if we meet the eip
5533 * and the address again, we can break out of the potential infinite
5536 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5538 if (!(emulation_type & EMULTYPE_RETRY))
5541 if (x86_page_table_writing_insn(ctxt))
5544 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5547 vcpu->arch.last_retry_eip = ctxt->eip;
5548 vcpu->arch.last_retry_addr = cr2;
5550 if (!vcpu->arch.mmu.direct_map)
5551 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5553 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5558 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5559 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5561 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5563 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5564 /* This is a good place to trace that we are exiting SMM. */
5565 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5567 /* Process a latched INIT or SMI, if any. */
5568 kvm_make_request(KVM_REQ_EVENT, vcpu);
5571 kvm_mmu_reset_context(vcpu);
5574 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5576 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5578 vcpu->arch.hflags = emul_flags;
5580 if (changed & HF_SMM_MASK)
5581 kvm_smm_changed(vcpu);
5584 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5593 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5594 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5599 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5601 struct kvm_run *kvm_run = vcpu->run;
5603 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5604 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5605 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5606 kvm_run->debug.arch.exception = DB_VECTOR;
5607 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5608 *r = EMULATE_USER_EXIT;
5611 * "Certain debug exceptions may clear bit 0-3. The
5612 * remaining contents of the DR6 register are never
5613 * cleared by the processor".
5615 vcpu->arch.dr6 &= ~15;
5616 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5617 kvm_queue_exception(vcpu, DB_VECTOR);
5621 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5623 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5624 int r = EMULATE_DONE;
5626 kvm_x86_ops->skip_emulated_instruction(vcpu);
5629 * rflags is the old, "raw" value of the flags. The new value has
5630 * not been saved yet.
5632 * This is correct even for TF set by the guest, because "the
5633 * processor will not generate this exception after the instruction
5634 * that sets the TF flag".
5636 if (unlikely(rflags & X86_EFLAGS_TF))
5637 kvm_vcpu_do_singlestep(vcpu, &r);
5638 return r == EMULATE_DONE;
5640 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5642 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5644 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5645 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5646 struct kvm_run *kvm_run = vcpu->run;
5647 unsigned long eip = kvm_get_linear_rip(vcpu);
5648 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5649 vcpu->arch.guest_debug_dr7,
5653 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5654 kvm_run->debug.arch.pc = eip;
5655 kvm_run->debug.arch.exception = DB_VECTOR;
5656 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5657 *r = EMULATE_USER_EXIT;
5662 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5663 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5664 unsigned long eip = kvm_get_linear_rip(vcpu);
5665 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5670 vcpu->arch.dr6 &= ~15;
5671 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5672 kvm_queue_exception(vcpu, DB_VECTOR);
5681 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5688 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5689 bool writeback = true;
5690 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5693 * Clear write_fault_to_shadow_pgtable here to ensure it is
5696 vcpu->arch.write_fault_to_shadow_pgtable = false;
5697 kvm_clear_exception_queue(vcpu);
5699 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5700 init_emulate_ctxt(vcpu);
5703 * We will reenter on the same instruction since
5704 * we do not set complete_userspace_io. This does not
5705 * handle watchpoints yet, those would be handled in
5708 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5711 ctxt->interruptibility = 0;
5712 ctxt->have_exception = false;
5713 ctxt->exception.vector = -1;
5714 ctxt->perm_ok = false;
5716 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5718 r = x86_decode_insn(ctxt, insn, insn_len);
5720 trace_kvm_emulate_insn_start(vcpu);
5721 ++vcpu->stat.insn_emulation;
5722 if (r != EMULATION_OK) {
5723 if (emulation_type & EMULTYPE_TRAP_UD)
5724 return EMULATE_FAIL;
5725 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5727 return EMULATE_DONE;
5728 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5729 return EMULATE_DONE;
5730 if (emulation_type & EMULTYPE_SKIP)
5731 return EMULATE_FAIL;
5732 return handle_emulation_failure(vcpu);
5736 if (emulation_type & EMULTYPE_SKIP) {
5737 kvm_rip_write(vcpu, ctxt->_eip);
5738 if (ctxt->eflags & X86_EFLAGS_RF)
5739 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5740 return EMULATE_DONE;
5743 if (retry_instruction(ctxt, cr2, emulation_type))
5744 return EMULATE_DONE;
5746 /* this is needed for vmware backdoor interface to work since it
5747 changes registers values during IO operation */
5748 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5749 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5750 emulator_invalidate_register_cache(ctxt);
5754 /* Save the faulting GPA (cr2) in the address field */
5755 ctxt->exception.address = cr2;
5757 r = x86_emulate_insn(ctxt);
5759 if (r == EMULATION_INTERCEPTED)
5760 return EMULATE_DONE;
5762 if (r == EMULATION_FAILED) {
5763 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5765 return EMULATE_DONE;
5767 return handle_emulation_failure(vcpu);
5770 if (ctxt->have_exception) {
5772 if (inject_emulated_exception(vcpu))
5774 } else if (vcpu->arch.pio.count) {
5775 if (!vcpu->arch.pio.in) {
5776 /* FIXME: return into emulator if single-stepping. */
5777 vcpu->arch.pio.count = 0;
5780 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5782 r = EMULATE_USER_EXIT;
5783 } else if (vcpu->mmio_needed) {
5784 if (!vcpu->mmio_is_write)
5786 r = EMULATE_USER_EXIT;
5787 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5788 } else if (r == EMULATION_RESTART)
5794 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5795 toggle_interruptibility(vcpu, ctxt->interruptibility);
5796 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5797 kvm_rip_write(vcpu, ctxt->eip);
5798 if (r == EMULATE_DONE &&
5799 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5800 kvm_vcpu_do_singlestep(vcpu, &r);
5801 if (!ctxt->have_exception ||
5802 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5803 __kvm_set_rflags(vcpu, ctxt->eflags);
5806 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5807 * do nothing, and it will be requested again as soon as
5808 * the shadow expires. But we still need to check here,
5809 * because POPF has no interrupt shadow.
5811 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5812 kvm_make_request(KVM_REQ_EVENT, vcpu);
5814 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5818 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5820 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5822 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5823 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5824 size, port, &val, 1);
5825 /* do not return to emulator after return from userspace */
5826 vcpu->arch.pio.count = 0;
5829 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5831 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5835 /* We should only ever be called with arch.pio.count equal to 1 */
5836 BUG_ON(vcpu->arch.pio.count != 1);
5838 /* For size less than 4 we merge, else we zero extend */
5839 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5843 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5844 * the copy and tracing
5846 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5847 vcpu->arch.pio.port, &val, 1);
5848 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5853 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5858 /* For size less than 4 we merge, else we zero extend */
5859 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5861 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5864 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5868 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5872 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5874 static int kvmclock_cpu_down_prep(unsigned int cpu)
5876 __this_cpu_write(cpu_tsc_khz, 0);
5880 static void tsc_khz_changed(void *data)
5882 struct cpufreq_freqs *freq = data;
5883 unsigned long khz = 0;
5887 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5888 khz = cpufreq_quick_get(raw_smp_processor_id());
5891 __this_cpu_write(cpu_tsc_khz, khz);
5894 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5897 struct cpufreq_freqs *freq = data;
5899 struct kvm_vcpu *vcpu;
5900 int i, send_ipi = 0;
5903 * We allow guests to temporarily run on slowing clocks,
5904 * provided we notify them after, or to run on accelerating
5905 * clocks, provided we notify them before. Thus time never
5908 * However, we have a problem. We can't atomically update
5909 * the frequency of a given CPU from this function; it is
5910 * merely a notifier, which can be called from any CPU.
5911 * Changing the TSC frequency at arbitrary points in time
5912 * requires a recomputation of local variables related to
5913 * the TSC for each VCPU. We must flag these local variables
5914 * to be updated and be sure the update takes place with the
5915 * new frequency before any guests proceed.
5917 * Unfortunately, the combination of hotplug CPU and frequency
5918 * change creates an intractable locking scenario; the order
5919 * of when these callouts happen is undefined with respect to
5920 * CPU hotplug, and they can race with each other. As such,
5921 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5922 * undefined; you can actually have a CPU frequency change take
5923 * place in between the computation of X and the setting of the
5924 * variable. To protect against this problem, all updates of
5925 * the per_cpu tsc_khz variable are done in an interrupt
5926 * protected IPI, and all callers wishing to update the value
5927 * must wait for a synchronous IPI to complete (which is trivial
5928 * if the caller is on the CPU already). This establishes the
5929 * necessary total order on variable updates.
5931 * Note that because a guest time update may take place
5932 * anytime after the setting of the VCPU's request bit, the
5933 * correct TSC value must be set before the request. However,
5934 * to ensure the update actually makes it to any guest which
5935 * starts running in hardware virtualization between the set
5936 * and the acquisition of the spinlock, we must also ping the
5937 * CPU after setting the request bit.
5941 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5943 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5946 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5948 spin_lock(&kvm_lock);
5949 list_for_each_entry(kvm, &vm_list, vm_list) {
5950 kvm_for_each_vcpu(i, vcpu, kvm) {
5951 if (vcpu->cpu != freq->cpu)
5953 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5954 if (vcpu->cpu != smp_processor_id())
5958 spin_unlock(&kvm_lock);
5960 if (freq->old < freq->new && send_ipi) {
5962 * We upscale the frequency. Must make the guest
5963 * doesn't see old kvmclock values while running with
5964 * the new frequency, otherwise we risk the guest sees
5965 * time go backwards.
5967 * In case we update the frequency for another cpu
5968 * (which might be in guest context) send an interrupt
5969 * to kick the cpu out of guest context. Next time
5970 * guest context is entered kvmclock will be updated,
5971 * so the guest will not see stale values.
5973 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5978 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5979 .notifier_call = kvmclock_cpufreq_notifier
5982 static int kvmclock_cpu_online(unsigned int cpu)
5984 tsc_khz_changed(NULL);
5988 static void kvm_timer_init(void)
5990 max_tsc_khz = tsc_khz;
5992 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5993 #ifdef CONFIG_CPU_FREQ
5994 struct cpufreq_policy policy;
5997 memset(&policy, 0, sizeof(policy));
5999 cpufreq_get_policy(&policy, cpu);
6000 if (policy.cpuinfo.max_freq)
6001 max_tsc_khz = policy.cpuinfo.max_freq;
6004 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6005 CPUFREQ_TRANSITION_NOTIFIER);
6007 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6009 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6010 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6013 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6015 int kvm_is_in_guest(void)
6017 return __this_cpu_read(current_vcpu) != NULL;
6020 static int kvm_is_user_mode(void)
6024 if (__this_cpu_read(current_vcpu))
6025 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6027 return user_mode != 0;
6030 static unsigned long kvm_get_guest_ip(void)
6032 unsigned long ip = 0;
6034 if (__this_cpu_read(current_vcpu))
6035 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6040 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6041 .is_in_guest = kvm_is_in_guest,
6042 .is_user_mode = kvm_is_user_mode,
6043 .get_guest_ip = kvm_get_guest_ip,
6046 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6048 __this_cpu_write(current_vcpu, vcpu);
6050 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6052 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6054 __this_cpu_write(current_vcpu, NULL);
6056 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6058 static void kvm_set_mmio_spte_mask(void)
6061 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6064 * Set the reserved bits and the present bit of an paging-structure
6065 * entry to generate page fault with PFER.RSV = 1.
6067 /* Mask the reserved physical address bits. */
6068 mask = rsvd_bits(maxphyaddr, 51);
6070 /* Set the present bit. */
6073 #ifdef CONFIG_X86_64
6075 * If reserved bit is not supported, clear the present bit to disable
6078 if (maxphyaddr == 52)
6082 kvm_mmu_set_mmio_spte_mask(mask, mask);
6085 #ifdef CONFIG_X86_64
6086 static void pvclock_gtod_update_fn(struct work_struct *work)
6090 struct kvm_vcpu *vcpu;
6093 spin_lock(&kvm_lock);
6094 list_for_each_entry(kvm, &vm_list, vm_list)
6095 kvm_for_each_vcpu(i, vcpu, kvm)
6096 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6097 atomic_set(&kvm_guest_has_master_clock, 0);
6098 spin_unlock(&kvm_lock);
6101 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6104 * Notification about pvclock gtod data update.
6106 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6109 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6110 struct timekeeper *tk = priv;
6112 update_pvclock_gtod(tk);
6114 /* disable master clock if host does not trust, or does not
6115 * use, TSC clocksource
6117 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6118 atomic_read(&kvm_guest_has_master_clock) != 0)
6119 queue_work(system_long_wq, &pvclock_gtod_work);
6124 static struct notifier_block pvclock_gtod_notifier = {
6125 .notifier_call = pvclock_gtod_notify,
6129 int kvm_arch_init(void *opaque)
6132 struct kvm_x86_ops *ops = opaque;
6135 printk(KERN_ERR "kvm: already loaded the other module\n");
6140 if (!ops->cpu_has_kvm_support()) {
6141 printk(KERN_ERR "kvm: no hardware support\n");
6145 if (ops->disabled_by_bios()) {
6146 printk(KERN_ERR "kvm: disabled by bios\n");
6152 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6154 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6158 r = kvm_mmu_module_init();
6160 goto out_free_percpu;
6162 kvm_set_mmio_spte_mask();
6166 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6167 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6168 PT_PRESENT_MASK, 0, sme_me_mask);
6171 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6173 if (boot_cpu_has(X86_FEATURE_XSAVE))
6174 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6177 #ifdef CONFIG_X86_64
6178 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6184 free_percpu(shared_msrs);
6189 void kvm_arch_exit(void)
6192 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6194 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6195 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6196 CPUFREQ_TRANSITION_NOTIFIER);
6197 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6198 #ifdef CONFIG_X86_64
6199 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6202 kvm_mmu_module_exit();
6203 free_percpu(shared_msrs);
6206 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6208 ++vcpu->stat.halt_exits;
6209 if (lapic_in_kernel(vcpu)) {
6210 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6213 vcpu->run->exit_reason = KVM_EXIT_HLT;
6217 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6219 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6221 int ret = kvm_skip_emulated_instruction(vcpu);
6223 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6224 * KVM_EXIT_DEBUG here.
6226 return kvm_vcpu_halt(vcpu) && ret;
6228 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6230 #ifdef CONFIG_X86_64
6231 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6232 unsigned long clock_type)
6234 struct kvm_clock_pairing clock_pairing;
6239 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6240 return -KVM_EOPNOTSUPP;
6242 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6243 return -KVM_EOPNOTSUPP;
6245 clock_pairing.sec = ts.tv_sec;
6246 clock_pairing.nsec = ts.tv_nsec;
6247 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6248 clock_pairing.flags = 0;
6251 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6252 sizeof(struct kvm_clock_pairing)))
6260 * kvm_pv_kick_cpu_op: Kick a vcpu.
6262 * @apicid - apicid of vcpu to be kicked.
6264 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6266 struct kvm_lapic_irq lapic_irq;
6268 lapic_irq.shorthand = 0;
6269 lapic_irq.dest_mode = 0;
6270 lapic_irq.level = 0;
6271 lapic_irq.dest_id = apicid;
6272 lapic_irq.msi_redir_hint = false;
6274 lapic_irq.delivery_mode = APIC_DM_REMRD;
6275 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6278 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6280 vcpu->arch.apicv_active = false;
6281 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6284 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6286 unsigned long nr, a0, a1, a2, a3, ret;
6289 r = kvm_skip_emulated_instruction(vcpu);
6291 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6292 return kvm_hv_hypercall(vcpu);
6294 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6295 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6296 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6297 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6298 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6300 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6302 op_64_bit = is_64_bit_mode(vcpu);
6311 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6317 case KVM_HC_VAPIC_POLL_IRQ:
6320 case KVM_HC_KICK_CPU:
6321 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6324 #ifdef CONFIG_X86_64
6325 case KVM_HC_CLOCK_PAIRING:
6326 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6336 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6337 ++vcpu->stat.hypercalls;
6340 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6342 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6344 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6345 char instruction[3];
6346 unsigned long rip = kvm_rip_read(vcpu);
6348 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6350 return emulator_write_emulated(ctxt, rip, instruction, 3,
6354 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6356 return vcpu->run->request_interrupt_window &&
6357 likely(!pic_in_kernel(vcpu->kvm));
6360 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6362 struct kvm_run *kvm_run = vcpu->run;
6364 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6365 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6366 kvm_run->cr8 = kvm_get_cr8(vcpu);
6367 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6368 kvm_run->ready_for_interrupt_injection =
6369 pic_in_kernel(vcpu->kvm) ||
6370 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6373 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6377 if (!kvm_x86_ops->update_cr8_intercept)
6380 if (!lapic_in_kernel(vcpu))
6383 if (vcpu->arch.apicv_active)
6386 if (!vcpu->arch.apic->vapic_addr)
6387 max_irr = kvm_lapic_find_highest_irr(vcpu);
6394 tpr = kvm_lapic_get_cr8(vcpu);
6396 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6399 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6403 /* try to reinject previous events if any */
6404 if (vcpu->arch.exception.injected) {
6405 kvm_x86_ops->queue_exception(vcpu);
6410 * Exceptions must be injected immediately, or the exception
6411 * frame will have the address of the NMI or interrupt handler.
6413 if (!vcpu->arch.exception.pending) {
6414 if (vcpu->arch.nmi_injected) {
6415 kvm_x86_ops->set_nmi(vcpu);
6419 if (vcpu->arch.interrupt.pending) {
6420 kvm_x86_ops->set_irq(vcpu);
6425 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6426 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6431 /* try to inject new event if pending */
6432 if (vcpu->arch.exception.pending) {
6433 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6434 vcpu->arch.exception.has_error_code,
6435 vcpu->arch.exception.error_code);
6437 vcpu->arch.exception.pending = false;
6438 vcpu->arch.exception.injected = true;
6440 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6441 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6444 if (vcpu->arch.exception.nr == DB_VECTOR &&
6445 (vcpu->arch.dr7 & DR7_GD)) {
6446 vcpu->arch.dr7 &= ~DR7_GD;
6447 kvm_update_dr7(vcpu);
6450 kvm_x86_ops->queue_exception(vcpu);
6451 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
6452 vcpu->arch.smi_pending = false;
6454 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6455 --vcpu->arch.nmi_pending;
6456 vcpu->arch.nmi_injected = true;
6457 kvm_x86_ops->set_nmi(vcpu);
6458 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6460 * Because interrupts can be injected asynchronously, we are
6461 * calling check_nested_events again here to avoid a race condition.
6462 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6463 * proposal and current concerns. Perhaps we should be setting
6464 * KVM_REQ_EVENT only on certain events and not unconditionally?
6466 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6467 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6471 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6472 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6474 kvm_x86_ops->set_irq(vcpu);
6481 static void process_nmi(struct kvm_vcpu *vcpu)
6486 * x86 is limited to one NMI running, and one NMI pending after it.
6487 * If an NMI is already in progress, limit further NMIs to just one.
6488 * Otherwise, allow two (and we'll inject the first one immediately).
6490 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6493 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6494 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6495 kvm_make_request(KVM_REQ_EVENT, vcpu);
6498 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6501 flags |= seg->g << 23;
6502 flags |= seg->db << 22;
6503 flags |= seg->l << 21;
6504 flags |= seg->avl << 20;
6505 flags |= seg->present << 15;
6506 flags |= seg->dpl << 13;
6507 flags |= seg->s << 12;
6508 flags |= seg->type << 8;
6512 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6514 struct kvm_segment seg;
6517 kvm_get_segment(vcpu, &seg, n);
6518 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6521 offset = 0x7f84 + n * 12;
6523 offset = 0x7f2c + (n - 3) * 12;
6525 put_smstate(u32, buf, offset + 8, seg.base);
6526 put_smstate(u32, buf, offset + 4, seg.limit);
6527 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6530 #ifdef CONFIG_X86_64
6531 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6533 struct kvm_segment seg;
6537 kvm_get_segment(vcpu, &seg, n);
6538 offset = 0x7e00 + n * 16;
6540 flags = enter_smm_get_segment_flags(&seg) >> 8;
6541 put_smstate(u16, buf, offset, seg.selector);
6542 put_smstate(u16, buf, offset + 2, flags);
6543 put_smstate(u32, buf, offset + 4, seg.limit);
6544 put_smstate(u64, buf, offset + 8, seg.base);
6548 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6551 struct kvm_segment seg;
6555 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6556 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6557 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6558 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6560 for (i = 0; i < 8; i++)
6561 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6563 kvm_get_dr(vcpu, 6, &val);
6564 put_smstate(u32, buf, 0x7fcc, (u32)val);
6565 kvm_get_dr(vcpu, 7, &val);
6566 put_smstate(u32, buf, 0x7fc8, (u32)val);
6568 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6569 put_smstate(u32, buf, 0x7fc4, seg.selector);
6570 put_smstate(u32, buf, 0x7f64, seg.base);
6571 put_smstate(u32, buf, 0x7f60, seg.limit);
6572 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6574 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6575 put_smstate(u32, buf, 0x7fc0, seg.selector);
6576 put_smstate(u32, buf, 0x7f80, seg.base);
6577 put_smstate(u32, buf, 0x7f7c, seg.limit);
6578 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6580 kvm_x86_ops->get_gdt(vcpu, &dt);
6581 put_smstate(u32, buf, 0x7f74, dt.address);
6582 put_smstate(u32, buf, 0x7f70, dt.size);
6584 kvm_x86_ops->get_idt(vcpu, &dt);
6585 put_smstate(u32, buf, 0x7f58, dt.address);
6586 put_smstate(u32, buf, 0x7f54, dt.size);
6588 for (i = 0; i < 6; i++)
6589 enter_smm_save_seg_32(vcpu, buf, i);
6591 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6594 put_smstate(u32, buf, 0x7efc, 0x00020000);
6595 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6598 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6600 #ifdef CONFIG_X86_64
6602 struct kvm_segment seg;
6606 for (i = 0; i < 16; i++)
6607 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6609 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6610 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6612 kvm_get_dr(vcpu, 6, &val);
6613 put_smstate(u64, buf, 0x7f68, val);
6614 kvm_get_dr(vcpu, 7, &val);
6615 put_smstate(u64, buf, 0x7f60, val);
6617 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6618 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6619 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6621 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6624 put_smstate(u32, buf, 0x7efc, 0x00020064);
6626 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6628 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6629 put_smstate(u16, buf, 0x7e90, seg.selector);
6630 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6631 put_smstate(u32, buf, 0x7e94, seg.limit);
6632 put_smstate(u64, buf, 0x7e98, seg.base);
6634 kvm_x86_ops->get_idt(vcpu, &dt);
6635 put_smstate(u32, buf, 0x7e84, dt.size);
6636 put_smstate(u64, buf, 0x7e88, dt.address);
6638 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6639 put_smstate(u16, buf, 0x7e70, seg.selector);
6640 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6641 put_smstate(u32, buf, 0x7e74, seg.limit);
6642 put_smstate(u64, buf, 0x7e78, seg.base);
6644 kvm_x86_ops->get_gdt(vcpu, &dt);
6645 put_smstate(u32, buf, 0x7e64, dt.size);
6646 put_smstate(u64, buf, 0x7e68, dt.address);
6648 for (i = 0; i < 6; i++)
6649 enter_smm_save_seg_64(vcpu, buf, i);
6655 static void enter_smm(struct kvm_vcpu *vcpu)
6657 struct kvm_segment cs, ds;
6662 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6663 memset(buf, 0, 512);
6664 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6665 enter_smm_save_state_64(vcpu, buf);
6667 enter_smm_save_state_32(vcpu, buf);
6670 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6671 * vCPU state (e.g. leave guest mode) after we've saved the state into
6672 * the SMM state-save area.
6674 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6676 vcpu->arch.hflags |= HF_SMM_MASK;
6677 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6679 if (kvm_x86_ops->get_nmi_mask(vcpu))
6680 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6682 kvm_x86_ops->set_nmi_mask(vcpu, true);
6684 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6685 kvm_rip_write(vcpu, 0x8000);
6687 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6688 kvm_x86_ops->set_cr0(vcpu, cr0);
6689 vcpu->arch.cr0 = cr0;
6691 kvm_x86_ops->set_cr4(vcpu, 0);
6693 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6694 dt.address = dt.size = 0;
6695 kvm_x86_ops->set_idt(vcpu, &dt);
6697 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6699 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6700 cs.base = vcpu->arch.smbase;
6705 cs.limit = ds.limit = 0xffffffff;
6706 cs.type = ds.type = 0x3;
6707 cs.dpl = ds.dpl = 0;
6712 cs.avl = ds.avl = 0;
6713 cs.present = ds.present = 1;
6714 cs.unusable = ds.unusable = 0;
6715 cs.padding = ds.padding = 0;
6717 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6718 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6719 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6720 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6721 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6722 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6724 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6725 kvm_x86_ops->set_efer(vcpu, 0);
6727 kvm_update_cpuid(vcpu);
6728 kvm_mmu_reset_context(vcpu);
6731 static void process_smi(struct kvm_vcpu *vcpu)
6733 vcpu->arch.smi_pending = true;
6734 kvm_make_request(KVM_REQ_EVENT, vcpu);
6737 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6739 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6742 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6744 u64 eoi_exit_bitmap[4];
6746 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6749 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6751 if (irqchip_split(vcpu->kvm))
6752 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6754 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6755 kvm_x86_ops->sync_pir_to_irr(vcpu);
6756 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6758 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6759 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6760 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6763 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6765 ++vcpu->stat.tlb_flush;
6766 kvm_x86_ops->tlb_flush(vcpu);
6769 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6770 unsigned long start, unsigned long end)
6772 unsigned long apic_address;
6775 * The physical address of apic access page is stored in the VMCS.
6776 * Update it when it becomes invalid.
6778 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6779 if (start <= apic_address && apic_address < end)
6780 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6783 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6785 struct page *page = NULL;
6787 if (!lapic_in_kernel(vcpu))
6790 if (!kvm_x86_ops->set_apic_access_page_addr)
6793 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6794 if (is_error_page(page))
6796 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6799 * Do not pin apic access page in memory, the MMU notifier
6800 * will call us again if it is migrated or swapped out.
6804 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6807 * Returns 1 to let vcpu_run() continue the guest execution loop without
6808 * exiting to the userspace. Otherwise, the value will be returned to the
6811 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6815 dm_request_for_irq_injection(vcpu) &&
6816 kvm_cpu_accept_dm_intr(vcpu);
6818 bool req_immediate_exit = false;
6820 if (kvm_request_pending(vcpu)) {
6821 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6822 kvm_mmu_unload(vcpu);
6823 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6824 __kvm_migrate_timers(vcpu);
6825 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6826 kvm_gen_update_masterclock(vcpu->kvm);
6827 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6828 kvm_gen_kvmclock_update(vcpu);
6829 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6830 r = kvm_guest_time_update(vcpu);
6834 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6835 kvm_mmu_sync_roots(vcpu);
6836 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6837 kvm_vcpu_flush_tlb(vcpu);
6838 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6839 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6843 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6844 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6845 vcpu->mmio_needed = 0;
6849 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6850 /* Page is swapped out. Do synthetic halt */
6851 vcpu->arch.apf.halted = true;
6855 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6856 record_steal_time(vcpu);
6857 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6859 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6861 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6862 kvm_pmu_handle_event(vcpu);
6863 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6864 kvm_pmu_deliver_pmi(vcpu);
6865 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6866 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6867 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6868 vcpu->arch.ioapic_handled_vectors)) {
6869 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6870 vcpu->run->eoi.vector =
6871 vcpu->arch.pending_ioapic_eoi;
6876 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6877 vcpu_scan_ioapic(vcpu);
6878 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6879 kvm_vcpu_reload_apic_access_page(vcpu);
6880 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6881 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6882 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6886 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6887 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6888 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6892 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6893 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6894 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6900 * KVM_REQ_HV_STIMER has to be processed after
6901 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6902 * depend on the guest clock being up-to-date
6904 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6905 kvm_hv_process_stimers(vcpu);
6908 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6909 ++vcpu->stat.req_event;
6910 kvm_apic_accept_events(vcpu);
6911 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6916 if (inject_pending_event(vcpu, req_int_win) != 0)
6917 req_immediate_exit = true;
6919 /* Enable SMI/NMI/IRQ window open exits if needed.
6921 * SMIs have three cases:
6922 * 1) They can be nested, and then there is nothing to
6923 * do here because RSM will cause a vmexit anyway.
6924 * 2) There is an ISA-specific reason why SMI cannot be
6925 * injected, and the moment when this changes can be
6927 * 3) Or the SMI can be pending because
6928 * inject_pending_event has completed the injection
6929 * of an IRQ or NMI from the previous vmexit, and
6930 * then we request an immediate exit to inject the
6933 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6934 if (!kvm_x86_ops->enable_smi_window(vcpu))
6935 req_immediate_exit = true;
6936 if (vcpu->arch.nmi_pending)
6937 kvm_x86_ops->enable_nmi_window(vcpu);
6938 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6939 kvm_x86_ops->enable_irq_window(vcpu);
6940 WARN_ON(vcpu->arch.exception.pending);
6943 if (kvm_lapic_enabled(vcpu)) {
6944 update_cr8_intercept(vcpu);
6945 kvm_lapic_sync_to_vapic(vcpu);
6949 r = kvm_mmu_reload(vcpu);
6951 goto cancel_injection;
6956 kvm_x86_ops->prepare_guest_switch(vcpu);
6959 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6960 * IPI are then delayed after guest entry, which ensures that they
6961 * result in virtual interrupt delivery.
6963 local_irq_disable();
6964 vcpu->mode = IN_GUEST_MODE;
6966 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6969 * 1) We should set ->mode before checking ->requests. Please see
6970 * the comment in kvm_vcpu_exiting_guest_mode().
6972 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6973 * pairs with the memory barrier implicit in pi_test_and_set_on
6974 * (see vmx_deliver_posted_interrupt).
6976 * 3) This also orders the write to mode from any reads to the page
6977 * tables done while the VCPU is running. Please see the comment
6978 * in kvm_flush_remote_tlbs.
6980 smp_mb__after_srcu_read_unlock();
6983 * This handles the case where a posted interrupt was
6984 * notified with kvm_vcpu_kick.
6986 if (kvm_lapic_enabled(vcpu)) {
6987 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6988 kvm_x86_ops->sync_pir_to_irr(vcpu);
6991 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
6992 || need_resched() || signal_pending(current)) {
6993 vcpu->mode = OUTSIDE_GUEST_MODE;
6997 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6999 goto cancel_injection;
7002 kvm_load_guest_xcr0(vcpu);
7004 if (req_immediate_exit) {
7005 kvm_make_request(KVM_REQ_EVENT, vcpu);
7006 smp_send_reschedule(vcpu->cpu);
7009 trace_kvm_entry(vcpu->vcpu_id);
7010 wait_lapic_expire(vcpu);
7011 guest_enter_irqoff();
7013 if (unlikely(vcpu->arch.switch_db_regs)) {
7015 set_debugreg(vcpu->arch.eff_db[0], 0);
7016 set_debugreg(vcpu->arch.eff_db[1], 1);
7017 set_debugreg(vcpu->arch.eff_db[2], 2);
7018 set_debugreg(vcpu->arch.eff_db[3], 3);
7019 set_debugreg(vcpu->arch.dr6, 6);
7020 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7023 kvm_x86_ops->run(vcpu);
7026 * Do this here before restoring debug registers on the host. And
7027 * since we do this before handling the vmexit, a DR access vmexit
7028 * can (a) read the correct value of the debug registers, (b) set
7029 * KVM_DEBUGREG_WONT_EXIT again.
7031 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7032 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7033 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7034 kvm_update_dr0123(vcpu);
7035 kvm_update_dr6(vcpu);
7036 kvm_update_dr7(vcpu);
7037 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7041 * If the guest has used debug registers, at least dr7
7042 * will be disabled while returning to the host.
7043 * If we don't have active breakpoints in the host, we don't
7044 * care about the messed up debug address registers. But if
7045 * we have some of them active, restore the old state.
7047 if (hw_breakpoint_active())
7048 hw_breakpoint_restore();
7050 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7052 vcpu->mode = OUTSIDE_GUEST_MODE;
7055 kvm_put_guest_xcr0(vcpu);
7057 kvm_x86_ops->handle_external_intr(vcpu);
7061 guest_exit_irqoff();
7066 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7069 * Profile KVM exit RIPs:
7071 if (unlikely(prof_on == KVM_PROFILING)) {
7072 unsigned long rip = kvm_rip_read(vcpu);
7073 profile_hit(KVM_PROFILING, (void *)rip);
7076 if (unlikely(vcpu->arch.tsc_always_catchup))
7077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7079 if (vcpu->arch.apic_attention)
7080 kvm_lapic_sync_from_vapic(vcpu);
7082 vcpu->arch.gpa_available = false;
7083 r = kvm_x86_ops->handle_exit(vcpu);
7087 kvm_x86_ops->cancel_injection(vcpu);
7088 if (unlikely(vcpu->arch.apic_attention))
7089 kvm_lapic_sync_from_vapic(vcpu);
7094 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7096 if (!kvm_arch_vcpu_runnable(vcpu) &&
7097 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7098 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7099 kvm_vcpu_block(vcpu);
7100 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7102 if (kvm_x86_ops->post_block)
7103 kvm_x86_ops->post_block(vcpu);
7105 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7109 kvm_apic_accept_events(vcpu);
7110 switch(vcpu->arch.mp_state) {
7111 case KVM_MP_STATE_HALTED:
7112 vcpu->arch.pv.pv_unhalted = false;
7113 vcpu->arch.mp_state =
7114 KVM_MP_STATE_RUNNABLE;
7115 case KVM_MP_STATE_RUNNABLE:
7116 vcpu->arch.apf.halted = false;
7118 case KVM_MP_STATE_INIT_RECEIVED:
7127 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7129 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7130 kvm_x86_ops->check_nested_events(vcpu, false);
7132 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7133 !vcpu->arch.apf.halted);
7136 static int vcpu_run(struct kvm_vcpu *vcpu)
7139 struct kvm *kvm = vcpu->kvm;
7141 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7144 if (kvm_vcpu_running(vcpu)) {
7145 r = vcpu_enter_guest(vcpu);
7147 r = vcpu_block(kvm, vcpu);
7153 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7154 if (kvm_cpu_has_pending_timer(vcpu))
7155 kvm_inject_pending_timer_irqs(vcpu);
7157 if (dm_request_for_irq_injection(vcpu) &&
7158 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7160 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7161 ++vcpu->stat.request_irq_exits;
7165 kvm_check_async_pf_completion(vcpu);
7167 if (signal_pending(current)) {
7169 vcpu->run->exit_reason = KVM_EXIT_INTR;
7170 ++vcpu->stat.signal_exits;
7173 if (need_resched()) {
7174 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7176 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7180 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7185 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7188 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7189 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7190 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7191 if (r != EMULATE_DONE)
7196 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7198 BUG_ON(!vcpu->arch.pio.count);
7200 return complete_emulated_io(vcpu);
7204 * Implements the following, as a state machine:
7208 * for each mmio piece in the fragment
7216 * for each mmio piece in the fragment
7221 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7223 struct kvm_run *run = vcpu->run;
7224 struct kvm_mmio_fragment *frag;
7227 BUG_ON(!vcpu->mmio_needed);
7229 /* Complete previous fragment */
7230 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7231 len = min(8u, frag->len);
7232 if (!vcpu->mmio_is_write)
7233 memcpy(frag->data, run->mmio.data, len);
7235 if (frag->len <= 8) {
7236 /* Switch to the next fragment. */
7238 vcpu->mmio_cur_fragment++;
7240 /* Go forward to the next mmio piece. */
7246 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7247 vcpu->mmio_needed = 0;
7249 /* FIXME: return into emulator if single-stepping. */
7250 if (vcpu->mmio_is_write)
7252 vcpu->mmio_read_completed = 1;
7253 return complete_emulated_io(vcpu);
7256 run->exit_reason = KVM_EXIT_MMIO;
7257 run->mmio.phys_addr = frag->gpa;
7258 if (vcpu->mmio_is_write)
7259 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7260 run->mmio.len = min(8u, frag->len);
7261 run->mmio.is_write = vcpu->mmio_is_write;
7262 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7267 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7271 kvm_sigset_activate(vcpu);
7273 kvm_load_guest_fpu(vcpu);
7275 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7276 if (kvm_run->immediate_exit) {
7280 kvm_vcpu_block(vcpu);
7281 kvm_apic_accept_events(vcpu);
7282 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7284 if (signal_pending(current)) {
7286 vcpu->run->exit_reason = KVM_EXIT_INTR;
7287 ++vcpu->stat.signal_exits;
7292 /* re-sync apic's tpr */
7293 if (!lapic_in_kernel(vcpu)) {
7294 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7300 if (unlikely(vcpu->arch.complete_userspace_io)) {
7301 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7302 vcpu->arch.complete_userspace_io = NULL;
7307 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7309 if (kvm_run->immediate_exit)
7315 kvm_put_guest_fpu(vcpu);
7316 post_kvm_run_save(vcpu);
7317 kvm_sigset_deactivate(vcpu);
7322 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7324 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7326 * We are here if userspace calls get_regs() in the middle of
7327 * instruction emulation. Registers state needs to be copied
7328 * back from emulation context to vcpu. Userspace shouldn't do
7329 * that usually, but some bad designed PV devices (vmware
7330 * backdoor interface) need this to work
7332 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7333 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7335 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7336 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7337 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7338 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7339 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7340 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7341 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7342 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7343 #ifdef CONFIG_X86_64
7344 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7345 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7346 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7347 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7348 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7349 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7350 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7351 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7354 regs->rip = kvm_rip_read(vcpu);
7355 regs->rflags = kvm_get_rflags(vcpu);
7360 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7362 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7363 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7365 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7366 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7367 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7368 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7369 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7370 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7371 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7372 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7373 #ifdef CONFIG_X86_64
7374 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7375 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7376 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7377 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7378 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7379 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7380 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7381 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7384 kvm_rip_write(vcpu, regs->rip);
7385 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7387 vcpu->arch.exception.pending = false;
7389 kvm_make_request(KVM_REQ_EVENT, vcpu);
7394 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7396 struct kvm_segment cs;
7398 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7402 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7404 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7405 struct kvm_sregs *sregs)
7409 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7410 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7411 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7412 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7413 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7414 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7416 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7417 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7419 kvm_x86_ops->get_idt(vcpu, &dt);
7420 sregs->idt.limit = dt.size;
7421 sregs->idt.base = dt.address;
7422 kvm_x86_ops->get_gdt(vcpu, &dt);
7423 sregs->gdt.limit = dt.size;
7424 sregs->gdt.base = dt.address;
7426 sregs->cr0 = kvm_read_cr0(vcpu);
7427 sregs->cr2 = vcpu->arch.cr2;
7428 sregs->cr3 = kvm_read_cr3(vcpu);
7429 sregs->cr4 = kvm_read_cr4(vcpu);
7430 sregs->cr8 = kvm_get_cr8(vcpu);
7431 sregs->efer = vcpu->arch.efer;
7432 sregs->apic_base = kvm_get_apic_base(vcpu);
7434 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7436 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7437 set_bit(vcpu->arch.interrupt.nr,
7438 (unsigned long *)sregs->interrupt_bitmap);
7443 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7444 struct kvm_mp_state *mp_state)
7446 kvm_apic_accept_events(vcpu);
7447 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7448 vcpu->arch.pv.pv_unhalted)
7449 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7451 mp_state->mp_state = vcpu->arch.mp_state;
7456 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7457 struct kvm_mp_state *mp_state)
7459 if (!lapic_in_kernel(vcpu) &&
7460 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7463 /* INITs are latched while in SMM */
7464 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7465 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7466 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7469 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7470 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7471 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7473 vcpu->arch.mp_state = mp_state->mp_state;
7474 kvm_make_request(KVM_REQ_EVENT, vcpu);
7478 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7479 int reason, bool has_error_code, u32 error_code)
7481 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7484 init_emulate_ctxt(vcpu);
7486 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7487 has_error_code, error_code);
7490 return EMULATE_FAIL;
7492 kvm_rip_write(vcpu, ctxt->eip);
7493 kvm_set_rflags(vcpu, ctxt->eflags);
7494 kvm_make_request(KVM_REQ_EVENT, vcpu);
7495 return EMULATE_DONE;
7497 EXPORT_SYMBOL_GPL(kvm_task_switch);
7499 int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7501 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7503 * When EFER.LME and CR0.PG are set, the processor is in
7504 * 64-bit mode (though maybe in a 32-bit code segment).
7505 * CR4.PAE and EFER.LMA must be set.
7507 if (!(sregs->cr4 & X86_CR4_PAE)
7508 || !(sregs->efer & EFER_LMA))
7512 * Not in 64-bit mode: EFER.LMA is clear and the code
7513 * segment cannot be 64-bit.
7515 if (sregs->efer & EFER_LMA || sregs->cs.l)
7522 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7523 struct kvm_sregs *sregs)
7525 struct msr_data apic_base_msr;
7526 int mmu_reset_needed = 0;
7527 int pending_vec, max_bits, idx;
7530 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7531 (sregs->cr4 & X86_CR4_OSXSAVE))
7534 if (kvm_valid_sregs(vcpu, sregs))
7537 apic_base_msr.data = sregs->apic_base;
7538 apic_base_msr.host_initiated = true;
7539 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7542 dt.size = sregs->idt.limit;
7543 dt.address = sregs->idt.base;
7544 kvm_x86_ops->set_idt(vcpu, &dt);
7545 dt.size = sregs->gdt.limit;
7546 dt.address = sregs->gdt.base;
7547 kvm_x86_ops->set_gdt(vcpu, &dt);
7549 vcpu->arch.cr2 = sregs->cr2;
7550 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7551 vcpu->arch.cr3 = sregs->cr3;
7552 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7554 kvm_set_cr8(vcpu, sregs->cr8);
7556 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7557 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7559 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7560 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7561 vcpu->arch.cr0 = sregs->cr0;
7563 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7564 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7565 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7566 kvm_update_cpuid(vcpu);
7568 idx = srcu_read_lock(&vcpu->kvm->srcu);
7569 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7570 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7571 mmu_reset_needed = 1;
7573 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7575 if (mmu_reset_needed)
7576 kvm_mmu_reset_context(vcpu);
7578 max_bits = KVM_NR_INTERRUPTS;
7579 pending_vec = find_first_bit(
7580 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7581 if (pending_vec < max_bits) {
7582 kvm_queue_interrupt(vcpu, pending_vec, false);
7583 pr_debug("Set back pending irq %d\n", pending_vec);
7586 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7587 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7588 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7589 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7590 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7591 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7593 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7594 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7596 update_cr8_intercept(vcpu);
7598 /* Older userspace won't unhalt the vcpu on reset. */
7599 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7600 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7602 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7604 kvm_make_request(KVM_REQ_EVENT, vcpu);
7609 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7610 struct kvm_guest_debug *dbg)
7612 unsigned long rflags;
7615 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7617 if (vcpu->arch.exception.pending)
7619 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7620 kvm_queue_exception(vcpu, DB_VECTOR);
7622 kvm_queue_exception(vcpu, BP_VECTOR);
7626 * Read rflags as long as potentially injected trace flags are still
7629 rflags = kvm_get_rflags(vcpu);
7631 vcpu->guest_debug = dbg->control;
7632 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7633 vcpu->guest_debug = 0;
7635 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7636 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7637 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7638 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7640 for (i = 0; i < KVM_NR_DB_REGS; i++)
7641 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7643 kvm_update_dr7(vcpu);
7645 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7646 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7647 get_segment_base(vcpu, VCPU_SREG_CS);
7650 * Trigger an rflags update that will inject or remove the trace
7653 kvm_set_rflags(vcpu, rflags);
7655 kvm_x86_ops->update_bp_intercept(vcpu);
7665 * Translate a guest virtual address to a guest physical address.
7667 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7668 struct kvm_translation *tr)
7670 unsigned long vaddr = tr->linear_address;
7674 idx = srcu_read_lock(&vcpu->kvm->srcu);
7675 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7676 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7677 tr->physical_address = gpa;
7678 tr->valid = gpa != UNMAPPED_GVA;
7685 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7687 struct fxregs_state *fxsave =
7688 &vcpu->arch.guest_fpu.state.fxsave;
7690 memcpy(fpu->fpr, fxsave->st_space, 128);
7691 fpu->fcw = fxsave->cwd;
7692 fpu->fsw = fxsave->swd;
7693 fpu->ftwx = fxsave->twd;
7694 fpu->last_opcode = fxsave->fop;
7695 fpu->last_ip = fxsave->rip;
7696 fpu->last_dp = fxsave->rdp;
7697 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7702 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7704 struct fxregs_state *fxsave =
7705 &vcpu->arch.guest_fpu.state.fxsave;
7707 memcpy(fxsave->st_space, fpu->fpr, 128);
7708 fxsave->cwd = fpu->fcw;
7709 fxsave->swd = fpu->fsw;
7710 fxsave->twd = fpu->ftwx;
7711 fxsave->fop = fpu->last_opcode;
7712 fxsave->rip = fpu->last_ip;
7713 fxsave->rdp = fpu->last_dp;
7714 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7719 static void fx_init(struct kvm_vcpu *vcpu)
7721 fpstate_init(&vcpu->arch.guest_fpu.state);
7722 if (boot_cpu_has(X86_FEATURE_XSAVES))
7723 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7724 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7727 * Ensure guest xcr0 is valid for loading
7729 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7731 vcpu->arch.cr0 |= X86_CR0_ET;
7734 /* Swap (qemu) user FPU context for the guest FPU context. */
7735 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7738 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7739 /* PKRU is separately restored in kvm_x86_ops->run. */
7740 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7741 ~XFEATURE_MASK_PKRU);
7746 /* When vcpu_run ends, restore user space FPU context. */
7747 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7750 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7751 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7753 ++vcpu->stat.fpu_reload;
7757 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7759 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7761 kvmclock_reset(vcpu);
7763 kvm_x86_ops->vcpu_free(vcpu);
7764 free_cpumask_var(wbinvd_dirty_mask);
7767 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7770 struct kvm_vcpu *vcpu;
7772 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7773 printk_once(KERN_WARNING
7774 "kvm: SMP vm created on host with unstable TSC; "
7775 "guest TSC will not be reliable\n");
7777 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7782 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7786 kvm_vcpu_mtrr_init(vcpu);
7787 r = vcpu_load(vcpu);
7790 kvm_vcpu_reset(vcpu, false);
7791 kvm_mmu_setup(vcpu);
7796 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7798 struct msr_data msr;
7799 struct kvm *kvm = vcpu->kvm;
7801 kvm_hv_vcpu_postcreate(vcpu);
7803 if (vcpu_load(vcpu))
7806 msr.index = MSR_IA32_TSC;
7807 msr.host_initiated = true;
7808 kvm_write_tsc(vcpu, &msr);
7811 if (!kvmclock_periodic_sync)
7814 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7815 KVMCLOCK_SYNC_PERIOD);
7818 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7821 vcpu->arch.apf.msr_val = 0;
7823 r = vcpu_load(vcpu);
7825 kvm_mmu_unload(vcpu);
7828 kvm_x86_ops->vcpu_free(vcpu);
7831 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7833 vcpu->arch.hflags = 0;
7835 vcpu->arch.smi_pending = 0;
7836 atomic_set(&vcpu->arch.nmi_queued, 0);
7837 vcpu->arch.nmi_pending = 0;
7838 vcpu->arch.nmi_injected = false;
7839 kvm_clear_interrupt_queue(vcpu);
7840 kvm_clear_exception_queue(vcpu);
7841 vcpu->arch.exception.pending = false;
7843 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7844 kvm_update_dr0123(vcpu);
7845 vcpu->arch.dr6 = DR6_INIT;
7846 kvm_update_dr6(vcpu);
7847 vcpu->arch.dr7 = DR7_FIXED_1;
7848 kvm_update_dr7(vcpu);
7852 kvm_make_request(KVM_REQ_EVENT, vcpu);
7853 vcpu->arch.apf.msr_val = 0;
7854 vcpu->arch.st.msr_val = 0;
7856 kvmclock_reset(vcpu);
7858 kvm_clear_async_pf_completion_queue(vcpu);
7859 kvm_async_pf_hash_reset(vcpu);
7860 vcpu->arch.apf.halted = false;
7862 if (kvm_mpx_supported()) {
7863 void *mpx_state_buffer;
7866 * To avoid have the INIT path from kvm_apic_has_events() that be
7867 * called with loaded FPU and does not let userspace fix the state.
7870 kvm_put_guest_fpu(vcpu);
7871 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7872 XFEATURE_MASK_BNDREGS);
7873 if (mpx_state_buffer)
7874 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7875 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7876 XFEATURE_MASK_BNDCSR);
7877 if (mpx_state_buffer)
7878 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
7880 kvm_load_guest_fpu(vcpu);
7884 kvm_pmu_reset(vcpu);
7885 vcpu->arch.smbase = 0x30000;
7887 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7888 vcpu->arch.msr_misc_features_enables = 0;
7890 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7893 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7894 vcpu->arch.regs_avail = ~0;
7895 vcpu->arch.regs_dirty = ~0;
7897 vcpu->arch.ia32_xss = 0;
7899 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7902 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7904 struct kvm_segment cs;
7906 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7907 cs.selector = vector << 8;
7908 cs.base = vector << 12;
7909 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7910 kvm_rip_write(vcpu, 0);
7913 int kvm_arch_hardware_enable(void)
7916 struct kvm_vcpu *vcpu;
7921 bool stable, backwards_tsc = false;
7923 kvm_shared_msr_cpu_online();
7924 ret = kvm_x86_ops->hardware_enable();
7928 local_tsc = rdtsc();
7929 stable = !check_tsc_unstable();
7930 list_for_each_entry(kvm, &vm_list, vm_list) {
7931 kvm_for_each_vcpu(i, vcpu, kvm) {
7932 if (!stable && vcpu->cpu == smp_processor_id())
7933 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7934 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7935 backwards_tsc = true;
7936 if (vcpu->arch.last_host_tsc > max_tsc)
7937 max_tsc = vcpu->arch.last_host_tsc;
7943 * Sometimes, even reliable TSCs go backwards. This happens on
7944 * platforms that reset TSC during suspend or hibernate actions, but
7945 * maintain synchronization. We must compensate. Fortunately, we can
7946 * detect that condition here, which happens early in CPU bringup,
7947 * before any KVM threads can be running. Unfortunately, we can't
7948 * bring the TSCs fully up to date with real time, as we aren't yet far
7949 * enough into CPU bringup that we know how much real time has actually
7950 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7951 * variables that haven't been updated yet.
7953 * So we simply find the maximum observed TSC above, then record the
7954 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7955 * the adjustment will be applied. Note that we accumulate
7956 * adjustments, in case multiple suspend cycles happen before some VCPU
7957 * gets a chance to run again. In the event that no KVM threads get a
7958 * chance to run, we will miss the entire elapsed period, as we'll have
7959 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7960 * loose cycle time. This isn't too big a deal, since the loss will be
7961 * uniform across all VCPUs (not to mention the scenario is extremely
7962 * unlikely). It is possible that a second hibernate recovery happens
7963 * much faster than a first, causing the observed TSC here to be
7964 * smaller; this would require additional padding adjustment, which is
7965 * why we set last_host_tsc to the local tsc observed here.
7967 * N.B. - this code below runs only on platforms with reliable TSC,
7968 * as that is the only way backwards_tsc is set above. Also note
7969 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7970 * have the same delta_cyc adjustment applied if backwards_tsc
7971 * is detected. Note further, this adjustment is only done once,
7972 * as we reset last_host_tsc on all VCPUs to stop this from being
7973 * called multiple times (one for each physical CPU bringup).
7975 * Platforms with unreliable TSCs don't have to deal with this, they
7976 * will be compensated by the logic in vcpu_load, which sets the TSC to
7977 * catchup mode. This will catchup all VCPUs to real time, but cannot
7978 * guarantee that they stay in perfect synchronization.
7980 if (backwards_tsc) {
7981 u64 delta_cyc = max_tsc - local_tsc;
7982 list_for_each_entry(kvm, &vm_list, vm_list) {
7983 kvm->arch.backwards_tsc_observed = true;
7984 kvm_for_each_vcpu(i, vcpu, kvm) {
7985 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7986 vcpu->arch.last_host_tsc = local_tsc;
7987 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7991 * We have to disable TSC offset matching.. if you were
7992 * booting a VM while issuing an S4 host suspend....
7993 * you may have some problem. Solving this issue is
7994 * left as an exercise to the reader.
7996 kvm->arch.last_tsc_nsec = 0;
7997 kvm->arch.last_tsc_write = 0;
8004 void kvm_arch_hardware_disable(void)
8006 kvm_x86_ops->hardware_disable();
8007 drop_user_return_notifiers();
8010 int kvm_arch_hardware_setup(void)
8014 r = kvm_x86_ops->hardware_setup();
8018 if (kvm_has_tsc_control) {
8020 * Make sure the user can only configure tsc_khz values that
8021 * fit into a signed integer.
8022 * A min value is not calculated needed because it will always
8023 * be 1 on all machines.
8025 u64 max = min(0x7fffffffULL,
8026 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8027 kvm_max_guest_tsc_khz = max;
8029 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8032 kvm_init_msr_list();
8036 void kvm_arch_hardware_unsetup(void)
8038 kvm_x86_ops->hardware_unsetup();
8041 void kvm_arch_check_processor_compat(void *rtn)
8043 kvm_x86_ops->check_processor_compatibility(rtn);
8046 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8048 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8050 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8052 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8054 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8057 struct static_key kvm_no_apic_vcpu __read_mostly;
8058 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8060 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8065 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8066 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8067 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8068 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8070 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8072 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8077 vcpu->arch.pio_data = page_address(page);
8079 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8081 r = kvm_mmu_create(vcpu);
8083 goto fail_free_pio_data;
8085 if (irqchip_in_kernel(vcpu->kvm)) {
8086 r = kvm_create_lapic(vcpu);
8088 goto fail_mmu_destroy;
8090 static_key_slow_inc(&kvm_no_apic_vcpu);
8092 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8094 if (!vcpu->arch.mce_banks) {
8096 goto fail_free_lapic;
8098 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8100 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8102 goto fail_free_mce_banks;
8107 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8109 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8111 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8113 kvm_async_pf_hash_reset(vcpu);
8116 vcpu->arch.pending_external_vector = -1;
8117 vcpu->arch.preempted_in_kernel = false;
8119 kvm_hv_vcpu_init(vcpu);
8123 fail_free_mce_banks:
8124 kfree(vcpu->arch.mce_banks);
8126 kvm_free_lapic(vcpu);
8128 kvm_mmu_destroy(vcpu);
8130 free_page((unsigned long)vcpu->arch.pio_data);
8135 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8139 kvm_hv_vcpu_uninit(vcpu);
8140 kvm_pmu_destroy(vcpu);
8141 kfree(vcpu->arch.mce_banks);
8142 kvm_free_lapic(vcpu);
8143 idx = srcu_read_lock(&vcpu->kvm->srcu);
8144 kvm_mmu_destroy(vcpu);
8145 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8146 free_page((unsigned long)vcpu->arch.pio_data);
8147 if (!lapic_in_kernel(vcpu))
8148 static_key_slow_dec(&kvm_no_apic_vcpu);
8151 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8153 kvm_x86_ops->sched_in(vcpu, cpu);
8156 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8161 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8162 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8163 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8164 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8165 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8167 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8168 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8169 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8170 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8171 &kvm->arch.irq_sources_bitmap);
8173 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8174 mutex_init(&kvm->arch.apic_map_lock);
8175 mutex_init(&kvm->arch.hyperv.hv_lock);
8176 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8178 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8179 pvclock_update_vm_gtod_copy(kvm);
8181 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8182 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8184 kvm_page_track_init(kvm);
8185 kvm_mmu_init_vm(kvm);
8187 if (kvm_x86_ops->vm_init)
8188 return kvm_x86_ops->vm_init(kvm);
8193 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8196 r = vcpu_load(vcpu);
8198 kvm_mmu_unload(vcpu);
8202 static void kvm_free_vcpus(struct kvm *kvm)
8205 struct kvm_vcpu *vcpu;
8208 * Unpin any mmu pages first.
8210 kvm_for_each_vcpu(i, vcpu, kvm) {
8211 kvm_clear_async_pf_completion_queue(vcpu);
8212 kvm_unload_vcpu_mmu(vcpu);
8214 kvm_for_each_vcpu(i, vcpu, kvm)
8215 kvm_arch_vcpu_free(vcpu);
8217 mutex_lock(&kvm->lock);
8218 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8219 kvm->vcpus[i] = NULL;
8221 atomic_set(&kvm->online_vcpus, 0);
8222 mutex_unlock(&kvm->lock);
8225 void kvm_arch_sync_events(struct kvm *kvm)
8227 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8228 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8232 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8236 struct kvm_memslots *slots = kvm_memslots(kvm);
8237 struct kvm_memory_slot *slot, old;
8239 /* Called with kvm->slots_lock held. */
8240 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8243 slot = id_to_memslot(slots, id);
8249 * MAP_SHARED to prevent internal slot pages from being moved
8252 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8253 MAP_SHARED | MAP_ANONYMOUS, 0);
8254 if (IS_ERR((void *)hva))
8255 return PTR_ERR((void *)hva);
8264 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8265 struct kvm_userspace_memory_region m;
8267 m.slot = id | (i << 16);
8269 m.guest_phys_addr = gpa;
8270 m.userspace_addr = hva;
8271 m.memory_size = size;
8272 r = __kvm_set_memory_region(kvm, &m);
8278 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8284 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8286 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8290 mutex_lock(&kvm->slots_lock);
8291 r = __x86_set_memory_region(kvm, id, gpa, size);
8292 mutex_unlock(&kvm->slots_lock);
8296 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8298 void kvm_arch_destroy_vm(struct kvm *kvm)
8300 if (current->mm == kvm->mm) {
8302 * Free memory regions allocated on behalf of userspace,
8303 * unless the the memory map has changed due to process exit
8306 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8307 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8308 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8310 if (kvm_x86_ops->vm_destroy)
8311 kvm_x86_ops->vm_destroy(kvm);
8312 kvm_pic_destroy(kvm);
8313 kvm_ioapic_destroy(kvm);
8314 kvm_free_vcpus(kvm);
8315 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8316 kvm_mmu_uninit_vm(kvm);
8317 kvm_page_track_cleanup(kvm);
8320 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8321 struct kvm_memory_slot *dont)
8325 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8326 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8327 kvfree(free->arch.rmap[i]);
8328 free->arch.rmap[i] = NULL;
8333 if (!dont || free->arch.lpage_info[i - 1] !=
8334 dont->arch.lpage_info[i - 1]) {
8335 kvfree(free->arch.lpage_info[i - 1]);
8336 free->arch.lpage_info[i - 1] = NULL;
8340 kvm_page_track_free_memslot(free, dont);
8343 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8344 unsigned long npages)
8348 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8349 struct kvm_lpage_info *linfo;
8354 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8355 slot->base_gfn, level) + 1;
8357 slot->arch.rmap[i] =
8358 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8359 if (!slot->arch.rmap[i])
8364 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8368 slot->arch.lpage_info[i - 1] = linfo;
8370 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8371 linfo[0].disallow_lpage = 1;
8372 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8373 linfo[lpages - 1].disallow_lpage = 1;
8374 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8376 * If the gfn and userspace address are not aligned wrt each
8377 * other, or if explicitly asked to, disable large page
8378 * support for this slot
8380 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8381 !kvm_largepages_enabled()) {
8384 for (j = 0; j < lpages; ++j)
8385 linfo[j].disallow_lpage = 1;
8389 if (kvm_page_track_create_memslot(slot, npages))
8395 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8396 kvfree(slot->arch.rmap[i]);
8397 slot->arch.rmap[i] = NULL;
8401 kvfree(slot->arch.lpage_info[i - 1]);
8402 slot->arch.lpage_info[i - 1] = NULL;
8407 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8410 * memslots->generation has been incremented.
8411 * mmio generation may have reached its maximum value.
8413 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8416 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8417 struct kvm_memory_slot *memslot,
8418 const struct kvm_userspace_memory_region *mem,
8419 enum kvm_mr_change change)
8424 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8425 struct kvm_memory_slot *new)
8427 /* Still write protect RO slot */
8428 if (new->flags & KVM_MEM_READONLY) {
8429 kvm_mmu_slot_remove_write_access(kvm, new);
8434 * Call kvm_x86_ops dirty logging hooks when they are valid.
8436 * kvm_x86_ops->slot_disable_log_dirty is called when:
8438 * - KVM_MR_CREATE with dirty logging is disabled
8439 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8441 * The reason is, in case of PML, we need to set D-bit for any slots
8442 * with dirty logging disabled in order to eliminate unnecessary GPA
8443 * logging in PML buffer (and potential PML buffer full VMEXT). This
8444 * guarantees leaving PML enabled during guest's lifetime won't have
8445 * any additonal overhead from PML when guest is running with dirty
8446 * logging disabled for memory slots.
8448 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8449 * to dirty logging mode.
8451 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8453 * In case of write protect:
8455 * Write protect all pages for dirty logging.
8457 * All the sptes including the large sptes which point to this
8458 * slot are set to readonly. We can not create any new large
8459 * spte on this slot until the end of the logging.
8461 * See the comments in fast_page_fault().
8463 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8464 if (kvm_x86_ops->slot_enable_log_dirty)
8465 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8467 kvm_mmu_slot_remove_write_access(kvm, new);
8469 if (kvm_x86_ops->slot_disable_log_dirty)
8470 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8474 void kvm_arch_commit_memory_region(struct kvm *kvm,
8475 const struct kvm_userspace_memory_region *mem,
8476 const struct kvm_memory_slot *old,
8477 const struct kvm_memory_slot *new,
8478 enum kvm_mr_change change)
8480 int nr_mmu_pages = 0;
8482 if (!kvm->arch.n_requested_mmu_pages)
8483 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8486 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8489 * Dirty logging tracks sptes in 4k granularity, meaning that large
8490 * sptes have to be split. If live migration is successful, the guest
8491 * in the source machine will be destroyed and large sptes will be
8492 * created in the destination. However, if the guest continues to run
8493 * in the source machine (for example if live migration fails), small
8494 * sptes will remain around and cause bad performance.
8496 * Scan sptes if dirty logging has been stopped, dropping those
8497 * which can be collapsed into a single large-page spte. Later
8498 * page faults will create the large-page sptes.
8500 if ((change != KVM_MR_DELETE) &&
8501 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8502 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8503 kvm_mmu_zap_collapsible_sptes(kvm, new);
8506 * Set up write protection and/or dirty logging for the new slot.
8508 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8509 * been zapped so no dirty logging staff is needed for old slot. For
8510 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8511 * new and it's also covered when dealing with the new slot.
8513 * FIXME: const-ify all uses of struct kvm_memory_slot.
8515 if (change != KVM_MR_DELETE)
8516 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8519 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8521 kvm_mmu_invalidate_zap_all_pages(kvm);
8524 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8525 struct kvm_memory_slot *slot)
8527 kvm_page_track_flush_slot(kvm, slot);
8530 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8532 if (!list_empty_careful(&vcpu->async_pf.done))
8535 if (kvm_apic_has_events(vcpu))
8538 if (vcpu->arch.pv.pv_unhalted)
8541 if (vcpu->arch.exception.pending)
8544 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8545 (vcpu->arch.nmi_pending &&
8546 kvm_x86_ops->nmi_allowed(vcpu)))
8549 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8550 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8553 if (kvm_arch_interrupt_allowed(vcpu) &&
8554 kvm_cpu_has_interrupt(vcpu))
8557 if (kvm_hv_has_stimer_pending(vcpu))
8563 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8565 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8568 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8570 return vcpu->arch.preempted_in_kernel;
8573 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8575 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8578 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8580 return kvm_x86_ops->interrupt_allowed(vcpu);
8583 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8585 if (is_64_bit_mode(vcpu))
8586 return kvm_rip_read(vcpu);
8587 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8588 kvm_rip_read(vcpu));
8590 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8592 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8594 return kvm_get_linear_rip(vcpu) == linear_rip;
8596 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8598 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8600 unsigned long rflags;
8602 rflags = kvm_x86_ops->get_rflags(vcpu);
8603 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8604 rflags &= ~X86_EFLAGS_TF;
8607 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8609 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8612 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8613 rflags |= X86_EFLAGS_TF;
8614 kvm_x86_ops->set_rflags(vcpu, rflags);
8617 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8619 __kvm_set_rflags(vcpu, rflags);
8620 kvm_make_request(KVM_REQ_EVENT, vcpu);
8622 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8624 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8628 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8632 r = kvm_mmu_reload(vcpu);
8636 if (!vcpu->arch.mmu.direct_map &&
8637 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8640 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8643 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8645 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8648 static inline u32 kvm_async_pf_next_probe(u32 key)
8650 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8653 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8655 u32 key = kvm_async_pf_hash_fn(gfn);
8657 while (vcpu->arch.apf.gfns[key] != ~0)
8658 key = kvm_async_pf_next_probe(key);
8660 vcpu->arch.apf.gfns[key] = gfn;
8663 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8666 u32 key = kvm_async_pf_hash_fn(gfn);
8668 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8669 (vcpu->arch.apf.gfns[key] != gfn &&
8670 vcpu->arch.apf.gfns[key] != ~0); i++)
8671 key = kvm_async_pf_next_probe(key);
8676 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8678 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8681 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8685 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8687 vcpu->arch.apf.gfns[i] = ~0;
8689 j = kvm_async_pf_next_probe(j);
8690 if (vcpu->arch.apf.gfns[j] == ~0)
8692 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8694 * k lies cyclically in ]i,j]
8696 * |....j i.k.| or |.k..j i...|
8698 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8699 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8704 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8707 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8711 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8714 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8718 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8719 struct kvm_async_pf *work)
8721 struct x86_exception fault;
8723 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8724 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8726 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8727 (vcpu->arch.apf.send_user_only &&
8728 kvm_x86_ops->get_cpl(vcpu) == 0))
8729 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8730 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8731 fault.vector = PF_VECTOR;
8732 fault.error_code_valid = true;
8733 fault.error_code = 0;
8734 fault.nested_page_fault = false;
8735 fault.address = work->arch.token;
8736 fault.async_page_fault = true;
8737 kvm_inject_page_fault(vcpu, &fault);
8741 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8742 struct kvm_async_pf *work)
8744 struct x86_exception fault;
8747 if (work->wakeup_all)
8748 work->arch.token = ~0; /* broadcast wakeup */
8750 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8751 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8753 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8754 !apf_get_user(vcpu, &val)) {
8755 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8756 vcpu->arch.exception.pending &&
8757 vcpu->arch.exception.nr == PF_VECTOR &&
8758 !apf_put_user(vcpu, 0)) {
8759 vcpu->arch.exception.injected = false;
8760 vcpu->arch.exception.pending = false;
8761 vcpu->arch.exception.nr = 0;
8762 vcpu->arch.exception.has_error_code = false;
8763 vcpu->arch.exception.error_code = 0;
8764 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8765 fault.vector = PF_VECTOR;
8766 fault.error_code_valid = true;
8767 fault.error_code = 0;
8768 fault.nested_page_fault = false;
8769 fault.address = work->arch.token;
8770 fault.async_page_fault = true;
8771 kvm_inject_page_fault(vcpu, &fault);
8774 vcpu->arch.apf.halted = false;
8775 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8778 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8780 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8783 return kvm_can_do_async_pf(vcpu);
8786 void kvm_arch_start_assignment(struct kvm *kvm)
8788 atomic_inc(&kvm->arch.assigned_device_count);
8790 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8792 void kvm_arch_end_assignment(struct kvm *kvm)
8794 atomic_dec(&kvm->arch.assigned_device_count);
8796 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8798 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8800 return atomic_read(&kvm->arch.assigned_device_count);
8802 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8804 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8806 atomic_inc(&kvm->arch.noncoherent_dma_count);
8808 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8810 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8812 atomic_dec(&kvm->arch.noncoherent_dma_count);
8814 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8816 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8818 return atomic_read(&kvm->arch.noncoherent_dma_count);
8820 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8822 bool kvm_arch_has_irq_bypass(void)
8824 return kvm_x86_ops->update_pi_irte != NULL;
8827 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8828 struct irq_bypass_producer *prod)
8830 struct kvm_kernel_irqfd *irqfd =
8831 container_of(cons, struct kvm_kernel_irqfd, consumer);
8833 irqfd->producer = prod;
8835 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8836 prod->irq, irqfd->gsi, 1);
8839 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8840 struct irq_bypass_producer *prod)
8843 struct kvm_kernel_irqfd *irqfd =
8844 container_of(cons, struct kvm_kernel_irqfd, consumer);
8846 WARN_ON(irqfd->producer != prod);
8847 irqfd->producer = NULL;
8850 * When producer of consumer is unregistered, we change back to
8851 * remapped mode, so we can re-use the current implementation
8852 * when the irq is masked/disabled or the consumer side (KVM
8853 * int this case doesn't want to receive the interrupts.
8855 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8857 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8858 " fails: %d\n", irqfd->consumer.token, ret);
8861 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8862 uint32_t guest_irq, bool set)
8864 if (!kvm_x86_ops->update_pi_irte)
8867 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8870 bool kvm_vector_hashing_enabled(void)
8872 return vector_hashing;
8874 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8876 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8877 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8878 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8879 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8880 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8881 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8882 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8883 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8884 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8885 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8886 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8887 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8888 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8889 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8890 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8891 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8892 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8893 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8894 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);