2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72 #include <asm/intel_pt.h>
74 #define CREATE_TRACE_POINTS
77 #define MAX_IO_MSRS 256
78 #define KVM_MAX_MCE_BANKS 32
79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
82 #define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
102 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
103 static void process_nmi(struct kvm_vcpu *vcpu);
104 static void enter_smm(struct kvm_vcpu *vcpu);
105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
106 static void store_regs(struct kvm_vcpu *vcpu);
107 static int sync_regs(struct kvm_vcpu *vcpu);
109 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
110 EXPORT_SYMBOL_GPL(kvm_x86_ops);
112 static bool __read_mostly ignore_msrs = 0;
113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
115 static bool __read_mostly report_ignored_msrs = true;
116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
118 unsigned int min_timer_period_us = 200;
119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
121 static bool __read_mostly kvmclock_periodic_sync = true;
122 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
124 bool __read_mostly kvm_has_tsc_control;
125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
126 u32 __read_mostly kvm_max_guest_tsc_khz;
127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
128 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130 u64 __read_mostly kvm_max_tsc_scaling_ratio;
131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
132 u64 __read_mostly kvm_default_tsc_scaling_ratio;
133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
136 static u32 __read_mostly tsc_tolerance_ppm = 250;
137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
139 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
140 unsigned int __read_mostly lapic_timer_advance_ns = 1000;
141 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
142 EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
144 static bool __read_mostly vector_hashing = true;
145 module_param(vector_hashing, bool, S_IRUGO);
147 bool __read_mostly enable_vmware_backdoor = false;
148 module_param(enable_vmware_backdoor, bool, S_IRUGO);
149 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
151 static bool __read_mostly force_emulation_prefix = false;
152 module_param(force_emulation_prefix, bool, S_IRUGO);
154 #define KVM_NR_SHARED_MSRS 16
156 struct kvm_shared_msrs_global {
158 u32 msrs[KVM_NR_SHARED_MSRS];
161 struct kvm_shared_msrs {
162 struct user_return_notifier urn;
164 struct kvm_shared_msr_values {
167 } values[KVM_NR_SHARED_MSRS];
170 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
171 static struct kvm_shared_msrs __percpu *shared_msrs;
173 struct kvm_stats_debugfs_item debugfs_entries[] = {
174 { "pf_fixed", VCPU_STAT(pf_fixed) },
175 { "pf_guest", VCPU_STAT(pf_guest) },
176 { "tlb_flush", VCPU_STAT(tlb_flush) },
177 { "invlpg", VCPU_STAT(invlpg) },
178 { "exits", VCPU_STAT(exits) },
179 { "io_exits", VCPU_STAT(io_exits) },
180 { "mmio_exits", VCPU_STAT(mmio_exits) },
181 { "signal_exits", VCPU_STAT(signal_exits) },
182 { "irq_window", VCPU_STAT(irq_window_exits) },
183 { "nmi_window", VCPU_STAT(nmi_window_exits) },
184 { "halt_exits", VCPU_STAT(halt_exits) },
185 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
186 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
187 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
188 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
189 { "hypercalls", VCPU_STAT(hypercalls) },
190 { "request_irq", VCPU_STAT(request_irq_exits) },
191 { "irq_exits", VCPU_STAT(irq_exits) },
192 { "host_state_reload", VCPU_STAT(host_state_reload) },
193 { "fpu_reload", VCPU_STAT(fpu_reload) },
194 { "insn_emulation", VCPU_STAT(insn_emulation) },
195 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
196 { "irq_injections", VCPU_STAT(irq_injections) },
197 { "nmi_injections", VCPU_STAT(nmi_injections) },
198 { "req_event", VCPU_STAT(req_event) },
199 { "l1d_flush", VCPU_STAT(l1d_flush) },
200 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
201 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
202 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
203 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
204 { "mmu_flooded", VM_STAT(mmu_flooded) },
205 { "mmu_recycled", VM_STAT(mmu_recycled) },
206 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
207 { "mmu_unsync", VM_STAT(mmu_unsync) },
208 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
209 { "largepages", VM_STAT(lpages) },
210 { "max_mmu_page_hash_collisions",
211 VM_STAT(max_mmu_page_hash_collisions) },
215 u64 __read_mostly host_xcr0;
217 struct kmem_cache *x86_fpu_cache;
218 EXPORT_SYMBOL_GPL(x86_fpu_cache);
220 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
222 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
225 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
226 vcpu->arch.apf.gfns[i] = ~0;
229 static void kvm_on_user_return(struct user_return_notifier *urn)
232 struct kvm_shared_msrs *locals
233 = container_of(urn, struct kvm_shared_msrs, urn);
234 struct kvm_shared_msr_values *values;
238 * Disabling irqs at this point since the following code could be
239 * interrupted and executed through kvm_arch_hardware_disable()
241 local_irq_save(flags);
242 if (locals->registered) {
243 locals->registered = false;
244 user_return_notifier_unregister(urn);
246 local_irq_restore(flags);
247 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
248 values = &locals->values[slot];
249 if (values->host != values->curr) {
250 wrmsrl(shared_msrs_global.msrs[slot], values->host);
251 values->curr = values->host;
256 static void shared_msr_update(unsigned slot, u32 msr)
259 unsigned int cpu = smp_processor_id();
260 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
262 /* only read, and nobody should modify it at this time,
263 * so don't need lock */
264 if (slot >= shared_msrs_global.nr) {
265 printk(KERN_ERR "kvm: invalid MSR slot!");
268 rdmsrl_safe(msr, &value);
269 smsr->values[slot].host = value;
270 smsr->values[slot].curr = value;
273 void kvm_define_shared_msr(unsigned slot, u32 msr)
275 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
276 shared_msrs_global.msrs[slot] = msr;
277 if (slot >= shared_msrs_global.nr)
278 shared_msrs_global.nr = slot + 1;
280 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
282 static void kvm_shared_msr_cpu_online(void)
286 for (i = 0; i < shared_msrs_global.nr; ++i)
287 shared_msr_update(i, shared_msrs_global.msrs[i]);
290 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
292 unsigned int cpu = smp_processor_id();
293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
296 if (((value ^ smsr->values[slot].curr) & mask) == 0)
298 smsr->values[slot].curr = value;
299 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
303 if (!smsr->registered) {
304 smsr->urn.on_user_return = kvm_on_user_return;
305 user_return_notifier_register(&smsr->urn);
306 smsr->registered = true;
310 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
312 static void drop_user_return_notifiers(void)
314 unsigned int cpu = smp_processor_id();
315 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
317 if (smsr->registered)
318 kvm_on_user_return(&smsr->urn);
321 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
323 return vcpu->arch.apic_base;
325 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
327 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
329 return kvm_apic_mode(kvm_get_apic_base(vcpu));
331 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
333 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
335 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
336 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
337 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
338 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
340 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
342 if (!msr_info->host_initiated) {
343 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
345 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
349 kvm_lapic_set_base(vcpu, msr_info->data);
352 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
354 asmlinkage __visible void kvm_spurious_fault(void)
356 /* Fault while not rebooting. We want the trace. */
359 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
361 #define EXCPT_BENIGN 0
362 #define EXCPT_CONTRIBUTORY 1
365 static int exception_class(int vector)
375 return EXCPT_CONTRIBUTORY;
382 #define EXCPT_FAULT 0
384 #define EXCPT_ABORT 2
385 #define EXCPT_INTERRUPT 3
387 static int exception_type(int vector)
391 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
392 return EXCPT_INTERRUPT;
396 /* #DB is trap, as instruction watchpoints are handled elsewhere */
397 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
400 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
403 /* Reserved exceptions will result in fault */
407 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
409 unsigned nr = vcpu->arch.exception.nr;
410 bool has_payload = vcpu->arch.exception.has_payload;
411 unsigned long payload = vcpu->arch.exception.payload;
419 * "Certain debug exceptions may clear bit 0-3. The
420 * remaining contents of the DR6 register are never
421 * cleared by the processor".
423 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
425 * DR6.RTM is set by all #DB exceptions that don't clear it.
427 vcpu->arch.dr6 |= DR6_RTM;
428 vcpu->arch.dr6 |= payload;
430 * Bit 16 should be set in the payload whenever the #DB
431 * exception should clear DR6.RTM. This makes the payload
432 * compatible with the pending debug exceptions under VMX.
433 * Though not currently documented in the SDM, this also
434 * makes the payload compatible with the exit qualification
435 * for #DB exceptions under VMX.
437 vcpu->arch.dr6 ^= payload & DR6_RTM;
440 vcpu->arch.cr2 = payload;
444 vcpu->arch.exception.has_payload = false;
445 vcpu->arch.exception.payload = 0;
447 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
449 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
450 unsigned nr, bool has_error, u32 error_code,
451 bool has_payload, unsigned long payload, bool reinject)
456 kvm_make_request(KVM_REQ_EVENT, vcpu);
458 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
460 if (has_error && !is_protmode(vcpu))
464 * On vmentry, vcpu->arch.exception.pending is only
465 * true if an event injection was blocked by
466 * nested_run_pending. In that case, however,
467 * vcpu_enter_guest requests an immediate exit,
468 * and the guest shouldn't proceed far enough to
471 WARN_ON_ONCE(vcpu->arch.exception.pending);
472 vcpu->arch.exception.injected = true;
473 if (WARN_ON_ONCE(has_payload)) {
475 * A reinjected event has already
476 * delivered its payload.
482 vcpu->arch.exception.pending = true;
483 vcpu->arch.exception.injected = false;
485 vcpu->arch.exception.has_error_code = has_error;
486 vcpu->arch.exception.nr = nr;
487 vcpu->arch.exception.error_code = error_code;
488 vcpu->arch.exception.has_payload = has_payload;
489 vcpu->arch.exception.payload = payload;
491 * In guest mode, payload delivery should be deferred,
492 * so that the L1 hypervisor can intercept #PF before
493 * CR2 is modified (or intercept #DB before DR6 is
494 * modified under nVMX). However, for ABI
495 * compatibility with KVM_GET_VCPU_EVENTS and
496 * KVM_SET_VCPU_EVENTS, we can't delay payload
497 * delivery unless userspace has enabled this
498 * functionality via the per-VM capability,
499 * KVM_CAP_EXCEPTION_PAYLOAD.
501 if (!vcpu->kvm->arch.exception_payload_enabled ||
502 !is_guest_mode(vcpu))
503 kvm_deliver_exception_payload(vcpu);
507 /* to check exception */
508 prev_nr = vcpu->arch.exception.nr;
509 if (prev_nr == DF_VECTOR) {
510 /* triple fault -> shutdown */
511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
514 class1 = exception_class(prev_nr);
515 class2 = exception_class(nr);
516 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
517 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
519 * Generate double fault per SDM Table 5-5. Set
520 * exception.pending = true so that the double fault
521 * can trigger a nested vmexit.
523 vcpu->arch.exception.pending = true;
524 vcpu->arch.exception.injected = false;
525 vcpu->arch.exception.has_error_code = true;
526 vcpu->arch.exception.nr = DF_VECTOR;
527 vcpu->arch.exception.error_code = 0;
528 vcpu->arch.exception.has_payload = false;
529 vcpu->arch.exception.payload = 0;
531 /* replace previous exception with a new one in a hope
532 that instruction re-execution will regenerate lost
537 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
539 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
541 EXPORT_SYMBOL_GPL(kvm_queue_exception);
543 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
547 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
549 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
550 unsigned long payload)
552 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
555 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
556 u32 error_code, unsigned long payload)
558 kvm_multiple_exception(vcpu, nr, true, error_code,
559 true, payload, false);
562 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
565 kvm_inject_gp(vcpu, 0);
567 return kvm_skip_emulated_instruction(vcpu);
571 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
573 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
575 ++vcpu->stat.pf_guest;
576 vcpu->arch.exception.nested_apf =
577 is_guest_mode(vcpu) && fault->async_page_fault;
578 if (vcpu->arch.exception.nested_apf) {
579 vcpu->arch.apf.nested_apf_token = fault->address;
580 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
582 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
586 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
588 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
590 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
591 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
593 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
595 return fault->nested_page_fault;
598 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
600 atomic_inc(&vcpu->arch.nmi_queued);
601 kvm_make_request(KVM_REQ_NMI, vcpu);
603 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
605 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
607 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
609 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
611 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
615 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
618 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
619 * a #GP and return false.
621 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
623 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
625 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
628 EXPORT_SYMBOL_GPL(kvm_require_cpl);
630 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
632 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
635 kvm_queue_exception(vcpu, UD_VECTOR);
638 EXPORT_SYMBOL_GPL(kvm_require_dr);
641 * This function will be used to read from the physical memory of the currently
642 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
643 * can read from guest physical or from the guest's guest physical memory.
645 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
646 gfn_t ngfn, void *data, int offset, int len,
649 struct x86_exception exception;
653 ngpa = gfn_to_gpa(ngfn);
654 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
655 if (real_gfn == UNMAPPED_GVA)
658 real_gfn = gpa_to_gfn(real_gfn);
660 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
662 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
664 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
665 void *data, int offset, int len, u32 access)
667 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
668 data, offset, len, access);
672 * Load the pae pdptrs. Return true is they are all valid.
674 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
676 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
677 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
680 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
682 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
683 offset * sizeof(u64), sizeof(pdpte),
684 PFERR_USER_MASK|PFERR_WRITE_MASK);
689 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
690 if ((pdpte[i] & PT_PRESENT_MASK) &&
692 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
699 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
700 __set_bit(VCPU_EXREG_PDPTR,
701 (unsigned long *)&vcpu->arch.regs_avail);
702 __set_bit(VCPU_EXREG_PDPTR,
703 (unsigned long *)&vcpu->arch.regs_dirty);
708 EXPORT_SYMBOL_GPL(load_pdptrs);
710 bool pdptrs_changed(struct kvm_vcpu *vcpu)
712 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
718 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
721 if (!test_bit(VCPU_EXREG_PDPTR,
722 (unsigned long *)&vcpu->arch.regs_avail))
725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
731 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
736 EXPORT_SYMBOL_GPL(pdptrs_changed);
738 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
740 unsigned long old_cr0 = kvm_read_cr0(vcpu);
741 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
746 if (cr0 & 0xffffffff00000000UL)
750 cr0 &= ~CR0_RESERVED_BITS;
752 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
755 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
758 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
760 if ((vcpu->arch.efer & EFER_LME)) {
765 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
770 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
778 kvm_x86_ops->set_cr0(vcpu, cr0);
780 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
781 kvm_clear_async_pf_completion_queue(vcpu);
782 kvm_async_pf_hash_reset(vcpu);
785 if ((cr0 ^ old_cr0) & update_bits)
786 kvm_mmu_reset_context(vcpu);
788 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
789 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
790 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
791 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
795 EXPORT_SYMBOL_GPL(kvm_set_cr0);
797 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
799 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
801 EXPORT_SYMBOL_GPL(kvm_lmsw);
803 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
805 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
806 !vcpu->guest_xcr0_loaded) {
807 /* kvm_set_xcr() also depends on this */
808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
810 vcpu->guest_xcr0_loaded = 1;
813 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
815 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
817 if (vcpu->guest_xcr0_loaded) {
818 if (vcpu->arch.xcr0 != host_xcr0)
819 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
820 vcpu->guest_xcr0_loaded = 0;
823 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
825 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
828 u64 old_xcr0 = vcpu->arch.xcr0;
831 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
832 if (index != XCR_XFEATURE_ENABLED_MASK)
834 if (!(xcr0 & XFEATURE_MASK_FP))
836 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
840 * Do not allow the guest to set bits that we do not support
841 * saving. However, xcr0 bit 0 is always set, even if the
842 * emulated CPU does not support XSAVE (see fx_init).
844 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
845 if (xcr0 & ~valid_bits)
848 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
849 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
852 if (xcr0 & XFEATURE_MASK_AVX512) {
853 if (!(xcr0 & XFEATURE_MASK_YMM))
855 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
858 vcpu->arch.xcr0 = xcr0;
860 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
861 kvm_update_cpuid(vcpu);
865 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
867 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
868 __kvm_set_xcr(vcpu, index, xcr)) {
869 kvm_inject_gp(vcpu, 0);
874 EXPORT_SYMBOL_GPL(kvm_set_xcr);
876 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
878 unsigned long old_cr4 = kvm_read_cr4(vcpu);
879 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
880 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
882 if (cr4 & CR4_RESERVED_BITS)
885 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
888 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
891 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
894 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
897 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
900 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
903 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
906 if (is_long_mode(vcpu)) {
907 if (!(cr4 & X86_CR4_PAE))
909 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
910 && ((cr4 ^ old_cr4) & pdptr_bits)
911 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
915 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
916 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
919 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
920 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
924 if (kvm_x86_ops->set_cr4(vcpu, cr4))
927 if (((cr4 ^ old_cr4) & pdptr_bits) ||
928 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
929 kvm_mmu_reset_context(vcpu);
931 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
932 kvm_update_cpuid(vcpu);
936 EXPORT_SYMBOL_GPL(kvm_set_cr4);
938 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
940 bool skip_tlb_flush = false;
942 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
945 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
946 cr3 &= ~X86_CR3_PCID_NOFLUSH;
950 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
951 if (!skip_tlb_flush) {
952 kvm_mmu_sync_roots(vcpu);
953 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
958 if (is_long_mode(vcpu) &&
959 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
961 else if (is_pae(vcpu) && is_paging(vcpu) &&
962 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
965 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
966 vcpu->arch.cr3 = cr3;
967 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
971 EXPORT_SYMBOL_GPL(kvm_set_cr3);
973 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
975 if (cr8 & CR8_RESERVED_BITS)
977 if (lapic_in_kernel(vcpu))
978 kvm_lapic_set_tpr(vcpu, cr8);
980 vcpu->arch.cr8 = cr8;
983 EXPORT_SYMBOL_GPL(kvm_set_cr8);
985 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
987 if (lapic_in_kernel(vcpu))
988 return kvm_lapic_get_cr8(vcpu);
990 return vcpu->arch.cr8;
992 EXPORT_SYMBOL_GPL(kvm_get_cr8);
994 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
998 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
999 for (i = 0; i < KVM_NR_DB_REGS; i++)
1000 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1001 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1005 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1007 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1008 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1011 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1015 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1016 dr7 = vcpu->arch.guest_debug_dr7;
1018 dr7 = vcpu->arch.dr7;
1019 kvm_x86_ops->set_dr7(vcpu, dr7);
1020 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1021 if (dr7 & DR7_BP_EN_MASK)
1022 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1025 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1027 u64 fixed = DR6_FIXED_1;
1029 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1034 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1038 vcpu->arch.db[dr] = val;
1039 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1040 vcpu->arch.eff_db[dr] = val;
1045 if (val & 0xffffffff00000000ULL)
1046 return -1; /* #GP */
1047 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1048 kvm_update_dr6(vcpu);
1053 if (val & 0xffffffff00000000ULL)
1054 return -1; /* #GP */
1055 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1056 kvm_update_dr7(vcpu);
1063 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1065 if (__kvm_set_dr(vcpu, dr, val)) {
1066 kvm_inject_gp(vcpu, 0);
1071 EXPORT_SYMBOL_GPL(kvm_set_dr);
1073 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1077 *val = vcpu->arch.db[dr];
1082 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1083 *val = vcpu->arch.dr6;
1085 *val = kvm_x86_ops->get_dr6(vcpu);
1090 *val = vcpu->arch.dr7;
1095 EXPORT_SYMBOL_GPL(kvm_get_dr);
1097 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1099 u32 ecx = kvm_rcx_read(vcpu);
1103 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1106 kvm_rax_write(vcpu, (u32)data);
1107 kvm_rdx_write(vcpu, data >> 32);
1110 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1113 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1114 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1116 * This list is modified at module load time to reflect the
1117 * capabilities of the host cpu. This capabilities test skips MSRs that are
1118 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1119 * may depend on host virtualization features rather than host cpu features.
1122 static u32 msrs_to_save[] = {
1123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1125 #ifdef CONFIG_X86_64
1126 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1128 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1129 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1131 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1132 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1133 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1134 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1135 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1136 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1139 static unsigned num_msrs_to_save;
1141 static u32 emulated_msrs[] = {
1142 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1143 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1144 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1145 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1146 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1147 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1148 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1150 HV_X64_MSR_VP_INDEX,
1151 HV_X64_MSR_VP_RUNTIME,
1152 HV_X64_MSR_SCONTROL,
1153 HV_X64_MSR_STIMER0_CONFIG,
1154 HV_X64_MSR_VP_ASSIST_PAGE,
1155 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1156 HV_X64_MSR_TSC_EMULATION_STATUS,
1158 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1161 MSR_IA32_TSC_ADJUST,
1162 MSR_IA32_TSCDEADLINE,
1163 MSR_IA32_ARCH_CAPABILITIES,
1164 MSR_IA32_MISC_ENABLE,
1165 MSR_IA32_MCG_STATUS,
1167 MSR_IA32_MCG_EXT_CTL,
1171 MSR_MISC_FEATURES_ENABLES,
1172 MSR_AMD64_VIRT_SPEC_CTRL,
1178 static unsigned num_emulated_msrs;
1181 * List of msr numbers which are used to expose MSR-based features that
1182 * can be used by a hypervisor to validate requested CPU features.
1184 static u32 msr_based_features[] = {
1186 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1187 MSR_IA32_VMX_PINBASED_CTLS,
1188 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1189 MSR_IA32_VMX_PROCBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1191 MSR_IA32_VMX_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1193 MSR_IA32_VMX_ENTRY_CTLS,
1195 MSR_IA32_VMX_CR0_FIXED0,
1196 MSR_IA32_VMX_CR0_FIXED1,
1197 MSR_IA32_VMX_CR4_FIXED0,
1198 MSR_IA32_VMX_CR4_FIXED1,
1199 MSR_IA32_VMX_VMCS_ENUM,
1200 MSR_IA32_VMX_PROCBASED_CTLS2,
1201 MSR_IA32_VMX_EPT_VPID_CAP,
1202 MSR_IA32_VMX_VMFUNC,
1206 MSR_IA32_ARCH_CAPABILITIES,
1209 static unsigned int num_msr_based_features;
1211 u64 kvm_get_arch_capabilities(void)
1215 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1218 * If we're doing cache flushes (either "always" or "cond")
1219 * we will do one whenever the guest does a vmlaunch/vmresume.
1220 * If an outer hypervisor is doing the cache flush for us
1221 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1222 * capability to the guest too, and if EPT is disabled we're not
1223 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1224 * require a nested hypervisor to do a flush of its own.
1226 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1227 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1231 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1233 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1235 switch (msr->index) {
1236 case MSR_IA32_ARCH_CAPABILITIES:
1237 msr->data = kvm_get_arch_capabilities();
1239 case MSR_IA32_UCODE_REV:
1240 rdmsrl_safe(msr->index, &msr->data);
1243 if (kvm_x86_ops->get_msr_feature(msr))
1249 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1251 struct kvm_msr_entry msr;
1255 r = kvm_get_msr_feature(&msr);
1264 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1266 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1269 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1272 if (efer & (EFER_LME | EFER_LMA) &&
1273 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1276 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1282 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1284 if (efer & efer_reserved_bits)
1287 return __kvm_valid_efer(vcpu, efer);
1289 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1291 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1293 u64 old_efer = vcpu->arch.efer;
1294 u64 efer = msr_info->data;
1296 if (efer & efer_reserved_bits)
1299 if (!msr_info->host_initiated) {
1300 if (!__kvm_valid_efer(vcpu, efer))
1303 if (is_paging(vcpu) &&
1304 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1309 efer |= vcpu->arch.efer & EFER_LMA;
1311 kvm_x86_ops->set_efer(vcpu, efer);
1313 /* Update reserved bits */
1314 if ((efer ^ old_efer) & EFER_NX)
1315 kvm_mmu_reset_context(vcpu);
1320 void kvm_enable_efer_bits(u64 mask)
1322 efer_reserved_bits &= ~mask;
1324 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1327 * Writes msr value into into the appropriate "register".
1328 * Returns 0 on success, non-0 otherwise.
1329 * Assumes vcpu_load() was already called.
1331 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1333 switch (msr->index) {
1336 case MSR_KERNEL_GS_BASE:
1339 if (is_noncanonical_address(msr->data, vcpu))
1342 case MSR_IA32_SYSENTER_EIP:
1343 case MSR_IA32_SYSENTER_ESP:
1345 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1346 * non-canonical address is written on Intel but not on
1347 * AMD (which ignores the top 32-bits, because it does
1348 * not implement 64-bit SYSENTER).
1350 * 64-bit code should hence be able to write a non-canonical
1351 * value on AMD. Making the address canonical ensures that
1352 * vmentry does not fail on Intel after writing a non-canonical
1353 * value, and that something deterministic happens if the guest
1354 * invokes 64-bit SYSENTER.
1356 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1358 return kvm_x86_ops->set_msr(vcpu, msr);
1360 EXPORT_SYMBOL_GPL(kvm_set_msr);
1363 * Adapt set_msr() to msr_io()'s calling convention
1365 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1367 struct msr_data msr;
1371 msr.host_initiated = true;
1372 r = kvm_get_msr(vcpu, &msr);
1380 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1382 struct msr_data msr;
1386 msr.host_initiated = true;
1387 return kvm_set_msr(vcpu, &msr);
1390 #ifdef CONFIG_X86_64
1391 struct pvclock_gtod_data {
1394 struct { /* extract of a clocksource struct */
1407 static struct pvclock_gtod_data pvclock_gtod_data;
1409 static void update_pvclock_gtod(struct timekeeper *tk)
1411 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1414 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1416 write_seqcount_begin(&vdata->seq);
1418 /* copy pvclock gtod data */
1419 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1420 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1421 vdata->clock.mask = tk->tkr_mono.mask;
1422 vdata->clock.mult = tk->tkr_mono.mult;
1423 vdata->clock.shift = tk->tkr_mono.shift;
1425 vdata->boot_ns = boot_ns;
1426 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1428 vdata->wall_time_sec = tk->xtime_sec;
1430 write_seqcount_end(&vdata->seq);
1434 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1437 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1438 * vcpu_enter_guest. This function is only called from
1439 * the physical CPU that is running vcpu.
1441 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1444 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1448 struct pvclock_wall_clock wc;
1449 struct timespec64 boot;
1454 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1459 ++version; /* first time write, random junk */
1463 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1467 * The guest calculates current wall clock time by adding
1468 * system time (updated by kvm_guest_time_update below) to the
1469 * wall clock specified here. guest system time equals host
1470 * system time for us, thus we must fill in host boot time here.
1472 getboottime64(&boot);
1474 if (kvm->arch.kvmclock_offset) {
1475 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1476 boot = timespec64_sub(boot, ts);
1478 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1479 wc.nsec = boot.tv_nsec;
1480 wc.version = version;
1482 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1485 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1488 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1490 do_shl32_div32(dividend, divisor);
1494 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1495 s8 *pshift, u32 *pmultiplier)
1503 scaled64 = scaled_hz;
1504 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1509 tps32 = (uint32_t)tps64;
1510 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1511 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1519 *pmultiplier = div_frac(scaled64, tps32);
1521 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1522 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1525 #ifdef CONFIG_X86_64
1526 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1529 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1530 static unsigned long max_tsc_khz;
1532 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1534 u64 v = (u64)khz * (1000000 + ppm);
1539 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1543 /* Guest TSC same frequency as host TSC? */
1545 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1549 /* TSC scaling supported? */
1550 if (!kvm_has_tsc_control) {
1551 if (user_tsc_khz > tsc_khz) {
1552 vcpu->arch.tsc_catchup = 1;
1553 vcpu->arch.tsc_always_catchup = 1;
1556 WARN(1, "user requested TSC rate below hardware speed\n");
1561 /* TSC scaling required - calculate ratio */
1562 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1563 user_tsc_khz, tsc_khz);
1565 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1566 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1571 vcpu->arch.tsc_scaling_ratio = ratio;
1575 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1577 u32 thresh_lo, thresh_hi;
1578 int use_scaling = 0;
1580 /* tsc_khz can be zero if TSC calibration fails */
1581 if (user_tsc_khz == 0) {
1582 /* set tsc_scaling_ratio to a safe value */
1583 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1587 /* Compute a scale to convert nanoseconds in TSC cycles */
1588 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1589 &vcpu->arch.virtual_tsc_shift,
1590 &vcpu->arch.virtual_tsc_mult);
1591 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1594 * Compute the variation in TSC rate which is acceptable
1595 * within the range of tolerance and decide if the
1596 * rate being applied is within that bounds of the hardware
1597 * rate. If so, no scaling or compensation need be done.
1599 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1600 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1601 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1602 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1605 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1608 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1610 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1611 vcpu->arch.virtual_tsc_mult,
1612 vcpu->arch.virtual_tsc_shift);
1613 tsc += vcpu->arch.this_tsc_write;
1617 static inline int gtod_is_based_on_tsc(int mode)
1619 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1622 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1624 #ifdef CONFIG_X86_64
1626 struct kvm_arch *ka = &vcpu->kvm->arch;
1627 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1629 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1630 atomic_read(&vcpu->kvm->online_vcpus));
1633 * Once the masterclock is enabled, always perform request in
1634 * order to update it.
1636 * In order to enable masterclock, the host clocksource must be TSC
1637 * and the vcpus need to have matched TSCs. When that happens,
1638 * perform request to enable masterclock.
1640 if (ka->use_master_clock ||
1641 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1642 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1644 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1645 atomic_read(&vcpu->kvm->online_vcpus),
1646 ka->use_master_clock, gtod->clock.vclock_mode);
1650 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1652 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1653 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1657 * Multiply tsc by a fixed point number represented by ratio.
1659 * The most significant 64-N bits (mult) of ratio represent the
1660 * integral part of the fixed point number; the remaining N bits
1661 * (frac) represent the fractional part, ie. ratio represents a fixed
1662 * point number (mult + frac * 2^(-N)).
1664 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1666 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1668 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1671 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1674 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1676 if (ratio != kvm_default_tsc_scaling_ratio)
1677 _tsc = __scale_tsc(ratio, tsc);
1681 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1683 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1687 tsc = kvm_scale_tsc(vcpu, rdtsc());
1689 return target_tsc - tsc;
1692 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1694 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1696 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1698 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1700 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1702 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1705 static inline bool kvm_check_tsc_unstable(void)
1707 #ifdef CONFIG_X86_64
1709 * TSC is marked unstable when we're running on Hyper-V,
1710 * 'TSC page' clocksource is good.
1712 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1715 return check_tsc_unstable();
1718 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1720 struct kvm *kvm = vcpu->kvm;
1721 u64 offset, ns, elapsed;
1722 unsigned long flags;
1724 bool already_matched;
1725 u64 data = msr->data;
1726 bool synchronizing = false;
1728 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1729 offset = kvm_compute_tsc_offset(vcpu, data);
1730 ns = ktime_get_boot_ns();
1731 elapsed = ns - kvm->arch.last_tsc_nsec;
1733 if (vcpu->arch.virtual_tsc_khz) {
1734 if (data == 0 && msr->host_initiated) {
1736 * detection of vcpu initialization -- need to sync
1737 * with other vCPUs. This particularly helps to keep
1738 * kvm_clock stable after CPU hotplug
1740 synchronizing = true;
1742 u64 tsc_exp = kvm->arch.last_tsc_write +
1743 nsec_to_cycles(vcpu, elapsed);
1744 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1746 * Special case: TSC write with a small delta (1 second)
1747 * of virtual cycle time against real time is
1748 * interpreted as an attempt to synchronize the CPU.
1750 synchronizing = data < tsc_exp + tsc_hz &&
1751 data + tsc_hz > tsc_exp;
1756 * For a reliable TSC, we can match TSC offsets, and for an unstable
1757 * TSC, we add elapsed time in this computation. We could let the
1758 * compensation code attempt to catch up if we fall behind, but
1759 * it's better to try to match offsets from the beginning.
1761 if (synchronizing &&
1762 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1763 if (!kvm_check_tsc_unstable()) {
1764 offset = kvm->arch.cur_tsc_offset;
1765 pr_debug("kvm: matched tsc offset for %llu\n", data);
1767 u64 delta = nsec_to_cycles(vcpu, elapsed);
1769 offset = kvm_compute_tsc_offset(vcpu, data);
1770 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1773 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1776 * We split periods of matched TSC writes into generations.
1777 * For each generation, we track the original measured
1778 * nanosecond time, offset, and write, so if TSCs are in
1779 * sync, we can match exact offset, and if not, we can match
1780 * exact software computation in compute_guest_tsc()
1782 * These values are tracked in kvm->arch.cur_xxx variables.
1784 kvm->arch.cur_tsc_generation++;
1785 kvm->arch.cur_tsc_nsec = ns;
1786 kvm->arch.cur_tsc_write = data;
1787 kvm->arch.cur_tsc_offset = offset;
1789 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1790 kvm->arch.cur_tsc_generation, data);
1794 * We also track th most recent recorded KHZ, write and time to
1795 * allow the matching interval to be extended at each write.
1797 kvm->arch.last_tsc_nsec = ns;
1798 kvm->arch.last_tsc_write = data;
1799 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1801 vcpu->arch.last_guest_tsc = data;
1803 /* Keep track of which generation this VCPU has synchronized to */
1804 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1805 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1806 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1808 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1809 update_ia32_tsc_adjust_msr(vcpu, offset);
1811 kvm_vcpu_write_tsc_offset(vcpu, offset);
1812 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1814 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1816 kvm->arch.nr_vcpus_matched_tsc = 0;
1817 } else if (!already_matched) {
1818 kvm->arch.nr_vcpus_matched_tsc++;
1821 kvm_track_tsc_matching(vcpu);
1822 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1825 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1827 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1830 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1831 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1834 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1836 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1837 WARN_ON(adjustment < 0);
1838 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1839 adjust_tsc_offset_guest(vcpu, adjustment);
1842 #ifdef CONFIG_X86_64
1844 static u64 read_tsc(void)
1846 u64 ret = (u64)rdtsc_ordered();
1847 u64 last = pvclock_gtod_data.clock.cycle_last;
1849 if (likely(ret >= last))
1853 * GCC likes to generate cmov here, but this branch is extremely
1854 * predictable (it's just a function of time and the likely is
1855 * very likely) and there's a data dependence, so force GCC
1856 * to generate a branch instead. I don't barrier() because
1857 * we don't actually need a barrier, and if this function
1858 * ever gets inlined it will generate worse code.
1864 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1867 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1870 switch (gtod->clock.vclock_mode) {
1871 case VCLOCK_HVCLOCK:
1872 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1874 if (tsc_pg_val != U64_MAX) {
1875 /* TSC page valid */
1876 *mode = VCLOCK_HVCLOCK;
1877 v = (tsc_pg_val - gtod->clock.cycle_last) &
1880 /* TSC page invalid */
1881 *mode = VCLOCK_NONE;
1886 *tsc_timestamp = read_tsc();
1887 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1891 *mode = VCLOCK_NONE;
1894 if (*mode == VCLOCK_NONE)
1895 *tsc_timestamp = v = 0;
1897 return v * gtod->clock.mult;
1900 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1902 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1908 seq = read_seqcount_begin(>od->seq);
1909 ns = gtod->nsec_base;
1910 ns += vgettsc(tsc_timestamp, &mode);
1911 ns >>= gtod->clock.shift;
1912 ns += gtod->boot_ns;
1913 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1919 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1921 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1927 seq = read_seqcount_begin(>od->seq);
1928 ts->tv_sec = gtod->wall_time_sec;
1929 ns = gtod->nsec_base;
1930 ns += vgettsc(tsc_timestamp, &mode);
1931 ns >>= gtod->clock.shift;
1932 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1934 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1940 /* returns true if host is using TSC based clocksource */
1941 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1943 /* checked again under seqlock below */
1944 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1947 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1951 /* returns true if host is using TSC based clocksource */
1952 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1955 /* checked again under seqlock below */
1956 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1959 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1965 * Assuming a stable TSC across physical CPUS, and a stable TSC
1966 * across virtual CPUs, the following condition is possible.
1967 * Each numbered line represents an event visible to both
1968 * CPUs at the next numbered event.
1970 * "timespecX" represents host monotonic time. "tscX" represents
1973 * VCPU0 on CPU0 | VCPU1 on CPU1
1975 * 1. read timespec0,tsc0
1976 * 2. | timespec1 = timespec0 + N
1978 * 3. transition to guest | transition to guest
1979 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1980 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1981 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1983 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1986 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1988 * - 0 < N - M => M < N
1990 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1991 * always the case (the difference between two distinct xtime instances
1992 * might be smaller then the difference between corresponding TSC reads,
1993 * when updating guest vcpus pvclock areas).
1995 * To avoid that problem, do not allow visibility of distinct
1996 * system_timestamp/tsc_timestamp values simultaneously: use a master
1997 * copy of host monotonic time values. Update that master copy
2000 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2004 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2006 #ifdef CONFIG_X86_64
2007 struct kvm_arch *ka = &kvm->arch;
2009 bool host_tsc_clocksource, vcpus_matched;
2011 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2012 atomic_read(&kvm->online_vcpus));
2015 * If the host uses TSC clock, then passthrough TSC as stable
2018 host_tsc_clocksource = kvm_get_time_and_clockread(
2019 &ka->master_kernel_ns,
2020 &ka->master_cycle_now);
2022 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2023 && !ka->backwards_tsc_observed
2024 && !ka->boot_vcpu_runs_old_kvmclock;
2026 if (ka->use_master_clock)
2027 atomic_set(&kvm_guest_has_master_clock, 1);
2029 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2030 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2035 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2037 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2040 static void kvm_gen_update_masterclock(struct kvm *kvm)
2042 #ifdef CONFIG_X86_64
2044 struct kvm_vcpu *vcpu;
2045 struct kvm_arch *ka = &kvm->arch;
2047 spin_lock(&ka->pvclock_gtod_sync_lock);
2048 kvm_make_mclock_inprogress_request(kvm);
2049 /* no guest entries from this point */
2050 pvclock_update_vm_gtod_copy(kvm);
2052 kvm_for_each_vcpu(i, vcpu, kvm)
2053 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2055 /* guest entries allowed */
2056 kvm_for_each_vcpu(i, vcpu, kvm)
2057 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2059 spin_unlock(&ka->pvclock_gtod_sync_lock);
2063 u64 get_kvmclock_ns(struct kvm *kvm)
2065 struct kvm_arch *ka = &kvm->arch;
2066 struct pvclock_vcpu_time_info hv_clock;
2069 spin_lock(&ka->pvclock_gtod_sync_lock);
2070 if (!ka->use_master_clock) {
2071 spin_unlock(&ka->pvclock_gtod_sync_lock);
2072 return ktime_get_boot_ns() + ka->kvmclock_offset;
2075 hv_clock.tsc_timestamp = ka->master_cycle_now;
2076 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2077 spin_unlock(&ka->pvclock_gtod_sync_lock);
2079 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2082 if (__this_cpu_read(cpu_tsc_khz)) {
2083 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2084 &hv_clock.tsc_shift,
2085 &hv_clock.tsc_to_system_mul);
2086 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2088 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
2095 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2097 struct kvm_vcpu_arch *vcpu = &v->arch;
2098 struct pvclock_vcpu_time_info guest_hv_clock;
2100 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2101 &guest_hv_clock, sizeof(guest_hv_clock))))
2104 /* This VCPU is paused, but it's legal for a guest to read another
2105 * VCPU's kvmclock, so we really have to follow the specification where
2106 * it says that version is odd if data is being modified, and even after
2109 * Version field updates must be kept separate. This is because
2110 * kvm_write_guest_cached might use a "rep movs" instruction, and
2111 * writes within a string instruction are weakly ordered. So there
2112 * are three writes overall.
2114 * As a small optimization, only write the version field in the first
2115 * and third write. The vcpu->pv_time cache is still valid, because the
2116 * version field is the first in the struct.
2118 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2120 if (guest_hv_clock.version & 1)
2121 ++guest_hv_clock.version; /* first time write, random junk */
2123 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2124 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2126 sizeof(vcpu->hv_clock.version));
2130 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2131 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2133 if (vcpu->pvclock_set_guest_stopped_request) {
2134 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2135 vcpu->pvclock_set_guest_stopped_request = false;
2138 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2140 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2142 sizeof(vcpu->hv_clock));
2146 vcpu->hv_clock.version++;
2147 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2149 sizeof(vcpu->hv_clock.version));
2152 static int kvm_guest_time_update(struct kvm_vcpu *v)
2154 unsigned long flags, tgt_tsc_khz;
2155 struct kvm_vcpu_arch *vcpu = &v->arch;
2156 struct kvm_arch *ka = &v->kvm->arch;
2158 u64 tsc_timestamp, host_tsc;
2160 bool use_master_clock;
2166 * If the host uses TSC clock, then passthrough TSC as stable
2169 spin_lock(&ka->pvclock_gtod_sync_lock);
2170 use_master_clock = ka->use_master_clock;
2171 if (use_master_clock) {
2172 host_tsc = ka->master_cycle_now;
2173 kernel_ns = ka->master_kernel_ns;
2175 spin_unlock(&ka->pvclock_gtod_sync_lock);
2177 /* Keep irq disabled to prevent changes to the clock */
2178 local_irq_save(flags);
2179 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2180 if (unlikely(tgt_tsc_khz == 0)) {
2181 local_irq_restore(flags);
2182 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2185 if (!use_master_clock) {
2187 kernel_ns = ktime_get_boot_ns();
2190 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2193 * We may have to catch up the TSC to match elapsed wall clock
2194 * time for two reasons, even if kvmclock is used.
2195 * 1) CPU could have been running below the maximum TSC rate
2196 * 2) Broken TSC compensation resets the base at each VCPU
2197 * entry to avoid unknown leaps of TSC even when running
2198 * again on the same CPU. This may cause apparent elapsed
2199 * time to disappear, and the guest to stand still or run
2202 if (vcpu->tsc_catchup) {
2203 u64 tsc = compute_guest_tsc(v, kernel_ns);
2204 if (tsc > tsc_timestamp) {
2205 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2206 tsc_timestamp = tsc;
2210 local_irq_restore(flags);
2212 /* With all the info we got, fill in the values */
2214 if (kvm_has_tsc_control)
2215 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2217 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2218 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2219 &vcpu->hv_clock.tsc_shift,
2220 &vcpu->hv_clock.tsc_to_system_mul);
2221 vcpu->hw_tsc_khz = tgt_tsc_khz;
2224 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2225 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2226 vcpu->last_guest_tsc = tsc_timestamp;
2228 /* If the host uses TSC clocksource, then it is stable */
2230 if (use_master_clock)
2231 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2233 vcpu->hv_clock.flags = pvclock_flags;
2235 if (vcpu->pv_time_enabled)
2236 kvm_setup_pvclock_page(v);
2237 if (v == kvm_get_vcpu(v->kvm, 0))
2238 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2243 * kvmclock updates which are isolated to a given vcpu, such as
2244 * vcpu->cpu migration, should not allow system_timestamp from
2245 * the rest of the vcpus to remain static. Otherwise ntp frequency
2246 * correction applies to one vcpu's system_timestamp but not
2249 * So in those cases, request a kvmclock update for all vcpus.
2250 * We need to rate-limit these requests though, as they can
2251 * considerably slow guests that have a large number of vcpus.
2252 * The time for a remote vcpu to update its kvmclock is bound
2253 * by the delay we use to rate-limit the updates.
2256 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2258 static void kvmclock_update_fn(struct work_struct *work)
2261 struct delayed_work *dwork = to_delayed_work(work);
2262 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2263 kvmclock_update_work);
2264 struct kvm *kvm = container_of(ka, struct kvm, arch);
2265 struct kvm_vcpu *vcpu;
2267 kvm_for_each_vcpu(i, vcpu, kvm) {
2268 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2269 kvm_vcpu_kick(vcpu);
2273 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2275 struct kvm *kvm = v->kvm;
2277 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2278 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2279 KVMCLOCK_UPDATE_DELAY);
2282 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2284 static void kvmclock_sync_fn(struct work_struct *work)
2286 struct delayed_work *dwork = to_delayed_work(work);
2287 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2288 kvmclock_sync_work);
2289 struct kvm *kvm = container_of(ka, struct kvm, arch);
2291 if (!kvmclock_periodic_sync)
2294 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2295 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2296 KVMCLOCK_SYNC_PERIOD);
2300 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2302 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2304 /* McStatusWrEn enabled? */
2305 if (guest_cpuid_is_amd(vcpu))
2306 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2311 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2313 u64 mcg_cap = vcpu->arch.mcg_cap;
2314 unsigned bank_num = mcg_cap & 0xff;
2315 u32 msr = msr_info->index;
2316 u64 data = msr_info->data;
2319 case MSR_IA32_MCG_STATUS:
2320 vcpu->arch.mcg_status = data;
2322 case MSR_IA32_MCG_CTL:
2323 if (!(mcg_cap & MCG_CTL_P) &&
2324 (data || !msr_info->host_initiated))
2326 if (data != 0 && data != ~(u64)0)
2328 vcpu->arch.mcg_ctl = data;
2331 if (msr >= MSR_IA32_MC0_CTL &&
2332 msr < MSR_IA32_MCx_CTL(bank_num)) {
2333 u32 offset = msr - MSR_IA32_MC0_CTL;
2334 /* only 0 or all 1s can be written to IA32_MCi_CTL
2335 * some Linux kernels though clear bit 10 in bank 4 to
2336 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2337 * this to avoid an uncatched #GP in the guest
2339 if ((offset & 0x3) == 0 &&
2340 data != 0 && (data | (1 << 10)) != ~(u64)0)
2344 if (!msr_info->host_initiated &&
2345 (offset & 0x3) == 1 && data != 0) {
2346 if (!can_set_mci_status(vcpu))
2350 vcpu->arch.mce_banks[offset] = data;
2358 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2360 struct kvm *kvm = vcpu->kvm;
2361 int lm = is_long_mode(vcpu);
2362 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2363 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2364 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2365 : kvm->arch.xen_hvm_config.blob_size_32;
2366 u32 page_num = data & ~PAGE_MASK;
2367 u64 page_addr = data & PAGE_MASK;
2372 if (page_num >= blob_size)
2375 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2380 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2389 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2391 gpa_t gpa = data & ~0x3f;
2393 /* Bits 3:5 are reserved, Should be zero */
2397 vcpu->arch.apf.msr_val = data;
2399 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2400 kvm_clear_async_pf_completion_queue(vcpu);
2401 kvm_async_pf_hash_reset(vcpu);
2405 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2409 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2410 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2411 kvm_async_pf_wakeup_all(vcpu);
2415 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2417 vcpu->arch.pv_time_enabled = false;
2420 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2422 ++vcpu->stat.tlb_flush;
2423 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2426 static void record_steal_time(struct kvm_vcpu *vcpu)
2428 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2431 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2432 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2436 * Doing a TLB flush here, on the guest's behalf, can avoid
2439 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2440 kvm_vcpu_flush_tlb(vcpu, false);
2442 if (vcpu->arch.st.steal.version & 1)
2443 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2445 vcpu->arch.st.steal.version += 1;
2447 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2448 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2452 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2453 vcpu->arch.st.last_steal;
2454 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2456 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2457 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2461 vcpu->arch.st.steal.version += 1;
2463 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2464 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2467 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2470 u32 msr = msr_info->index;
2471 u64 data = msr_info->data;
2474 case MSR_AMD64_NB_CFG:
2475 case MSR_IA32_UCODE_WRITE:
2476 case MSR_VM_HSAVE_PA:
2477 case MSR_AMD64_PATCH_LOADER:
2478 case MSR_AMD64_BU_CFG2:
2479 case MSR_AMD64_DC_CFG:
2480 case MSR_F15H_EX_CFG:
2483 case MSR_IA32_UCODE_REV:
2484 if (msr_info->host_initiated)
2485 vcpu->arch.microcode_version = data;
2487 case MSR_IA32_ARCH_CAPABILITIES:
2488 if (!msr_info->host_initiated)
2490 vcpu->arch.arch_capabilities = data;
2493 return set_efer(vcpu, msr_info);
2495 data &= ~(u64)0x40; /* ignore flush filter disable */
2496 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2497 data &= ~(u64)0x8; /* ignore TLB cache disable */
2499 /* Handle McStatusWrEn */
2500 if (data == BIT_ULL(18)) {
2501 vcpu->arch.msr_hwcr = data;
2502 } else if (data != 0) {
2503 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2508 case MSR_FAM10H_MMIO_CONF_BASE:
2510 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2515 case MSR_IA32_DEBUGCTLMSR:
2517 /* We support the non-activated case already */
2519 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2520 /* Values other than LBR and BTF are vendor-specific,
2521 thus reserved and should throw a #GP */
2524 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2527 case 0x200 ... 0x2ff:
2528 return kvm_mtrr_set_msr(vcpu, msr, data);
2529 case MSR_IA32_APICBASE:
2530 return kvm_set_apic_base(vcpu, msr_info);
2531 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2532 return kvm_x2apic_msr_write(vcpu, msr, data);
2533 case MSR_IA32_TSCDEADLINE:
2534 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2536 case MSR_IA32_TSC_ADJUST:
2537 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2538 if (!msr_info->host_initiated) {
2539 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2540 adjust_tsc_offset_guest(vcpu, adj);
2542 vcpu->arch.ia32_tsc_adjust_msr = data;
2545 case MSR_IA32_MISC_ENABLE:
2546 vcpu->arch.ia32_misc_enable_msr = data;
2548 case MSR_IA32_SMBASE:
2549 if (!msr_info->host_initiated)
2551 vcpu->arch.smbase = data;
2554 kvm_write_tsc(vcpu, msr_info);
2557 if (!msr_info->host_initiated)
2559 vcpu->arch.smi_count = data;
2561 case MSR_KVM_WALL_CLOCK_NEW:
2562 case MSR_KVM_WALL_CLOCK:
2563 vcpu->kvm->arch.wall_clock = data;
2564 kvm_write_wall_clock(vcpu->kvm, data);
2566 case MSR_KVM_SYSTEM_TIME_NEW:
2567 case MSR_KVM_SYSTEM_TIME: {
2568 struct kvm_arch *ka = &vcpu->kvm->arch;
2570 kvmclock_reset(vcpu);
2572 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2573 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2575 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2576 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2578 ka->boot_vcpu_runs_old_kvmclock = tmp;
2581 vcpu->arch.time = data;
2582 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2584 /* we verify if the enable bit is set... */
2588 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2589 &vcpu->arch.pv_time, data & ~1ULL,
2590 sizeof(struct pvclock_vcpu_time_info)))
2591 vcpu->arch.pv_time_enabled = false;
2593 vcpu->arch.pv_time_enabled = true;
2597 case MSR_KVM_ASYNC_PF_EN:
2598 if (kvm_pv_enable_async_pf(vcpu, data))
2601 case MSR_KVM_STEAL_TIME:
2603 if (unlikely(!sched_info_on()))
2606 if (data & KVM_STEAL_RESERVED_MASK)
2609 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2610 data & KVM_STEAL_VALID_BITS,
2611 sizeof(struct kvm_steal_time)))
2614 vcpu->arch.st.msr_val = data;
2616 if (!(data & KVM_MSR_ENABLED))
2619 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2622 case MSR_KVM_PV_EOI_EN:
2623 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2627 case MSR_IA32_MCG_CTL:
2628 case MSR_IA32_MCG_STATUS:
2629 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2630 return set_msr_mce(vcpu, msr_info);
2632 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2633 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2634 pr = true; /* fall through */
2635 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2636 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2637 if (kvm_pmu_is_valid_msr(vcpu, msr))
2638 return kvm_pmu_set_msr(vcpu, msr_info);
2640 if (pr || data != 0)
2641 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2642 "0x%x data 0x%llx\n", msr, data);
2644 case MSR_K7_CLK_CTL:
2646 * Ignore all writes to this no longer documented MSR.
2647 * Writes are only relevant for old K7 processors,
2648 * all pre-dating SVM, but a recommended workaround from
2649 * AMD for these chips. It is possible to specify the
2650 * affected processor models on the command line, hence
2651 * the need to ignore the workaround.
2654 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2655 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2656 case HV_X64_MSR_CRASH_CTL:
2657 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2658 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2659 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2660 case HV_X64_MSR_TSC_EMULATION_STATUS:
2661 return kvm_hv_set_msr_common(vcpu, msr, data,
2662 msr_info->host_initiated);
2663 case MSR_IA32_BBL_CR_CTL3:
2664 /* Drop writes to this legacy MSR -- see rdmsr
2665 * counterpart for further detail.
2667 if (report_ignored_msrs)
2668 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2671 case MSR_AMD64_OSVW_ID_LENGTH:
2672 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2674 vcpu->arch.osvw.length = data;
2676 case MSR_AMD64_OSVW_STATUS:
2677 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2679 vcpu->arch.osvw.status = data;
2681 case MSR_PLATFORM_INFO:
2682 if (!msr_info->host_initiated ||
2683 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2684 cpuid_fault_enabled(vcpu)))
2686 vcpu->arch.msr_platform_info = data;
2688 case MSR_MISC_FEATURES_ENABLES:
2689 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2690 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2691 !supports_cpuid_fault(vcpu)))
2693 vcpu->arch.msr_misc_features_enables = data;
2696 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2697 return xen_hvm_config(vcpu, data);
2698 if (kvm_pmu_is_valid_msr(vcpu, msr))
2699 return kvm_pmu_set_msr(vcpu, msr_info);
2701 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2705 if (report_ignored_msrs)
2707 "ignored wrmsr: 0x%x data 0x%llx\n",
2714 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2718 * Reads an msr value (of 'msr_index') into 'pdata'.
2719 * Returns 0 on success, non-0 otherwise.
2720 * Assumes vcpu_load() was already called.
2722 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2724 return kvm_x86_ops->get_msr(vcpu, msr);
2726 EXPORT_SYMBOL_GPL(kvm_get_msr);
2728 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2731 u64 mcg_cap = vcpu->arch.mcg_cap;
2732 unsigned bank_num = mcg_cap & 0xff;
2735 case MSR_IA32_P5_MC_ADDR:
2736 case MSR_IA32_P5_MC_TYPE:
2739 case MSR_IA32_MCG_CAP:
2740 data = vcpu->arch.mcg_cap;
2742 case MSR_IA32_MCG_CTL:
2743 if (!(mcg_cap & MCG_CTL_P) && !host)
2745 data = vcpu->arch.mcg_ctl;
2747 case MSR_IA32_MCG_STATUS:
2748 data = vcpu->arch.mcg_status;
2751 if (msr >= MSR_IA32_MC0_CTL &&
2752 msr < MSR_IA32_MCx_CTL(bank_num)) {
2753 u32 offset = msr - MSR_IA32_MC0_CTL;
2754 data = vcpu->arch.mce_banks[offset];
2763 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2765 switch (msr_info->index) {
2766 case MSR_IA32_PLATFORM_ID:
2767 case MSR_IA32_EBL_CR_POWERON:
2768 case MSR_IA32_DEBUGCTLMSR:
2769 case MSR_IA32_LASTBRANCHFROMIP:
2770 case MSR_IA32_LASTBRANCHTOIP:
2771 case MSR_IA32_LASTINTFROMIP:
2772 case MSR_IA32_LASTINTTOIP:
2774 case MSR_K8_TSEG_ADDR:
2775 case MSR_K8_TSEG_MASK:
2776 case MSR_VM_HSAVE_PA:
2777 case MSR_K8_INT_PENDING_MSG:
2778 case MSR_AMD64_NB_CFG:
2779 case MSR_FAM10H_MMIO_CONF_BASE:
2780 case MSR_AMD64_BU_CFG2:
2781 case MSR_IA32_PERF_CTL:
2782 case MSR_AMD64_DC_CFG:
2783 case MSR_F15H_EX_CFG:
2786 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2787 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2788 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2789 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2790 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2791 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2792 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2795 case MSR_IA32_UCODE_REV:
2796 msr_info->data = vcpu->arch.microcode_version;
2798 case MSR_IA32_ARCH_CAPABILITIES:
2799 if (!msr_info->host_initiated &&
2800 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2802 msr_info->data = vcpu->arch.arch_capabilities;
2805 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2808 case 0x200 ... 0x2ff:
2809 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2810 case 0xcd: /* fsb frequency */
2814 * MSR_EBC_FREQUENCY_ID
2815 * Conservative value valid for even the basic CPU models.
2816 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2817 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2818 * and 266MHz for model 3, or 4. Set Core Clock
2819 * Frequency to System Bus Frequency Ratio to 1 (bits
2820 * 31:24) even though these are only valid for CPU
2821 * models > 2, however guests may end up dividing or
2822 * multiplying by zero otherwise.
2824 case MSR_EBC_FREQUENCY_ID:
2825 msr_info->data = 1 << 24;
2827 case MSR_IA32_APICBASE:
2828 msr_info->data = kvm_get_apic_base(vcpu);
2830 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2831 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2833 case MSR_IA32_TSCDEADLINE:
2834 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2836 case MSR_IA32_TSC_ADJUST:
2837 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2839 case MSR_IA32_MISC_ENABLE:
2840 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2842 case MSR_IA32_SMBASE:
2843 if (!msr_info->host_initiated)
2845 msr_info->data = vcpu->arch.smbase;
2848 msr_info->data = vcpu->arch.smi_count;
2850 case MSR_IA32_PERF_STATUS:
2851 /* TSC increment by tick */
2852 msr_info->data = 1000ULL;
2853 /* CPU multiplier */
2854 msr_info->data |= (((uint64_t)4ULL) << 40);
2857 msr_info->data = vcpu->arch.efer;
2859 case MSR_KVM_WALL_CLOCK:
2860 case MSR_KVM_WALL_CLOCK_NEW:
2861 msr_info->data = vcpu->kvm->arch.wall_clock;
2863 case MSR_KVM_SYSTEM_TIME:
2864 case MSR_KVM_SYSTEM_TIME_NEW:
2865 msr_info->data = vcpu->arch.time;
2867 case MSR_KVM_ASYNC_PF_EN:
2868 msr_info->data = vcpu->arch.apf.msr_val;
2870 case MSR_KVM_STEAL_TIME:
2871 msr_info->data = vcpu->arch.st.msr_val;
2873 case MSR_KVM_PV_EOI_EN:
2874 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2876 case MSR_IA32_P5_MC_ADDR:
2877 case MSR_IA32_P5_MC_TYPE:
2878 case MSR_IA32_MCG_CAP:
2879 case MSR_IA32_MCG_CTL:
2880 case MSR_IA32_MCG_STATUS:
2881 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2882 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2883 msr_info->host_initiated);
2884 case MSR_K7_CLK_CTL:
2886 * Provide expected ramp-up count for K7. All other
2887 * are set to zero, indicating minimum divisors for
2890 * This prevents guest kernels on AMD host with CPU
2891 * type 6, model 8 and higher from exploding due to
2892 * the rdmsr failing.
2894 msr_info->data = 0x20000000;
2896 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2897 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2898 case HV_X64_MSR_CRASH_CTL:
2899 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2900 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2901 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2902 case HV_X64_MSR_TSC_EMULATION_STATUS:
2903 return kvm_hv_get_msr_common(vcpu,
2904 msr_info->index, &msr_info->data,
2905 msr_info->host_initiated);
2907 case MSR_IA32_BBL_CR_CTL3:
2908 /* This legacy MSR exists but isn't fully documented in current
2909 * silicon. It is however accessed by winxp in very narrow
2910 * scenarios where it sets bit #19, itself documented as
2911 * a "reserved" bit. Best effort attempt to source coherent
2912 * read data here should the balance of the register be
2913 * interpreted by the guest:
2915 * L2 cache control register 3: 64GB range, 256KB size,
2916 * enabled, latency 0x1, configured
2918 msr_info->data = 0xbe702111;
2920 case MSR_AMD64_OSVW_ID_LENGTH:
2921 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2923 msr_info->data = vcpu->arch.osvw.length;
2925 case MSR_AMD64_OSVW_STATUS:
2926 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2928 msr_info->data = vcpu->arch.osvw.status;
2930 case MSR_PLATFORM_INFO:
2931 if (!msr_info->host_initiated &&
2932 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2934 msr_info->data = vcpu->arch.msr_platform_info;
2936 case MSR_MISC_FEATURES_ENABLES:
2937 msr_info->data = vcpu->arch.msr_misc_features_enables;
2940 msr_info->data = vcpu->arch.msr_hwcr;
2943 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2944 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2946 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2950 if (report_ignored_msrs)
2951 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2959 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2962 * Read or write a bunch of msrs. All parameters are kernel addresses.
2964 * @return number of msrs set successfully.
2966 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2967 struct kvm_msr_entry *entries,
2968 int (*do_msr)(struct kvm_vcpu *vcpu,
2969 unsigned index, u64 *data))
2973 for (i = 0; i < msrs->nmsrs; ++i)
2974 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2981 * Read or write a bunch of msrs. Parameters are user addresses.
2983 * @return number of msrs set successfully.
2985 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2986 int (*do_msr)(struct kvm_vcpu *vcpu,
2987 unsigned index, u64 *data),
2990 struct kvm_msrs msrs;
2991 struct kvm_msr_entry *entries;
2996 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3000 if (msrs.nmsrs >= MAX_IO_MSRS)
3003 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3004 entries = memdup_user(user_msrs->entries, size);
3005 if (IS_ERR(entries)) {
3006 r = PTR_ERR(entries);
3010 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3015 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3026 static inline bool kvm_can_mwait_in_guest(void)
3028 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3029 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3030 boot_cpu_has(X86_FEATURE_ARAT);
3033 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3038 case KVM_CAP_IRQCHIP:
3040 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3041 case KVM_CAP_SET_TSS_ADDR:
3042 case KVM_CAP_EXT_CPUID:
3043 case KVM_CAP_EXT_EMUL_CPUID:
3044 case KVM_CAP_CLOCKSOURCE:
3046 case KVM_CAP_NOP_IO_DELAY:
3047 case KVM_CAP_MP_STATE:
3048 case KVM_CAP_SYNC_MMU:
3049 case KVM_CAP_USER_NMI:
3050 case KVM_CAP_REINJECT_CONTROL:
3051 case KVM_CAP_IRQ_INJECT_STATUS:
3052 case KVM_CAP_IOEVENTFD:
3053 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3055 case KVM_CAP_PIT_STATE2:
3056 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3057 case KVM_CAP_XEN_HVM:
3058 case KVM_CAP_VCPU_EVENTS:
3059 case KVM_CAP_HYPERV:
3060 case KVM_CAP_HYPERV_VAPIC:
3061 case KVM_CAP_HYPERV_SPIN:
3062 case KVM_CAP_HYPERV_SYNIC:
3063 case KVM_CAP_HYPERV_SYNIC2:
3064 case KVM_CAP_HYPERV_VP_INDEX:
3065 case KVM_CAP_HYPERV_EVENTFD:
3066 case KVM_CAP_HYPERV_TLBFLUSH:
3067 case KVM_CAP_HYPERV_SEND_IPI:
3068 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3069 case KVM_CAP_HYPERV_CPUID:
3070 case KVM_CAP_PCI_SEGMENT:
3071 case KVM_CAP_DEBUGREGS:
3072 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3074 case KVM_CAP_ASYNC_PF:
3075 case KVM_CAP_GET_TSC_KHZ:
3076 case KVM_CAP_KVMCLOCK_CTRL:
3077 case KVM_CAP_READONLY_MEM:
3078 case KVM_CAP_HYPERV_TIME:
3079 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3080 case KVM_CAP_TSC_DEADLINE_TIMER:
3081 case KVM_CAP_DISABLE_QUIRKS:
3082 case KVM_CAP_SET_BOOT_CPU_ID:
3083 case KVM_CAP_SPLIT_IRQCHIP:
3084 case KVM_CAP_IMMEDIATE_EXIT:
3085 case KVM_CAP_GET_MSR_FEATURES:
3086 case KVM_CAP_MSR_PLATFORM_INFO:
3087 case KVM_CAP_EXCEPTION_PAYLOAD:
3090 case KVM_CAP_SYNC_REGS:
3091 r = KVM_SYNC_X86_VALID_FIELDS;
3093 case KVM_CAP_ADJUST_CLOCK:
3094 r = KVM_CLOCK_TSC_STABLE;
3096 case KVM_CAP_X86_DISABLE_EXITS:
3097 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
3098 if(kvm_can_mwait_in_guest())
3099 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3101 case KVM_CAP_X86_SMM:
3102 /* SMBASE is usually relocated above 1M on modern chipsets,
3103 * and SMM handlers might indeed rely on 4G segment limits,
3104 * so do not report SMM to be available if real mode is
3105 * emulated via vm86 mode. Still, do not go to great lengths
3106 * to avoid userspace's usage of the feature, because it is a
3107 * fringe case that is not enabled except via specific settings
3108 * of the module parameters.
3110 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3113 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3115 case KVM_CAP_NR_VCPUS:
3116 r = KVM_SOFT_MAX_VCPUS;
3118 case KVM_CAP_MAX_VCPUS:
3121 case KVM_CAP_PV_MMU: /* obsolete */
3125 r = KVM_MAX_MCE_BANKS;
3128 r = boot_cpu_has(X86_FEATURE_XSAVE);
3130 case KVM_CAP_TSC_CONTROL:
3131 r = kvm_has_tsc_control;
3133 case KVM_CAP_X2APIC_API:
3134 r = KVM_X2APIC_API_VALID_FLAGS;
3136 case KVM_CAP_NESTED_STATE:
3137 r = kvm_x86_ops->get_nested_state ?
3138 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3147 long kvm_arch_dev_ioctl(struct file *filp,
3148 unsigned int ioctl, unsigned long arg)
3150 void __user *argp = (void __user *)arg;
3154 case KVM_GET_MSR_INDEX_LIST: {
3155 struct kvm_msr_list __user *user_msr_list = argp;
3156 struct kvm_msr_list msr_list;
3160 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3163 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3164 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3167 if (n < msr_list.nmsrs)
3170 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3171 num_msrs_to_save * sizeof(u32)))
3173 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3175 num_emulated_msrs * sizeof(u32)))
3180 case KVM_GET_SUPPORTED_CPUID:
3181 case KVM_GET_EMULATED_CPUID: {
3182 struct kvm_cpuid2 __user *cpuid_arg = argp;
3183 struct kvm_cpuid2 cpuid;
3186 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3189 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3195 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3200 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3202 if (copy_to_user(argp, &kvm_mce_cap_supported,
3203 sizeof(kvm_mce_cap_supported)))
3207 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3208 struct kvm_msr_list __user *user_msr_list = argp;
3209 struct kvm_msr_list msr_list;
3213 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3216 msr_list.nmsrs = num_msr_based_features;
3217 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3220 if (n < msr_list.nmsrs)
3223 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3224 num_msr_based_features * sizeof(u32)))
3230 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3240 static void wbinvd_ipi(void *garbage)
3245 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3247 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3250 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3252 /* Address WBINVD may be executed by guest */
3253 if (need_emulate_wbinvd(vcpu)) {
3254 if (kvm_x86_ops->has_wbinvd_exit())
3255 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3256 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3257 smp_call_function_single(vcpu->cpu,
3258 wbinvd_ipi, NULL, 1);
3261 kvm_x86_ops->vcpu_load(vcpu, cpu);
3263 /* Apply any externally detected TSC adjustments (due to suspend) */
3264 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3265 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3266 vcpu->arch.tsc_offset_adjustment = 0;
3267 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3270 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3271 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3272 rdtsc() - vcpu->arch.last_host_tsc;
3274 mark_tsc_unstable("KVM discovered backwards TSC");
3276 if (kvm_check_tsc_unstable()) {
3277 u64 offset = kvm_compute_tsc_offset(vcpu,
3278 vcpu->arch.last_guest_tsc);
3279 kvm_vcpu_write_tsc_offset(vcpu, offset);
3280 vcpu->arch.tsc_catchup = 1;
3283 if (kvm_lapic_hv_timer_in_use(vcpu))
3284 kvm_lapic_restart_hv_timer(vcpu);
3287 * On a host with synchronized TSC, there is no need to update
3288 * kvmclock on vcpu->cpu migration
3290 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3291 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3292 if (vcpu->cpu != cpu)
3293 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3297 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3300 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3302 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3305 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3307 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3308 &vcpu->arch.st.steal.preempted,
3309 offsetof(struct kvm_steal_time, preempted),
3310 sizeof(vcpu->arch.st.steal.preempted));
3313 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3317 if (vcpu->preempted)
3318 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3321 * Disable page faults because we're in atomic context here.
3322 * kvm_write_guest_offset_cached() would call might_fault()
3323 * that relies on pagefault_disable() to tell if there's a
3324 * bug. NOTE: the write to guest memory may not go through if
3325 * during postcopy live migration or if there's heavy guest
3328 pagefault_disable();
3330 * kvm_memslots() will be called by
3331 * kvm_write_guest_offset_cached() so take the srcu lock.
3333 idx = srcu_read_lock(&vcpu->kvm->srcu);
3334 kvm_steal_time_set_preempted(vcpu);
3335 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3337 kvm_x86_ops->vcpu_put(vcpu);
3338 vcpu->arch.last_host_tsc = rdtsc();
3340 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3341 * on every vmexit, but if not, we might have a stale dr6 from the
3342 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3347 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3348 struct kvm_lapic_state *s)
3350 if (vcpu->arch.apicv_active)
3351 kvm_x86_ops->sync_pir_to_irr(vcpu);
3353 return kvm_apic_get_state(vcpu, s);
3356 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3357 struct kvm_lapic_state *s)
3361 r = kvm_apic_set_state(vcpu, s);
3364 update_cr8_intercept(vcpu);
3369 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3371 return (!lapic_in_kernel(vcpu) ||
3372 kvm_apic_accept_pic_intr(vcpu));
3376 * if userspace requested an interrupt window, check that the
3377 * interrupt window is open.
3379 * No need to exit to userspace if we already have an interrupt queued.
3381 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3383 return kvm_arch_interrupt_allowed(vcpu) &&
3384 !kvm_cpu_has_interrupt(vcpu) &&
3385 !kvm_event_needs_reinjection(vcpu) &&
3386 kvm_cpu_accept_dm_intr(vcpu);
3389 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3390 struct kvm_interrupt *irq)
3392 if (irq->irq >= KVM_NR_INTERRUPTS)
3395 if (!irqchip_in_kernel(vcpu->kvm)) {
3396 kvm_queue_interrupt(vcpu, irq->irq, false);
3397 kvm_make_request(KVM_REQ_EVENT, vcpu);
3402 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3403 * fail for in-kernel 8259.
3405 if (pic_in_kernel(vcpu->kvm))
3408 if (vcpu->arch.pending_external_vector != -1)
3411 vcpu->arch.pending_external_vector = irq->irq;
3412 kvm_make_request(KVM_REQ_EVENT, vcpu);
3416 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3418 kvm_inject_nmi(vcpu);
3423 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3425 kvm_make_request(KVM_REQ_SMI, vcpu);
3430 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3431 struct kvm_tpr_access_ctl *tac)
3435 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3439 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3443 unsigned bank_num = mcg_cap & 0xff, bank;
3446 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3448 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3451 vcpu->arch.mcg_cap = mcg_cap;
3452 /* Init IA32_MCG_CTL to all 1s */
3453 if (mcg_cap & MCG_CTL_P)
3454 vcpu->arch.mcg_ctl = ~(u64)0;
3455 /* Init IA32_MCi_CTL to all 1s */
3456 for (bank = 0; bank < bank_num; bank++)
3457 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3459 if (kvm_x86_ops->setup_mce)
3460 kvm_x86_ops->setup_mce(vcpu);
3465 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3466 struct kvm_x86_mce *mce)
3468 u64 mcg_cap = vcpu->arch.mcg_cap;
3469 unsigned bank_num = mcg_cap & 0xff;
3470 u64 *banks = vcpu->arch.mce_banks;
3472 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3475 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3476 * reporting is disabled
3478 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3479 vcpu->arch.mcg_ctl != ~(u64)0)
3481 banks += 4 * mce->bank;
3483 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3484 * reporting is disabled for the bank
3486 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3488 if (mce->status & MCI_STATUS_UC) {
3489 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3490 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3491 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3494 if (banks[1] & MCI_STATUS_VAL)
3495 mce->status |= MCI_STATUS_OVER;
3496 banks[2] = mce->addr;
3497 banks[3] = mce->misc;
3498 vcpu->arch.mcg_status = mce->mcg_status;
3499 banks[1] = mce->status;
3500 kvm_queue_exception(vcpu, MC_VECTOR);
3501 } else if (!(banks[1] & MCI_STATUS_VAL)
3502 || !(banks[1] & MCI_STATUS_UC)) {
3503 if (banks[1] & MCI_STATUS_VAL)
3504 mce->status |= MCI_STATUS_OVER;
3505 banks[2] = mce->addr;
3506 banks[3] = mce->misc;
3507 banks[1] = mce->status;
3509 banks[1] |= MCI_STATUS_OVER;
3513 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3514 struct kvm_vcpu_events *events)
3519 * The API doesn't provide the instruction length for software
3520 * exceptions, so don't report them. As long as the guest RIP
3521 * isn't advanced, we should expect to encounter the exception
3524 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3525 events->exception.injected = 0;
3526 events->exception.pending = 0;
3528 events->exception.injected = vcpu->arch.exception.injected;
3529 events->exception.pending = vcpu->arch.exception.pending;
3531 * For ABI compatibility, deliberately conflate
3532 * pending and injected exceptions when
3533 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3535 if (!vcpu->kvm->arch.exception_payload_enabled)
3536 events->exception.injected |=
3537 vcpu->arch.exception.pending;
3539 events->exception.nr = vcpu->arch.exception.nr;
3540 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3541 events->exception.error_code = vcpu->arch.exception.error_code;
3542 events->exception_has_payload = vcpu->arch.exception.has_payload;
3543 events->exception_payload = vcpu->arch.exception.payload;
3545 events->interrupt.injected =
3546 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3547 events->interrupt.nr = vcpu->arch.interrupt.nr;
3548 events->interrupt.soft = 0;
3549 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3551 events->nmi.injected = vcpu->arch.nmi_injected;
3552 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3553 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3554 events->nmi.pad = 0;
3556 events->sipi_vector = 0; /* never valid when reporting to user space */
3558 events->smi.smm = is_smm(vcpu);
3559 events->smi.pending = vcpu->arch.smi_pending;
3560 events->smi.smm_inside_nmi =
3561 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3562 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3564 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3565 | KVM_VCPUEVENT_VALID_SHADOW
3566 | KVM_VCPUEVENT_VALID_SMM);
3567 if (vcpu->kvm->arch.exception_payload_enabled)
3568 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3570 memset(&events->reserved, 0, sizeof(events->reserved));
3573 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3575 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3576 struct kvm_vcpu_events *events)
3578 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3579 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3580 | KVM_VCPUEVENT_VALID_SHADOW
3581 | KVM_VCPUEVENT_VALID_SMM
3582 | KVM_VCPUEVENT_VALID_PAYLOAD))
3585 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3586 if (!vcpu->kvm->arch.exception_payload_enabled)
3588 if (events->exception.pending)
3589 events->exception.injected = 0;
3591 events->exception_has_payload = 0;
3593 events->exception.pending = 0;
3594 events->exception_has_payload = 0;
3597 if ((events->exception.injected || events->exception.pending) &&
3598 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3601 /* INITs are latched while in SMM */
3602 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3603 (events->smi.smm || events->smi.pending) &&
3604 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3608 vcpu->arch.exception.injected = events->exception.injected;
3609 vcpu->arch.exception.pending = events->exception.pending;
3610 vcpu->arch.exception.nr = events->exception.nr;
3611 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3612 vcpu->arch.exception.error_code = events->exception.error_code;
3613 vcpu->arch.exception.has_payload = events->exception_has_payload;
3614 vcpu->arch.exception.payload = events->exception_payload;
3616 vcpu->arch.interrupt.injected = events->interrupt.injected;
3617 vcpu->arch.interrupt.nr = events->interrupt.nr;
3618 vcpu->arch.interrupt.soft = events->interrupt.soft;
3619 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3620 kvm_x86_ops->set_interrupt_shadow(vcpu,
3621 events->interrupt.shadow);
3623 vcpu->arch.nmi_injected = events->nmi.injected;
3624 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3625 vcpu->arch.nmi_pending = events->nmi.pending;
3626 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3628 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3629 lapic_in_kernel(vcpu))
3630 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3632 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3633 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3634 if (events->smi.smm)
3635 vcpu->arch.hflags |= HF_SMM_MASK;
3637 vcpu->arch.hflags &= ~HF_SMM_MASK;
3638 kvm_smm_changed(vcpu);
3641 vcpu->arch.smi_pending = events->smi.pending;
3643 if (events->smi.smm) {
3644 if (events->smi.smm_inside_nmi)
3645 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3647 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3648 if (lapic_in_kernel(vcpu)) {
3649 if (events->smi.latched_init)
3650 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3652 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3657 kvm_make_request(KVM_REQ_EVENT, vcpu);
3662 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3663 struct kvm_debugregs *dbgregs)
3667 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3668 kvm_get_dr(vcpu, 6, &val);
3670 dbgregs->dr7 = vcpu->arch.dr7;
3672 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3675 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3676 struct kvm_debugregs *dbgregs)
3681 if (dbgregs->dr6 & ~0xffffffffull)
3683 if (dbgregs->dr7 & ~0xffffffffull)
3686 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3687 kvm_update_dr0123(vcpu);
3688 vcpu->arch.dr6 = dbgregs->dr6;
3689 kvm_update_dr6(vcpu);
3690 vcpu->arch.dr7 = dbgregs->dr7;
3691 kvm_update_dr7(vcpu);
3696 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3698 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3700 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3701 u64 xstate_bv = xsave->header.xfeatures;
3705 * Copy legacy XSAVE area, to avoid complications with CPUID
3706 * leaves 0 and 1 in the loop below.
3708 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3711 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3712 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3715 * Copy each region from the possibly compacted offset to the
3716 * non-compacted offset.
3718 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3720 u64 feature = valid & -valid;
3721 int index = fls64(feature) - 1;
3722 void *src = get_xsave_addr(xsave, feature);
3725 u32 size, offset, ecx, edx;
3726 cpuid_count(XSTATE_CPUID, index,
3727 &size, &offset, &ecx, &edx);
3728 if (feature == XFEATURE_MASK_PKRU)
3729 memcpy(dest + offset, &vcpu->arch.pkru,
3730 sizeof(vcpu->arch.pkru));
3732 memcpy(dest + offset, src, size);
3740 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3742 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3743 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3747 * Copy legacy XSAVE area, to avoid complications with CPUID
3748 * leaves 0 and 1 in the loop below.
3750 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3752 /* Set XSTATE_BV and possibly XCOMP_BV. */
3753 xsave->header.xfeatures = xstate_bv;
3754 if (boot_cpu_has(X86_FEATURE_XSAVES))
3755 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3758 * Copy each region from the non-compacted offset to the
3759 * possibly compacted offset.
3761 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3763 u64 feature = valid & -valid;
3764 int index = fls64(feature) - 1;
3765 void *dest = get_xsave_addr(xsave, feature);
3768 u32 size, offset, ecx, edx;
3769 cpuid_count(XSTATE_CPUID, index,
3770 &size, &offset, &ecx, &edx);
3771 if (feature == XFEATURE_MASK_PKRU)
3772 memcpy(&vcpu->arch.pkru, src + offset,
3773 sizeof(vcpu->arch.pkru));
3775 memcpy(dest, src + offset, size);
3782 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3783 struct kvm_xsave *guest_xsave)
3785 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3786 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3787 fill_xsave((u8 *) guest_xsave->region, vcpu);
3789 memcpy(guest_xsave->region,
3790 &vcpu->arch.guest_fpu->state.fxsave,
3791 sizeof(struct fxregs_state));
3792 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3793 XFEATURE_MASK_FPSSE;
3797 #define XSAVE_MXCSR_OFFSET 24
3799 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3800 struct kvm_xsave *guest_xsave)
3803 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3804 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3806 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3808 * Here we allow setting states that are not present in
3809 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3810 * with old userspace.
3812 if (xstate_bv & ~kvm_supported_xcr0() ||
3813 mxcsr & ~mxcsr_feature_mask)
3815 load_xsave(vcpu, (u8 *)guest_xsave->region);
3817 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3818 mxcsr & ~mxcsr_feature_mask)
3820 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3821 guest_xsave->region, sizeof(struct fxregs_state));
3826 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3827 struct kvm_xcrs *guest_xcrs)
3829 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3830 guest_xcrs->nr_xcrs = 0;
3834 guest_xcrs->nr_xcrs = 1;
3835 guest_xcrs->flags = 0;
3836 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3837 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3840 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3841 struct kvm_xcrs *guest_xcrs)
3845 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3848 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3851 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3852 /* Only support XCR0 currently */
3853 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3854 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3855 guest_xcrs->xcrs[i].value);
3864 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3865 * stopped by the hypervisor. This function will be called from the host only.
3866 * EINVAL is returned when the host attempts to set the flag for a guest that
3867 * does not support pv clocks.
3869 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3871 if (!vcpu->arch.pv_time_enabled)
3873 vcpu->arch.pvclock_set_guest_stopped_request = true;
3874 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3878 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3879 struct kvm_enable_cap *cap)
3882 uint16_t vmcs_version;
3883 void __user *user_ptr;
3889 case KVM_CAP_HYPERV_SYNIC2:
3894 case KVM_CAP_HYPERV_SYNIC:
3895 if (!irqchip_in_kernel(vcpu->kvm))
3897 return kvm_hv_activate_synic(vcpu, cap->cap ==
3898 KVM_CAP_HYPERV_SYNIC2);
3899 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3900 if (!kvm_x86_ops->nested_enable_evmcs)
3902 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3904 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3905 if (copy_to_user(user_ptr, &vmcs_version,
3906 sizeof(vmcs_version)))
3916 long kvm_arch_vcpu_ioctl(struct file *filp,
3917 unsigned int ioctl, unsigned long arg)
3919 struct kvm_vcpu *vcpu = filp->private_data;
3920 void __user *argp = (void __user *)arg;
3923 struct kvm_lapic_state *lapic;
3924 struct kvm_xsave *xsave;
3925 struct kvm_xcrs *xcrs;
3933 case KVM_GET_LAPIC: {
3935 if (!lapic_in_kernel(vcpu))
3937 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3938 GFP_KERNEL_ACCOUNT);
3943 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3947 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3952 case KVM_SET_LAPIC: {
3954 if (!lapic_in_kernel(vcpu))
3956 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3957 if (IS_ERR(u.lapic)) {
3958 r = PTR_ERR(u.lapic);
3962 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3965 case KVM_INTERRUPT: {
3966 struct kvm_interrupt irq;
3969 if (copy_from_user(&irq, argp, sizeof(irq)))
3971 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3975 r = kvm_vcpu_ioctl_nmi(vcpu);
3979 r = kvm_vcpu_ioctl_smi(vcpu);
3982 case KVM_SET_CPUID: {
3983 struct kvm_cpuid __user *cpuid_arg = argp;
3984 struct kvm_cpuid cpuid;
3987 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3989 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3992 case KVM_SET_CPUID2: {
3993 struct kvm_cpuid2 __user *cpuid_arg = argp;
3994 struct kvm_cpuid2 cpuid;
3997 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3999 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4000 cpuid_arg->entries);
4003 case KVM_GET_CPUID2: {
4004 struct kvm_cpuid2 __user *cpuid_arg = argp;
4005 struct kvm_cpuid2 cpuid;
4008 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4010 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4011 cpuid_arg->entries);
4015 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4020 case KVM_GET_MSRS: {
4021 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4022 r = msr_io(vcpu, argp, do_get_msr, 1);
4023 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4026 case KVM_SET_MSRS: {
4027 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4028 r = msr_io(vcpu, argp, do_set_msr, 0);
4029 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4032 case KVM_TPR_ACCESS_REPORTING: {
4033 struct kvm_tpr_access_ctl tac;
4036 if (copy_from_user(&tac, argp, sizeof(tac)))
4038 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4042 if (copy_to_user(argp, &tac, sizeof(tac)))
4047 case KVM_SET_VAPIC_ADDR: {
4048 struct kvm_vapic_addr va;
4052 if (!lapic_in_kernel(vcpu))
4055 if (copy_from_user(&va, argp, sizeof(va)))
4057 idx = srcu_read_lock(&vcpu->kvm->srcu);
4058 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4059 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4062 case KVM_X86_SETUP_MCE: {
4066 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4068 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4071 case KVM_X86_SET_MCE: {
4072 struct kvm_x86_mce mce;
4075 if (copy_from_user(&mce, argp, sizeof(mce)))
4077 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4080 case KVM_GET_VCPU_EVENTS: {
4081 struct kvm_vcpu_events events;
4083 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4086 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4091 case KVM_SET_VCPU_EVENTS: {
4092 struct kvm_vcpu_events events;
4095 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4098 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4101 case KVM_GET_DEBUGREGS: {
4102 struct kvm_debugregs dbgregs;
4104 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4107 if (copy_to_user(argp, &dbgregs,
4108 sizeof(struct kvm_debugregs)))
4113 case KVM_SET_DEBUGREGS: {
4114 struct kvm_debugregs dbgregs;
4117 if (copy_from_user(&dbgregs, argp,
4118 sizeof(struct kvm_debugregs)))
4121 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4124 case KVM_GET_XSAVE: {
4125 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4130 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4133 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4138 case KVM_SET_XSAVE: {
4139 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4140 if (IS_ERR(u.xsave)) {
4141 r = PTR_ERR(u.xsave);
4145 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4148 case KVM_GET_XCRS: {
4149 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4154 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4157 if (copy_to_user(argp, u.xcrs,
4158 sizeof(struct kvm_xcrs)))
4163 case KVM_SET_XCRS: {
4164 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4165 if (IS_ERR(u.xcrs)) {
4166 r = PTR_ERR(u.xcrs);
4170 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4173 case KVM_SET_TSC_KHZ: {
4177 user_tsc_khz = (u32)arg;
4179 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4182 if (user_tsc_khz == 0)
4183 user_tsc_khz = tsc_khz;
4185 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4190 case KVM_GET_TSC_KHZ: {
4191 r = vcpu->arch.virtual_tsc_khz;
4194 case KVM_KVMCLOCK_CTRL: {
4195 r = kvm_set_guest_paused(vcpu);
4198 case KVM_ENABLE_CAP: {
4199 struct kvm_enable_cap cap;
4202 if (copy_from_user(&cap, argp, sizeof(cap)))
4204 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4207 case KVM_GET_NESTED_STATE: {
4208 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4212 if (!kvm_x86_ops->get_nested_state)
4215 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4217 if (get_user(user_data_size, &user_kvm_nested_state->size))
4220 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4225 if (r > user_data_size) {
4226 if (put_user(r, &user_kvm_nested_state->size))
4236 case KVM_SET_NESTED_STATE: {
4237 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4238 struct kvm_nested_state kvm_state;
4241 if (!kvm_x86_ops->set_nested_state)
4245 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4249 if (kvm_state.size < sizeof(kvm_state))
4252 if (kvm_state.flags &
4253 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4254 | KVM_STATE_NESTED_EVMCS))
4257 /* nested_run_pending implies guest_mode. */
4258 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4259 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4262 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4265 case KVM_GET_SUPPORTED_HV_CPUID: {
4266 struct kvm_cpuid2 __user *cpuid_arg = argp;
4267 struct kvm_cpuid2 cpuid;
4270 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4273 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4274 cpuid_arg->entries);
4279 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4294 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4296 return VM_FAULT_SIGBUS;
4299 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4303 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4305 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4309 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4312 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4315 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4316 unsigned long kvm_nr_mmu_pages)
4318 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4321 mutex_lock(&kvm->slots_lock);
4323 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4324 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4326 mutex_unlock(&kvm->slots_lock);
4330 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4332 return kvm->arch.n_max_mmu_pages;
4335 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4337 struct kvm_pic *pic = kvm->arch.vpic;
4341 switch (chip->chip_id) {
4342 case KVM_IRQCHIP_PIC_MASTER:
4343 memcpy(&chip->chip.pic, &pic->pics[0],
4344 sizeof(struct kvm_pic_state));
4346 case KVM_IRQCHIP_PIC_SLAVE:
4347 memcpy(&chip->chip.pic, &pic->pics[1],
4348 sizeof(struct kvm_pic_state));
4350 case KVM_IRQCHIP_IOAPIC:
4351 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4360 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4362 struct kvm_pic *pic = kvm->arch.vpic;
4366 switch (chip->chip_id) {
4367 case KVM_IRQCHIP_PIC_MASTER:
4368 spin_lock(&pic->lock);
4369 memcpy(&pic->pics[0], &chip->chip.pic,
4370 sizeof(struct kvm_pic_state));
4371 spin_unlock(&pic->lock);
4373 case KVM_IRQCHIP_PIC_SLAVE:
4374 spin_lock(&pic->lock);
4375 memcpy(&pic->pics[1], &chip->chip.pic,
4376 sizeof(struct kvm_pic_state));
4377 spin_unlock(&pic->lock);
4379 case KVM_IRQCHIP_IOAPIC:
4380 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4386 kvm_pic_update_irq(pic);
4390 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4392 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4394 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4396 mutex_lock(&kps->lock);
4397 memcpy(ps, &kps->channels, sizeof(*ps));
4398 mutex_unlock(&kps->lock);
4402 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4405 struct kvm_pit *pit = kvm->arch.vpit;
4407 mutex_lock(&pit->pit_state.lock);
4408 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4409 for (i = 0; i < 3; i++)
4410 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4411 mutex_unlock(&pit->pit_state.lock);
4415 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4417 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4418 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4419 sizeof(ps->channels));
4420 ps->flags = kvm->arch.vpit->pit_state.flags;
4421 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4422 memset(&ps->reserved, 0, sizeof(ps->reserved));
4426 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4430 u32 prev_legacy, cur_legacy;
4431 struct kvm_pit *pit = kvm->arch.vpit;
4433 mutex_lock(&pit->pit_state.lock);
4434 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4435 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4436 if (!prev_legacy && cur_legacy)
4438 memcpy(&pit->pit_state.channels, &ps->channels,
4439 sizeof(pit->pit_state.channels));
4440 pit->pit_state.flags = ps->flags;
4441 for (i = 0; i < 3; i++)
4442 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4444 mutex_unlock(&pit->pit_state.lock);
4448 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4449 struct kvm_reinject_control *control)
4451 struct kvm_pit *pit = kvm->arch.vpit;
4456 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4457 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4458 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4460 mutex_lock(&pit->pit_state.lock);
4461 kvm_pit_set_reinject(pit, control->pit_reinject);
4462 mutex_unlock(&pit->pit_state.lock);
4468 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4469 * @kvm: kvm instance
4470 * @log: slot id and address to which we copy the log
4472 * Steps 1-4 below provide general overview of dirty page logging. See
4473 * kvm_get_dirty_log_protect() function description for additional details.
4475 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4476 * always flush the TLB (step 4) even if previous step failed and the dirty
4477 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4478 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4479 * writes will be marked dirty for next log read.
4481 * 1. Take a snapshot of the bit and clear it if needed.
4482 * 2. Write protect the corresponding page.
4483 * 3. Copy the snapshot to the userspace.
4484 * 4. Flush TLB's if needed.
4486 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4491 mutex_lock(&kvm->slots_lock);
4494 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4496 if (kvm_x86_ops->flush_log_dirty)
4497 kvm_x86_ops->flush_log_dirty(kvm);
4499 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4502 * All the TLBs can be flushed out of mmu lock, see the comments in
4503 * kvm_mmu_slot_remove_write_access().
4505 lockdep_assert_held(&kvm->slots_lock);
4507 kvm_flush_remote_tlbs(kvm);
4509 mutex_unlock(&kvm->slots_lock);
4513 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4518 mutex_lock(&kvm->slots_lock);
4521 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4523 if (kvm_x86_ops->flush_log_dirty)
4524 kvm_x86_ops->flush_log_dirty(kvm);
4526 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4529 * All the TLBs can be flushed out of mmu lock, see the comments in
4530 * kvm_mmu_slot_remove_write_access().
4532 lockdep_assert_held(&kvm->slots_lock);
4534 kvm_flush_remote_tlbs(kvm);
4536 mutex_unlock(&kvm->slots_lock);
4540 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4543 if (!irqchip_in_kernel(kvm))
4546 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4547 irq_event->irq, irq_event->level,
4552 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4553 struct kvm_enable_cap *cap)
4561 case KVM_CAP_DISABLE_QUIRKS:
4562 kvm->arch.disabled_quirks = cap->args[0];
4565 case KVM_CAP_SPLIT_IRQCHIP: {
4566 mutex_lock(&kvm->lock);
4568 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4569 goto split_irqchip_unlock;
4571 if (irqchip_in_kernel(kvm))
4572 goto split_irqchip_unlock;
4573 if (kvm->created_vcpus)
4574 goto split_irqchip_unlock;
4575 r = kvm_setup_empty_irq_routing(kvm);
4577 goto split_irqchip_unlock;
4578 /* Pairs with irqchip_in_kernel. */
4580 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4581 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4583 split_irqchip_unlock:
4584 mutex_unlock(&kvm->lock);
4587 case KVM_CAP_X2APIC_API:
4589 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4592 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4593 kvm->arch.x2apic_format = true;
4594 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4595 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4599 case KVM_CAP_X86_DISABLE_EXITS:
4601 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4604 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4605 kvm_can_mwait_in_guest())
4606 kvm->arch.mwait_in_guest = true;
4607 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4608 kvm->arch.hlt_in_guest = true;
4609 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4610 kvm->arch.pause_in_guest = true;
4613 case KVM_CAP_MSR_PLATFORM_INFO:
4614 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4617 case KVM_CAP_EXCEPTION_PAYLOAD:
4618 kvm->arch.exception_payload_enabled = cap->args[0];
4628 long kvm_arch_vm_ioctl(struct file *filp,
4629 unsigned int ioctl, unsigned long arg)
4631 struct kvm *kvm = filp->private_data;
4632 void __user *argp = (void __user *)arg;
4635 * This union makes it completely explicit to gcc-3.x
4636 * that these two variables' stack usage should be
4637 * combined, not added together.
4640 struct kvm_pit_state ps;
4641 struct kvm_pit_state2 ps2;
4642 struct kvm_pit_config pit_config;
4646 case KVM_SET_TSS_ADDR:
4647 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4649 case KVM_SET_IDENTITY_MAP_ADDR: {
4652 mutex_lock(&kvm->lock);
4654 if (kvm->created_vcpus)
4655 goto set_identity_unlock;
4657 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4658 goto set_identity_unlock;
4659 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4660 set_identity_unlock:
4661 mutex_unlock(&kvm->lock);
4664 case KVM_SET_NR_MMU_PAGES:
4665 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4667 case KVM_GET_NR_MMU_PAGES:
4668 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4670 case KVM_CREATE_IRQCHIP: {
4671 mutex_lock(&kvm->lock);
4674 if (irqchip_in_kernel(kvm))
4675 goto create_irqchip_unlock;
4678 if (kvm->created_vcpus)
4679 goto create_irqchip_unlock;
4681 r = kvm_pic_init(kvm);
4683 goto create_irqchip_unlock;
4685 r = kvm_ioapic_init(kvm);
4687 kvm_pic_destroy(kvm);
4688 goto create_irqchip_unlock;
4691 r = kvm_setup_default_irq_routing(kvm);
4693 kvm_ioapic_destroy(kvm);
4694 kvm_pic_destroy(kvm);
4695 goto create_irqchip_unlock;
4697 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4699 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4700 create_irqchip_unlock:
4701 mutex_unlock(&kvm->lock);
4704 case KVM_CREATE_PIT:
4705 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4707 case KVM_CREATE_PIT2:
4709 if (copy_from_user(&u.pit_config, argp,
4710 sizeof(struct kvm_pit_config)))
4713 mutex_lock(&kvm->lock);
4716 goto create_pit_unlock;
4718 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4722 mutex_unlock(&kvm->lock);
4724 case KVM_GET_IRQCHIP: {
4725 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4726 struct kvm_irqchip *chip;
4728 chip = memdup_user(argp, sizeof(*chip));
4735 if (!irqchip_kernel(kvm))
4736 goto get_irqchip_out;
4737 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4739 goto get_irqchip_out;
4741 if (copy_to_user(argp, chip, sizeof(*chip)))
4742 goto get_irqchip_out;
4748 case KVM_SET_IRQCHIP: {
4749 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4750 struct kvm_irqchip *chip;
4752 chip = memdup_user(argp, sizeof(*chip));
4759 if (!irqchip_kernel(kvm))
4760 goto set_irqchip_out;
4761 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4763 goto set_irqchip_out;
4771 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4774 if (!kvm->arch.vpit)
4776 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4780 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4787 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4790 if (!kvm->arch.vpit)
4792 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4795 case KVM_GET_PIT2: {
4797 if (!kvm->arch.vpit)
4799 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4803 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4808 case KVM_SET_PIT2: {
4810 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4813 if (!kvm->arch.vpit)
4815 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4818 case KVM_REINJECT_CONTROL: {
4819 struct kvm_reinject_control control;
4821 if (copy_from_user(&control, argp, sizeof(control)))
4823 r = kvm_vm_ioctl_reinject(kvm, &control);
4826 case KVM_SET_BOOT_CPU_ID:
4828 mutex_lock(&kvm->lock);
4829 if (kvm->created_vcpus)
4832 kvm->arch.bsp_vcpu_id = arg;
4833 mutex_unlock(&kvm->lock);
4835 case KVM_XEN_HVM_CONFIG: {
4836 struct kvm_xen_hvm_config xhc;
4838 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4843 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4847 case KVM_SET_CLOCK: {
4848 struct kvm_clock_data user_ns;
4852 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4861 * TODO: userspace has to take care of races with VCPU_RUN, so
4862 * kvm_gen_update_masterclock() can be cut down to locked
4863 * pvclock_update_vm_gtod_copy().
4865 kvm_gen_update_masterclock(kvm);
4866 now_ns = get_kvmclock_ns(kvm);
4867 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4868 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4871 case KVM_GET_CLOCK: {
4872 struct kvm_clock_data user_ns;
4875 now_ns = get_kvmclock_ns(kvm);
4876 user_ns.clock = now_ns;
4877 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4878 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4881 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4886 case KVM_MEMORY_ENCRYPT_OP: {
4888 if (kvm_x86_ops->mem_enc_op)
4889 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4892 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4893 struct kvm_enc_region region;
4896 if (copy_from_user(®ion, argp, sizeof(region)))
4900 if (kvm_x86_ops->mem_enc_reg_region)
4901 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4904 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4905 struct kvm_enc_region region;
4908 if (copy_from_user(®ion, argp, sizeof(region)))
4912 if (kvm_x86_ops->mem_enc_unreg_region)
4913 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4916 case KVM_HYPERV_EVENTFD: {
4917 struct kvm_hyperv_eventfd hvevfd;
4920 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4922 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4932 static void kvm_init_msr_list(void)
4937 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4938 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4942 * Even MSRs that are valid in the host may not be exposed
4943 * to the guests in some cases.
4945 switch (msrs_to_save[i]) {
4946 case MSR_IA32_BNDCFGS:
4947 if (!kvm_mpx_supported())
4951 if (!kvm_x86_ops->rdtscp_supported())
4954 case MSR_IA32_RTIT_CTL:
4955 case MSR_IA32_RTIT_STATUS:
4956 if (!kvm_x86_ops->pt_supported())
4959 case MSR_IA32_RTIT_CR3_MATCH:
4960 if (!kvm_x86_ops->pt_supported() ||
4961 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4964 case MSR_IA32_RTIT_OUTPUT_BASE:
4965 case MSR_IA32_RTIT_OUTPUT_MASK:
4966 if (!kvm_x86_ops->pt_supported() ||
4967 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4968 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4971 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4972 if (!kvm_x86_ops->pt_supported() ||
4973 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4974 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4983 msrs_to_save[j] = msrs_to_save[i];
4986 num_msrs_to_save = j;
4988 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4989 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4993 emulated_msrs[j] = emulated_msrs[i];
4996 num_emulated_msrs = j;
4998 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4999 struct kvm_msr_entry msr;
5001 msr.index = msr_based_features[i];
5002 if (kvm_get_msr_feature(&msr))
5006 msr_based_features[j] = msr_based_features[i];
5009 num_msr_based_features = j;
5012 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5020 if (!(lapic_in_kernel(vcpu) &&
5021 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5022 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5033 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5040 if (!(lapic_in_kernel(vcpu) &&
5041 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5043 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5045 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5055 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5056 struct kvm_segment *var, int seg)
5058 kvm_x86_ops->set_segment(vcpu, var, seg);
5061 void kvm_get_segment(struct kvm_vcpu *vcpu,
5062 struct kvm_segment *var, int seg)
5064 kvm_x86_ops->get_segment(vcpu, var, seg);
5067 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5068 struct x86_exception *exception)
5072 BUG_ON(!mmu_is_nested(vcpu));
5074 /* NPT walks are always user-walks */
5075 access |= PFERR_USER_MASK;
5076 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5081 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5082 struct x86_exception *exception)
5084 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5085 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5088 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5089 struct x86_exception *exception)
5091 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5092 access |= PFERR_FETCH_MASK;
5093 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5096 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5097 struct x86_exception *exception)
5099 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5100 access |= PFERR_WRITE_MASK;
5101 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5104 /* uses this to access any guest's mapped memory without checking CPL */
5105 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5106 struct x86_exception *exception)
5108 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5111 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5112 struct kvm_vcpu *vcpu, u32 access,
5113 struct x86_exception *exception)
5116 int r = X86EMUL_CONTINUE;
5119 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5121 unsigned offset = addr & (PAGE_SIZE-1);
5122 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5125 if (gpa == UNMAPPED_GVA)
5126 return X86EMUL_PROPAGATE_FAULT;
5127 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5130 r = X86EMUL_IO_NEEDED;
5142 /* used for instruction fetching */
5143 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5144 gva_t addr, void *val, unsigned int bytes,
5145 struct x86_exception *exception)
5147 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5148 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5152 /* Inline kvm_read_guest_virt_helper for speed. */
5153 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5155 if (unlikely(gpa == UNMAPPED_GVA))
5156 return X86EMUL_PROPAGATE_FAULT;
5158 offset = addr & (PAGE_SIZE-1);
5159 if (WARN_ON(offset + bytes > PAGE_SIZE))
5160 bytes = (unsigned)PAGE_SIZE - offset;
5161 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5163 if (unlikely(ret < 0))
5164 return X86EMUL_IO_NEEDED;
5166 return X86EMUL_CONTINUE;
5169 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5170 gva_t addr, void *val, unsigned int bytes,
5171 struct x86_exception *exception)
5173 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5176 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5177 * is returned, but our callers are not ready for that and they blindly
5178 * call kvm_inject_page_fault. Ensure that they at least do not leak
5179 * uninitialized kernel stack memory into cr2 and error code.
5181 memset(exception, 0, sizeof(*exception));
5182 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5185 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5187 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5188 gva_t addr, void *val, unsigned int bytes,
5189 struct x86_exception *exception, bool system)
5191 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5194 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5195 access |= PFERR_USER_MASK;
5197 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5200 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5201 unsigned long addr, void *val, unsigned int bytes)
5203 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5204 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5206 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5209 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5210 struct kvm_vcpu *vcpu, u32 access,
5211 struct x86_exception *exception)
5214 int r = X86EMUL_CONTINUE;
5217 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5220 unsigned offset = addr & (PAGE_SIZE-1);
5221 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5224 if (gpa == UNMAPPED_GVA)
5225 return X86EMUL_PROPAGATE_FAULT;
5226 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5228 r = X86EMUL_IO_NEEDED;
5240 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5241 unsigned int bytes, struct x86_exception *exception,
5244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5245 u32 access = PFERR_WRITE_MASK;
5247 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5248 access |= PFERR_USER_MASK;
5250 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5254 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5255 unsigned int bytes, struct x86_exception *exception)
5257 /* kvm_write_guest_virt_system can pull in tons of pages. */
5258 vcpu->arch.l1tf_flush_l1d = true;
5260 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5261 PFERR_WRITE_MASK, exception);
5263 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5265 int handle_ud(struct kvm_vcpu *vcpu)
5267 int emul_type = EMULTYPE_TRAP_UD;
5268 enum emulation_result er;
5269 char sig[5]; /* ud2; .ascii "kvm" */
5270 struct x86_exception e;
5272 if (force_emulation_prefix &&
5273 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5274 sig, sizeof(sig), &e) == 0 &&
5275 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5276 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5280 er = kvm_emulate_instruction(vcpu, emul_type);
5281 if (er == EMULATE_USER_EXIT)
5283 if (er != EMULATE_DONE)
5284 kvm_queue_exception(vcpu, UD_VECTOR);
5287 EXPORT_SYMBOL_GPL(handle_ud);
5289 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5290 gpa_t gpa, bool write)
5292 /* For APIC access vmexit */
5293 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5296 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5297 trace_vcpu_match_mmio(gva, gpa, write, true);
5304 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5305 gpa_t *gpa, struct x86_exception *exception,
5308 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5309 | (write ? PFERR_WRITE_MASK : 0);
5312 * currently PKRU is only applied to ept enabled guest so
5313 * there is no pkey in EPT page table for L1 guest or EPT
5314 * shadow page table for L2 guest.
5316 if (vcpu_match_mmio_gva(vcpu, gva)
5317 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5318 vcpu->arch.access, 0, access)) {
5319 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5320 (gva & (PAGE_SIZE - 1));
5321 trace_vcpu_match_mmio(gva, *gpa, write, false);
5325 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5327 if (*gpa == UNMAPPED_GVA)
5330 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5333 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5334 const void *val, int bytes)
5338 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5341 kvm_page_track_write(vcpu, gpa, val, bytes);
5345 struct read_write_emulator_ops {
5346 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5348 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5349 void *val, int bytes);
5350 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5351 int bytes, void *val);
5352 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5353 void *val, int bytes);
5357 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5359 if (vcpu->mmio_read_completed) {
5360 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5361 vcpu->mmio_fragments[0].gpa, val);
5362 vcpu->mmio_read_completed = 0;
5369 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5370 void *val, int bytes)
5372 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5375 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5376 void *val, int bytes)
5378 return emulator_write_phys(vcpu, gpa, val, bytes);
5381 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5383 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5384 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5387 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5388 void *val, int bytes)
5390 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5391 return X86EMUL_IO_NEEDED;
5394 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5395 void *val, int bytes)
5397 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5399 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5400 return X86EMUL_CONTINUE;
5403 static const struct read_write_emulator_ops read_emultor = {
5404 .read_write_prepare = read_prepare,
5405 .read_write_emulate = read_emulate,
5406 .read_write_mmio = vcpu_mmio_read,
5407 .read_write_exit_mmio = read_exit_mmio,
5410 static const struct read_write_emulator_ops write_emultor = {
5411 .read_write_emulate = write_emulate,
5412 .read_write_mmio = write_mmio,
5413 .read_write_exit_mmio = write_exit_mmio,
5417 static int emulator_read_write_onepage(unsigned long addr, void *val,
5419 struct x86_exception *exception,
5420 struct kvm_vcpu *vcpu,
5421 const struct read_write_emulator_ops *ops)
5425 bool write = ops->write;
5426 struct kvm_mmio_fragment *frag;
5427 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5430 * If the exit was due to a NPF we may already have a GPA.
5431 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5432 * Note, this cannot be used on string operations since string
5433 * operation using rep will only have the initial GPA from the NPF
5436 if (vcpu->arch.gpa_available &&
5437 emulator_can_use_gpa(ctxt) &&
5438 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5439 gpa = vcpu->arch.gpa_val;
5440 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5442 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5444 return X86EMUL_PROPAGATE_FAULT;
5447 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5448 return X86EMUL_CONTINUE;
5451 * Is this MMIO handled locally?
5453 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5454 if (handled == bytes)
5455 return X86EMUL_CONTINUE;
5461 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5462 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5466 return X86EMUL_CONTINUE;
5469 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5471 void *val, unsigned int bytes,
5472 struct x86_exception *exception,
5473 const struct read_write_emulator_ops *ops)
5475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5479 if (ops->read_write_prepare &&
5480 ops->read_write_prepare(vcpu, val, bytes))
5481 return X86EMUL_CONTINUE;
5483 vcpu->mmio_nr_fragments = 0;
5485 /* Crossing a page boundary? */
5486 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5489 now = -addr & ~PAGE_MASK;
5490 rc = emulator_read_write_onepage(addr, val, now, exception,
5493 if (rc != X86EMUL_CONTINUE)
5496 if (ctxt->mode != X86EMUL_MODE_PROT64)
5502 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5504 if (rc != X86EMUL_CONTINUE)
5507 if (!vcpu->mmio_nr_fragments)
5510 gpa = vcpu->mmio_fragments[0].gpa;
5512 vcpu->mmio_needed = 1;
5513 vcpu->mmio_cur_fragment = 0;
5515 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5516 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5517 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5518 vcpu->run->mmio.phys_addr = gpa;
5520 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5523 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5527 struct x86_exception *exception)
5529 return emulator_read_write(ctxt, addr, val, bytes,
5530 exception, &read_emultor);
5533 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5537 struct x86_exception *exception)
5539 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5540 exception, &write_emultor);
5543 #define CMPXCHG_TYPE(t, ptr, old, new) \
5544 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5546 #ifdef CONFIG_X86_64
5547 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5549 # define CMPXCHG64(ptr, old, new) \
5550 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5553 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5558 struct x86_exception *exception)
5560 struct kvm_host_map map;
5561 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5566 /* guests cmpxchg8b have to be emulated atomically */
5567 if (bytes > 8 || (bytes & (bytes - 1)))
5570 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5572 if (gpa == UNMAPPED_GVA ||
5573 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5576 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5579 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5582 kaddr = map.hva + offset_in_page(gpa);
5586 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5589 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5592 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5595 exchanged = CMPXCHG64(kaddr, old, new);
5601 kvm_vcpu_unmap(vcpu, &map, true);
5604 return X86EMUL_CMPXCHG_FAILED;
5606 kvm_page_track_write(vcpu, gpa, new, bytes);
5608 return X86EMUL_CONTINUE;
5611 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5613 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5616 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5620 for (i = 0; i < vcpu->arch.pio.count; i++) {
5621 if (vcpu->arch.pio.in)
5622 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5623 vcpu->arch.pio.size, pd);
5625 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5626 vcpu->arch.pio.port, vcpu->arch.pio.size,
5630 pd += vcpu->arch.pio.size;
5635 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5636 unsigned short port, void *val,
5637 unsigned int count, bool in)
5639 vcpu->arch.pio.port = port;
5640 vcpu->arch.pio.in = in;
5641 vcpu->arch.pio.count = count;
5642 vcpu->arch.pio.size = size;
5644 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5645 vcpu->arch.pio.count = 0;
5649 vcpu->run->exit_reason = KVM_EXIT_IO;
5650 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5651 vcpu->run->io.size = size;
5652 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5653 vcpu->run->io.count = count;
5654 vcpu->run->io.port = port;
5659 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5660 int size, unsigned short port, void *val,
5663 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5666 if (vcpu->arch.pio.count)
5669 memset(vcpu->arch.pio_data, 0, size * count);
5671 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5674 memcpy(val, vcpu->arch.pio_data, size * count);
5675 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5676 vcpu->arch.pio.count = 0;
5683 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5684 int size, unsigned short port,
5685 const void *val, unsigned int count)
5687 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5689 memcpy(vcpu->arch.pio_data, val, size * count);
5690 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5691 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5694 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5696 return kvm_x86_ops->get_segment_base(vcpu, seg);
5699 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5701 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5704 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5706 if (!need_emulate_wbinvd(vcpu))
5707 return X86EMUL_CONTINUE;
5709 if (kvm_x86_ops->has_wbinvd_exit()) {
5710 int cpu = get_cpu();
5712 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5713 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5714 wbinvd_ipi, NULL, 1);
5716 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5719 return X86EMUL_CONTINUE;
5722 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5724 kvm_emulate_wbinvd_noskip(vcpu);
5725 return kvm_skip_emulated_instruction(vcpu);
5727 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5731 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5733 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5736 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5737 unsigned long *dest)
5739 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5742 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5743 unsigned long value)
5746 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5749 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5751 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5754 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5756 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5757 unsigned long value;
5761 value = kvm_read_cr0(vcpu);
5764 value = vcpu->arch.cr2;
5767 value = kvm_read_cr3(vcpu);
5770 value = kvm_read_cr4(vcpu);
5773 value = kvm_get_cr8(vcpu);
5776 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5783 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5785 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5790 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5793 vcpu->arch.cr2 = val;
5796 res = kvm_set_cr3(vcpu, val);
5799 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5802 res = kvm_set_cr8(vcpu, val);
5805 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5812 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5814 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5817 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5819 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5822 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5824 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5827 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5829 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5832 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5834 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5837 static unsigned long emulator_get_cached_segment_base(
5838 struct x86_emulate_ctxt *ctxt, int seg)
5840 return get_segment_base(emul_to_vcpu(ctxt), seg);
5843 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5844 struct desc_struct *desc, u32 *base3,
5847 struct kvm_segment var;
5849 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5850 *selector = var.selector;
5853 memset(desc, 0, sizeof(*desc));
5861 set_desc_limit(desc, var.limit);
5862 set_desc_base(desc, (unsigned long)var.base);
5863 #ifdef CONFIG_X86_64
5865 *base3 = var.base >> 32;
5867 desc->type = var.type;
5869 desc->dpl = var.dpl;
5870 desc->p = var.present;
5871 desc->avl = var.avl;
5879 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5880 struct desc_struct *desc, u32 base3,
5883 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5884 struct kvm_segment var;
5886 var.selector = selector;
5887 var.base = get_desc_base(desc);
5888 #ifdef CONFIG_X86_64
5889 var.base |= ((u64)base3) << 32;
5891 var.limit = get_desc_limit(desc);
5893 var.limit = (var.limit << 12) | 0xfff;
5894 var.type = desc->type;
5895 var.dpl = desc->dpl;
5900 var.avl = desc->avl;
5901 var.present = desc->p;
5902 var.unusable = !var.present;
5905 kvm_set_segment(vcpu, &var, seg);
5909 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5910 u32 msr_index, u64 *pdata)
5912 struct msr_data msr;
5915 msr.index = msr_index;
5916 msr.host_initiated = false;
5917 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5925 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5926 u32 msr_index, u64 data)
5928 struct msr_data msr;
5931 msr.index = msr_index;
5932 msr.host_initiated = false;
5933 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5936 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5940 return vcpu->arch.smbase;
5943 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5945 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5947 vcpu->arch.smbase = smbase;
5950 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5953 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5956 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5957 u32 pmc, u64 *pdata)
5959 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5962 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5964 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5967 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5968 struct x86_instruction_info *info,
5969 enum x86_intercept_stage stage)
5971 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5974 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5975 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5977 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5980 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5982 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5985 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5987 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5990 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5992 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5995 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5997 return emul_to_vcpu(ctxt)->arch.hflags;
6000 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6002 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6005 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6006 const char *smstate)
6008 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6011 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6013 kvm_smm_changed(emul_to_vcpu(ctxt));
6016 static const struct x86_emulate_ops emulate_ops = {
6017 .read_gpr = emulator_read_gpr,
6018 .write_gpr = emulator_write_gpr,
6019 .read_std = emulator_read_std,
6020 .write_std = emulator_write_std,
6021 .read_phys = kvm_read_guest_phys_system,
6022 .fetch = kvm_fetch_guest_virt,
6023 .read_emulated = emulator_read_emulated,
6024 .write_emulated = emulator_write_emulated,
6025 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6026 .invlpg = emulator_invlpg,
6027 .pio_in_emulated = emulator_pio_in_emulated,
6028 .pio_out_emulated = emulator_pio_out_emulated,
6029 .get_segment = emulator_get_segment,
6030 .set_segment = emulator_set_segment,
6031 .get_cached_segment_base = emulator_get_cached_segment_base,
6032 .get_gdt = emulator_get_gdt,
6033 .get_idt = emulator_get_idt,
6034 .set_gdt = emulator_set_gdt,
6035 .set_idt = emulator_set_idt,
6036 .get_cr = emulator_get_cr,
6037 .set_cr = emulator_set_cr,
6038 .cpl = emulator_get_cpl,
6039 .get_dr = emulator_get_dr,
6040 .set_dr = emulator_set_dr,
6041 .get_smbase = emulator_get_smbase,
6042 .set_smbase = emulator_set_smbase,
6043 .set_msr = emulator_set_msr,
6044 .get_msr = emulator_get_msr,
6045 .check_pmc = emulator_check_pmc,
6046 .read_pmc = emulator_read_pmc,
6047 .halt = emulator_halt,
6048 .wbinvd = emulator_wbinvd,
6049 .fix_hypercall = emulator_fix_hypercall,
6050 .intercept = emulator_intercept,
6051 .get_cpuid = emulator_get_cpuid,
6052 .set_nmi_mask = emulator_set_nmi_mask,
6053 .get_hflags = emulator_get_hflags,
6054 .set_hflags = emulator_set_hflags,
6055 .pre_leave_smm = emulator_pre_leave_smm,
6056 .post_leave_smm = emulator_post_leave_smm,
6059 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6061 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6063 * an sti; sti; sequence only disable interrupts for the first
6064 * instruction. So, if the last instruction, be it emulated or
6065 * not, left the system with the INT_STI flag enabled, it
6066 * means that the last instruction is an sti. We should not
6067 * leave the flag on in this case. The same goes for mov ss
6069 if (int_shadow & mask)
6071 if (unlikely(int_shadow || mask)) {
6072 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6074 kvm_make_request(KVM_REQ_EVENT, vcpu);
6078 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6080 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6081 if (ctxt->exception.vector == PF_VECTOR)
6082 return kvm_propagate_fault(vcpu, &ctxt->exception);
6084 if (ctxt->exception.error_code_valid)
6085 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6086 ctxt->exception.error_code);
6088 kvm_queue_exception(vcpu, ctxt->exception.vector);
6092 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6094 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6097 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6099 ctxt->eflags = kvm_get_rflags(vcpu);
6100 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6102 ctxt->eip = kvm_rip_read(vcpu);
6103 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6104 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6105 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6106 cs_db ? X86EMUL_MODE_PROT32 :
6107 X86EMUL_MODE_PROT16;
6108 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6109 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6110 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6112 init_decode_cache(ctxt);
6113 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6116 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6118 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6121 init_emulate_ctxt(vcpu);
6125 ctxt->_eip = ctxt->eip + inc_eip;
6126 ret = emulate_int_real(ctxt, irq);
6128 if (ret != X86EMUL_CONTINUE)
6129 return EMULATE_FAIL;
6131 ctxt->eip = ctxt->_eip;
6132 kvm_rip_write(vcpu, ctxt->eip);
6133 kvm_set_rflags(vcpu, ctxt->eflags);
6135 return EMULATE_DONE;
6137 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6139 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6141 int r = EMULATE_DONE;
6143 ++vcpu->stat.insn_emulation_fail;
6144 trace_kvm_emulate_insn_failed(vcpu);
6146 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6147 return EMULATE_FAIL;
6149 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6150 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6151 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6152 vcpu->run->internal.ndata = 0;
6153 r = EMULATE_USER_EXIT;
6156 kvm_queue_exception(vcpu, UD_VECTOR);
6161 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6162 bool write_fault_to_shadow_pgtable,
6168 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6171 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6174 if (!vcpu->arch.mmu->direct_map) {
6176 * Write permission should be allowed since only
6177 * write access need to be emulated.
6179 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6182 * If the mapping is invalid in guest, let cpu retry
6183 * it to generate fault.
6185 if (gpa == UNMAPPED_GVA)
6190 * Do not retry the unhandleable instruction if it faults on the
6191 * readonly host memory, otherwise it will goto a infinite loop:
6192 * retry instruction -> write #PF -> emulation fail -> retry
6193 * instruction -> ...
6195 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6198 * If the instruction failed on the error pfn, it can not be fixed,
6199 * report the error to userspace.
6201 if (is_error_noslot_pfn(pfn))
6204 kvm_release_pfn_clean(pfn);
6206 /* The instructions are well-emulated on direct mmu. */
6207 if (vcpu->arch.mmu->direct_map) {
6208 unsigned int indirect_shadow_pages;
6210 spin_lock(&vcpu->kvm->mmu_lock);
6211 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6212 spin_unlock(&vcpu->kvm->mmu_lock);
6214 if (indirect_shadow_pages)
6215 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6221 * if emulation was due to access to shadowed page table
6222 * and it failed try to unshadow page and re-enter the
6223 * guest to let CPU execute the instruction.
6225 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6228 * If the access faults on its page table, it can not
6229 * be fixed by unprotecting shadow page and it should
6230 * be reported to userspace.
6232 return !write_fault_to_shadow_pgtable;
6235 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6236 unsigned long cr2, int emulation_type)
6238 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6239 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6241 last_retry_eip = vcpu->arch.last_retry_eip;
6242 last_retry_addr = vcpu->arch.last_retry_addr;
6245 * If the emulation is caused by #PF and it is non-page_table
6246 * writing instruction, it means the VM-EXIT is caused by shadow
6247 * page protected, we can zap the shadow page and retry this
6248 * instruction directly.
6250 * Note: if the guest uses a non-page-table modifying instruction
6251 * on the PDE that points to the instruction, then we will unmap
6252 * the instruction and go to an infinite loop. So, we cache the
6253 * last retried eip and the last fault address, if we meet the eip
6254 * and the address again, we can break out of the potential infinite
6257 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6259 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6262 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6265 if (x86_page_table_writing_insn(ctxt))
6268 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6271 vcpu->arch.last_retry_eip = ctxt->eip;
6272 vcpu->arch.last_retry_addr = cr2;
6274 if (!vcpu->arch.mmu->direct_map)
6275 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6277 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6282 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6283 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6285 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6287 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6288 /* This is a good place to trace that we are exiting SMM. */
6289 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6291 /* Process a latched INIT or SMI, if any. */
6292 kvm_make_request(KVM_REQ_EVENT, vcpu);
6295 kvm_mmu_reset_context(vcpu);
6298 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6307 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6308 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6313 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6315 struct kvm_run *kvm_run = vcpu->run;
6317 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6318 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6319 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6320 kvm_run->debug.arch.exception = DB_VECTOR;
6321 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6322 *r = EMULATE_USER_EXIT;
6324 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6328 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6330 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6331 int r = EMULATE_DONE;
6333 kvm_x86_ops->skip_emulated_instruction(vcpu);
6336 * rflags is the old, "raw" value of the flags. The new value has
6337 * not been saved yet.
6339 * This is correct even for TF set by the guest, because "the
6340 * processor will not generate this exception after the instruction
6341 * that sets the TF flag".
6343 if (unlikely(rflags & X86_EFLAGS_TF))
6344 kvm_vcpu_do_singlestep(vcpu, &r);
6345 return r == EMULATE_DONE;
6347 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6349 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6351 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6352 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6353 struct kvm_run *kvm_run = vcpu->run;
6354 unsigned long eip = kvm_get_linear_rip(vcpu);
6355 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6356 vcpu->arch.guest_debug_dr7,
6360 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6361 kvm_run->debug.arch.pc = eip;
6362 kvm_run->debug.arch.exception = DB_VECTOR;
6363 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6364 *r = EMULATE_USER_EXIT;
6369 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6370 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6371 unsigned long eip = kvm_get_linear_rip(vcpu);
6372 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6377 vcpu->arch.dr6 &= ~15;
6378 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6379 kvm_queue_exception(vcpu, DB_VECTOR);
6388 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6390 switch (ctxt->opcode_len) {
6397 case 0xe6: /* OUT */
6401 case 0x6c: /* INS */
6403 case 0x6e: /* OUTS */
6410 case 0x33: /* RDPMC */
6419 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6426 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6427 bool writeback = true;
6428 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6430 vcpu->arch.l1tf_flush_l1d = true;
6433 * Clear write_fault_to_shadow_pgtable here to ensure it is
6436 vcpu->arch.write_fault_to_shadow_pgtable = false;
6437 kvm_clear_exception_queue(vcpu);
6439 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6440 init_emulate_ctxt(vcpu);
6443 * We will reenter on the same instruction since
6444 * we do not set complete_userspace_io. This does not
6445 * handle watchpoints yet, those would be handled in
6448 if (!(emulation_type & EMULTYPE_SKIP) &&
6449 kvm_vcpu_check_breakpoint(vcpu, &r))
6452 ctxt->interruptibility = 0;
6453 ctxt->have_exception = false;
6454 ctxt->exception.vector = -1;
6455 ctxt->perm_ok = false;
6457 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6459 r = x86_decode_insn(ctxt, insn, insn_len);
6461 trace_kvm_emulate_insn_start(vcpu);
6462 ++vcpu->stat.insn_emulation;
6463 if (r != EMULATION_OK) {
6464 if (emulation_type & EMULTYPE_TRAP_UD)
6465 return EMULATE_FAIL;
6466 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6468 return EMULATE_DONE;
6469 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6470 return EMULATE_DONE;
6471 if (emulation_type & EMULTYPE_SKIP)
6472 return EMULATE_FAIL;
6473 return handle_emulation_failure(vcpu, emulation_type);
6477 if ((emulation_type & EMULTYPE_VMWARE) &&
6478 !is_vmware_backdoor_opcode(ctxt))
6479 return EMULATE_FAIL;
6481 if (emulation_type & EMULTYPE_SKIP) {
6482 kvm_rip_write(vcpu, ctxt->_eip);
6483 if (ctxt->eflags & X86_EFLAGS_RF)
6484 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6485 return EMULATE_DONE;
6488 if (retry_instruction(ctxt, cr2, emulation_type))
6489 return EMULATE_DONE;
6491 /* this is needed for vmware backdoor interface to work since it
6492 changes registers values during IO operation */
6493 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6494 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6495 emulator_invalidate_register_cache(ctxt);
6499 /* Save the faulting GPA (cr2) in the address field */
6500 ctxt->exception.address = cr2;
6502 r = x86_emulate_insn(ctxt);
6504 if (r == EMULATION_INTERCEPTED)
6505 return EMULATE_DONE;
6507 if (r == EMULATION_FAILED) {
6508 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6510 return EMULATE_DONE;
6512 return handle_emulation_failure(vcpu, emulation_type);
6515 if (ctxt->have_exception) {
6517 if (inject_emulated_exception(vcpu))
6519 } else if (vcpu->arch.pio.count) {
6520 if (!vcpu->arch.pio.in) {
6521 /* FIXME: return into emulator if single-stepping. */
6522 vcpu->arch.pio.count = 0;
6525 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6527 r = EMULATE_USER_EXIT;
6528 } else if (vcpu->mmio_needed) {
6529 if (!vcpu->mmio_is_write)
6531 r = EMULATE_USER_EXIT;
6532 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6533 } else if (r == EMULATION_RESTART)
6539 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6540 toggle_interruptibility(vcpu, ctxt->interruptibility);
6541 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6542 kvm_rip_write(vcpu, ctxt->eip);
6543 if (r == EMULATE_DONE && ctxt->tf)
6544 kvm_vcpu_do_singlestep(vcpu, &r);
6545 if (!ctxt->have_exception ||
6546 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6547 __kvm_set_rflags(vcpu, ctxt->eflags);
6550 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6551 * do nothing, and it will be requested again as soon as
6552 * the shadow expires. But we still need to check here,
6553 * because POPF has no interrupt shadow.
6555 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6556 kvm_make_request(KVM_REQ_EVENT, vcpu);
6558 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6563 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6565 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6567 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6569 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6570 void *insn, int insn_len)
6572 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6574 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6576 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6578 vcpu->arch.pio.count = 0;
6580 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6583 return kvm_skip_emulated_instruction(vcpu);
6586 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6587 unsigned short port)
6589 unsigned long val = kvm_rax_read(vcpu);
6590 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6591 size, port, &val, 1);
6594 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6595 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6600 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6604 /* We should only ever be called with arch.pio.count equal to 1 */
6605 BUG_ON(vcpu->arch.pio.count != 1);
6607 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6608 vcpu->arch.pio.count = 0;
6612 /* For size less than 4 we merge, else we zero extend */
6613 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6616 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6617 * the copy and tracing
6619 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6620 vcpu->arch.pio.port, &val, 1);
6621 kvm_rax_write(vcpu, val);
6623 return kvm_skip_emulated_instruction(vcpu);
6626 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6627 unsigned short port)
6632 /* For size less than 4 we merge, else we zero extend */
6633 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6635 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6638 kvm_rax_write(vcpu, val);
6642 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6643 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6648 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6653 ret = kvm_fast_pio_in(vcpu, size, port);
6655 ret = kvm_fast_pio_out(vcpu, size, port);
6656 return ret && kvm_skip_emulated_instruction(vcpu);
6658 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6660 static int kvmclock_cpu_down_prep(unsigned int cpu)
6662 __this_cpu_write(cpu_tsc_khz, 0);
6666 static void tsc_khz_changed(void *data)
6668 struct cpufreq_freqs *freq = data;
6669 unsigned long khz = 0;
6673 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6674 khz = cpufreq_quick_get(raw_smp_processor_id());
6677 __this_cpu_write(cpu_tsc_khz, khz);
6680 #ifdef CONFIG_X86_64
6681 static void kvm_hyperv_tsc_notifier(void)
6684 struct kvm_vcpu *vcpu;
6687 spin_lock(&kvm_lock);
6688 list_for_each_entry(kvm, &vm_list, vm_list)
6689 kvm_make_mclock_inprogress_request(kvm);
6691 hyperv_stop_tsc_emulation();
6693 /* TSC frequency always matches when on Hyper-V */
6694 for_each_present_cpu(cpu)
6695 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6696 kvm_max_guest_tsc_khz = tsc_khz;
6698 list_for_each_entry(kvm, &vm_list, vm_list) {
6699 struct kvm_arch *ka = &kvm->arch;
6701 spin_lock(&ka->pvclock_gtod_sync_lock);
6703 pvclock_update_vm_gtod_copy(kvm);
6705 kvm_for_each_vcpu(cpu, vcpu, kvm)
6706 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6708 kvm_for_each_vcpu(cpu, vcpu, kvm)
6709 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6711 spin_unlock(&ka->pvclock_gtod_sync_lock);
6713 spin_unlock(&kvm_lock);
6717 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6720 struct cpufreq_freqs *freq = data;
6722 struct kvm_vcpu *vcpu;
6723 int i, send_ipi = 0;
6726 * We allow guests to temporarily run on slowing clocks,
6727 * provided we notify them after, or to run on accelerating
6728 * clocks, provided we notify them before. Thus time never
6731 * However, we have a problem. We can't atomically update
6732 * the frequency of a given CPU from this function; it is
6733 * merely a notifier, which can be called from any CPU.
6734 * Changing the TSC frequency at arbitrary points in time
6735 * requires a recomputation of local variables related to
6736 * the TSC for each VCPU. We must flag these local variables
6737 * to be updated and be sure the update takes place with the
6738 * new frequency before any guests proceed.
6740 * Unfortunately, the combination of hotplug CPU and frequency
6741 * change creates an intractable locking scenario; the order
6742 * of when these callouts happen is undefined with respect to
6743 * CPU hotplug, and they can race with each other. As such,
6744 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6745 * undefined; you can actually have a CPU frequency change take
6746 * place in between the computation of X and the setting of the
6747 * variable. To protect against this problem, all updates of
6748 * the per_cpu tsc_khz variable are done in an interrupt
6749 * protected IPI, and all callers wishing to update the value
6750 * must wait for a synchronous IPI to complete (which is trivial
6751 * if the caller is on the CPU already). This establishes the
6752 * necessary total order on variable updates.
6754 * Note that because a guest time update may take place
6755 * anytime after the setting of the VCPU's request bit, the
6756 * correct TSC value must be set before the request. However,
6757 * to ensure the update actually makes it to any guest which
6758 * starts running in hardware virtualization between the set
6759 * and the acquisition of the spinlock, we must also ping the
6760 * CPU after setting the request bit.
6764 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6766 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6769 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6771 spin_lock(&kvm_lock);
6772 list_for_each_entry(kvm, &vm_list, vm_list) {
6773 kvm_for_each_vcpu(i, vcpu, kvm) {
6774 if (vcpu->cpu != freq->cpu)
6776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6777 if (vcpu->cpu != smp_processor_id())
6781 spin_unlock(&kvm_lock);
6783 if (freq->old < freq->new && send_ipi) {
6785 * We upscale the frequency. Must make the guest
6786 * doesn't see old kvmclock values while running with
6787 * the new frequency, otherwise we risk the guest sees
6788 * time go backwards.
6790 * In case we update the frequency for another cpu
6791 * (which might be in guest context) send an interrupt
6792 * to kick the cpu out of guest context. Next time
6793 * guest context is entered kvmclock will be updated,
6794 * so the guest will not see stale values.
6796 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6801 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6802 .notifier_call = kvmclock_cpufreq_notifier
6805 static int kvmclock_cpu_online(unsigned int cpu)
6807 tsc_khz_changed(NULL);
6811 static void kvm_timer_init(void)
6813 max_tsc_khz = tsc_khz;
6815 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6816 #ifdef CONFIG_CPU_FREQ
6817 struct cpufreq_policy policy;
6820 memset(&policy, 0, sizeof(policy));
6822 cpufreq_get_policy(&policy, cpu);
6823 if (policy.cpuinfo.max_freq)
6824 max_tsc_khz = policy.cpuinfo.max_freq;
6827 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6828 CPUFREQ_TRANSITION_NOTIFIER);
6830 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6832 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6833 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6836 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6837 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6839 int kvm_is_in_guest(void)
6841 return __this_cpu_read(current_vcpu) != NULL;
6844 static int kvm_is_user_mode(void)
6848 if (__this_cpu_read(current_vcpu))
6849 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6851 return user_mode != 0;
6854 static unsigned long kvm_get_guest_ip(void)
6856 unsigned long ip = 0;
6858 if (__this_cpu_read(current_vcpu))
6859 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6864 static void kvm_handle_intel_pt_intr(void)
6866 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6868 kvm_make_request(KVM_REQ_PMI, vcpu);
6869 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6870 (unsigned long *)&vcpu->arch.pmu.global_status);
6873 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6874 .is_in_guest = kvm_is_in_guest,
6875 .is_user_mode = kvm_is_user_mode,
6876 .get_guest_ip = kvm_get_guest_ip,
6877 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
6880 static void kvm_set_mmio_spte_mask(void)
6883 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6886 * Set the reserved bits and the present bit of an paging-structure
6887 * entry to generate page fault with PFER.RSV = 1.
6891 * Mask the uppermost physical address bit, which would be reserved as
6892 * long as the supported physical address width is less than 52.
6896 /* Set the present bit. */
6900 * If reserved bit is not supported, clear the present bit to disable
6903 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
6906 kvm_mmu_set_mmio_spte_mask(mask, mask);
6909 #ifdef CONFIG_X86_64
6910 static void pvclock_gtod_update_fn(struct work_struct *work)
6914 struct kvm_vcpu *vcpu;
6917 spin_lock(&kvm_lock);
6918 list_for_each_entry(kvm, &vm_list, vm_list)
6919 kvm_for_each_vcpu(i, vcpu, kvm)
6920 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6921 atomic_set(&kvm_guest_has_master_clock, 0);
6922 spin_unlock(&kvm_lock);
6925 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6928 * Notification about pvclock gtod data update.
6930 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6933 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6934 struct timekeeper *tk = priv;
6936 update_pvclock_gtod(tk);
6938 /* disable master clock if host does not trust, or does not
6939 * use, TSC based clocksource.
6941 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6942 atomic_read(&kvm_guest_has_master_clock) != 0)
6943 queue_work(system_long_wq, &pvclock_gtod_work);
6948 static struct notifier_block pvclock_gtod_notifier = {
6949 .notifier_call = pvclock_gtod_notify,
6953 int kvm_arch_init(void *opaque)
6956 struct kvm_x86_ops *ops = opaque;
6959 printk(KERN_ERR "kvm: already loaded the other module\n");
6964 if (!ops->cpu_has_kvm_support()) {
6965 printk(KERN_ERR "kvm: no hardware support\n");
6969 if (ops->disabled_by_bios()) {
6970 printk(KERN_ERR "kvm: disabled by bios\n");
6976 * KVM explicitly assumes that the guest has an FPU and
6977 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6978 * vCPU's FPU state as a fxregs_state struct.
6980 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6981 printk(KERN_ERR "kvm: inadequate fpu\n");
6987 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
6988 __alignof__(struct fpu), SLAB_ACCOUNT,
6990 if (!x86_fpu_cache) {
6991 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6995 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6997 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6998 goto out_free_x86_fpu_cache;
7001 r = kvm_mmu_module_init();
7003 goto out_free_percpu;
7005 kvm_set_mmio_spte_mask();
7009 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7010 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7011 PT_PRESENT_MASK, 0, sme_me_mask);
7014 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7016 if (boot_cpu_has(X86_FEATURE_XSAVE))
7017 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7020 #ifdef CONFIG_X86_64
7021 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7023 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7024 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7030 free_percpu(shared_msrs);
7031 out_free_x86_fpu_cache:
7032 kmem_cache_destroy(x86_fpu_cache);
7037 void kvm_arch_exit(void)
7039 #ifdef CONFIG_X86_64
7040 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7041 clear_hv_tscchange_cb();
7044 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7046 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7047 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7048 CPUFREQ_TRANSITION_NOTIFIER);
7049 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7050 #ifdef CONFIG_X86_64
7051 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7054 kvm_mmu_module_exit();
7055 free_percpu(shared_msrs);
7056 kmem_cache_destroy(x86_fpu_cache);
7059 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7061 ++vcpu->stat.halt_exits;
7062 if (lapic_in_kernel(vcpu)) {
7063 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7066 vcpu->run->exit_reason = KVM_EXIT_HLT;
7070 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7072 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7074 int ret = kvm_skip_emulated_instruction(vcpu);
7076 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7077 * KVM_EXIT_DEBUG here.
7079 return kvm_vcpu_halt(vcpu) && ret;
7081 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7083 #ifdef CONFIG_X86_64
7084 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7085 unsigned long clock_type)
7087 struct kvm_clock_pairing clock_pairing;
7088 struct timespec64 ts;
7092 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7093 return -KVM_EOPNOTSUPP;
7095 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7096 return -KVM_EOPNOTSUPP;
7098 clock_pairing.sec = ts.tv_sec;
7099 clock_pairing.nsec = ts.tv_nsec;
7100 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7101 clock_pairing.flags = 0;
7102 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7105 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7106 sizeof(struct kvm_clock_pairing)))
7114 * kvm_pv_kick_cpu_op: Kick a vcpu.
7116 * @apicid - apicid of vcpu to be kicked.
7118 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7120 struct kvm_lapic_irq lapic_irq;
7122 lapic_irq.shorthand = 0;
7123 lapic_irq.dest_mode = 0;
7124 lapic_irq.level = 0;
7125 lapic_irq.dest_id = apicid;
7126 lapic_irq.msi_redir_hint = false;
7128 lapic_irq.delivery_mode = APIC_DM_REMRD;
7129 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7132 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7134 if (!lapic_in_kernel(vcpu)) {
7135 WARN_ON_ONCE(vcpu->arch.apicv_active);
7138 if (!vcpu->arch.apicv_active)
7141 vcpu->arch.apicv_active = false;
7142 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7145 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7147 unsigned long nr, a0, a1, a2, a3, ret;
7150 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7151 return kvm_hv_hypercall(vcpu);
7153 nr = kvm_rax_read(vcpu);
7154 a0 = kvm_rbx_read(vcpu);
7155 a1 = kvm_rcx_read(vcpu);
7156 a2 = kvm_rdx_read(vcpu);
7157 a3 = kvm_rsi_read(vcpu);
7159 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7161 op_64_bit = is_64_bit_mode(vcpu);
7170 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7176 case KVM_HC_VAPIC_POLL_IRQ:
7179 case KVM_HC_KICK_CPU:
7180 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7183 #ifdef CONFIG_X86_64
7184 case KVM_HC_CLOCK_PAIRING:
7185 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7188 case KVM_HC_SEND_IPI:
7189 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7198 kvm_rax_write(vcpu, ret);
7200 ++vcpu->stat.hypercalls;
7201 return kvm_skip_emulated_instruction(vcpu);
7203 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7205 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7207 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7208 char instruction[3];
7209 unsigned long rip = kvm_rip_read(vcpu);
7211 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7213 return emulator_write_emulated(ctxt, rip, instruction, 3,
7217 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7219 return vcpu->run->request_interrupt_window &&
7220 likely(!pic_in_kernel(vcpu->kvm));
7223 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7225 struct kvm_run *kvm_run = vcpu->run;
7227 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7228 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7229 kvm_run->cr8 = kvm_get_cr8(vcpu);
7230 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7231 kvm_run->ready_for_interrupt_injection =
7232 pic_in_kernel(vcpu->kvm) ||
7233 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7236 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7240 if (!kvm_x86_ops->update_cr8_intercept)
7243 if (!lapic_in_kernel(vcpu))
7246 if (vcpu->arch.apicv_active)
7249 if (!vcpu->arch.apic->vapic_addr)
7250 max_irr = kvm_lapic_find_highest_irr(vcpu);
7257 tpr = kvm_lapic_get_cr8(vcpu);
7259 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7262 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7266 /* try to reinject previous events if any */
7268 if (vcpu->arch.exception.injected)
7269 kvm_x86_ops->queue_exception(vcpu);
7271 * Do not inject an NMI or interrupt if there is a pending
7272 * exception. Exceptions and interrupts are recognized at
7273 * instruction boundaries, i.e. the start of an instruction.
7274 * Trap-like exceptions, e.g. #DB, have higher priority than
7275 * NMIs and interrupts, i.e. traps are recognized before an
7276 * NMI/interrupt that's pending on the same instruction.
7277 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7278 * priority, but are only generated (pended) during instruction
7279 * execution, i.e. a pending fault-like exception means the
7280 * fault occurred on the *previous* instruction and must be
7281 * serviced prior to recognizing any new events in order to
7282 * fully complete the previous instruction.
7284 else if (!vcpu->arch.exception.pending) {
7285 if (vcpu->arch.nmi_injected)
7286 kvm_x86_ops->set_nmi(vcpu);
7287 else if (vcpu->arch.interrupt.injected)
7288 kvm_x86_ops->set_irq(vcpu);
7292 * Call check_nested_events() even if we reinjected a previous event
7293 * in order for caller to determine if it should require immediate-exit
7294 * from L2 to L1 due to pending L1 events which require exit
7297 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7298 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7303 /* try to inject new event if pending */
7304 if (vcpu->arch.exception.pending) {
7305 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7306 vcpu->arch.exception.has_error_code,
7307 vcpu->arch.exception.error_code);
7309 WARN_ON_ONCE(vcpu->arch.exception.injected);
7310 vcpu->arch.exception.pending = false;
7311 vcpu->arch.exception.injected = true;
7313 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7314 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7317 if (vcpu->arch.exception.nr == DB_VECTOR) {
7319 * This code assumes that nSVM doesn't use
7320 * check_nested_events(). If it does, the
7321 * DR6/DR7 changes should happen before L1
7322 * gets a #VMEXIT for an intercepted #DB in
7323 * L2. (Under VMX, on the other hand, the
7324 * DR6/DR7 changes should not happen in the
7325 * event of a VM-exit to L1 for an intercepted
7328 kvm_deliver_exception_payload(vcpu);
7329 if (vcpu->arch.dr7 & DR7_GD) {
7330 vcpu->arch.dr7 &= ~DR7_GD;
7331 kvm_update_dr7(vcpu);
7335 kvm_x86_ops->queue_exception(vcpu);
7338 /* Don't consider new event if we re-injected an event */
7339 if (kvm_event_needs_reinjection(vcpu))
7342 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7343 kvm_x86_ops->smi_allowed(vcpu)) {
7344 vcpu->arch.smi_pending = false;
7345 ++vcpu->arch.smi_count;
7347 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7348 --vcpu->arch.nmi_pending;
7349 vcpu->arch.nmi_injected = true;
7350 kvm_x86_ops->set_nmi(vcpu);
7351 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7353 * Because interrupts can be injected asynchronously, we are
7354 * calling check_nested_events again here to avoid a race condition.
7355 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7356 * proposal and current concerns. Perhaps we should be setting
7357 * KVM_REQ_EVENT only on certain events and not unconditionally?
7359 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7360 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7364 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7365 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7367 kvm_x86_ops->set_irq(vcpu);
7374 static void process_nmi(struct kvm_vcpu *vcpu)
7379 * x86 is limited to one NMI running, and one NMI pending after it.
7380 * If an NMI is already in progress, limit further NMIs to just one.
7381 * Otherwise, allow two (and we'll inject the first one immediately).
7383 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7386 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7387 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7388 kvm_make_request(KVM_REQ_EVENT, vcpu);
7391 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7394 flags |= seg->g << 23;
7395 flags |= seg->db << 22;
7396 flags |= seg->l << 21;
7397 flags |= seg->avl << 20;
7398 flags |= seg->present << 15;
7399 flags |= seg->dpl << 13;
7400 flags |= seg->s << 12;
7401 flags |= seg->type << 8;
7405 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7407 struct kvm_segment seg;
7410 kvm_get_segment(vcpu, &seg, n);
7411 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7414 offset = 0x7f84 + n * 12;
7416 offset = 0x7f2c + (n - 3) * 12;
7418 put_smstate(u32, buf, offset + 8, seg.base);
7419 put_smstate(u32, buf, offset + 4, seg.limit);
7420 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7423 #ifdef CONFIG_X86_64
7424 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7426 struct kvm_segment seg;
7430 kvm_get_segment(vcpu, &seg, n);
7431 offset = 0x7e00 + n * 16;
7433 flags = enter_smm_get_segment_flags(&seg) >> 8;
7434 put_smstate(u16, buf, offset, seg.selector);
7435 put_smstate(u16, buf, offset + 2, flags);
7436 put_smstate(u32, buf, offset + 4, seg.limit);
7437 put_smstate(u64, buf, offset + 8, seg.base);
7441 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7444 struct kvm_segment seg;
7448 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7449 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7450 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7451 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7453 for (i = 0; i < 8; i++)
7454 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7456 kvm_get_dr(vcpu, 6, &val);
7457 put_smstate(u32, buf, 0x7fcc, (u32)val);
7458 kvm_get_dr(vcpu, 7, &val);
7459 put_smstate(u32, buf, 0x7fc8, (u32)val);
7461 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7462 put_smstate(u32, buf, 0x7fc4, seg.selector);
7463 put_smstate(u32, buf, 0x7f64, seg.base);
7464 put_smstate(u32, buf, 0x7f60, seg.limit);
7465 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7467 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7468 put_smstate(u32, buf, 0x7fc0, seg.selector);
7469 put_smstate(u32, buf, 0x7f80, seg.base);
7470 put_smstate(u32, buf, 0x7f7c, seg.limit);
7471 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7473 kvm_x86_ops->get_gdt(vcpu, &dt);
7474 put_smstate(u32, buf, 0x7f74, dt.address);
7475 put_smstate(u32, buf, 0x7f70, dt.size);
7477 kvm_x86_ops->get_idt(vcpu, &dt);
7478 put_smstate(u32, buf, 0x7f58, dt.address);
7479 put_smstate(u32, buf, 0x7f54, dt.size);
7481 for (i = 0; i < 6; i++)
7482 enter_smm_save_seg_32(vcpu, buf, i);
7484 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7487 put_smstate(u32, buf, 0x7efc, 0x00020000);
7488 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7491 #ifdef CONFIG_X86_64
7492 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7495 struct kvm_segment seg;
7499 for (i = 0; i < 16; i++)
7500 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7502 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7503 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7505 kvm_get_dr(vcpu, 6, &val);
7506 put_smstate(u64, buf, 0x7f68, val);
7507 kvm_get_dr(vcpu, 7, &val);
7508 put_smstate(u64, buf, 0x7f60, val);
7510 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7511 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7512 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7514 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7517 put_smstate(u32, buf, 0x7efc, 0x00020064);
7519 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7521 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7522 put_smstate(u16, buf, 0x7e90, seg.selector);
7523 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7524 put_smstate(u32, buf, 0x7e94, seg.limit);
7525 put_smstate(u64, buf, 0x7e98, seg.base);
7527 kvm_x86_ops->get_idt(vcpu, &dt);
7528 put_smstate(u32, buf, 0x7e84, dt.size);
7529 put_smstate(u64, buf, 0x7e88, dt.address);
7531 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7532 put_smstate(u16, buf, 0x7e70, seg.selector);
7533 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7534 put_smstate(u32, buf, 0x7e74, seg.limit);
7535 put_smstate(u64, buf, 0x7e78, seg.base);
7537 kvm_x86_ops->get_gdt(vcpu, &dt);
7538 put_smstate(u32, buf, 0x7e64, dt.size);
7539 put_smstate(u64, buf, 0x7e68, dt.address);
7541 for (i = 0; i < 6; i++)
7542 enter_smm_save_seg_64(vcpu, buf, i);
7546 static void enter_smm(struct kvm_vcpu *vcpu)
7548 struct kvm_segment cs, ds;
7553 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7554 memset(buf, 0, 512);
7555 #ifdef CONFIG_X86_64
7556 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7557 enter_smm_save_state_64(vcpu, buf);
7560 enter_smm_save_state_32(vcpu, buf);
7563 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7564 * vCPU state (e.g. leave guest mode) after we've saved the state into
7565 * the SMM state-save area.
7567 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7569 vcpu->arch.hflags |= HF_SMM_MASK;
7570 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7572 if (kvm_x86_ops->get_nmi_mask(vcpu))
7573 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7575 kvm_x86_ops->set_nmi_mask(vcpu, true);
7577 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7578 kvm_rip_write(vcpu, 0x8000);
7580 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7581 kvm_x86_ops->set_cr0(vcpu, cr0);
7582 vcpu->arch.cr0 = cr0;
7584 kvm_x86_ops->set_cr4(vcpu, 0);
7586 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7587 dt.address = dt.size = 0;
7588 kvm_x86_ops->set_idt(vcpu, &dt);
7590 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7592 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7593 cs.base = vcpu->arch.smbase;
7598 cs.limit = ds.limit = 0xffffffff;
7599 cs.type = ds.type = 0x3;
7600 cs.dpl = ds.dpl = 0;
7605 cs.avl = ds.avl = 0;
7606 cs.present = ds.present = 1;
7607 cs.unusable = ds.unusable = 0;
7608 cs.padding = ds.padding = 0;
7610 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7611 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7612 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7613 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7614 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7615 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7617 #ifdef CONFIG_X86_64
7618 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7619 kvm_x86_ops->set_efer(vcpu, 0);
7622 kvm_update_cpuid(vcpu);
7623 kvm_mmu_reset_context(vcpu);
7626 static void process_smi(struct kvm_vcpu *vcpu)
7628 vcpu->arch.smi_pending = true;
7629 kvm_make_request(KVM_REQ_EVENT, vcpu);
7632 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7634 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7637 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7639 if (!kvm_apic_present(vcpu))
7642 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7644 if (irqchip_split(vcpu->kvm))
7645 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7647 if (vcpu->arch.apicv_active)
7648 kvm_x86_ops->sync_pir_to_irr(vcpu);
7649 if (ioapic_in_kernel(vcpu->kvm))
7650 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7653 if (is_guest_mode(vcpu))
7654 vcpu->arch.load_eoi_exitmap_pending = true;
7656 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7659 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7661 u64 eoi_exit_bitmap[4];
7663 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7666 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7667 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7668 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7671 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7672 unsigned long start, unsigned long end,
7675 unsigned long apic_address;
7678 * The physical address of apic access page is stored in the VMCS.
7679 * Update it when it becomes invalid.
7681 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7682 if (start <= apic_address && apic_address < end)
7683 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7688 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7690 struct page *page = NULL;
7692 if (!lapic_in_kernel(vcpu))
7695 if (!kvm_x86_ops->set_apic_access_page_addr)
7698 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7699 if (is_error_page(page))
7701 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7704 * Do not pin apic access page in memory, the MMU notifier
7705 * will call us again if it is migrated or swapped out.
7709 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7711 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7713 smp_send_reschedule(vcpu->cpu);
7715 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7718 * Returns 1 to let vcpu_run() continue the guest execution loop without
7719 * exiting to the userspace. Otherwise, the value will be returned to the
7722 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7726 dm_request_for_irq_injection(vcpu) &&
7727 kvm_cpu_accept_dm_intr(vcpu);
7729 bool req_immediate_exit = false;
7731 if (kvm_request_pending(vcpu)) {
7732 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7733 kvm_x86_ops->get_vmcs12_pages(vcpu);
7734 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7735 kvm_mmu_unload(vcpu);
7736 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7737 __kvm_migrate_timers(vcpu);
7738 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7739 kvm_gen_update_masterclock(vcpu->kvm);
7740 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7741 kvm_gen_kvmclock_update(vcpu);
7742 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7743 r = kvm_guest_time_update(vcpu);
7747 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7748 kvm_mmu_sync_roots(vcpu);
7749 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7750 kvm_mmu_load_cr3(vcpu);
7751 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7752 kvm_vcpu_flush_tlb(vcpu, true);
7753 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7754 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7758 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7759 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7760 vcpu->mmio_needed = 0;
7764 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7765 /* Page is swapped out. Do synthetic halt */
7766 vcpu->arch.apf.halted = true;
7770 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7771 record_steal_time(vcpu);
7772 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7774 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7776 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7777 kvm_pmu_handle_event(vcpu);
7778 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7779 kvm_pmu_deliver_pmi(vcpu);
7780 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7781 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7782 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7783 vcpu->arch.ioapic_handled_vectors)) {
7784 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7785 vcpu->run->eoi.vector =
7786 vcpu->arch.pending_ioapic_eoi;
7791 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7792 vcpu_scan_ioapic(vcpu);
7793 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7794 vcpu_load_eoi_exitmap(vcpu);
7795 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7796 kvm_vcpu_reload_apic_access_page(vcpu);
7797 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7798 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7799 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7803 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7804 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7805 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7809 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7810 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7811 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7817 * KVM_REQ_HV_STIMER has to be processed after
7818 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7819 * depend on the guest clock being up-to-date
7821 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7822 kvm_hv_process_stimers(vcpu);
7825 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7826 ++vcpu->stat.req_event;
7827 kvm_apic_accept_events(vcpu);
7828 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7833 if (inject_pending_event(vcpu, req_int_win) != 0)
7834 req_immediate_exit = true;
7836 /* Enable SMI/NMI/IRQ window open exits if needed.
7838 * SMIs have three cases:
7839 * 1) They can be nested, and then there is nothing to
7840 * do here because RSM will cause a vmexit anyway.
7841 * 2) There is an ISA-specific reason why SMI cannot be
7842 * injected, and the moment when this changes can be
7844 * 3) Or the SMI can be pending because
7845 * inject_pending_event has completed the injection
7846 * of an IRQ or NMI from the previous vmexit, and
7847 * then we request an immediate exit to inject the
7850 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7851 if (!kvm_x86_ops->enable_smi_window(vcpu))
7852 req_immediate_exit = true;
7853 if (vcpu->arch.nmi_pending)
7854 kvm_x86_ops->enable_nmi_window(vcpu);
7855 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7856 kvm_x86_ops->enable_irq_window(vcpu);
7857 WARN_ON(vcpu->arch.exception.pending);
7860 if (kvm_lapic_enabled(vcpu)) {
7861 update_cr8_intercept(vcpu);
7862 kvm_lapic_sync_to_vapic(vcpu);
7866 r = kvm_mmu_reload(vcpu);
7868 goto cancel_injection;
7873 kvm_x86_ops->prepare_guest_switch(vcpu);
7876 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7877 * IPI are then delayed after guest entry, which ensures that they
7878 * result in virtual interrupt delivery.
7880 local_irq_disable();
7881 vcpu->mode = IN_GUEST_MODE;
7883 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7886 * 1) We should set ->mode before checking ->requests. Please see
7887 * the comment in kvm_vcpu_exiting_guest_mode().
7889 * 2) For APICv, we should set ->mode before checking PID.ON. This
7890 * pairs with the memory barrier implicit in pi_test_and_set_on
7891 * (see vmx_deliver_posted_interrupt).
7893 * 3) This also orders the write to mode from any reads to the page
7894 * tables done while the VCPU is running. Please see the comment
7895 * in kvm_flush_remote_tlbs.
7897 smp_mb__after_srcu_read_unlock();
7900 * This handles the case where a posted interrupt was
7901 * notified with kvm_vcpu_kick.
7903 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7904 kvm_x86_ops->sync_pir_to_irr(vcpu);
7906 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7907 || need_resched() || signal_pending(current)) {
7908 vcpu->mode = OUTSIDE_GUEST_MODE;
7912 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7914 goto cancel_injection;
7917 if (req_immediate_exit) {
7918 kvm_make_request(KVM_REQ_EVENT, vcpu);
7919 kvm_x86_ops->request_immediate_exit(vcpu);
7922 trace_kvm_entry(vcpu->vcpu_id);
7923 if (lapic_timer_advance_ns)
7924 wait_lapic_expire(vcpu);
7925 guest_enter_irqoff();
7927 if (unlikely(vcpu->arch.switch_db_regs)) {
7929 set_debugreg(vcpu->arch.eff_db[0], 0);
7930 set_debugreg(vcpu->arch.eff_db[1], 1);
7931 set_debugreg(vcpu->arch.eff_db[2], 2);
7932 set_debugreg(vcpu->arch.eff_db[3], 3);
7933 set_debugreg(vcpu->arch.dr6, 6);
7934 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7937 kvm_x86_ops->run(vcpu);
7940 * Do this here before restoring debug registers on the host. And
7941 * since we do this before handling the vmexit, a DR access vmexit
7942 * can (a) read the correct value of the debug registers, (b) set
7943 * KVM_DEBUGREG_WONT_EXIT again.
7945 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7946 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7947 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7948 kvm_update_dr0123(vcpu);
7949 kvm_update_dr6(vcpu);
7950 kvm_update_dr7(vcpu);
7951 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7955 * If the guest has used debug registers, at least dr7
7956 * will be disabled while returning to the host.
7957 * If we don't have active breakpoints in the host, we don't
7958 * care about the messed up debug address registers. But if
7959 * we have some of them active, restore the old state.
7961 if (hw_breakpoint_active())
7962 hw_breakpoint_restore();
7964 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7966 vcpu->mode = OUTSIDE_GUEST_MODE;
7969 kvm_before_interrupt(vcpu);
7970 kvm_x86_ops->handle_external_intr(vcpu);
7971 kvm_after_interrupt(vcpu);
7975 guest_exit_irqoff();
7980 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7983 * Profile KVM exit RIPs:
7985 if (unlikely(prof_on == KVM_PROFILING)) {
7986 unsigned long rip = kvm_rip_read(vcpu);
7987 profile_hit(KVM_PROFILING, (void *)rip);
7990 if (unlikely(vcpu->arch.tsc_always_catchup))
7991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7993 if (vcpu->arch.apic_attention)
7994 kvm_lapic_sync_from_vapic(vcpu);
7996 vcpu->arch.gpa_available = false;
7997 r = kvm_x86_ops->handle_exit(vcpu);
8001 kvm_x86_ops->cancel_injection(vcpu);
8002 if (unlikely(vcpu->arch.apic_attention))
8003 kvm_lapic_sync_from_vapic(vcpu);
8008 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8010 if (!kvm_arch_vcpu_runnable(vcpu) &&
8011 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8012 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8013 kvm_vcpu_block(vcpu);
8014 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8016 if (kvm_x86_ops->post_block)
8017 kvm_x86_ops->post_block(vcpu);
8019 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8023 kvm_apic_accept_events(vcpu);
8024 switch(vcpu->arch.mp_state) {
8025 case KVM_MP_STATE_HALTED:
8026 vcpu->arch.pv.pv_unhalted = false;
8027 vcpu->arch.mp_state =
8028 KVM_MP_STATE_RUNNABLE;
8030 case KVM_MP_STATE_RUNNABLE:
8031 vcpu->arch.apf.halted = false;
8033 case KVM_MP_STATE_INIT_RECEIVED:
8042 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8044 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8045 kvm_x86_ops->check_nested_events(vcpu, false);
8047 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8048 !vcpu->arch.apf.halted);
8051 static int vcpu_run(struct kvm_vcpu *vcpu)
8054 struct kvm *kvm = vcpu->kvm;
8056 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8057 vcpu->arch.l1tf_flush_l1d = true;
8060 if (kvm_vcpu_running(vcpu)) {
8061 r = vcpu_enter_guest(vcpu);
8063 r = vcpu_block(kvm, vcpu);
8069 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8070 if (kvm_cpu_has_pending_timer(vcpu))
8071 kvm_inject_pending_timer_irqs(vcpu);
8073 if (dm_request_for_irq_injection(vcpu) &&
8074 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8076 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8077 ++vcpu->stat.request_irq_exits;
8081 kvm_check_async_pf_completion(vcpu);
8083 if (signal_pending(current)) {
8085 vcpu->run->exit_reason = KVM_EXIT_INTR;
8086 ++vcpu->stat.signal_exits;
8089 if (need_resched()) {
8090 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8092 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8096 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8101 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8104 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8105 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8106 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8107 if (r != EMULATE_DONE)
8112 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8114 BUG_ON(!vcpu->arch.pio.count);
8116 return complete_emulated_io(vcpu);
8120 * Implements the following, as a state machine:
8124 * for each mmio piece in the fragment
8132 * for each mmio piece in the fragment
8137 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8139 struct kvm_run *run = vcpu->run;
8140 struct kvm_mmio_fragment *frag;
8143 BUG_ON(!vcpu->mmio_needed);
8145 /* Complete previous fragment */
8146 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8147 len = min(8u, frag->len);
8148 if (!vcpu->mmio_is_write)
8149 memcpy(frag->data, run->mmio.data, len);
8151 if (frag->len <= 8) {
8152 /* Switch to the next fragment. */
8154 vcpu->mmio_cur_fragment++;
8156 /* Go forward to the next mmio piece. */
8162 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8163 vcpu->mmio_needed = 0;
8165 /* FIXME: return into emulator if single-stepping. */
8166 if (vcpu->mmio_is_write)
8168 vcpu->mmio_read_completed = 1;
8169 return complete_emulated_io(vcpu);
8172 run->exit_reason = KVM_EXIT_MMIO;
8173 run->mmio.phys_addr = frag->gpa;
8174 if (vcpu->mmio_is_write)
8175 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8176 run->mmio.len = min(8u, frag->len);
8177 run->mmio.is_write = vcpu->mmio_is_write;
8178 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8182 /* Swap (qemu) user FPU context for the guest FPU context. */
8183 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8186 copy_fpregs_to_fpstate(¤t->thread.fpu);
8187 /* PKRU is separately restored in kvm_x86_ops->run. */
8188 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8189 ~XFEATURE_MASK_PKRU);
8194 /* When vcpu_run ends, restore user space FPU context. */
8195 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8198 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8199 copy_kernel_to_fpregs(¤t->thread.fpu.state);
8201 ++vcpu->stat.fpu_reload;
8205 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8210 kvm_sigset_activate(vcpu);
8211 kvm_load_guest_fpu(vcpu);
8213 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8214 if (kvm_run->immediate_exit) {
8218 kvm_vcpu_block(vcpu);
8219 kvm_apic_accept_events(vcpu);
8220 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8222 if (signal_pending(current)) {
8224 vcpu->run->exit_reason = KVM_EXIT_INTR;
8225 ++vcpu->stat.signal_exits;
8230 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8235 if (vcpu->run->kvm_dirty_regs) {
8236 r = sync_regs(vcpu);
8241 /* re-sync apic's tpr */
8242 if (!lapic_in_kernel(vcpu)) {
8243 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8249 if (unlikely(vcpu->arch.complete_userspace_io)) {
8250 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8251 vcpu->arch.complete_userspace_io = NULL;
8256 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8258 if (kvm_run->immediate_exit)
8264 kvm_put_guest_fpu(vcpu);
8265 if (vcpu->run->kvm_valid_regs)
8267 post_kvm_run_save(vcpu);
8268 kvm_sigset_deactivate(vcpu);
8274 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8276 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8278 * We are here if userspace calls get_regs() in the middle of
8279 * instruction emulation. Registers state needs to be copied
8280 * back from emulation context to vcpu. Userspace shouldn't do
8281 * that usually, but some bad designed PV devices (vmware
8282 * backdoor interface) need this to work
8284 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8285 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8287 regs->rax = kvm_rax_read(vcpu);
8288 regs->rbx = kvm_rbx_read(vcpu);
8289 regs->rcx = kvm_rcx_read(vcpu);
8290 regs->rdx = kvm_rdx_read(vcpu);
8291 regs->rsi = kvm_rsi_read(vcpu);
8292 regs->rdi = kvm_rdi_read(vcpu);
8293 regs->rsp = kvm_rsp_read(vcpu);
8294 regs->rbp = kvm_rbp_read(vcpu);
8295 #ifdef CONFIG_X86_64
8296 regs->r8 = kvm_r8_read(vcpu);
8297 regs->r9 = kvm_r9_read(vcpu);
8298 regs->r10 = kvm_r10_read(vcpu);
8299 regs->r11 = kvm_r11_read(vcpu);
8300 regs->r12 = kvm_r12_read(vcpu);
8301 regs->r13 = kvm_r13_read(vcpu);
8302 regs->r14 = kvm_r14_read(vcpu);
8303 regs->r15 = kvm_r15_read(vcpu);
8306 regs->rip = kvm_rip_read(vcpu);
8307 regs->rflags = kvm_get_rflags(vcpu);
8310 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8313 __get_regs(vcpu, regs);
8318 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8320 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8321 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8323 kvm_rax_write(vcpu, regs->rax);
8324 kvm_rbx_write(vcpu, regs->rbx);
8325 kvm_rcx_write(vcpu, regs->rcx);
8326 kvm_rdx_write(vcpu, regs->rdx);
8327 kvm_rsi_write(vcpu, regs->rsi);
8328 kvm_rdi_write(vcpu, regs->rdi);
8329 kvm_rsp_write(vcpu, regs->rsp);
8330 kvm_rbp_write(vcpu, regs->rbp);
8331 #ifdef CONFIG_X86_64
8332 kvm_r8_write(vcpu, regs->r8);
8333 kvm_r9_write(vcpu, regs->r9);
8334 kvm_r10_write(vcpu, regs->r10);
8335 kvm_r11_write(vcpu, regs->r11);
8336 kvm_r12_write(vcpu, regs->r12);
8337 kvm_r13_write(vcpu, regs->r13);
8338 kvm_r14_write(vcpu, regs->r14);
8339 kvm_r15_write(vcpu, regs->r15);
8342 kvm_rip_write(vcpu, regs->rip);
8343 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8345 vcpu->arch.exception.pending = false;
8347 kvm_make_request(KVM_REQ_EVENT, vcpu);
8350 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8353 __set_regs(vcpu, regs);
8358 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8360 struct kvm_segment cs;
8362 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8366 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8368 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8372 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8373 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8374 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8375 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8376 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8377 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8379 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8380 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8382 kvm_x86_ops->get_idt(vcpu, &dt);
8383 sregs->idt.limit = dt.size;
8384 sregs->idt.base = dt.address;
8385 kvm_x86_ops->get_gdt(vcpu, &dt);
8386 sregs->gdt.limit = dt.size;
8387 sregs->gdt.base = dt.address;
8389 sregs->cr0 = kvm_read_cr0(vcpu);
8390 sregs->cr2 = vcpu->arch.cr2;
8391 sregs->cr3 = kvm_read_cr3(vcpu);
8392 sregs->cr4 = kvm_read_cr4(vcpu);
8393 sregs->cr8 = kvm_get_cr8(vcpu);
8394 sregs->efer = vcpu->arch.efer;
8395 sregs->apic_base = kvm_get_apic_base(vcpu);
8397 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8399 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8400 set_bit(vcpu->arch.interrupt.nr,
8401 (unsigned long *)sregs->interrupt_bitmap);
8404 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8405 struct kvm_sregs *sregs)
8408 __get_sregs(vcpu, sregs);
8413 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8414 struct kvm_mp_state *mp_state)
8418 kvm_apic_accept_events(vcpu);
8419 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8420 vcpu->arch.pv.pv_unhalted)
8421 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8423 mp_state->mp_state = vcpu->arch.mp_state;
8429 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8430 struct kvm_mp_state *mp_state)
8436 if (!lapic_in_kernel(vcpu) &&
8437 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8440 /* INITs are latched while in SMM */
8441 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8442 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8443 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8446 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8447 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8448 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8450 vcpu->arch.mp_state = mp_state->mp_state;
8451 kvm_make_request(KVM_REQ_EVENT, vcpu);
8459 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8460 int reason, bool has_error_code, u32 error_code)
8462 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8465 init_emulate_ctxt(vcpu);
8467 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8468 has_error_code, error_code);
8471 return EMULATE_FAIL;
8473 kvm_rip_write(vcpu, ctxt->eip);
8474 kvm_set_rflags(vcpu, ctxt->eflags);
8475 kvm_make_request(KVM_REQ_EVENT, vcpu);
8476 return EMULATE_DONE;
8478 EXPORT_SYMBOL_GPL(kvm_task_switch);
8480 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8482 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8483 (sregs->cr4 & X86_CR4_OSXSAVE))
8486 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8488 * When EFER.LME and CR0.PG are set, the processor is in
8489 * 64-bit mode (though maybe in a 32-bit code segment).
8490 * CR4.PAE and EFER.LMA must be set.
8492 if (!(sregs->cr4 & X86_CR4_PAE)
8493 || !(sregs->efer & EFER_LMA))
8497 * Not in 64-bit mode: EFER.LMA is clear and the code
8498 * segment cannot be 64-bit.
8500 if (sregs->efer & EFER_LMA || sregs->cs.l)
8507 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8509 struct msr_data apic_base_msr;
8510 int mmu_reset_needed = 0;
8511 int cpuid_update_needed = 0;
8512 int pending_vec, max_bits, idx;
8516 if (kvm_valid_sregs(vcpu, sregs))
8519 apic_base_msr.data = sregs->apic_base;
8520 apic_base_msr.host_initiated = true;
8521 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8524 dt.size = sregs->idt.limit;
8525 dt.address = sregs->idt.base;
8526 kvm_x86_ops->set_idt(vcpu, &dt);
8527 dt.size = sregs->gdt.limit;
8528 dt.address = sregs->gdt.base;
8529 kvm_x86_ops->set_gdt(vcpu, &dt);
8531 vcpu->arch.cr2 = sregs->cr2;
8532 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8533 vcpu->arch.cr3 = sregs->cr3;
8534 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8536 kvm_set_cr8(vcpu, sregs->cr8);
8538 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8539 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8541 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8542 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8543 vcpu->arch.cr0 = sregs->cr0;
8545 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8546 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8547 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8548 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8549 if (cpuid_update_needed)
8550 kvm_update_cpuid(vcpu);
8552 idx = srcu_read_lock(&vcpu->kvm->srcu);
8553 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
8554 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8555 mmu_reset_needed = 1;
8557 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8559 if (mmu_reset_needed)
8560 kvm_mmu_reset_context(vcpu);
8562 max_bits = KVM_NR_INTERRUPTS;
8563 pending_vec = find_first_bit(
8564 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8565 if (pending_vec < max_bits) {
8566 kvm_queue_interrupt(vcpu, pending_vec, false);
8567 pr_debug("Set back pending irq %d\n", pending_vec);
8570 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8571 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8572 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8573 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8574 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8575 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8577 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8578 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8580 update_cr8_intercept(vcpu);
8582 /* Older userspace won't unhalt the vcpu on reset. */
8583 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8584 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8586 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8588 kvm_make_request(KVM_REQ_EVENT, vcpu);
8595 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8596 struct kvm_sregs *sregs)
8601 ret = __set_sregs(vcpu, sregs);
8606 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8607 struct kvm_guest_debug *dbg)
8609 unsigned long rflags;
8614 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8616 if (vcpu->arch.exception.pending)
8618 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8619 kvm_queue_exception(vcpu, DB_VECTOR);
8621 kvm_queue_exception(vcpu, BP_VECTOR);
8625 * Read rflags as long as potentially injected trace flags are still
8628 rflags = kvm_get_rflags(vcpu);
8630 vcpu->guest_debug = dbg->control;
8631 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8632 vcpu->guest_debug = 0;
8634 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8635 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8636 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8637 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8639 for (i = 0; i < KVM_NR_DB_REGS; i++)
8640 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8642 kvm_update_dr7(vcpu);
8644 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8645 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8646 get_segment_base(vcpu, VCPU_SREG_CS);
8649 * Trigger an rflags update that will inject or remove the trace
8652 kvm_set_rflags(vcpu, rflags);
8654 kvm_x86_ops->update_bp_intercept(vcpu);
8664 * Translate a guest virtual address to a guest physical address.
8666 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8667 struct kvm_translation *tr)
8669 unsigned long vaddr = tr->linear_address;
8675 idx = srcu_read_lock(&vcpu->kvm->srcu);
8676 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8677 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8678 tr->physical_address = gpa;
8679 tr->valid = gpa != UNMAPPED_GVA;
8687 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8689 struct fxregs_state *fxsave;
8693 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8694 memcpy(fpu->fpr, fxsave->st_space, 128);
8695 fpu->fcw = fxsave->cwd;
8696 fpu->fsw = fxsave->swd;
8697 fpu->ftwx = fxsave->twd;
8698 fpu->last_opcode = fxsave->fop;
8699 fpu->last_ip = fxsave->rip;
8700 fpu->last_dp = fxsave->rdp;
8701 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8707 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8709 struct fxregs_state *fxsave;
8713 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8715 memcpy(fxsave->st_space, fpu->fpr, 128);
8716 fxsave->cwd = fpu->fcw;
8717 fxsave->swd = fpu->fsw;
8718 fxsave->twd = fpu->ftwx;
8719 fxsave->fop = fpu->last_opcode;
8720 fxsave->rip = fpu->last_ip;
8721 fxsave->rdp = fpu->last_dp;
8722 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8728 static void store_regs(struct kvm_vcpu *vcpu)
8730 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8732 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8733 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8735 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8736 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8738 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8739 kvm_vcpu_ioctl_x86_get_vcpu_events(
8740 vcpu, &vcpu->run->s.regs.events);
8743 static int sync_regs(struct kvm_vcpu *vcpu)
8745 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8748 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8749 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8750 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8752 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8753 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8755 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8757 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8758 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8759 vcpu, &vcpu->run->s.regs.events))
8761 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8767 static void fx_init(struct kvm_vcpu *vcpu)
8769 fpstate_init(&vcpu->arch.guest_fpu->state);
8770 if (boot_cpu_has(X86_FEATURE_XSAVES))
8771 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8772 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8775 * Ensure guest xcr0 is valid for loading
8777 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8779 vcpu->arch.cr0 |= X86_CR0_ET;
8782 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8784 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8786 kvmclock_reset(vcpu);
8788 kvm_x86_ops->vcpu_free(vcpu);
8789 free_cpumask_var(wbinvd_dirty_mask);
8792 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8795 struct kvm_vcpu *vcpu;
8797 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8798 printk_once(KERN_WARNING
8799 "kvm: SMP vm created on host with unstable TSC; "
8800 "guest TSC will not be reliable\n");
8802 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8807 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8809 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8810 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8811 kvm_vcpu_mtrr_init(vcpu);
8813 kvm_vcpu_reset(vcpu, false);
8814 kvm_init_mmu(vcpu, false);
8819 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8821 struct msr_data msr;
8822 struct kvm *kvm = vcpu->kvm;
8824 kvm_hv_vcpu_postcreate(vcpu);
8826 if (mutex_lock_killable(&vcpu->mutex))
8830 msr.index = MSR_IA32_TSC;
8831 msr.host_initiated = true;
8832 kvm_write_tsc(vcpu, &msr);
8834 mutex_unlock(&vcpu->mutex);
8836 if (!kvmclock_periodic_sync)
8839 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8840 KVMCLOCK_SYNC_PERIOD);
8843 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8845 vcpu->arch.apf.msr_val = 0;
8848 kvm_mmu_unload(vcpu);
8851 kvm_x86_ops->vcpu_free(vcpu);
8854 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8856 kvm_lapic_reset(vcpu, init_event);
8858 vcpu->arch.hflags = 0;
8860 vcpu->arch.smi_pending = 0;
8861 vcpu->arch.smi_count = 0;
8862 atomic_set(&vcpu->arch.nmi_queued, 0);
8863 vcpu->arch.nmi_pending = 0;
8864 vcpu->arch.nmi_injected = false;
8865 kvm_clear_interrupt_queue(vcpu);
8866 kvm_clear_exception_queue(vcpu);
8867 vcpu->arch.exception.pending = false;
8869 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8870 kvm_update_dr0123(vcpu);
8871 vcpu->arch.dr6 = DR6_INIT;
8872 kvm_update_dr6(vcpu);
8873 vcpu->arch.dr7 = DR7_FIXED_1;
8874 kvm_update_dr7(vcpu);
8878 kvm_make_request(KVM_REQ_EVENT, vcpu);
8879 vcpu->arch.apf.msr_val = 0;
8880 vcpu->arch.st.msr_val = 0;
8882 kvmclock_reset(vcpu);
8884 kvm_clear_async_pf_completion_queue(vcpu);
8885 kvm_async_pf_hash_reset(vcpu);
8886 vcpu->arch.apf.halted = false;
8888 if (kvm_mpx_supported()) {
8889 void *mpx_state_buffer;
8892 * To avoid have the INIT path from kvm_apic_has_events() that be
8893 * called with loaded FPU and does not let userspace fix the state.
8896 kvm_put_guest_fpu(vcpu);
8897 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8898 XFEATURE_MASK_BNDREGS);
8899 if (mpx_state_buffer)
8900 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8901 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8902 XFEATURE_MASK_BNDCSR);
8903 if (mpx_state_buffer)
8904 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8906 kvm_load_guest_fpu(vcpu);
8910 kvm_pmu_reset(vcpu);
8911 vcpu->arch.smbase = 0x30000;
8913 vcpu->arch.msr_misc_features_enables = 0;
8915 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8918 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8919 vcpu->arch.regs_avail = ~0;
8920 vcpu->arch.regs_dirty = ~0;
8922 vcpu->arch.ia32_xss = 0;
8924 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8927 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8929 struct kvm_segment cs;
8931 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8932 cs.selector = vector << 8;
8933 cs.base = vector << 12;
8934 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8935 kvm_rip_write(vcpu, 0);
8938 int kvm_arch_hardware_enable(void)
8941 struct kvm_vcpu *vcpu;
8946 bool stable, backwards_tsc = false;
8948 kvm_shared_msr_cpu_online();
8949 ret = kvm_x86_ops->hardware_enable();
8953 local_tsc = rdtsc();
8954 stable = !kvm_check_tsc_unstable();
8955 list_for_each_entry(kvm, &vm_list, vm_list) {
8956 kvm_for_each_vcpu(i, vcpu, kvm) {
8957 if (!stable && vcpu->cpu == smp_processor_id())
8958 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8959 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8960 backwards_tsc = true;
8961 if (vcpu->arch.last_host_tsc > max_tsc)
8962 max_tsc = vcpu->arch.last_host_tsc;
8968 * Sometimes, even reliable TSCs go backwards. This happens on
8969 * platforms that reset TSC during suspend or hibernate actions, but
8970 * maintain synchronization. We must compensate. Fortunately, we can
8971 * detect that condition here, which happens early in CPU bringup,
8972 * before any KVM threads can be running. Unfortunately, we can't
8973 * bring the TSCs fully up to date with real time, as we aren't yet far
8974 * enough into CPU bringup that we know how much real time has actually
8975 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8976 * variables that haven't been updated yet.
8978 * So we simply find the maximum observed TSC above, then record the
8979 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8980 * the adjustment will be applied. Note that we accumulate
8981 * adjustments, in case multiple suspend cycles happen before some VCPU
8982 * gets a chance to run again. In the event that no KVM threads get a
8983 * chance to run, we will miss the entire elapsed period, as we'll have
8984 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8985 * loose cycle time. This isn't too big a deal, since the loss will be
8986 * uniform across all VCPUs (not to mention the scenario is extremely
8987 * unlikely). It is possible that a second hibernate recovery happens
8988 * much faster than a first, causing the observed TSC here to be
8989 * smaller; this would require additional padding adjustment, which is
8990 * why we set last_host_tsc to the local tsc observed here.
8992 * N.B. - this code below runs only on platforms with reliable TSC,
8993 * as that is the only way backwards_tsc is set above. Also note
8994 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8995 * have the same delta_cyc adjustment applied if backwards_tsc
8996 * is detected. Note further, this adjustment is only done once,
8997 * as we reset last_host_tsc on all VCPUs to stop this from being
8998 * called multiple times (one for each physical CPU bringup).
9000 * Platforms with unreliable TSCs don't have to deal with this, they
9001 * will be compensated by the logic in vcpu_load, which sets the TSC to
9002 * catchup mode. This will catchup all VCPUs to real time, but cannot
9003 * guarantee that they stay in perfect synchronization.
9005 if (backwards_tsc) {
9006 u64 delta_cyc = max_tsc - local_tsc;
9007 list_for_each_entry(kvm, &vm_list, vm_list) {
9008 kvm->arch.backwards_tsc_observed = true;
9009 kvm_for_each_vcpu(i, vcpu, kvm) {
9010 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9011 vcpu->arch.last_host_tsc = local_tsc;
9012 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9016 * We have to disable TSC offset matching.. if you were
9017 * booting a VM while issuing an S4 host suspend....
9018 * you may have some problem. Solving this issue is
9019 * left as an exercise to the reader.
9021 kvm->arch.last_tsc_nsec = 0;
9022 kvm->arch.last_tsc_write = 0;
9029 void kvm_arch_hardware_disable(void)
9031 kvm_x86_ops->hardware_disable();
9032 drop_user_return_notifiers();
9035 int kvm_arch_hardware_setup(void)
9039 r = kvm_x86_ops->hardware_setup();
9043 if (kvm_has_tsc_control) {
9045 * Make sure the user can only configure tsc_khz values that
9046 * fit into a signed integer.
9047 * A min value is not calculated because it will always
9048 * be 1 on all machines.
9050 u64 max = min(0x7fffffffULL,
9051 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9052 kvm_max_guest_tsc_khz = max;
9054 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9057 kvm_init_msr_list();
9061 void kvm_arch_hardware_unsetup(void)
9063 kvm_x86_ops->hardware_unsetup();
9066 void kvm_arch_check_processor_compat(void *rtn)
9068 kvm_x86_ops->check_processor_compatibility(rtn);
9071 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9073 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9075 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9077 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9079 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9082 struct static_key kvm_no_apic_vcpu __read_mostly;
9083 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9085 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9090 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9091 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9092 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9094 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9096 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9101 vcpu->arch.pio_data = page_address(page);
9103 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9105 r = kvm_mmu_create(vcpu);
9107 goto fail_free_pio_data;
9109 if (irqchip_in_kernel(vcpu->kvm)) {
9110 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9111 r = kvm_create_lapic(vcpu);
9113 goto fail_mmu_destroy;
9115 static_key_slow_inc(&kvm_no_apic_vcpu);
9117 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9118 GFP_KERNEL_ACCOUNT);
9119 if (!vcpu->arch.mce_banks) {
9121 goto fail_free_lapic;
9123 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9125 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9126 GFP_KERNEL_ACCOUNT)) {
9128 goto fail_free_mce_banks;
9133 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9135 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9137 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9139 kvm_async_pf_hash_reset(vcpu);
9142 vcpu->arch.pending_external_vector = -1;
9143 vcpu->arch.preempted_in_kernel = false;
9145 kvm_hv_vcpu_init(vcpu);
9149 fail_free_mce_banks:
9150 kfree(vcpu->arch.mce_banks);
9152 kvm_free_lapic(vcpu);
9154 kvm_mmu_destroy(vcpu);
9156 free_page((unsigned long)vcpu->arch.pio_data);
9161 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9165 kvm_hv_vcpu_uninit(vcpu);
9166 kvm_pmu_destroy(vcpu);
9167 kfree(vcpu->arch.mce_banks);
9168 kvm_free_lapic(vcpu);
9169 idx = srcu_read_lock(&vcpu->kvm->srcu);
9170 kvm_mmu_destroy(vcpu);
9171 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9172 free_page((unsigned long)vcpu->arch.pio_data);
9173 if (!lapic_in_kernel(vcpu))
9174 static_key_slow_dec(&kvm_no_apic_vcpu);
9177 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9179 vcpu->arch.l1tf_flush_l1d = true;
9180 kvm_x86_ops->sched_in(vcpu, cpu);
9183 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9188 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9189 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9190 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9191 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9193 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9194 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9195 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9196 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9197 &kvm->arch.irq_sources_bitmap);
9199 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9200 mutex_init(&kvm->arch.apic_map_lock);
9201 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9203 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
9204 pvclock_update_vm_gtod_copy(kvm);
9206 kvm->arch.guest_can_read_msr_platform_info = true;
9208 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9209 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9211 kvm_hv_init_vm(kvm);
9212 kvm_page_track_init(kvm);
9213 kvm_mmu_init_vm(kvm);
9215 if (kvm_x86_ops->vm_init)
9216 return kvm_x86_ops->vm_init(kvm);
9221 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9224 kvm_mmu_unload(vcpu);
9228 static void kvm_free_vcpus(struct kvm *kvm)
9231 struct kvm_vcpu *vcpu;
9234 * Unpin any mmu pages first.
9236 kvm_for_each_vcpu(i, vcpu, kvm) {
9237 kvm_clear_async_pf_completion_queue(vcpu);
9238 kvm_unload_vcpu_mmu(vcpu);
9240 kvm_for_each_vcpu(i, vcpu, kvm)
9241 kvm_arch_vcpu_free(vcpu);
9243 mutex_lock(&kvm->lock);
9244 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9245 kvm->vcpus[i] = NULL;
9247 atomic_set(&kvm->online_vcpus, 0);
9248 mutex_unlock(&kvm->lock);
9251 void kvm_arch_sync_events(struct kvm *kvm)
9253 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9254 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9258 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9262 struct kvm_memslots *slots = kvm_memslots(kvm);
9263 struct kvm_memory_slot *slot, old;
9265 /* Called with kvm->slots_lock held. */
9266 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9269 slot = id_to_memslot(slots, id);
9275 * MAP_SHARED to prevent internal slot pages from being moved
9278 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9279 MAP_SHARED | MAP_ANONYMOUS, 0);
9280 if (IS_ERR((void *)hva))
9281 return PTR_ERR((void *)hva);
9290 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9291 struct kvm_userspace_memory_region m;
9293 m.slot = id | (i << 16);
9295 m.guest_phys_addr = gpa;
9296 m.userspace_addr = hva;
9297 m.memory_size = size;
9298 r = __kvm_set_memory_region(kvm, &m);
9304 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9308 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9310 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9314 mutex_lock(&kvm->slots_lock);
9315 r = __x86_set_memory_region(kvm, id, gpa, size);
9316 mutex_unlock(&kvm->slots_lock);
9320 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9322 void kvm_arch_destroy_vm(struct kvm *kvm)
9324 if (current->mm == kvm->mm) {
9326 * Free memory regions allocated on behalf of userspace,
9327 * unless the the memory map has changed due to process exit
9330 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9331 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9332 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9334 if (kvm_x86_ops->vm_destroy)
9335 kvm_x86_ops->vm_destroy(kvm);
9336 kvm_pic_destroy(kvm);
9337 kvm_ioapic_destroy(kvm);
9338 kvm_free_vcpus(kvm);
9339 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9340 kvm_mmu_uninit_vm(kvm);
9341 kvm_page_track_cleanup(kvm);
9342 kvm_hv_destroy_vm(kvm);
9345 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9346 struct kvm_memory_slot *dont)
9350 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9351 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9352 kvfree(free->arch.rmap[i]);
9353 free->arch.rmap[i] = NULL;
9358 if (!dont || free->arch.lpage_info[i - 1] !=
9359 dont->arch.lpage_info[i - 1]) {
9360 kvfree(free->arch.lpage_info[i - 1]);
9361 free->arch.lpage_info[i - 1] = NULL;
9365 kvm_page_track_free_memslot(free, dont);
9368 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9369 unsigned long npages)
9373 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9374 struct kvm_lpage_info *linfo;
9379 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9380 slot->base_gfn, level) + 1;
9382 slot->arch.rmap[i] =
9383 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9384 GFP_KERNEL_ACCOUNT);
9385 if (!slot->arch.rmap[i])
9390 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9394 slot->arch.lpage_info[i - 1] = linfo;
9396 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9397 linfo[0].disallow_lpage = 1;
9398 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9399 linfo[lpages - 1].disallow_lpage = 1;
9400 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9402 * If the gfn and userspace address are not aligned wrt each
9403 * other, or if explicitly asked to, disable large page
9404 * support for this slot
9406 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9407 !kvm_largepages_enabled()) {
9410 for (j = 0; j < lpages; ++j)
9411 linfo[j].disallow_lpage = 1;
9415 if (kvm_page_track_create_memslot(slot, npages))
9421 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9422 kvfree(slot->arch.rmap[i]);
9423 slot->arch.rmap[i] = NULL;
9427 kvfree(slot->arch.lpage_info[i - 1]);
9428 slot->arch.lpage_info[i - 1] = NULL;
9433 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9436 * memslots->generation has been incremented.
9437 * mmio generation may have reached its maximum value.
9439 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9442 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9443 struct kvm_memory_slot *memslot,
9444 const struct kvm_userspace_memory_region *mem,
9445 enum kvm_mr_change change)
9450 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9451 struct kvm_memory_slot *new)
9453 /* Still write protect RO slot */
9454 if (new->flags & KVM_MEM_READONLY) {
9455 kvm_mmu_slot_remove_write_access(kvm, new);
9460 * Call kvm_x86_ops dirty logging hooks when they are valid.
9462 * kvm_x86_ops->slot_disable_log_dirty is called when:
9464 * - KVM_MR_CREATE with dirty logging is disabled
9465 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9467 * The reason is, in case of PML, we need to set D-bit for any slots
9468 * with dirty logging disabled in order to eliminate unnecessary GPA
9469 * logging in PML buffer (and potential PML buffer full VMEXT). This
9470 * guarantees leaving PML enabled during guest's lifetime won't have
9471 * any additional overhead from PML when guest is running with dirty
9472 * logging disabled for memory slots.
9474 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9475 * to dirty logging mode.
9477 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9479 * In case of write protect:
9481 * Write protect all pages for dirty logging.
9483 * All the sptes including the large sptes which point to this
9484 * slot are set to readonly. We can not create any new large
9485 * spte on this slot until the end of the logging.
9487 * See the comments in fast_page_fault().
9489 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9490 if (kvm_x86_ops->slot_enable_log_dirty)
9491 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9493 kvm_mmu_slot_remove_write_access(kvm, new);
9495 if (kvm_x86_ops->slot_disable_log_dirty)
9496 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9500 void kvm_arch_commit_memory_region(struct kvm *kvm,
9501 const struct kvm_userspace_memory_region *mem,
9502 const struct kvm_memory_slot *old,
9503 const struct kvm_memory_slot *new,
9504 enum kvm_mr_change change)
9506 if (!kvm->arch.n_requested_mmu_pages)
9507 kvm_mmu_change_mmu_pages(kvm,
9508 kvm_mmu_calculate_default_mmu_pages(kvm));
9511 * Dirty logging tracks sptes in 4k granularity, meaning that large
9512 * sptes have to be split. If live migration is successful, the guest
9513 * in the source machine will be destroyed and large sptes will be
9514 * created in the destination. However, if the guest continues to run
9515 * in the source machine (for example if live migration fails), small
9516 * sptes will remain around and cause bad performance.
9518 * Scan sptes if dirty logging has been stopped, dropping those
9519 * which can be collapsed into a single large-page spte. Later
9520 * page faults will create the large-page sptes.
9522 if ((change != KVM_MR_DELETE) &&
9523 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9524 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9525 kvm_mmu_zap_collapsible_sptes(kvm, new);
9528 * Set up write protection and/or dirty logging for the new slot.
9530 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9531 * been zapped so no dirty logging staff is needed for old slot. For
9532 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9533 * new and it's also covered when dealing with the new slot.
9535 * FIXME: const-ify all uses of struct kvm_memory_slot.
9537 if (change != KVM_MR_DELETE)
9538 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9541 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9543 kvm_mmu_zap_all(kvm);
9546 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9547 struct kvm_memory_slot *slot)
9549 kvm_page_track_flush_slot(kvm, slot);
9552 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9554 return (is_guest_mode(vcpu) &&
9555 kvm_x86_ops->guest_apic_has_interrupt &&
9556 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9559 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9561 if (!list_empty_careful(&vcpu->async_pf.done))
9564 if (kvm_apic_has_events(vcpu))
9567 if (vcpu->arch.pv.pv_unhalted)
9570 if (vcpu->arch.exception.pending)
9573 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9574 (vcpu->arch.nmi_pending &&
9575 kvm_x86_ops->nmi_allowed(vcpu)))
9578 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9579 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9582 if (kvm_arch_interrupt_allowed(vcpu) &&
9583 (kvm_cpu_has_interrupt(vcpu) ||
9584 kvm_guest_apic_has_interrupt(vcpu)))
9587 if (kvm_hv_has_stimer_pending(vcpu))
9593 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9595 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9598 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9600 return vcpu->arch.preempted_in_kernel;
9603 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9605 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9608 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9610 return kvm_x86_ops->interrupt_allowed(vcpu);
9613 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9615 if (is_64_bit_mode(vcpu))
9616 return kvm_rip_read(vcpu);
9617 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9618 kvm_rip_read(vcpu));
9620 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9622 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9624 return kvm_get_linear_rip(vcpu) == linear_rip;
9626 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9628 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9630 unsigned long rflags;
9632 rflags = kvm_x86_ops->get_rflags(vcpu);
9633 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9634 rflags &= ~X86_EFLAGS_TF;
9637 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9639 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9641 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9642 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9643 rflags |= X86_EFLAGS_TF;
9644 kvm_x86_ops->set_rflags(vcpu, rflags);
9647 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9649 __kvm_set_rflags(vcpu, rflags);
9650 kvm_make_request(KVM_REQ_EVENT, vcpu);
9652 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9654 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9658 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9662 r = kvm_mmu_reload(vcpu);
9666 if (!vcpu->arch.mmu->direct_map &&
9667 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9670 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9673 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9675 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9678 static inline u32 kvm_async_pf_next_probe(u32 key)
9680 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9683 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9685 u32 key = kvm_async_pf_hash_fn(gfn);
9687 while (vcpu->arch.apf.gfns[key] != ~0)
9688 key = kvm_async_pf_next_probe(key);
9690 vcpu->arch.apf.gfns[key] = gfn;
9693 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9696 u32 key = kvm_async_pf_hash_fn(gfn);
9698 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9699 (vcpu->arch.apf.gfns[key] != gfn &&
9700 vcpu->arch.apf.gfns[key] != ~0); i++)
9701 key = kvm_async_pf_next_probe(key);
9706 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9708 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9711 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9715 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9717 vcpu->arch.apf.gfns[i] = ~0;
9719 j = kvm_async_pf_next_probe(j);
9720 if (vcpu->arch.apf.gfns[j] == ~0)
9722 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9724 * k lies cyclically in ]i,j]
9726 * |....j i.k.| or |.k..j i...|
9728 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9729 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9734 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9737 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9741 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9744 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9748 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9749 struct kvm_async_pf *work)
9751 struct x86_exception fault;
9753 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9754 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9756 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9757 (vcpu->arch.apf.send_user_only &&
9758 kvm_x86_ops->get_cpl(vcpu) == 0))
9759 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9760 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9761 fault.vector = PF_VECTOR;
9762 fault.error_code_valid = true;
9763 fault.error_code = 0;
9764 fault.nested_page_fault = false;
9765 fault.address = work->arch.token;
9766 fault.async_page_fault = true;
9767 kvm_inject_page_fault(vcpu, &fault);
9771 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9772 struct kvm_async_pf *work)
9774 struct x86_exception fault;
9777 if (work->wakeup_all)
9778 work->arch.token = ~0; /* broadcast wakeup */
9780 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9781 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9783 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9784 !apf_get_user(vcpu, &val)) {
9785 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9786 vcpu->arch.exception.pending &&
9787 vcpu->arch.exception.nr == PF_VECTOR &&
9788 !apf_put_user(vcpu, 0)) {
9789 vcpu->arch.exception.injected = false;
9790 vcpu->arch.exception.pending = false;
9791 vcpu->arch.exception.nr = 0;
9792 vcpu->arch.exception.has_error_code = false;
9793 vcpu->arch.exception.error_code = 0;
9794 vcpu->arch.exception.has_payload = false;
9795 vcpu->arch.exception.payload = 0;
9796 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9797 fault.vector = PF_VECTOR;
9798 fault.error_code_valid = true;
9799 fault.error_code = 0;
9800 fault.nested_page_fault = false;
9801 fault.address = work->arch.token;
9802 fault.async_page_fault = true;
9803 kvm_inject_page_fault(vcpu, &fault);
9806 vcpu->arch.apf.halted = false;
9807 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9810 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9812 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9815 return kvm_can_do_async_pf(vcpu);
9818 void kvm_arch_start_assignment(struct kvm *kvm)
9820 atomic_inc(&kvm->arch.assigned_device_count);
9822 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9824 void kvm_arch_end_assignment(struct kvm *kvm)
9826 atomic_dec(&kvm->arch.assigned_device_count);
9828 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9830 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9832 return atomic_read(&kvm->arch.assigned_device_count);
9834 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9836 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9838 atomic_inc(&kvm->arch.noncoherent_dma_count);
9840 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9842 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9844 atomic_dec(&kvm->arch.noncoherent_dma_count);
9846 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9848 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9850 return atomic_read(&kvm->arch.noncoherent_dma_count);
9852 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9854 bool kvm_arch_has_irq_bypass(void)
9856 return kvm_x86_ops->update_pi_irte != NULL;
9859 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9860 struct irq_bypass_producer *prod)
9862 struct kvm_kernel_irqfd *irqfd =
9863 container_of(cons, struct kvm_kernel_irqfd, consumer);
9865 irqfd->producer = prod;
9867 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9868 prod->irq, irqfd->gsi, 1);
9871 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9872 struct irq_bypass_producer *prod)
9875 struct kvm_kernel_irqfd *irqfd =
9876 container_of(cons, struct kvm_kernel_irqfd, consumer);
9878 WARN_ON(irqfd->producer != prod);
9879 irqfd->producer = NULL;
9882 * When producer of consumer is unregistered, we change back to
9883 * remapped mode, so we can re-use the current implementation
9884 * when the irq is masked/disabled or the consumer side (KVM
9885 * int this case doesn't want to receive the interrupts.
9887 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9889 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9890 " fails: %d\n", irqfd->consumer.token, ret);
9893 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9894 uint32_t guest_irq, bool set)
9896 if (!kvm_x86_ops->update_pi_irte)
9899 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9902 bool kvm_vector_hashing_enabled(void)
9904 return vector_hashing;
9906 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9908 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9909 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9910 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9911 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9912 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9913 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9914 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9915 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9916 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9917 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9918 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9919 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9920 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9921 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9922 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9923 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9924 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9925 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9926 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);