1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef ARCH_X86_KVM_X86_H
3 #define ARCH_X86_KVM_X86_H
5 #include <asm/processor.h>
7 #include <linux/kvm_host.h>
8 #include <asm/pvclock.h>
9 #include "kvm_cache_regs.h"
11 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
13 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
15 vcpu->arch.exception.injected = false;
18 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
21 vcpu->arch.interrupt.pending = true;
22 vcpu->arch.interrupt.soft = soft;
23 vcpu->arch.interrupt.nr = vector;
26 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
28 vcpu->arch.interrupt.pending = false;
31 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
33 return vcpu->arch.exception.injected || vcpu->arch.interrupt.pending ||
34 vcpu->arch.nmi_injected;
37 static inline bool kvm_exception_is_soft(unsigned int nr)
39 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
42 static inline bool is_protmode(struct kvm_vcpu *vcpu)
44 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
47 static inline int is_long_mode(struct kvm_vcpu *vcpu)
50 return vcpu->arch.efer & EFER_LMA;
56 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
60 if (!is_long_mode(vcpu))
62 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
66 static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
69 return (vcpu->arch.efer & EFER_LMA) &&
70 kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
76 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
78 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
81 static inline int is_pae(struct kvm_vcpu *vcpu)
83 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
86 static inline int is_pse(struct kvm_vcpu *vcpu)
88 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
91 static inline int is_paging(struct kvm_vcpu *vcpu)
93 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
96 static inline u32 bit(int bitno)
98 return 1 << (bitno & 31);
101 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
103 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
106 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
108 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
111 static inline u64 get_canonical(u64 la, u8 vaddr_bits)
113 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
116 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
119 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
125 static inline bool emul_is_noncanonical_address(u64 la,
126 struct x86_emulate_ctxt *ctxt)
129 return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
135 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
136 gva_t gva, gfn_t gfn, unsigned access)
139 * If this is a shadow nested page table, the "GVA" is
142 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
143 vcpu->arch.access = access;
144 vcpu->arch.mmio_gfn = gfn;
145 vcpu->arch.mmio_gen = kvm_memslots(vcpu->kvm)->generation;
148 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
150 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
154 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
155 * clear all mmio cache info.
157 #define MMIO_GVA_ANY (~(gva_t)0)
159 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
161 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
164 vcpu->arch.mmio_gva = 0;
167 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
169 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
170 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
176 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
178 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
179 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
185 static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu,
188 unsigned long val = kvm_register_read(vcpu, reg);
190 return is_64_bit_mode(vcpu) ? val : (u32)val;
193 static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
197 if (!is_64_bit_mode(vcpu))
199 return kvm_register_write(vcpu, reg, val);
202 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
204 return !(kvm->arch.disabled_quirks & quirk);
207 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu);
208 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu);
209 void kvm_set_pending_timer(struct kvm_vcpu *vcpu);
210 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
212 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
213 u64 get_kvmclock_ns(struct kvm *kvm);
215 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
216 gva_t addr, void *val, unsigned int bytes,
217 struct x86_exception *exception);
219 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
220 gva_t addr, void *val, unsigned int bytes,
221 struct x86_exception *exception);
223 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
224 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
225 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
226 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
227 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
228 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
230 bool kvm_vector_hashing_enabled(void);
232 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
233 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
234 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
235 | XFEATURE_MASK_PKRU)
236 extern u64 host_xcr0;
238 extern u64 kvm_supported_xcr0(void);
240 extern unsigned int min_timer_period_us;
242 extern unsigned int lapic_timer_advance_ns;
244 extern struct static_key kvm_no_apic_vcpu;
246 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
248 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
249 vcpu->arch.virtual_tsc_shift);
252 /* Same "calling convention" as do_div:
253 * - divide (n << 32) by base
257 #define do_shl32_div32(n, base) \
260 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
261 : "rm" (base), "0" (0), "1" ((u32) n)); \
266 static inline bool kvm_mwait_in_guest(void)
268 unsigned int eax, ebx, ecx, edx;
270 if (!cpu_has(&boot_cpu_data, X86_FEATURE_MWAIT))
273 switch (boot_cpu_data.x86_vendor) {
275 /* All AMD CPUs have a working MWAIT implementation */
277 case X86_VENDOR_INTEL:
278 /* Handle Intel below */
285 * Intel CPUs without CPUID5_ECX_INTERRUPT_BREAK are problematic as
286 * they would allow guest to stop the CPU completely by disabling
287 * interrupts then invoking MWAIT.
289 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
292 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
294 if (!(ecx & CPUID5_ECX_INTERRUPT_BREAK))