1 #include <linux/init.h>
4 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/export.h>
9 #include <linux/debugfs.h>
11 #include <asm/tlbflush.h>
12 #include <asm/mmu_context.h>
13 #include <asm/nospec-branch.h>
14 #include <asm/cache.h>
16 #include <asm/uv/uv.h>
19 * TLB flushing, formerly SMP-only
22 * These mean you can really definitely utterly forget about
23 * writing to user space from interrupts. (Its not allowed anyway).
25 * Optimizations Manfred Spraul <manfred@colorfullife.com>
27 * More scalable flush, from Andi Kleen
29 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
33 * We get here when we do something requiring a TLB invalidation
34 * but could not go invalidate all of the contexts. We do the
35 * necessary invalidation by clearing out the 'ctx_id' which
36 * forces a TLB flush when the context is loaded.
38 void clear_asid_other(void)
43 * This is only expected to be set if we have disabled
44 * kernel _PAGE_GLOBAL pages.
46 if (!static_cpu_has(X86_FEATURE_PTI)) {
51 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
52 /* Do not need to flush the current asid */
53 if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid))
56 * Make sure the next time we go to switch to
57 * this asid, we do a flush:
59 this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0);
61 this_cpu_write(cpu_tlbstate.invalidate_other, false);
64 atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
67 static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
68 u16 *new_asid, bool *need_flush)
72 if (!static_cpu_has(X86_FEATURE_PCID)) {
78 if (this_cpu_read(cpu_tlbstate.invalidate_other))
81 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
82 if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
87 *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
93 * We don't currently own an ASID slot on this CPU.
96 *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;
97 if (*new_asid >= TLB_NR_DYN_ASIDS) {
99 this_cpu_write(cpu_tlbstate.next_asid, 1);
104 static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
106 unsigned long new_mm_cr3;
109 invalidate_user_asid(new_asid);
110 new_mm_cr3 = build_cr3(pgdir, new_asid);
112 new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
116 * Caution: many callers of this function expect
117 * that load_cr3() is serializing and orders TLB
118 * fills with respect to the mm_cpumask writes.
120 write_cr3(new_mm_cr3);
123 void leave_mm(int cpu)
125 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
128 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
129 * If so, our callers still expect us to flush the TLB, but there
130 * aren't any user TLB entries in init_mm to worry about.
132 * This needs to happen before any other sanity checks due to
133 * intel_idle's shenanigans.
135 if (loaded_mm == &init_mm)
138 /* Warn if we're not lazy. */
139 WARN_ON(!this_cpu_read(cpu_tlbstate.is_lazy));
141 switch_mm(NULL, &init_mm, NULL);
143 EXPORT_SYMBOL_GPL(leave_mm);
145 void switch_mm(struct mm_struct *prev, struct mm_struct *next,
146 struct task_struct *tsk)
150 local_irq_save(flags);
151 switch_mm_irqs_off(prev, next, tsk);
152 local_irq_restore(flags);
155 static void sync_current_stack_to_mm(struct mm_struct *mm)
157 unsigned long sp = current_stack_pointer;
158 pgd_t *pgd = pgd_offset(mm, sp);
160 if (CONFIG_PGTABLE_LEVELS > 4) {
161 if (unlikely(pgd_none(*pgd))) {
162 pgd_t *pgd_ref = pgd_offset_k(sp);
164 set_pgd(pgd, *pgd_ref);
168 * "pgd" is faked. The top level entries are "p4d"s, so sync
169 * the p4d. This compiles to approximately the same code as
172 p4d_t *p4d = p4d_offset(pgd, sp);
174 if (unlikely(p4d_none(*p4d))) {
175 pgd_t *pgd_ref = pgd_offset_k(sp);
176 p4d_t *p4d_ref = p4d_offset(pgd_ref, sp);
178 set_p4d(p4d, *p4d_ref);
183 void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
184 struct task_struct *tsk)
186 struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm);
187 u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
188 unsigned cpu = smp_processor_id();
192 * NB: The scheduler will call us with prev == next when switching
193 * from lazy TLB mode to normal mode if active_mm isn't changing.
194 * When this happens, we don't assume that CR3 (and hence
195 * cpu_tlbstate.loaded_mm) matches next.
197 * NB: leave_mm() calls us with prev == NULL and tsk == NULL.
200 /* We don't want flush_tlb_func_* to run concurrently with us. */
201 if (IS_ENABLED(CONFIG_PROVE_LOCKING))
202 WARN_ON_ONCE(!irqs_disabled());
205 * Verify that CR3 is what we think it is. This will catch
206 * hypothetical buggy code that directly switches to swapper_pg_dir
207 * without going through leave_mm() / switch_mm_irqs_off() or that
208 * does something like write_cr3(read_cr3_pa()).
210 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
213 #ifdef CONFIG_DEBUG_VM
214 if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {
216 * If we were to BUG here, we'd be very likely to kill
217 * the system so hard that we don't see the call trace.
218 * Try to recover instead by ignoring the error and doing
219 * a global flush to minimize the chance of corruption.
221 * (This is far from being a fully correct recovery.
222 * Architecturally, the CPU could prefetch something
223 * back into an incorrect ASID slot and leave it there
224 * to cause trouble down the road. It's better than
230 this_cpu_write(cpu_tlbstate.is_lazy, false);
232 if (real_prev == next) {
233 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
234 next->context.ctx_id);
237 * We don't currently support having a real mm loaded without
238 * our cpu set in mm_cpumask(). We have all the bookkeeping
239 * in place to figure out whether we would need to flush
240 * if our cpu were cleared in mm_cpumask(), but we don't
243 if (WARN_ON_ONCE(real_prev != &init_mm &&
244 !cpumask_test_cpu(cpu, mm_cpumask(next))))
245 cpumask_set_cpu(cpu, mm_cpumask(next));
251 u64 last_ctx_id = this_cpu_read(cpu_tlbstate.last_ctx_id);
254 * Avoid user/user BTB poisoning by flushing the branch
255 * predictor when switching between processes. This stops
256 * one process from doing Spectre-v2 attacks on another.
258 * As an optimization, flush indirect branches only when
259 * switching into processes that disable dumping. This
260 * protects high value processes like gpg, without having
261 * too high performance overhead. IBPB is *expensive*!
263 * This will not flush branches when switching into kernel
264 * threads. It will also not flush if we switch to idle
265 * thread and back to the same process. It will flush if we
266 * switch to a different non-dumpable process.
268 if (tsk && tsk->mm &&
269 tsk->mm->context.ctx_id != last_ctx_id &&
270 get_dumpable(tsk->mm) != SUID_DUMP_USER)
271 indirect_branch_prediction_barrier();
273 if (IS_ENABLED(CONFIG_VMAP_STACK)) {
275 * If our current stack is in vmalloc space and isn't
276 * mapped in the new pgd, we'll double-fault. Forcibly
279 sync_current_stack_to_mm(next);
282 /* Stop remote flushes for the previous mm */
283 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu, mm_cpumask(real_prev)) &&
284 real_prev != &init_mm);
285 cpumask_clear_cpu(cpu, mm_cpumask(real_prev));
288 * Start remote flushes and then read tlb_gen.
290 cpumask_set_cpu(cpu, mm_cpumask(next));
291 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
293 choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
296 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
297 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
298 load_new_mm_cr3(next->pgd, new_asid, true);
301 * NB: This gets called via leave_mm() in the idle path
302 * where RCU functions differently. Tracing normally
303 * uses RCU, so we need to use the _rcuidle variant.
305 * (There is no good reason for this. The idle code should
306 * be rearranged to call this before rcu_idle_enter().)
308 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
310 /* The new ASID is already up to date. */
311 load_new_mm_cr3(next->pgd, new_asid, false);
313 /* See above wrt _rcuidle. */
314 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0);
318 * Record last user mm's context id, so we can avoid
319 * flushing branch buffer with IBPB if we switch back
322 if (next != &init_mm)
323 this_cpu_write(cpu_tlbstate.last_ctx_id, next->context.ctx_id);
325 this_cpu_write(cpu_tlbstate.loaded_mm, next);
326 this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
330 switch_ldt(real_prev, next);
334 * Please ignore the name of this function. It should be called
335 * switch_to_kernel_thread().
337 * enter_lazy_tlb() is a hint from the scheduler that we are entering a
338 * kernel thread or other context without an mm. Acceptable implementations
339 * include doing nothing whatsoever, switching to init_mm, or various clever
340 * lazy tricks to try to minimize TLB flushes.
342 * The scheduler reserves the right to call enter_lazy_tlb() several times
343 * in a row. It will notify us that we're going back to a real mm by
344 * calling switch_mm_irqs_off().
346 void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
348 if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
351 if (tlb_defer_switch_to_init_mm()) {
353 * There's a significant optimization that may be possible
354 * here. We have accurate enough TLB flush tracking that we
355 * don't need to maintain coherence of TLB per se when we're
356 * lazy. We do, however, need to maintain coherence of
357 * paging-structure caches. We could, in principle, leave our
358 * old mm loaded and only switch to init_mm when
359 * tlb_remove_page() happens.
361 this_cpu_write(cpu_tlbstate.is_lazy, true);
363 switch_mm(NULL, &init_mm, NULL);
368 * Call this when reinitializing a CPU. It fixes the following potential
371 * - The ASID changed from what cpu_tlbstate thinks it is (most likely
372 * because the CPU was taken down and came back up with CR3's PCID
373 * bits clear. CPU hotplug can do this.
375 * - The TLB contains junk in slots corresponding to inactive ASIDs.
377 * - The CPU went so far out to lunch that it may have missed a TLB
380 void initialize_tlbstate_and_flush(void)
383 struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
384 u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
385 unsigned long cr3 = __read_cr3();
387 /* Assert that CR3 already references the right mm. */
388 WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
391 * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
392 * doesn't work like other CR4 bits because it can only be set from
395 WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
396 !(cr4_read_shadow() & X86_CR4_PCIDE));
398 /* Force ASID 0 and force a TLB flush. */
399 write_cr3(build_cr3(mm->pgd, 0));
401 /* Reinitialize tlbstate. */
402 this_cpu_write(cpu_tlbstate.last_ctx_id, mm->context.ctx_id);
403 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
404 this_cpu_write(cpu_tlbstate.next_asid, 1);
405 this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
406 this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
408 for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
409 this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
413 * flush_tlb_func_common()'s memory ordering requirement is that any
414 * TLB fills that happen after we flush the TLB are ordered after we
415 * read active_mm's tlb_gen. We don't need any explicit barriers
416 * because all x86 flush operations are serializing and the
417 * atomic64_read operation won't be reordered by the compiler.
419 static void flush_tlb_func_common(const struct flush_tlb_info *f,
420 bool local, enum tlb_flush_reason reason)
423 * We have three different tlb_gen values in here. They are:
425 * - mm_tlb_gen: the latest generation.
426 * - local_tlb_gen: the generation that this CPU has already caught
428 * - f->new_tlb_gen: the generation that the requester of the flush
429 * wants us to catch up to.
431 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
432 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
433 u64 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
434 u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
436 /* This code cannot presently handle being reentered. */
437 VM_WARN_ON(!irqs_disabled());
439 if (unlikely(loaded_mm == &init_mm))
442 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=
443 loaded_mm->context.ctx_id);
445 if (this_cpu_read(cpu_tlbstate.is_lazy)) {
447 * We're in lazy mode. We need to at least flush our
448 * paging-structure cache to avoid speculatively reading
449 * garbage into our TLB. Since switching to init_mm is barely
450 * slower than a minimal flush, just switch to init_mm.
452 switch_mm_irqs_off(NULL, &init_mm, NULL);
456 if (unlikely(local_tlb_gen == mm_tlb_gen)) {
458 * There's nothing to do: we're already up to date. This can
459 * happen if two concurrent flushes happen -- the first flush to
460 * be handled can catch us all the way up, leaving no work for
463 trace_tlb_flush(reason, 0);
467 WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen);
468 WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);
471 * If we get to this point, we know that our TLB is out of date.
472 * This does not strictly imply that we need to flush (it's
473 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
474 * going to need to flush in the very near future, so we might
475 * as well get it over with.
477 * The only question is whether to do a full or partial flush.
479 * We do a partial flush if requested and two extra conditions
482 * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that
483 * we've always done all needed flushes to catch up to
484 * local_tlb_gen. If, for example, local_tlb_gen == 2 and
485 * f->new_tlb_gen == 3, then we know that the flush needed to bring
486 * us up to date for tlb_gen 3 is the partial flush we're
489 * As an example of why this check is needed, suppose that there
490 * are two concurrent flushes. The first is a full flush that
491 * changes context.tlb_gen from 1 to 2. The second is a partial
492 * flush that changes context.tlb_gen from 2 to 3. If they get
493 * processed on this CPU in reverse order, we'll see
494 * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
495 * If we were to use __flush_tlb_single() and set local_tlb_gen to
496 * 3, we'd be break the invariant: we'd update local_tlb_gen above
497 * 1 without the full flush that's needed for tlb_gen 2.
499 * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimiation.
500 * Partial TLB flushes are not all that much cheaper than full TLB
501 * flushes, so it seems unlikely that it would be a performance win
502 * to do a partial flush if that won't bring our TLB fully up to
503 * date. By doing a full flush instead, we can increase
504 * local_tlb_gen all the way to mm_tlb_gen and we can probably
505 * avoid another flush in the very near future.
507 if (f->end != TLB_FLUSH_ALL &&
508 f->new_tlb_gen == local_tlb_gen + 1 &&
509 f->new_tlb_gen == mm_tlb_gen) {
512 unsigned long nr_pages = (f->end - f->start) >> PAGE_SHIFT;
515 while (addr < f->end) {
516 __flush_tlb_single(addr);
520 count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_pages);
521 trace_tlb_flush(reason, nr_pages);
526 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
527 trace_tlb_flush(reason, TLB_FLUSH_ALL);
530 /* Both paths above update our state to mm_tlb_gen. */
531 this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen);
534 static void flush_tlb_func_local(void *info, enum tlb_flush_reason reason)
536 const struct flush_tlb_info *f = info;
538 flush_tlb_func_common(f, true, reason);
541 static void flush_tlb_func_remote(void *info)
543 const struct flush_tlb_info *f = info;
545 inc_irq_stat(irq_tlb_count);
547 if (f->mm && f->mm != this_cpu_read(cpu_tlbstate.loaded_mm))
550 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
551 flush_tlb_func_common(f, false, TLB_REMOTE_SHOOTDOWN);
554 void native_flush_tlb_others(const struct cpumask *cpumask,
555 const struct flush_tlb_info *info)
557 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
558 if (info->end == TLB_FLUSH_ALL)
559 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
561 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
562 (info->end - info->start) >> PAGE_SHIFT);
564 if (is_uv_system()) {
566 * This whole special case is confused. UV has a "Broadcast
567 * Assist Unit", which seems to be a fancy way to send IPIs.
568 * Back when x86 used an explicit TLB flush IPI, UV was
569 * optimized to use its own mechanism. These days, x86 uses
570 * smp_call_function_many(), but UV still uses a manual IPI,
571 * and that IPI's action is out of date -- it does a manual
572 * flush instead of calling flush_tlb_func_remote(). This
573 * means that the percpu tlb_gen variables won't be updated
574 * and we'll do pointless flushes on future context switches.
576 * Rather than hooking native_flush_tlb_others() here, I think
577 * that UV should be updated so that smp_call_function_many(),
578 * etc, are optimal on UV.
582 cpu = smp_processor_id();
583 cpumask = uv_flush_tlb_others(cpumask, info);
585 smp_call_function_many(cpumask, flush_tlb_func_remote,
589 smp_call_function_many(cpumask, flush_tlb_func_remote,
594 * See Documentation/x86/tlb.txt for details. We choose 33
595 * because it is large enough to cover the vast majority (at
596 * least 95%) of allocations, and is small enough that we are
597 * confident it will not cause too much overhead. Each single
598 * flush is about 100 ns, so this caps the maximum overhead at
601 * This is in units of pages.
603 static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
605 void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
606 unsigned long end, unsigned long vmflag)
610 struct flush_tlb_info info = {
616 /* This is also a barrier that synchronizes with switch_mm(). */
617 info.new_tlb_gen = inc_mm_tlb_gen(mm);
619 /* Should we flush just the requested range? */
620 if ((end != TLB_FLUSH_ALL) &&
621 !(vmflag & VM_HUGETLB) &&
622 ((end - start) >> PAGE_SHIFT) <= tlb_single_page_flush_ceiling) {
627 info.end = TLB_FLUSH_ALL;
630 if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) {
631 VM_WARN_ON(irqs_disabled());
633 flush_tlb_func_local(&info, TLB_LOCAL_MM_SHOOTDOWN);
637 if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids)
638 flush_tlb_others(mm_cpumask(mm), &info);
644 static void do_flush_tlb_all(void *info)
646 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
650 void flush_tlb_all(void)
652 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
653 on_each_cpu(do_flush_tlb_all, NULL, 1);
656 static void do_kernel_range_flush(void *info)
658 struct flush_tlb_info *f = info;
661 /* flush range by one by one 'invlpg' */
662 for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
663 __flush_tlb_one(addr);
666 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
669 /* Balance as user space task's flush, a bit conservative */
670 if (end == TLB_FLUSH_ALL ||
671 (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
672 on_each_cpu(do_flush_tlb_all, NULL, 1);
674 struct flush_tlb_info info;
677 on_each_cpu(do_kernel_range_flush, &info, 1);
681 void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
683 struct flush_tlb_info info = {
686 .end = TLB_FLUSH_ALL,
691 if (cpumask_test_cpu(cpu, &batch->cpumask)) {
692 VM_WARN_ON(irqs_disabled());
694 flush_tlb_func_local(&info, TLB_LOCAL_SHOOTDOWN);
698 if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids)
699 flush_tlb_others(&batch->cpumask, &info);
701 cpumask_clear(&batch->cpumask);
706 static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
707 size_t count, loff_t *ppos)
712 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
713 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
716 static ssize_t tlbflush_write_file(struct file *file,
717 const char __user *user_buf, size_t count, loff_t *ppos)
723 len = min(count, sizeof(buf) - 1);
724 if (copy_from_user(buf, user_buf, len))
728 if (kstrtoint(buf, 0, &ceiling))
734 tlb_single_page_flush_ceiling = ceiling;
738 static const struct file_operations fops_tlbflush = {
739 .read = tlbflush_read_file,
740 .write = tlbflush_write_file,
741 .llseek = default_llseek,
744 static int __init create_tlb_single_page_flush_ceiling(void)
746 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
747 arch_debugfs_dir, NULL, &fops_tlbflush);
750 late_initcall(create_tlb_single_page_flush_ceiling);