arch/x86/mm/tlb.c

   1 #include <linux/init.h>
   2
   3 #include <linux/mm.h>
   4 #include <linux/spinlock.h>
   5 #include <linux/smp.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/export.h>
   8 #include <linux/cpu.h>
   9
  10 #include <asm/tlbflush.h>
  11 #include <asm/mmu_context.h>
  12 #include <asm/cache.h>
  13 #include <asm/apic.h>
  14 #include <asm/uv/uv.h>
  15 #include <linux/debugfs.h>
  16
  17 /*
  18  *      Smarter SMP flushing macros.
  19  *              c/o Linus Torvalds.
  20  *
  21  *      These mean you can really definitely utterly forget about
  22  *      writing to user space from interrupts. (Its not allowed anyway).
  23  *
  24  *      Optimizations Manfred Spraul <manfred@colorfullife.com>
  25  *
  26  *      More scalable flush, from Andi Kleen
  27  *
  28  *      Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
  29  */
  30
  31 #ifdef CONFIG_SMP
  32
  33 struct flush_tlb_info {
  34         struct mm_struct *flush_mm;
  35         unsigned long flush_start;
  36         unsigned long flush_end;
  37 };
  38
  39 /*
  40  * We cannot call mmdrop() because we are in interrupt context,
  41  * instead update mm->cpu_vm_mask.
  42  */
  43 void leave_mm(int cpu)
  44 {
  45         struct mm_struct *active_mm = this_cpu_read(cpu_tlbstate.active_mm);
  46         if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
  47                 BUG();
  48         if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {
  49                 cpumask_clear_cpu(cpu, mm_cpumask(active_mm));
  50                 load_cr3(swapper_pg_dir);
  51                 /*
  52                  * This gets called in the idle path where RCU
  53                  * functions differently.  Tracing normally
  54                  * uses RCU, so we have to call the tracepoint
  55                  * specially here.
  56                  */
  57                 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
  58         }
  59 }
  60 EXPORT_SYMBOL_GPL(leave_mm);
  61
  62 #endif /* CONFIG_SMP */
  63
  64 void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  65                struct task_struct *tsk)
  66 {
  67         unsigned long flags;
  68
  69         local_irq_save(flags);
  70         switch_mm_irqs_off(prev, next, tsk);
  71         local_irq_restore(flags);
  72 }
  73
  74 void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
  75                         struct task_struct *tsk)
  76 {
  77         unsigned cpu = smp_processor_id();
  78
  79         if (likely(prev != next)) {
  80                 if (IS_ENABLED(CONFIG_VMAP_STACK)) {
  81                         /*
  82                          * If our current stack is in vmalloc space and isn't
  83                          * mapped in the new pgd, we'll double-fault.  Forcibly
  84                          * map it.
  85                          */
  86                         unsigned int stack_pgd_index = pgd_index(current_stack_pointer());
  87
  88                         pgd_t *pgd = next->pgd + stack_pgd_index;
  89
  90                         if (unlikely(pgd_none(*pgd)))
  91                                 set_pgd(pgd, init_mm.pgd[stack_pgd_index]);
  92                 }
  93
  94 #ifdef CONFIG_SMP
  95                 this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
  96                 this_cpu_write(cpu_tlbstate.active_mm, next);
  97 #endif
  98
  99                 cpumask_set_cpu(cpu, mm_cpumask(next));
 100
 101                 /*
 102                  * Re-load page tables.
 103                  *
 104                  * This logic has an ordering constraint:
 105                  *
 106                  *  CPU 0: Write to a PTE for 'next'
 107                  *  CPU 0: load bit 1 in mm_cpumask.  if nonzero, send IPI.
 108                  *  CPU 1: set bit 1 in next's mm_cpumask
 109                  *  CPU 1: load from the PTE that CPU 0 writes (implicit)
 110                  *
 111                  * We need to prevent an outcome in which CPU 1 observes
 112                  * the new PTE value and CPU 0 observes bit 1 clear in
 113                  * mm_cpumask.  (If that occurs, then the IPI will never
 114                  * be sent, and CPU 0's TLB will contain a stale entry.)
 115                  *
 116                  * The bad outcome can occur if either CPU's load is
 117                  * reordered before that CPU's store, so both CPUs must
 118                  * execute full barriers to prevent this from happening.
 119                  *
 120                  * Thus, switch_mm needs a full barrier between the
 121                  * store to mm_cpumask and any operation that could load
 122                  * from next->pgd.  TLB fills are special and can happen
 123                  * due to instruction fetches or for no reason at all,
 124                  * and neither LOCK nor MFENCE orders them.
 125                  * Fortunately, load_cr3() is serializing and gives the
 126                  * ordering guarantee we need.
 127                  *
 128                  */
 129                 load_cr3(next->pgd);
 130
 131                 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
 132
 133                 /* Stop flush ipis for the previous mm */
 134                 cpumask_clear_cpu(cpu, mm_cpumask(prev));
 135
 136                 /* Load per-mm CR4 state */
 137                 load_mm_cr4(next);
 138
 139 #ifdef CONFIG_MODIFY_LDT_SYSCALL
 140                 /*
 141                  * Load the LDT, if the LDT is different.
 142                  *
 143                  * It's possible that prev->context.ldt doesn't match
 144                  * the LDT register.  This can happen if leave_mm(prev)
 145                  * was called and then modify_ldt changed
 146                  * prev->context.ldt but suppressed an IPI to this CPU.
 147                  * In this case, prev->context.ldt != NULL, because we
 148                  * never set context.ldt to NULL while the mm still
 149                  * exists.  That means that next->context.ldt !=
 150                  * prev->context.ldt, because mms never share an LDT.
 151                  */
 152                 if (unlikely(prev->context.ldt != next->context.ldt))
 153                         load_mm_ldt(next);
 154 #endif
 155         }
 156 #ifdef CONFIG_SMP
 157           else {
 158                 this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
 159                 BUG_ON(this_cpu_read(cpu_tlbstate.active_mm) != next);
 160
 161                 if (!cpumask_test_cpu(cpu, mm_cpumask(next))) {
 162                         /*
 163                          * On established mms, the mm_cpumask is only changed
 164                          * from irq context, from ptep_clear_flush() while in
 165                          * lazy tlb mode, and here. Irqs are blocked during
 166                          * schedule, protecting us from simultaneous changes.
 167                          */
 168                         cpumask_set_cpu(cpu, mm_cpumask(next));
 169
 170                         /*
 171                          * We were in lazy tlb mode and leave_mm disabled
 172                          * tlb flush IPI delivery. We must reload CR3
 173                          * to make sure to use no freed page tables.
 174                          *
 175                          * As above, load_cr3() is serializing and orders TLB
 176                          * fills with respect to the mm_cpumask write.
 177                          */
 178                         load_cr3(next->pgd);
 179                         trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
 180                         load_mm_cr4(next);
 181                         load_mm_ldt(next);
 182                 }
 183         }
 184 #endif
 185 }
 186
 187 #ifdef CONFIG_SMP
 188
 189 /*
 190  * The flush IPI assumes that a thread switch happens in this order:
 191  * [cpu0: the cpu that switches]
 192  * 1) switch_mm() either 1a) or 1b)
 193  * 1a) thread switch to a different mm
 194  * 1a1) set cpu_tlbstate to TLBSTATE_OK
 195  *      Now the tlb flush NMI handler flush_tlb_func won't call leave_mm
 196  *      if cpu0 was in lazy tlb mode.
 197  * 1a2) update cpu active_mm
 198  *      Now cpu0 accepts tlb flushes for the new mm.
 199  * 1a3) cpu_set(cpu, new_mm->cpu_vm_mask);
 200  *      Now the other cpus will send tlb flush ipis.
 201  * 1a4) change cr3.
 202  * 1a5) cpu_clear(cpu, old_mm->cpu_vm_mask);
 203  *      Stop ipi delivery for the old mm. This is not synchronized with
 204  *      the other cpus, but flush_tlb_func ignore flush ipis for the wrong
 205  *      mm, and in the worst case we perform a superfluous tlb flush.
 206  * 1b) thread switch without mm change
 207  *      cpu active_mm is correct, cpu0 already handles flush ipis.
 208  * 1b1) set cpu_tlbstate to TLBSTATE_OK
 209  * 1b2) test_and_set the cpu bit in cpu_vm_mask.
 210  *      Atomically set the bit [other cpus will start sending flush ipis],
 211  *      and test the bit.
 212  * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
 213  * 2) switch %%esp, ie current
 214  *
 215  * The interrupt must handle 2 special cases:
 216  * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
 217  * - the cpu performs speculative tlb reads, i.e. even if the cpu only
 218  *   runs in kernel space, the cpu could load tlb entries for user space
 219  *   pages.
 220  *
 221  * The good news is that cpu_tlbstate is local to each cpu, no
 222  * write/read ordering problems.
 223  */
 224
 225 /*
 226  * TLB flush funcation:
 227  * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
 228  * 2) Leave the mm if we are in the lazy tlb mode.
 229  */
 230 static void flush_tlb_func(void *info)
 231 {
 232         struct flush_tlb_info *f = info;
 233
 234         inc_irq_stat(irq_tlb_count);
 235
 236         if (f->flush_mm && f->flush_mm != this_cpu_read(cpu_tlbstate.active_mm))
 237                 return;
 238
 239         count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
 240         if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
 241                 if (f->flush_end == TLB_FLUSH_ALL) {
 242                         local_flush_tlb();
 243                         trace_tlb_flush(TLB_REMOTE_SHOOTDOWN, TLB_FLUSH_ALL);
 244                 } else {
 245                         unsigned long addr;
 246                         unsigned long nr_pages =
 247                                 (f->flush_end - f->flush_start) / PAGE_SIZE;
 248                         addr = f->flush_start;
 249                         while (addr < f->flush_end) {
 250                                 __flush_tlb_single(addr);
 251                                 addr += PAGE_SIZE;
 252                         }
 253                         trace_tlb_flush(TLB_REMOTE_SHOOTDOWN, nr_pages);
 254                 }
 255         } else
 256                 leave_mm(smp_processor_id());
 257
 258 }
 259
 260 void native_flush_tlb_others(const struct cpumask *cpumask,
 261                                  struct mm_struct *mm, unsigned long start,
 262                                  unsigned long end)
 263 {
 264         struct flush_tlb_info info;
 265
 266         info.flush_mm = mm;
 267         info.flush_start = start;
 268         info.flush_end = end;
 269
 270         count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
 271         if (end == TLB_FLUSH_ALL)
 272                 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
 273         else
 274                 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
 275                                 (end - start) >> PAGE_SHIFT);
 276
 277         if (is_uv_system()) {
 278                 unsigned int cpu;
 279
 280                 cpu = smp_processor_id();
 281                 cpumask = uv_flush_tlb_others(cpumask, mm, start, end, cpu);
 282                 if (cpumask)
 283                         smp_call_function_many(cpumask, flush_tlb_func,
 284                                                                 &info, 1);
 285                 return;
 286         }
 287         smp_call_function_many(cpumask, flush_tlb_func, &info, 1);
 288 }
 289
 290 /*
 291  * See Documentation/x86/tlb.txt for details.  We choose 33
 292  * because it is large enough to cover the vast majority (at
 293  * least 95%) of allocations, and is small enough that we are
 294  * confident it will not cause too much overhead.  Each single
 295  * flush is about 100 ns, so this caps the maximum overhead at
 296  * _about_ 3,000 ns.
 297  *
 298  * This is in units of pages.
 299  */
 300 static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
 301
 302 void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
 303                                 unsigned long end, unsigned long vmflag)
 304 {
 305         unsigned long addr;
 306         /* do a global flush by default */
 307         unsigned long base_pages_to_flush = TLB_FLUSH_ALL;
 308
 309         preempt_disable();
 310
 311         if ((end != TLB_FLUSH_ALL) && !(vmflag & VM_HUGETLB))
 312                 base_pages_to_flush = (end - start) >> PAGE_SHIFT;
 313         if (base_pages_to_flush > tlb_single_page_flush_ceiling)
 314                 base_pages_to_flush = TLB_FLUSH_ALL;
 315
 316         if (current->active_mm != mm) {
 317                 /* Synchronize with switch_mm. */
 318                 smp_mb();
 319
 320                 goto out;
 321         }
 322
 323         if (!current->mm) {
 324                 leave_mm(smp_processor_id());
 325
 326                 /* Synchronize with switch_mm. */
 327                 smp_mb();
 328
 329                 goto out;
 330         }
 331
 332         /*
 333          * Both branches below are implicit full barriers (MOV to CR or
 334          * INVLPG) that synchronize with switch_mm.
 335          */
 336         if (base_pages_to_flush == TLB_FLUSH_ALL) {
 337                 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
 338                 local_flush_tlb();
 339         } else {
 340                 /* flush range by one by one 'invlpg' */
 341                 for (addr = start; addr < end;  addr += PAGE_SIZE) {
 342                         count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
 343                         __flush_tlb_single(addr);
 344                 }
 345         }
 346         trace_tlb_flush(TLB_LOCAL_MM_SHOOTDOWN, base_pages_to_flush);
 347 out:
 348         if (base_pages_to_flush == TLB_FLUSH_ALL) {
 349                 start = 0UL;
 350                 end = TLB_FLUSH_ALL;
 351         }
 352         if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
 353                 flush_tlb_others(mm_cpumask(mm), mm, start, end);
 354         preempt_enable();
 355 }
 356
 357 void flush_tlb_page(struct vm_area_struct *vma, unsigned long start)
 358 {
 359         struct mm_struct *mm = vma->vm_mm;
 360
 361         preempt_disable();
 362
 363         if (current->active_mm == mm) {
 364                 if (current->mm) {
 365                         /*
 366                          * Implicit full barrier (INVLPG) that synchronizes
 367                          * with switch_mm.
 368                          */
 369                         __flush_tlb_one(start);
 370                 } else {
 371                         leave_mm(smp_processor_id());
 372
 373                         /* Synchronize with switch_mm. */
 374                         smp_mb();
 375                 }
 376         }
 377
 378         if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
 379                 flush_tlb_others(mm_cpumask(mm), mm, start, start + PAGE_SIZE);
 380
 381         preempt_enable();
 382 }
 383
 384 static void do_flush_tlb_all(void *info)
 385 {
 386         count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
 387         __flush_tlb_all();
 388         if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
 389                 leave_mm(smp_processor_id());
 390 }
 391
 392 void flush_tlb_all(void)
 393 {
 394         count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
 395         on_each_cpu(do_flush_tlb_all, NULL, 1);
 396 }
 397
 398 static void do_kernel_range_flush(void *info)
 399 {
 400         struct flush_tlb_info *f = info;
 401         unsigned long addr;
 402
 403         /* flush range by one by one 'invlpg' */
 404         for (addr = f->flush_start; addr < f->flush_end; addr += PAGE_SIZE)
 405                 __flush_tlb_single(addr);
 406 }
 407
 408 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 409 {
 410
 411         /* Balance as user space task's flush, a bit conservative */
 412         if (end == TLB_FLUSH_ALL ||
 413             (end - start) > tlb_single_page_flush_ceiling * PAGE_SIZE) {
 414                 on_each_cpu(do_flush_tlb_all, NULL, 1);
 415         } else {
 416                 struct flush_tlb_info info;
 417                 info.flush_start = start;
 418                 info.flush_end = end;
 419                 on_each_cpu(do_kernel_range_flush, &info, 1);
 420         }
 421 }
 422
 423 static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
 424                              size_t count, loff_t *ppos)
 425 {
 426         char buf[32];
 427         unsigned int len;
 428
 429         len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
 430         return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 431 }
 432
 433 static ssize_t tlbflush_write_file(struct file *file,
 434                  const char __user *user_buf, size_t count, loff_t *ppos)
 435 {
 436         char buf[32];
 437         ssize_t len;
 438         int ceiling;
 439
 440         len = min(count, sizeof(buf) - 1);
 441         if (copy_from_user(buf, user_buf, len))
 442                 return -EFAULT;
 443
 444         buf[len] = '\0';
 445         if (kstrtoint(buf, 0, &ceiling))
 446                 return -EINVAL;
 447
 448         if (ceiling < 0)
 449                 return -EINVAL;
 450
 451         tlb_single_page_flush_ceiling = ceiling;
 452         return count;
 453 }
 454
 455 static const struct file_operations fops_tlbflush = {
 456         .read = tlbflush_read_file,
 457         .write = tlbflush_write_file,
 458         .llseek = default_llseek,
 459 };
 460
 461 static int __init create_tlb_single_page_flush_ceiling(void)
 462 {
 463         debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
 464                             arch_debugfs_dir, NULL, &fops_tlbflush);
 465         return 0;
 466 }
 467 late_initcall(create_tlb_single_page_flush_ceiling);
 468
 469 #endif /* CONFIG_SMP */