1 // SPDX-License-Identifier: GPL-2.0
3 * Just-In-Time compiler for eBPF filters on IA32 (32bit x86)
5 * Author: Wang YanQing (udknight@gmail.com)
6 * The code based on code and ideas from:
7 * Eric Dumazet (eric.dumazet@gmail.com)
9 * Shubham Bansal <illusionist.neo@gmail.com>
12 #include <linux/netdevice.h>
13 #include <linux/filter.h>
14 #include <linux/if_vlan.h>
15 #include <asm/cacheflush.h>
16 #include <asm/set_memory.h>
17 #include <asm/nospec-branch.h>
18 #include <linux/bpf.h>
21 * eBPF prog stack layout:
24 * original ESP => +-----+
25 * | | callee saved registers
27 * | ... | eBPF JIT scratch space
28 * BPF_FP,IA32_EBP => +-----+
29 * | ... | eBPF prog stack
31 * |RSVD | JIT scratchpad
32 * current ESP => +-----+
34 * | ... | Function call stack
39 * The callee saved registers:
42 * original ESP => +------------------+ \
44 * current EBP => +------------------+ } callee saved registers
46 * +------------------+ /
50 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
63 #define EMIT(bytes, len) \
64 do { prog = emit_code(prog, bytes, len); cnt += len; } while (0)
66 #define EMIT1(b1) EMIT(b1, 1)
67 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
68 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
69 #define EMIT4(b1, b2, b3, b4) \
70 EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
72 #define EMIT1_off32(b1, off) \
73 do { EMIT1(b1); EMIT(off, 4); } while (0)
74 #define EMIT2_off32(b1, b2, off) \
75 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
76 #define EMIT3_off32(b1, b2, b3, off) \
77 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
78 #define EMIT4_off32(b1, b2, b3, b4, off) \
79 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
81 #define jmp_label(label, jmp_insn_len) (label - cnt - jmp_insn_len)
83 static bool is_imm8(int value)
85 return value <= 127 && value >= -128;
88 static bool is_simm32(s64 value)
90 return value == (s64) (s32) value;
93 #define STACK_OFFSET(k) (k)
94 #define TCALL_CNT (MAX_BPF_JIT_REG + 0) /* Tail Call Count */
96 #define IA32_EAX (0x0)
97 #define IA32_EBX (0x3)
98 #define IA32_ECX (0x1)
99 #define IA32_EDX (0x2)
100 #define IA32_ESI (0x6)
101 #define IA32_EDI (0x7)
102 #define IA32_EBP (0x5)
103 #define IA32_ESP (0x4)
106 * List of x86 cond jumps opcodes (. + s8)
107 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
110 #define IA32_JAE 0x73
112 #define IA32_JNE 0x75
113 #define IA32_JBE 0x76
116 #define IA32_JGE 0x7D
117 #define IA32_JLE 0x7E
120 #define COND_JMP_OPCODE_INVALID (0xFF)
123 * Map eBPF registers to IA32 32bit registers or stack scratch space.
125 * 1. All the registers, R0-R10, are mapped to scratch space on stack.
126 * 2. We need two 64 bit temp registers to do complex operations on eBPF
128 * 3. For performance reason, the BPF_REG_AX for blinding constant, is
129 * mapped to real hardware register pair, IA32_ESI and IA32_EDI.
131 * As the eBPF registers are all 64 bit registers and IA32 has only 32 bit
132 * registers, we have to map each eBPF registers with two IA32 32 bit regs
133 * or scratch memory space and we have to build eBPF 64 bit register from those.
135 * We use IA32_EAX, IA32_EDX, IA32_ECX, IA32_EBX as temporary registers.
137 static const u8 bpf2ia32[][2] = {
138 /* Return value from in-kernel function, and exit value from eBPF */
139 [BPF_REG_0] = {STACK_OFFSET(0), STACK_OFFSET(4)},
141 /* The arguments from eBPF program to in-kernel function */
142 /* Stored on stack scratch space */
143 [BPF_REG_1] = {STACK_OFFSET(8), STACK_OFFSET(12)},
144 [BPF_REG_2] = {STACK_OFFSET(16), STACK_OFFSET(20)},
145 [BPF_REG_3] = {STACK_OFFSET(24), STACK_OFFSET(28)},
146 [BPF_REG_4] = {STACK_OFFSET(32), STACK_OFFSET(36)},
147 [BPF_REG_5] = {STACK_OFFSET(40), STACK_OFFSET(44)},
149 /* Callee saved registers that in-kernel function will preserve */
150 /* Stored on stack scratch space */
151 [BPF_REG_6] = {STACK_OFFSET(48), STACK_OFFSET(52)},
152 [BPF_REG_7] = {STACK_OFFSET(56), STACK_OFFSET(60)},
153 [BPF_REG_8] = {STACK_OFFSET(64), STACK_OFFSET(68)},
154 [BPF_REG_9] = {STACK_OFFSET(72), STACK_OFFSET(76)},
156 /* Read only Frame Pointer to access Stack */
157 [BPF_REG_FP] = {STACK_OFFSET(80), STACK_OFFSET(84)},
159 /* Temporary register for blinding constants. */
160 [BPF_REG_AX] = {IA32_ESI, IA32_EDI},
162 /* Tail call count. Stored on stack scratch space. */
163 [TCALL_CNT] = {STACK_OFFSET(88), STACK_OFFSET(92)},
166 #define dst_lo dst[0]
167 #define dst_hi dst[1]
168 #define src_lo src[0]
169 #define src_hi src[1]
171 #define STACK_ALIGNMENT 8
173 * Stack space for BPF_REG_1, BPF_REG_2, BPF_REG_3, BPF_REG_4,
174 * BPF_REG_5, BPF_REG_6, BPF_REG_7, BPF_REG_8, BPF_REG_9,
175 * BPF_REG_FP, BPF_REG_AX and Tail call counts.
177 #define SCRATCH_SIZE 96
179 /* Total stack size used in JITed code */
180 #define _STACK_SIZE (stack_depth + SCRATCH_SIZE)
182 #define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
184 /* Get the offset of eBPF REGISTERs stored on scratch space. */
185 #define STACK_VAR(off) (off)
187 /* Encode 'dst_reg' register into IA32 opcode 'byte' */
188 static u8 add_1reg(u8 byte, u32 dst_reg)
190 return byte + dst_reg;
193 /* Encode 'dst_reg' and 'src_reg' registers into IA32 opcode 'byte' */
194 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
196 return byte + dst_reg + (src_reg << 3);
199 static void jit_fill_hole(void *area, unsigned int size)
201 /* Fill whole space with int3 instructions */
202 memset(area, 0xcc, size);
205 static inline void emit_ia32_mov_i(const u8 dst, const u32 val, bool dstk,
214 EMIT2(0x33, add_2reg(0xC0, IA32_EAX, IA32_EAX));
215 /* mov dword ptr [ebp+off],eax */
216 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
219 EMIT3_off32(0xC7, add_1reg(0x40, IA32_EBP),
220 STACK_VAR(dst), val);
224 EMIT2(0x33, add_2reg(0xC0, dst, dst));
226 EMIT2_off32(0xC7, add_1reg(0xC0, dst),
232 /* dst = imm (4 bytes)*/
233 static inline void emit_ia32_mov_r(const u8 dst, const u8 src, bool dstk,
234 bool sstk, u8 **pprog)
238 u8 sreg = sstk ? IA32_EAX : src;
241 /* mov eax,dword ptr [ebp+off] */
242 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
244 /* mov dword ptr [ebp+off],eax */
245 EMIT3(0x89, add_2reg(0x40, IA32_EBP, sreg), STACK_VAR(dst));
248 EMIT2(0x89, add_2reg(0xC0, dst, sreg));
254 static inline void emit_ia32_mov_r64(const bool is64, const u8 dst[],
255 const u8 src[], bool dstk,
256 bool sstk, u8 **pprog)
258 emit_ia32_mov_r(dst_lo, src_lo, dstk, sstk, pprog);
260 /* complete 8 byte move */
261 emit_ia32_mov_r(dst_hi, src_hi, dstk, sstk, pprog);
263 /* zero out high 4 bytes */
264 emit_ia32_mov_i(dst_hi, 0, dstk, pprog);
267 /* Sign extended move */
268 static inline void emit_ia32_mov_i64(const bool is64, const u8 dst[],
269 const u32 val, bool dstk, u8 **pprog)
273 if (is64 && (val & (1<<31)))
275 emit_ia32_mov_i(dst_lo, val, dstk, pprog);
276 emit_ia32_mov_i(dst_hi, hi, dstk, pprog);
280 * ALU operation (32 bit)
283 static inline void emit_ia32_mul_r(const u8 dst, const u8 src, bool dstk,
284 bool sstk, u8 **pprog)
288 u8 sreg = sstk ? IA32_ECX : src;
291 /* mov ecx,dword ptr [ebp+off] */
292 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
295 /* mov eax,dword ptr [ebp+off] */
296 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
299 EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
302 EMIT2(0xF7, add_1reg(0xE0, sreg));
305 /* mov dword ptr [ebp+off],eax */
306 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
310 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
315 static inline void emit_ia32_to_le_r64(const u8 dst[], s32 val,
316 bool dstk, u8 **pprog)
320 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
321 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
323 if (dstk && val != 64) {
324 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
326 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
332 * Emit 'movzwl eax,ax' to zero extend 16-bit
336 EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
337 /* xor dreg_hi,dreg_hi */
338 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
341 /* xor dreg_hi,dreg_hi */
342 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
349 if (dstk && val != 64) {
350 /* mov dword ptr [ebp+off],dreg_lo */
351 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
353 /* mov dword ptr [ebp+off],dreg_hi */
354 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
360 static inline void emit_ia32_to_be_r64(const u8 dst[], s32 val,
361 bool dstk, u8 **pprog)
365 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
366 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
369 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
371 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
376 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
378 EMIT3(0xC1, add_1reg(0xC8, dreg_lo), 8);
381 EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
383 /* xor dreg_hi,dreg_hi */
384 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
387 /* Emit 'bswap eax' to swap lower 4 bytes */
389 EMIT1(add_1reg(0xC8, dreg_lo));
391 /* xor dreg_hi,dreg_hi */
392 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
395 /* Emit 'bswap eax' to swap lower 4 bytes */
397 EMIT1(add_1reg(0xC8, dreg_lo));
399 /* Emit 'bswap edx' to swap lower 4 bytes */
401 EMIT1(add_1reg(0xC8, dreg_hi));
403 /* mov ecx,dreg_hi */
404 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, dreg_hi));
405 /* mov dreg_hi,dreg_lo */
406 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
407 /* mov dreg_lo,ecx */
408 EMIT2(0x89, add_2reg(0xC0, dreg_lo, IA32_ECX));
413 /* mov dword ptr [ebp+off],dreg_lo */
414 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
416 /* mov dword ptr [ebp+off],dreg_hi */
417 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
424 * ALU operation (32 bit)
425 * dst = dst (div|mod) src
427 static inline void emit_ia32_div_mod_r(const u8 op, const u8 dst, const u8 src,
428 bool dstk, bool sstk, u8 **pprog)
434 /* mov ecx,dword ptr [ebp+off] */
435 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
437 else if (src != IA32_ECX)
439 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX));
442 /* mov eax,dword ptr [ebp+off] */
443 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
447 EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
450 EMIT2(0x31, add_2reg(0xC0, IA32_EDX, IA32_EDX));
452 EMIT2(0xF7, add_1reg(0xF0, IA32_ECX));
456 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
459 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EDX));
462 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
465 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
471 * ALU operation (32 bit)
472 * dst = dst (shift) src
474 static inline void emit_ia32_shift_r(const u8 op, const u8 dst, const u8 src,
475 bool dstk, bool sstk, u8 **pprog)
479 u8 dreg = dstk ? IA32_EAX : dst;
483 /* mov eax,dword ptr [ebp+off] */
484 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
487 /* mov ecx,dword ptr [ebp+off] */
488 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
489 else if (src != IA32_ECX)
491 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX));
503 EMIT2(0xD3, add_1reg(b2, dreg));
506 /* mov dword ptr [ebp+off],dreg */
507 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg), STACK_VAR(dst));
512 * ALU operation (32 bit)
515 static inline void emit_ia32_alu_r(const bool is64, const bool hi, const u8 op,
516 const u8 dst, const u8 src, bool dstk,
517 bool sstk, u8 **pprog)
521 u8 sreg = sstk ? IA32_EAX : src;
522 u8 dreg = dstk ? IA32_EDX : dst;
525 /* mov eax,dword ptr [ebp+off] */
526 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
529 /* mov eax,dword ptr [ebp+off] */
530 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(dst));
532 switch (BPF_OP(op)) {
533 /* dst = dst + src */
536 EMIT2(0x11, add_2reg(0xC0, dreg, sreg));
538 EMIT2(0x01, add_2reg(0xC0, dreg, sreg));
540 /* dst = dst - src */
543 EMIT2(0x19, add_2reg(0xC0, dreg, sreg));
545 EMIT2(0x29, add_2reg(0xC0, dreg, sreg));
547 /* dst = dst | src */
549 EMIT2(0x09, add_2reg(0xC0, dreg, sreg));
551 /* dst = dst & src */
553 EMIT2(0x21, add_2reg(0xC0, dreg, sreg));
555 /* dst = dst ^ src */
557 EMIT2(0x31, add_2reg(0xC0, dreg, sreg));
562 /* mov dword ptr [ebp+off],dreg */
563 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
568 /* ALU operation (64 bit) */
569 static inline void emit_ia32_alu_r64(const bool is64, const u8 op,
570 const u8 dst[], const u8 src[],
571 bool dstk, bool sstk,
576 emit_ia32_alu_r(is64, false, op, dst_lo, src_lo, dstk, sstk, &prog);
578 emit_ia32_alu_r(is64, true, op, dst_hi, src_hi, dstk, sstk,
581 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
586 * ALU operation (32 bit)
589 static inline void emit_ia32_alu_i(const bool is64, const bool hi, const u8 op,
590 const u8 dst, const s32 val, bool dstk,
595 u8 dreg = dstk ? IA32_EAX : dst;
599 /* mov eax,dword ptr [ebp+off] */
600 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
604 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val);
607 /* dst = dst + val */
611 EMIT3(0x83, add_1reg(0xD0, dreg), val);
613 EMIT2(0x11, add_2reg(0xC0, dreg, sreg));
616 EMIT3(0x83, add_1reg(0xC0, dreg), val);
618 EMIT2(0x01, add_2reg(0xC0, dreg, sreg));
621 /* dst = dst - val */
625 EMIT3(0x83, add_1reg(0xD8, dreg), val);
627 EMIT2(0x19, add_2reg(0xC0, dreg, sreg));
630 EMIT3(0x83, add_1reg(0xE8, dreg), val);
632 EMIT2(0x29, add_2reg(0xC0, dreg, sreg));
635 /* dst = dst | val */
638 EMIT3(0x83, add_1reg(0xC8, dreg), val);
640 EMIT2(0x09, add_2reg(0xC0, dreg, sreg));
642 /* dst = dst & val */
645 EMIT3(0x83, add_1reg(0xE0, dreg), val);
647 EMIT2(0x21, add_2reg(0xC0, dreg, sreg));
649 /* dst = dst ^ val */
652 EMIT3(0x83, add_1reg(0xF0, dreg), val);
654 EMIT2(0x31, add_2reg(0xC0, dreg, sreg));
657 EMIT2(0xF7, add_1reg(0xD8, dreg));
662 /* mov dword ptr [ebp+off],dreg */
663 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
668 /* ALU operation (64 bit) */
669 static inline void emit_ia32_alu_i64(const bool is64, const u8 op,
670 const u8 dst[], const u32 val,
671 bool dstk, u8 **pprog)
676 if (is64 && (val & (1<<31)))
679 emit_ia32_alu_i(is64, false, op, dst_lo, val, dstk, &prog);
681 emit_ia32_alu_i(is64, true, op, dst_hi, hi, dstk, &prog);
683 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
688 /* dst = ~dst (64 bit) */
689 static inline void emit_ia32_neg64(const u8 dst[], bool dstk, u8 **pprog)
693 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
694 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
697 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
699 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
704 EMIT2(0xF7, add_1reg(0xD8, dreg_lo));
705 /* adc dreg_hi,0x0 */
706 EMIT3(0x83, add_1reg(0xD0, dreg_hi), 0x00);
708 EMIT2(0xF7, add_1reg(0xD8, dreg_hi));
711 /* mov dword ptr [ebp+off],dreg_lo */
712 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
714 /* mov dword ptr [ebp+off],dreg_hi */
715 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
721 /* dst = dst << src */
722 static inline void emit_ia32_lsh_r64(const u8 dst[], const u8 src[],
723 bool dstk, bool sstk, u8 **pprog)
727 static int jmp_label1 = -1;
728 static int jmp_label2 = -1;
729 static int jmp_label3 = -1;
730 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
731 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
734 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
736 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
741 /* mov ecx,dword ptr [ebp+off] */
742 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
746 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
749 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
750 /* Jumps when >= 32 */
751 if (is_imm8(jmp_label(jmp_label1, 2)))
752 EMIT2(IA32_JAE, jmp_label(jmp_label1, 2));
754 EMIT2_off32(0x0F, IA32_JAE + 0x10, jmp_label(jmp_label1, 6));
758 EMIT2(0xD3, add_1reg(0xE0, dreg_hi));
759 /* mov ebx,dreg_lo */
760 EMIT2(0x8B, add_2reg(0xC0, dreg_lo, IA32_EBX));
762 EMIT2(0xD3, add_1reg(0xE0, dreg_lo));
764 /* IA32_ECX = -IA32_ECX + 32 */
766 EMIT2(0xF7, add_1reg(0xD8, IA32_ECX));
768 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 32);
771 EMIT2(0xD3, add_1reg(0xE8, IA32_EBX));
773 EMIT2(0x09, add_2reg(0xC0, dreg_hi, IA32_EBX));
776 if (is_imm8(jmp_label(jmp_label3, 2)))
777 EMIT2(0xEB, jmp_label(jmp_label3, 2));
779 EMIT1_off32(0xE9, jmp_label(jmp_label3, 5));
782 if (jmp_label1 == -1)
786 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 64);
787 /* Jumps when >= 64 */
788 if (is_imm8(jmp_label(jmp_label2, 2)))
789 EMIT2(IA32_JAE, jmp_label(jmp_label2, 2));
791 EMIT2_off32(0x0F, IA32_JAE + 0x10, jmp_label(jmp_label2, 6));
795 EMIT3(0x83, add_1reg(0xE8, IA32_ECX), 32);
797 EMIT2(0xD3, add_1reg(0xE0, dreg_lo));
798 /* mov dreg_hi,dreg_lo */
799 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
801 /* xor dreg_lo,dreg_lo */
802 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
805 if (is_imm8(jmp_label(jmp_label3, 2)))
806 EMIT2(0xEB, jmp_label(jmp_label3, 2));
808 EMIT1_off32(0xE9, jmp_label(jmp_label3, 5));
811 if (jmp_label2 == -1)
813 /* xor dreg_lo,dreg_lo */
814 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
815 /* xor dreg_hi,dreg_hi */
816 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
818 if (jmp_label3 == -1)
822 /* mov dword ptr [ebp+off],dreg_lo */
823 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
825 /* mov dword ptr [ebp+off],dreg_hi */
826 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
833 /* dst = dst >> src (signed)*/
834 static inline void emit_ia32_arsh_r64(const u8 dst[], const u8 src[],
835 bool dstk, bool sstk, u8 **pprog)
839 static int jmp_label1 = -1;
840 static int jmp_label2 = -1;
841 static int jmp_label3 = -1;
842 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
843 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
846 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
848 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
853 /* mov ecx,dword ptr [ebp+off] */
854 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
858 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
861 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
862 /* Jumps when >= 32 */
863 if (is_imm8(jmp_label(jmp_label1, 2)))
864 EMIT2(IA32_JAE, jmp_label(jmp_label1, 2));
866 EMIT2_off32(0x0F, IA32_JAE + 0x10, jmp_label(jmp_label1, 6));
869 /* lshr dreg_lo,cl */
870 EMIT2(0xD3, add_1reg(0xE8, dreg_lo));
871 /* mov ebx,dreg_hi */
872 EMIT2(0x8B, add_2reg(0xC0, dreg_hi, IA32_EBX));
873 /* ashr dreg_hi,cl */
874 EMIT2(0xD3, add_1reg(0xF8, dreg_hi));
876 /* IA32_ECX = -IA32_ECX + 32 */
878 EMIT2(0xF7, add_1reg(0xD8, IA32_ECX));
880 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 32);
883 EMIT2(0xD3, add_1reg(0xE0, IA32_EBX));
885 EMIT2(0x09, add_2reg(0xC0, dreg_lo, IA32_EBX));
888 if (is_imm8(jmp_label(jmp_label3, 2)))
889 EMIT2(0xEB, jmp_label(jmp_label3, 2));
891 EMIT1_off32(0xE9, jmp_label(jmp_label3, 5));
894 if (jmp_label1 == -1)
898 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 64);
899 /* Jumps when >= 64 */
900 if (is_imm8(jmp_label(jmp_label2, 2)))
901 EMIT2(IA32_JAE, jmp_label(jmp_label2, 2));
903 EMIT2_off32(0x0F, IA32_JAE + 0x10, jmp_label(jmp_label2, 6));
907 EMIT3(0x83, add_1reg(0xE8, IA32_ECX), 32);
908 /* ashr dreg_hi,cl */
909 EMIT2(0xD3, add_1reg(0xF8, dreg_hi));
910 /* mov dreg_lo,dreg_hi */
911 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
913 /* ashr dreg_hi,imm8 */
914 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
917 if (is_imm8(jmp_label(jmp_label3, 2)))
918 EMIT2(0xEB, jmp_label(jmp_label3, 2));
920 EMIT1_off32(0xE9, jmp_label(jmp_label3, 5));
923 if (jmp_label2 == -1)
925 /* ashr dreg_hi,imm8 */
926 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
927 /* mov dreg_lo,dreg_hi */
928 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
930 if (jmp_label3 == -1)
934 /* mov dword ptr [ebp+off],dreg_lo */
935 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
937 /* mov dword ptr [ebp+off],dreg_hi */
938 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
945 /* dst = dst >> src */
946 static inline void emit_ia32_rsh_r64(const u8 dst[], const u8 src[], bool dstk,
947 bool sstk, u8 **pprog)
951 static int jmp_label1 = -1;
952 static int jmp_label2 = -1;
953 static int jmp_label3 = -1;
954 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
955 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
958 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
960 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
965 /* mov ecx,dword ptr [ebp+off] */
966 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
970 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
973 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
974 /* Jumps when >= 32 */
975 if (is_imm8(jmp_label(jmp_label1, 2)))
976 EMIT2(IA32_JAE, jmp_label(jmp_label1, 2));
978 EMIT2_off32(0x0F, IA32_JAE + 0x10, jmp_label(jmp_label1, 6));
981 /* lshr dreg_lo,cl */
982 EMIT2(0xD3, add_1reg(0xE8, dreg_lo));
983 /* mov ebx,dreg_hi */
984 EMIT2(0x8B, add_2reg(0xC0, dreg_hi, IA32_EBX));
986 EMIT2(0xD3, add_1reg(0xE8, dreg_hi));
988 /* IA32_ECX = -IA32_ECX + 32 */
990 EMIT2(0xF7, add_1reg(0xD8, IA32_ECX));
992 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 32);
995 EMIT2(0xD3, add_1reg(0xE0, IA32_EBX));
997 EMIT2(0x09, add_2reg(0xC0, dreg_lo, IA32_EBX));
1000 if (is_imm8(jmp_label(jmp_label3, 2)))
1001 EMIT2(0xEB, jmp_label(jmp_label3, 2));
1003 EMIT1_off32(0xE9, jmp_label(jmp_label3, 5));
1006 if (jmp_label1 == -1)
1009 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 64);
1010 /* Jumps when >= 64 */
1011 if (is_imm8(jmp_label(jmp_label2, 2)))
1012 EMIT2(IA32_JAE, jmp_label(jmp_label2, 2));
1014 EMIT2_off32(0x0F, IA32_JAE + 0x10, jmp_label(jmp_label2, 6));
1018 EMIT3(0x83, add_1reg(0xE8, IA32_ECX), 32);
1019 /* shr dreg_hi,cl */
1020 EMIT2(0xD3, add_1reg(0xE8, dreg_hi));
1021 /* mov dreg_lo,dreg_hi */
1022 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1023 /* xor dreg_hi,dreg_hi */
1024 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
1027 if (is_imm8(jmp_label(jmp_label3, 2)))
1028 EMIT2(0xEB, jmp_label(jmp_label3, 2));
1030 EMIT1_off32(0xE9, jmp_label(jmp_label3, 5));
1033 if (jmp_label2 == -1)
1035 /* xor dreg_lo,dreg_lo */
1036 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
1037 /* xor dreg_hi,dreg_hi */
1038 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
1040 if (jmp_label3 == -1)
1044 /* mov dword ptr [ebp+off],dreg_lo */
1045 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
1047 /* mov dword ptr [ebp+off],dreg_hi */
1048 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
1055 /* dst = dst << val */
1056 static inline void emit_ia32_lsh_i64(const u8 dst[], const u32 val,
1057 bool dstk, u8 **pprog)
1061 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
1062 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1065 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1067 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1070 /* Do LSH operation */
1072 /* shl dreg_hi,imm8 */
1073 EMIT3(0xC1, add_1reg(0xE0, dreg_hi), val);
1074 /* mov ebx,dreg_lo */
1075 EMIT2(0x8B, add_2reg(0xC0, dreg_lo, IA32_EBX));
1076 /* shl dreg_lo,imm8 */
1077 EMIT3(0xC1, add_1reg(0xE0, dreg_lo), val);
1079 /* IA32_ECX = 32 - val */
1083 EMIT3(0x0F, 0xB6, add_2reg(0xC0, IA32_ECX, IA32_ECX));
1085 EMIT2(0xF7, add_1reg(0xD8, IA32_ECX));
1087 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 32);
1090 EMIT2(0xD3, add_1reg(0xE8, IA32_EBX));
1091 /* or dreg_hi,ebx */
1092 EMIT2(0x09, add_2reg(0xC0, dreg_hi, IA32_EBX));
1093 } else if (val >= 32 && val < 64) {
1094 u32 value = val - 32;
1096 /* shl dreg_lo,imm8 */
1097 EMIT3(0xC1, add_1reg(0xE0, dreg_lo), value);
1098 /* mov dreg_hi,dreg_lo */
1099 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
1100 /* xor dreg_lo,dreg_lo */
1101 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
1103 /* xor dreg_lo,dreg_lo */
1104 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
1105 /* xor dreg_hi,dreg_hi */
1106 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
1110 /* mov dword ptr [ebp+off],dreg_lo */
1111 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
1113 /* mov dword ptr [ebp+off],dreg_hi */
1114 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
1120 /* dst = dst >> val */
1121 static inline void emit_ia32_rsh_i64(const u8 dst[], const u32 val,
1122 bool dstk, u8 **pprog)
1126 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
1127 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1130 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1132 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1136 /* Do RSH operation */
1138 /* shr dreg_lo,imm8 */
1139 EMIT3(0xC1, add_1reg(0xE8, dreg_lo), val);
1140 /* mov ebx,dreg_hi */
1141 EMIT2(0x8B, add_2reg(0xC0, dreg_hi, IA32_EBX));
1142 /* shr dreg_hi,imm8 */
1143 EMIT3(0xC1, add_1reg(0xE8, dreg_hi), val);
1145 /* IA32_ECX = 32 - val */
1149 EMIT3(0x0F, 0xB6, add_2reg(0xC0, IA32_ECX, IA32_ECX));
1151 EMIT2(0xF7, add_1reg(0xD8, IA32_ECX));
1153 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 32);
1156 EMIT2(0xD3, add_1reg(0xE0, IA32_EBX));
1157 /* or dreg_lo,ebx */
1158 EMIT2(0x09, add_2reg(0xC0, dreg_lo, IA32_EBX));
1159 } else if (val >= 32 && val < 64) {
1160 u32 value = val - 32;
1162 /* shr dreg_hi,imm8 */
1163 EMIT3(0xC1, add_1reg(0xE8, dreg_hi), value);
1164 /* mov dreg_lo,dreg_hi */
1165 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1166 /* xor dreg_hi,dreg_hi */
1167 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
1169 /* xor dreg_lo,dreg_lo */
1170 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
1171 /* xor dreg_hi,dreg_hi */
1172 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
1176 /* mov dword ptr [ebp+off],dreg_lo */
1177 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
1179 /* mov dword ptr [ebp+off],dreg_hi */
1180 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
1186 /* dst = dst >> val (signed) */
1187 static inline void emit_ia32_arsh_i64(const u8 dst[], const u32 val,
1188 bool dstk, u8 **pprog)
1192 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
1193 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1196 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1198 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1201 /* Do RSH operation */
1203 /* shr dreg_lo,imm8 */
1204 EMIT3(0xC1, add_1reg(0xE8, dreg_lo), val);
1205 /* mov ebx,dreg_hi */
1206 EMIT2(0x8B, add_2reg(0xC0, dreg_hi, IA32_EBX));
1207 /* ashr dreg_hi,imm8 */
1208 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), val);
1210 /* IA32_ECX = 32 - val */
1214 EMIT3(0x0F, 0xB6, add_2reg(0xC0, IA32_ECX, IA32_ECX));
1216 EMIT2(0xF7, add_1reg(0xD8, IA32_ECX));
1218 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 32);
1221 EMIT2(0xD3, add_1reg(0xE0, IA32_EBX));
1222 /* or dreg_lo,ebx */
1223 EMIT2(0x09, add_2reg(0xC0, dreg_lo, IA32_EBX));
1224 } else if (val >= 32 && val < 64) {
1225 u32 value = val - 32;
1227 /* ashr dreg_hi,imm8 */
1228 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), value);
1229 /* mov dreg_lo,dreg_hi */
1230 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1232 /* ashr dreg_hi,imm8 */
1233 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1235 /* ashr dreg_hi,imm8 */
1236 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1237 /* mov dreg_lo,dreg_hi */
1238 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1242 /* mov dword ptr [ebp+off],dreg_lo */
1243 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
1245 /* mov dword ptr [ebp+off],dreg_hi */
1246 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
1252 static inline void emit_ia32_mul_r64(const u8 dst[], const u8 src[], bool dstk,
1253 bool sstk, u8 **pprog)
1259 /* mov eax,dword ptr [ebp+off] */
1260 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1263 /* mov eax,dst_hi */
1264 EMIT2(0x8B, add_2reg(0xC0, dst_hi, IA32_EAX));
1267 /* mul dword ptr [ebp+off] */
1268 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
1271 EMIT2(0xF7, add_1reg(0xE0, src_lo));
1274 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1277 /* mov eax,dword ptr [ebp+off] */
1278 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1281 /* mov eax,dst_lo */
1282 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1285 /* mul dword ptr [ebp+off] */
1286 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_hi));
1289 EMIT2(0xF7, add_1reg(0xE0, src_hi));
1292 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1295 /* mov eax,dword ptr [ebp+off] */
1296 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1299 /* mov eax,dst_lo */
1300 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1303 /* mul dword ptr [ebp+off] */
1304 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
1307 EMIT2(0xF7, add_1reg(0xE0, src_lo));
1310 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
1313 /* mov dword ptr [ebp+off],eax */
1314 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1316 /* mov dword ptr [ebp+off],ecx */
1317 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
1320 /* mov dst_lo,eax */
1321 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
1322 /* mov dst_hi,ecx */
1323 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX));
1329 static inline void emit_ia32_mul_i64(const u8 dst[], const u32 val,
1330 bool dstk, u8 **pprog)
1336 hi = val & (1<<31) ? (u32)~0 : 0;
1337 /* movl eax,imm32 */
1338 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
1340 /* mul dword ptr [ebp+off] */
1341 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_hi));
1344 EMIT2(0xF7, add_1reg(0xE0, dst_hi));
1347 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1349 /* movl eax,imm32 */
1350 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), hi);
1352 /* mul dword ptr [ebp+off] */
1353 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
1356 EMIT2(0xF7, add_1reg(0xE0, dst_lo));
1358 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1360 /* movl eax,imm32 */
1361 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
1363 /* mul dword ptr [ebp+off] */
1364 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
1367 EMIT2(0xF7, add_1reg(0xE0, dst_lo));
1370 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
1373 /* mov dword ptr [ebp+off],eax */
1374 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1376 /* mov dword ptr [ebp+off],ecx */
1377 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
1380 /* mov dword ptr [ebp+off],eax */
1381 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
1382 /* mov dword ptr [ebp+off],ecx */
1383 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX));
1389 static int bpf_size_to_x86_bytes(int bpf_size)
1391 if (bpf_size == BPF_W)
1393 else if (bpf_size == BPF_H)
1395 else if (bpf_size == BPF_B)
1397 else if (bpf_size == BPF_DW)
1398 return 4; /* imm32 */
1403 struct jit_context {
1404 int cleanup_addr; /* Epilogue code offset */
1407 /* Maximum number of bytes emitted while JITing one eBPF insn */
1408 #define BPF_MAX_INSN_SIZE 128
1409 #define BPF_INSN_SAFETY 64
1411 #define PROLOGUE_SIZE 35
1414 * Emit prologue code for BPF program and check it's size.
1415 * bpf_tail_call helper will skip it while jumping into another program.
1417 static void emit_prologue(u8 **pprog, u32 stack_depth)
1421 const u8 *r1 = bpf2ia32[BPF_REG_1];
1422 const u8 fplo = bpf2ia32[BPF_REG_FP][0];
1423 const u8 fphi = bpf2ia32[BPF_REG_FP][1];
1424 const u8 *tcc = bpf2ia32[TCALL_CNT];
1437 /* sub esp,STACK_SIZE */
1438 EMIT2_off32(0x81, 0xEC, STACK_SIZE);
1439 /* sub ebp,SCRATCH_SIZE+12*/
1440 EMIT3(0x83, add_1reg(0xE8, IA32_EBP), SCRATCH_SIZE + 12);
1442 EMIT2(0x31, add_2reg(0xC0, IA32_EBX, IA32_EBX));
1444 /* Set up BPF prog stack base register */
1445 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBP), STACK_VAR(fplo));
1446 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(fphi));
1448 /* Move BPF_CTX (EAX) to BPF_REG_R1 */
1449 /* mov dword ptr [ebp+off],eax */
1450 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
1451 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(r1[1]));
1453 /* Initialize Tail Count */
1454 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[0]));
1455 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1457 BUILD_BUG_ON(cnt != PROLOGUE_SIZE);
1461 /* Emit epilogue code for BPF program */
1462 static void emit_epilogue(u8 **pprog, u32 stack_depth)
1465 const u8 *r0 = bpf2ia32[BPF_REG_0];
1468 /* mov eax,dword ptr [ebp+off]*/
1469 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r0[0]));
1470 /* mov edx,dword ptr [ebp+off]*/
1471 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r0[1]));
1473 /* add ebp,SCRATCH_SIZE+12*/
1474 EMIT3(0x83, add_1reg(0xC0, IA32_EBP), SCRATCH_SIZE + 12);
1476 /* mov ebx,dword ptr [ebp-12]*/
1477 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), -12);
1478 /* mov esi,dword ptr [ebp-8]*/
1479 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ESI), -8);
1480 /* mov edi,dword ptr [ebp-4]*/
1481 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDI), -4);
1483 EMIT1(0xC9); /* leave */
1484 EMIT1(0xC3); /* ret */
1489 * Generate the following code:
1490 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
1491 * if (index >= array->map.max_entries)
1493 * if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
1495 * prog = array->ptrs[index];
1498 * goto *(prog->bpf_func + prologue_size);
1501 static void emit_bpf_tail_call(u8 **pprog)
1505 const u8 *r1 = bpf2ia32[BPF_REG_1];
1506 const u8 *r2 = bpf2ia32[BPF_REG_2];
1507 const u8 *r3 = bpf2ia32[BPF_REG_3];
1508 const u8 *tcc = bpf2ia32[TCALL_CNT];
1510 static int jmp_label1 = -1;
1513 * if (index >= array->map.max_entries)
1516 /* mov eax,dword ptr [ebp+off] */
1517 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r2[0]));
1518 /* mov edx,dword ptr [ebp+off] */
1519 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r3[0]));
1521 /* cmp dword ptr [eax+off],edx */
1522 EMIT3(0x39, add_2reg(0x40, IA32_EAX, IA32_EDX),
1523 offsetof(struct bpf_array, map.max_entries));
1525 EMIT2(IA32_JBE, jmp_label(jmp_label1, 2));
1528 * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
1531 lo = (u32)MAX_TAIL_CALL_CNT;
1532 hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
1533 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
1534 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1537 EMIT3(0x83, add_1reg(0xF8, IA32_EBX), hi);
1540 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), lo);
1543 EMIT2(IA32_JAE, jmp_label(jmp_label1, 2));
1546 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 0x01);
1548 EMIT3(0x83, add_1reg(0xD0, IA32_EBX), 0x00);
1550 /* mov dword ptr [ebp+off],eax */
1551 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
1552 /* mov dword ptr [ebp+off],edx */
1553 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1555 /* prog = array->ptrs[index]; */
1556 /* mov edx, [eax + edx * 4 + offsetof(...)] */
1557 EMIT3_off32(0x8B, 0x94, 0x90, offsetof(struct bpf_array, ptrs));
1564 EMIT2(0x85, add_2reg(0xC0, IA32_EDX, IA32_EDX));
1566 EMIT2(IA32_JE, jmp_label(jmp_label1, 2));
1568 /* goto *(prog->bpf_func + prologue_size); */
1569 /* mov edx, dword ptr [edx + 32] */
1570 EMIT3(0x8B, add_2reg(0x40, IA32_EDX, IA32_EDX),
1571 offsetof(struct bpf_prog, bpf_func));
1572 /* add edx,prologue_size */
1573 EMIT3(0x83, add_1reg(0xC0, IA32_EDX), PROLOGUE_SIZE);
1575 /* mov eax,dword ptr [ebp+off] */
1576 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
1579 * Now we're ready to jump into next BPF program:
1580 * eax == ctx (1st arg)
1581 * edx == prog->bpf_func + prologue_size
1583 RETPOLINE_EDX_BPF_JIT();
1585 if (jmp_label1 == -1)
1592 /* Push the scratch stack register on top of the stack. */
1593 static inline void emit_push_r64(const u8 src[], u8 **pprog)
1598 /* mov ecx,dword ptr [ebp+off] */
1599 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_hi));
1603 /* mov ecx,dword ptr [ebp+off] */
1604 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_lo));
1611 static u8 get_cond_jmp_opcode(const u8 op, bool is_cmp_lo)
1615 /* Convert BPF opcode to x86 */
1622 jmp_cond = IA32_JNE;
1625 /* GT is unsigned '>', JA in x86 */
1629 /* LT is unsigned '<', JB in x86 */
1633 /* GE is unsigned '>=', JAE in x86 */
1634 jmp_cond = IA32_JAE;
1637 /* LE is unsigned '<=', JBE in x86 */
1638 jmp_cond = IA32_JBE;
1642 /* Signed '>', GT in x86 */
1645 /* GT is unsigned '>', JA in x86 */
1650 /* Signed '<', LT in x86 */
1653 /* LT is unsigned '<', JB in x86 */
1658 /* Signed '>=', GE in x86 */
1659 jmp_cond = IA32_JGE;
1661 /* GE is unsigned '>=', JAE in x86 */
1662 jmp_cond = IA32_JAE;
1666 /* Signed '<=', LE in x86 */
1667 jmp_cond = IA32_JLE;
1669 /* LE is unsigned '<=', JBE in x86 */
1670 jmp_cond = IA32_JBE;
1672 default: /* to silence GCC warning */
1673 jmp_cond = COND_JMP_OPCODE_INVALID;
1680 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
1681 int oldproglen, struct jit_context *ctx)
1683 struct bpf_insn *insn = bpf_prog->insnsi;
1684 int insn_cnt = bpf_prog->len;
1685 bool seen_exit = false;
1686 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
1691 emit_prologue(&prog, bpf_prog->aux->stack_depth);
1693 for (i = 0; i < insn_cnt; i++, insn++) {
1694 const s32 imm32 = insn->imm;
1695 const bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1696 const bool dstk = insn->dst_reg == BPF_REG_AX ? false : true;
1697 const bool sstk = insn->src_reg == BPF_REG_AX ? false : true;
1698 const u8 code = insn->code;
1699 const u8 *dst = bpf2ia32[insn->dst_reg];
1700 const u8 *src = bpf2ia32[insn->src_reg];
1701 const u8 *r0 = bpf2ia32[BPF_REG_0];
1708 /* ALU operations */
1710 case BPF_ALU | BPF_MOV | BPF_K:
1711 case BPF_ALU | BPF_MOV | BPF_X:
1712 case BPF_ALU64 | BPF_MOV | BPF_K:
1713 case BPF_ALU64 | BPF_MOV | BPF_X:
1714 switch (BPF_SRC(code)) {
1716 emit_ia32_mov_r64(is64, dst, src, dstk,
1720 /* Sign-extend immediate value to dst reg */
1721 emit_ia32_mov_i64(is64, dst, imm32,
1726 /* dst = dst + src/imm */
1727 /* dst = dst - src/imm */
1728 /* dst = dst | src/imm */
1729 /* dst = dst & src/imm */
1730 /* dst = dst ^ src/imm */
1731 /* dst = dst * src/imm */
1732 /* dst = dst << src */
1733 /* dst = dst >> src */
1734 case BPF_ALU | BPF_ADD | BPF_K:
1735 case BPF_ALU | BPF_ADD | BPF_X:
1736 case BPF_ALU | BPF_SUB | BPF_K:
1737 case BPF_ALU | BPF_SUB | BPF_X:
1738 case BPF_ALU | BPF_OR | BPF_K:
1739 case BPF_ALU | BPF_OR | BPF_X:
1740 case BPF_ALU | BPF_AND | BPF_K:
1741 case BPF_ALU | BPF_AND | BPF_X:
1742 case BPF_ALU | BPF_XOR | BPF_K:
1743 case BPF_ALU | BPF_XOR | BPF_X:
1744 case BPF_ALU64 | BPF_ADD | BPF_K:
1745 case BPF_ALU64 | BPF_ADD | BPF_X:
1746 case BPF_ALU64 | BPF_SUB | BPF_K:
1747 case BPF_ALU64 | BPF_SUB | BPF_X:
1748 case BPF_ALU64 | BPF_OR | BPF_K:
1749 case BPF_ALU64 | BPF_OR | BPF_X:
1750 case BPF_ALU64 | BPF_AND | BPF_K:
1751 case BPF_ALU64 | BPF_AND | BPF_X:
1752 case BPF_ALU64 | BPF_XOR | BPF_K:
1753 case BPF_ALU64 | BPF_XOR | BPF_X:
1754 switch (BPF_SRC(code)) {
1756 emit_ia32_alu_r64(is64, BPF_OP(code), dst,
1757 src, dstk, sstk, &prog);
1760 emit_ia32_alu_i64(is64, BPF_OP(code), dst,
1761 imm32, dstk, &prog);
1765 case BPF_ALU | BPF_MUL | BPF_K:
1766 case BPF_ALU | BPF_MUL | BPF_X:
1767 switch (BPF_SRC(code)) {
1769 emit_ia32_mul_r(dst_lo, src_lo, dstk,
1774 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1776 emit_ia32_mul_r(dst_lo, IA32_ECX, dstk,
1780 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1782 case BPF_ALU | BPF_LSH | BPF_X:
1783 case BPF_ALU | BPF_RSH | BPF_X:
1784 case BPF_ALU | BPF_ARSH | BPF_K:
1785 case BPF_ALU | BPF_ARSH | BPF_X:
1786 switch (BPF_SRC(code)) {
1788 emit_ia32_shift_r(BPF_OP(code), dst_lo, src_lo,
1793 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1795 emit_ia32_shift_r(BPF_OP(code), dst_lo,
1796 IA32_ECX, dstk, false,
1800 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1802 /* dst = dst / src(imm) */
1803 /* dst = dst % src(imm) */
1804 case BPF_ALU | BPF_DIV | BPF_K:
1805 case BPF_ALU | BPF_DIV | BPF_X:
1806 case BPF_ALU | BPF_MOD | BPF_K:
1807 case BPF_ALU | BPF_MOD | BPF_X:
1808 switch (BPF_SRC(code)) {
1810 emit_ia32_div_mod_r(BPF_OP(code), dst_lo,
1811 src_lo, dstk, sstk, &prog);
1815 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1817 emit_ia32_div_mod_r(BPF_OP(code), dst_lo,
1818 IA32_ECX, dstk, false,
1822 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1824 case BPF_ALU64 | BPF_DIV | BPF_K:
1825 case BPF_ALU64 | BPF_DIV | BPF_X:
1826 case BPF_ALU64 | BPF_MOD | BPF_K:
1827 case BPF_ALU64 | BPF_MOD | BPF_X:
1829 /* dst = dst >> imm */
1830 /* dst = dst << imm */
1831 case BPF_ALU | BPF_RSH | BPF_K:
1832 case BPF_ALU | BPF_LSH | BPF_K:
1833 if (unlikely(imm32 > 31))
1836 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
1837 emit_ia32_shift_r(BPF_OP(code), dst_lo, IA32_ECX, dstk,
1839 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1841 /* dst = dst << imm */
1842 case BPF_ALU64 | BPF_LSH | BPF_K:
1843 if (unlikely(imm32 > 63))
1845 emit_ia32_lsh_i64(dst, imm32, dstk, &prog);
1847 /* dst = dst >> imm */
1848 case BPF_ALU64 | BPF_RSH | BPF_K:
1849 if (unlikely(imm32 > 63))
1851 emit_ia32_rsh_i64(dst, imm32, dstk, &prog);
1853 /* dst = dst << src */
1854 case BPF_ALU64 | BPF_LSH | BPF_X:
1855 emit_ia32_lsh_r64(dst, src, dstk, sstk, &prog);
1857 /* dst = dst >> src */
1858 case BPF_ALU64 | BPF_RSH | BPF_X:
1859 emit_ia32_rsh_r64(dst, src, dstk, sstk, &prog);
1861 /* dst = dst >> src (signed) */
1862 case BPF_ALU64 | BPF_ARSH | BPF_X:
1863 emit_ia32_arsh_r64(dst, src, dstk, sstk, &prog);
1865 /* dst = dst >> imm (signed) */
1866 case BPF_ALU64 | BPF_ARSH | BPF_K:
1867 if (unlikely(imm32 > 63))
1869 emit_ia32_arsh_i64(dst, imm32, dstk, &prog);
1872 case BPF_ALU | BPF_NEG:
1873 emit_ia32_alu_i(is64, false, BPF_OP(code),
1874 dst_lo, 0, dstk, &prog);
1875 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1877 /* dst = ~dst (64 bit) */
1878 case BPF_ALU64 | BPF_NEG:
1879 emit_ia32_neg64(dst, dstk, &prog);
1881 /* dst = dst * src/imm */
1882 case BPF_ALU64 | BPF_MUL | BPF_X:
1883 case BPF_ALU64 | BPF_MUL | BPF_K:
1884 switch (BPF_SRC(code)) {
1886 emit_ia32_mul_r64(dst, src, dstk, sstk, &prog);
1889 emit_ia32_mul_i64(dst, imm32, dstk, &prog);
1893 /* dst = htole(dst) */
1894 case BPF_ALU | BPF_END | BPF_FROM_LE:
1895 emit_ia32_to_le_r64(dst, imm32, dstk, &prog);
1897 /* dst = htobe(dst) */
1898 case BPF_ALU | BPF_END | BPF_FROM_BE:
1899 emit_ia32_to_be_r64(dst, imm32, dstk, &prog);
1902 case BPF_LD | BPF_IMM | BPF_DW: {
1906 emit_ia32_mov_i(dst_lo, lo, dstk, &prog);
1907 emit_ia32_mov_i(dst_hi, hi, dstk, &prog);
1912 /* ST: *(u8*)(dst_reg + off) = imm */
1913 case BPF_ST | BPF_MEM | BPF_H:
1914 case BPF_ST | BPF_MEM | BPF_B:
1915 case BPF_ST | BPF_MEM | BPF_W:
1916 case BPF_ST | BPF_MEM | BPF_DW:
1918 /* mov eax,dword ptr [ebp+off] */
1919 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1922 /* mov eax,dst_lo */
1923 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1925 switch (BPF_SIZE(code)) {
1927 EMIT(0xC6, 1); break;
1929 EMIT2(0x66, 0xC7); break;
1932 EMIT(0xC7, 1); break;
1935 if (is_imm8(insn->off))
1936 EMIT2(add_1reg(0x40, IA32_EAX), insn->off);
1938 EMIT1_off32(add_1reg(0x80, IA32_EAX),
1940 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(code)));
1942 if (BPF_SIZE(code) == BPF_DW) {
1945 hi = imm32 & (1<<31) ? (u32)~0 : 0;
1946 EMIT2_off32(0xC7, add_1reg(0x80, IA32_EAX),
1952 /* STX: *(u8*)(dst_reg + off) = src_reg */
1953 case BPF_STX | BPF_MEM | BPF_B:
1954 case BPF_STX | BPF_MEM | BPF_H:
1955 case BPF_STX | BPF_MEM | BPF_W:
1956 case BPF_STX | BPF_MEM | BPF_DW:
1958 /* mov eax,dword ptr [ebp+off] */
1959 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1962 /* mov eax,dst_lo */
1963 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1966 /* mov edx,dword ptr [ebp+off] */
1967 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1970 /* mov edx,src_lo */
1971 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EDX));
1973 switch (BPF_SIZE(code)) {
1975 EMIT(0x88, 1); break;
1977 EMIT2(0x66, 0x89); break;
1980 EMIT(0x89, 1); break;
1983 if (is_imm8(insn->off))
1984 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
1987 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
1990 if (BPF_SIZE(code) == BPF_DW) {
1992 /* mov edi,dword ptr [ebp+off] */
1993 EMIT3(0x8B, add_2reg(0x40, IA32_EBP,
1997 /* mov edi,src_hi */
1998 EMIT2(0x8B, add_2reg(0xC0, src_hi,
2001 if (is_imm8(insn->off + 4)) {
2002 EMIT2(add_2reg(0x40, IA32_EAX,
2006 EMIT1(add_2reg(0x80, IA32_EAX,
2008 EMIT(insn->off + 4, 4);
2013 /* LDX: dst_reg = *(u8*)(src_reg + off) */
2014 case BPF_LDX | BPF_MEM | BPF_B:
2015 case BPF_LDX | BPF_MEM | BPF_H:
2016 case BPF_LDX | BPF_MEM | BPF_W:
2017 case BPF_LDX | BPF_MEM | BPF_DW:
2019 /* mov eax,dword ptr [ebp+off] */
2020 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2023 /* mov eax,dword ptr [ebp+off] */
2024 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EAX));
2026 switch (BPF_SIZE(code)) {
2028 EMIT2(0x0F, 0xB6); break;
2030 EMIT2(0x0F, 0xB7); break;
2033 EMIT(0x8B, 1); break;
2036 if (is_imm8(insn->off))
2037 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
2040 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
2044 /* mov dword ptr [ebp+off],edx */
2045 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
2048 /* mov dst_lo,edx */
2049 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EDX));
2050 switch (BPF_SIZE(code)) {
2055 EMIT3(0xC7, add_1reg(0x40, IA32_EBP),
2059 EMIT3(0xC7, add_1reg(0xC0, dst_hi), 0);
2064 add_2reg(0x80, IA32_EAX, IA32_EDX),
2068 add_2reg(0x40, IA32_EBP,
2073 add_2reg(0xC0, dst_hi, IA32_EDX));
2080 case BPF_JMP | BPF_CALL:
2082 const u8 *r1 = bpf2ia32[BPF_REG_1];
2083 const u8 *r2 = bpf2ia32[BPF_REG_2];
2084 const u8 *r3 = bpf2ia32[BPF_REG_3];
2085 const u8 *r4 = bpf2ia32[BPF_REG_4];
2086 const u8 *r5 = bpf2ia32[BPF_REG_5];
2088 if (insn->src_reg == BPF_PSEUDO_CALL)
2091 func = (u8 *) __bpf_call_base + imm32;
2092 jmp_offset = func - (image + addrs[i]);
2094 if (!imm32 || !is_simm32(jmp_offset)) {
2095 pr_err("unsupported BPF func %d addr %p image %p\n",
2096 imm32, func, image);
2100 /* mov eax,dword ptr [ebp+off] */
2101 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2103 /* mov edx,dword ptr [ebp+off] */
2104 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
2107 emit_push_r64(r5, &prog);
2108 emit_push_r64(r4, &prog);
2109 emit_push_r64(r3, &prog);
2110 emit_push_r64(r2, &prog);
2112 EMIT1_off32(0xE8, jmp_offset + 9);
2114 /* mov dword ptr [ebp+off],eax */
2115 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
2117 /* mov dword ptr [ebp+off],edx */
2118 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
2122 EMIT3(0x83, add_1reg(0xC0, IA32_ESP), 32);
2125 case BPF_JMP | BPF_TAIL_CALL:
2126 emit_bpf_tail_call(&prog);
2130 case BPF_JMP | BPF_JEQ | BPF_X:
2131 case BPF_JMP | BPF_JNE | BPF_X:
2132 case BPF_JMP | BPF_JGT | BPF_X:
2133 case BPF_JMP | BPF_JLT | BPF_X:
2134 case BPF_JMP | BPF_JGE | BPF_X:
2135 case BPF_JMP | BPF_JLE | BPF_X:
2136 case BPF_JMP32 | BPF_JEQ | BPF_X:
2137 case BPF_JMP32 | BPF_JNE | BPF_X:
2138 case BPF_JMP32 | BPF_JGT | BPF_X:
2139 case BPF_JMP32 | BPF_JLT | BPF_X:
2140 case BPF_JMP32 | BPF_JGE | BPF_X:
2141 case BPF_JMP32 | BPF_JLE | BPF_X:
2142 case BPF_JMP32 | BPF_JSGT | BPF_X:
2143 case BPF_JMP32 | BPF_JSLE | BPF_X:
2144 case BPF_JMP32 | BPF_JSLT | BPF_X:
2145 case BPF_JMP32 | BPF_JSGE | BPF_X: {
2146 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
2147 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2148 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2149 u8 sreg_lo = sstk ? IA32_ECX : src_lo;
2150 u8 sreg_hi = sstk ? IA32_EBX : src_hi;
2153 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2157 add_2reg(0x40, IA32_EBP,
2163 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
2167 add_2reg(0x40, IA32_EBP,
2173 /* cmp dreg_hi,sreg_hi */
2174 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2177 /* cmp dreg_lo,sreg_lo */
2178 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2181 case BPF_JMP | BPF_JSGT | BPF_X:
2182 case BPF_JMP | BPF_JSLE | BPF_X:
2183 case BPF_JMP | BPF_JSLT | BPF_X:
2184 case BPF_JMP | BPF_JSGE | BPF_X: {
2185 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2186 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2187 u8 sreg_lo = sstk ? IA32_ECX : src_lo;
2188 u8 sreg_hi = sstk ? IA32_EBX : src_hi;
2191 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2194 add_2reg(0x40, IA32_EBP,
2200 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
2203 add_2reg(0x40, IA32_EBP,
2208 /* cmp dreg_hi,sreg_hi */
2209 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2210 EMIT2(IA32_JNE, 10);
2211 /* cmp dreg_lo,sreg_lo */
2212 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2213 goto emit_cond_jmp_signed;
2215 case BPF_JMP | BPF_JSET | BPF_X:
2216 case BPF_JMP32 | BPF_JSET | BPF_X: {
2217 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
2218 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2219 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2220 u8 sreg_lo = sstk ? IA32_ECX : src_lo;
2221 u8 sreg_hi = sstk ? IA32_EBX : src_hi;
2224 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2228 add_2reg(0x40, IA32_EBP,
2234 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
2238 add_2reg(0x40, IA32_EBP,
2242 /* and dreg_lo,sreg_lo */
2243 EMIT2(0x23, add_2reg(0xC0, sreg_lo, dreg_lo));
2244 /* and dreg_hi,sreg_hi */
2245 EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2246 /* or dreg_lo,dreg_hi */
2247 EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2250 case BPF_JMP | BPF_JSET | BPF_K:
2251 case BPF_JMP32 | BPF_JSET | BPF_K: {
2252 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
2253 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2254 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2255 u8 sreg_lo = IA32_ECX;
2256 u8 sreg_hi = IA32_EBX;
2260 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2264 add_2reg(0x40, IA32_EBP,
2270 EMIT2_off32(0xC7, add_1reg(0xC0, sreg_lo), imm32);
2272 /* and dreg_lo,sreg_lo */
2273 EMIT2(0x23, add_2reg(0xC0, sreg_lo, dreg_lo));
2275 hi = imm32 & (1 << 31) ? (u32)~0 : 0;
2277 EMIT2_off32(0xC7, add_1reg(0xC0, sreg_hi), hi);
2278 /* and dreg_hi,sreg_hi */
2279 EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2280 /* or dreg_lo,dreg_hi */
2281 EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2285 case BPF_JMP | BPF_JEQ | BPF_K:
2286 case BPF_JMP | BPF_JNE | BPF_K:
2287 case BPF_JMP | BPF_JGT | BPF_K:
2288 case BPF_JMP | BPF_JLT | BPF_K:
2289 case BPF_JMP | BPF_JGE | BPF_K:
2290 case BPF_JMP | BPF_JLE | BPF_K:
2291 case BPF_JMP32 | BPF_JEQ | BPF_K:
2292 case BPF_JMP32 | BPF_JNE | BPF_K:
2293 case BPF_JMP32 | BPF_JGT | BPF_K:
2294 case BPF_JMP32 | BPF_JLT | BPF_K:
2295 case BPF_JMP32 | BPF_JGE | BPF_K:
2296 case BPF_JMP32 | BPF_JLE | BPF_K:
2297 case BPF_JMP32 | BPF_JSGT | BPF_K:
2298 case BPF_JMP32 | BPF_JSLE | BPF_K:
2299 case BPF_JMP32 | BPF_JSLT | BPF_K:
2300 case BPF_JMP32 | BPF_JSGE | BPF_K: {
2301 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
2302 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2303 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2304 u8 sreg_lo = IA32_ECX;
2305 u8 sreg_hi = IA32_EBX;
2309 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2313 add_2reg(0x40, IA32_EBP,
2319 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
2321 hi = imm32 & (1 << 31) ? (u32)~0 : 0;
2323 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
2324 /* cmp dreg_hi,sreg_hi */
2325 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2328 /* cmp dreg_lo,sreg_lo */
2329 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2331 emit_cond_jmp: jmp_cond = get_cond_jmp_opcode(BPF_OP(code), false);
2332 if (jmp_cond == COND_JMP_OPCODE_INVALID)
2334 jmp_offset = addrs[i + insn->off] - addrs[i];
2335 if (is_imm8(jmp_offset)) {
2336 EMIT2(jmp_cond, jmp_offset);
2337 } else if (is_simm32(jmp_offset)) {
2338 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2340 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2345 case BPF_JMP | BPF_JSGT | BPF_K:
2346 case BPF_JMP | BPF_JSLE | BPF_K:
2347 case BPF_JMP | BPF_JSLT | BPF_K:
2348 case BPF_JMP | BPF_JSGE | BPF_K: {
2349 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2350 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2351 u8 sreg_lo = IA32_ECX;
2352 u8 sreg_hi = IA32_EBX;
2356 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2359 add_2reg(0x40, IA32_EBP,
2365 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
2366 hi = imm32 & (1 << 31) ? (u32)~0 : 0;
2368 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
2369 /* cmp dreg_hi,sreg_hi */
2370 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2371 EMIT2(IA32_JNE, 10);
2372 /* cmp dreg_lo,sreg_lo */
2373 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2376 * For simplicity of branch offset computation,
2377 * let's use fixed jump coding here.
2379 emit_cond_jmp_signed: /* Check the condition for low 32-bit comparison */
2380 jmp_cond = get_cond_jmp_opcode(BPF_OP(code), true);
2381 if (jmp_cond == COND_JMP_OPCODE_INVALID)
2383 jmp_offset = addrs[i + insn->off] - addrs[i] + 8;
2384 if (is_simm32(jmp_offset)) {
2385 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2387 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2392 /* Check the condition for high 32-bit comparison */
2393 jmp_cond = get_cond_jmp_opcode(BPF_OP(code), false);
2394 if (jmp_cond == COND_JMP_OPCODE_INVALID)
2396 jmp_offset = addrs[i + insn->off] - addrs[i];
2397 if (is_simm32(jmp_offset)) {
2398 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2400 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2405 case BPF_JMP | BPF_JA:
2406 if (insn->off == -1)
2407 /* -1 jmp instructions will always jump
2408 * backwards two bytes. Explicitly handling
2409 * this case avoids wasting too many passes
2410 * when there are long sequences of replaced
2415 jmp_offset = addrs[i + insn->off] - addrs[i];
2418 /* Optimize out nop jumps */
2421 if (is_imm8(jmp_offset)) {
2422 EMIT2(0xEB, jmp_offset);
2423 } else if (is_simm32(jmp_offset)) {
2424 EMIT1_off32(0xE9, jmp_offset);
2426 pr_err("jmp gen bug %llx\n", jmp_offset);
2430 /* STX XADD: lock *(u32 *)(dst + off) += src */
2431 case BPF_STX | BPF_XADD | BPF_W:
2432 /* STX XADD: lock *(u64 *)(dst + off) += src */
2433 case BPF_STX | BPF_XADD | BPF_DW:
2435 case BPF_JMP | BPF_EXIT:
2437 jmp_offset = ctx->cleanup_addr - addrs[i];
2441 /* Update cleanup_addr */
2442 ctx->cleanup_addr = proglen;
2443 emit_epilogue(&prog, bpf_prog->aux->stack_depth);
2446 pr_info_once("*** NOT YET: opcode %02x ***\n", code);
2450 * This error will be seen if new instruction was added
2451 * to interpreter, but not to JIT or if there is junk in
2454 pr_err("bpf_jit: unknown opcode %02x\n", code);
2459 if (ilen > BPF_MAX_INSN_SIZE) {
2460 pr_err("bpf_jit: fatal insn size error\n");
2465 if (unlikely(proglen + ilen > oldproglen)) {
2466 pr_err("bpf_jit: fatal error\n");
2469 memcpy(image + proglen, temp, ilen);
2478 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2480 struct bpf_binary_header *header = NULL;
2481 struct bpf_prog *tmp, *orig_prog = prog;
2482 int proglen, oldproglen = 0;
2483 struct jit_context ctx = {};
2484 bool tmp_blinded = false;
2490 if (!prog->jit_requested)
2493 tmp = bpf_jit_blind_constants(prog);
2495 * If blinding was requested and we failed during blinding,
2496 * we must fall back to the interpreter.
2505 addrs = kmalloc_array(prog->len, sizeof(*addrs), GFP_KERNEL);
2512 * Before first pass, make a rough estimation of addrs[]
2513 * each BPF instruction is translated to less than 64 bytes
2515 for (proglen = 0, i = 0; i < prog->len; i++) {
2519 ctx.cleanup_addr = proglen;
2522 * JITed image shrinks with every pass and the loop iterates
2523 * until the image stops shrinking. Very large BPF programs
2524 * may converge on the last pass. In such case do one more
2525 * pass to emit the final image.
2527 for (pass = 0; pass < 20 || image; pass++) {
2528 proglen = do_jit(prog, addrs, image, oldproglen, &ctx);
2533 bpf_jit_binary_free(header);
2538 if (proglen != oldproglen) {
2539 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2540 proglen, oldproglen);
2545 if (proglen == oldproglen) {
2546 header = bpf_jit_binary_alloc(proglen, &image,
2553 oldproglen = proglen;
2557 if (bpf_jit_enable > 1)
2558 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2561 bpf_jit_binary_lock_ro(header);
2562 prog->bpf_func = (void *)image;
2564 prog->jited_len = proglen;
2573 bpf_jit_prog_release_other(prog, prog == orig_prog ?