2 * Suspend support specific for i386/x86-64.
4 * Distribute under GPLv2
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
11 #include <linux/suspend.h>
12 #include <linux/export.h>
13 #include <linux/smp.h>
14 #include <linux/perf_event.h>
15 #include <linux/tboot.h>
17 #include <asm/pgtable.h>
18 #include <asm/proto.h>
22 #include <asm/suspend.h>
23 #include <asm/fpu/internal.h>
24 #include <asm/debugreg.h>
26 #include <asm/mmu_context.h>
27 #include <linux/dmi.h>
30 __visible unsigned long saved_context_ebx;
31 __visible unsigned long saved_context_esp, saved_context_ebp;
32 __visible unsigned long saved_context_esi, saved_context_edi;
33 __visible unsigned long saved_context_eflags;
35 struct saved_context saved_context;
37 static void msr_save_context(struct saved_context *ctxt)
39 struct saved_msr *msr = ctxt->saved_msrs.array;
40 struct saved_msr *end = msr + ctxt->saved_msrs.num;
43 msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
48 static void msr_restore_context(struct saved_context *ctxt)
50 struct saved_msr *msr = ctxt->saved_msrs.array;
51 struct saved_msr *end = msr + ctxt->saved_msrs.num;
55 wrmsrl(msr->info.msr_no, msr->info.reg.q);
61 * __save_processor_state - save CPU registers before creating a
62 * hibernation image and before restoring the memory state from it
63 * @ctxt - structure to store the registers contents in
65 * NOTE: If there is a CPU register the modification of which by the
66 * boot kernel (ie. the kernel used for loading the hibernation image)
67 * might affect the operations of the restored target kernel (ie. the one
68 * saved in the hibernation image), then its contents must be saved by this
69 * function. In other words, if kernel A is hibernated and different
70 * kernel B is used for loading the hibernation image into memory, the
71 * kernel A's __save_processor_state() function must save all registers
72 * needed by kernel A, so that it can operate correctly after the resume
73 * regardless of what kernel B does in the meantime.
75 static void __save_processor_state(struct saved_context *ctxt)
78 mtrr_save_fixed_ranges(NULL);
86 store_idt(&ctxt->idt);
89 store_idt((struct desc_ptr *)&ctxt->idt_limit);
92 * We save it here, but restore it only in the hibernate case.
93 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
94 * mode in "secondary_startup_64". In 32-bit mode it is done via
95 * 'pmode_gdt' in wakeup_start.
97 ctxt->gdt_desc.size = GDT_SIZE - 1;
98 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
102 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
107 savesegment(es, ctxt->es);
108 savesegment(fs, ctxt->fs);
109 savesegment(gs, ctxt->gs);
110 savesegment(ss, ctxt->ss);
113 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
114 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
115 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
116 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
117 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
119 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
120 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
121 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
122 mtrr_save_fixed_ranges(NULL);
124 rdmsrl(MSR_EFER, ctxt->efer);
130 ctxt->cr0 = read_cr0();
131 ctxt->cr2 = read_cr2();
132 ctxt->cr3 = __read_cr3();
133 ctxt->cr4 = __read_cr4();
135 ctxt->cr8 = read_cr8();
137 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
139 msr_save_context(ctxt);
142 /* Needed by apm.c */
143 void save_processor_state(void)
145 __save_processor_state(&saved_context);
146 x86_platform.save_sched_clock_state();
149 EXPORT_SYMBOL(save_processor_state);
152 static void do_fpu_end(void)
155 * Restore FPU regs if necessary.
160 static void fix_processor_context(void)
162 int cpu = smp_processor_id();
163 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
165 struct desc_struct *desc = get_cpu_gdt_rw(cpu);
168 set_tss_desc(cpu, t); /*
169 * This just modifies memory; should not be
170 * necessary. But... This is necessary, because
171 * 386 hardware has concept of busy TSS or some
176 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
177 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
178 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
180 syscall_init(); /* This sets MSR_*STAR and related */
182 load_TR_desc(); /* This does ltr */
183 load_mm_ldt(current->active_mm); /* This does lldt */
184 initialize_tlbstate_and_flush();
188 /* The processor is back on the direct GDT, load back the fixmap */
189 load_fixmap_gdt(cpu);
193 * __restore_processor_state - restore the contents of CPU registers saved
194 * by __save_processor_state()
195 * @ctxt - structure to load the registers contents from
197 static void notrace __restore_processor_state(struct saved_context *ctxt)
199 if (ctxt->misc_enable_saved)
200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
204 /* cr4 was introduced in the Pentium CPU */
207 __write_cr4(ctxt->cr4);
210 wrmsrl(MSR_EFER, ctxt->efer);
211 write_cr8(ctxt->cr8);
212 __write_cr4(ctxt->cr4);
214 write_cr3(ctxt->cr3);
215 write_cr2(ctxt->cr2);
216 write_cr0(ctxt->cr0);
219 * now restore the descriptor tables to their proper values
220 * ltr is done i fix_processor_context().
223 load_idt(&ctxt->idt);
226 load_idt((const struct desc_ptr *)&ctxt->idt_limit);
233 loadsegment(es, ctxt->es);
234 loadsegment(fs, ctxt->fs);
235 loadsegment(gs, ctxt->gs);
236 loadsegment(ss, ctxt->ss);
241 if (boot_cpu_has(X86_FEATURE_SEP))
245 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
246 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
247 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
248 load_gs_index(ctxt->gs);
249 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
251 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
252 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
253 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
256 fix_processor_context();
259 tsc_verify_tsc_adjust(true);
260 x86_platform.restore_sched_clock_state();
262 perf_restore_debug_store();
263 msr_restore_context(ctxt);
266 /* Needed by apm.c */
267 void notrace restore_processor_state(void)
269 __restore_processor_state(&saved_context);
272 EXPORT_SYMBOL(restore_processor_state);
275 #if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
276 static void resume_play_dead(void)
279 tboot_shutdown(TB_SHUTDOWN_WFS);
283 int hibernate_resume_nonboot_cpu_disable(void)
285 void (*play_dead)(void) = smp_ops.play_dead;
289 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
290 * during hibernate image restoration, because it is likely that the
291 * monitored address will be actually written to at that time and then
292 * the "dead" CPU will attempt to execute instructions again, but the
293 * address in its instruction pointer may not be possible to resolve
294 * any more at that point (the page tables used by it previously may
295 * have been overwritten by hibernate image data).
297 smp_ops.play_dead = resume_play_dead;
298 ret = disable_nonboot_cpus();
299 smp_ops.play_dead = play_dead;
305 * When bsp_check() is called in hibernate and suspend, cpu hotplug
306 * is disabled already. So it's unnessary to handle race condition between
307 * cpumask query and cpu hotplug.
309 static int bsp_check(void)
311 if (cpumask_first(cpu_online_mask) != 0) {
312 pr_warn("CPU0 is offline.\n");
319 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
325 case PM_SUSPEND_PREPARE:
326 case PM_HIBERNATION_PREPARE:
329 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
330 case PM_RESTORE_PREPARE:
332 * When system resumes from hibernation, online CPU0 because
333 * 1. it's required for resume and
334 * 2. the CPU was online before hibernation
337 _debug_hotplug_cpu(0, 1);
339 case PM_POST_RESTORE:
341 * When a resume really happens, this code won't be called.
343 * This code is called only when user space hibernation software
344 * prepares for snapshot device during boot time. So we just
345 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
346 * preparing the snapshot device.
348 * This works for normal boot case in our CPU0 hotplug debug
349 * mode, i.e. CPU0 is offline and user mode hibernation
350 * software initializes during boot time.
352 * If CPU0 is online and user application accesses snapshot
353 * device after boot time, this will offline CPU0 and user may
354 * see different CPU0 state before and after accessing
355 * the snapshot device. But hopefully this is not a case when
356 * user debugging CPU0 hotplug. Even if users hit this case,
357 * they can easily online CPU0 back.
359 * To simplify this debug code, we only consider normal boot
360 * case. Otherwise we need to remember CPU0's state and restore
361 * to that state and resolve racy conditions etc.
363 _debug_hotplug_cpu(0, 0);
369 return notifier_from_errno(ret);
372 static int __init bsp_pm_check_init(void)
375 * Set this bsp_pm_callback as lower priority than
376 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
377 * earlier to disable cpu hotplug before bsp online check.
379 pm_notifier(bsp_pm_callback, -INT_MAX);
383 core_initcall(bsp_pm_check_init);
385 static int msr_init_context(const u32 *msr_id, const int total_num)
388 struct saved_msr *msr_array;
390 if (saved_context.saved_msrs.array || saved_context.saved_msrs.num > 0) {
391 pr_err("x86/pm: MSR quirk already applied, please check your DMI match table.\n");
395 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
397 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
401 for (i = 0; i < total_num; i++) {
402 msr_array[i].info.msr_no = msr_id[i];
403 msr_array[i].valid = false;
404 msr_array[i].info.reg.q = 0;
406 saved_context.saved_msrs.num = total_num;
407 saved_context.saved_msrs.array = msr_array;
413 * The following section is a quirk framework for problematic BIOSen:
414 * Sometimes MSRs are modified by the BIOSen after suspended to
415 * RAM, this might cause unexpected behavior after wakeup.
416 * Thus we save/restore these specified MSRs across suspend/resume
417 * in order to work around it.
419 * For any further problematic BIOSen/platforms,
420 * please add your own function similar to msr_initialize_bdw.
422 static int msr_initialize_bdw(const struct dmi_system_id *d)
424 /* Add any extra MSR ids into this array. */
425 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
427 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
428 return msr_init_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
431 static const struct dmi_system_id msr_save_dmi_table[] = {
433 .callback = msr_initialize_bdw,
434 .ident = "BROADWELL BDX_EP",
436 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
437 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
443 static int pm_check_save_msr(void)
445 dmi_check_system(msr_save_dmi_table);
449 device_initcall(pm_check_save_msr);