2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
18 #include <linux/errno.h>
19 #include <linux/init.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/bootmem.h>
24 #include <linux/kernel.h>
25 #include <linux/percpu.h>
26 #include <linux/cpu.h>
28 #include <linux/of_fdt.h>
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
35 # include <linux/timex.h>
39 # include <linux/seq_file.h>
42 #include <asm/bootparam.h>
43 #include <asm/mmu_context.h>
44 #include <asm/pgtable.h>
45 #include <asm/processor.h>
46 #include <asm/timex.h>
47 #include <asm/platform.h>
49 #include <asm/setup.h>
50 #include <asm/param.h>
51 #include <asm/traps.h>
53 #include <asm/sysmem.h>
55 #include <platform/hardware.h>
57 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
58 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
61 #ifdef CONFIG_BLK_DEV_FD
62 extern struct fd_ops no_fd_ops;
63 struct fd_ops *fd_ops;
66 extern struct rtc_ops no_rtc_ops;
67 struct rtc_ops *rtc_ops;
69 #ifdef CONFIG_BLK_DEV_INITRD
70 extern unsigned long initrd_start;
71 extern unsigned long initrd_end;
72 int initrd_is_mapped = 0;
73 extern int initrd_below_start_ok;
77 void *dtb_start = __dtb_start;
80 unsigned char aux_device_present;
81 extern unsigned long loops_per_jiffy;
83 /* Command line specified as configuration option. */
85 static char __initdata command_line[COMMAND_LINE_SIZE];
87 #ifdef CONFIG_CMDLINE_BOOL
88 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
92 * Boot parameter parsing.
94 * The Xtensa port uses a list of variable-sized tags to pass data to
95 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
96 * to be recognised. The list is terminated with a zero-sized
100 typedef struct tagtable {
102 int (*parse)(const bp_tag_t*);
105 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
106 __attribute__((used, section(".taglist"))) = { tag, fn }
108 /* parse current tag */
110 static int __init parse_tag_mem(const bp_tag_t *tag)
112 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
114 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
117 return memblock_add(mi->start, mi->end - mi->start);
120 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
122 #ifdef CONFIG_BLK_DEV_INITRD
124 static int __init parse_tag_initrd(const bp_tag_t* tag)
126 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
128 initrd_start = (unsigned long)__va(mi->start);
129 initrd_end = (unsigned long)__va(mi->end);
134 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
138 static int __init parse_tag_fdt(const bp_tag_t *tag)
140 dtb_start = __va(tag->data[0]);
144 __tagtable(BP_TAG_FDT, parse_tag_fdt);
146 #endif /* CONFIG_OF */
148 #endif /* CONFIG_BLK_DEV_INITRD */
150 static int __init parse_tag_cmdline(const bp_tag_t* tag)
152 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
156 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
158 static int __init parse_bootparam(const bp_tag_t* tag)
160 extern tagtable_t __tagtable_begin, __tagtable_end;
163 /* Boot parameters must start with a BP_TAG_FIRST tag. */
165 if (tag->id != BP_TAG_FIRST) {
166 printk(KERN_WARNING "Invalid boot parameters!\n");
170 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
172 /* Parse all tags. */
174 while (tag != NULL && tag->id != BP_TAG_LAST) {
175 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
176 if (tag->id == t->tag) {
181 if (t == &__tagtable_end)
182 printk(KERN_WARNING "Ignoring tag "
183 "0x%08x\n", tag->id);
184 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
192 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
193 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
194 EXPORT_SYMBOL(xtensa_kio_paddr);
196 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
197 int depth, void *data)
199 const __be32 *ranges;
205 if (!of_flat_dt_is_compatible(node, "simple-bus"))
208 ranges = of_get_flat_dt_prop(node, "ranges", &len);
214 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
215 /* round down to nearest 256MB boundary */
216 xtensa_kio_paddr &= 0xf0000000;
221 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
222 int depth, void *data)
228 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
231 memblock_add(base, size);
234 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
236 return __alloc_bootmem(size, align, 0);
239 void __init early_init_devtree(void *params)
241 early_init_dt_scan(params);
242 of_scan_flat_dt(xtensa_dt_io_area, NULL);
244 if (!command_line[0])
245 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
248 #endif /* CONFIG_OF */
251 * Initialize architecture. (Early stage)
254 void __init init_arch(bp_tag_t *bp_start)
256 /* Parse boot parameters */
259 parse_bootparam(bp_start);
262 early_init_devtree(dtb_start);
265 #ifdef CONFIG_CMDLINE_BOOL
266 if (!command_line[0])
267 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
270 /* Early hook for platforms */
272 platform_init(bp_start);
274 /* Initialize MMU. */
280 * Initialize system. Setup memory and reserve regions.
285 extern char _WindowVectors_text_start;
286 extern char _WindowVectors_text_end;
287 extern char _DebugInterruptVector_literal_start;
288 extern char _DebugInterruptVector_text_end;
289 extern char _KernelExceptionVector_literal_start;
290 extern char _KernelExceptionVector_text_end;
291 extern char _UserExceptionVector_literal_start;
292 extern char _UserExceptionVector_text_end;
293 extern char _DoubleExceptionVector_literal_start;
294 extern char _DoubleExceptionVector_text_end;
295 #if XCHAL_EXCM_LEVEL >= 2
296 extern char _Level2InterruptVector_text_start;
297 extern char _Level2InterruptVector_text_end;
299 #if XCHAL_EXCM_LEVEL >= 3
300 extern char _Level3InterruptVector_text_start;
301 extern char _Level3InterruptVector_text_end;
303 #if XCHAL_EXCM_LEVEL >= 4
304 extern char _Level4InterruptVector_text_start;
305 extern char _Level4InterruptVector_text_end;
307 #if XCHAL_EXCM_LEVEL >= 5
308 extern char _Level5InterruptVector_text_start;
309 extern char _Level5InterruptVector_text_end;
311 #if XCHAL_EXCM_LEVEL >= 6
312 extern char _Level6InterruptVector_text_start;
313 extern char _Level6InterruptVector_text_end;
316 extern char _SecondaryResetVector_text_start;
317 extern char _SecondaryResetVector_text_end;
321 #ifdef CONFIG_S32C1I_SELFTEST
322 #if XCHAL_HAVE_S32C1I
324 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
327 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
329 * If *v == cmp, set *v = set. Return previous *v.
331 static inline int probed_compare_swap(int *v, int cmp, int set)
335 __asm__ __volatile__(
338 " wsr %2, scompare1\n"
339 "1: s32c1i %0, %3, 0\n"
340 : "=a" (set), "=&a" (tmp)
341 : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
347 /* Handle probed exception */
349 static void __init do_probed_exception(struct pt_regs *regs,
350 unsigned long exccause)
352 if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
353 regs->pc += 3; /* skip the s32c1i instruction */
356 do_unhandled(regs, exccause);
360 /* Simple test of S32C1I (soc bringup assist) */
362 static int __init check_s32c1i(void)
364 int n, cause1, cause2;
365 void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
368 handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
369 do_probed_exception);
370 handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
371 do_probed_exception);
372 handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
373 do_probed_exception);
375 /* First try an S32C1I that does not store: */
378 n = probed_compare_swap(&rcw_word, 0, 2);
381 /* took exception? */
383 /* unclean exception? */
384 if (n != 2 || rcw_word != 1)
385 panic("S32C1I exception error");
386 } else if (rcw_word != 1 || n != 1) {
387 panic("S32C1I compare error");
390 /* Then an S32C1I that stores: */
392 rcw_word = 0x1234567;
393 n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
397 /* unclean exception? */
398 if (n != 0xabcde || rcw_word != 0x1234567)
399 panic("S32C1I exception error (b)");
400 } else if (rcw_word != 0xabcde || n != 0x1234567) {
401 panic("S32C1I store error");
404 /* Verify consistency of exceptions: */
405 if (cause1 || cause2) {
406 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
407 /* If emulation of S32C1I upon bus error gets implemented,
408 we can get rid of this panic for single core (not SMP) */
409 panic("S32C1I exceptions not currently supported");
411 if (cause1 != cause2)
412 panic("inconsistent S32C1I exceptions");
414 trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
415 trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
416 trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
420 #else /* XCHAL_HAVE_S32C1I */
422 /* This condition should not occur with a commercially deployed processor.
423 Display reminder for early engr test or demo chips / FPGA bitstreams */
424 static int __init check_s32c1i(void)
426 pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
430 #endif /* XCHAL_HAVE_S32C1I */
431 early_initcall(check_s32c1i);
432 #endif /* CONFIG_S32C1I_SELFTEST */
434 static inline int mem_reserve(unsigned long start, unsigned long end)
436 return memblock_reserve(start, end - start);
439 void __init setup_arch(char **cmdline_p)
441 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
442 *cmdline_p = command_line;
444 /* Reserve some memory regions */
446 #ifdef CONFIG_BLK_DEV_INITRD
447 if (initrd_start < initrd_end) {
448 initrd_is_mapped = mem_reserve(__pa(initrd_start),
449 __pa(initrd_end)) == 0;
450 initrd_below_start_ok = 1;
456 mem_reserve(__pa(&_stext), __pa(&_end));
458 mem_reserve(__pa(&_WindowVectors_text_start),
459 __pa(&_WindowVectors_text_end));
461 mem_reserve(__pa(&_DebugInterruptVector_literal_start),
462 __pa(&_DebugInterruptVector_text_end));
464 mem_reserve(__pa(&_KernelExceptionVector_literal_start),
465 __pa(&_KernelExceptionVector_text_end));
467 mem_reserve(__pa(&_UserExceptionVector_literal_start),
468 __pa(&_UserExceptionVector_text_end));
470 mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
471 __pa(&_DoubleExceptionVector_text_end));
473 #if XCHAL_EXCM_LEVEL >= 2
474 mem_reserve(__pa(&_Level2InterruptVector_text_start),
475 __pa(&_Level2InterruptVector_text_end));
477 #if XCHAL_EXCM_LEVEL >= 3
478 mem_reserve(__pa(&_Level3InterruptVector_text_start),
479 __pa(&_Level3InterruptVector_text_end));
481 #if XCHAL_EXCM_LEVEL >= 4
482 mem_reserve(__pa(&_Level4InterruptVector_text_start),
483 __pa(&_Level4InterruptVector_text_end));
485 #if XCHAL_EXCM_LEVEL >= 5
486 mem_reserve(__pa(&_Level5InterruptVector_text_start),
487 __pa(&_Level5InterruptVector_text_end));
489 #if XCHAL_EXCM_LEVEL >= 6
490 mem_reserve(__pa(&_Level6InterruptVector_text_start),
491 __pa(&_Level6InterruptVector_text_end));
495 mem_reserve(__pa(&_SecondaryResetVector_text_start),
496 __pa(&_SecondaryResetVector_text_end));
501 unflatten_and_copy_device_tree();
503 platform_setup(cmdline_p);
513 # if defined(CONFIG_VGA_CONSOLE)
514 conswitchp = &vga_con;
515 # elif defined(CONFIG_DUMMY_CONSOLE)
516 conswitchp = &dummy_con;
521 platform_pcibios_init();
525 static DEFINE_PER_CPU(struct cpu, cpu_data);
527 static int __init topology_init(void)
531 for_each_possible_cpu(i) {
532 struct cpu *cpu = &per_cpu(cpu_data, i);
533 cpu->hotpluggable = !!i;
534 register_cpu(cpu, i);
539 subsys_initcall(topology_init);
543 #if XCHAL_HAVE_PTP_MMU
546 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
548 * Way 4 is not currently used by linux.
549 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
550 * Way 5 shall be flushed and way 6 shall be set to identity mapping
553 local_flush_tlb_all();
554 invalidate_page_directory();
555 #if XCHAL_HAVE_SPANNING_WAY
558 unsigned long vaddr = (unsigned long)cpu_reset;
559 unsigned long paddr = __pa(vaddr);
560 unsigned long tmpaddr = vaddr + SZ_512M;
561 unsigned long tmp0, tmp1, tmp2, tmp3;
564 * Find a place for the temporary mapping. It must not be
565 * in the same 512MB region with vaddr or paddr, otherwise
566 * there may be multihit exception either on entry to the
567 * temporary mapping, or on entry to the identity mapping.
568 * (512MB is the biggest page size supported by TLB.)
570 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
573 /* Invalidate mapping in the selected temporary area */
574 if (itlb_probe(tmpaddr) & 0x8)
575 invalidate_itlb_entry(itlb_probe(tmpaddr));
576 if (itlb_probe(tmpaddr + PAGE_SIZE) & 0x8)
577 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
580 * Map two consecutive pages starting at the physical address
581 * of this function to the temporary mapping area.
583 write_itlb_entry(__pte((paddr & PAGE_MASK) |
587 tmpaddr & PAGE_MASK);
588 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
592 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
594 /* Reinitialize TLB */
595 __asm__ __volatile__ ("movi %0, 1f\n\t"
601 * No literal, data or stack access
605 /* Initialize *tlbcfg */
607 "wsr %0, itlbcfg\n\t"
608 "wsr %0, dtlbcfg\n\t"
609 /* Invalidate TLB way 5 */
616 "addi %0, %0, -1\n\t"
618 /* Initialize TLB way 6 */
627 "addi %0, %0, -1\n\t"
629 /* Jump to identity mapping */
632 /* Complete way 6 initialization */
635 /* Invalidate temporary mapping */
640 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
642 : "a"(tmpaddr - vaddr),
644 "a"(SZ_128M), "a"(SZ_512M),
646 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
651 __asm__ __volatile__ ("movi a2, 0\n\t"
652 "wsr a2, icountlevel\n\t"
655 #if XCHAL_NUM_IBREAK > 0
656 "wsr a2, ibreakenable\n\t"
666 : "a" (XCHAL_RESET_VECTOR_VADDR)
672 void machine_restart(char * cmd)
677 void machine_halt(void)
683 void machine_power_off(void)
685 platform_power_off();
688 #ifdef CONFIG_PROC_FS
691 * Display some core information through /proc/cpuinfo.
695 c_show(struct seq_file *f, void *slot)
697 /* high-level stuff */
698 seq_printf(f, "CPU count\t: %u\n"
699 "CPU list\t: %*pbl\n"
700 "vendor_id\t: Tensilica\n"
701 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
702 "core ID\t\t: " XCHAL_CORE_ID "\n"
705 "cpu MHz\t\t: %lu.%02lu\n"
706 "bogomips\t: %lu.%02lu\n",
708 cpumask_pr_args(cpu_online_mask),
709 XCHAL_BUILD_UNIQUE_ID,
710 XCHAL_HAVE_BE ? "big" : "little",
712 (ccount_freq/10000) % 100,
713 loops_per_jiffy/(500000/HZ),
714 (loops_per_jiffy/(5000/HZ)) % 100);
716 seq_printf(f,"flags\t\t: "
726 #if XCHAL_HAVE_DENSITY
729 #if XCHAL_HAVE_BOOLEANS
738 #if XCHAL_HAVE_MINMAX
744 #if XCHAL_HAVE_CLAMPS
756 #if XCHAL_HAVE_MUL32_HIGH
762 #if XCHAL_HAVE_S32C1I
768 seq_printf(f,"physical aregs\t: %d\n"
779 seq_printf(f,"num ints\t: %d\n"
783 "debug level\t: %d\n",
784 XCHAL_NUM_INTERRUPTS,
785 XCHAL_NUM_EXTINTERRUPTS,
791 seq_printf(f,"icache line size: %d\n"
792 "icache ways\t: %d\n"
793 "icache size\t: %d\n"
795 #if XCHAL_ICACHE_LINE_LOCKABLE
799 "dcache line size: %d\n"
800 "dcache ways\t: %d\n"
801 "dcache size\t: %d\n"
803 #if XCHAL_DCACHE_IS_WRITEBACK
806 #if XCHAL_DCACHE_LINE_LOCKABLE
810 XCHAL_ICACHE_LINESIZE,
813 XCHAL_DCACHE_LINESIZE,
821 * We show only CPU #0 info.
824 c_start(struct seq_file *f, loff_t *pos)
826 return (*pos == 0) ? (void *)1 : NULL;
830 c_next(struct seq_file *f, void *v, loff_t *pos)
836 c_stop(struct seq_file *f, void *v)
840 const struct seq_operations cpuinfo_op =
848 #endif /* CONFIG_PROC_FS */