2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
18 #include <linux/errno.h>
19 #include <linux/init.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
27 #include <linux/of_fdt.h>
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
34 # include <linux/seq_file.h>
37 #include <asm/bootparam.h>
38 #include <asm/kasan.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
41 #include <asm/processor.h>
42 #include <asm/timex.h>
43 #include <asm/platform.h>
45 #include <asm/setup.h>
46 #include <asm/param.h>
48 #include <asm/sysmem.h>
50 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
51 struct screen_info screen_info = {
54 .orig_video_cols = 80,
55 .orig_video_lines = 24,
56 .orig_video_isVGA = 1,
57 .orig_video_points = 16,
61 #ifdef CONFIG_BLK_DEV_INITRD
62 extern unsigned long initrd_start;
63 extern unsigned long initrd_end;
64 int initrd_is_mapped = 0;
65 extern int initrd_below_start_ok;
69 void *dtb_start = __dtb_start;
72 extern unsigned long loops_per_jiffy;
74 /* Command line specified as configuration option. */
76 static char __initdata command_line[COMMAND_LINE_SIZE];
78 #ifdef CONFIG_CMDLINE_BOOL
79 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
82 #ifdef CONFIG_PARSE_BOOTPARAM
84 * Boot parameter parsing.
86 * The Xtensa port uses a list of variable-sized tags to pass data to
87 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
88 * to be recognised. The list is terminated with a zero-sized
92 typedef struct tagtable {
94 int (*parse)(const bp_tag_t*);
97 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
98 __attribute__((used, section(".taglist"))) = { tag, fn }
100 /* parse current tag */
102 static int __init parse_tag_mem(const bp_tag_t *tag)
104 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
106 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
109 return memblock_add(mi->start, mi->end - mi->start);
112 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
114 #ifdef CONFIG_BLK_DEV_INITRD
116 static int __init parse_tag_initrd(const bp_tag_t* tag)
118 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
120 initrd_start = (unsigned long)__va(mi->start);
121 initrd_end = (unsigned long)__va(mi->end);
126 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
128 #endif /* CONFIG_BLK_DEV_INITRD */
132 static int __init parse_tag_fdt(const bp_tag_t *tag)
134 dtb_start = __va(tag->data[0]);
138 __tagtable(BP_TAG_FDT, parse_tag_fdt);
140 #endif /* CONFIG_OF */
142 static int __init parse_tag_cmdline(const bp_tag_t* tag)
144 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
148 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
150 static int __init parse_bootparam(const bp_tag_t* tag)
152 extern tagtable_t __tagtable_begin, __tagtable_end;
155 /* Boot parameters must start with a BP_TAG_FIRST tag. */
157 if (tag->id != BP_TAG_FIRST) {
158 pr_warn("Invalid boot parameters!\n");
162 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
164 /* Parse all tags. */
166 while (tag != NULL && tag->id != BP_TAG_LAST) {
167 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
168 if (tag->id == t->tag) {
173 if (t == &__tagtable_end)
174 pr_warn("Ignoring tag 0x%08x\n", tag->id);
175 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
181 static int __init parse_bootparam(const bp_tag_t *tag)
183 pr_info("Ignoring boot parameters at %p\n", tag);
190 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
191 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
192 EXPORT_SYMBOL(xtensa_kio_paddr);
194 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
195 int depth, void *data)
197 const __be32 *ranges;
203 if (!of_flat_dt_is_compatible(node, "simple-bus"))
206 ranges = of_get_flat_dt_prop(node, "ranges", &len);
212 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
213 /* round down to nearest 256MB boundary */
214 xtensa_kio_paddr &= 0xf0000000;
221 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
222 int depth, void *data)
228 void __init early_init_devtree(void *params)
230 early_init_dt_scan(params);
231 of_scan_flat_dt(xtensa_dt_io_area, NULL);
233 if (!command_line[0])
234 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
237 #endif /* CONFIG_OF */
240 * Initialize architecture. (Early stage)
243 void __init init_arch(bp_tag_t *bp_start)
245 /* Initialize MMU. */
249 /* Initialize initial KASAN shadow map */
253 /* Parse boot parameters */
256 parse_bootparam(bp_start);
259 early_init_devtree(dtb_start);
262 #ifdef CONFIG_CMDLINE_BOOL
263 if (!command_line[0])
264 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
267 /* Early hook for platforms */
269 platform_init(bp_start);
273 * Initialize system. Setup memory and reserve regions.
277 extern char _stext[];
278 extern char _WindowVectors_text_start;
279 extern char _WindowVectors_text_end;
280 extern char _DebugInterruptVector_text_start;
281 extern char _DebugInterruptVector_text_end;
282 extern char _KernelExceptionVector_text_start;
283 extern char _KernelExceptionVector_text_end;
284 extern char _UserExceptionVector_text_start;
285 extern char _UserExceptionVector_text_end;
286 extern char _DoubleExceptionVector_text_start;
287 extern char _DoubleExceptionVector_text_end;
288 #if XCHAL_EXCM_LEVEL >= 2
289 extern char _Level2InterruptVector_text_start;
290 extern char _Level2InterruptVector_text_end;
292 #if XCHAL_EXCM_LEVEL >= 3
293 extern char _Level3InterruptVector_text_start;
294 extern char _Level3InterruptVector_text_end;
296 #if XCHAL_EXCM_LEVEL >= 4
297 extern char _Level4InterruptVector_text_start;
298 extern char _Level4InterruptVector_text_end;
300 #if XCHAL_EXCM_LEVEL >= 5
301 extern char _Level5InterruptVector_text_start;
302 extern char _Level5InterruptVector_text_end;
304 #if XCHAL_EXCM_LEVEL >= 6
305 extern char _Level6InterruptVector_text_start;
306 extern char _Level6InterruptVector_text_end;
309 extern char _SecondaryResetVector_text_start;
310 extern char _SecondaryResetVector_text_end;
313 static inline int __init_memblock mem_reserve(unsigned long start,
316 return memblock_reserve(start, end - start);
319 void __init setup_arch(char **cmdline_p)
321 pr_info("config ID: %08x:%08x\n",
322 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
323 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
324 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
325 pr_info("built for config ID: %08x:%08x\n",
326 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
328 *cmdline_p = command_line;
329 platform_setup(cmdline_p);
330 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
332 /* Reserve some memory regions */
334 #ifdef CONFIG_BLK_DEV_INITRD
335 if (initrd_start < initrd_end) {
336 initrd_is_mapped = mem_reserve(__pa(initrd_start),
337 __pa(initrd_end)) == 0;
338 initrd_below_start_ok = 1;
344 mem_reserve(__pa(_stext), __pa(_end));
346 #ifdef CONFIG_VECTORS_OFFSET
347 mem_reserve(__pa(&_WindowVectors_text_start),
348 __pa(&_WindowVectors_text_end));
350 mem_reserve(__pa(&_DebugInterruptVector_text_start),
351 __pa(&_DebugInterruptVector_text_end));
353 mem_reserve(__pa(&_KernelExceptionVector_text_start),
354 __pa(&_KernelExceptionVector_text_end));
356 mem_reserve(__pa(&_UserExceptionVector_text_start),
357 __pa(&_UserExceptionVector_text_end));
359 mem_reserve(__pa(&_DoubleExceptionVector_text_start),
360 __pa(&_DoubleExceptionVector_text_end));
362 #if XCHAL_EXCM_LEVEL >= 2
363 mem_reserve(__pa(&_Level2InterruptVector_text_start),
364 __pa(&_Level2InterruptVector_text_end));
366 #if XCHAL_EXCM_LEVEL >= 3
367 mem_reserve(__pa(&_Level3InterruptVector_text_start),
368 __pa(&_Level3InterruptVector_text_end));
370 #if XCHAL_EXCM_LEVEL >= 4
371 mem_reserve(__pa(&_Level4InterruptVector_text_start),
372 __pa(&_Level4InterruptVector_text_end));
374 #if XCHAL_EXCM_LEVEL >= 5
375 mem_reserve(__pa(&_Level5InterruptVector_text_start),
376 __pa(&_Level5InterruptVector_text_end));
378 #if XCHAL_EXCM_LEVEL >= 6
379 mem_reserve(__pa(&_Level6InterruptVector_text_start),
380 __pa(&_Level6InterruptVector_text_end));
383 #endif /* CONFIG_VECTORS_OFFSET */
386 mem_reserve(__pa(&_SecondaryResetVector_text_start),
387 __pa(&_SecondaryResetVector_text_end));
392 unflatten_and_copy_device_tree();
402 # if defined(CONFIG_VGA_CONSOLE)
403 conswitchp = &vga_con;
404 # elif defined(CONFIG_DUMMY_CONSOLE)
405 conswitchp = &dummy_con;
410 static DEFINE_PER_CPU(struct cpu, cpu_data);
412 static int __init topology_init(void)
416 for_each_possible_cpu(i) {
417 struct cpu *cpu = &per_cpu(cpu_data, i);
418 cpu->hotpluggable = !!i;
419 register_cpu(cpu, i);
424 subsys_initcall(topology_init);
428 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
431 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
433 * Way 4 is not currently used by linux.
434 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
435 * Way 5 shall be flushed and way 6 shall be set to identity mapping
438 local_flush_tlb_all();
439 invalidate_page_directory();
440 #if XCHAL_HAVE_SPANNING_WAY
443 unsigned long vaddr = (unsigned long)cpu_reset;
444 unsigned long paddr = __pa(vaddr);
445 unsigned long tmpaddr = vaddr + SZ_512M;
446 unsigned long tmp0, tmp1, tmp2, tmp3;
449 * Find a place for the temporary mapping. It must not be
450 * in the same 512MB region with vaddr or paddr, otherwise
451 * there may be multihit exception either on entry to the
452 * temporary mapping, or on entry to the identity mapping.
453 * (512MB is the biggest page size supported by TLB.)
455 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
458 /* Invalidate mapping in the selected temporary area */
459 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
460 invalidate_itlb_entry(itlb_probe(tmpaddr));
461 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
462 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
465 * Map two consecutive pages starting at the physical address
466 * of this function to the temporary mapping area.
468 write_itlb_entry(__pte((paddr & PAGE_MASK) |
472 tmpaddr & PAGE_MASK);
473 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
477 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
479 /* Reinitialize TLB */
480 __asm__ __volatile__ ("movi %0, 1f\n\t"
486 * No literal, data or stack access
490 /* Initialize *tlbcfg */
492 "wsr %0, itlbcfg\n\t"
493 "wsr %0, dtlbcfg\n\t"
494 /* Invalidate TLB way 5 */
501 "addi %0, %0, -1\n\t"
503 /* Initialize TLB way 6 */
512 "addi %0, %0, -1\n\t"
514 /* Jump to identity mapping */
517 /* Complete way 6 initialization */
520 /* Invalidate temporary mapping */
525 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
527 : "a"(tmpaddr - vaddr),
529 "a"(SZ_128M), "a"(SZ_512M),
531 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
536 __asm__ __volatile__ ("movi a2, 0\n\t"
537 "wsr a2, icountlevel\n\t"
540 #if XCHAL_NUM_IBREAK > 0
541 "wsr a2, ibreakenable\n\t"
551 : "a" (XCHAL_RESET_VECTOR_VADDR)
557 void machine_restart(char * cmd)
562 void machine_halt(void)
568 void machine_power_off(void)
570 platform_power_off();
573 #ifdef CONFIG_PROC_FS
576 * Display some core information through /proc/cpuinfo.
580 c_show(struct seq_file *f, void *slot)
582 /* high-level stuff */
583 seq_printf(f, "CPU count\t: %u\n"
584 "CPU list\t: %*pbl\n"
585 "vendor_id\t: Tensilica\n"
586 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
587 "core ID\t\t: " XCHAL_CORE_ID "\n"
589 "config ID\t: %08x:%08x\n"
591 "cpu MHz\t\t: %lu.%02lu\n"
592 "bogomips\t: %lu.%02lu\n",
594 cpumask_pr_args(cpu_online_mask),
595 XCHAL_BUILD_UNIQUE_ID,
596 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
597 XCHAL_HAVE_BE ? "big" : "little",
599 (ccount_freq/10000) % 100,
600 loops_per_jiffy/(500000/HZ),
601 (loops_per_jiffy/(5000/HZ)) % 100);
602 seq_puts(f, "flags\t\t: "
612 #if XCHAL_HAVE_DENSITY
615 #if XCHAL_HAVE_BOOLEANS
624 #if XCHAL_HAVE_MINMAX
630 #if XCHAL_HAVE_CLAMPS
642 #if XCHAL_HAVE_MUL32_HIGH
648 #if XCHAL_HAVE_S32C1I
651 #if XCHAL_HAVE_EXCLUSIVE
657 seq_printf(f,"physical aregs\t: %d\n"
668 seq_printf(f,"num ints\t: %d\n"
672 "debug level\t: %d\n",
673 XCHAL_NUM_INTERRUPTS,
674 XCHAL_NUM_EXTINTERRUPTS,
680 seq_printf(f,"icache line size: %d\n"
681 "icache ways\t: %d\n"
682 "icache size\t: %d\n"
684 #if XCHAL_ICACHE_LINE_LOCKABLE
688 "dcache line size: %d\n"
689 "dcache ways\t: %d\n"
690 "dcache size\t: %d\n"
692 #if XCHAL_DCACHE_IS_WRITEBACK
695 #if XCHAL_DCACHE_LINE_LOCKABLE
699 XCHAL_ICACHE_LINESIZE,
702 XCHAL_DCACHE_LINESIZE,
710 * We show only CPU #0 info.
713 c_start(struct seq_file *f, loff_t *pos)
715 return (*pos == 0) ? (void *)1 : NULL;
719 c_next(struct seq_file *f, void *v, loff_t *pos)
725 c_stop(struct seq_file *f, void *v)
729 const struct seq_operations cpuinfo_op =
737 #endif /* CONFIG_PROC_FS */