2 * arch/xtensa/platform/xtavnet/include/platform/hardware.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2006 Tensilica Inc.
12 * This file contains the hardware configuration of the XTAVNET boards.
15 #include <asm/types.h>
17 #ifndef __XTENSA_XTAVNET_HARDWARE_H
18 #define __XTENSA_XTAVNET_HARDWARE_H
20 /* Interrupt configuration. */
22 #define PLATFORM_NR_IRQS 0
24 /* Default assignment of LX60 devices to external interrupts. */
26 #ifdef CONFIG_XTENSA_MX
27 #define DUART16552_INTNUM XCHAL_EXTINT3_NUM
28 #define OETH_IRQ XCHAL_EXTINT4_NUM
29 #define C67X00_IRQ XCHAL_EXTINT8_NUM
31 #define DUART16552_INTNUM XCHAL_EXTINT0_NUM
32 #define OETH_IRQ XCHAL_EXTINT1_NUM
33 #define C67X00_IRQ XCHAL_EXTINT5_NUM
37 * Device addresses and parameters.
41 #define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020)
44 #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000)
45 /* Clock frequency in Hz (read-only): */
46 #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04)
47 /* Setting of 8 DIP switches: */
48 #define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C)
49 /* Software reset (write 0xdead): */
50 #define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10)
52 /* OpenCores Ethernet controller: */
53 /* regs + RX/TX descriptors */
54 #define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000)
55 #define OETH_REGS_SIZE 0x1000
56 #define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000)
58 /* 5*rx buffs + 5*tx buffs */
59 #define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600)
61 #define C67X00_PADDR (XCHAL_KIO_PADDR + 0x0D0D0000)
62 #define C67X00_SIZE 0x10
64 #endif /* __XTENSA_XTAVNET_HARDWARE_H */