1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
49 /* board IDs by feature in alphabetical order */
58 /* board IDs for specific chipsets in alphabetical order */
65 board_ahci_sb700, /* for SB700 and SB800 */
69 * board IDs for Intel chipsets that support more than 6 ports
70 * *and* end up needing the PCS quirk.
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static void ahci_remove_one(struct pci_dev *dev);
83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88 static bool is_mcp89_apple(struct pci_dev *pdev);
89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
92 static int ahci_pci_device_runtime_suspend(struct device *dev);
93 static int ahci_pci_device_runtime_resume(struct device *dev);
94 #ifdef CONFIG_PM_SLEEP
95 static int ahci_pci_device_suspend(struct device *dev);
96 static int ahci_pci_device_resume(struct device *dev);
98 #endif /* CONFIG_PM */
100 static struct scsi_host_template ahci_sht = {
104 static struct ata_port_operations ahci_vt8251_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_vt8251_hardreset,
109 static struct ata_port_operations ahci_p5wdh_ops = {
110 .inherits = &ahci_ops,
111 .hardreset = ahci_p5wdh_hardreset,
114 static struct ata_port_operations ahci_avn_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_avn_hardreset,
119 static const struct ata_port_info ahci_port_info[] = {
122 .flags = AHCI_FLAG_COMMON,
123 .pio_mask = ATA_PIO4,
124 .udma_mask = ATA_UDMA6,
125 .port_ops = &ahci_ops,
127 [board_ahci_ign_iferr] = {
128 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_mobile] = {
135 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
141 [board_ahci_nomsi] = {
142 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
148 [board_ahci_noncq] = {
149 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
150 .flags = AHCI_FLAG_COMMON,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
155 [board_ahci_nosntf] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
162 [board_ahci_yes_fbs] = {
163 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_avn_ops,
176 [board_ahci_mcp65] = {
177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
179 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
184 [board_ahci_mcp77] = {
185 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_ops,
191 [board_ahci_mcp89] = {
192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
199 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
200 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
201 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_ops,
206 [board_ahci_sb600] = {
207 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
208 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
209 AHCI_HFLAG_32BIT_ONLY),
210 .flags = AHCI_FLAG_COMMON,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_pmp_retry_srst_ops,
215 [board_ahci_sb700] = { /* for SB700 and SB800 */
216 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
217 .flags = AHCI_FLAG_COMMON,
218 .pio_mask = ATA_PIO4,
219 .udma_mask = ATA_UDMA6,
220 .port_ops = &ahci_pmp_retry_srst_ops,
222 [board_ahci_vt8251] = {
223 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
224 .flags = AHCI_FLAG_COMMON,
225 .pio_mask = ATA_PIO4,
226 .udma_mask = ATA_UDMA6,
227 .port_ops = &ahci_vt8251_ops,
229 [board_ahci_pcs7] = {
230 .flags = AHCI_FLAG_COMMON,
231 .pio_mask = ATA_PIO4,
232 .udma_mask = ATA_UDMA6,
233 .port_ops = &ahci_ops,
237 static const struct pci_device_id ahci_pci_tbl[] = {
239 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
240 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
241 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
242 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
243 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
244 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
245 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
246 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
247 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
248 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
249 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
250 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
251 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
252 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
253 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
254 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
256 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
257 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
258 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
259 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
263 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
265 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
266 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
267 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
268 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
269 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
270 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
271 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
272 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
273 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
274 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
275 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
276 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
277 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
278 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
300 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
301 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
302 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
303 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
304 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
305 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
306 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
307 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
308 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
309 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
310 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
311 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
312 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
313 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
314 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
315 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
316 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
317 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
319 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
321 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
322 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
323 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
324 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
325 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
326 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
327 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
329 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
330 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
331 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
332 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
333 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
334 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
335 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
336 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
338 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
343 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
344 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
346 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
347 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
353 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
354 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
356 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
357 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
358 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
359 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
360 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
361 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
362 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
363 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
364 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
365 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
366 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
367 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
368 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
369 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
370 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
371 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
372 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
373 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
374 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
375 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
376 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
377 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
378 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
379 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
380 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
381 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
382 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
384 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
387 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
389 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
390 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
391 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
392 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
393 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
394 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
395 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
396 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
397 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
398 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
399 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
401 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
402 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
403 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
404 /* JMicron 362B and 362C have an AHCI function with IDE class code */
405 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
406 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
407 /* May need to update quirk_jmicron_async_suspend() for additions */
410 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
411 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
412 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
413 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
414 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
415 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
416 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
419 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
420 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
421 /* AMD is using RAID class only for ahci controllers */
422 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
423 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
426 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
427 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
430 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
437 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
438 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
461 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
462 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
463 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
464 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
465 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
466 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
502 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
508 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
509 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
510 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
511 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
512 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
513 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
516 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
517 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
518 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
520 /* ST Microelectronics */
521 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
524 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
525 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
527 .class = PCI_CLASS_STORAGE_SATA_AHCI,
528 .class_mask = 0xffffff,
529 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
531 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
532 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
533 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
534 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
536 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
538 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
540 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
542 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
544 .driver_data = board_ahci_yes_fbs },
545 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
546 .driver_data = board_ahci_yes_fbs },
547 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
548 .driver_data = board_ahci_yes_fbs },
549 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
550 .driver_data = board_ahci_yes_fbs },
551 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
552 .driver_data = board_ahci_yes_fbs },
553 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
554 .driver_data = board_ahci_yes_fbs },
557 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
558 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
561 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
562 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
563 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
564 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
565 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
566 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
569 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
570 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
572 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
573 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
576 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
578 /* Generic, PCI class code for AHCI */
579 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
580 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
582 { } /* terminate list */
585 static const struct dev_pm_ops ahci_pci_pm_ops = {
586 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
587 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
588 ahci_pci_device_runtime_resume, NULL)
591 static struct pci_driver ahci_pci_driver = {
593 .id_table = ahci_pci_tbl,
594 .probe = ahci_init_one,
595 .remove = ahci_remove_one,
597 .pm = &ahci_pci_pm_ops,
601 #if IS_ENABLED(CONFIG_PATA_MARVELL)
602 static int marvell_enable;
604 static int marvell_enable = 1;
606 module_param(marvell_enable, int, 0644);
607 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
609 static int mobile_lpm_policy = -1;
610 module_param(mobile_lpm_policy, int, 0644);
611 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
613 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
614 struct ahci_host_priv *hpriv)
616 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
617 dev_info(&pdev->dev, "JMB361 has only one port\n");
618 hpriv->force_port_map = 1;
622 * Temporary Marvell 6145 hack: PATA port presence
623 * is asserted through the standard AHCI port
624 * presence register, as bit 4 (counting from 0)
626 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
627 if (pdev->device == 0x6121)
628 hpriv->mask_port_map = 0x3;
630 hpriv->mask_port_map = 0xf;
632 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
635 ahci_save_initial_config(&pdev->dev, hpriv);
638 static void ahci_pci_init_controller(struct ata_host *host)
640 struct ahci_host_priv *hpriv = host->private_data;
641 struct pci_dev *pdev = to_pci_dev(host->dev);
642 void __iomem *port_mmio;
646 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
647 if (pdev->device == 0x6121)
651 port_mmio = __ahci_port_base(host, mv);
653 writel(0, port_mmio + PORT_IRQ_MASK);
656 tmp = readl(port_mmio + PORT_IRQ_STAT);
657 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
659 writel(tmp, port_mmio + PORT_IRQ_STAT);
662 ahci_init_controller(host);
665 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
666 unsigned long deadline)
668 struct ata_port *ap = link->ap;
669 struct ahci_host_priv *hpriv = ap->host->private_data;
675 hpriv->stop_engine(ap);
677 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
678 deadline, &online, NULL);
680 hpriv->start_engine(ap);
682 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
684 /* vt8251 doesn't clear BSY on signature FIS reception,
685 * request follow-up softreset.
687 return online ? -EAGAIN : rc;
690 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
691 unsigned long deadline)
693 struct ata_port *ap = link->ap;
694 struct ahci_port_priv *pp = ap->private_data;
695 struct ahci_host_priv *hpriv = ap->host->private_data;
696 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
697 struct ata_taskfile tf;
701 hpriv->stop_engine(ap);
703 /* clear D2H reception area to properly wait for D2H FIS */
704 ata_tf_init(link->device, &tf);
705 tf.command = ATA_BUSY;
706 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
708 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
709 deadline, &online, NULL);
711 hpriv->start_engine(ap);
713 /* The pseudo configuration device on SIMG4726 attached to
714 * ASUS P5W-DH Deluxe doesn't send signature FIS after
715 * hardreset if no device is attached to the first downstream
716 * port && the pseudo device locks up on SRST w/ PMP==0. To
717 * work around this, wait for !BSY only briefly. If BSY isn't
718 * cleared, perform CLO and proceed to IDENTIFY (achieved by
719 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
721 * Wait for two seconds. Devices attached to downstream port
722 * which can't process the following IDENTIFY after this will
723 * have to be reset again. For most cases, this should
724 * suffice while making probing snappish enough.
727 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
730 ahci_kick_engine(ap);
736 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
738 * It has been observed with some SSDs that the timing of events in the
739 * link synchronization phase can leave the port in a state that can not
740 * be recovered by a SATA-hard-reset alone. The failing signature is
741 * SStatus.DET stuck at 1 ("Device presence detected but Phy
742 * communication not established"). It was found that unloading and
743 * reloading the driver when this problem occurs allows the drive
744 * connection to be recovered (DET advanced to 0x3). The critical
745 * component of reloading the driver is that the port state machines are
746 * reset by bouncing "port enable" in the AHCI PCS configuration
747 * register. So, reproduce that effect by bouncing a port whenever we
748 * see DET==1 after a reset.
750 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
751 unsigned long deadline)
753 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
754 struct ata_port *ap = link->ap;
755 struct ahci_port_priv *pp = ap->private_data;
756 struct ahci_host_priv *hpriv = ap->host->private_data;
757 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
758 unsigned long tmo = deadline - jiffies;
759 struct ata_taskfile tf;
765 hpriv->stop_engine(ap);
767 for (i = 0; i < 2; i++) {
770 int port = ap->port_no;
771 struct ata_host *host = ap->host;
772 struct pci_dev *pdev = to_pci_dev(host->dev);
774 /* clear D2H reception area to properly wait for D2H FIS */
775 ata_tf_init(link->device, &tf);
776 tf.command = ATA_BUSY;
777 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
779 rc = sata_link_hardreset(link, timing, deadline, &online,
782 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
783 (sstatus & 0xf) != 1)
786 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
789 pci_read_config_word(pdev, 0x92, &val);
791 pci_write_config_word(pdev, 0x92, val);
792 ata_msleep(ap, 1000);
794 pci_write_config_word(pdev, 0x92, val);
798 hpriv->start_engine(ap);
801 *class = ahci_dev_classify(ap);
803 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
809 static void ahci_pci_disable_interrupts(struct ata_host *host)
811 struct ahci_host_priv *hpriv = host->private_data;
812 void __iomem *mmio = hpriv->mmio;
815 /* AHCI spec rev1.1 section 8.3.3:
816 * Software must disable interrupts prior to requesting a
817 * transition of the HBA to D3 state.
819 ctl = readl(mmio + HOST_CTL);
821 writel(ctl, mmio + HOST_CTL);
822 readl(mmio + HOST_CTL); /* flush */
825 static int ahci_pci_device_runtime_suspend(struct device *dev)
827 struct pci_dev *pdev = to_pci_dev(dev);
828 struct ata_host *host = pci_get_drvdata(pdev);
830 ahci_pci_disable_interrupts(host);
834 static int ahci_pci_device_runtime_resume(struct device *dev)
836 struct pci_dev *pdev = to_pci_dev(dev);
837 struct ata_host *host = pci_get_drvdata(pdev);
840 rc = ahci_reset_controller(host);
843 ahci_pci_init_controller(host);
847 #ifdef CONFIG_PM_SLEEP
848 static int ahci_pci_device_suspend(struct device *dev)
850 struct pci_dev *pdev = to_pci_dev(dev);
851 struct ata_host *host = pci_get_drvdata(pdev);
852 struct ahci_host_priv *hpriv = host->private_data;
854 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
856 "BIOS update required for suspend/resume\n");
860 ahci_pci_disable_interrupts(host);
861 return ata_host_suspend(host, PMSG_SUSPEND);
864 static int ahci_pci_device_resume(struct device *dev)
866 struct pci_dev *pdev = to_pci_dev(dev);
867 struct ata_host *host = pci_get_drvdata(pdev);
870 /* Apple BIOS helpfully mangles the registers on resume */
871 if (is_mcp89_apple(pdev))
872 ahci_mcp89_apple_enable(pdev);
874 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
875 rc = ahci_reset_controller(host);
879 ahci_pci_init_controller(host);
882 ata_host_resume(host);
888 #endif /* CONFIG_PM */
890 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
892 const int dma_bits = using_dac ? 64 : 32;
896 * If the device fixup already set the dma_mask to some non-standard
897 * value, don't extend it here. This happens on STA2X11, for example.
899 * XXX: manipulating the DMA mask from platform code is completely
900 * bogus, platform code should use dev->bus_dma_mask instead..
902 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
905 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
907 dev_err(&pdev->dev, "DMA enable failed\n");
911 static void ahci_pci_print_info(struct ata_host *host)
913 struct pci_dev *pdev = to_pci_dev(host->dev);
917 pci_read_config_word(pdev, 0x0a, &cc);
918 if (cc == PCI_CLASS_STORAGE_IDE)
920 else if (cc == PCI_CLASS_STORAGE_SATA)
922 else if (cc == PCI_CLASS_STORAGE_RAID)
927 ahci_print_info(host, scc_s);
930 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
931 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
932 * support PMP and the 4726 either directly exports the device
933 * attached to the first downstream port or acts as a hardware storage
934 * controller and emulate a single ATA device (can be RAID 0/1 or some
935 * other configuration).
937 * When there's no device attached to the first downstream port of the
938 * 4726, "Config Disk" appears, which is a pseudo ATA device to
939 * configure the 4726. However, ATA emulation of the device is very
940 * lame. It doesn't send signature D2H Reg FIS after the initial
941 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
943 * The following function works around the problem by always using
944 * hardreset on the port and not depending on receiving signature FIS
945 * afterward. If signature FIS isn't received soon, ATA class is
946 * assumed without follow-up softreset.
948 static void ahci_p5wdh_workaround(struct ata_host *host)
950 static const struct dmi_system_id sysids[] = {
952 .ident = "P5W DH Deluxe",
954 DMI_MATCH(DMI_SYS_VENDOR,
955 "ASUSTEK COMPUTER INC"),
956 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
961 struct pci_dev *pdev = to_pci_dev(host->dev);
963 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
964 dmi_check_system(sysids)) {
965 struct ata_port *ap = host->ports[1];
968 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
970 ap->ops = &ahci_p5wdh_ops;
971 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
976 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
977 * booting in BIOS compatibility mode. We restore the registers but not ID.
979 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
983 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
985 pci_read_config_dword(pdev, 0xf8, &val);
987 /* the following changes the device ID, but appears not to affect function */
988 /* val = (val & ~0xf0000000) | 0x80000000; */
989 pci_write_config_dword(pdev, 0xf8, val);
991 pci_read_config_dword(pdev, 0x54c, &val);
993 pci_write_config_dword(pdev, 0x54c, val);
995 pci_read_config_dword(pdev, 0x4a4, &val);
998 pci_write_config_dword(pdev, 0x4a4, val);
1000 pci_read_config_dword(pdev, 0x54c, &val);
1002 pci_write_config_dword(pdev, 0x54c, val);
1004 pci_read_config_dword(pdev, 0xf8, &val);
1005 val &= ~(1 << 0x1b);
1006 pci_write_config_dword(pdev, 0xf8, val);
1009 static bool is_mcp89_apple(struct pci_dev *pdev)
1011 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1012 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1013 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1014 pdev->subsystem_device == 0xcb89;
1017 /* only some SB600 ahci controllers can do 64bit DMA */
1018 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1020 static const struct dmi_system_id sysids[] = {
1022 * The oldest version known to be broken is 0901 and
1023 * working is 1501 which was released on 2007-10-26.
1024 * Enable 64bit DMA on 1501 and anything newer.
1026 * Please read bko#9412 for more info.
1029 .ident = "ASUS M2A-VM",
1031 DMI_MATCH(DMI_BOARD_VENDOR,
1032 "ASUSTeK Computer INC."),
1033 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1035 .driver_data = "20071026", /* yyyymmdd */
1038 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1039 * support 64bit DMA.
1041 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1042 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1043 * This spelling mistake was fixed in BIOS version 1.5, so
1044 * 1.5 and later have the Manufacturer as
1045 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1046 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1048 * BIOS versions earlier than 1.9 had a Board Product Name
1049 * DMI field of "MS-7376". This was changed to be
1050 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1051 * match on DMI_BOARD_NAME of "MS-7376".
1054 .ident = "MSI K9A2 Platinum",
1056 DMI_MATCH(DMI_BOARD_VENDOR,
1057 "MICRO-STAR INTER"),
1058 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1062 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1065 * This board also had the typo mentioned above in the
1066 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1067 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1070 .ident = "MSI K9AGM2",
1072 DMI_MATCH(DMI_BOARD_VENDOR,
1073 "MICRO-STAR INTER"),
1074 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1078 * All BIOS versions for the Asus M3A support 64bit DMA.
1079 * (all release versions from 0301 to 1206 were tested)
1082 .ident = "ASUS M3A",
1084 DMI_MATCH(DMI_BOARD_VENDOR,
1085 "ASUSTeK Computer INC."),
1086 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1091 const struct dmi_system_id *match;
1092 int year, month, date;
1095 match = dmi_first_match(sysids);
1096 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1100 if (!match->driver_data)
1103 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1104 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1106 if (strcmp(buf, match->driver_data) >= 0)
1109 dev_warn(&pdev->dev,
1110 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1116 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1120 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1122 static const struct dmi_system_id broken_systems[] = {
1124 .ident = "HP Compaq nx6310",
1126 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1127 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1129 /* PCI slot number of the controller */
1130 .driver_data = (void *)0x1FUL,
1133 .ident = "HP Compaq 6720s",
1135 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1136 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1138 /* PCI slot number of the controller */
1139 .driver_data = (void *)0x1FUL,
1142 { } /* terminate list */
1144 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1147 unsigned long slot = (unsigned long)dmi->driver_data;
1148 /* apply the quirk only to on-board controllers */
1149 return slot == PCI_SLOT(pdev->devfn);
1155 static bool ahci_broken_suspend(struct pci_dev *pdev)
1157 static const struct dmi_system_id sysids[] = {
1159 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1160 * to the harddisk doesn't become online after
1161 * resuming from STR. Warn and fail suspend.
1163 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1165 * Use dates instead of versions to match as HP is
1166 * apparently recycling both product and version
1169 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1174 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1175 DMI_MATCH(DMI_PRODUCT_NAME,
1176 "HP Pavilion dv4 Notebook PC"),
1178 .driver_data = "20090105", /* F.30 */
1183 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1184 DMI_MATCH(DMI_PRODUCT_NAME,
1185 "HP Pavilion dv5 Notebook PC"),
1187 .driver_data = "20090506", /* F.16 */
1192 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1193 DMI_MATCH(DMI_PRODUCT_NAME,
1194 "HP Pavilion dv6 Notebook PC"),
1196 .driver_data = "20090423", /* F.21 */
1201 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1202 DMI_MATCH(DMI_PRODUCT_NAME,
1203 "HP HDX18 Notebook PC"),
1205 .driver_data = "20090430", /* F.23 */
1208 * Acer eMachines G725 has the same problem. BIOS
1209 * V1.03 is known to be broken. V3.04 is known to
1210 * work. Between, there are V1.06, V2.06 and V3.03
1211 * that we don't have much idea about. For now,
1212 * blacklist anything older than V3.04.
1214 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1219 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1220 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1222 .driver_data = "20091216", /* V3.04 */
1224 { } /* terminate list */
1226 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1227 int year, month, date;
1230 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1233 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1234 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1236 return strcmp(buf, dmi->driver_data) < 0;
1239 static bool ahci_broken_lpm(struct pci_dev *pdev)
1241 static const struct dmi_system_id sysids[] = {
1242 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1245 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1246 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1248 .driver_data = "20180406", /* 1.31 */
1252 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1253 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1255 .driver_data = "20180420", /* 1.28 */
1259 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1260 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1262 .driver_data = "20180315", /* 1.33 */
1266 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1267 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1270 * Note date based on release notes, 2.35 has been
1271 * reported to be good, but I've been unable to get
1272 * a hold of the reporter to get the DMI BIOS date.
1275 .driver_data = "20180310", /* 2.35 */
1277 { } /* terminate list */
1279 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1280 int year, month, date;
1286 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1287 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1289 return strcmp(buf, dmi->driver_data) < 0;
1292 static bool ahci_broken_online(struct pci_dev *pdev)
1294 #define ENCODE_BUSDEVFN(bus, slot, func) \
1295 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1296 static const struct dmi_system_id sysids[] = {
1298 * There are several gigabyte boards which use
1299 * SIMG5723s configured as hardware RAID. Certain
1300 * 5723 firmware revisions shipped there keep the link
1301 * online but fail to answer properly to SRST or
1302 * IDENTIFY when no device is attached downstream
1303 * causing libata to retry quite a few times leading
1304 * to excessive detection delay.
1306 * As these firmwares respond to the second reset try
1307 * with invalid device signature, considering unknown
1308 * sig as offline works around the problem acceptably.
1311 .ident = "EP45-DQ6",
1313 DMI_MATCH(DMI_BOARD_VENDOR,
1314 "Gigabyte Technology Co., Ltd."),
1315 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1317 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1320 .ident = "EP45-DS5",
1322 DMI_MATCH(DMI_BOARD_VENDOR,
1323 "Gigabyte Technology Co., Ltd."),
1324 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1326 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1328 { } /* terminate list */
1330 #undef ENCODE_BUSDEVFN
1331 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1337 val = (unsigned long)dmi->driver_data;
1339 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1342 static bool ahci_broken_devslp(struct pci_dev *pdev)
1344 /* device with broken DEVSLP but still showing SDS capability */
1345 static const struct pci_device_id ids[] = {
1346 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1350 return pci_match_id(ids, pdev);
1353 #ifdef CONFIG_ATA_ACPI
1354 static void ahci_gtf_filter_workaround(struct ata_host *host)
1356 static const struct dmi_system_id sysids[] = {
1358 * Aspire 3810T issues a bunch of SATA enable commands
1359 * via _GTF including an invalid one and one which is
1360 * rejected by the device. Among the successful ones
1361 * is FPDMA non-zero offset enable which when enabled
1362 * only on the drive side leads to NCQ command
1363 * failures. Filter it out.
1366 .ident = "Aspire 3810T",
1368 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1369 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1371 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1375 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1376 unsigned int filter;
1382 filter = (unsigned long)dmi->driver_data;
1383 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1384 filter, dmi->ident);
1386 for (i = 0; i < host->n_ports; i++) {
1387 struct ata_port *ap = host->ports[i];
1388 struct ata_link *link;
1389 struct ata_device *dev;
1391 ata_for_each_link(link, ap, EDGE)
1392 ata_for_each_dev(dev, link, ALL)
1393 dev->gtf_filter |= filter;
1397 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1402 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1403 * as DUMMY, or detected but eventually get a "link down" and never get up
1404 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1405 * port_map may hold a value of 0x00.
1407 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1408 * and can significantly reduce the occurrence of the problem.
1410 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1412 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1413 struct pci_dev *pdev)
1415 static const struct dmi_system_id sysids[] = {
1417 .ident = "Acer Switch Alpha 12",
1419 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1420 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1426 if (dmi_check_system(sysids)) {
1427 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1428 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1429 hpriv->port_map = 0x7;
1430 hpriv->cap = 0xC734FF02;
1437 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1438 * Workaround is to make sure all pending IRQs are served before leaving
1441 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1443 struct ata_host *host = dev_instance;
1444 struct ahci_host_priv *hpriv;
1445 unsigned int rc = 0;
1447 u32 irq_stat, irq_masked;
1448 unsigned int handled = 1;
1451 hpriv = host->private_data;
1453 irq_stat = readl(mmio + HOST_IRQ_STAT);
1458 irq_masked = irq_stat & hpriv->port_map;
1459 spin_lock(&host->lock);
1460 rc = ahci_handle_port_intr(host, irq_masked);
1463 writel(irq_stat, mmio + HOST_IRQ_STAT);
1464 irq_stat = readl(mmio + HOST_IRQ_STAT);
1465 spin_unlock(&host->lock);
1469 return IRQ_RETVAL(handled);
1473 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1474 struct ahci_host_priv *hpriv)
1480 * Check if this device might have remapped nvme devices.
1482 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1483 pci_resource_len(pdev, bar) < SZ_512K ||
1484 bar != AHCI_PCI_BAR_STANDARD ||
1485 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1488 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1489 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1490 if ((cap & (1 << i)) == 0)
1492 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1493 != PCI_CLASS_STORAGE_EXPRESS)
1496 /* We've found a remapped device */
1503 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1504 dev_warn(&pdev->dev,
1505 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1508 * Don't rely on the msi-x capability in the remap case,
1509 * share the legacy interrupt across ahci and remapped devices.
1511 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1514 static int ahci_get_irq_vector(struct ata_host *host, int port)
1516 return pci_irq_vector(to_pci_dev(host->dev), port);
1519 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1520 struct ahci_host_priv *hpriv)
1524 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1528 * If number of MSIs is less than number of ports then Sharing Last
1529 * Message mode could be enforced. In this case assume that advantage
1530 * of multipe MSIs is negated and use single MSI mode instead.
1533 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1534 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1536 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1537 hpriv->get_irq_vector = ahci_get_irq_vector;
1538 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1543 * Fallback to single MSI mode if the controller
1544 * enforced MRSM mode.
1547 "ahci: MRSM is on, fallback to single MSI\n");
1548 pci_free_irq_vectors(pdev);
1553 * If the host is not capable of supporting per-port vectors, fall
1554 * back to single MSI before finally attempting single MSI-X.
1556 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1559 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1562 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1563 struct ahci_host_priv *hpriv)
1565 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1568 /* Ignore processing for non mobile platforms */
1569 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1572 /* user modified policy via module param */
1573 if (mobile_lpm_policy != -1) {
1574 policy = mobile_lpm_policy;
1579 if (policy > ATA_LPM_MED_POWER &&
1580 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1581 if (hpriv->cap & HOST_CAP_PART)
1582 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1583 else if (hpriv->cap & HOST_CAP_SSC)
1584 policy = ATA_LPM_MIN_POWER;
1589 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1590 ap->target_lpm_policy = policy;
1593 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1595 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1599 * Only apply the 6-port PCS quirk for known legacy platforms.
1601 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1603 if (((enum board_ids) id->driver_data) < board_ahci_pcs7)
1607 * port_map is determined from PORTS_IMPL PCI register which is
1608 * implemented as write or write-once register. If the register
1609 * isn't programmed, ahci automatically generates it from number
1610 * of ports, which is good enough for PCS programming. It is
1611 * otherwise expected that platform firmware enables the ports
1612 * before the OS boots.
1614 pci_read_config_word(pdev, PCS_6, &tmp16);
1615 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1616 tmp16 |= hpriv->port_map;
1617 pci_write_config_word(pdev, PCS_6, tmp16);
1621 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1623 unsigned int board_id = ent->driver_data;
1624 struct ata_port_info pi = ahci_port_info[board_id];
1625 const struct ata_port_info *ppi[] = { &pi, NULL };
1626 struct device *dev = &pdev->dev;
1627 struct ahci_host_priv *hpriv;
1628 struct ata_host *host;
1630 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1634 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1636 ata_print_version_once(&pdev->dev, DRV_VERSION);
1638 /* The AHCI driver can only drive the SATA ports, the PATA driver
1639 can drive them all so if both drivers are selected make sure
1640 AHCI stays out of the way */
1641 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1644 /* Apple BIOS on MCP89 prevents us using AHCI */
1645 if (is_mcp89_apple(pdev))
1646 ahci_mcp89_apple_enable(pdev);
1648 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1649 * At the moment, we can only use the AHCI mode. Let the users know
1650 * that for SAS drives they're out of luck.
1652 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1653 dev_info(&pdev->dev,
1654 "PDC42819 can only drive SATA devices with this driver\n");
1656 /* Some devices use non-standard BARs */
1657 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1658 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1659 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1660 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1661 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1662 if (pdev->device == 0xa01c)
1663 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1664 if (pdev->device == 0xa084)
1665 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1668 /* acquire resources */
1669 rc = pcim_enable_device(pdev);
1673 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1674 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1677 /* ICH6s share the same PCI ID for both piix and ahci
1678 * modes. Enabling ahci mode while MAP indicates
1679 * combined mode is a bad idea. Yield to ata_piix.
1681 pci_read_config_byte(pdev, ICH_MAP, &map);
1683 dev_info(&pdev->dev,
1684 "controller is in combined mode, can't enable AHCI mode\n");
1689 /* AHCI controllers often implement SFF compatible interface.
1690 * Grab all PCI BARs just in case.
1692 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1694 pcim_pin_device(pdev);
1698 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1701 hpriv->flags |= (unsigned long)pi.private_data;
1703 /* MCP65 revision A1 and A2 can't do MSI */
1704 if (board_id == board_ahci_mcp65 &&
1705 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1706 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1708 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1709 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1710 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1712 /* only some SB600s can do 64bit DMA */
1713 if (ahci_sb600_enable_64bit(pdev))
1714 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1716 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1718 /* detect remapped nvme devices */
1719 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1721 /* must set flag prior to save config in order to take effect */
1722 if (ahci_broken_devslp(pdev))
1723 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1726 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1727 hpriv->irq_handler = ahci_thunderx_irq_handler;
1730 /* save initial config */
1731 ahci_pci_save_initial_config(pdev, hpriv);
1734 * If platform firmware failed to enable ports, try to enable
1737 ahci_intel_pcs_quirk(pdev, hpriv);
1740 if (hpriv->cap & HOST_CAP_NCQ) {
1741 pi.flags |= ATA_FLAG_NCQ;
1743 * Auto-activate optimization is supposed to be
1744 * supported on all AHCI controllers indicating NCQ
1745 * capability, but it seems to be broken on some
1746 * chipsets including NVIDIAs.
1748 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1749 pi.flags |= ATA_FLAG_FPDMA_AA;
1752 * All AHCI controllers should be forward-compatible
1753 * with the new auxiliary field. This code should be
1754 * conditionalized if any buggy AHCI controllers are
1757 pi.flags |= ATA_FLAG_FPDMA_AUX;
1760 if (hpriv->cap & HOST_CAP_PMP)
1761 pi.flags |= ATA_FLAG_PMP;
1763 ahci_set_em_messages(hpriv, &pi);
1765 if (ahci_broken_system_poweroff(pdev)) {
1766 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1767 dev_info(&pdev->dev,
1768 "quirky BIOS, skipping spindown on poweroff\n");
1771 if (ahci_broken_lpm(pdev)) {
1772 pi.flags |= ATA_FLAG_NO_LPM;
1773 dev_warn(&pdev->dev,
1774 "BIOS update required for Link Power Management support\n");
1777 if (ahci_broken_suspend(pdev)) {
1778 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1779 dev_warn(&pdev->dev,
1780 "BIOS update required for suspend/resume\n");
1783 if (ahci_broken_online(pdev)) {
1784 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1785 dev_info(&pdev->dev,
1786 "online status unreliable, applying workaround\n");
1790 /* Acer SA5-271 workaround modifies private_data */
1791 acer_sa5_271_workaround(hpriv, pdev);
1793 /* CAP.NP sometimes indicate the index of the last enabled
1794 * port, at other times, that of the last possible port, so
1795 * determining the maximum port number requires looking at
1796 * both CAP.NP and port_map.
1798 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1800 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1803 host->private_data = hpriv;
1805 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1806 /* legacy intx interrupts */
1809 hpriv->irq = pci_irq_vector(pdev, 0);
1811 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1812 host->flags |= ATA_HOST_PARALLEL_SCAN;
1814 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1816 if (pi.flags & ATA_FLAG_EM)
1817 ahci_reset_em(host);
1819 for (i = 0; i < host->n_ports; i++) {
1820 struct ata_port *ap = host->ports[i];
1822 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1823 ata_port_pbar_desc(ap, ahci_pci_bar,
1824 0x100 + ap->port_no * 0x80, "port");
1826 /* set enclosure management message type */
1827 if (ap->flags & ATA_FLAG_EM)
1828 ap->em_message_type = hpriv->em_msg_type;
1830 ahci_update_initial_lpm_policy(ap, hpriv);
1832 /* disabled/not-implemented port */
1833 if (!(hpriv->port_map & (1 << i)))
1834 ap->ops = &ata_dummy_port_ops;
1837 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1838 ahci_p5wdh_workaround(host);
1840 /* apply gtf filter quirk */
1841 ahci_gtf_filter_workaround(host);
1843 /* initialize adapter */
1844 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1848 rc = ahci_reset_controller(host);
1852 ahci_pci_init_controller(host);
1853 ahci_pci_print_info(host);
1855 pci_set_master(pdev);
1857 rc = ahci_host_activate(host, &ahci_sht);
1861 pm_runtime_put_noidle(&pdev->dev);
1865 static void ahci_remove_one(struct pci_dev *pdev)
1867 pm_runtime_get_noresume(&pdev->dev);
1868 ata_pci_remove_one(pdev);
1871 module_pci_driver(ahci_pci_driver);
1873 MODULE_AUTHOR("Jeff Garzik");
1874 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1875 MODULE_LICENSE("GPL");
1876 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1877 MODULE_VERSION(DRV_VERSION);