2 * regmap based irq_chip
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/device.h>
14 #include <linux/export.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
24 struct regmap_irq_chip_data {
26 struct irq_chip irq_chip;
29 const struct regmap_irq_chip *chip;
32 struct irq_domain *domain;
38 unsigned int *status_buf;
39 unsigned int *mask_buf;
40 unsigned int *mask_buf_def;
41 unsigned int *wake_buf;
42 unsigned int *type_buf;
43 unsigned int *type_buf_def;
45 unsigned int irq_reg_stride;
46 unsigned int type_reg_stride;
50 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
53 return &data->chip->irqs[irq];
56 static void regmap_irq_lock(struct irq_data *data)
58 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
63 static void regmap_irq_sync_unlock(struct irq_data *data)
65 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
66 struct regmap *map = d->map;
71 if (d->chip->runtime_pm) {
72 ret = pm_runtime_get_sync(map->dev);
74 dev_err(map->dev, "IRQ sync failed to resume: %d\n",
79 * If there's been a change in the mask write it back to the
80 * hardware. We rely on the use of the regmap core cache to
81 * suppress pointless writes.
83 for (i = 0; i < d->chip->num_regs; i++) {
84 reg = d->chip->mask_base +
85 (i * map->reg_stride * d->irq_reg_stride);
86 if (d->chip->mask_invert) {
87 ret = regmap_update_bits(d->map, reg,
88 d->mask_buf_def[i], ~d->mask_buf[i]);
89 } else if (d->chip->unmask_base) {
90 /* set mask with mask_base register */
91 ret = regmap_update_bits(d->map, reg,
92 d->mask_buf_def[i], ~d->mask_buf[i]);
95 "Failed to sync unmasks in %x\n",
97 unmask_offset = d->chip->unmask_base -
99 /* clear mask with unmask_base register */
100 ret = regmap_update_bits(d->map,
105 ret = regmap_update_bits(d->map, reg,
106 d->mask_buf_def[i], d->mask_buf[i]);
109 dev_err(d->map->dev, "Failed to sync masks in %x\n",
112 reg = d->chip->wake_base +
113 (i * map->reg_stride * d->irq_reg_stride);
115 if (d->chip->wake_invert)
116 ret = regmap_update_bits(d->map, reg,
120 ret = regmap_update_bits(d->map, reg,
125 "Failed to sync wakes in %x: %d\n",
129 if (!d->chip->init_ack_masked)
132 * Ack all the masked interrupts unconditionally,
133 * OR if there is masked interrupt which hasn't been Acked,
134 * it'll be ignored in irq handler, then may introduce irq storm
136 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
137 reg = d->chip->ack_base +
138 (i * map->reg_stride * d->irq_reg_stride);
139 /* some chips ack by write 0 */
140 if (d->chip->ack_invert)
141 ret = regmap_write(map, reg, ~d->mask_buf[i]);
143 ret = regmap_write(map, reg, d->mask_buf[i]);
145 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
150 for (i = 0; i < d->chip->num_type_reg; i++) {
151 if (!d->type_buf_def[i])
153 reg = d->chip->type_base +
154 (i * map->reg_stride * d->type_reg_stride);
155 if (d->chip->type_invert)
156 ret = regmap_update_bits(d->map, reg,
157 d->type_buf_def[i], ~d->type_buf[i]);
159 ret = regmap_update_bits(d->map, reg,
160 d->type_buf_def[i], d->type_buf[i]);
162 dev_err(d->map->dev, "Failed to sync type in %x\n",
166 if (d->chip->runtime_pm)
167 pm_runtime_put(map->dev);
169 /* If we've changed our wakeup count propagate it to the parent */
170 if (d->wake_count < 0)
171 for (i = d->wake_count; i < 0; i++)
172 irq_set_irq_wake(d->irq, 0);
173 else if (d->wake_count > 0)
174 for (i = 0; i < d->wake_count; i++)
175 irq_set_irq_wake(d->irq, 1);
179 mutex_unlock(&d->lock);
182 static void regmap_irq_enable(struct irq_data *data)
184 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
185 struct regmap *map = d->map;
186 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
188 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
191 static void regmap_irq_disable(struct irq_data *data)
193 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
194 struct regmap *map = d->map;
195 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
197 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
200 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
202 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
203 struct regmap *map = d->map;
204 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
205 int reg = irq_data->type_reg_offset / map->reg_stride;
207 if (!(irq_data->type_rising_mask | irq_data->type_falling_mask))
210 d->type_buf[reg] &= ~(irq_data->type_falling_mask |
211 irq_data->type_rising_mask);
213 case IRQ_TYPE_EDGE_FALLING:
214 d->type_buf[reg] |= irq_data->type_falling_mask;
217 case IRQ_TYPE_EDGE_RISING:
218 d->type_buf[reg] |= irq_data->type_rising_mask;
221 case IRQ_TYPE_EDGE_BOTH:
222 d->type_buf[reg] |= (irq_data->type_falling_mask |
223 irq_data->type_rising_mask);
232 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
234 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
235 struct regmap *map = d->map;
236 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
240 d->wake_buf[irq_data->reg_offset / map->reg_stride]
245 d->wake_buf[irq_data->reg_offset / map->reg_stride]
253 static const struct irq_chip regmap_irq_chip = {
254 .irq_bus_lock = regmap_irq_lock,
255 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
256 .irq_disable = regmap_irq_disable,
257 .irq_enable = regmap_irq_enable,
258 .irq_set_type = regmap_irq_set_type,
259 .irq_set_wake = regmap_irq_set_wake,
262 static irqreturn_t regmap_irq_thread(int irq, void *d)
264 struct regmap_irq_chip_data *data = d;
265 const struct regmap_irq_chip *chip = data->chip;
266 struct regmap *map = data->map;
268 bool handled = false;
271 if (chip->handle_pre_irq)
272 chip->handle_pre_irq(chip->irq_drv_data);
274 if (chip->runtime_pm) {
275 ret = pm_runtime_get_sync(map->dev);
277 dev_err(map->dev, "IRQ thread failed to resume: %d\n",
279 pm_runtime_put(map->dev);
285 * Read in the statuses, using a single bulk read if possible
286 * in order to reduce the I/O overheads.
288 if (!map->use_single_read && map->reg_stride == 1 &&
289 data->irq_reg_stride == 1) {
290 u8 *buf8 = data->status_reg_buf;
291 u16 *buf16 = data->status_reg_buf;
292 u32 *buf32 = data->status_reg_buf;
294 BUG_ON(!data->status_reg_buf);
296 ret = regmap_bulk_read(map, chip->status_base,
297 data->status_reg_buf,
300 dev_err(map->dev, "Failed to read IRQ status: %d\n",
305 for (i = 0; i < data->chip->num_regs; i++) {
306 switch (map->format.val_bytes) {
308 data->status_buf[i] = buf8[i];
311 data->status_buf[i] = buf16[i];
314 data->status_buf[i] = buf32[i];
323 for (i = 0; i < data->chip->num_regs; i++) {
324 ret = regmap_read(map, chip->status_base +
326 * data->irq_reg_stride),
327 &data->status_buf[i]);
331 "Failed to read IRQ status: %d\n",
333 if (chip->runtime_pm)
334 pm_runtime_put(map->dev);
341 * Ignore masked IRQs and ack if we need to; we ack early so
342 * there is no race between handling and acknowleding the
343 * interrupt. We assume that typically few of the interrupts
344 * will fire simultaneously so don't worry about overhead from
345 * doing a write per register.
347 for (i = 0; i < data->chip->num_regs; i++) {
348 data->status_buf[i] &= ~data->mask_buf[i];
350 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
351 reg = chip->ack_base +
352 (i * map->reg_stride * data->irq_reg_stride);
353 ret = regmap_write(map, reg, data->status_buf[i]);
355 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
360 for (i = 0; i < chip->num_irqs; i++) {
361 if (data->status_buf[chip->irqs[i].reg_offset /
362 map->reg_stride] & chip->irqs[i].mask) {
363 handle_nested_irq(irq_find_mapping(data->domain, i));
368 if (chip->runtime_pm)
369 pm_runtime_put(map->dev);
372 if (chip->handle_post_irq)
373 chip->handle_post_irq(chip->irq_drv_data);
381 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
384 struct regmap_irq_chip_data *data = h->host_data;
386 irq_set_chip_data(virq, data);
387 irq_set_chip(virq, &data->irq_chip);
388 irq_set_nested_thread(virq, 1);
389 irq_set_parent(virq, data->irq);
390 irq_set_noprobe(virq);
395 static const struct irq_domain_ops regmap_domain_ops = {
396 .map = regmap_irq_map,
397 .xlate = irq_domain_xlate_twocell,
401 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
403 * @map: The regmap for the device.
404 * @irq: The IRQ the device uses to signal interrupts.
405 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
406 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
407 * @chip: Configuration for the interrupt controller.
408 * @data: Runtime data structure for the controller, allocated on success.
410 * Returns 0 on success or an errno on failure.
412 * In order for this to be efficient the chip really should use a
413 * register cache. The chip driver is responsible for restoring the
414 * register values used by the IRQ controller over suspend and resume.
416 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
417 int irq_base, const struct regmap_irq_chip *chip,
418 struct regmap_irq_chip_data **data)
420 struct regmap_irq_chip_data *d;
426 if (chip->num_regs <= 0)
429 for (i = 0; i < chip->num_irqs; i++) {
430 if (chip->irqs[i].reg_offset % map->reg_stride)
432 if (chip->irqs[i].reg_offset / map->reg_stride >=
438 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
440 dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
446 d = kzalloc(sizeof(*d), GFP_KERNEL);
450 d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
455 d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
460 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
462 if (!d->mask_buf_def)
465 if (chip->wake_base) {
466 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
472 if (chip->num_type_reg) {
473 d->type_buf_def = kcalloc(chip->num_type_reg,
474 sizeof(unsigned int), GFP_KERNEL);
475 if (!d->type_buf_def)
478 d->type_buf = kcalloc(chip->num_type_reg, sizeof(unsigned int),
484 d->irq_chip = regmap_irq_chip;
485 d->irq_chip.name = chip->name;
489 d->irq_base = irq_base;
491 if (chip->irq_reg_stride)
492 d->irq_reg_stride = chip->irq_reg_stride;
494 d->irq_reg_stride = 1;
496 if (chip->type_reg_stride)
497 d->type_reg_stride = chip->type_reg_stride;
499 d->type_reg_stride = 1;
501 if (!map->use_single_read && map->reg_stride == 1 &&
502 d->irq_reg_stride == 1) {
503 d->status_reg_buf = kmalloc_array(chip->num_regs,
504 map->format.val_bytes,
506 if (!d->status_reg_buf)
510 mutex_init(&d->lock);
512 for (i = 0; i < chip->num_irqs; i++)
513 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
514 |= chip->irqs[i].mask;
516 /* Mask all the interrupts by default */
517 for (i = 0; i < chip->num_regs; i++) {
518 d->mask_buf[i] = d->mask_buf_def[i];
519 reg = chip->mask_base +
520 (i * map->reg_stride * d->irq_reg_stride);
521 if (chip->mask_invert)
522 ret = regmap_update_bits(map, reg,
523 d->mask_buf[i], ~d->mask_buf[i]);
524 else if (d->chip->unmask_base) {
525 unmask_offset = d->chip->unmask_base -
527 ret = regmap_update_bits(d->map,
532 ret = regmap_update_bits(map, reg,
533 d->mask_buf[i], d->mask_buf[i]);
535 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
540 if (!chip->init_ack_masked)
543 /* Ack masked but set interrupts */
544 reg = chip->status_base +
545 (i * map->reg_stride * d->irq_reg_stride);
546 ret = regmap_read(map, reg, &d->status_buf[i]);
548 dev_err(map->dev, "Failed to read IRQ status: %d\n",
553 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
554 reg = chip->ack_base +
555 (i * map->reg_stride * d->irq_reg_stride);
556 if (chip->ack_invert)
557 ret = regmap_write(map, reg,
558 ~(d->status_buf[i] & d->mask_buf[i]));
560 ret = regmap_write(map, reg,
561 d->status_buf[i] & d->mask_buf[i]);
563 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
570 /* Wake is disabled by default */
572 for (i = 0; i < chip->num_regs; i++) {
573 d->wake_buf[i] = d->mask_buf_def[i];
574 reg = chip->wake_base +
575 (i * map->reg_stride * d->irq_reg_stride);
577 if (chip->wake_invert)
578 ret = regmap_update_bits(map, reg,
582 ret = regmap_update_bits(map, reg,
586 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
593 if (chip->num_type_reg) {
594 for (i = 0; i < chip->num_irqs; i++) {
595 reg = chip->irqs[i].type_reg_offset / map->reg_stride;
596 d->type_buf_def[reg] |= chip->irqs[i].type_rising_mask |
597 chip->irqs[i].type_falling_mask;
599 for (i = 0; i < chip->num_type_reg; ++i) {
600 if (!d->type_buf_def[i])
603 reg = chip->type_base +
604 (i * map->reg_stride * d->type_reg_stride);
605 if (chip->type_invert)
606 ret = regmap_update_bits(map, reg,
607 d->type_buf_def[i], 0xFF);
609 ret = regmap_update_bits(map, reg,
610 d->type_buf_def[i], 0x0);
613 "Failed to set type in 0x%x: %x\n",
621 d->domain = irq_domain_add_legacy(map->dev->of_node,
622 chip->num_irqs, irq_base, 0,
623 ®map_domain_ops, d);
625 d->domain = irq_domain_add_linear(map->dev->of_node,
627 ®map_domain_ops, d);
629 dev_err(map->dev, "Failed to create IRQ domain\n");
634 ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
635 irq_flags | IRQF_ONESHOT,
638 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
639 irq, chip->name, ret);
648 /* Should really dispose of the domain but... */
651 kfree(d->type_buf_def);
653 kfree(d->mask_buf_def);
655 kfree(d->status_buf);
656 kfree(d->status_reg_buf);
660 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
663 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
665 * @irq: Primary IRQ for the device
666 * @d: ®map_irq_chip_data allocated by regmap_add_irq_chip()
668 * This function also disposes of all mapped IRQs on the chip.
670 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
680 /* Dispose all virtual irq from irq domain before removing it */
681 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
682 /* Ignore hwirq if holes in the IRQ list */
683 if (!d->chip->irqs[hwirq].mask)
687 * Find the virtual irq of hwirq on chip and if it is
688 * there then dispose it
690 virq = irq_find_mapping(d->domain, hwirq);
692 irq_dispose_mapping(virq);
695 irq_domain_remove(d->domain);
697 kfree(d->type_buf_def);
699 kfree(d->mask_buf_def);
701 kfree(d->status_reg_buf);
702 kfree(d->status_buf);
705 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
707 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
709 struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
711 regmap_del_irq_chip(d->irq, d);
714 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
717 struct regmap_irq_chip_data **r = res;
727 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
729 * @dev: The device pointer on which irq_chip belongs to.
730 * @map: The regmap for the device.
731 * @irq: The IRQ the device uses to signal interrupts
732 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
733 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
734 * @chip: Configuration for the interrupt controller.
735 * @data: Runtime data structure for the controller, allocated on success
737 * Returns 0 on success or an errno on failure.
739 * The ®map_irq_chip_data will be automatically released when the device is
742 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
743 int irq_flags, int irq_base,
744 const struct regmap_irq_chip *chip,
745 struct regmap_irq_chip_data **data)
747 struct regmap_irq_chip_data **ptr, *d;
750 ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
755 ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
763 devres_add(dev, ptr);
767 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
770 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
772 * @dev: Device for which which resource was allocated.
773 * @irq: Primary IRQ for the device.
774 * @data: ®map_irq_chip_data allocated by regmap_add_irq_chip().
776 * A resource managed version of regmap_del_irq_chip().
778 void devm_regmap_del_irq_chip(struct device *dev, int irq,
779 struct regmap_irq_chip_data *data)
783 WARN_ON(irq != data->irq);
784 rc = devres_release(dev, devm_regmap_irq_chip_release,
785 devm_regmap_irq_chip_match, data);
790 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
793 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
795 * @data: regmap irq controller to operate on.
797 * Useful for drivers to request their own IRQs.
799 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
801 WARN_ON(!data->irq_base);
802 return data->irq_base;
804 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
807 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
809 * @data: regmap irq controller to operate on.
810 * @irq: index of the interrupt requested in the chip IRQs.
812 * Useful for drivers to request their own IRQs.
814 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
816 /* Handle holes in the IRQ list */
817 if (!data->chip->irqs[irq].mask)
820 return irq_create_mapping(data->domain, irq);
822 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
825 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
827 * @data: regmap_irq controller to operate on.
829 * Useful for drivers to request their own IRQs and for integration
830 * with subsystems. For ease of integration NULL is accepted as a
831 * domain, allowing devices to just call this even if no domain is
834 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
841 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);