2 * Broadcom specific AMBA
3 * ChipCommon core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/bcm47xx_wdt.h>
14 #include <linux/export.h>
15 #include <linux/platform_device.h>
16 #include <linux/bcma/bcma.h>
18 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
20 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
24 value |= bcma_cc_read32(cc, offset) & ~mask;
25 bcma_cc_write32(cc, offset, value);
30 u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
32 if (cc->capabilities & BCMA_CC_CAP_PMU)
33 return bcma_pmu_get_alp_clock(cc);
37 EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
39 static bool bcma_core_cc_has_pmu_watchdog(struct bcma_drv_cc *cc)
41 struct bcma_bus *bus = cc->core->bus;
43 if (cc->capabilities & BCMA_CC_CAP_PMU) {
44 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573) {
45 WARN(bus->chipinfo.rev <= 1, "No watchdog available\n");
46 /* 53573B0 and 53573B1 have bugged PMU watchdog. It can
47 * be enabled but timer can't be bumped. Use CC one
58 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
60 struct bcma_bus *bus = cc->core->bus;
63 if (bcma_core_cc_has_pmu_watchdog(cc)) {
64 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
66 else if (cc->core->id.rev < 26)
69 nb = (cc->core->id.rev >= 37) ? 32 : 24;
79 static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
82 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
84 return bcma_chipco_watchdog_timer_set(cc, ticks);
87 static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
90 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
93 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
94 return ticks / cc->ticks_per_ms;
97 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
99 struct bcma_bus *bus = cc->core->bus;
101 if (cc->capabilities & BCMA_CC_CAP_PMU) {
102 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
103 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP
106 return bcma_chipco_get_alp_clock(cc) / 4000;
108 /* based on 32KHz ILP clock */
111 return bcma_chipco_get_alp_clock(cc) / 1000;
115 int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
117 struct bcma_bus *bus = cc->core->bus;
118 struct bcm47xx_wdt wdt = {};
119 struct platform_device *pdev;
121 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53573 &&
122 bus->chipinfo.rev <= 1) {
123 pr_debug("No watchdog on 53573A0 / 53573A1\n");
127 wdt.driver_data = cc;
128 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
129 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
131 bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
133 pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
137 return PTR_ERR(pdev);
144 static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
146 struct bcma_bus *bus = cc->core->bus;
148 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
149 case BCMA_CC_FLASHT_STSER:
150 case BCMA_CC_FLASHT_ATSER:
151 bcma_debug(bus, "Found serial flash\n");
152 bcma_sflash_init(cc);
154 case BCMA_CC_FLASHT_PARA:
155 bcma_debug(bus, "Found parallel flash\n");
156 bcma_pflash_init(cc);
159 bcma_err(bus, "Flash type not supported\n");
162 if (cc->core->id.rev == 38 ||
163 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
164 if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
165 bcma_debug(bus, "Found NAND flash\n");
166 bcma_nflash_init(cc);
171 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
173 struct bcma_bus *bus = cc->core->bus;
175 if (cc->early_setup_done)
178 spin_lock_init(&cc->gpio_lock);
180 if (cc->core->id.rev >= 11)
181 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
182 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
183 if (cc->core->id.rev >= 35)
184 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
186 if (cc->capabilities & BCMA_CC_CAP_PMU)
187 bcma_pmu_early_init(cc);
189 if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
190 bcma_chipco_serial_init(cc);
192 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
193 bcma_core_chipcommon_flash_detect(cc);
195 cc->early_setup_done = true;
198 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
206 bcma_core_chipcommon_early_init(cc);
208 if (cc->core->id.rev >= 20) {
209 u32 pullup = 0, pulldown = 0;
211 if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
216 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
217 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
220 if (cc->capabilities & BCMA_CC_CAP_PMU)
222 if (cc->capabilities & BCMA_CC_CAP_PCTL)
223 bcma_err(cc->core->bus, "Power control not implemented!\n");
225 if (cc->core->id.rev >= 16) {
226 if (cc->core->bus->sprom.leddc_on_time &&
227 cc->core->bus->sprom.leddc_off_time) {
228 leddc_on = cc->core->bus->sprom.leddc_on_time;
229 leddc_off = cc->core->bus->sprom.leddc_off_time;
231 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
232 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
233 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
235 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
237 cc->setup_done = true;
240 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
241 u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
245 maxt = bcma_chipco_watchdog_get_max_timer(cc);
246 if (bcma_core_cc_has_pmu_watchdog(cc)) {
249 else if (ticks > maxt)
251 bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
253 struct bcma_bus *bus = cc->core->bus;
255 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
256 bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
257 bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
258 bcma_core_set_clockmode(cc->core,
259 ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
264 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
269 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
271 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
274 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
276 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
279 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
281 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
284 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
289 spin_lock_irqsave(&cc->gpio_lock, flags);
290 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
291 spin_unlock_irqrestore(&cc->gpio_lock, flags);
295 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
297 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
302 spin_lock_irqsave(&cc->gpio_lock, flags);
303 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
304 spin_unlock_irqrestore(&cc->gpio_lock, flags);
308 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
311 * If the bit is set to 0, chipcommon controlls this GPIO,
312 * if the bit is set to 1, it is used by some part of the chip and not our code.
314 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
319 spin_lock_irqsave(&cc->gpio_lock, flags);
320 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
321 spin_unlock_irqrestore(&cc->gpio_lock, flags);
325 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
327 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
332 spin_lock_irqsave(&cc->gpio_lock, flags);
333 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
334 spin_unlock_irqrestore(&cc->gpio_lock, flags);
339 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
344 spin_lock_irqsave(&cc->gpio_lock, flags);
345 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
346 spin_unlock_irqrestore(&cc->gpio_lock, flags);
351 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
356 if (cc->core->id.rev < 20)
359 spin_lock_irqsave(&cc->gpio_lock, flags);
360 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
361 spin_unlock_irqrestore(&cc->gpio_lock, flags);
366 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
371 if (cc->core->id.rev < 20)
374 spin_lock_irqsave(&cc->gpio_lock, flags);
375 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
376 spin_unlock_irqrestore(&cc->gpio_lock, flags);
381 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
383 #if IS_BUILTIN(CONFIG_BCM47XX)
387 unsigned int ccrev = cc->core->id.rev;
388 struct bcma_serial_port *ports = cc->serial_ports;
390 if (ccrev >= 11 && ccrev != 15) {
391 baud_base = bcma_chipco_get_alp_clock(cc);
393 /* Turn off UART clock before switching clocksource. */
394 bcma_cc_write32(cc, BCMA_CC_CORECTL,
395 bcma_cc_read32(cc, BCMA_CC_CORECTL)
396 & ~BCMA_CC_CORECTL_UARTCLKEN);
398 /* Set the override bit so we don't divide it */
399 bcma_cc_write32(cc, BCMA_CC_CORECTL,
400 bcma_cc_read32(cc, BCMA_CC_CORECTL)
401 | BCMA_CC_CORECTL_UARTCLK0);
403 /* Re-enable the UART clock. */
404 bcma_cc_write32(cc, BCMA_CC_CORECTL,
405 bcma_cc_read32(cc, BCMA_CC_CORECTL)
406 | BCMA_CC_CORECTL_UARTCLKEN);
409 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n",
414 irq = bcma_core_irq(cc->core, 0);
416 /* Determine the registers of the UARTs */
417 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
418 for (i = 0; i < cc->nr_serial_ports; i++) {
419 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
422 ports[i].baud_base = baud_base;
423 ports[i].reg_shift = 0;
425 #endif /* CONFIG_BCM47XX */