2 * CCI cache coherent interconnect driver
4 * Copyright (C) 2013 ARM Ltd.
5 * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/arm-cci.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
25 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
28 /* Referenced read-only by the PMU driver; see drivers/perf/arm-cci.c */
29 void __iomem *cci_ctrl_base;
30 static unsigned long cci_ctrl_phys;
32 #ifdef CONFIG_ARM_CCI400_PORT_CTRL
35 unsigned int nb_ace_lite;
38 static const struct cci_nb_ports cci400_ports = {
43 #define CCI400_PORTS_DATA (&cci400_ports)
45 #define CCI400_PORTS_DATA (NULL)
48 static const struct of_device_id arm_cci_matches[] = {
49 #ifdef CONFIG_ARM_CCI400_COMMON
50 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 #ifdef CONFIG_ARM_CCI5xx_PMU
53 { .compatible = "arm,cci-500", },
54 { .compatible = "arm,cci-550", },
59 #define DRIVER_NAME "ARM-CCI"
61 static int cci_platform_probe(struct platform_device *pdev)
66 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
69 static struct platform_driver cci_platform_driver = {
72 .of_match_table = arm_cci_matches,
74 .probe = cci_platform_probe,
77 static int __init cci_platform_init(void)
79 return platform_driver_register(&cci_platform_driver);
82 #ifdef CONFIG_ARM_CCI400_PORT_CTRL
84 #define CCI_PORT_CTRL 0x0
85 #define CCI_CTRL_STATUS 0xc
87 #define CCI_ENABLE_SNOOP_REQ 0x1
88 #define CCI_ENABLE_DVM_REQ 0x2
89 #define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
91 enum cci_ace_port_type {
92 ACE_INVALID_PORT = 0x0,
100 enum cci_ace_port_type type;
101 struct device_node *dn;
104 static struct cci_ace_port *ports;
105 static unsigned int nb_cci_ports;
113 * Use the port MSB as valid flag, shift can be made dynamic
114 * by computing number of bits required for port indexes.
115 * Code disabling CCI cpu ports runs with D-cache invalidated
116 * and SCTLR bit clear so data accesses must be kept to a minimum
117 * to improve performance; for now shift is left static to
118 * avoid one more data access while disabling the CCI port.
120 #define PORT_VALID_SHIFT 31
121 #define PORT_VALID (0x1 << PORT_VALID_SHIFT)
123 static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
125 port->port = PORT_VALID | index;
129 static inline bool cpu_port_is_valid(struct cpu_port *port)
131 return !!(port->port & PORT_VALID);
134 static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
136 return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
139 static struct cpu_port cpu_port[NR_CPUS];
142 * __cci_ace_get_port - Function to retrieve the port index connected to
145 * @dn: device node of the device to look-up
149 * - CCI port index if success
150 * - -ENODEV if failure
152 static int __cci_ace_get_port(struct device_node *dn, int type)
156 struct device_node *cci_portn;
158 cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
159 for (i = 0; i < nb_cci_ports; i++) {
160 ace_match = ports[i].type == type;
161 if (ace_match && cci_portn == ports[i].dn)
167 int cci_ace_get_port(struct device_node *dn)
169 return __cci_ace_get_port(dn, ACE_LITE_PORT);
171 EXPORT_SYMBOL_GPL(cci_ace_get_port);
173 static void cci_ace_init_ports(void)
176 struct device_node *cpun;
179 * Port index look-up speeds up the function disabling ports by CPU,
180 * since the logical to port index mapping is done once and does
181 * not change after system boot.
182 * The stashed index array is initialized for all possible CPUs
185 for_each_possible_cpu(cpu) {
186 /* too early to use cpu->of_node */
187 cpun = of_get_cpu_node(cpu, NULL);
189 if (WARN(!cpun, "Missing cpu device node\n"))
192 port = __cci_ace_get_port(cpun, ACE_PORT);
196 init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
199 for_each_possible_cpu(cpu) {
200 WARN(!cpu_port_is_valid(&cpu_port[cpu]),
201 "CPU %u does not have an associated CCI port\n",
206 * Functions to enable/disable a CCI interconnect slave port
208 * They are called by low-level power management code to disable slave
209 * interfaces snoops and DVM broadcast.
210 * Since they may execute with cache data allocation disabled and
211 * after the caches have been cleaned and invalidated the functions provide
212 * no explicit locking since they may run with D-cache disabled, so normal
213 * cacheable kernel locks based on ldrex/strex may not work.
214 * Locking has to be provided by BSP implementations to ensure proper
219 * cci_port_control() - function to control a CCI port
221 * @port: index of the port to setup
222 * @enable: if true enables the port, if false disables it
224 static void notrace cci_port_control(unsigned int port, bool enable)
226 void __iomem *base = ports[port].base;
228 writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
230 * This function is called from power down procedures
231 * and must not execute any instruction that might
232 * cause the processor to be put in a quiescent state
233 * (eg wfi). Hence, cpu_relax() can not be added to this
234 * read loop to optimize power, since it might hide possibly
235 * disruptive operations.
237 while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
242 * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
245 * @mpidr: mpidr of the CPU whose CCI port should be disabled
247 * Disabling a CCI port for a CPU implies disabling the CCI port
248 * controlling that CPU cluster. Code disabling CPU CCI ports
249 * must make sure that the CPU running the code is the last active CPU
250 * in the cluster ie all other CPUs are quiescent in a low power state.
254 * -ENODEV on port look-up failure
256 int notrace cci_disable_port_by_cpu(u64 mpidr)
260 for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
261 is_valid = cpu_port_is_valid(&cpu_port[cpu]);
262 if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
263 cci_port_control(cpu_port[cpu].port, false);
269 EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
272 * cci_enable_port_for_self() - enable a CCI port for calling CPU
274 * Enabling a CCI port for the calling CPU implies enabling the CCI
275 * port controlling that CPU's cluster. Caller must make sure that the
276 * CPU running the code is the first active CPU in the cluster and all
277 * other CPUs are quiescent in a low power state or waiting for this CPU
278 * to complete the CCI initialization.
280 * Because this is called when the MMU is still off and with no stack,
281 * the code must be position independent and ideally rely on callee
282 * clobbered registers only. To achieve this we must code this function
283 * entirely in assembler.
285 * On success this returns with the proper CCI port enabled. In case of
286 * any failure this never returns as the inability to enable the CCI is
287 * fatal and there is no possible recovery at this stage.
289 asmlinkage void __naked cci_enable_port_for_self(void)
293 " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n"
294 " and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
297 " add r1, r1, r2 @ &cpu_port \n"
298 " add ip, r1, %[sizeof_cpu_port] \n"
300 /* Loop over the cpu_port array looking for a matching MPIDR */
301 "1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
302 " cmp r2, r0 @ compare MPIDR \n"
305 /* Found a match, now test port validity */
306 " ldr r3, [r1, %[offsetof_cpu_port_port]] \n"
307 " tst r3, #"__stringify(PORT_VALID)" \n"
310 /* no match, loop with the next cpu_port entry */
311 "2: add r1, r1, %[sizeof_struct_cpu_port] \n"
312 " cmp r1, ip @ done? \n"
315 /* CCI port not found -- cheaply try to stall this CPU */
316 "cci_port_not_found: \n"
319 " b cci_port_not_found \n"
321 /* Use matched port index to look up the corresponding ports entry */
322 "3: bic r3, r3, #"__stringify(PORT_VALID)" \n"
324 " ldmia r0, {r1, r2} \n"
325 " sub r1, r1, r0 @ virt - phys \n"
326 " ldr r0, [r0, r2] @ *(&ports) \n"
327 " mov r2, %[sizeof_struct_ace_port] \n"
328 " mla r0, r2, r3, r0 @ &ports[index] \n"
329 " sub r0, r0, r1 @ virt_to_phys() \n"
331 /* Enable the CCI port */
332 " ldr r0, [r0, %[offsetof_port_phys]] \n"
333 " mov r3, %[cci_enable_req]\n"
334 " str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
336 /* poll the status reg for completion */
339 " ldr r0, [r0, r1] @ cci_ctrl_base \n"
340 "4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
341 " tst r1, %[cci_control_status_bits] \n"
348 "5: .word cpu_port - . \n"
350 " .word ports - 6b \n"
351 "7: .word cci_ctrl_phys - . \n"
353 [sizeof_cpu_port] "i" (sizeof(cpu_port)),
354 [cci_enable_req] "i" cpu_to_le32(CCI_ENABLE_REQ),
355 [cci_control_status_bits] "i" cpu_to_le32(1),
357 [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
359 [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
361 [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
362 [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
363 [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
364 [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
370 * __cci_control_port_by_device() - function to control a CCI port by device
373 * @dn: device node pointer of the device whose CCI port should be
375 * @enable: if true enables the port, if false disables it
379 * -ENODEV on port look-up failure
381 int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
388 port = __cci_ace_get_port(dn, ACE_LITE_PORT);
389 if (WARN_ONCE(port < 0, "node %pOF ACE lite port look-up failure\n",
392 cci_port_control(port, enable);
395 EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
398 * __cci_control_port_by_index() - function to control a CCI port by port index
400 * @port: port index previously retrieved with cci_ace_get_port()
401 * @enable: if true enables the port, if false disables it
405 * -ENODEV on port index out of range
406 * -EPERM if operation carried out on an ACE PORT
408 int notrace __cci_control_port_by_index(u32 port, bool enable)
410 if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
413 * CCI control for ports connected to CPUS is extremely fragile
414 * and must be made to go through a specific and controlled
415 * interface (ie cci_disable_port_by_cpu(); control by general purpose
416 * indexing is therefore disabled for ACE ports.
418 if (ports[port].type == ACE_PORT)
421 cci_port_control(port, enable);
424 EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
426 static const struct of_device_id arm_cci_ctrl_if_matches[] = {
427 {.compatible = "arm,cci-400-ctrl-if", },
431 static int cci_probe_ports(struct device_node *np)
433 struct cci_nb_ports const *cci_config;
434 int ret, i, nb_ace = 0, nb_ace_lite = 0;
435 struct device_node *cp;
437 const char *match_str;
441 cci_config = of_match_node(arm_cci_matches, np)->data;
445 nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
447 ports = kcalloc(nb_cci_ports, sizeof(*ports), GFP_KERNEL);
451 for_each_available_child_of_node(np, cp) {
452 if (!of_match_node(arm_cci_ctrl_if_matches, cp))
455 i = nb_ace + nb_ace_lite;
457 if (i >= nb_cci_ports)
460 if (of_property_read_string(cp, "interface-type",
462 WARN(1, "node %pOF missing interface-type property\n",
466 is_ace = strcmp(match_str, "ace") == 0;
467 if (!is_ace && strcmp(match_str, "ace-lite")) {
468 WARN(1, "node %pOF containing invalid interface-type property, skipping it\n",
473 ret = of_address_to_resource(cp, 0, &res);
475 ports[i].base = ioremap(res.start, resource_size(&res));
476 ports[i].phys = res.start;
478 if (ret || !ports[i].base) {
479 WARN(1, "unable to ioremap CCI port %d\n", i);
484 if (WARN_ON(nb_ace >= cci_config->nb_ace))
486 ports[i].type = ACE_PORT;
489 if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
491 ports[i].type = ACE_LITE_PORT;
498 * If there is no CCI port that is under kernel control
499 * return early and report probe status.
501 if (!nb_ace && !nb_ace_lite)
504 /* initialize a stashed array of ACE ports to speed-up look-up */
505 cci_ace_init_ports();
508 * Multi-cluster systems may need this data when non-coherent, during
509 * cluster power-up/power-down. Make sure it reaches main memory.
511 sync_cache_w(&cci_ctrl_base);
512 sync_cache_w(&cci_ctrl_phys);
513 sync_cache_w(&ports);
514 sync_cache_w(&cpu_port);
515 __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
516 pr_info("ARM CCI driver probed\n");
520 #else /* !CONFIG_ARM_CCI400_PORT_CTRL */
521 static inline int cci_probe_ports(struct device_node *np)
525 #endif /* CONFIG_ARM_CCI400_PORT_CTRL */
527 static int cci_probe(void)
530 struct device_node *np;
533 np = of_find_matching_node(NULL, arm_cci_matches);
534 if (!of_device_is_available(np))
537 ret = of_address_to_resource(np, 0, &res);
539 cci_ctrl_base = ioremap(res.start, resource_size(&res));
540 cci_ctrl_phys = res.start;
542 if (ret || !cci_ctrl_base) {
543 WARN(1, "unable to ioremap CCI ctrl\n");
547 return cci_probe_ports(np);
550 static int cci_init_status = -EAGAIN;
551 static DEFINE_MUTEX(cci_probing);
553 static int cci_init(void)
555 if (cci_init_status != -EAGAIN)
556 return cci_init_status;
558 mutex_lock(&cci_probing);
559 if (cci_init_status == -EAGAIN)
560 cci_init_status = cci_probe();
561 mutex_unlock(&cci_probing);
562 return cci_init_status;
566 * To sort out early init calls ordering a helper function is provided to
567 * check if the CCI driver has beed initialized. Function check if the driver
568 * has been initialized, if not it calls the init function that probes
569 * the driver and updates the return value.
571 bool cci_probed(void)
573 return cci_init() == 0;
575 EXPORT_SYMBOL_GPL(cci_probed);
577 early_initcall(cci_init);
578 core_initcall(cci_platform_init);
579 MODULE_LICENSE("GPL");
580 MODULE_DESCRIPTION("ARM CCI support");