2 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/of_address.h>
24 #include <linux/of_platform.h>
25 #include <linux/slab.h>
26 #include <linux/iopoll.h>
28 #include <linux/platform_data/ti-sysc.h>
30 #include <dt-bindings/bus/ti-sysc.h>
32 #define MAX_MODULE_SOFTRESET_WAIT 10000
34 static const char * const reg_names[] = { "rev", "sysc", "syss", };
50 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
51 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
52 "opt5", "opt6", "opt7",
55 #define SYSC_IDLEMODE_MASK 3
56 #define SYSC_CLOCKACTIVITY_MASK 3
59 * struct sysc - TI sysc interconnect target module registers and capabilities
60 * @dev: struct device pointer
61 * @module_pa: physical address of the interconnect target module
62 * @module_size: size of the interconnect target module
63 * @module_va: virtual address of the interconnect target module
64 * @offsets: register offsets from module base
65 * @clocks: clocks used by the interconnect target module
66 * @clock_roles: clock role names for the found clocks
67 * @nr_clocks: number of clocks used by the interconnect target module
68 * @legacy_mode: configured for legacy mode if set
69 * @cap: interconnect target module capabilities
70 * @cfg: interconnect target module configuration
71 * @name: name if available
72 * @revision: interconnect target module revision
73 * @needs_resume: runtime resume needed on resume from suspend
79 void __iomem *module_va;
80 int offsets[SYSC_MAX_REGS];
81 struct ti_sysc_module_data *mdata;
83 const char **clock_roles;
85 struct reset_control *rsts;
86 const char *legacy_mode;
87 const struct sysc_capabilities *cap;
88 struct sysc_config cfg;
89 struct ti_sysc_cookie cookie;
94 bool child_needs_resume;
95 struct delayed_work idle_work;
98 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
101 static void sysc_write(struct sysc *ddata, int offset, u32 value)
103 writel_relaxed(value, ddata->module_va + offset);
106 static u32 sysc_read(struct sysc *ddata, int offset)
108 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
111 val = readw_relaxed(ddata->module_va + offset);
112 val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
117 return readl_relaxed(ddata->module_va + offset);
120 static bool sysc_opt_clks_needed(struct sysc *ddata)
122 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
125 static u32 sysc_read_revision(struct sysc *ddata)
127 int offset = ddata->offsets[SYSC_REVISION];
132 return sysc_read(ddata, offset);
135 static int sysc_add_named_clock_from_child(struct sysc *ddata,
137 const char *optfck_name)
139 struct device_node *np = ddata->dev->of_node;
140 struct device_node *child;
141 struct clk_lookup *cl;
150 /* Does the clock alias already exist? */
151 clock = of_clk_get_by_name(np, n);
152 if (!IS_ERR(clock)) {
158 child = of_get_next_available_child(np, NULL);
162 clock = devm_get_clk_from_child(ddata->dev, child, name);
164 return PTR_ERR(clock);
167 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
168 * limit for clk_get(). If cl ever needs to be freed, it should be done
169 * with clkdev_drop().
171 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
176 cl->dev_id = dev_name(ddata->dev);
185 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
187 const char *optfck_name;
190 if (ddata->nr_clocks < SYSC_OPTFCK0)
191 index = SYSC_OPTFCK0;
193 index = ddata->nr_clocks;
198 optfck_name = clock_names[index];
200 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
204 ddata->clock_roles[index] = optfck_name;
210 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
212 int error, i, index = -ENODEV;
214 if (!strncmp(clock_names[SYSC_FCK], name, 3))
216 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
220 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
221 if (!ddata->clocks[i]) {
229 dev_err(ddata->dev, "clock %s not added\n", name);
233 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
234 if (IS_ERR(ddata->clocks[index])) {
235 if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
238 dev_err(ddata->dev, "clock get error for %s: %li\n",
239 name, PTR_ERR(ddata->clocks[index]));
241 return PTR_ERR(ddata->clocks[index]);
244 error = clk_prepare(ddata->clocks[index]);
246 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
255 static int sysc_get_clocks(struct sysc *ddata)
257 struct device_node *np = ddata->dev->of_node;
258 struct property *prop;
260 int nr_fck = 0, nr_ick = 0, i, error = 0;
262 ddata->clock_roles = devm_kcalloc(ddata->dev,
264 sizeof(*ddata->clock_roles),
266 if (!ddata->clock_roles)
269 of_property_for_each_string(np, "clock-names", prop, name) {
270 if (!strncmp(clock_names[SYSC_FCK], name, 3))
272 if (!strncmp(clock_names[SYSC_ICK], name, 3))
274 ddata->clock_roles[ddata->nr_clocks] = name;
278 if (ddata->nr_clocks < 1)
281 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
282 error = sysc_init_ext_opt_clock(ddata, NULL);
287 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
288 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
293 if (nr_fck > 1 || nr_ick > 1) {
294 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
299 ddata->clocks = devm_kcalloc(ddata->dev,
300 ddata->nr_clocks, sizeof(*ddata->clocks),
305 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
306 const char *name = ddata->clock_roles[i];
311 error = sysc_get_one_clock(ddata, name);
312 if (error && error != -ENOENT)
319 static int sysc_enable_main_clocks(struct sysc *ddata)
327 for (i = 0; i < SYSC_OPTFCK0; i++) {
328 clock = ddata->clocks[i];
330 /* Main clocks may not have ick */
331 if (IS_ERR_OR_NULL(clock))
334 error = clk_enable(clock);
342 for (i--; i >= 0; i--) {
343 clock = ddata->clocks[i];
345 /* Main clocks may not have ick */
346 if (IS_ERR_OR_NULL(clock))
355 static void sysc_disable_main_clocks(struct sysc *ddata)
363 for (i = 0; i < SYSC_OPTFCK0; i++) {
364 clock = ddata->clocks[i];
365 if (IS_ERR_OR_NULL(clock))
372 static int sysc_enable_opt_clocks(struct sysc *ddata)
380 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
381 clock = ddata->clocks[i];
383 /* Assume no holes for opt clocks */
384 if (IS_ERR_OR_NULL(clock))
387 error = clk_enable(clock);
395 for (i--; i >= 0; i--) {
396 clock = ddata->clocks[i];
397 if (IS_ERR_OR_NULL(clock))
406 static void sysc_disable_opt_clocks(struct sysc *ddata)
414 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
415 clock = ddata->clocks[i];
417 /* Assume no holes for opt clocks */
418 if (IS_ERR_OR_NULL(clock))
426 * sysc_init_resets - init rstctrl reset line if configured
427 * @ddata: device driver data
429 * See sysc_rstctrl_reset_deassert().
431 static int sysc_init_resets(struct sysc *ddata)
434 devm_reset_control_array_get_optional_exclusive(ddata->dev);
435 if (IS_ERR(ddata->rsts))
436 return PTR_ERR(ddata->rsts);
442 * sysc_parse_and_check_child_range - parses module IO region from ranges
443 * @ddata: device driver data
445 * In general we only need rev, syss, and sysc registers and not the whole
446 * module range. But we do want the offsets for these registers from the
447 * module base. This allows us to check them against the legacy hwmod
448 * platform data. Let's also check the ranges are configured properly.
450 static int sysc_parse_and_check_child_range(struct sysc *ddata)
452 struct device_node *np = ddata->dev->of_node;
453 const __be32 *ranges;
454 u32 nr_addr, nr_size;
457 ranges = of_get_property(np, "ranges", &len);
459 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
464 len /= sizeof(*ranges);
467 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
472 error = of_property_read_u32(np, "#address-cells", &nr_addr);
476 error = of_property_read_u32(np, "#size-cells", &nr_size);
480 if (nr_addr != 1 || nr_size != 1) {
481 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
487 ddata->module_pa = of_translate_address(np, ranges++);
488 ddata->module_size = be32_to_cpup(ranges);
493 static struct device_node *stdout_path;
495 static void sysc_init_stdout_path(struct sysc *ddata)
497 struct device_node *np = NULL;
500 if (IS_ERR(stdout_path))
506 np = of_find_node_by_path("/chosen");
510 uart = of_get_property(np, "stdout-path", NULL);
514 np = of_find_node_by_path(uart);
523 stdout_path = ERR_PTR(-ENODEV);
526 static void sysc_check_quirk_stdout(struct sysc *ddata,
527 struct device_node *np)
529 sysc_init_stdout_path(ddata);
530 if (np != stdout_path)
533 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
534 SYSC_QUIRK_NO_RESET_ON_INIT;
538 * sysc_check_one_child - check child configuration
539 * @ddata: device driver data
540 * @np: child device node
542 * Let's avoid messy situations where we have new interconnect target
543 * node but children have "ti,hwmods". These belong to the interconnect
544 * target node and are managed by this driver.
546 static int sysc_check_one_child(struct sysc *ddata,
547 struct device_node *np)
551 name = of_get_property(np, "ti,hwmods", NULL);
553 dev_warn(ddata->dev, "really a child ti,hwmods property?");
555 sysc_check_quirk_stdout(ddata, np);
556 sysc_parse_dts_quirks(ddata, np, true);
561 static int sysc_check_children(struct sysc *ddata)
563 struct device_node *child;
566 for_each_child_of_node(ddata->dev->of_node, child) {
567 error = sysc_check_one_child(ddata, child);
576 * So far only I2C uses 16-bit read access with clockactivity with revision
577 * in two registers with stride of 4. We can detect this based on the rev
578 * register size to configure things far enough to be able to properly read
579 * the revision register.
581 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
583 if (resource_size(res) == 8)
584 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
588 * sysc_parse_one - parses the interconnect target module registers
589 * @ddata: device driver data
590 * @reg: register to parse
592 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
594 struct resource *res;
601 name = reg_names[reg];
607 res = platform_get_resource_byname(to_platform_device(ddata->dev),
608 IORESOURCE_MEM, name);
610 ddata->offsets[reg] = -ENODEV;
615 ddata->offsets[reg] = res->start - ddata->module_pa;
616 if (reg == SYSC_REVISION)
617 sysc_check_quirk_16bit(ddata, res);
622 static int sysc_parse_registers(struct sysc *ddata)
626 for (i = 0; i < SYSC_MAX_REGS; i++) {
627 error = sysc_parse_one(ddata, i);
636 * sysc_check_registers - check for misconfigured register overlaps
637 * @ddata: device driver data
639 static int sysc_check_registers(struct sysc *ddata)
641 int i, j, nr_regs = 0, nr_matches = 0;
643 for (i = 0; i < SYSC_MAX_REGS; i++) {
644 if (ddata->offsets[i] < 0)
647 if (ddata->offsets[i] > (ddata->module_size - 4)) {
648 dev_err(ddata->dev, "register outside module range");
653 for (j = 0; j < SYSC_MAX_REGS; j++) {
654 if (ddata->offsets[j] < 0)
657 if (ddata->offsets[i] == ddata->offsets[j])
663 if (nr_matches > nr_regs) {
664 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
665 nr_regs, nr_matches);
674 * syc_ioremap - ioremap register space for the interconnect target module
675 * @ddata: device driver data
677 * Note that the interconnect target module registers can be anywhere
678 * within the interconnect target module range. For example, SGX has
679 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
680 * has them at offset 0x1200 in the CPSW_WR child. Usually the
681 * the interconnect target module registers are at the beginning of
682 * the module range though.
684 static int sysc_ioremap(struct sysc *ddata)
688 if (ddata->offsets[SYSC_REVISION] < 0 &&
689 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
690 ddata->offsets[SYSC_SYSSTATUS] < 0) {
691 size = ddata->module_size;
693 size = max3(ddata->offsets[SYSC_REVISION],
694 ddata->offsets[SYSC_SYSCONFIG],
695 ddata->offsets[SYSC_SYSSTATUS]);
697 if ((size + sizeof(u32)) > ddata->module_size)
701 ddata->module_va = devm_ioremap(ddata->dev,
704 if (!ddata->module_va)
711 * sysc_map_and_check_registers - ioremap and check device registers
712 * @ddata: device driver data
714 static int sysc_map_and_check_registers(struct sysc *ddata)
718 error = sysc_parse_and_check_child_range(ddata);
722 error = sysc_check_children(ddata);
726 error = sysc_parse_registers(ddata);
730 error = sysc_ioremap(ddata);
734 error = sysc_check_registers(ddata);
742 * sysc_show_rev - read and show interconnect target module revision
743 * @bufp: buffer to print the information to
744 * @ddata: device driver data
746 static int sysc_show_rev(char *bufp, struct sysc *ddata)
750 if (ddata->offsets[SYSC_REVISION] < 0)
751 return sprintf(bufp, ":NA");
753 len = sprintf(bufp, ":%08x", ddata->revision);
758 static int sysc_show_reg(struct sysc *ddata,
759 char *bufp, enum sysc_registers reg)
761 if (ddata->offsets[reg] < 0)
762 return sprintf(bufp, ":NA");
764 return sprintf(bufp, ":%x", ddata->offsets[reg]);
767 static int sysc_show_name(char *bufp, struct sysc *ddata)
772 return sprintf(bufp, ":%s", ddata->name);
776 * sysc_show_registers - show information about interconnect target module
777 * @ddata: device driver data
779 static void sysc_show_registers(struct sysc *ddata)
785 for (i = 0; i < SYSC_MAX_REGS; i++)
786 bufp += sysc_show_reg(ddata, bufp, i);
788 bufp += sysc_show_rev(bufp, ddata);
789 bufp += sysc_show_name(bufp, ddata);
791 dev_dbg(ddata->dev, "%llx:%x%s\n",
792 ddata->module_pa, ddata->module_size,
796 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
798 static int sysc_enable_module(struct device *dev)
801 const struct sysc_regbits *regbits;
802 u32 reg, idlemodes, best_mode;
804 ddata = dev_get_drvdata(dev);
805 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
809 * TODO: Need to prevent clockdomain autoidle?
810 * See clkdm_deny_idle() in arch/mach-omap2/omap_hwmod.c
813 regbits = ddata->cap->regbits;
814 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
817 idlemodes = ddata->cfg.sidlemodes;
818 if (!idlemodes || regbits->sidle_shift < 0)
821 best_mode = fls(ddata->cfg.sidlemodes) - 1;
822 if (best_mode > SYSC_IDLE_MASK) {
823 dev_err(dev, "%s: invalid sidlemode\n", __func__);
827 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
828 reg |= best_mode << regbits->sidle_shift;
829 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
833 idlemodes = ddata->cfg.midlemodes;
834 if (!idlemodes || regbits->midle_shift < 0)
837 best_mode = fls(ddata->cfg.midlemodes) - 1;
838 if (best_mode > SYSC_IDLE_MASK) {
839 dev_err(dev, "%s: invalid midlemode\n", __func__);
843 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
844 reg |= best_mode << regbits->midle_shift;
845 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
850 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
852 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
853 *best_mode = SYSC_IDLE_SMART_WKUP;
854 else if (idlemodes & BIT(SYSC_IDLE_SMART))
855 *best_mode = SYSC_IDLE_SMART;
856 else if (idlemodes & SYSC_IDLE_FORCE)
857 *best_mode = SYSC_IDLE_FORCE;
864 static int sysc_disable_module(struct device *dev)
867 const struct sysc_regbits *regbits;
868 u32 reg, idlemodes, best_mode;
871 ddata = dev_get_drvdata(dev);
872 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
876 * TODO: Need to prevent clockdomain autoidle?
877 * See clkdm_deny_idle() in arch/mach-omap2/omap_hwmod.c
880 regbits = ddata->cap->regbits;
881 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
884 idlemodes = ddata->cfg.midlemodes;
885 if (!idlemodes || regbits->midle_shift < 0)
888 ret = sysc_best_idle_mode(idlemodes, &best_mode);
890 dev_err(dev, "%s: invalid midlemode\n", __func__);
894 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
895 reg |= best_mode << regbits->midle_shift;
896 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
900 idlemodes = ddata->cfg.sidlemodes;
901 if (!idlemodes || regbits->sidle_shift < 0)
904 ret = sysc_best_idle_mode(idlemodes, &best_mode);
906 dev_err(dev, "%s: invalid sidlemode\n", __func__);
910 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
911 reg |= best_mode << regbits->sidle_shift;
912 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
917 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
920 struct ti_sysc_platform_data *pdata;
923 pdata = dev_get_platdata(ddata->dev);
927 if (!pdata->idle_module)
930 error = pdata->idle_module(dev, &ddata->cookie);
932 dev_err(dev, "%s: could not idle: %i\n",
938 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
941 struct ti_sysc_platform_data *pdata;
944 pdata = dev_get_platdata(ddata->dev);
948 if (!pdata->enable_module)
951 error = pdata->enable_module(dev, &ddata->cookie);
953 dev_err(dev, "%s: could not enable: %i\n",
959 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
964 ddata = dev_get_drvdata(dev);
969 if (ddata->legacy_mode) {
970 error = sysc_runtime_suspend_legacy(dev, ddata);
974 error = sysc_disable_module(dev);
979 sysc_disable_main_clocks(ddata);
981 if (sysc_opt_clks_needed(ddata))
982 sysc_disable_opt_clocks(ddata);
984 ddata->enabled = false;
989 static int __maybe_unused sysc_runtime_resume(struct device *dev)
994 ddata = dev_get_drvdata(dev);
999 if (sysc_opt_clks_needed(ddata)) {
1000 error = sysc_enable_opt_clocks(ddata);
1005 error = sysc_enable_main_clocks(ddata);
1007 goto err_opt_clocks;
1009 if (ddata->legacy_mode) {
1010 error = sysc_runtime_resume_legacy(dev, ddata);
1012 goto err_main_clocks;
1014 error = sysc_enable_module(dev);
1016 goto err_main_clocks;
1019 ddata->enabled = true;
1024 sysc_disable_main_clocks(ddata);
1026 if (sysc_opt_clks_needed(ddata))
1027 sysc_disable_opt_clocks(ddata);
1032 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1036 ddata = dev_get_drvdata(dev);
1038 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1041 return pm_runtime_force_suspend(dev);
1044 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1048 ddata = dev_get_drvdata(dev);
1050 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1053 return pm_runtime_force_resume(dev);
1056 static const struct dev_pm_ops sysc_pm_ops = {
1057 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1058 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1059 sysc_runtime_resume,
1063 /* Module revision register based quirks */
1064 struct sysc_revision_quirk {
1075 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1076 optrev_val, optrevmask, optquirkmask) \
1078 .name = (optname), \
1079 .base = (optbase), \
1080 .rev_offset = (optrev), \
1081 .sysc_offset = (optsysc), \
1082 .syss_offset = (optsyss), \
1083 .revision = (optrev_val), \
1084 .revision_mask = (optrevmask), \
1085 .quirks = (optquirkmask), \
1088 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1089 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1090 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1091 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1092 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1093 SYSC_QUIRK_LEGACY_IDLE),
1094 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1095 SYSC_QUIRK_LEGACY_IDLE),
1096 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1097 SYSC_QUIRK_LEGACY_IDLE),
1098 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1099 SYSC_QUIRK_LEGACY_IDLE),
1100 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1101 SYSC_QUIRK_LEGACY_IDLE),
1102 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1104 /* Some timers on omap4 and later */
1105 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
1107 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
1109 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1110 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1111 /* Uarts on omap4 and later */
1112 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1113 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1114 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1115 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1117 /* Quirks that need to be set based on the module address */
1118 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1119 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1120 SYSC_QUIRK_SWSUP_SIDLE),
1123 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
1124 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
1125 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
1126 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
1127 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1128 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1130 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
1131 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1132 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1133 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
1134 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1135 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0),
1136 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0),
1137 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1138 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
1139 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0),
1140 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
1141 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1142 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
1143 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
1144 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1145 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1146 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1147 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
1148 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1149 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
1150 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
1151 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
1152 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
1153 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1154 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
1155 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1156 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1157 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
1158 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
1159 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
1160 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1161 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1162 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1163 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1164 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1165 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1166 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
1167 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1168 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
1169 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1170 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1171 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1172 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1173 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1175 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0),
1176 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
1181 * Early quirks based on module base and register offsets only that are
1182 * needed before the module revision can be read
1184 static void sysc_init_early_quirks(struct sysc *ddata)
1186 const struct sysc_revision_quirk *q;
1189 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1190 q = &sysc_revision_quirks[i];
1195 if (q->base != ddata->module_pa)
1198 if (q->rev_offset >= 0 &&
1199 q->rev_offset != ddata->offsets[SYSC_REVISION])
1202 if (q->sysc_offset >= 0 &&
1203 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1206 if (q->syss_offset >= 0 &&
1207 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1210 ddata->name = q->name;
1211 ddata->cfg.quirks |= q->quirks;
1215 /* Quirks that also consider the revision register value */
1216 static void sysc_init_revision_quirks(struct sysc *ddata)
1218 const struct sysc_revision_quirk *q;
1221 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1222 q = &sysc_revision_quirks[i];
1224 if (q->base && q->base != ddata->module_pa)
1227 if (q->rev_offset >= 0 &&
1228 q->rev_offset != ddata->offsets[SYSC_REVISION])
1231 if (q->sysc_offset >= 0 &&
1232 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1235 if (q->syss_offset >= 0 &&
1236 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1239 if (q->revision == ddata->revision ||
1240 (q->revision & q->revision_mask) ==
1241 (ddata->revision & q->revision_mask)) {
1242 ddata->name = q->name;
1243 ddata->cfg.quirks |= q->quirks;
1249 * Note that pdata->init_module() typically does a reset first. After
1250 * pdata->init_module() is done, PM runtime can be used for the interconnect
1253 static int sysc_legacy_init(struct sysc *ddata)
1255 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1258 if (!ddata->legacy_mode || !pdata || !pdata->init_module)
1261 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1262 if (error == -EEXIST)
1269 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1270 * @ddata: device driver data
1271 * @reset: reset before deassert
1273 * A module can have both OCP softreset control and external rstctrl.
1274 * If more complicated rstctrl resets are needed, please handle these
1275 * directly from the child device driver and map only the module reset
1276 * for the parent interconnect target module device.
1278 * Automatic reset of the module on init can be skipped with the
1279 * "ti,no-reset-on-init" device tree property.
1281 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1289 error = reset_control_assert(ddata->rsts);
1294 return reset_control_deassert(ddata->rsts);
1297 static int sysc_reset(struct sysc *ddata)
1299 int offset = ddata->offsets[SYSC_SYSCONFIG];
1302 if (ddata->legacy_mode || offset < 0 ||
1303 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1307 * Currently only support reset status in sysstatus.
1308 * Warn and return error in all other cases
1310 if (!ddata->cfg.syss_mask) {
1311 dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n");
1315 val = sysc_read(ddata, offset);
1316 val |= (0x1 << ddata->cap->regbits->srst_shift);
1317 sysc_write(ddata, offset, val);
1319 /* Poll on reset status */
1320 offset = ddata->offsets[SYSC_SYSSTATUS];
1322 return readl_poll_timeout(ddata->module_va + offset, val,
1323 (val & ddata->cfg.syss_mask) == 0x0,
1324 100, MAX_MODULE_SOFTRESET_WAIT);
1328 * At this point the module is configured enough to read the revision but
1329 * module may not be completely configured yet to use PM runtime. Enable
1330 * all clocks directly during init to configure the quirks needed for PM
1331 * runtime based on the revision register.
1333 static int sysc_init_module(struct sysc *ddata)
1336 bool manage_clocks = true;
1339 if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1342 error = sysc_rstctrl_reset_deassert(ddata, reset);
1346 if (ddata->cfg.quirks &
1347 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1348 manage_clocks = false;
1350 if (manage_clocks) {
1351 error = sysc_enable_opt_clocks(ddata);
1355 error = sysc_enable_main_clocks(ddata);
1357 goto err_opt_clocks;
1360 ddata->revision = sysc_read_revision(ddata);
1361 sysc_init_revision_quirks(ddata);
1363 error = sysc_legacy_init(ddata);
1365 goto err_main_clocks;
1367 error = sysc_reset(ddata);
1369 dev_err(ddata->dev, "Reset failed with %d\n", error);
1373 sysc_disable_main_clocks(ddata);
1376 sysc_disable_opt_clocks(ddata);
1381 static int sysc_init_sysc_mask(struct sysc *ddata)
1383 struct device_node *np = ddata->dev->of_node;
1387 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1392 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1394 ddata->cfg.sysc_val = ddata->cap->sysc_mask;
1399 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1402 struct device_node *np = ddata->dev->of_node;
1403 struct property *prop;
1407 of_property_for_each_u32(np, name, prop, p, val) {
1408 if (val >= SYSC_NR_IDLEMODES) {
1409 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1412 *idlemodes |= (1 << val);
1418 static int sysc_init_idlemodes(struct sysc *ddata)
1422 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1427 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1436 * Only some devices on omap4 and later have SYSCONFIG reset done
1437 * bit. We can detect this if there is no SYSSTATUS at all, or the
1438 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1439 * have multiple bits for the child devices like OHCI and EHCI.
1440 * Depends on SYSC being parsed first.
1442 static int sysc_init_syss_mask(struct sysc *ddata)
1444 struct device_node *np = ddata->dev->of_node;
1448 error = of_property_read_u32(np, "ti,syss-mask", &val);
1450 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1451 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1452 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1453 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1458 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1459 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1461 ddata->cfg.syss_mask = val;
1467 * Many child device drivers need to have fck and opt clocks available
1468 * to get the clock rate for device internal configuration etc.
1470 static int sysc_child_add_named_clock(struct sysc *ddata,
1471 struct device *child,
1475 struct clk_lookup *l;
1481 clk = clk_get(child, name);
1488 clk = clk_get(ddata->dev, name);
1492 l = clkdev_create(clk, name, dev_name(child));
1501 static int sysc_child_add_clocks(struct sysc *ddata,
1502 struct device *child)
1506 for (i = 0; i < ddata->nr_clocks; i++) {
1507 error = sysc_child_add_named_clock(ddata,
1509 ddata->clock_roles[i]);
1510 if (error && error != -EEXIST) {
1511 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1512 ddata->clock_roles[i], error);
1521 static struct device_type sysc_device_type = {
1524 static struct sysc *sysc_child_to_parent(struct device *dev)
1526 struct device *parent = dev->parent;
1528 if (!parent || parent->type != &sysc_device_type)
1531 return dev_get_drvdata(parent);
1534 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1539 ddata = sysc_child_to_parent(dev);
1541 error = pm_generic_runtime_suspend(dev);
1545 if (!ddata->enabled)
1548 return sysc_runtime_suspend(ddata->dev);
1551 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1556 ddata = sysc_child_to_parent(dev);
1558 if (!ddata->enabled) {
1559 error = sysc_runtime_resume(ddata->dev);
1562 "%s error: %i\n", __func__, error);
1565 return pm_generic_runtime_resume(dev);
1568 #ifdef CONFIG_PM_SLEEP
1569 static int sysc_child_suspend_noirq(struct device *dev)
1574 ddata = sysc_child_to_parent(dev);
1576 dev_dbg(ddata->dev, "%s %s\n", __func__,
1577 ddata->name ? ddata->name : "");
1579 error = pm_generic_suspend_noirq(dev);
1581 dev_err(dev, "%s error at %i: %i\n",
1582 __func__, __LINE__, error);
1587 if (!pm_runtime_status_suspended(dev)) {
1588 error = pm_generic_runtime_suspend(dev);
1590 dev_dbg(dev, "%s busy at %i: %i\n",
1591 __func__, __LINE__, error);
1596 error = sysc_runtime_suspend(ddata->dev);
1598 dev_err(dev, "%s error at %i: %i\n",
1599 __func__, __LINE__, error);
1604 ddata->child_needs_resume = true;
1610 static int sysc_child_resume_noirq(struct device *dev)
1615 ddata = sysc_child_to_parent(dev);
1617 dev_dbg(ddata->dev, "%s %s\n", __func__,
1618 ddata->name ? ddata->name : "");
1620 if (ddata->child_needs_resume) {
1621 ddata->child_needs_resume = false;
1623 error = sysc_runtime_resume(ddata->dev);
1626 "%s runtime resume error: %i\n",
1629 error = pm_generic_runtime_resume(dev);
1632 "%s generic runtime resume: %i\n",
1636 return pm_generic_resume_noirq(dev);
1640 static struct dev_pm_domain sysc_child_pm_domain = {
1642 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1643 sysc_child_runtime_resume,
1645 USE_PLATFORM_PM_SLEEP_OPS
1646 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1647 sysc_child_resume_noirq)
1652 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1653 * @ddata: device driver data
1654 * @child: child device driver
1656 * Allow idle for child devices as done with _od_runtime_suspend().
1657 * Otherwise many child devices will not idle because of the permanent
1658 * parent usecount set in pm_runtime_irq_safe().
1660 * Note that the long term solution is to just modify the child device
1661 * drivers to not set pm_runtime_irq_safe() and then this can be just
1664 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1666 if (!ddata->legacy_mode)
1669 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1670 dev_pm_domain_set(child, &sysc_child_pm_domain);
1673 static int sysc_notifier_call(struct notifier_block *nb,
1674 unsigned long event, void *device)
1676 struct device *dev = device;
1680 ddata = sysc_child_to_parent(dev);
1685 case BUS_NOTIFY_ADD_DEVICE:
1686 error = sysc_child_add_clocks(ddata, dev);
1689 sysc_legacy_idle_quirk(ddata, dev);
1698 static struct notifier_block sysc_nb = {
1699 .notifier_call = sysc_notifier_call,
1702 /* Device tree configured quirks */
1703 struct sysc_dts_quirk {
1708 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
1709 { .name = "ti,no-idle-on-init",
1710 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1711 { .name = "ti,no-reset-on-init",
1712 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
1713 { .name = "ti,no-idle",
1714 .mask = SYSC_QUIRK_NO_IDLE, },
1717 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
1720 const struct property *prop;
1723 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
1724 const char *name = sysc_dts_quirks[i].name;
1726 prop = of_get_property(np, name, &len);
1730 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
1732 dev_warn(ddata->dev,
1733 "dts flag should be at module level for %s\n",
1739 static int sysc_init_dts_quirks(struct sysc *ddata)
1741 struct device_node *np = ddata->dev->of_node;
1745 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
1747 sysc_parse_dts_quirks(ddata, np, false);
1748 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
1751 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
1755 ddata->cfg.srst_udelay = (u8)val;
1761 static void sysc_unprepare(struct sysc *ddata)
1768 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
1769 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
1770 clk_unprepare(ddata->clocks[i]);
1775 * Common sysc register bits found on omap2, also known as type1
1777 static const struct sysc_regbits sysc_regbits_omap2 = {
1778 .dmadisable_shift = -ENODEV,
1785 .autoidle_shift = 0,
1788 static const struct sysc_capabilities sysc_omap2 = {
1789 .type = TI_SYSC_OMAP2,
1790 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1791 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1792 SYSC_OMAP2_AUTOIDLE,
1793 .regbits = &sysc_regbits_omap2,
1796 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
1797 static const struct sysc_capabilities sysc_omap2_timer = {
1798 .type = TI_SYSC_OMAP2_TIMER,
1799 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1800 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1801 SYSC_OMAP2_AUTOIDLE,
1802 .regbits = &sysc_regbits_omap2,
1803 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
1807 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
1808 * with different sidle position
1810 static const struct sysc_regbits sysc_regbits_omap3_sham = {
1811 .dmadisable_shift = -ENODEV,
1812 .midle_shift = -ENODEV,
1814 .clkact_shift = -ENODEV,
1815 .enwkup_shift = -ENODEV,
1817 .autoidle_shift = 0,
1818 .emufree_shift = -ENODEV,
1821 static const struct sysc_capabilities sysc_omap3_sham = {
1822 .type = TI_SYSC_OMAP3_SHAM,
1823 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1824 .regbits = &sysc_regbits_omap3_sham,
1828 * AES register bits found on omap3 and later, a variant of
1829 * sysc_regbits_omap2 with different sidle position
1831 static const struct sysc_regbits sysc_regbits_omap3_aes = {
1832 .dmadisable_shift = -ENODEV,
1833 .midle_shift = -ENODEV,
1835 .clkact_shift = -ENODEV,
1836 .enwkup_shift = -ENODEV,
1838 .autoidle_shift = 0,
1839 .emufree_shift = -ENODEV,
1842 static const struct sysc_capabilities sysc_omap3_aes = {
1843 .type = TI_SYSC_OMAP3_AES,
1844 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1845 .regbits = &sysc_regbits_omap3_aes,
1849 * Common sysc register bits found on omap4, also known as type2
1851 static const struct sysc_regbits sysc_regbits_omap4 = {
1852 .dmadisable_shift = 16,
1855 .clkact_shift = -ENODEV,
1856 .enwkup_shift = -ENODEV,
1859 .autoidle_shift = -ENODEV,
1862 static const struct sysc_capabilities sysc_omap4 = {
1863 .type = TI_SYSC_OMAP4,
1864 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1865 SYSC_OMAP4_SOFTRESET,
1866 .regbits = &sysc_regbits_omap4,
1869 static const struct sysc_capabilities sysc_omap4_timer = {
1870 .type = TI_SYSC_OMAP4_TIMER,
1871 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1872 SYSC_OMAP4_SOFTRESET,
1873 .regbits = &sysc_regbits_omap4,
1877 * Common sysc register bits found on omap4, also known as type3
1879 static const struct sysc_regbits sysc_regbits_omap4_simple = {
1880 .dmadisable_shift = -ENODEV,
1883 .clkact_shift = -ENODEV,
1884 .enwkup_shift = -ENODEV,
1885 .srst_shift = -ENODEV,
1886 .emufree_shift = -ENODEV,
1887 .autoidle_shift = -ENODEV,
1890 static const struct sysc_capabilities sysc_omap4_simple = {
1891 .type = TI_SYSC_OMAP4_SIMPLE,
1892 .regbits = &sysc_regbits_omap4_simple,
1896 * SmartReflex sysc found on omap34xx
1898 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
1899 .dmadisable_shift = -ENODEV,
1900 .midle_shift = -ENODEV,
1901 .sidle_shift = -ENODEV,
1903 .enwkup_shift = -ENODEV,
1904 .srst_shift = -ENODEV,
1905 .emufree_shift = -ENODEV,
1906 .autoidle_shift = -ENODEV,
1909 static const struct sysc_capabilities sysc_34xx_sr = {
1910 .type = TI_SYSC_OMAP34XX_SR,
1911 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
1912 .regbits = &sysc_regbits_omap34xx_sr,
1913 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
1914 SYSC_QUIRK_LEGACY_IDLE,
1918 * SmartReflex sysc found on omap36xx and later
1920 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
1921 .dmadisable_shift = -ENODEV,
1922 .midle_shift = -ENODEV,
1924 .clkact_shift = -ENODEV,
1926 .srst_shift = -ENODEV,
1927 .emufree_shift = -ENODEV,
1928 .autoidle_shift = -ENODEV,
1931 static const struct sysc_capabilities sysc_36xx_sr = {
1932 .type = TI_SYSC_OMAP36XX_SR,
1933 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
1934 .regbits = &sysc_regbits_omap36xx_sr,
1935 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
1938 static const struct sysc_capabilities sysc_omap4_sr = {
1939 .type = TI_SYSC_OMAP4_SR,
1940 .regbits = &sysc_regbits_omap36xx_sr,
1941 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
1945 * McASP register bits found on omap4 and later
1947 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
1948 .dmadisable_shift = -ENODEV,
1949 .midle_shift = -ENODEV,
1951 .clkact_shift = -ENODEV,
1952 .enwkup_shift = -ENODEV,
1953 .srst_shift = -ENODEV,
1954 .emufree_shift = -ENODEV,
1955 .autoidle_shift = -ENODEV,
1958 static const struct sysc_capabilities sysc_omap4_mcasp = {
1959 .type = TI_SYSC_OMAP4_MCASP,
1960 .regbits = &sysc_regbits_omap4_mcasp,
1961 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
1965 * McASP found on dra7 and later
1967 static const struct sysc_capabilities sysc_dra7_mcasp = {
1968 .type = TI_SYSC_OMAP4_SIMPLE,
1969 .regbits = &sysc_regbits_omap4_simple,
1970 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
1974 * FS USB host found on omap4 and later
1976 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
1977 .dmadisable_shift = -ENODEV,
1978 .midle_shift = -ENODEV,
1980 .clkact_shift = -ENODEV,
1982 .srst_shift = -ENODEV,
1983 .emufree_shift = -ENODEV,
1984 .autoidle_shift = -ENODEV,
1987 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
1988 .type = TI_SYSC_OMAP4_USB_HOST_FS,
1989 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
1990 .regbits = &sysc_regbits_omap4_usb_host_fs,
1993 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
1994 .dmadisable_shift = -ENODEV,
1995 .midle_shift = -ENODEV,
1996 .sidle_shift = -ENODEV,
1997 .clkact_shift = -ENODEV,
2000 .emufree_shift = -ENODEV,
2001 .autoidle_shift = -ENODEV,
2004 static const struct sysc_capabilities sysc_dra7_mcan = {
2005 .type = TI_SYSC_DRA7_MCAN,
2006 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2007 .regbits = &sysc_regbits_dra7_mcan,
2010 static int sysc_init_pdata(struct sysc *ddata)
2012 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2013 struct ti_sysc_module_data *mdata;
2015 if (!pdata || !ddata->legacy_mode)
2018 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2022 mdata->name = ddata->legacy_mode;
2023 mdata->module_pa = ddata->module_pa;
2024 mdata->module_size = ddata->module_size;
2025 mdata->offsets = ddata->offsets;
2026 mdata->nr_offsets = SYSC_MAX_REGS;
2027 mdata->cap = ddata->cap;
2028 mdata->cfg = &ddata->cfg;
2030 ddata->mdata = mdata;
2035 static int sysc_init_match(struct sysc *ddata)
2037 const struct sysc_capabilities *cap;
2039 cap = of_device_get_match_data(ddata->dev);
2045 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2050 static void ti_sysc_idle(struct work_struct *work)
2054 ddata = container_of(work, struct sysc, idle_work.work);
2056 if (pm_runtime_active(ddata->dev))
2057 pm_runtime_put_sync(ddata->dev);
2060 static const struct of_device_id sysc_match_table[] = {
2061 { .compatible = "simple-bus", },
2065 static int sysc_probe(struct platform_device *pdev)
2067 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2071 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2075 ddata->dev = &pdev->dev;
2076 platform_set_drvdata(pdev, ddata);
2078 error = sysc_init_match(ddata);
2082 error = sysc_init_dts_quirks(ddata);
2086 error = sysc_map_and_check_registers(ddata);
2090 error = sysc_init_sysc_mask(ddata);
2094 error = sysc_init_idlemodes(ddata);
2098 error = sysc_init_syss_mask(ddata);
2102 error = sysc_init_pdata(ddata);
2106 sysc_init_early_quirks(ddata);
2108 error = sysc_get_clocks(ddata);
2112 error = sysc_init_resets(ddata);
2116 error = sysc_init_module(ddata);
2120 pm_runtime_enable(ddata->dev);
2121 error = pm_runtime_get_sync(ddata->dev);
2123 pm_runtime_put_noidle(ddata->dev);
2124 pm_runtime_disable(ddata->dev);
2128 sysc_show_registers(ddata);
2130 ddata->dev->type = &sysc_device_type;
2131 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2132 pdata ? pdata->auxdata : NULL,
2137 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2139 /* At least earlycon won't survive without deferred idle */
2140 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT |
2141 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2142 schedule_delayed_work(&ddata->idle_work, 3000);
2144 pm_runtime_put(&pdev->dev);
2147 if (!of_get_available_child_count(ddata->dev->of_node))
2148 reset_control_assert(ddata->rsts);
2153 pm_runtime_put_sync(&pdev->dev);
2154 pm_runtime_disable(&pdev->dev);
2156 sysc_unprepare(ddata);
2161 static int sysc_remove(struct platform_device *pdev)
2163 struct sysc *ddata = platform_get_drvdata(pdev);
2166 cancel_delayed_work_sync(&ddata->idle_work);
2168 error = pm_runtime_get_sync(ddata->dev);
2170 pm_runtime_put_noidle(ddata->dev);
2171 pm_runtime_disable(ddata->dev);
2175 of_platform_depopulate(&pdev->dev);
2177 pm_runtime_put_sync(&pdev->dev);
2178 pm_runtime_disable(&pdev->dev);
2179 reset_control_assert(ddata->rsts);
2182 sysc_unprepare(ddata);
2187 static const struct of_device_id sysc_match[] = {
2188 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2189 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2190 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2191 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2192 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2193 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2194 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2195 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2196 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2197 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2198 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2199 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2200 { .compatible = "ti,sysc-usb-host-fs",
2201 .data = &sysc_omap4_usb_host_fs, },
2202 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2205 MODULE_DEVICE_TABLE(of, sysc_match);
2207 static struct platform_driver sysc_driver = {
2208 .probe = sysc_probe,
2209 .remove = sysc_remove,
2212 .of_match_table = sysc_match,
2217 static int __init sysc_init(void)
2219 bus_register_notifier(&platform_bus_type, &sysc_nb);
2221 return platform_driver_register(&sysc_driver);
2223 module_init(sysc_init);
2225 static void __exit sysc_exit(void)
2227 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2228 platform_driver_unregister(&sysc_driver);
2230 module_exit(sysc_exit);
2232 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2233 MODULE_LICENSE("GPL v2");