1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_domain.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/slab.h>
18 #include <linux/iopoll.h>
20 #include <linux/platform_data/ti-sysc.h>
22 #include <dt-bindings/bus/ti-sysc.h>
24 #define MAX_MODULE_SOFTRESET_WAIT 10000
26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
47 #define SYSC_IDLEMODE_MASK 3
48 #define SYSC_CLOCKACTIVITY_MASK 3
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
57 * @mdata: ti-sysc to hwmod translation data for a module
58 * @clocks: clocks used by the interconnect target module
59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
61 * @rsts: resets used by the interconnect target module
62 * @legacy_mode: configured for legacy mode if set
63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
65 * @cookie: data used by legacy platform callbacks
66 * @name: name if available
67 * @revision: interconnect target module revision
68 * @enabled: sysc runtime enabled status
69 * @needs_resume: runtime resume needed on resume from suspend
70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
73 * @clk_enable_quirk: module specific clock enable quirk
74 * @clk_disable_quirk: module specific clock disable quirk
75 * @reset_done_quirk: module specific reset done quirk
76 * @module_enable_quirk: module specific enable quirk
82 void __iomem *module_va;
83 int offsets[SYSC_MAX_REGS];
84 struct ti_sysc_module_data *mdata;
86 const char **clock_roles;
88 struct reset_control *rsts;
89 const char *legacy_mode;
90 const struct sysc_capabilities *cap;
91 struct sysc_config cfg;
92 struct ti_sysc_cookie cookie;
95 unsigned int enabled:1;
96 unsigned int needs_resume:1;
97 unsigned int child_needs_resume:1;
98 struct delayed_work idle_work;
99 void (*clk_enable_quirk)(struct sysc *sysc);
100 void (*clk_disable_quirk)(struct sysc *sysc);
101 void (*reset_done_quirk)(struct sysc *sysc);
102 void (*module_enable_quirk)(struct sysc *sysc);
105 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
108 static void sysc_write(struct sysc *ddata, int offset, u32 value)
110 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
111 writew_relaxed(value & 0xffff, ddata->module_va + offset);
113 /* Only i2c revision has LO and HI register with stride of 4 */
114 if (ddata->offsets[SYSC_REVISION] >= 0 &&
115 offset == ddata->offsets[SYSC_REVISION]) {
116 u16 hi = value >> 16;
118 writew_relaxed(hi, ddata->module_va + offset + 4);
124 writel_relaxed(value, ddata->module_va + offset);
127 static u32 sysc_read(struct sysc *ddata, int offset)
129 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
132 val = readw_relaxed(ddata->module_va + offset);
134 /* Only i2c revision has LO and HI register with stride of 4 */
135 if (ddata->offsets[SYSC_REVISION] >= 0 &&
136 offset == ddata->offsets[SYSC_REVISION]) {
137 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
145 return readl_relaxed(ddata->module_va + offset);
148 static bool sysc_opt_clks_needed(struct sysc *ddata)
150 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
153 static u32 sysc_read_revision(struct sysc *ddata)
155 int offset = ddata->offsets[SYSC_REVISION];
160 return sysc_read(ddata, offset);
163 static u32 sysc_read_sysconfig(struct sysc *ddata)
165 int offset = ddata->offsets[SYSC_SYSCONFIG];
170 return sysc_read(ddata, offset);
173 static u32 sysc_read_sysstatus(struct sysc *ddata)
175 int offset = ddata->offsets[SYSC_SYSSTATUS];
180 return sysc_read(ddata, offset);
183 static int sysc_add_named_clock_from_child(struct sysc *ddata,
185 const char *optfck_name)
187 struct device_node *np = ddata->dev->of_node;
188 struct device_node *child;
189 struct clk_lookup *cl;
198 /* Does the clock alias already exist? */
199 clock = of_clk_get_by_name(np, n);
200 if (!IS_ERR(clock)) {
206 child = of_get_next_available_child(np, NULL);
210 clock = devm_get_clk_from_child(ddata->dev, child, name);
212 return PTR_ERR(clock);
215 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
216 * limit for clk_get(). If cl ever needs to be freed, it should be done
217 * with clkdev_drop().
219 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
224 cl->dev_id = dev_name(ddata->dev);
233 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
235 const char *optfck_name;
238 if (ddata->nr_clocks < SYSC_OPTFCK0)
239 index = SYSC_OPTFCK0;
241 index = ddata->nr_clocks;
246 optfck_name = clock_names[index];
248 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
252 ddata->clock_roles[index] = optfck_name;
258 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
260 int error, i, index = -ENODEV;
262 if (!strncmp(clock_names[SYSC_FCK], name, 3))
264 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
268 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
269 if (!ddata->clocks[i]) {
277 dev_err(ddata->dev, "clock %s not added\n", name);
281 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
282 if (IS_ERR(ddata->clocks[index])) {
283 if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
286 dev_err(ddata->dev, "clock get error for %s: %li\n",
287 name, PTR_ERR(ddata->clocks[index]));
289 return PTR_ERR(ddata->clocks[index]);
292 error = clk_prepare(ddata->clocks[index]);
294 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
303 static int sysc_get_clocks(struct sysc *ddata)
305 struct device_node *np = ddata->dev->of_node;
306 struct property *prop;
308 int nr_fck = 0, nr_ick = 0, i, error = 0;
310 ddata->clock_roles = devm_kcalloc(ddata->dev,
312 sizeof(*ddata->clock_roles),
314 if (!ddata->clock_roles)
317 of_property_for_each_string(np, "clock-names", prop, name) {
318 if (!strncmp(clock_names[SYSC_FCK], name, 3))
320 if (!strncmp(clock_names[SYSC_ICK], name, 3))
322 ddata->clock_roles[ddata->nr_clocks] = name;
326 if (ddata->nr_clocks < 1)
329 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
330 error = sysc_init_ext_opt_clock(ddata, NULL);
335 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
336 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
341 if (nr_fck > 1 || nr_ick > 1) {
342 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
347 ddata->clocks = devm_kcalloc(ddata->dev,
348 ddata->nr_clocks, sizeof(*ddata->clocks),
353 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
354 const char *name = ddata->clock_roles[i];
359 error = sysc_get_one_clock(ddata, name);
360 if (error && error != -ENOENT)
367 static int sysc_enable_main_clocks(struct sysc *ddata)
375 for (i = 0; i < SYSC_OPTFCK0; i++) {
376 clock = ddata->clocks[i];
378 /* Main clocks may not have ick */
379 if (IS_ERR_OR_NULL(clock))
382 error = clk_enable(clock);
390 for (i--; i >= 0; i--) {
391 clock = ddata->clocks[i];
393 /* Main clocks may not have ick */
394 if (IS_ERR_OR_NULL(clock))
403 static void sysc_disable_main_clocks(struct sysc *ddata)
411 for (i = 0; i < SYSC_OPTFCK0; i++) {
412 clock = ddata->clocks[i];
413 if (IS_ERR_OR_NULL(clock))
420 static int sysc_enable_opt_clocks(struct sysc *ddata)
428 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
429 clock = ddata->clocks[i];
431 /* Assume no holes for opt clocks */
432 if (IS_ERR_OR_NULL(clock))
435 error = clk_enable(clock);
443 for (i--; i >= 0; i--) {
444 clock = ddata->clocks[i];
445 if (IS_ERR_OR_NULL(clock))
454 static void sysc_disable_opt_clocks(struct sysc *ddata)
462 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
463 clock = ddata->clocks[i];
465 /* Assume no holes for opt clocks */
466 if (IS_ERR_OR_NULL(clock))
473 static void sysc_clkdm_deny_idle(struct sysc *ddata)
475 struct ti_sysc_platform_data *pdata;
477 if (ddata->legacy_mode)
480 pdata = dev_get_platdata(ddata->dev);
481 if (pdata && pdata->clkdm_deny_idle)
482 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
485 static void sysc_clkdm_allow_idle(struct sysc *ddata)
487 struct ti_sysc_platform_data *pdata;
489 if (ddata->legacy_mode)
492 pdata = dev_get_platdata(ddata->dev);
493 if (pdata && pdata->clkdm_allow_idle)
494 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
498 * sysc_init_resets - init rstctrl reset line if configured
499 * @ddata: device driver data
501 * See sysc_rstctrl_reset_deassert().
503 static int sysc_init_resets(struct sysc *ddata)
506 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
507 if (IS_ERR(ddata->rsts))
508 return PTR_ERR(ddata->rsts);
514 * sysc_parse_and_check_child_range - parses module IO region from ranges
515 * @ddata: device driver data
517 * In general we only need rev, syss, and sysc registers and not the whole
518 * module range. But we do want the offsets for these registers from the
519 * module base. This allows us to check them against the legacy hwmod
520 * platform data. Let's also check the ranges are configured properly.
522 static int sysc_parse_and_check_child_range(struct sysc *ddata)
524 struct device_node *np = ddata->dev->of_node;
525 const __be32 *ranges;
526 u32 nr_addr, nr_size;
529 ranges = of_get_property(np, "ranges", &len);
531 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
536 len /= sizeof(*ranges);
539 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
544 error = of_property_read_u32(np, "#address-cells", &nr_addr);
548 error = of_property_read_u32(np, "#size-cells", &nr_size);
552 if (nr_addr != 1 || nr_size != 1) {
553 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
559 ddata->module_pa = of_translate_address(np, ranges++);
560 ddata->module_size = be32_to_cpup(ranges);
565 static struct device_node *stdout_path;
567 static void sysc_init_stdout_path(struct sysc *ddata)
569 struct device_node *np = NULL;
572 if (IS_ERR(stdout_path))
578 np = of_find_node_by_path("/chosen");
582 uart = of_get_property(np, "stdout-path", NULL);
586 np = of_find_node_by_path(uart);
595 stdout_path = ERR_PTR(-ENODEV);
598 static void sysc_check_quirk_stdout(struct sysc *ddata,
599 struct device_node *np)
601 sysc_init_stdout_path(ddata);
602 if (np != stdout_path)
605 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
606 SYSC_QUIRK_NO_RESET_ON_INIT;
610 * sysc_check_one_child - check child configuration
611 * @ddata: device driver data
612 * @np: child device node
614 * Let's avoid messy situations where we have new interconnect target
615 * node but children have "ti,hwmods". These belong to the interconnect
616 * target node and are managed by this driver.
618 static void sysc_check_one_child(struct sysc *ddata,
619 struct device_node *np)
623 name = of_get_property(np, "ti,hwmods", NULL);
625 dev_warn(ddata->dev, "really a child ti,hwmods property?");
627 sysc_check_quirk_stdout(ddata, np);
628 sysc_parse_dts_quirks(ddata, np, true);
631 static void sysc_check_children(struct sysc *ddata)
633 struct device_node *child;
635 for_each_child_of_node(ddata->dev->of_node, child)
636 sysc_check_one_child(ddata, child);
640 * So far only I2C uses 16-bit read access with clockactivity with revision
641 * in two registers with stride of 4. We can detect this based on the rev
642 * register size to configure things far enough to be able to properly read
643 * the revision register.
645 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
647 if (resource_size(res) == 8)
648 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
652 * sysc_parse_one - parses the interconnect target module registers
653 * @ddata: device driver data
654 * @reg: register to parse
656 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
658 struct resource *res;
665 name = reg_names[reg];
671 res = platform_get_resource_byname(to_platform_device(ddata->dev),
672 IORESOURCE_MEM, name);
674 ddata->offsets[reg] = -ENODEV;
679 ddata->offsets[reg] = res->start - ddata->module_pa;
680 if (reg == SYSC_REVISION)
681 sysc_check_quirk_16bit(ddata, res);
686 static int sysc_parse_registers(struct sysc *ddata)
690 for (i = 0; i < SYSC_MAX_REGS; i++) {
691 error = sysc_parse_one(ddata, i);
700 * sysc_check_registers - check for misconfigured register overlaps
701 * @ddata: device driver data
703 static int sysc_check_registers(struct sysc *ddata)
705 int i, j, nr_regs = 0, nr_matches = 0;
707 for (i = 0; i < SYSC_MAX_REGS; i++) {
708 if (ddata->offsets[i] < 0)
711 if (ddata->offsets[i] > (ddata->module_size - 4)) {
712 dev_err(ddata->dev, "register outside module range");
717 for (j = 0; j < SYSC_MAX_REGS; j++) {
718 if (ddata->offsets[j] < 0)
721 if (ddata->offsets[i] == ddata->offsets[j])
727 if (nr_matches > nr_regs) {
728 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
729 nr_regs, nr_matches);
738 * syc_ioremap - ioremap register space for the interconnect target module
739 * @ddata: device driver data
741 * Note that the interconnect target module registers can be anywhere
742 * within the interconnect target module range. For example, SGX has
743 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
744 * has them at offset 0x1200 in the CPSW_WR child. Usually the
745 * the interconnect target module registers are at the beginning of
746 * the module range though.
748 static int sysc_ioremap(struct sysc *ddata)
752 if (ddata->offsets[SYSC_REVISION] < 0 &&
753 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
754 ddata->offsets[SYSC_SYSSTATUS] < 0) {
755 size = ddata->module_size;
757 size = max3(ddata->offsets[SYSC_REVISION],
758 ddata->offsets[SYSC_SYSCONFIG],
759 ddata->offsets[SYSC_SYSSTATUS]);
764 if ((size + sizeof(u32)) > ddata->module_size)
765 size = ddata->module_size;
768 ddata->module_va = devm_ioremap(ddata->dev,
771 if (!ddata->module_va)
778 * sysc_map_and_check_registers - ioremap and check device registers
779 * @ddata: device driver data
781 static int sysc_map_and_check_registers(struct sysc *ddata)
785 error = sysc_parse_and_check_child_range(ddata);
789 sysc_check_children(ddata);
791 error = sysc_parse_registers(ddata);
795 error = sysc_ioremap(ddata);
799 error = sysc_check_registers(ddata);
807 * sysc_show_rev - read and show interconnect target module revision
808 * @bufp: buffer to print the information to
809 * @ddata: device driver data
811 static int sysc_show_rev(char *bufp, struct sysc *ddata)
815 if (ddata->offsets[SYSC_REVISION] < 0)
816 return sprintf(bufp, ":NA");
818 len = sprintf(bufp, ":%08x", ddata->revision);
823 static int sysc_show_reg(struct sysc *ddata,
824 char *bufp, enum sysc_registers reg)
826 if (ddata->offsets[reg] < 0)
827 return sprintf(bufp, ":NA");
829 return sprintf(bufp, ":%x", ddata->offsets[reg]);
832 static int sysc_show_name(char *bufp, struct sysc *ddata)
837 return sprintf(bufp, ":%s", ddata->name);
841 * sysc_show_registers - show information about interconnect target module
842 * @ddata: device driver data
844 static void sysc_show_registers(struct sysc *ddata)
850 for (i = 0; i < SYSC_MAX_REGS; i++)
851 bufp += sysc_show_reg(ddata, bufp, i);
853 bufp += sysc_show_rev(bufp, ddata);
854 bufp += sysc_show_name(bufp, ddata);
856 dev_dbg(ddata->dev, "%llx:%x%s\n",
857 ddata->module_pa, ddata->module_size,
861 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
862 #define SYSC_CLOCACT_ICK 2
864 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
865 static int sysc_enable_module(struct device *dev)
868 const struct sysc_regbits *regbits;
869 u32 reg, idlemodes, best_mode;
871 ddata = dev_get_drvdata(dev);
872 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
875 regbits = ddata->cap->regbits;
876 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
878 /* Set CLOCKACTIVITY, we only use it for ick */
879 if (regbits->clkact_shift >= 0 &&
880 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
881 ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
882 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
885 idlemodes = ddata->cfg.sidlemodes;
886 if (!idlemodes || regbits->sidle_shift < 0)
889 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
890 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
891 best_mode = SYSC_IDLE_NO;
893 best_mode = fls(ddata->cfg.sidlemodes) - 1;
894 if (best_mode > SYSC_IDLE_MASK) {
895 dev_err(dev, "%s: invalid sidlemode\n", __func__);
900 if (regbits->enwkup_shift >= 0 &&
901 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
902 reg |= BIT(regbits->enwkup_shift);
905 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
906 reg |= best_mode << regbits->sidle_shift;
907 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
911 idlemodes = ddata->cfg.midlemodes;
912 if (!idlemodes || regbits->midle_shift < 0)
915 best_mode = fls(ddata->cfg.midlemodes) - 1;
916 if (best_mode > SYSC_IDLE_MASK) {
917 dev_err(dev, "%s: invalid midlemode\n", __func__);
921 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
922 reg |= best_mode << regbits->midle_shift;
923 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
926 /* Autoidle bit must enabled separately if available */
927 if (regbits->autoidle_shift >= 0 &&
928 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
929 reg |= 1 << regbits->autoidle_shift;
930 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
933 if (ddata->module_enable_quirk)
934 ddata->module_enable_quirk(ddata);
939 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
941 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
942 *best_mode = SYSC_IDLE_SMART_WKUP;
943 else if (idlemodes & BIT(SYSC_IDLE_SMART))
944 *best_mode = SYSC_IDLE_SMART;
945 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
946 *best_mode = SYSC_IDLE_FORCE;
953 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
954 static int sysc_disable_module(struct device *dev)
957 const struct sysc_regbits *regbits;
958 u32 reg, idlemodes, best_mode;
961 ddata = dev_get_drvdata(dev);
962 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
965 regbits = ddata->cap->regbits;
966 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
969 idlemodes = ddata->cfg.midlemodes;
970 if (!idlemodes || regbits->midle_shift < 0)
973 ret = sysc_best_idle_mode(idlemodes, &best_mode);
975 dev_err(dev, "%s: invalid midlemode\n", __func__);
979 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
980 reg |= best_mode << regbits->midle_shift;
981 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
985 idlemodes = ddata->cfg.sidlemodes;
986 if (!idlemodes || regbits->sidle_shift < 0)
989 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
990 best_mode = SYSC_IDLE_FORCE;
992 ret = sysc_best_idle_mode(idlemodes, &best_mode);
994 dev_err(dev, "%s: invalid sidlemode\n", __func__);
999 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1000 reg |= best_mode << regbits->sidle_shift;
1001 if (regbits->autoidle_shift >= 0 &&
1002 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1003 reg |= 1 << regbits->autoidle_shift;
1004 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1009 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1012 struct ti_sysc_platform_data *pdata;
1015 pdata = dev_get_platdata(ddata->dev);
1019 if (!pdata->idle_module)
1022 error = pdata->idle_module(dev, &ddata->cookie);
1024 dev_err(dev, "%s: could not idle: %i\n",
1027 reset_control_assert(ddata->rsts);
1032 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1035 struct ti_sysc_platform_data *pdata;
1038 reset_control_deassert(ddata->rsts);
1040 pdata = dev_get_platdata(ddata->dev);
1044 if (!pdata->enable_module)
1047 error = pdata->enable_module(dev, &ddata->cookie);
1049 dev_err(dev, "%s: could not enable: %i\n",
1055 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1060 ddata = dev_get_drvdata(dev);
1062 if (!ddata->enabled)
1065 sysc_clkdm_deny_idle(ddata);
1067 if (ddata->legacy_mode) {
1068 error = sysc_runtime_suspend_legacy(dev, ddata);
1070 goto err_allow_idle;
1072 error = sysc_disable_module(dev);
1074 goto err_allow_idle;
1077 sysc_disable_main_clocks(ddata);
1079 if (sysc_opt_clks_needed(ddata))
1080 sysc_disable_opt_clocks(ddata);
1082 ddata->enabled = false;
1085 reset_control_assert(ddata->rsts);
1087 sysc_clkdm_allow_idle(ddata);
1092 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1097 ddata = dev_get_drvdata(dev);
1103 sysc_clkdm_deny_idle(ddata);
1105 reset_control_deassert(ddata->rsts);
1107 if (sysc_opt_clks_needed(ddata)) {
1108 error = sysc_enable_opt_clocks(ddata);
1110 goto err_allow_idle;
1113 error = sysc_enable_main_clocks(ddata);
1115 goto err_opt_clocks;
1117 if (ddata->legacy_mode) {
1118 error = sysc_runtime_resume_legacy(dev, ddata);
1120 goto err_main_clocks;
1122 error = sysc_enable_module(dev);
1124 goto err_main_clocks;
1127 ddata->enabled = true;
1129 sysc_clkdm_allow_idle(ddata);
1134 sysc_disable_main_clocks(ddata);
1136 if (sysc_opt_clks_needed(ddata))
1137 sysc_disable_opt_clocks(ddata);
1139 sysc_clkdm_allow_idle(ddata);
1144 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1148 ddata = dev_get_drvdata(dev);
1150 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1153 return pm_runtime_force_suspend(dev);
1156 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1160 ddata = dev_get_drvdata(dev);
1162 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1165 return pm_runtime_force_resume(dev);
1168 static const struct dev_pm_ops sysc_pm_ops = {
1169 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1170 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1171 sysc_runtime_resume,
1175 /* Module revision register based quirks */
1176 struct sysc_revision_quirk {
1187 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1188 optrev_val, optrevmask, optquirkmask) \
1190 .name = (optname), \
1191 .base = (optbase), \
1192 .rev_offset = (optrev), \
1193 .sysc_offset = (optsysc), \
1194 .syss_offset = (optsyss), \
1195 .revision = (optrev_val), \
1196 .revision_mask = (optrevmask), \
1197 .quirks = (optquirkmask), \
1200 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1201 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1202 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1203 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1204 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1205 SYSC_QUIRK_LEGACY_IDLE),
1206 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1207 SYSC_QUIRK_LEGACY_IDLE),
1208 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1209 SYSC_QUIRK_LEGACY_IDLE),
1210 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1211 SYSC_QUIRK_LEGACY_IDLE),
1212 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1213 SYSC_QUIRK_LEGACY_IDLE),
1214 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1216 /* Some timers on omap4 and later */
1217 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
1219 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
1221 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1222 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1223 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1224 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1225 /* Uarts on omap4 and later */
1226 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1227 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1228 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1229 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1231 /* Quirks that need to be set based on the module address */
1232 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1233 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1234 SYSC_QUIRK_SWSUP_SIDLE),
1236 /* Quirks that need to be set based on detected module */
1237 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1238 SYSC_MODULE_QUIRK_HDQ1W),
1239 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1240 SYSC_MODULE_QUIRK_HDQ1W),
1241 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1242 SYSC_MODULE_QUIRK_I2C),
1243 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1244 SYSC_MODULE_QUIRK_I2C),
1245 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1246 SYSC_MODULE_QUIRK_I2C),
1247 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1248 SYSC_MODULE_QUIRK_I2C),
1249 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1250 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1251 SYSC_MODULE_QUIRK_SGX),
1252 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1253 SYSC_MODULE_QUIRK_WDT),
1256 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
1257 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
1258 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
1259 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
1260 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1261 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1263 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1264 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
1265 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1266 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1267 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1268 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1269 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
1270 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1271 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
1272 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1273 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
1274 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
1275 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1276 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
1277 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
1278 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1279 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1280 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1281 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
1282 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1283 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
1284 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
1285 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
1286 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
1287 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1288 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
1289 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1290 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1291 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
1292 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
1293 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
1294 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1295 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1296 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1297 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1298 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1299 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1300 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
1301 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1302 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
1303 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1304 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1305 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1306 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1307 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1309 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
1314 * Early quirks based on module base and register offsets only that are
1315 * needed before the module revision can be read
1317 static void sysc_init_early_quirks(struct sysc *ddata)
1319 const struct sysc_revision_quirk *q;
1322 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1323 q = &sysc_revision_quirks[i];
1328 if (q->base != ddata->module_pa)
1331 if (q->rev_offset >= 0 &&
1332 q->rev_offset != ddata->offsets[SYSC_REVISION])
1335 if (q->sysc_offset >= 0 &&
1336 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1339 if (q->syss_offset >= 0 &&
1340 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1343 ddata->name = q->name;
1344 ddata->cfg.quirks |= q->quirks;
1348 /* Quirks that also consider the revision register value */
1349 static void sysc_init_revision_quirks(struct sysc *ddata)
1351 const struct sysc_revision_quirk *q;
1354 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1355 q = &sysc_revision_quirks[i];
1357 if (q->base && q->base != ddata->module_pa)
1360 if (q->rev_offset >= 0 &&
1361 q->rev_offset != ddata->offsets[SYSC_REVISION])
1364 if (q->sysc_offset >= 0 &&
1365 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1368 if (q->syss_offset >= 0 &&
1369 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1372 if (q->revision == ddata->revision ||
1373 (q->revision & q->revision_mask) ==
1374 (ddata->revision & q->revision_mask)) {
1375 ddata->name = q->name;
1376 ddata->cfg.quirks |= q->quirks;
1381 /* 1-wire needs module's internal clocks enabled for reset */
1382 static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
1384 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1387 val = sysc_read(ddata, offset);
1389 sysc_write(ddata, offset, val);
1392 /* I2C needs extra enable bit toggling for reset */
1393 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1398 /* I2C_CON, omap2/3 is different from omap4 and later */
1399 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1405 val = sysc_read(ddata, offset);
1410 sysc_write(ddata, offset, val);
1413 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1415 sysc_clk_quirk_i2c(ddata, true);
1418 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1420 sysc_clk_quirk_i2c(ddata, false);
1423 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1424 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1426 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1427 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1429 sysc_write(ddata, offset, val);
1432 /* Watchdog timer needs a disable sequence after reset */
1433 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1435 int wps, spr, error;
1441 sysc_write(ddata, spr, 0xaaaa);
1442 error = readl_poll_timeout(ddata->module_va + wps, val,
1444 MAX_MODULE_SOFTRESET_WAIT);
1446 dev_warn(ddata->dev, "wdt disable spr failed\n");
1448 sysc_write(ddata, wps, 0x5555);
1449 error = readl_poll_timeout(ddata->module_va + wps, val,
1451 MAX_MODULE_SOFTRESET_WAIT);
1453 dev_warn(ddata->dev, "wdt disable wps failed\n");
1456 static void sysc_init_module_quirks(struct sysc *ddata)
1458 if (ddata->legacy_mode || !ddata->name)
1461 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1462 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
1467 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1468 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1469 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1474 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1475 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1477 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT)
1478 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1481 static int sysc_clockdomain_init(struct sysc *ddata)
1483 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1484 struct clk *fck = NULL, *ick = NULL;
1487 if (!pdata || !pdata->init_clockdomain)
1490 switch (ddata->nr_clocks) {
1492 ick = ddata->clocks[SYSC_ICK];
1495 fck = ddata->clocks[SYSC_FCK];
1501 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1502 if (!error || error == -ENODEV)
1509 * Note that pdata->init_module() typically does a reset first. After
1510 * pdata->init_module() is done, PM runtime can be used for the interconnect
1513 static int sysc_legacy_init(struct sysc *ddata)
1515 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1518 if (!pdata || !pdata->init_module)
1521 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1522 if (error == -EEXIST)
1529 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1530 * @ddata: device driver data
1531 * @reset: reset before deassert
1533 * A module can have both OCP softreset control and external rstctrl.
1534 * If more complicated rstctrl resets are needed, please handle these
1535 * directly from the child device driver and map only the module reset
1536 * for the parent interconnect target module device.
1538 * Automatic reset of the module on init can be skipped with the
1539 * "ti,no-reset-on-init" device tree property.
1541 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1549 error = reset_control_assert(ddata->rsts);
1554 reset_control_deassert(ddata->rsts);
1560 * Note that the caller must ensure the interconnect target module is enabled
1561 * before calling reset. Otherwise reset will not complete.
1563 static int sysc_reset(struct sysc *ddata)
1565 int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
1566 u32 sysc_mask, syss_done;
1568 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1569 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1571 if (ddata->legacy_mode || sysc_offset < 0 ||
1572 ddata->cap->regbits->srst_shift < 0 ||
1573 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1576 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1578 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1581 syss_done = ddata->cfg.syss_mask;
1583 if (ddata->clk_disable_quirk)
1584 ddata->clk_disable_quirk(ddata);
1586 sysc_val = sysc_read_sysconfig(ddata);
1587 sysc_val |= sysc_mask;
1588 sysc_write(ddata, sysc_offset, sysc_val);
1590 if (ddata->clk_enable_quirk)
1591 ddata->clk_enable_quirk(ddata);
1593 /* Poll on reset status */
1594 if (syss_offset >= 0) {
1595 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1596 (rstval & ddata->cfg.syss_mask) ==
1598 100, MAX_MODULE_SOFTRESET_WAIT);
1600 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1601 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1602 !(rstval & sysc_mask),
1603 100, MAX_MODULE_SOFTRESET_WAIT);
1606 if (ddata->reset_done_quirk)
1607 ddata->reset_done_quirk(ddata);
1613 * At this point the module is configured enough to read the revision but
1614 * module may not be completely configured yet to use PM runtime. Enable
1615 * all clocks directly during init to configure the quirks needed for PM
1616 * runtime based on the revision register.
1618 static int sysc_init_module(struct sysc *ddata)
1621 bool manage_clocks = true;
1623 error = sysc_rstctrl_reset_deassert(ddata, false);
1627 if (ddata->cfg.quirks &
1628 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1629 manage_clocks = false;
1631 error = sysc_clockdomain_init(ddata);
1635 if (manage_clocks) {
1636 sysc_clkdm_deny_idle(ddata);
1638 error = sysc_enable_opt_clocks(ddata);
1642 error = sysc_enable_main_clocks(ddata);
1644 goto err_opt_clocks;
1647 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1648 error = sysc_rstctrl_reset_deassert(ddata, true);
1650 goto err_main_clocks;
1653 ddata->revision = sysc_read_revision(ddata);
1654 sysc_init_revision_quirks(ddata);
1655 sysc_init_module_quirks(ddata);
1657 if (ddata->legacy_mode) {
1658 error = sysc_legacy_init(ddata);
1660 goto err_main_clocks;
1663 if (!ddata->legacy_mode && manage_clocks) {
1664 error = sysc_enable_module(ddata->dev);
1666 goto err_main_clocks;
1669 error = sysc_reset(ddata);
1671 dev_err(ddata->dev, "Reset failed with %d\n", error);
1673 if (!ddata->legacy_mode && manage_clocks)
1674 sysc_disable_module(ddata->dev);
1678 sysc_disable_main_clocks(ddata);
1680 if (manage_clocks) {
1681 sysc_disable_opt_clocks(ddata);
1682 sysc_clkdm_allow_idle(ddata);
1688 static int sysc_init_sysc_mask(struct sysc *ddata)
1690 struct device_node *np = ddata->dev->of_node;
1694 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1698 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1703 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1706 struct device_node *np = ddata->dev->of_node;
1707 struct property *prop;
1711 of_property_for_each_u32(np, name, prop, p, val) {
1712 if (val >= SYSC_NR_IDLEMODES) {
1713 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1716 *idlemodes |= (1 << val);
1722 static int sysc_init_idlemodes(struct sysc *ddata)
1726 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1731 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1740 * Only some devices on omap4 and later have SYSCONFIG reset done
1741 * bit. We can detect this if there is no SYSSTATUS at all, or the
1742 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1743 * have multiple bits for the child devices like OHCI and EHCI.
1744 * Depends on SYSC being parsed first.
1746 static int sysc_init_syss_mask(struct sysc *ddata)
1748 struct device_node *np = ddata->dev->of_node;
1752 error = of_property_read_u32(np, "ti,syss-mask", &val);
1754 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1755 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1756 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1757 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1762 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1763 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1765 ddata->cfg.syss_mask = val;
1771 * Many child device drivers need to have fck and opt clocks available
1772 * to get the clock rate for device internal configuration etc.
1774 static int sysc_child_add_named_clock(struct sysc *ddata,
1775 struct device *child,
1779 struct clk_lookup *l;
1785 clk = clk_get(child, name);
1792 clk = clk_get(ddata->dev, name);
1796 l = clkdev_create(clk, name, dev_name(child));
1805 static int sysc_child_add_clocks(struct sysc *ddata,
1806 struct device *child)
1810 for (i = 0; i < ddata->nr_clocks; i++) {
1811 error = sysc_child_add_named_clock(ddata,
1813 ddata->clock_roles[i]);
1814 if (error && error != -EEXIST) {
1815 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1816 ddata->clock_roles[i], error);
1825 static struct device_type sysc_device_type = {
1828 static struct sysc *sysc_child_to_parent(struct device *dev)
1830 struct device *parent = dev->parent;
1832 if (!parent || parent->type != &sysc_device_type)
1835 return dev_get_drvdata(parent);
1838 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1843 ddata = sysc_child_to_parent(dev);
1845 error = pm_generic_runtime_suspend(dev);
1849 if (!ddata->enabled)
1852 return sysc_runtime_suspend(ddata->dev);
1855 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1860 ddata = sysc_child_to_parent(dev);
1862 if (!ddata->enabled) {
1863 error = sysc_runtime_resume(ddata->dev);
1866 "%s error: %i\n", __func__, error);
1869 return pm_generic_runtime_resume(dev);
1872 #ifdef CONFIG_PM_SLEEP
1873 static int sysc_child_suspend_noirq(struct device *dev)
1878 ddata = sysc_child_to_parent(dev);
1880 dev_dbg(ddata->dev, "%s %s\n", __func__,
1881 ddata->name ? ddata->name : "");
1883 error = pm_generic_suspend_noirq(dev);
1885 dev_err(dev, "%s error at %i: %i\n",
1886 __func__, __LINE__, error);
1891 if (!pm_runtime_status_suspended(dev)) {
1892 error = pm_generic_runtime_suspend(dev);
1894 dev_dbg(dev, "%s busy at %i: %i\n",
1895 __func__, __LINE__, error);
1900 error = sysc_runtime_suspend(ddata->dev);
1902 dev_err(dev, "%s error at %i: %i\n",
1903 __func__, __LINE__, error);
1908 ddata->child_needs_resume = true;
1914 static int sysc_child_resume_noirq(struct device *dev)
1919 ddata = sysc_child_to_parent(dev);
1921 dev_dbg(ddata->dev, "%s %s\n", __func__,
1922 ddata->name ? ddata->name : "");
1924 if (ddata->child_needs_resume) {
1925 ddata->child_needs_resume = false;
1927 error = sysc_runtime_resume(ddata->dev);
1930 "%s runtime resume error: %i\n",
1933 error = pm_generic_runtime_resume(dev);
1936 "%s generic runtime resume: %i\n",
1940 return pm_generic_resume_noirq(dev);
1944 static struct dev_pm_domain sysc_child_pm_domain = {
1946 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1947 sysc_child_runtime_resume,
1949 USE_PLATFORM_PM_SLEEP_OPS
1950 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1951 sysc_child_resume_noirq)
1956 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1957 * @ddata: device driver data
1958 * @child: child device driver
1960 * Allow idle for child devices as done with _od_runtime_suspend().
1961 * Otherwise many child devices will not idle because of the permanent
1962 * parent usecount set in pm_runtime_irq_safe().
1964 * Note that the long term solution is to just modify the child device
1965 * drivers to not set pm_runtime_irq_safe() and then this can be just
1968 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1970 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1971 dev_pm_domain_set(child, &sysc_child_pm_domain);
1974 static int sysc_notifier_call(struct notifier_block *nb,
1975 unsigned long event, void *device)
1977 struct device *dev = device;
1981 ddata = sysc_child_to_parent(dev);
1986 case BUS_NOTIFY_ADD_DEVICE:
1987 error = sysc_child_add_clocks(ddata, dev);
1990 sysc_legacy_idle_quirk(ddata, dev);
1999 static struct notifier_block sysc_nb = {
2000 .notifier_call = sysc_notifier_call,
2003 /* Device tree configured quirks */
2004 struct sysc_dts_quirk {
2009 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2010 { .name = "ti,no-idle-on-init",
2011 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2012 { .name = "ti,no-reset-on-init",
2013 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2014 { .name = "ti,no-idle",
2015 .mask = SYSC_QUIRK_NO_IDLE, },
2018 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2021 const struct property *prop;
2024 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2025 const char *name = sysc_dts_quirks[i].name;
2027 prop = of_get_property(np, name, &len);
2031 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2033 dev_warn(ddata->dev,
2034 "dts flag should be at module level for %s\n",
2040 static int sysc_init_dts_quirks(struct sysc *ddata)
2042 struct device_node *np = ddata->dev->of_node;
2046 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2048 sysc_parse_dts_quirks(ddata, np, false);
2049 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2052 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2056 ddata->cfg.srst_udelay = (u8)val;
2062 static void sysc_unprepare(struct sysc *ddata)
2069 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2070 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2071 clk_unprepare(ddata->clocks[i]);
2076 * Common sysc register bits found on omap2, also known as type1
2078 static const struct sysc_regbits sysc_regbits_omap2 = {
2079 .dmadisable_shift = -ENODEV,
2086 .autoidle_shift = 0,
2089 static const struct sysc_capabilities sysc_omap2 = {
2090 .type = TI_SYSC_OMAP2,
2091 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2092 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2093 SYSC_OMAP2_AUTOIDLE,
2094 .regbits = &sysc_regbits_omap2,
2097 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2098 static const struct sysc_capabilities sysc_omap2_timer = {
2099 .type = TI_SYSC_OMAP2_TIMER,
2100 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2101 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2102 SYSC_OMAP2_AUTOIDLE,
2103 .regbits = &sysc_regbits_omap2,
2104 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2108 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2109 * with different sidle position
2111 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2112 .dmadisable_shift = -ENODEV,
2113 .midle_shift = -ENODEV,
2115 .clkact_shift = -ENODEV,
2116 .enwkup_shift = -ENODEV,
2118 .autoidle_shift = 0,
2119 .emufree_shift = -ENODEV,
2122 static const struct sysc_capabilities sysc_omap3_sham = {
2123 .type = TI_SYSC_OMAP3_SHAM,
2124 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2125 .regbits = &sysc_regbits_omap3_sham,
2129 * AES register bits found on omap3 and later, a variant of
2130 * sysc_regbits_omap2 with different sidle position
2132 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2133 .dmadisable_shift = -ENODEV,
2134 .midle_shift = -ENODEV,
2136 .clkact_shift = -ENODEV,
2137 .enwkup_shift = -ENODEV,
2139 .autoidle_shift = 0,
2140 .emufree_shift = -ENODEV,
2143 static const struct sysc_capabilities sysc_omap3_aes = {
2144 .type = TI_SYSC_OMAP3_AES,
2145 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2146 .regbits = &sysc_regbits_omap3_aes,
2150 * Common sysc register bits found on omap4, also known as type2
2152 static const struct sysc_regbits sysc_regbits_omap4 = {
2153 .dmadisable_shift = 16,
2156 .clkact_shift = -ENODEV,
2157 .enwkup_shift = -ENODEV,
2160 .autoidle_shift = -ENODEV,
2163 static const struct sysc_capabilities sysc_omap4 = {
2164 .type = TI_SYSC_OMAP4,
2165 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2166 SYSC_OMAP4_SOFTRESET,
2167 .regbits = &sysc_regbits_omap4,
2170 static const struct sysc_capabilities sysc_omap4_timer = {
2171 .type = TI_SYSC_OMAP4_TIMER,
2172 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2173 SYSC_OMAP4_SOFTRESET,
2174 .regbits = &sysc_regbits_omap4,
2178 * Common sysc register bits found on omap4, also known as type3
2180 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2181 .dmadisable_shift = -ENODEV,
2184 .clkact_shift = -ENODEV,
2185 .enwkup_shift = -ENODEV,
2186 .srst_shift = -ENODEV,
2187 .emufree_shift = -ENODEV,
2188 .autoidle_shift = -ENODEV,
2191 static const struct sysc_capabilities sysc_omap4_simple = {
2192 .type = TI_SYSC_OMAP4_SIMPLE,
2193 .regbits = &sysc_regbits_omap4_simple,
2197 * SmartReflex sysc found on omap34xx
2199 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2200 .dmadisable_shift = -ENODEV,
2201 .midle_shift = -ENODEV,
2202 .sidle_shift = -ENODEV,
2204 .enwkup_shift = -ENODEV,
2205 .srst_shift = -ENODEV,
2206 .emufree_shift = -ENODEV,
2207 .autoidle_shift = -ENODEV,
2210 static const struct sysc_capabilities sysc_34xx_sr = {
2211 .type = TI_SYSC_OMAP34XX_SR,
2212 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2213 .regbits = &sysc_regbits_omap34xx_sr,
2214 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2215 SYSC_QUIRK_LEGACY_IDLE,
2219 * SmartReflex sysc found on omap36xx and later
2221 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2222 .dmadisable_shift = -ENODEV,
2223 .midle_shift = -ENODEV,
2225 .clkact_shift = -ENODEV,
2227 .srst_shift = -ENODEV,
2228 .emufree_shift = -ENODEV,
2229 .autoidle_shift = -ENODEV,
2232 static const struct sysc_capabilities sysc_36xx_sr = {
2233 .type = TI_SYSC_OMAP36XX_SR,
2234 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2235 .regbits = &sysc_regbits_omap36xx_sr,
2236 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2239 static const struct sysc_capabilities sysc_omap4_sr = {
2240 .type = TI_SYSC_OMAP4_SR,
2241 .regbits = &sysc_regbits_omap36xx_sr,
2242 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2246 * McASP register bits found on omap4 and later
2248 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2249 .dmadisable_shift = -ENODEV,
2250 .midle_shift = -ENODEV,
2252 .clkact_shift = -ENODEV,
2253 .enwkup_shift = -ENODEV,
2254 .srst_shift = -ENODEV,
2255 .emufree_shift = -ENODEV,
2256 .autoidle_shift = -ENODEV,
2259 static const struct sysc_capabilities sysc_omap4_mcasp = {
2260 .type = TI_SYSC_OMAP4_MCASP,
2261 .regbits = &sysc_regbits_omap4_mcasp,
2262 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2266 * McASP found on dra7 and later
2268 static const struct sysc_capabilities sysc_dra7_mcasp = {
2269 .type = TI_SYSC_OMAP4_SIMPLE,
2270 .regbits = &sysc_regbits_omap4_simple,
2271 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2275 * FS USB host found on omap4 and later
2277 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2278 .dmadisable_shift = -ENODEV,
2279 .midle_shift = -ENODEV,
2281 .clkact_shift = -ENODEV,
2283 .srst_shift = -ENODEV,
2284 .emufree_shift = -ENODEV,
2285 .autoidle_shift = -ENODEV,
2288 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2289 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2290 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2291 .regbits = &sysc_regbits_omap4_usb_host_fs,
2294 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2295 .dmadisable_shift = -ENODEV,
2296 .midle_shift = -ENODEV,
2297 .sidle_shift = -ENODEV,
2298 .clkact_shift = -ENODEV,
2301 .emufree_shift = -ENODEV,
2302 .autoidle_shift = -ENODEV,
2305 static const struct sysc_capabilities sysc_dra7_mcan = {
2306 .type = TI_SYSC_DRA7_MCAN,
2307 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2308 .regbits = &sysc_regbits_dra7_mcan,
2309 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2312 static int sysc_init_pdata(struct sysc *ddata)
2314 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2315 struct ti_sysc_module_data *mdata;
2320 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2324 if (ddata->legacy_mode) {
2325 mdata->name = ddata->legacy_mode;
2326 mdata->module_pa = ddata->module_pa;
2327 mdata->module_size = ddata->module_size;
2328 mdata->offsets = ddata->offsets;
2329 mdata->nr_offsets = SYSC_MAX_REGS;
2330 mdata->cap = ddata->cap;
2331 mdata->cfg = &ddata->cfg;
2334 ddata->mdata = mdata;
2339 static int sysc_init_match(struct sysc *ddata)
2341 const struct sysc_capabilities *cap;
2343 cap = of_device_get_match_data(ddata->dev);
2349 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2354 static void ti_sysc_idle(struct work_struct *work)
2358 ddata = container_of(work, struct sysc, idle_work.work);
2360 if (pm_runtime_active(ddata->dev))
2361 pm_runtime_put_sync(ddata->dev);
2364 static const struct of_device_id sysc_match_table[] = {
2365 { .compatible = "simple-bus", },
2369 static int sysc_probe(struct platform_device *pdev)
2371 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2375 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2379 ddata->dev = &pdev->dev;
2380 platform_set_drvdata(pdev, ddata);
2382 error = sysc_init_match(ddata);
2386 error = sysc_init_dts_quirks(ddata);
2390 error = sysc_map_and_check_registers(ddata);
2394 error = sysc_init_sysc_mask(ddata);
2398 error = sysc_init_idlemodes(ddata);
2402 error = sysc_init_syss_mask(ddata);
2406 error = sysc_init_pdata(ddata);
2410 sysc_init_early_quirks(ddata);
2412 error = sysc_get_clocks(ddata);
2416 error = sysc_init_resets(ddata);
2420 error = sysc_init_module(ddata);
2424 pm_runtime_enable(ddata->dev);
2425 error = pm_runtime_get_sync(ddata->dev);
2427 pm_runtime_put_noidle(ddata->dev);
2428 pm_runtime_disable(ddata->dev);
2432 /* Balance reset counts */
2434 reset_control_assert(ddata->rsts);
2436 sysc_show_registers(ddata);
2438 ddata->dev->type = &sysc_device_type;
2439 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2440 pdata ? pdata->auxdata : NULL,
2445 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2447 /* At least earlycon won't survive without deferred idle */
2448 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT |
2449 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2450 schedule_delayed_work(&ddata->idle_work, 3000);
2452 pm_runtime_put(&pdev->dev);
2458 pm_runtime_put_sync(&pdev->dev);
2459 pm_runtime_disable(&pdev->dev);
2461 sysc_unprepare(ddata);
2466 static int sysc_remove(struct platform_device *pdev)
2468 struct sysc *ddata = platform_get_drvdata(pdev);
2471 cancel_delayed_work_sync(&ddata->idle_work);
2473 error = pm_runtime_get_sync(ddata->dev);
2475 pm_runtime_put_noidle(ddata->dev);
2476 pm_runtime_disable(ddata->dev);
2480 of_platform_depopulate(&pdev->dev);
2482 pm_runtime_put_sync(&pdev->dev);
2483 pm_runtime_disable(&pdev->dev);
2484 reset_control_assert(ddata->rsts);
2487 sysc_unprepare(ddata);
2492 static const struct of_device_id sysc_match[] = {
2493 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2494 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2495 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2496 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2497 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2498 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2499 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2500 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2501 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2502 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2503 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2504 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2505 { .compatible = "ti,sysc-usb-host-fs",
2506 .data = &sysc_omap4_usb_host_fs, },
2507 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2510 MODULE_DEVICE_TABLE(of, sysc_match);
2512 static struct platform_driver sysc_driver = {
2513 .probe = sysc_probe,
2514 .remove = sysc_remove,
2517 .of_match_table = sysc_match,
2522 static int __init sysc_init(void)
2524 bus_register_notifier(&platform_bus_type, &sysc_nb);
2526 return platform_driver_register(&sysc_driver);
2528 module_init(sysc_init);
2530 static void __exit sysc_exit(void)
2532 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2533 platform_driver_unregister(&sysc_driver);
2535 module_exit(sysc_exit);
2537 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2538 MODULE_LICENSE("GPL v2");