1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_domain.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/slab.h>
18 #include <linux/iopoll.h>
20 #include <linux/platform_data/ti-sysc.h>
22 #include <dt-bindings/bus/ti-sysc.h>
24 #define MAX_MODULE_SOFTRESET_WAIT 10000
26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
47 #define SYSC_IDLEMODE_MASK 3
48 #define SYSC_CLOCKACTIVITY_MASK 3
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
57 * @mdata: ti-sysc to hwmod translation data for a module
58 * @clocks: clocks used by the interconnect target module
59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
61 * @rsts: resets used by the interconnect target module
62 * @legacy_mode: configured for legacy mode if set
63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
65 * @cookie: data used by legacy platform callbacks
66 * @name: name if available
67 * @revision: interconnect target module revision
68 * @enabled: sysc runtime enabled status
69 * @needs_resume: runtime resume needed on resume from suspend
70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
73 * @clk_enable_quirk: module specific clock enable quirk
74 * @clk_disable_quirk: module specific clock disable quirk
75 * @reset_done_quirk: module specific reset done quirk
76 * @module_enable_quirk: module specific enable quirk
77 * @module_disable_quirk: module specific disable quirk
83 void __iomem *module_va;
84 int offsets[SYSC_MAX_REGS];
85 struct ti_sysc_module_data *mdata;
87 const char **clock_roles;
89 struct reset_control *rsts;
90 const char *legacy_mode;
91 const struct sysc_capabilities *cap;
92 struct sysc_config cfg;
93 struct ti_sysc_cookie cookie;
96 unsigned int enabled:1;
97 unsigned int needs_resume:1;
98 unsigned int child_needs_resume:1;
99 struct delayed_work idle_work;
100 void (*clk_enable_quirk)(struct sysc *sysc);
101 void (*clk_disable_quirk)(struct sysc *sysc);
102 void (*reset_done_quirk)(struct sysc *sysc);
103 void (*module_enable_quirk)(struct sysc *sysc);
104 void (*module_disable_quirk)(struct sysc *sysc);
107 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
110 static void sysc_write(struct sysc *ddata, int offset, u32 value)
112 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
113 writew_relaxed(value & 0xffff, ddata->module_va + offset);
115 /* Only i2c revision has LO and HI register with stride of 4 */
116 if (ddata->offsets[SYSC_REVISION] >= 0 &&
117 offset == ddata->offsets[SYSC_REVISION]) {
118 u16 hi = value >> 16;
120 writew_relaxed(hi, ddata->module_va + offset + 4);
126 writel_relaxed(value, ddata->module_va + offset);
129 static u32 sysc_read(struct sysc *ddata, int offset)
131 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
134 val = readw_relaxed(ddata->module_va + offset);
136 /* Only i2c revision has LO and HI register with stride of 4 */
137 if (ddata->offsets[SYSC_REVISION] >= 0 &&
138 offset == ddata->offsets[SYSC_REVISION]) {
139 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
147 return readl_relaxed(ddata->module_va + offset);
150 static bool sysc_opt_clks_needed(struct sysc *ddata)
152 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
155 static u32 sysc_read_revision(struct sysc *ddata)
157 int offset = ddata->offsets[SYSC_REVISION];
162 return sysc_read(ddata, offset);
165 static u32 sysc_read_sysconfig(struct sysc *ddata)
167 int offset = ddata->offsets[SYSC_SYSCONFIG];
172 return sysc_read(ddata, offset);
175 static u32 sysc_read_sysstatus(struct sysc *ddata)
177 int offset = ddata->offsets[SYSC_SYSSTATUS];
182 return sysc_read(ddata, offset);
185 static int sysc_add_named_clock_from_child(struct sysc *ddata,
187 const char *optfck_name)
189 struct device_node *np = ddata->dev->of_node;
190 struct device_node *child;
191 struct clk_lookup *cl;
200 /* Does the clock alias already exist? */
201 clock = of_clk_get_by_name(np, n);
202 if (!IS_ERR(clock)) {
208 child = of_get_next_available_child(np, NULL);
212 clock = devm_get_clk_from_child(ddata->dev, child, name);
214 return PTR_ERR(clock);
217 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
218 * limit for clk_get(). If cl ever needs to be freed, it should be done
219 * with clkdev_drop().
221 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
226 cl->dev_id = dev_name(ddata->dev);
235 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
237 const char *optfck_name;
240 if (ddata->nr_clocks < SYSC_OPTFCK0)
241 index = SYSC_OPTFCK0;
243 index = ddata->nr_clocks;
248 optfck_name = clock_names[index];
250 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
254 ddata->clock_roles[index] = optfck_name;
260 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
262 int error, i, index = -ENODEV;
264 if (!strncmp(clock_names[SYSC_FCK], name, 3))
266 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
270 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
271 if (!ddata->clocks[i]) {
279 dev_err(ddata->dev, "clock %s not added\n", name);
283 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
284 if (IS_ERR(ddata->clocks[index])) {
285 dev_err(ddata->dev, "clock get error for %s: %li\n",
286 name, PTR_ERR(ddata->clocks[index]));
288 return PTR_ERR(ddata->clocks[index]);
291 error = clk_prepare(ddata->clocks[index]);
293 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
302 static int sysc_get_clocks(struct sysc *ddata)
304 struct device_node *np = ddata->dev->of_node;
305 struct property *prop;
307 int nr_fck = 0, nr_ick = 0, i, error = 0;
309 ddata->clock_roles = devm_kcalloc(ddata->dev,
311 sizeof(*ddata->clock_roles),
313 if (!ddata->clock_roles)
316 of_property_for_each_string(np, "clock-names", prop, name) {
317 if (!strncmp(clock_names[SYSC_FCK], name, 3))
319 if (!strncmp(clock_names[SYSC_ICK], name, 3))
321 ddata->clock_roles[ddata->nr_clocks] = name;
325 if (ddata->nr_clocks < 1)
328 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
329 error = sysc_init_ext_opt_clock(ddata, NULL);
334 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
335 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
340 if (nr_fck > 1 || nr_ick > 1) {
341 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
346 ddata->clocks = devm_kcalloc(ddata->dev,
347 ddata->nr_clocks, sizeof(*ddata->clocks),
352 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
353 const char *name = ddata->clock_roles[i];
358 error = sysc_get_one_clock(ddata, name);
366 static int sysc_enable_main_clocks(struct sysc *ddata)
374 for (i = 0; i < SYSC_OPTFCK0; i++) {
375 clock = ddata->clocks[i];
377 /* Main clocks may not have ick */
378 if (IS_ERR_OR_NULL(clock))
381 error = clk_enable(clock);
389 for (i--; i >= 0; i--) {
390 clock = ddata->clocks[i];
392 /* Main clocks may not have ick */
393 if (IS_ERR_OR_NULL(clock))
402 static void sysc_disable_main_clocks(struct sysc *ddata)
410 for (i = 0; i < SYSC_OPTFCK0; i++) {
411 clock = ddata->clocks[i];
412 if (IS_ERR_OR_NULL(clock))
419 static int sysc_enable_opt_clocks(struct sysc *ddata)
427 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
428 clock = ddata->clocks[i];
430 /* Assume no holes for opt clocks */
431 if (IS_ERR_OR_NULL(clock))
434 error = clk_enable(clock);
442 for (i--; i >= 0; i--) {
443 clock = ddata->clocks[i];
444 if (IS_ERR_OR_NULL(clock))
453 static void sysc_disable_opt_clocks(struct sysc *ddata)
461 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
462 clock = ddata->clocks[i];
464 /* Assume no holes for opt clocks */
465 if (IS_ERR_OR_NULL(clock))
472 static void sysc_clkdm_deny_idle(struct sysc *ddata)
474 struct ti_sysc_platform_data *pdata;
476 if (ddata->legacy_mode)
479 pdata = dev_get_platdata(ddata->dev);
480 if (pdata && pdata->clkdm_deny_idle)
481 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
484 static void sysc_clkdm_allow_idle(struct sysc *ddata)
486 struct ti_sysc_platform_data *pdata;
488 if (ddata->legacy_mode)
491 pdata = dev_get_platdata(ddata->dev);
492 if (pdata && pdata->clkdm_allow_idle)
493 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
497 * sysc_init_resets - init rstctrl reset line if configured
498 * @ddata: device driver data
500 * See sysc_rstctrl_reset_deassert().
502 static int sysc_init_resets(struct sysc *ddata)
505 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
506 if (IS_ERR(ddata->rsts))
507 return PTR_ERR(ddata->rsts);
513 * sysc_parse_and_check_child_range - parses module IO region from ranges
514 * @ddata: device driver data
516 * In general we only need rev, syss, and sysc registers and not the whole
517 * module range. But we do want the offsets for these registers from the
518 * module base. This allows us to check them against the legacy hwmod
519 * platform data. Let's also check the ranges are configured properly.
521 static int sysc_parse_and_check_child_range(struct sysc *ddata)
523 struct device_node *np = ddata->dev->of_node;
524 const __be32 *ranges;
525 u32 nr_addr, nr_size;
528 ranges = of_get_property(np, "ranges", &len);
530 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
535 len /= sizeof(*ranges);
538 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
543 error = of_property_read_u32(np, "#address-cells", &nr_addr);
547 error = of_property_read_u32(np, "#size-cells", &nr_size);
551 if (nr_addr != 1 || nr_size != 1) {
552 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
558 ddata->module_pa = of_translate_address(np, ranges++);
559 ddata->module_size = be32_to_cpup(ranges);
564 static struct device_node *stdout_path;
566 static void sysc_init_stdout_path(struct sysc *ddata)
568 struct device_node *np = NULL;
571 if (IS_ERR(stdout_path))
577 np = of_find_node_by_path("/chosen");
581 uart = of_get_property(np, "stdout-path", NULL);
585 np = of_find_node_by_path(uart);
594 stdout_path = ERR_PTR(-ENODEV);
597 static void sysc_check_quirk_stdout(struct sysc *ddata,
598 struct device_node *np)
600 sysc_init_stdout_path(ddata);
601 if (np != stdout_path)
604 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
605 SYSC_QUIRK_NO_RESET_ON_INIT;
609 * sysc_check_one_child - check child configuration
610 * @ddata: device driver data
611 * @np: child device node
613 * Let's avoid messy situations where we have new interconnect target
614 * node but children have "ti,hwmods". These belong to the interconnect
615 * target node and are managed by this driver.
617 static void sysc_check_one_child(struct sysc *ddata,
618 struct device_node *np)
622 name = of_get_property(np, "ti,hwmods", NULL);
624 dev_warn(ddata->dev, "really a child ti,hwmods property?");
626 sysc_check_quirk_stdout(ddata, np);
627 sysc_parse_dts_quirks(ddata, np, true);
630 static void sysc_check_children(struct sysc *ddata)
632 struct device_node *child;
634 for_each_child_of_node(ddata->dev->of_node, child)
635 sysc_check_one_child(ddata, child);
639 * So far only I2C uses 16-bit read access with clockactivity with revision
640 * in two registers with stride of 4. We can detect this based on the rev
641 * register size to configure things far enough to be able to properly read
642 * the revision register.
644 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
646 if (resource_size(res) == 8)
647 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
651 * sysc_parse_one - parses the interconnect target module registers
652 * @ddata: device driver data
653 * @reg: register to parse
655 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
657 struct resource *res;
664 name = reg_names[reg];
670 res = platform_get_resource_byname(to_platform_device(ddata->dev),
671 IORESOURCE_MEM, name);
673 ddata->offsets[reg] = -ENODEV;
678 ddata->offsets[reg] = res->start - ddata->module_pa;
679 if (reg == SYSC_REVISION)
680 sysc_check_quirk_16bit(ddata, res);
685 static int sysc_parse_registers(struct sysc *ddata)
689 for (i = 0; i < SYSC_MAX_REGS; i++) {
690 error = sysc_parse_one(ddata, i);
699 * sysc_check_registers - check for misconfigured register overlaps
700 * @ddata: device driver data
702 static int sysc_check_registers(struct sysc *ddata)
704 int i, j, nr_regs = 0, nr_matches = 0;
706 for (i = 0; i < SYSC_MAX_REGS; i++) {
707 if (ddata->offsets[i] < 0)
710 if (ddata->offsets[i] > (ddata->module_size - 4)) {
711 dev_err(ddata->dev, "register outside module range");
716 for (j = 0; j < SYSC_MAX_REGS; j++) {
717 if (ddata->offsets[j] < 0)
720 if (ddata->offsets[i] == ddata->offsets[j])
726 if (nr_matches > nr_regs) {
727 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
728 nr_regs, nr_matches);
737 * syc_ioremap - ioremap register space for the interconnect target module
738 * @ddata: device driver data
740 * Note that the interconnect target module registers can be anywhere
741 * within the interconnect target module range. For example, SGX has
742 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
743 * has them at offset 0x1200 in the CPSW_WR child. Usually the
744 * the interconnect target module registers are at the beginning of
745 * the module range though.
747 static int sysc_ioremap(struct sysc *ddata)
751 if (ddata->offsets[SYSC_REVISION] < 0 &&
752 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
753 ddata->offsets[SYSC_SYSSTATUS] < 0) {
754 size = ddata->module_size;
756 size = max3(ddata->offsets[SYSC_REVISION],
757 ddata->offsets[SYSC_SYSCONFIG],
758 ddata->offsets[SYSC_SYSSTATUS]);
763 if ((size + sizeof(u32)) > ddata->module_size)
764 size = ddata->module_size;
767 ddata->module_va = devm_ioremap(ddata->dev,
770 if (!ddata->module_va)
777 * sysc_map_and_check_registers - ioremap and check device registers
778 * @ddata: device driver data
780 static int sysc_map_and_check_registers(struct sysc *ddata)
784 error = sysc_parse_and_check_child_range(ddata);
788 sysc_check_children(ddata);
790 error = sysc_parse_registers(ddata);
794 error = sysc_ioremap(ddata);
798 error = sysc_check_registers(ddata);
806 * sysc_show_rev - read and show interconnect target module revision
807 * @bufp: buffer to print the information to
808 * @ddata: device driver data
810 static int sysc_show_rev(char *bufp, struct sysc *ddata)
814 if (ddata->offsets[SYSC_REVISION] < 0)
815 return sprintf(bufp, ":NA");
817 len = sprintf(bufp, ":%08x", ddata->revision);
822 static int sysc_show_reg(struct sysc *ddata,
823 char *bufp, enum sysc_registers reg)
825 if (ddata->offsets[reg] < 0)
826 return sprintf(bufp, ":NA");
828 return sprintf(bufp, ":%x", ddata->offsets[reg]);
831 static int sysc_show_name(char *bufp, struct sysc *ddata)
836 return sprintf(bufp, ":%s", ddata->name);
840 * sysc_show_registers - show information about interconnect target module
841 * @ddata: device driver data
843 static void sysc_show_registers(struct sysc *ddata)
849 for (i = 0; i < SYSC_MAX_REGS; i++)
850 bufp += sysc_show_reg(ddata, bufp, i);
852 bufp += sysc_show_rev(bufp, ddata);
853 bufp += sysc_show_name(bufp, ddata);
855 dev_dbg(ddata->dev, "%llx:%x%s\n",
856 ddata->module_pa, ddata->module_size,
860 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
861 #define SYSC_CLOCACT_ICK 2
863 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
864 static int sysc_enable_module(struct device *dev)
867 const struct sysc_regbits *regbits;
868 u32 reg, idlemodes, best_mode;
870 ddata = dev_get_drvdata(dev);
871 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
874 regbits = ddata->cap->regbits;
875 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
877 /* Set CLOCKACTIVITY, we only use it for ick */
878 if (regbits->clkact_shift >= 0 &&
879 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
880 ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
881 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
884 idlemodes = ddata->cfg.sidlemodes;
885 if (!idlemodes || regbits->sidle_shift < 0)
888 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
889 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
890 best_mode = SYSC_IDLE_NO;
892 best_mode = fls(ddata->cfg.sidlemodes) - 1;
893 if (best_mode > SYSC_IDLE_MASK) {
894 dev_err(dev, "%s: invalid sidlemode\n", __func__);
899 if (regbits->enwkup_shift >= 0 &&
900 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
901 reg |= BIT(regbits->enwkup_shift);
904 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
905 reg |= best_mode << regbits->sidle_shift;
906 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
910 idlemodes = ddata->cfg.midlemodes;
911 if (!idlemodes || regbits->midle_shift < 0)
914 best_mode = fls(ddata->cfg.midlemodes) - 1;
915 if (best_mode > SYSC_IDLE_MASK) {
916 dev_err(dev, "%s: invalid midlemode\n", __func__);
920 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
921 best_mode = SYSC_IDLE_NO;
923 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
924 reg |= best_mode << regbits->midle_shift;
925 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
928 /* Autoidle bit must enabled separately if available */
929 if (regbits->autoidle_shift >= 0 &&
930 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
931 reg |= 1 << regbits->autoidle_shift;
932 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
935 if (ddata->module_enable_quirk)
936 ddata->module_enable_quirk(ddata);
941 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
943 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
944 *best_mode = SYSC_IDLE_SMART_WKUP;
945 else if (idlemodes & BIT(SYSC_IDLE_SMART))
946 *best_mode = SYSC_IDLE_SMART;
947 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
948 *best_mode = SYSC_IDLE_FORCE;
955 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
956 static int sysc_disable_module(struct device *dev)
959 const struct sysc_regbits *regbits;
960 u32 reg, idlemodes, best_mode;
963 ddata = dev_get_drvdata(dev);
964 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
967 if (ddata->module_disable_quirk)
968 ddata->module_disable_quirk(ddata);
970 regbits = ddata->cap->regbits;
971 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
974 idlemodes = ddata->cfg.midlemodes;
975 if (!idlemodes || regbits->midle_shift < 0)
978 ret = sysc_best_idle_mode(idlemodes, &best_mode);
980 dev_err(dev, "%s: invalid midlemode\n", __func__);
984 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
985 best_mode = SYSC_IDLE_FORCE;
987 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
988 reg |= best_mode << regbits->midle_shift;
989 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
993 idlemodes = ddata->cfg.sidlemodes;
994 if (!idlemodes || regbits->sidle_shift < 0)
997 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
998 best_mode = SYSC_IDLE_FORCE;
1000 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1002 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1007 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1008 reg |= best_mode << regbits->sidle_shift;
1009 if (regbits->autoidle_shift >= 0 &&
1010 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1011 reg |= 1 << regbits->autoidle_shift;
1012 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1017 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1020 struct ti_sysc_platform_data *pdata;
1023 pdata = dev_get_platdata(ddata->dev);
1027 if (!pdata->idle_module)
1030 error = pdata->idle_module(dev, &ddata->cookie);
1032 dev_err(dev, "%s: could not idle: %i\n",
1035 reset_control_assert(ddata->rsts);
1040 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1043 struct ti_sysc_platform_data *pdata;
1046 pdata = dev_get_platdata(ddata->dev);
1050 if (!pdata->enable_module)
1053 error = pdata->enable_module(dev, &ddata->cookie);
1055 dev_err(dev, "%s: could not enable: %i\n",
1058 reset_control_deassert(ddata->rsts);
1063 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1068 ddata = dev_get_drvdata(dev);
1070 if (!ddata->enabled)
1073 sysc_clkdm_deny_idle(ddata);
1075 if (ddata->legacy_mode) {
1076 error = sysc_runtime_suspend_legacy(dev, ddata);
1078 goto err_allow_idle;
1080 error = sysc_disable_module(dev);
1082 goto err_allow_idle;
1085 sysc_disable_main_clocks(ddata);
1087 if (sysc_opt_clks_needed(ddata))
1088 sysc_disable_opt_clocks(ddata);
1090 ddata->enabled = false;
1093 reset_control_assert(ddata->rsts);
1095 sysc_clkdm_allow_idle(ddata);
1100 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1105 ddata = dev_get_drvdata(dev);
1111 sysc_clkdm_deny_idle(ddata);
1113 if (sysc_opt_clks_needed(ddata)) {
1114 error = sysc_enable_opt_clocks(ddata);
1116 goto err_allow_idle;
1119 error = sysc_enable_main_clocks(ddata);
1121 goto err_opt_clocks;
1123 reset_control_deassert(ddata->rsts);
1125 if (ddata->legacy_mode) {
1126 error = sysc_runtime_resume_legacy(dev, ddata);
1128 goto err_main_clocks;
1130 error = sysc_enable_module(dev);
1132 goto err_main_clocks;
1135 ddata->enabled = true;
1137 sysc_clkdm_allow_idle(ddata);
1142 sysc_disable_main_clocks(ddata);
1144 if (sysc_opt_clks_needed(ddata))
1145 sysc_disable_opt_clocks(ddata);
1147 sysc_clkdm_allow_idle(ddata);
1152 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1156 ddata = dev_get_drvdata(dev);
1158 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1161 return pm_runtime_force_suspend(dev);
1164 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1168 ddata = dev_get_drvdata(dev);
1170 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1173 return pm_runtime_force_resume(dev);
1176 static const struct dev_pm_ops sysc_pm_ops = {
1177 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1178 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1179 sysc_runtime_resume,
1183 /* Module revision register based quirks */
1184 struct sysc_revision_quirk {
1195 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1196 optrev_val, optrevmask, optquirkmask) \
1198 .name = (optname), \
1199 .base = (optbase), \
1200 .rev_offset = (optrev), \
1201 .sysc_offset = (optsysc), \
1202 .syss_offset = (optsyss), \
1203 .revision = (optrev_val), \
1204 .revision_mask = (optrevmask), \
1205 .quirks = (optquirkmask), \
1208 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1209 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1210 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1211 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1212 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1213 SYSC_QUIRK_LEGACY_IDLE),
1214 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1215 SYSC_QUIRK_LEGACY_IDLE),
1216 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1217 SYSC_QUIRK_LEGACY_IDLE),
1218 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1219 SYSC_QUIRK_LEGACY_IDLE),
1220 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1221 SYSC_QUIRK_LEGACY_IDLE),
1222 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1224 /* Some timers on omap4 and later */
1225 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
1227 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
1229 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1230 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1231 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1232 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1233 /* Uarts on omap4 and later */
1234 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1235 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1236 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1237 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1239 /* Quirks that need to be set based on the module address */
1240 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1241 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1242 SYSC_QUIRK_SWSUP_SIDLE),
1244 /* Quirks that need to be set based on detected module */
1245 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff,
1246 SYSC_MODULE_QUIRK_AESS),
1247 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1248 SYSC_MODULE_QUIRK_HDQ1W),
1249 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1250 SYSC_MODULE_QUIRK_HDQ1W),
1251 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1252 SYSC_MODULE_QUIRK_I2C),
1253 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1254 SYSC_MODULE_QUIRK_I2C),
1255 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1256 SYSC_MODULE_QUIRK_I2C),
1257 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1258 SYSC_MODULE_QUIRK_I2C),
1259 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1260 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1261 SYSC_MODULE_QUIRK_SGX),
1262 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1263 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1264 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff,
1265 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1266 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1267 SYSC_MODULE_QUIRK_WDT),
1268 /* Watchdog on am3 and am4 */
1269 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1270 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1273 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
1274 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
1275 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
1276 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1277 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1279 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1280 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
1281 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1282 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1283 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1284 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1285 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
1286 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1287 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
1288 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1289 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
1290 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
1291 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1292 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
1293 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
1294 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1295 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1296 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1297 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
1298 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1299 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
1300 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
1301 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
1302 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
1303 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1304 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
1305 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1306 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1307 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
1308 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
1309 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
1310 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1311 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1312 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1313 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1314 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1315 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1316 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
1317 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1318 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
1319 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1320 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1321 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1322 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1323 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
1328 * Early quirks based on module base and register offsets only that are
1329 * needed before the module revision can be read
1331 static void sysc_init_early_quirks(struct sysc *ddata)
1333 const struct sysc_revision_quirk *q;
1336 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1337 q = &sysc_revision_quirks[i];
1342 if (q->base != ddata->module_pa)
1345 if (q->rev_offset >= 0 &&
1346 q->rev_offset != ddata->offsets[SYSC_REVISION])
1349 if (q->sysc_offset >= 0 &&
1350 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1353 if (q->syss_offset >= 0 &&
1354 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1357 ddata->name = q->name;
1358 ddata->cfg.quirks |= q->quirks;
1362 /* Quirks that also consider the revision register value */
1363 static void sysc_init_revision_quirks(struct sysc *ddata)
1365 const struct sysc_revision_quirk *q;
1368 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1369 q = &sysc_revision_quirks[i];
1371 if (q->base && q->base != ddata->module_pa)
1374 if (q->rev_offset >= 0 &&
1375 q->rev_offset != ddata->offsets[SYSC_REVISION])
1378 if (q->sysc_offset >= 0 &&
1379 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1382 if (q->syss_offset >= 0 &&
1383 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1386 if (q->revision == ddata->revision ||
1387 (q->revision & q->revision_mask) ==
1388 (ddata->revision & q->revision_mask)) {
1389 ddata->name = q->name;
1390 ddata->cfg.quirks |= q->quirks;
1395 /* 1-wire needs module's internal clocks enabled for reset */
1396 static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
1398 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1401 val = sysc_read(ddata, offset);
1403 sysc_write(ddata, offset, val);
1406 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1407 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1409 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1411 sysc_write(ddata, offset, 1);
1414 /* I2C needs extra enable bit toggling for reset */
1415 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1420 /* I2C_CON, omap2/3 is different from omap4 and later */
1421 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1427 val = sysc_read(ddata, offset);
1432 sysc_write(ddata, offset, val);
1435 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1437 sysc_clk_quirk_i2c(ddata, true);
1440 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1442 sysc_clk_quirk_i2c(ddata, false);
1445 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1446 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1448 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1449 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1451 sysc_write(ddata, offset, val);
1454 /* Watchdog timer needs a disable sequence after reset */
1455 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1457 int wps, spr, error;
1463 sysc_write(ddata, spr, 0xaaaa);
1464 error = readl_poll_timeout(ddata->module_va + wps, val,
1466 MAX_MODULE_SOFTRESET_WAIT);
1468 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1470 sysc_write(ddata, spr, 0x5555);
1471 error = readl_poll_timeout(ddata->module_va + wps, val,
1473 MAX_MODULE_SOFTRESET_WAIT);
1475 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1478 static void sysc_init_module_quirks(struct sysc *ddata)
1480 if (ddata->legacy_mode || !ddata->name)
1483 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1484 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
1489 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1490 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1491 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1496 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1497 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1499 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1500 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1502 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1503 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1504 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1508 static int sysc_clockdomain_init(struct sysc *ddata)
1510 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1511 struct clk *fck = NULL, *ick = NULL;
1514 if (!pdata || !pdata->init_clockdomain)
1517 switch (ddata->nr_clocks) {
1519 ick = ddata->clocks[SYSC_ICK];
1522 fck = ddata->clocks[SYSC_FCK];
1528 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1529 if (!error || error == -ENODEV)
1536 * Note that pdata->init_module() typically does a reset first. After
1537 * pdata->init_module() is done, PM runtime can be used for the interconnect
1540 static int sysc_legacy_init(struct sysc *ddata)
1542 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1545 if (!pdata || !pdata->init_module)
1548 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1549 if (error == -EEXIST)
1556 * Note that the caller must ensure the interconnect target module is enabled
1557 * before calling reset. Otherwise reset will not complete.
1559 static int sysc_reset(struct sysc *ddata)
1561 int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
1562 u32 sysc_mask, syss_done;
1564 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1565 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1567 if (ddata->legacy_mode || sysc_offset < 0 ||
1568 ddata->cap->regbits->srst_shift < 0 ||
1569 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1572 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1574 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1577 syss_done = ddata->cfg.syss_mask;
1579 if (ddata->clk_disable_quirk)
1580 ddata->clk_disable_quirk(ddata);
1582 sysc_val = sysc_read_sysconfig(ddata);
1583 sysc_val |= sysc_mask;
1584 sysc_write(ddata, sysc_offset, sysc_val);
1586 if (ddata->clk_enable_quirk)
1587 ddata->clk_enable_quirk(ddata);
1589 /* Poll on reset status */
1590 if (syss_offset >= 0) {
1591 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1592 (rstval & ddata->cfg.syss_mask) ==
1594 100, MAX_MODULE_SOFTRESET_WAIT);
1596 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1597 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1598 !(rstval & sysc_mask),
1599 100, MAX_MODULE_SOFTRESET_WAIT);
1602 if (ddata->reset_done_quirk)
1603 ddata->reset_done_quirk(ddata);
1609 * At this point the module is configured enough to read the revision but
1610 * module may not be completely configured yet to use PM runtime. Enable
1611 * all clocks directly during init to configure the quirks needed for PM
1612 * runtime based on the revision register.
1614 static int sysc_init_module(struct sysc *ddata)
1618 error = sysc_clockdomain_init(ddata);
1622 sysc_clkdm_deny_idle(ddata);
1625 * Always enable clocks. The bootloader may or may not have enabled
1626 * the related clocks.
1628 error = sysc_enable_opt_clocks(ddata);
1632 error = sysc_enable_main_clocks(ddata);
1634 goto err_opt_clocks;
1636 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1637 error = reset_control_deassert(ddata->rsts);
1639 goto err_main_clocks;
1642 ddata->revision = sysc_read_revision(ddata);
1643 sysc_init_revision_quirks(ddata);
1644 sysc_init_module_quirks(ddata);
1646 if (ddata->legacy_mode) {
1647 error = sysc_legacy_init(ddata);
1652 if (!ddata->legacy_mode) {
1653 error = sysc_enable_module(ddata->dev);
1658 error = sysc_reset(ddata);
1660 dev_err(ddata->dev, "Reset failed with %d\n", error);
1662 if (error && !ddata->legacy_mode)
1663 sysc_disable_module(ddata->dev);
1666 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
1667 reset_control_assert(ddata->rsts);
1671 sysc_disable_main_clocks(ddata);
1673 /* No re-enable of clockdomain autoidle to prevent module autoidle */
1675 sysc_disable_opt_clocks(ddata);
1676 sysc_clkdm_allow_idle(ddata);
1682 static int sysc_init_sysc_mask(struct sysc *ddata)
1684 struct device_node *np = ddata->dev->of_node;
1688 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1692 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1697 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1700 struct device_node *np = ddata->dev->of_node;
1701 struct property *prop;
1705 of_property_for_each_u32(np, name, prop, p, val) {
1706 if (val >= SYSC_NR_IDLEMODES) {
1707 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1710 *idlemodes |= (1 << val);
1716 static int sysc_init_idlemodes(struct sysc *ddata)
1720 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1725 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1734 * Only some devices on omap4 and later have SYSCONFIG reset done
1735 * bit. We can detect this if there is no SYSSTATUS at all, or the
1736 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1737 * have multiple bits for the child devices like OHCI and EHCI.
1738 * Depends on SYSC being parsed first.
1740 static int sysc_init_syss_mask(struct sysc *ddata)
1742 struct device_node *np = ddata->dev->of_node;
1746 error = of_property_read_u32(np, "ti,syss-mask", &val);
1748 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1749 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1750 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1751 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1756 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1757 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1759 ddata->cfg.syss_mask = val;
1765 * Many child device drivers need to have fck and opt clocks available
1766 * to get the clock rate for device internal configuration etc.
1768 static int sysc_child_add_named_clock(struct sysc *ddata,
1769 struct device *child,
1773 struct clk_lookup *l;
1779 clk = clk_get(child, name);
1785 clk = clk_get(ddata->dev, name);
1789 l = clkdev_create(clk, name, dev_name(child));
1798 static int sysc_child_add_clocks(struct sysc *ddata,
1799 struct device *child)
1803 for (i = 0; i < ddata->nr_clocks; i++) {
1804 error = sysc_child_add_named_clock(ddata,
1806 ddata->clock_roles[i]);
1807 if (error && error != -EEXIST) {
1808 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1809 ddata->clock_roles[i], error);
1818 static struct device_type sysc_device_type = {
1821 static struct sysc *sysc_child_to_parent(struct device *dev)
1823 struct device *parent = dev->parent;
1825 if (!parent || parent->type != &sysc_device_type)
1828 return dev_get_drvdata(parent);
1831 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1836 ddata = sysc_child_to_parent(dev);
1838 error = pm_generic_runtime_suspend(dev);
1842 if (!ddata->enabled)
1845 return sysc_runtime_suspend(ddata->dev);
1848 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1853 ddata = sysc_child_to_parent(dev);
1855 if (!ddata->enabled) {
1856 error = sysc_runtime_resume(ddata->dev);
1859 "%s error: %i\n", __func__, error);
1862 return pm_generic_runtime_resume(dev);
1865 #ifdef CONFIG_PM_SLEEP
1866 static int sysc_child_suspend_noirq(struct device *dev)
1871 ddata = sysc_child_to_parent(dev);
1873 dev_dbg(ddata->dev, "%s %s\n", __func__,
1874 ddata->name ? ddata->name : "");
1876 error = pm_generic_suspend_noirq(dev);
1878 dev_err(dev, "%s error at %i: %i\n",
1879 __func__, __LINE__, error);
1884 if (!pm_runtime_status_suspended(dev)) {
1885 error = pm_generic_runtime_suspend(dev);
1887 dev_dbg(dev, "%s busy at %i: %i\n",
1888 __func__, __LINE__, error);
1893 error = sysc_runtime_suspend(ddata->dev);
1895 dev_err(dev, "%s error at %i: %i\n",
1896 __func__, __LINE__, error);
1901 ddata->child_needs_resume = true;
1907 static int sysc_child_resume_noirq(struct device *dev)
1912 ddata = sysc_child_to_parent(dev);
1914 dev_dbg(ddata->dev, "%s %s\n", __func__,
1915 ddata->name ? ddata->name : "");
1917 if (ddata->child_needs_resume) {
1918 ddata->child_needs_resume = false;
1920 error = sysc_runtime_resume(ddata->dev);
1923 "%s runtime resume error: %i\n",
1926 error = pm_generic_runtime_resume(dev);
1929 "%s generic runtime resume: %i\n",
1933 return pm_generic_resume_noirq(dev);
1937 static struct dev_pm_domain sysc_child_pm_domain = {
1939 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1940 sysc_child_runtime_resume,
1942 USE_PLATFORM_PM_SLEEP_OPS
1943 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1944 sysc_child_resume_noirq)
1949 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1950 * @ddata: device driver data
1951 * @child: child device driver
1953 * Allow idle for child devices as done with _od_runtime_suspend().
1954 * Otherwise many child devices will not idle because of the permanent
1955 * parent usecount set in pm_runtime_irq_safe().
1957 * Note that the long term solution is to just modify the child device
1958 * drivers to not set pm_runtime_irq_safe() and then this can be just
1961 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1963 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1964 dev_pm_domain_set(child, &sysc_child_pm_domain);
1967 static int sysc_notifier_call(struct notifier_block *nb,
1968 unsigned long event, void *device)
1970 struct device *dev = device;
1974 ddata = sysc_child_to_parent(dev);
1979 case BUS_NOTIFY_ADD_DEVICE:
1980 error = sysc_child_add_clocks(ddata, dev);
1983 sysc_legacy_idle_quirk(ddata, dev);
1992 static struct notifier_block sysc_nb = {
1993 .notifier_call = sysc_notifier_call,
1996 /* Device tree configured quirks */
1997 struct sysc_dts_quirk {
2002 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2003 { .name = "ti,no-idle-on-init",
2004 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2005 { .name = "ti,no-reset-on-init",
2006 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2007 { .name = "ti,no-idle",
2008 .mask = SYSC_QUIRK_NO_IDLE, },
2011 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2014 const struct property *prop;
2017 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2018 const char *name = sysc_dts_quirks[i].name;
2020 prop = of_get_property(np, name, &len);
2024 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2026 dev_warn(ddata->dev,
2027 "dts flag should be at module level for %s\n",
2033 static int sysc_init_dts_quirks(struct sysc *ddata)
2035 struct device_node *np = ddata->dev->of_node;
2039 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2041 sysc_parse_dts_quirks(ddata, np, false);
2042 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2045 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2049 ddata->cfg.srst_udelay = (u8)val;
2055 static void sysc_unprepare(struct sysc *ddata)
2062 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2063 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2064 clk_unprepare(ddata->clocks[i]);
2069 * Common sysc register bits found on omap2, also known as type1
2071 static const struct sysc_regbits sysc_regbits_omap2 = {
2072 .dmadisable_shift = -ENODEV,
2079 .autoidle_shift = 0,
2082 static const struct sysc_capabilities sysc_omap2 = {
2083 .type = TI_SYSC_OMAP2,
2084 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2085 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2086 SYSC_OMAP2_AUTOIDLE,
2087 .regbits = &sysc_regbits_omap2,
2090 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2091 static const struct sysc_capabilities sysc_omap2_timer = {
2092 .type = TI_SYSC_OMAP2_TIMER,
2093 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2094 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2095 SYSC_OMAP2_AUTOIDLE,
2096 .regbits = &sysc_regbits_omap2,
2097 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2101 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2102 * with different sidle position
2104 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2105 .dmadisable_shift = -ENODEV,
2106 .midle_shift = -ENODEV,
2108 .clkact_shift = -ENODEV,
2109 .enwkup_shift = -ENODEV,
2111 .autoidle_shift = 0,
2112 .emufree_shift = -ENODEV,
2115 static const struct sysc_capabilities sysc_omap3_sham = {
2116 .type = TI_SYSC_OMAP3_SHAM,
2117 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2118 .regbits = &sysc_regbits_omap3_sham,
2122 * AES register bits found on omap3 and later, a variant of
2123 * sysc_regbits_omap2 with different sidle position
2125 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2126 .dmadisable_shift = -ENODEV,
2127 .midle_shift = -ENODEV,
2129 .clkact_shift = -ENODEV,
2130 .enwkup_shift = -ENODEV,
2132 .autoidle_shift = 0,
2133 .emufree_shift = -ENODEV,
2136 static const struct sysc_capabilities sysc_omap3_aes = {
2137 .type = TI_SYSC_OMAP3_AES,
2138 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2139 .regbits = &sysc_regbits_omap3_aes,
2143 * Common sysc register bits found on omap4, also known as type2
2145 static const struct sysc_regbits sysc_regbits_omap4 = {
2146 .dmadisable_shift = 16,
2149 .clkact_shift = -ENODEV,
2150 .enwkup_shift = -ENODEV,
2153 .autoidle_shift = -ENODEV,
2156 static const struct sysc_capabilities sysc_omap4 = {
2157 .type = TI_SYSC_OMAP4,
2158 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2159 SYSC_OMAP4_SOFTRESET,
2160 .regbits = &sysc_regbits_omap4,
2163 static const struct sysc_capabilities sysc_omap4_timer = {
2164 .type = TI_SYSC_OMAP4_TIMER,
2165 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2166 SYSC_OMAP4_SOFTRESET,
2167 .regbits = &sysc_regbits_omap4,
2171 * Common sysc register bits found on omap4, also known as type3
2173 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2174 .dmadisable_shift = -ENODEV,
2177 .clkact_shift = -ENODEV,
2178 .enwkup_shift = -ENODEV,
2179 .srst_shift = -ENODEV,
2180 .emufree_shift = -ENODEV,
2181 .autoidle_shift = -ENODEV,
2184 static const struct sysc_capabilities sysc_omap4_simple = {
2185 .type = TI_SYSC_OMAP4_SIMPLE,
2186 .regbits = &sysc_regbits_omap4_simple,
2190 * SmartReflex sysc found on omap34xx
2192 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2193 .dmadisable_shift = -ENODEV,
2194 .midle_shift = -ENODEV,
2195 .sidle_shift = -ENODEV,
2197 .enwkup_shift = -ENODEV,
2198 .srst_shift = -ENODEV,
2199 .emufree_shift = -ENODEV,
2200 .autoidle_shift = -ENODEV,
2203 static const struct sysc_capabilities sysc_34xx_sr = {
2204 .type = TI_SYSC_OMAP34XX_SR,
2205 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2206 .regbits = &sysc_regbits_omap34xx_sr,
2207 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2208 SYSC_QUIRK_LEGACY_IDLE,
2212 * SmartReflex sysc found on omap36xx and later
2214 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2215 .dmadisable_shift = -ENODEV,
2216 .midle_shift = -ENODEV,
2218 .clkact_shift = -ENODEV,
2220 .srst_shift = -ENODEV,
2221 .emufree_shift = -ENODEV,
2222 .autoidle_shift = -ENODEV,
2225 static const struct sysc_capabilities sysc_36xx_sr = {
2226 .type = TI_SYSC_OMAP36XX_SR,
2227 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2228 .regbits = &sysc_regbits_omap36xx_sr,
2229 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2232 static const struct sysc_capabilities sysc_omap4_sr = {
2233 .type = TI_SYSC_OMAP4_SR,
2234 .regbits = &sysc_regbits_omap36xx_sr,
2235 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2239 * McASP register bits found on omap4 and later
2241 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2242 .dmadisable_shift = -ENODEV,
2243 .midle_shift = -ENODEV,
2245 .clkact_shift = -ENODEV,
2246 .enwkup_shift = -ENODEV,
2247 .srst_shift = -ENODEV,
2248 .emufree_shift = -ENODEV,
2249 .autoidle_shift = -ENODEV,
2252 static const struct sysc_capabilities sysc_omap4_mcasp = {
2253 .type = TI_SYSC_OMAP4_MCASP,
2254 .regbits = &sysc_regbits_omap4_mcasp,
2255 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2259 * McASP found on dra7 and later
2261 static const struct sysc_capabilities sysc_dra7_mcasp = {
2262 .type = TI_SYSC_OMAP4_SIMPLE,
2263 .regbits = &sysc_regbits_omap4_simple,
2264 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2268 * FS USB host found on omap4 and later
2270 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2271 .dmadisable_shift = -ENODEV,
2272 .midle_shift = -ENODEV,
2274 .clkact_shift = -ENODEV,
2276 .srst_shift = -ENODEV,
2277 .emufree_shift = -ENODEV,
2278 .autoidle_shift = -ENODEV,
2281 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2282 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2283 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2284 .regbits = &sysc_regbits_omap4_usb_host_fs,
2287 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2288 .dmadisable_shift = -ENODEV,
2289 .midle_shift = -ENODEV,
2290 .sidle_shift = -ENODEV,
2291 .clkact_shift = -ENODEV,
2294 .emufree_shift = -ENODEV,
2295 .autoidle_shift = -ENODEV,
2298 static const struct sysc_capabilities sysc_dra7_mcan = {
2299 .type = TI_SYSC_DRA7_MCAN,
2300 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2301 .regbits = &sysc_regbits_dra7_mcan,
2302 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2305 static int sysc_init_pdata(struct sysc *ddata)
2307 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2308 struct ti_sysc_module_data *mdata;
2313 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2317 if (ddata->legacy_mode) {
2318 mdata->name = ddata->legacy_mode;
2319 mdata->module_pa = ddata->module_pa;
2320 mdata->module_size = ddata->module_size;
2321 mdata->offsets = ddata->offsets;
2322 mdata->nr_offsets = SYSC_MAX_REGS;
2323 mdata->cap = ddata->cap;
2324 mdata->cfg = &ddata->cfg;
2327 ddata->mdata = mdata;
2332 static int sysc_init_match(struct sysc *ddata)
2334 const struct sysc_capabilities *cap;
2336 cap = of_device_get_match_data(ddata->dev);
2342 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2347 static void ti_sysc_idle(struct work_struct *work)
2351 ddata = container_of(work, struct sysc, idle_work.work);
2354 * One time decrement of clock usage counts if left on from init.
2355 * Note that we disable opt clocks unconditionally in this case
2356 * as they are enabled unconditionally during init without
2357 * considering sysc_opt_clks_needed() at that point.
2359 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2360 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2361 sysc_disable_main_clocks(ddata);
2362 sysc_disable_opt_clocks(ddata);
2363 sysc_clkdm_allow_idle(ddata);
2366 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2367 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2371 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2372 * and SYSC_QUIRK_NO_RESET_ON_INIT
2374 if (pm_runtime_active(ddata->dev))
2375 pm_runtime_put_sync(ddata->dev);
2378 static const struct of_device_id sysc_match_table[] = {
2379 { .compatible = "simple-bus", },
2383 static int sysc_probe(struct platform_device *pdev)
2385 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2389 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2393 ddata->dev = &pdev->dev;
2394 platform_set_drvdata(pdev, ddata);
2396 error = sysc_init_match(ddata);
2400 error = sysc_init_dts_quirks(ddata);
2404 error = sysc_map_and_check_registers(ddata);
2408 error = sysc_init_sysc_mask(ddata);
2412 error = sysc_init_idlemodes(ddata);
2416 error = sysc_init_syss_mask(ddata);
2420 error = sysc_init_pdata(ddata);
2424 sysc_init_early_quirks(ddata);
2426 error = sysc_get_clocks(ddata);
2430 error = sysc_init_resets(ddata);
2434 error = sysc_init_module(ddata);
2438 pm_runtime_enable(ddata->dev);
2439 error = pm_runtime_get_sync(ddata->dev);
2441 pm_runtime_put_noidle(ddata->dev);
2442 pm_runtime_disable(ddata->dev);
2446 /* Balance use counts as PM runtime should have enabled these all */
2447 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2448 reset_control_assert(ddata->rsts);
2450 if (!(ddata->cfg.quirks &
2451 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
2452 sysc_disable_main_clocks(ddata);
2453 sysc_disable_opt_clocks(ddata);
2454 sysc_clkdm_allow_idle(ddata);
2457 sysc_show_registers(ddata);
2459 ddata->dev->type = &sysc_device_type;
2460 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2461 pdata ? pdata->auxdata : NULL,
2466 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2468 /* At least earlycon won't survive without deferred idle */
2469 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2470 SYSC_QUIRK_NO_IDLE_ON_INIT |
2471 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2472 schedule_delayed_work(&ddata->idle_work, 3000);
2474 pm_runtime_put(&pdev->dev);
2480 pm_runtime_put_sync(&pdev->dev);
2481 pm_runtime_disable(&pdev->dev);
2483 sysc_unprepare(ddata);
2488 static int sysc_remove(struct platform_device *pdev)
2490 struct sysc *ddata = platform_get_drvdata(pdev);
2493 cancel_delayed_work_sync(&ddata->idle_work);
2495 error = pm_runtime_get_sync(ddata->dev);
2497 pm_runtime_put_noidle(ddata->dev);
2498 pm_runtime_disable(ddata->dev);
2502 of_platform_depopulate(&pdev->dev);
2504 pm_runtime_put_sync(&pdev->dev);
2505 pm_runtime_disable(&pdev->dev);
2506 reset_control_assert(ddata->rsts);
2509 sysc_unprepare(ddata);
2514 static const struct of_device_id sysc_match[] = {
2515 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2516 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2517 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2518 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2519 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2520 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2521 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2522 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2523 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2524 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2525 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2526 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2527 { .compatible = "ti,sysc-usb-host-fs",
2528 .data = &sysc_omap4_usb_host_fs, },
2529 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2532 MODULE_DEVICE_TABLE(of, sysc_match);
2534 static struct platform_driver sysc_driver = {
2535 .probe = sysc_probe,
2536 .remove = sysc_remove,
2539 .of_match_table = sysc_match,
2544 static int __init sysc_init(void)
2546 bus_register_notifier(&platform_bus_type, &sysc_nb);
2548 return platform_driver_register(&sysc_driver);
2550 module_init(sysc_init);
2552 static void __exit sysc_exit(void)
2554 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2555 platform_driver_unregister(&sysc_driver);
2557 module_exit(sysc_exit);
2559 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2560 MODULE_LICENSE("GPL v2");