2 * Cortina Gemini SoC Clock Controller driver
3 * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
6 #define pr_fmt(fmt) "clk-gemini: " fmt
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/err.h>
14 #include <linux/clk-provider.h>
16 #include <linux/of_address.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/regmap.h>
19 #include <linux/spinlock.h>
20 #include <linux/reset-controller.h>
21 #include <dt-bindings/reset/cortina,gemini-reset.h>
22 #include <dt-bindings/clock/cortina,gemini-clock.h>
24 /* Globally visible clocks */
25 static DEFINE_SPINLOCK(gemini_clk_lock);
27 #define GEMINI_GLOBAL_STATUS 0x04
28 #define PLL_OSC_SEL BIT(30)
29 #define AHBSPEED_SHIFT (15)
30 #define AHBSPEED_MASK 0x07
31 #define CPU_AHB_RATIO_SHIFT (18)
32 #define CPU_AHB_RATIO_MASK 0x03
34 #define GEMINI_GLOBAL_PLL_CONTROL 0x08
36 #define GEMINI_GLOBAL_SOFT_RESET 0x0c
38 #define GEMINI_GLOBAL_MISC_CONTROL 0x30
39 #define PCI_CLK_66MHZ BIT(18)
40 #define PCI_CLK_OE BIT(17)
42 #define GEMINI_GLOBAL_CLOCK_CONTROL 0x34
43 #define PCI_CLKRUN_EN BIT(16)
44 #define TVC_HALFDIV_SHIFT (24)
45 #define TVC_HALFDIV_MASK 0x1f
46 #define SECURITY_CLK_SEL BIT(29)
48 #define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44
49 #define PCI_DLL_BYPASS BIT(31)
50 #define PCI_DLL_TAP_SEL_MASK 0x1f
53 * struct gemini_data_data - Gemini gated clocks
54 * @bit_idx: the bit used to gate this clock in the clock register
55 * @name: the clock name
56 * @parent_name: the name of the parent clock
57 * @flags: standard clock framework flags
59 struct gemini_gate_data {
62 const char *parent_name;
67 * struct clk_gemini_pci - Gemini PCI clock
68 * @hw: corresponding clock hardware entry
69 * @map: regmap to access the registers
72 struct clk_gemini_pci {
79 * struct gemini_reset - gemini reset controller
80 * @map: regmap to access the containing system controller
81 * @rcdev: reset controller device
85 struct reset_controller_dev rcdev;
88 /* Keeps track of all clocks */
89 static struct clk_hw_onecell_data *gemini_clk_data;
91 static const struct gemini_gate_data gemini_gates[] = {
92 { 1, "security-gate", "secdiv", 0 },
93 { 2, "gmac0-gate", "ahb", 0 },
94 { 3, "gmac1-gate", "ahb", 0 },
95 { 4, "sata0-gate", "ahb", 0 },
96 { 5, "sata1-gate", "ahb", 0 },
97 { 6, "usb0-gate", "ahb", 0 },
98 { 7, "usb1-gate", "ahb", 0 },
99 { 8, "ide-gate", "ahb", 0 },
100 { 9, "pci-gate", "ahb", 0 },
102 * The DDR controller may never have a driver, but certainly must
105 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
107 * The flash controller must be on to access NOR flash through the
110 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
111 { 12, "tvc-gate", "ahb", 0 },
112 { 13, "boot-gate", "apb", 0 },
115 #define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
117 #define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
119 static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
120 unsigned long parent_rate)
122 struct clk_gemini_pci *pciclk = to_pciclk(hw);
125 regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
126 if (val & PCI_CLK_66MHZ)
131 static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long *prate)
134 /* We support 33 and 66 MHz */
140 static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
141 unsigned long parent_rate)
143 struct clk_gemini_pci *pciclk = to_pciclk(hw);
145 if (rate == 33000000)
146 return regmap_update_bits(pciclk->map,
147 GEMINI_GLOBAL_MISC_CONTROL,
149 if (rate == 66000000)
150 return regmap_update_bits(pciclk->map,
151 GEMINI_GLOBAL_MISC_CONTROL,
156 static int gemini_pci_enable(struct clk_hw *hw)
158 struct clk_gemini_pci *pciclk = to_pciclk(hw);
160 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
162 regmap_update_bits(pciclk->map,
163 GEMINI_GLOBAL_MISC_CONTROL,
168 static void gemini_pci_disable(struct clk_hw *hw)
170 struct clk_gemini_pci *pciclk = to_pciclk(hw);
172 regmap_update_bits(pciclk->map,
173 GEMINI_GLOBAL_MISC_CONTROL,
175 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
179 static int gemini_pci_is_enabled(struct clk_hw *hw)
181 struct clk_gemini_pci *pciclk = to_pciclk(hw);
184 regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
185 return !!(val & PCI_CLKRUN_EN);
188 static const struct clk_ops gemini_pci_clk_ops = {
189 .recalc_rate = gemini_pci_recalc_rate,
190 .round_rate = gemini_pci_round_rate,
191 .set_rate = gemini_pci_set_rate,
192 .enable = gemini_pci_enable,
193 .disable = gemini_pci_disable,
194 .is_enabled = gemini_pci_is_enabled,
197 static struct clk_hw *gemini_pci_clk_setup(const char *name,
198 const char *parent_name,
201 struct clk_gemini_pci *pciclk;
202 struct clk_init_data init;
205 pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
207 return ERR_PTR(-ENOMEM);
210 init.ops = &gemini_pci_clk_ops;
212 init.parent_names = &parent_name;
213 init.num_parents = 1;
215 pciclk->hw.init = &init;
217 ret = clk_hw_register(NULL, &pciclk->hw);
227 * This is a self-deasserting reset controller.
229 static int gemini_reset(struct reset_controller_dev *rcdev,
232 struct gemini_reset *gr = to_gemini_reset(rcdev);
234 /* Manual says to always set BIT 30 (CPU1) to 1 */
235 return regmap_write(gr->map,
236 GEMINI_GLOBAL_SOFT_RESET,
237 BIT(GEMINI_RESET_CPU1) | BIT(id));
240 static int gemini_reset_status(struct reset_controller_dev *rcdev,
243 struct gemini_reset *gr = to_gemini_reset(rcdev);
247 ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
251 return !!(val & BIT(id));
254 static const struct reset_control_ops gemini_reset_ops = {
255 .reset = gemini_reset,
256 .status = gemini_reset_status,
259 static int gemini_clk_probe(struct platform_device *pdev)
261 /* Gives the fracions 1x, 1.5x, 1.85x and 2x */
262 unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
263 unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
265 struct gemini_reset *gr;
268 struct device *dev = &pdev->dev;
269 struct device_node *np = dev->of_node;
270 unsigned int mult, div;
271 struct resource *res;
276 gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
280 /* Remap the system controller for the exclusive register */
281 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
282 base = devm_ioremap_resource(dev, res);
284 return PTR_ERR(base);
286 map = syscon_node_to_regmap(np);
288 dev_err(dev, "no syscon regmap\n");
293 gr->rcdev.owner = THIS_MODULE;
294 gr->rcdev.nr_resets = 32;
295 gr->rcdev.ops = &gemini_reset_ops;
296 gr->rcdev.of_node = np;
298 ret = devm_reset_controller_register(dev, &gr->rcdev);
300 dev_err(dev, "could not register reset controller\n");
304 /* RTC clock 32768 Hz */
305 hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
306 gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
308 /* CPU clock derived as a fixed ratio from the AHB clock */
309 regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
310 val >>= CPU_AHB_RATIO_SHIFT;
311 val &= CPU_AHB_RATIO_MASK;
312 hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
315 gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
317 /* Security clock is 1:1 or 0.75 of APB */
318 regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
319 if (val & SECURITY_CLK_SEL) {
326 hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
329 * These are the leaf gates, at boot no clocks are gated.
331 for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
332 const struct gemini_gate_data *gd;
334 gd = &gemini_gates[i];
335 gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
336 clk_hw_register_gate(NULL, gd->name,
339 base + GEMINI_GLOBAL_CLOCK_CONTROL,
341 CLK_GATE_SET_TO_DISABLE,
346 * The TV Interface Controller has a 5-bit half divider register.
347 * This clock is supposed to be 27MHz as this is an exact multiple
348 * of PAL and NTSC frequencies. The register is undocumented :(
349 * FIXME: figure out the parent and how the divider works.
352 div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
353 dev_dbg(dev, "TVC half divider value = %d\n", div);
355 hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
356 gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
358 /* FIXME: very unclear what the parent is */
359 hw = gemini_pci_clk_setup("PCI", "xtal", map);
360 gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
362 /* FIXME: very unclear what the parent is */
363 hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
364 gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
369 static const struct of_device_id gemini_clk_dt_ids[] = {
370 { .compatible = "cortina,gemini-syscon", },
374 static struct platform_driver gemini_clk_driver = {
375 .probe = gemini_clk_probe,
377 .name = "gemini-clk",
378 .of_match_table = gemini_clk_dt_ids,
379 .suppress_bind_attrs = true,
382 builtin_platform_driver(gemini_clk_driver);
384 static void __init gemini_cc_init(struct device_node *np)
389 unsigned int mult, div;
394 gemini_clk_data = kzalloc(sizeof(*gemini_clk_data) +
395 sizeof(*gemini_clk_data->hws) * GEMINI_NUM_CLKS,
397 if (!gemini_clk_data)
401 * This way all clock fetched before the platform device probes,
402 * except those we assign here for early use, will be deferred.
404 for (i = 0; i < GEMINI_NUM_CLKS; i++)
405 gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
407 map = syscon_node_to_regmap(np);
409 pr_err("no syscon regmap\n");
413 * We check that the regmap works on this very first access,
414 * but as this is an MMIO-backed regmap, subsequent regmap
415 * access is not going to fail and we skip error checks from
418 ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
420 pr_err("failed to read global status register\n");
425 * XTAL is the crystal oscillator, 60 or 30 MHz selected from
428 if (val & PLL_OSC_SEL)
432 hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
433 pr_debug("main crystal @%lu MHz\n", freq / 1000000);
435 /* VCO clock derived from the crystal */
436 mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
438 /* If we run on 30 MHz crystal we have to multiply with two */
439 if (val & PLL_OSC_SEL)
441 hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
443 /* The AHB clock is always 1/3 of the VCO */
444 hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
445 gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
447 /* The APB clock is always 1/6 of the AHB */
448 hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
449 gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
451 /* Register the clocks to be accessed by the device tree */
452 gemini_clk_data->num = GEMINI_NUM_CLKS;
453 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
455 CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);