1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Silicon Labs Si5341/Si5340 Clock generator
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/gcd.h>
12 #include <linux/math64.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <asm/unaligned.h>
19 #define SI5341_MAX_NUM_OUTPUTS 10
20 #define SI5340_MAX_NUM_OUTPUTS 4
22 #define SI5341_NUM_SYNTH 5
23 #define SI5340_NUM_SYNTH 4
25 /* Range of the synthesizer fractional divider */
26 #define SI5341_SYNTH_N_MIN 10
27 #define SI5341_SYNTH_N_MAX 4095
29 /* The chip can get its input clock from 3 input pins or an XTAL */
31 /* There is one PLL running at 13500–14256 MHz */
32 #define SI5341_PLL_VCO_MIN 13500000000ull
33 #define SI5341_PLL_VCO_MAX 14256000000ull
35 /* The 5 frequency synthesizers obtain their input from the PLL */
36 struct clk_si5341_synth {
38 struct clk_si5341 *data;
41 #define to_clk_si5341_synth(_hw) \
42 container_of(_hw, struct clk_si5341_synth, hw)
44 /* The output stages can be connected to any synth (full mux) */
45 struct clk_si5341_output {
47 struct clk_si5341 *data;
50 #define to_clk_si5341_output(_hw) \
51 container_of(_hw, struct clk_si5341_output, hw)
55 struct regmap *regmap;
56 struct i2c_client *i2c_client;
57 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
58 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
60 const char *pxtal_name;
61 const u16 *reg_output_offset;
62 const u16 *reg_rdiv_offset;
63 u64 freq_vco; /* 13500–14256 MHz */
67 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
69 struct clk_si5341_output_config {
70 u8 out_format_drv_bits;
76 #define SI5341_PAGE 0x0001
77 #define SI5341_PN_BASE 0x0002
78 #define SI5341_DEVICE_REV 0x0005
79 #define SI5341_STATUS 0x000C
80 #define SI5341_SOFT_RST 0x001C
82 /* Input dividers (48-bit) */
83 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
84 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
86 /* PLL configuration */
87 #define SI5341_PLL_M_NUM 0x0235
88 #define SI5341_PLL_M_DEN 0x023B
90 /* Output configuration */
91 #define SI5341_OUT_CONFIG(output) \
92 ((output)->data->reg_output_offset[(output)->index])
93 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
94 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
95 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
96 #define SI5341_OUT_R_REG(output) \
97 ((output)->data->reg_rdiv_offset[(output)->index])
99 /* Synthesize N divider */
100 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
101 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
102 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
104 /* Synthesizer output enable, phase bypass, power mode */
105 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
106 #define SI5341_SYNTH_N_PIBYP 0x0A04
107 #define SI5341_SYNTH_N_PDNB 0x0A05
108 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
110 #define SI5341_REGISTER_MAX 0xBFF
112 /* SI5341_OUT_CONFIG bits */
113 #define SI5341_OUT_CFG_PDN BIT(0)
114 #define SI5341_OUT_CFG_OE BIT(1)
115 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
117 /* Static configuration (to be moved to firmware) */
118 struct si5341_reg_default {
123 /* Output configuration registers 0..9 are not quite logically organized */
124 static const u16 si5341_reg_output_offset[] = {
137 static const u16 si5340_reg_output_offset[] = {
144 /* The location of the R divider registers */
145 static const u16 si5341_reg_rdiv_offset[] = {
157 static const u16 si5340_reg_rdiv_offset[] = {
165 * Programming sequence from ClockBuilder, settings to initialize the system
166 * using only the XTAL input, without pre-divider.
167 * This also contains settings that aren't mentioned anywhere in the datasheet.
168 * The "known" settings like synth and output configuration are done later.
170 static const struct si5341_reg_default si5341_reg_defaults[] = {
171 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
172 { 0x0018, 0xFF }, /* INT mask */
173 { 0x0021, 0x0F }, /* Select XTAL as input */
174 { 0x0022, 0x00 }, /* Not in datasheet */
175 { 0x002B, 0x02 }, /* SPI config */
176 { 0x002C, 0x20 }, /* LOS enable for XTAL */
177 { 0x002D, 0x00 }, /* LOS timing */
188 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
193 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
194 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
195 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
196 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
197 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
198 { 0x009E, 0x00 }, /* Not in datasheet */
199 { 0x0102, 0x01 }, /* Enable outputs */
200 { 0x013F, 0x00 }, /* Not in datasheet */
201 { 0x0140, 0x00 }, /* Not in datasheet */
202 { 0x0141, 0x40 }, /* OUT LOS */
203 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
207 { 0x0206, 0x00 }, /* PXAXB (2^x) */
208 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
247 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
248 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
255 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
256 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
257 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
286 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
287 { 0x0359, 0x00 }, /* Nx_DELAY */
296 { 0x0362, 0x00 }, /* Nx_DELAY end */
297 { 0x0802, 0x00 }, /* Not in datasheet */
298 { 0x0803, 0x00 }, /* Not in datasheet */
299 { 0x0804, 0x00 }, /* Not in datasheet */
300 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
301 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
302 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
303 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
304 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
305 { 0x0A02, 0x00 }, /* Not in datasheet */
306 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
309 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
310 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
311 u64 *val1, u32 *val2)
316 err = regmap_bulk_read(regmap, reg, r, 10);
320 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
321 (get_unaligned_le32(r));
322 *val2 = get_unaligned_le32(&r[6]);
327 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
328 u64 n_num, u32 n_den)
332 /* Shift left as far as possible without overflowing */
333 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
338 /* 44 bits (6 bytes) numerator */
339 put_unaligned_le32(n_num, r);
340 r[4] = (n_num >> 32) & 0xff;
341 r[5] = (n_num >> 40) & 0x0f;
342 /* 32 bits denominator */
343 put_unaligned_le32(n_den, &r[6]);
345 /* Program the fraction */
346 return regmap_bulk_write(regmap, reg, r, sizeof(r));
349 /* VCO, we assume it runs at a constant frequency */
350 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
351 unsigned long parent_rate)
353 struct clk_si5341 *data = to_clk_si5341(hw);
360 /* Assume that PDIV is not being used, just read the PLL setting */
361 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
366 if (!m_num || !m_den)
370 * Though m_num is 64-bit, only the upper bits are actually used. While
371 * calculating m_num and m_den, they are shifted as far as possible to
372 * the left. To avoid 96-bit division here, we just shift them back so
373 * we can do with just 64 bits.
377 while (res & 0xffff00000000ULL) {
382 do_div(res, (m_den >> shift));
384 /* We cannot return the actual frequency in 32 bit, store it locally */
385 data->freq_vco = res;
387 /* Report kHz since the value is out of range */
390 return (unsigned long)res;
393 static const struct clk_ops si5341_clk_ops = {
394 .recalc_rate = si5341_clk_recalc_rate,
397 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
399 /* The synthesizer is on if all power and enable bits are set */
400 static int si5341_synth_clk_is_on(struct clk_hw *hw)
402 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
405 u8 index = synth->index;
407 err = regmap_read(synth->data->regmap,
408 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
412 if (!(val & BIT(index)))
415 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
419 if (!(val & BIT(index)))
422 /* This bit must be 0 for the synthesizer to receive clock input */
423 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
427 return !(val & BIT(index));
430 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
432 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
433 u8 index = synth->index; /* In range 0..5 */
434 u8 mask = BIT(index);
437 regmap_update_bits(synth->data->regmap,
438 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
440 regmap_update_bits(synth->data->regmap,
441 SI5341_SYNTH_N_PDNB, mask, 0);
442 /* Disable clock input to synth (set to 1 to disable) */
443 regmap_update_bits(synth->data->regmap,
444 SI5341_SYNTH_N_CLK_DIS, mask, mask);
447 static int si5341_synth_clk_prepare(struct clk_hw *hw)
449 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
451 u8 index = synth->index;
452 u8 mask = BIT(index);
455 err = regmap_update_bits(synth->data->regmap,
456 SI5341_SYNTH_N_PDNB, mask, mask);
460 /* Enable clock input to synth (set bit to 0 to enable) */
461 err = regmap_update_bits(synth->data->regmap,
462 SI5341_SYNTH_N_CLK_DIS, mask, 0);
467 return regmap_update_bits(synth->data->regmap,
468 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
471 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
472 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
473 unsigned long parent_rate)
475 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
481 err = si5341_decode_44_32(synth->data->regmap,
482 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
487 * n_num and n_den are shifted left as much as possible, so to prevent
488 * overflow in 64-bit math, we shift n_den 4 bits to the right
490 f = synth->data->freq_vco;
493 /* Now we need to to 64-bit division: f/n_num */
494 /* And compensate for the 4 bits we dropped */
495 f = div64_u64(f, (n_num >> 4));
500 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
501 unsigned long *parent_rate)
503 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
506 /* The synthesizer accuracy is such that anything in range will work */
507 f = synth->data->freq_vco;
508 do_div(f, SI5341_SYNTH_N_MAX);
512 f = synth->data->freq_vco;
513 do_div(f, SI5341_SYNTH_N_MIN);
520 static int si5341_synth_program(struct clk_si5341_synth *synth,
521 u64 n_num, u32 n_den, bool is_integer)
524 u8 index = synth->index;
526 err = si5341_encode_44_32(synth->data->regmap,
527 SI5341_SYNTH_N_NUM(index), n_num, n_den);
529 err = regmap_update_bits(synth->data->regmap,
530 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
534 return regmap_write(synth->data->regmap,
535 SI5341_SYNTH_N_UPD(index), 0x01);
539 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
540 unsigned long parent_rate)
542 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
549 n_num = synth->data->freq_vco;
552 /* see if there's an integer solution */
553 r = do_div(n_num, rate);
554 is_integer = (r == 0);
556 /* Integer divider equal to n_num */
559 /* Calculate a fractional solution */
566 dev_dbg(&synth->data->i2c_client->dev,
567 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
568 synth->index, n_num, n_den,
569 is_integer ? "int" : "frac");
571 return si5341_synth_program(synth, n_num, n_den, is_integer);
574 static const struct clk_ops si5341_synth_clk_ops = {
575 .is_prepared = si5341_synth_clk_is_on,
576 .prepare = si5341_synth_clk_prepare,
577 .unprepare = si5341_synth_clk_unprepare,
578 .recalc_rate = si5341_synth_clk_recalc_rate,
579 .round_rate = si5341_synth_clk_round_rate,
580 .set_rate = si5341_synth_clk_set_rate,
583 static int si5341_output_clk_is_on(struct clk_hw *hw)
585 struct clk_si5341_output *output = to_clk_si5341_output(hw);
589 err = regmap_read(output->data->regmap,
590 SI5341_OUT_CONFIG(output), &val);
594 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
595 return (val & 0x03) == SI5341_OUT_CFG_OE;
598 /* Disables and then powers down the output */
599 static void si5341_output_clk_unprepare(struct clk_hw *hw)
601 struct clk_si5341_output *output = to_clk_si5341_output(hw);
603 regmap_update_bits(output->data->regmap,
604 SI5341_OUT_CONFIG(output),
605 SI5341_OUT_CFG_OE, 0);
606 regmap_update_bits(output->data->regmap,
607 SI5341_OUT_CONFIG(output),
608 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
611 /* Powers up and then enables the output */
612 static int si5341_output_clk_prepare(struct clk_hw *hw)
614 struct clk_si5341_output *output = to_clk_si5341_output(hw);
617 err = regmap_update_bits(output->data->regmap,
618 SI5341_OUT_CONFIG(output),
619 SI5341_OUT_CFG_PDN, 0);
623 return regmap_update_bits(output->data->regmap,
624 SI5341_OUT_CONFIG(output),
625 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
628 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
629 unsigned long parent_rate)
631 struct clk_si5341_output *output = to_clk_si5341_output(hw);
637 err = regmap_bulk_read(output->data->regmap,
638 SI5341_OUT_R_REG(output), r, 3);
642 /* Calculate value as 24-bit integer*/
643 r_divider = r[2] << 16 | r[1] << 8 | r[0];
645 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
649 /* Divider is 2*(Rx_REG+1) */
653 err = regmap_read(output->data->regmap,
654 SI5341_OUT_CONFIG(output), &val);
658 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
661 return parent_rate / r_divider;
664 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
665 unsigned long *parent_rate)
669 r = *parent_rate >> 1;
671 /* If rate is an even divisor, no changes to parent required */
672 if (r && !(r % rate))
675 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
676 if (rate > 200000000) {
677 /* minimum r-divider is 2 */
680 /* Take a parent frequency near 400 MHz */
681 r = (400000000u / rate) & ~1;
683 *parent_rate = r * rate;
685 /* We cannot change our parent's rate, report what we can do */
687 rate = *parent_rate / (r << 1);
693 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
694 unsigned long parent_rate)
696 struct clk_si5341_output *output = to_clk_si5341_output(hw);
697 /* Frequency divider is (r_div + 1) * 2 */
698 u32 r_div = (parent_rate / rate) >> 1;
704 else if (r_div >= BIT(24))
709 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
710 err = regmap_update_bits(output->data->regmap,
711 SI5341_OUT_CONFIG(output),
712 SI5341_OUT_CFG_RDIV_FORCE2,
713 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
717 /* Always write Rx_REG, because a zero value disables the divider */
718 r[0] = r_div ? (r_div & 0xff) : 1;
719 r[1] = (r_div >> 8) & 0xff;
720 r[2] = (r_div >> 16) & 0xff;
721 err = regmap_bulk_write(output->data->regmap,
722 SI5341_OUT_R_REG(output), r, 3);
727 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
729 return regmap_update_bits(output->data->regmap,
730 SI5341_OUT_MUX_SEL(output), 0x07, index);
733 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
735 struct clk_si5341_output *output = to_clk_si5341_output(hw);
737 if (index >= output->data->num_synth)
740 return si5341_output_reparent(output, index);
743 static u8 si5341_output_get_parent(struct clk_hw *hw)
745 struct clk_si5341_output *output = to_clk_si5341_output(hw);
749 err = regmap_read(output->data->regmap,
750 SI5341_OUT_MUX_SEL(output), &val);
755 static const struct clk_ops si5341_output_clk_ops = {
756 .is_prepared = si5341_output_clk_is_on,
757 .prepare = si5341_output_clk_prepare,
758 .unprepare = si5341_output_clk_unprepare,
759 .recalc_rate = si5341_output_clk_recalc_rate,
760 .round_rate = si5341_output_clk_round_rate,
761 .set_rate = si5341_output_clk_set_rate,
762 .set_parent = si5341_output_set_parent,
763 .get_parent = si5341_output_get_parent,
767 * The chip can be bought in a pre-programmed version, or one can program the
768 * NVM in the chip to boot up in a preset mode. This routine tries to determine
769 * if that's the case, or if we need to reset and program everything from
770 * scratch. Returns negative error, or true/false.
772 static int si5341_is_programmed_already(struct clk_si5341 *data)
777 /* Read the PLL divider value, it must have a non-zero value */
778 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
783 return !!get_unaligned_le32(r);
786 static struct clk_hw *
787 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
789 struct clk_si5341 *data = _data;
790 unsigned int idx = clkspec->args[1];
791 unsigned int group = clkspec->args[0];
795 if (idx >= data->num_outputs) {
796 dev_err(&data->i2c_client->dev,
797 "invalid output index %u\n", idx);
798 return ERR_PTR(-EINVAL);
800 return &data->clk[idx].hw;
802 if (idx >= data->num_synth) {
803 dev_err(&data->i2c_client->dev,
804 "invalid synthesizer index %u\n", idx);
805 return ERR_PTR(-EINVAL);
807 return &data->synth[idx].hw;
810 dev_err(&data->i2c_client->dev,
811 "invalid PLL index %u\n", idx);
812 return ERR_PTR(-EINVAL);
816 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
817 return ERR_PTR(-EINVAL);
821 static int si5341_probe_chip_id(struct clk_si5341 *data)
827 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
830 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
834 model = get_unaligned_le16(reg);
836 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
837 model, reg[2], reg[3]);
841 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
842 data->num_synth = SI5340_NUM_SYNTH;
843 data->reg_output_offset = si5340_reg_output_offset;
844 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
847 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
848 data->num_synth = SI5341_NUM_SYNTH;
849 data->reg_output_offset = si5341_reg_output_offset;
850 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
853 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
861 /* Read active settings into the regmap cache for later reference */
862 static int si5341_read_settings(struct clk_si5341 *data)
868 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
872 err = regmap_bulk_read(data->regmap,
873 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
877 err = regmap_bulk_read(data->regmap,
878 SI5341_SYNTH_N_CLK_DIS, r, 1);
882 for (i = 0; i < data->num_synth; ++i) {
883 err = regmap_bulk_read(data->regmap,
884 SI5341_SYNTH_N_NUM(i), r, 10);
889 for (i = 0; i < data->num_outputs; ++i) {
890 err = regmap_bulk_read(data->regmap,
891 data->reg_output_offset[i], r, 4);
895 err = regmap_bulk_read(data->regmap,
896 data->reg_rdiv_offset[i], r, 3);
904 static int si5341_write_multiple(struct clk_si5341 *data,
905 const struct si5341_reg_default *values, unsigned int num_values)
910 for (i = 0; i < num_values; ++i) {
911 res = regmap_write(data->regmap,
912 values[i].address, values[i].value);
914 dev_err(&data->i2c_client->dev,
915 "Failed to write %#x:%#x\n",
916 values[i].address, values[i].value);
924 static const struct si5341_reg_default si5341_preamble[] = {
932 static int si5341_send_preamble(struct clk_si5341 *data)
937 /* For revision 2 and up, the values are slightly different */
938 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
942 /* Write "preamble" as specified by datasheet */
943 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
946 res = si5341_write_multiple(data,
947 si5341_preamble, ARRAY_SIZE(si5341_preamble));
951 /* Datasheet specifies a 300ms wait after sending the preamble */
957 /* Perform a soft reset and write post-amble */
958 static int si5341_finalize_defaults(struct clk_si5341 *data)
963 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
967 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
969 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
973 /* Datasheet does not explain these nameless registers */
974 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
977 res = regmap_write(data->regmap, 0x0B25, 0x02);
985 static const struct regmap_range si5341_regmap_volatile_range[] = {
986 regmap_reg_range(0x000C, 0x0012), /* Status */
987 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
988 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
989 /* Update bits for synth config */
990 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
991 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
992 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
993 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
994 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
997 static const struct regmap_access_table si5341_regmap_volatile = {
998 .yes_ranges = si5341_regmap_volatile_range,
999 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1002 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1003 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1006 .range_max = SI5341_REGISTER_MAX,
1007 .selector_reg = SI5341_PAGE,
1008 .selector_mask = 0xff,
1009 .selector_shift = 0,
1015 static const struct regmap_config si5341_regmap_config = {
1018 .cache_type = REGCACHE_RBTREE,
1019 .ranges = si5341_regmap_ranges,
1020 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1021 .max_register = SI5341_REGISTER_MAX,
1022 .volatile_table = &si5341_regmap_volatile,
1025 static int si5341_dt_parse_dt(struct i2c_client *client,
1026 struct clk_si5341_output_config *config)
1028 struct device_node *child;
1029 struct device_node *np = client->dev.of_node;
1033 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1034 SI5341_MAX_NUM_OUTPUTS);
1036 for_each_child_of_node(np, child) {
1037 if (of_property_read_u32(child, "reg", &num)) {
1038 dev_err(&client->dev, "missing reg property of %s\n",
1043 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1044 dev_err(&client->dev, "invalid clkout %d\n", num);
1048 if (!of_property_read_u32(child, "silabs,format", &val)) {
1049 /* Set cm and ampl conservatively to 3v3 settings */
1051 case 1: /* normal differential */
1052 config[num].out_cm_ampl_bits = 0x33;
1054 case 2: /* low-power differential */
1055 config[num].out_cm_ampl_bits = 0x13;
1057 case 4: /* LVCMOS */
1058 config[num].out_cm_ampl_bits = 0x33;
1059 /* Set SI recommended impedance for LVCMOS */
1060 config[num].out_format_drv_bits |= 0xc0;
1063 dev_err(&client->dev,
1064 "invalid silabs,format %u for %u\n",
1068 config[num].out_format_drv_bits &= ~0x07;
1069 config[num].out_format_drv_bits |= val & 0x07;
1070 /* Always enable the SYNC feature */
1071 config[num].out_format_drv_bits |= 0x08;
1074 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1076 dev_err(&client->dev,
1077 "invalid silabs,common-mode %u\n",
1081 config[num].out_cm_ampl_bits &= 0xf0;
1082 config[num].out_cm_ampl_bits |= val & 0x0f;
1085 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1087 dev_err(&client->dev,
1088 "invalid silabs,amplitude %u\n",
1092 config[num].out_cm_ampl_bits &= 0x0f;
1093 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1096 if (of_property_read_bool(child, "silabs,disable-high"))
1097 config[num].out_format_drv_bits |= 0x10;
1099 config[num].synth_master =
1100 of_property_read_bool(child, "silabs,synth-master");
1102 config[num].always_on =
1103 of_property_read_bool(child, "always-on");
1114 * If not pre-configured, calculate and set the PLL configuration manually.
1115 * For low-jitter performance, the PLL should be set such that the synthesizers
1116 * only need integer division.
1117 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1118 * the chip to generate any frequency on its outputs, but jitter performance
1119 * may be sub-optimal.
1121 static int si5341_initialize_pll(struct clk_si5341 *data)
1123 struct device_node *np = data->i2c_client->dev.of_node;
1127 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1128 dev_err(&data->i2c_client->dev,
1129 "PLL configuration requires silabs,pll-m-num\n");
1131 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1132 dev_err(&data->i2c_client->dev,
1133 "PLL configuration requires silabs,pll-m-den\n");
1136 if (!m_num || !m_den) {
1137 dev_err(&data->i2c_client->dev,
1138 "PLL configuration invalid, assume 14GHz\n");
1139 m_den = clk_get_rate(data->pxtal) / 10;
1143 return si5341_encode_44_32(data->regmap,
1144 SI5341_PLL_M_NUM, m_num, m_den);
1147 static int si5341_probe(struct i2c_client *client,
1148 const struct i2c_device_id *id)
1150 struct clk_si5341 *data;
1151 struct clk_init_data init;
1152 const char *root_clock_name;
1153 const char *synth_clock_names[SI5341_NUM_SYNTH];
1156 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1157 bool initialization_required;
1159 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1163 data->i2c_client = client;
1165 data->pxtal = devm_clk_get(&client->dev, "xtal");
1166 if (IS_ERR(data->pxtal)) {
1167 if (PTR_ERR(data->pxtal) == -EPROBE_DEFER)
1168 return -EPROBE_DEFER;
1170 dev_err(&client->dev, "Missing xtal clock input\n");
1173 err = si5341_dt_parse_dt(client, config);
1177 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1179 init.name = client->dev.of_node->name;
1180 root_clock_name = init.name;
1182 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1183 if (IS_ERR(data->regmap))
1184 return PTR_ERR(data->regmap);
1186 i2c_set_clientdata(client, data);
1188 err = si5341_probe_chip_id(data);
1192 /* "Activate" the xtal (usually a fixed clock) */
1193 clk_prepare_enable(data->pxtal);
1195 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1196 initialization_required = true;
1198 err = si5341_is_programmed_already(data);
1202 initialization_required = !err;
1205 if (initialization_required) {
1206 /* Populate the regmap cache in preparation for "cache only" */
1207 err = si5341_read_settings(data);
1211 err = si5341_send_preamble(data);
1216 * We intend to send all 'final' register values in a single
1217 * transaction. So cache all register writes until we're done
1220 regcache_cache_only(data->regmap, true);
1222 /* Write the configuration pairs from the firmware blob */
1223 err = si5341_write_multiple(data, si5341_reg_defaults,
1224 ARRAY_SIZE(si5341_reg_defaults));
1228 /* PLL configuration is required */
1229 err = si5341_initialize_pll(data);
1234 /* Register the PLL */
1235 data->pxtal_name = __clk_get_name(data->pxtal);
1236 init.parent_names = &data->pxtal_name;
1237 init.num_parents = 1; /* For now, only XTAL input supported */
1238 init.ops = &si5341_clk_ops;
1240 data->hw.init = &init;
1242 err = devm_clk_hw_register(&client->dev, &data->hw);
1244 dev_err(&client->dev, "clock registration failed\n");
1248 init.num_parents = 1;
1249 init.parent_names = &root_clock_name;
1250 init.ops = &si5341_synth_clk_ops;
1251 for (i = 0; i < data->num_synth; ++i) {
1252 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1253 "%s.N%u", client->dev.of_node->name, i);
1254 init.name = synth_clock_names[i];
1255 data->synth[i].index = i;
1256 data->synth[i].data = data;
1257 data->synth[i].hw.init = &init;
1258 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1260 dev_err(&client->dev,
1261 "synth N%u registration failed\n", i);
1265 init.num_parents = data->num_synth;
1266 init.parent_names = synth_clock_names;
1267 init.ops = &si5341_output_clk_ops;
1268 for (i = 0; i < data->num_outputs; ++i) {
1269 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1270 client->dev.of_node->name, i);
1271 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1272 data->clk[i].index = i;
1273 data->clk[i].data = data;
1274 data->clk[i].hw.init = &init;
1275 if (config[i].out_format_drv_bits & 0x07) {
1276 regmap_write(data->regmap,
1277 SI5341_OUT_FORMAT(&data->clk[i]),
1278 config[i].out_format_drv_bits);
1279 regmap_write(data->regmap,
1280 SI5341_OUT_CM(&data->clk[i]),
1281 config[i].out_cm_ampl_bits);
1283 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1284 kfree(init.name); /* clock framework made a copy of the name */
1286 dev_err(&client->dev,
1287 "output %u registration failed\n", i);
1290 if (config[i].always_on)
1291 clk_prepare(data->clk[i].hw.clk);
1294 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get,
1297 dev_err(&client->dev, "unable to add clk provider\n");
1301 if (initialization_required) {
1303 regcache_cache_only(data->regmap, false);
1304 err = regcache_sync(data->regmap);
1308 err = si5341_finalize_defaults(data);
1313 /* Free the names, clk framework makes copies */
1314 for (i = 0; i < data->num_synth; ++i)
1315 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1320 static const struct i2c_device_id si5341_id[] = {
1325 MODULE_DEVICE_TABLE(i2c, si5341_id);
1327 static const struct of_device_id clk_si5341_of_match[] = {
1328 { .compatible = "silabs,si5340" },
1329 { .compatible = "silabs,si5341" },
1332 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1334 static struct i2c_driver si5341_driver = {
1337 .of_match_table = clk_si5341_of_match,
1339 .probe = si5341_probe,
1340 .id_table = si5341_id,
1342 module_i2c_driver(si5341_driver);
1344 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1345 MODULE_DESCRIPTION("Si5341 driver");
1346 MODULE_LICENSE("GPL");