1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
7 #include <linux/errno.h>
9 #include <linux/slab.h>
13 #define PCG_PREDIV_SHIFT 16
14 #define PCG_PREDIV_WIDTH 3
15 #define PCG_PREDIV_MAX 8
17 #define PCG_DIV_SHIFT 0
18 #define PCG_DIV_WIDTH 6
19 #define PCG_DIV_MAX 64
21 #define PCG_PCS_SHIFT 24
22 #define PCG_PCS_MASK 0x7
24 #define PCG_CGC_SHIFT 28
26 static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
27 unsigned long parent_rate)
29 struct clk_divider *divider = to_clk_divider(hw);
30 unsigned long prediv_rate;
31 unsigned int prediv_value;
32 unsigned int div_value;
34 prediv_value = readl(divider->reg) >> divider->shift;
35 prediv_value &= clk_div_mask(divider->width);
37 prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
41 div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
42 div_value &= clk_div_mask(PCG_DIV_WIDTH);
44 return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
45 divider->flags, PCG_DIV_WIDTH);
48 static int imx8m_clk_composite_compute_dividers(unsigned long rate,
49 unsigned long parent_rate,
50 int *prediv, int *postdiv)
59 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
60 for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
61 int new_error = ((parent_rate / div1) / div2) - rate;
63 if (abs(new_error) < abs(error)) {
74 static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw,
81 imx8m_clk_composite_compute_dividers(rate, *prate,
82 &prediv_value, &div_value);
83 rate = DIV_ROUND_UP(*prate, prediv_value);
85 return DIV_ROUND_UP(rate, div_value);
89 static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
91 unsigned long parent_rate)
93 struct clk_divider *divider = to_clk_divider(hw);
94 unsigned long flags = 0;
100 ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
101 &prediv_value, &div_value);
105 spin_lock_irqsave(divider->lock, flags);
107 val = readl(divider->reg);
108 val &= ~((clk_div_mask(divider->width) << divider->shift) |
109 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
111 val |= (u32)(prediv_value - 1) << divider->shift;
112 val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
113 writel(val, divider->reg);
115 spin_unlock_irqrestore(divider->lock, flags);
120 static const struct clk_ops imx8m_clk_composite_divider_ops = {
121 .recalc_rate = imx8m_clk_composite_divider_recalc_rate,
122 .round_rate = imx8m_clk_composite_divider_round_rate,
123 .set_rate = imx8m_clk_composite_divider_set_rate,
126 struct clk *imx8m_clk_composite_flags(const char *name,
127 const char * const *parent_names,
128 int num_parents, void __iomem *reg,
131 struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
132 struct clk_hw *div_hw, *gate_hw;
133 struct clk_divider *div = NULL;
134 struct clk_gate *gate = NULL;
135 struct clk_mux *mux = NULL;
137 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
143 mux->shift = PCG_PCS_SHIFT;
144 mux->mask = PCG_PCS_MASK;
146 div = kzalloc(sizeof(*div), GFP_KERNEL);
152 div->shift = PCG_PREDIV_SHIFT;
153 div->width = PCG_PREDIV_WIDTH;
154 div->lock = &imx_ccm_lock;
155 div->flags = CLK_DIVIDER_ROUND_CLOSEST;
157 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
163 gate->bit_idx = PCG_CGC_SHIFT;
165 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
166 mux_hw, &clk_mux_ops, div_hw,
167 &imx8m_clk_composite_divider_ops,
168 gate_hw, &clk_gate_ops, flags);