1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the fractional plls found in the imx8m SOCs
7 * Documentation for this fractional pll can be found at:
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
12 #include <linux/err.h>
14 #include <linux/iopoll.h>
15 #include <linux/slab.h>
16 #include <linux/bitfield.h>
23 #define PLL_LOCK_STATUS BIT(31)
24 #define PLL_PD_MASK BIT(19)
25 #define PLL_BYPASS_MASK BIT(14)
26 #define PLL_NEWDIV_VAL BIT(12)
27 #define PLL_NEWDIV_ACK BIT(11)
28 #define PLL_FRAC_DIV_MASK GENMASK(30, 7)
29 #define PLL_INT_DIV_MASK GENMASK(6, 0)
30 #define PLL_OUTPUT_DIV_MASK GENMASK(4, 0)
31 #define PLL_FRAC_DENOM 0x1000000
33 #define PLL_FRAC_LOCK_TIMEOUT 10000
34 #define PLL_FRAC_ACK_TIMEOUT 500000
41 #define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw)
43 static int clk_wait_lock(struct clk_frac_pll *pll)
47 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
48 PLL_FRAC_LOCK_TIMEOUT);
51 static int clk_wait_ack(struct clk_frac_pll *pll)
55 /* return directly if the pll is in powerdown or in bypass */
56 if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
59 /* Wait for the pll's divfi and divff to be reloaded */
60 return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
61 PLL_FRAC_ACK_TIMEOUT);
64 static int clk_pll_prepare(struct clk_hw *hw)
66 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
69 val = readl_relaxed(pll->base + PLL_CFG0);
71 writel_relaxed(val, pll->base + PLL_CFG0);
73 return clk_wait_lock(pll);
76 static void clk_pll_unprepare(struct clk_hw *hw)
78 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
81 val = readl_relaxed(pll->base + PLL_CFG0);
83 writel_relaxed(val, pll->base + PLL_CFG0);
86 static int clk_pll_is_prepared(struct clk_hw *hw)
88 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
91 val = readl_relaxed(pll->base + PLL_CFG0);
92 return (val & PLL_PD_MASK) ? 0 : 1;
95 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
96 unsigned long parent_rate)
98 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
99 u32 val, divff, divfi, divq;
100 u64 temp64 = parent_rate;
103 val = readl_relaxed(pll->base + PLL_CFG0);
104 divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2;
105 val = readl_relaxed(pll->base + PLL_CFG1);
106 divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
107 divfi = FIELD_GET(PLL_INT_DIV_MASK, val);
111 do_div(temp64, PLL_FRAC_DENOM);
112 do_div(temp64, divq);
114 rate = parent_rate * 8 * (divfi + 1);
121 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
122 unsigned long *prate)
124 u64 parent_rate = *prate;
131 do_div(temp64, parent_rate);
133 temp64 = rate - divfi * parent_rate;
134 temp64 *= PLL_FRAC_DENOM;
135 do_div(temp64, parent_rate);
138 temp64 = parent_rate;
140 do_div(temp64, PLL_FRAC_DENOM);
142 rate = parent_rate * divfi + temp64;
148 * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
149 * (means the PLL output will be divided by 2). So the PLL output can use
151 * pllout = parent_rate * 8 / 2 * DIVF_VAL;
152 * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
154 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
155 unsigned long parent_rate)
157 struct clk_frac_pll *pll = to_clk_frac_pll(hw);
158 u32 val, divfi, divff;
164 divfi = rate / parent_rate;
165 temp64 = parent_rate * divfi;
166 temp64 = rate - temp64;
167 temp64 *= PLL_FRAC_DENOM;
168 do_div(temp64, parent_rate);
171 val = readl_relaxed(pll->base + PLL_CFG1);
172 val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
173 val |= (divff << 7) | (divfi - 1);
174 writel_relaxed(val, pll->base + PLL_CFG1);
176 val = readl_relaxed(pll->base + PLL_CFG0);
178 writel_relaxed(val, pll->base + PLL_CFG0);
180 /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
181 val = readl_relaxed(pll->base + PLL_CFG0);
182 val |= PLL_NEWDIV_VAL;
183 writel_relaxed(val, pll->base + PLL_CFG0);
185 ret = clk_wait_ack(pll);
187 /* clear the NEV_DIV_VAL */
188 val = readl_relaxed(pll->base + PLL_CFG0);
189 val &= ~PLL_NEWDIV_VAL;
190 writel_relaxed(val, pll->base + PLL_CFG0);
195 static const struct clk_ops clk_frac_pll_ops = {
196 .prepare = clk_pll_prepare,
197 .unprepare = clk_pll_unprepare,
198 .is_prepared = clk_pll_is_prepared,
199 .recalc_rate = clk_pll_recalc_rate,
200 .round_rate = clk_pll_round_rate,
201 .set_rate = clk_pll_set_rate,
204 struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
207 struct clk_init_data init;
208 struct clk_frac_pll *pll;
212 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
214 return ERR_PTR(-ENOMEM);
217 init.ops = &clk_frac_pll_ops;
219 init.parent_names = &parent_name;
220 init.num_parents = 1;
223 pll->hw.init = &init;
227 ret = clk_hw_register(NULL, hw);