2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
23 #define PLL_IMX7_NUM_OFFSET 0x20
24 #define PLL_IMX7_DENOM_OFFSET 0x30
26 #define PLL_VF610_NUM_OFFSET 0x20
27 #define PLL_VF610_DENOM_OFFSET 0x30
29 #define BM_PLL_POWER (0x1 << 12)
30 #define BM_PLL_LOCK (0x1 << 31)
31 #define IMX7_ENET_PLL_POWER (0x1 << 5)
32 #define IMX7_DDR_PLL_POWER (0x1 << 20)
35 * struct clk_pllv3 - IMX PLL clock version 3
36 * @clk_hw: clock source
37 * @base: base address of PLL registers
38 * @power_bit: pll power bit mask
39 * @powerup_set: set power_bit to power up the PLL
40 * @div_mask: mask of divider bits
41 * @div_shift: shift of divider bits
43 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
44 * is actually a multiplier, and always sits at bit 0.
53 unsigned long ref_clock;
58 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
62 unsigned long timeout = jiffies + msecs_to_jiffies(10);
63 u32 val = readl_relaxed(pll->base) & pll->power_bit;
65 /* No need to wait for lock when pll is not powered up */
66 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
69 /* Wait for PLL to lock */
71 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
73 if (time_after(jiffies, timeout))
75 usleep_range(50, 500);
78 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
81 static int clk_pllv3_prepare(struct clk_hw *hw)
83 struct clk_pllv3 *pll = to_clk_pllv3(hw);
86 val = readl_relaxed(pll->base);
88 val |= pll->power_bit;
90 val &= ~pll->power_bit;
91 writel_relaxed(val, pll->base);
93 return clk_pllv3_wait_lock(pll);
96 static void clk_pllv3_unprepare(struct clk_hw *hw)
98 struct clk_pllv3 *pll = to_clk_pllv3(hw);
101 val = readl_relaxed(pll->base);
102 if (pll->powerup_set)
103 val &= ~pll->power_bit;
105 val |= pll->power_bit;
106 writel_relaxed(val, pll->base);
109 static int clk_pllv3_is_prepared(struct clk_hw *hw)
111 struct clk_pllv3 *pll = to_clk_pllv3(hw);
113 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
119 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
120 unsigned long parent_rate)
122 struct clk_pllv3 *pll = to_clk_pllv3(hw);
123 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
125 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
128 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
129 unsigned long *prate)
131 unsigned long parent_rate = *prate;
133 return (rate >= parent_rate * 22) ? parent_rate * 22 :
137 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
138 unsigned long parent_rate)
140 struct clk_pllv3 *pll = to_clk_pllv3(hw);
143 if (rate == parent_rate * 22)
145 else if (rate == parent_rate * 20)
150 val = readl_relaxed(pll->base);
151 val &= ~(pll->div_mask << pll->div_shift);
152 val |= (div << pll->div_shift);
153 writel_relaxed(val, pll->base);
155 return clk_pllv3_wait_lock(pll);
158 static const struct clk_ops clk_pllv3_ops = {
159 .prepare = clk_pllv3_prepare,
160 .unprepare = clk_pllv3_unprepare,
161 .is_prepared = clk_pllv3_is_prepared,
162 .recalc_rate = clk_pllv3_recalc_rate,
163 .round_rate = clk_pllv3_round_rate,
164 .set_rate = clk_pllv3_set_rate,
167 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
168 unsigned long parent_rate)
170 struct clk_pllv3 *pll = to_clk_pllv3(hw);
171 u32 div = readl_relaxed(pll->base) & pll->div_mask;
173 return parent_rate * div / 2;
176 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
177 unsigned long *prate)
179 unsigned long parent_rate = *prate;
180 unsigned long min_rate = parent_rate * 54 / 2;
181 unsigned long max_rate = parent_rate * 108 / 2;
186 else if (rate < min_rate)
188 div = rate * 2 / parent_rate;
190 return parent_rate * div / 2;
193 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
194 unsigned long parent_rate)
196 struct clk_pllv3 *pll = to_clk_pllv3(hw);
197 unsigned long min_rate = parent_rate * 54 / 2;
198 unsigned long max_rate = parent_rate * 108 / 2;
201 if (rate < min_rate || rate > max_rate)
204 div = rate * 2 / parent_rate;
205 val = readl_relaxed(pll->base);
206 val &= ~pll->div_mask;
208 writel_relaxed(val, pll->base);
210 return clk_pllv3_wait_lock(pll);
213 static const struct clk_ops clk_pllv3_sys_ops = {
214 .prepare = clk_pllv3_prepare,
215 .unprepare = clk_pllv3_unprepare,
216 .is_prepared = clk_pllv3_is_prepared,
217 .recalc_rate = clk_pllv3_sys_recalc_rate,
218 .round_rate = clk_pllv3_sys_round_rate,
219 .set_rate = clk_pllv3_sys_set_rate,
222 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
223 unsigned long parent_rate)
225 struct clk_pllv3 *pll = to_clk_pllv3(hw);
226 u32 mfn = readl_relaxed(pll->base + pll->num_offset);
227 u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
228 u32 div = readl_relaxed(pll->base) & pll->div_mask;
229 u64 temp64 = (u64)parent_rate;
234 return parent_rate * div + (unsigned long)temp64;
237 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
238 unsigned long *prate)
240 unsigned long parent_rate = *prate;
241 unsigned long min_rate = parent_rate * 27;
242 unsigned long max_rate = parent_rate * 54;
244 u32 mfn, mfd = 1000000;
245 u32 max_mfd = 0x3FFFFFFF;
250 else if (rate < min_rate)
253 if (parent_rate <= max_mfd)
256 div = rate / parent_rate;
257 temp64 = (u64) (rate - div * parent_rate);
259 do_div(temp64, parent_rate);
262 temp64 = (u64)parent_rate;
266 return parent_rate * div + (unsigned long)temp64;
269 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
270 unsigned long parent_rate)
272 struct clk_pllv3 *pll = to_clk_pllv3(hw);
273 unsigned long min_rate = parent_rate * 27;
274 unsigned long max_rate = parent_rate * 54;
276 u32 mfn, mfd = 1000000;
277 u32 max_mfd = 0x3FFFFFFF;
280 if (rate < min_rate || rate > max_rate)
283 if (parent_rate <= max_mfd)
286 div = rate / parent_rate;
287 temp64 = (u64) (rate - div * parent_rate);
289 do_div(temp64, parent_rate);
292 val = readl_relaxed(pll->base);
293 val &= ~pll->div_mask;
295 writel_relaxed(val, pll->base);
296 writel_relaxed(mfn, pll->base + pll->num_offset);
297 writel_relaxed(mfd, pll->base + pll->denom_offset);
299 return clk_pllv3_wait_lock(pll);
302 static const struct clk_ops clk_pllv3_av_ops = {
303 .prepare = clk_pllv3_prepare,
304 .unprepare = clk_pllv3_unprepare,
305 .is_prepared = clk_pllv3_is_prepared,
306 .recalc_rate = clk_pllv3_av_recalc_rate,
307 .round_rate = clk_pllv3_av_round_rate,
308 .set_rate = clk_pllv3_av_set_rate,
311 struct clk_pllv3_vf610_mf {
312 u32 mfi; /* integer part, can be 20 or 22 */
313 u32 mfn; /* numerator, 30-bit value */
314 u32 mfd; /* denominator, 30-bit value, must be less than mfn */
317 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
318 struct clk_pllv3_vf610_mf mf)
322 temp64 = parent_rate;
324 do_div(temp64, mf.mfd);
326 return (parent_rate * mf.mfi) + temp64;
329 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
330 unsigned long parent_rate, unsigned long rate)
332 struct clk_pllv3_vf610_mf mf;
335 mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
336 mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */
338 if (rate <= parent_rate * mf.mfi)
340 else if (rate >= parent_rate * (mf.mfi + 1))
343 /* rate = parent_rate * (mfi + mfn/mfd) */
344 temp64 = rate - parent_rate * mf.mfi;
346 do_div(temp64, parent_rate);
353 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
354 unsigned long parent_rate)
356 struct clk_pllv3 *pll = to_clk_pllv3(hw);
357 struct clk_pllv3_vf610_mf mf;
359 mf.mfn = readl_relaxed(pll->base + pll->num_offset);
360 mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
361 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
363 return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
366 static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
367 unsigned long *prate)
369 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
371 return clk_pllv3_vf610_mf_to_rate(*prate, mf);
374 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
375 unsigned long parent_rate)
377 struct clk_pllv3 *pll = to_clk_pllv3(hw);
378 struct clk_pllv3_vf610_mf mf =
379 clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
382 val = readl_relaxed(pll->base);
384 val &= ~pll->div_mask; /* clear bit for mfi=20 */
386 val |= pll->div_mask; /* set bit for mfi=22 */
387 writel_relaxed(val, pll->base);
389 writel_relaxed(mf.mfn, pll->base + pll->num_offset);
390 writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
392 return clk_pllv3_wait_lock(pll);
395 static const struct clk_ops clk_pllv3_vf610_ops = {
396 .prepare = clk_pllv3_prepare,
397 .unprepare = clk_pllv3_unprepare,
398 .is_prepared = clk_pllv3_is_prepared,
399 .recalc_rate = clk_pllv3_vf610_recalc_rate,
400 .round_rate = clk_pllv3_vf610_round_rate,
401 .set_rate = clk_pllv3_vf610_set_rate,
404 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
405 unsigned long parent_rate)
407 struct clk_pllv3 *pll = to_clk_pllv3(hw);
409 return pll->ref_clock;
412 static const struct clk_ops clk_pllv3_enet_ops = {
413 .prepare = clk_pllv3_prepare,
414 .unprepare = clk_pllv3_unprepare,
415 .is_prepared = clk_pllv3_is_prepared,
416 .recalc_rate = clk_pllv3_enet_recalc_rate,
419 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
420 const char *parent_name, void __iomem *base,
423 struct clk_pllv3 *pll;
424 const struct clk_ops *ops;
426 struct clk_init_data init;
428 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
430 return ERR_PTR(-ENOMEM);
432 pll->power_bit = BM_PLL_POWER;
433 pll->num_offset = PLL_NUM_OFFSET;
434 pll->denom_offset = PLL_DENOM_OFFSET;
438 ops = &clk_pllv3_sys_ops;
440 case IMX_PLLV3_SYS_VF610:
441 ops = &clk_pllv3_vf610_ops;
442 pll->num_offset = PLL_VF610_NUM_OFFSET;
443 pll->denom_offset = PLL_VF610_DENOM_OFFSET;
445 case IMX_PLLV3_USB_VF610:
449 ops = &clk_pllv3_ops;
450 pll->powerup_set = true;
452 case IMX_PLLV3_AV_IMX7:
453 pll->num_offset = PLL_IMX7_NUM_OFFSET;
454 pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
457 ops = &clk_pllv3_av_ops;
459 case IMX_PLLV3_ENET_IMX7:
460 pll->power_bit = IMX7_ENET_PLL_POWER;
461 pll->ref_clock = 1000000000;
462 ops = &clk_pllv3_enet_ops;
465 pll->ref_clock = 500000000;
466 ops = &clk_pllv3_enet_ops;
468 case IMX_PLLV3_DDR_IMX7:
469 pll->power_bit = IMX7_DDR_PLL_POWER;
470 pll->num_offset = PLL_IMX7_NUM_OFFSET;
471 pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
472 ops = &clk_pllv3_av_ops;
475 ops = &clk_pllv3_ops;
478 pll->div_mask = div_mask;
483 init.parent_names = &parent_name;
484 init.num_parents = 1;
486 pll->hw.init = &init;
488 clk = clk_register(NULL, &pll->hw);