2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/of_address.h>
18 #include <linux/slab.h>
19 #include <linux/clkdev.h>
20 #include <linux/delay.h>
27 #define CON0_BASE_EN BIT(0)
28 #define CON0_PWR_ON BIT(0)
29 #define CON0_ISO_EN BIT(1)
30 #define CON0_PCW_CHG BIT(31)
32 #define AUDPLL_TUNER_EN BIT(31)
34 #define POSTDIV_MASK 0x7
35 #define INTEGER_BITS 7
38 * MediaTek PLLs are configured through their pcw value. The pcw value describes
39 * a divider in the PLL feedback loop which consists of 7 bits for the integer
40 * part and the remaining bits (if present) for the fractional part. Also they
41 * have a 3 bit power-of-two post divider.
46 void __iomem *base_addr;
47 void __iomem *pd_addr;
48 void __iomem *pwr_addr;
49 void __iomem *tuner_addr;
50 void __iomem *tuner_en_addr;
51 void __iomem *pcw_addr;
52 const struct mtk_pll_data *data;
55 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
57 return container_of(hw, struct mtk_clk_pll, hw);
60 static int mtk_pll_is_prepared(struct clk_hw *hw)
62 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
64 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
67 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
70 int pcwbits = pll->data->pcwbits;
75 /* The fractional part of the PLL divider. */
76 pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
80 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
88 return ((unsigned long)vco + postdiv - 1) / postdiv;
91 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
97 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
100 val = readl(pll->pd_addr);
101 val &= ~(POSTDIV_MASK << pll->data->pd_shift);
102 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
104 /* postdiv and pcw need to set at the same time if on same register */
105 if (pll->pd_addr != pll->pcw_addr) {
106 writel(val, pll->pd_addr);
107 val = readl(pll->pcw_addr);
111 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
112 pll->data->pcw_shift);
113 val |= pcw << pll->data->pcw_shift;
114 writel(val, pll->pcw_addr);
116 con1 = readl(pll->base_addr + REG_CON1);
119 con1 |= CON0_PCW_CHG;
121 writel(con1, pll->base_addr + REG_CON1);
123 writel(con1 + 1, pll->tuner_addr);
130 * mtk_pll_calc_values - calculate good values for a given input frequency.
132 * @pcw: The pcw value (output)
133 * @postdiv: The post divider (output)
134 * @freq: The desired target frequency
135 * @fin: The input frequency
138 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
141 unsigned long fmin = 1000 * MHZ;
142 const struct mtk_pll_div_table *div_table = pll->data->div_table;
146 if (freq > pll->data->fmax)
147 freq = pll->data->fmax;
150 if (freq > div_table[0].freq)
151 freq = div_table[0].freq;
153 for (val = 0; div_table[val + 1].freq != 0; val++) {
154 if (freq > div_table[val + 1].freq)
159 for (val = 0; val < 5; val++) {
161 if ((u64)freq * *postdiv >= fmin)
166 /* _pcw = freq * postdiv / fin * 2^pcwfbits */
167 _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
173 static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
174 unsigned long parent_rate)
176 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
180 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
181 mtk_pll_set_rate_regs(pll, pcw, postdiv);
186 static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
187 unsigned long parent_rate)
189 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
193 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
194 postdiv = 1 << postdiv;
196 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
197 pcw &= GENMASK(pll->data->pcwbits - 1, 0);
199 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
202 static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
203 unsigned long *prate)
205 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
209 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
211 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
214 static int mtk_pll_prepare(struct clk_hw *hw)
216 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
219 r = readl(pll->pwr_addr) | CON0_PWR_ON;
220 writel(r, pll->pwr_addr);
223 r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
224 writel(r, pll->pwr_addr);
227 r = readl(pll->base_addr + REG_CON0);
228 r |= pll->data->en_mask;
229 writel(r, pll->base_addr + REG_CON0);
231 if (pll->tuner_en_addr) {
232 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
233 writel(r, pll->tuner_en_addr);
234 } else if (pll->tuner_addr) {
235 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
236 writel(r, pll->tuner_addr);
241 if (pll->data->flags & HAVE_RST_BAR) {
242 r = readl(pll->base_addr + REG_CON0);
243 r |= pll->data->rst_bar_mask;
244 writel(r, pll->base_addr + REG_CON0);
250 static void mtk_pll_unprepare(struct clk_hw *hw)
252 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
255 if (pll->data->flags & HAVE_RST_BAR) {
256 r = readl(pll->base_addr + REG_CON0);
257 r &= ~pll->data->rst_bar_mask;
258 writel(r, pll->base_addr + REG_CON0);
261 if (pll->tuner_en_addr) {
262 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
263 writel(r, pll->tuner_en_addr);
264 } else if (pll->tuner_addr) {
265 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
266 writel(r, pll->tuner_addr);
269 r = readl(pll->base_addr + REG_CON0);
271 writel(r, pll->base_addr + REG_CON0);
273 r = readl(pll->pwr_addr) | CON0_ISO_EN;
274 writel(r, pll->pwr_addr);
276 r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
277 writel(r, pll->pwr_addr);
280 static const struct clk_ops mtk_pll_ops = {
281 .is_prepared = mtk_pll_is_prepared,
282 .prepare = mtk_pll_prepare,
283 .unprepare = mtk_pll_unprepare,
284 .recalc_rate = mtk_pll_recalc_rate,
285 .round_rate = mtk_pll_round_rate,
286 .set_rate = mtk_pll_set_rate,
289 static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
292 struct mtk_clk_pll *pll;
293 struct clk_init_data init = {};
295 const char *parent_name = "clk26m";
297 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
299 return ERR_PTR(-ENOMEM);
301 pll->base_addr = base + data->reg;
302 pll->pwr_addr = base + data->pwr_reg;
303 pll->pd_addr = base + data->pd_reg;
304 pll->pcw_addr = base + data->pcw_reg;
306 pll->tuner_addr = base + data->tuner_reg;
307 if (data->tuner_en_reg)
308 pll->tuner_en_addr = base + data->tuner_en_reg;
309 pll->hw.init = &init;
312 init.name = data->name;
313 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
314 init.ops = &mtk_pll_ops;
315 if (data->parent_name)
316 init.parent_names = &data->parent_name;
318 init.parent_names = &parent_name;
319 init.num_parents = 1;
321 clk = clk_register(NULL, &pll->hw);
329 void mtk_clk_register_plls(struct device_node *node,
330 const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
336 base = of_iomap(node, 0);
338 pr_err("%s(): ioremap failed\n", __func__);
342 for (i = 0; i < num_plls; i++) {
343 const struct mtk_pll_data *pll = &plls[i];
345 clk = mtk_clk_register_pll(pll, base);
348 pr_err("Failed to register clk %s: %ld\n",
349 pll->name, PTR_ERR(clk));
353 clk_data->clks[pll->id] = clk;