drivers/clk/microchip/clk-core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Purna Chandra Mandal,<purna.mandal@microchip.com>
   4  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
   5  */
   6 #include <linux/clk-provider.h>
   7 #include <linux/delay.h>
   8 #include <linux/device.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <asm/mach-pic32/pic32.h>
  13 #include <asm/traps.h>
  14
  15 #include "clk-core.h"
  16
  17 /* OSCCON Reg fields */
  18 #define OSC_CUR_MASK            0x07
  19 #define OSC_CUR_SHIFT           12
  20 #define OSC_NEW_MASK            0x07
  21 #define OSC_NEW_SHIFT           8
  22 #define OSC_SWEN                BIT(0)
  23
  24 /* SPLLCON Reg fields */
  25 #define PLL_RANGE_MASK          0x07
  26 #define PLL_RANGE_SHIFT         0
  27 #define PLL_ICLK_MASK           0x01
  28 #define PLL_ICLK_SHIFT          7
  29 #define PLL_IDIV_MASK           0x07
  30 #define PLL_IDIV_SHIFT          8
  31 #define PLL_ODIV_MASK           0x07
  32 #define PLL_ODIV_SHIFT          24
  33 #define PLL_MULT_MASK           0x7F
  34 #define PLL_MULT_SHIFT          16
  35 #define PLL_MULT_MAX            128
  36 #define PLL_ODIV_MIN            1
  37 #define PLL_ODIV_MAX            5
  38
  39 /* Peripheral Bus Clock Reg Fields */
  40 #define PB_DIV_MASK             0x7f
  41 #define PB_DIV_SHIFT            0
  42 #define PB_DIV_READY            BIT(11)
  43 #define PB_DIV_ENABLE           BIT(15)
  44 #define PB_DIV_MAX              128
  45 #define PB_DIV_MIN              0
  46
  47 /* Reference Oscillator Control Reg fields */
  48 #define REFO_SEL_MASK           0x0f
  49 #define REFO_SEL_SHIFT          0
  50 #define REFO_ACTIVE             BIT(8)
  51 #define REFO_DIVSW_EN           BIT(9)
  52 #define REFO_OE                 BIT(12)
  53 #define REFO_ON                 BIT(15)
  54 #define REFO_DIV_SHIFT          16
  55 #define REFO_DIV_MASK           0x7fff
  56
  57 /* Reference Oscillator Trim Register Fields */
  58 #define REFO_TRIM_REG           0x10
  59 #define REFO_TRIM_MASK          0x1ff
  60 #define REFO_TRIM_SHIFT         23
  61 #define REFO_TRIM_MAX           511
  62
  63 /* Mux Slew Control Register fields */
  64 #define SLEW_BUSY               BIT(0)
  65 #define SLEW_DOWNEN             BIT(1)
  66 #define SLEW_UPEN               BIT(2)
  67 #define SLEW_DIV                0x07
  68 #define SLEW_DIV_SHIFT          8
  69 #define SLEW_SYSDIV             0x0f
  70 #define SLEW_SYSDIV_SHIFT       20
  71
  72 /* Clock Poll Timeout */
  73 #define LOCK_TIMEOUT_US         USEC_PER_MSEC
  74
  75 /* SoC specific clock needed during SPLL clock rate switch */
  76 static struct clk_hw *pic32_sclk_hw;
  77
  78 /* add instruction pipeline delay while CPU clock is in-transition. */
  79 #define cpu_nop5()                      \
  80 do {                                    \
  81         __asm__ __volatile__("nop");    \
  82         __asm__ __volatile__("nop");    \
  83         __asm__ __volatile__("nop");    \
  84         __asm__ __volatile__("nop");    \
  85         __asm__ __volatile__("nop");    \
  86 } while (0)
  87
  88 /* Perpheral bus clocks */
  89 struct pic32_periph_clk {
  90         struct clk_hw hw;
  91         void __iomem *ctrl_reg;
  92         struct pic32_clk_common *core;
  93 };
  94
  95 #define clkhw_to_pbclk(_hw)     container_of(_hw, struct pic32_periph_clk, hw)
  96
  97 static int pbclk_is_enabled(struct clk_hw *hw)
  98 {
  99         struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
 100
 101         return readl(pb->ctrl_reg) & PB_DIV_ENABLE;
 102 }
 103
 104 static int pbclk_enable(struct clk_hw *hw)
 105 {
 106         struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
 107
 108         writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));
 109         return 0;
 110 }
 111
 112 static void pbclk_disable(struct clk_hw *hw)
 113 {
 114         struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
 115
 116         writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg));
 117 }
 118
 119 static unsigned long calc_best_divided_rate(unsigned long rate,
 120                                             unsigned long parent_rate,
 121                                             u32 divider_max,
 122                                             u32 divider_min)
 123 {
 124         unsigned long divided_rate, divided_rate_down, best_rate;
 125         unsigned long div, div_up;
 126
 127         /* eq. clk_rate = parent_rate / divider.
 128          *
 129          * Find best divider to produce closest of target divided rate.
 130          */
 131         div = parent_rate / rate;
 132         div = clamp_val(div, divider_min, divider_max);
 133         div_up = clamp_val(div + 1, divider_min, divider_max);
 134
 135         divided_rate = parent_rate / div;
 136         divided_rate_down = parent_rate / div_up;
 137         if (abs(rate - divided_rate_down) < abs(rate - divided_rate))
 138                 best_rate = divided_rate_down;
 139         else
 140                 best_rate = divided_rate;
 141
 142         return best_rate;
 143 }
 144
 145 static inline u32 pbclk_read_pbdiv(struct pic32_periph_clk *pb)
 146 {
 147         return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1;
 148 }
 149
 150 static unsigned long pbclk_recalc_rate(struct clk_hw *hw,
 151                                        unsigned long parent_rate)
 152 {
 153         struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
 154
 155         return parent_rate / pbclk_read_pbdiv(pb);
 156 }
 157
 158 static long pbclk_round_rate(struct clk_hw *hw, unsigned long rate,
 159                              unsigned long *parent_rate)
 160 {
 161         return calc_best_divided_rate(rate, *parent_rate,
 162                                       PB_DIV_MAX, PB_DIV_MIN);
 163 }
 164
 165 static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate,
 166                           unsigned long parent_rate)
 167 {
 168         struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
 169         unsigned long flags;
 170         u32 v, div;
 171         int err;
 172
 173         /* check & wait for DIV_READY */
 174         err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
 175                                  1, LOCK_TIMEOUT_US);
 176         if (err)
 177                 return err;
 178
 179         /* calculate clkdiv and best rate */
 180         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 181
 182         spin_lock_irqsave(&pb->core->reg_lock, flags);
 183
 184         /* apply new div */
 185         v = readl(pb->ctrl_reg);
 186         v &= ~PB_DIV_MASK;
 187         v |= (div - 1);
 188
 189         pic32_syskey_unlock();
 190
 191         writel(v, pb->ctrl_reg);
 192
 193         spin_unlock_irqrestore(&pb->core->reg_lock, flags);
 194
 195         /* wait again for DIV_READY */
 196         err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
 197                                  1, LOCK_TIMEOUT_US);
 198         if (err)
 199                 return err;
 200
 201         /* confirm that new div is applied correctly */
 202         return (pbclk_read_pbdiv(pb) == div) ? 0 : -EBUSY;
 203 }
 204
 205 const struct clk_ops pic32_pbclk_ops = {
 206         .enable         = pbclk_enable,
 207         .disable        = pbclk_disable,
 208         .is_enabled     = pbclk_is_enabled,
 209         .recalc_rate    = pbclk_recalc_rate,
 210         .round_rate     = pbclk_round_rate,
 211         .set_rate       = pbclk_set_rate,
 212 };
 213
 214 struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *desc,
 215                                       struct pic32_clk_common *core)
 216 {
 217         struct pic32_periph_clk *pbclk;
 218         struct clk *clk;
 219
 220         pbclk = devm_kzalloc(core->dev, sizeof(*pbclk), GFP_KERNEL);
 221         if (!pbclk)
 222                 return ERR_PTR(-ENOMEM);
 223
 224         pbclk->hw.init = &desc->init_data;
 225         pbclk->core = core;
 226         pbclk->ctrl_reg = desc->ctrl_reg + core->iobase;
 227
 228         clk = devm_clk_register(core->dev, &pbclk->hw);
 229         if (IS_ERR(clk)) {
 230                 dev_err(core->dev, "%s: clk_register() failed\n", __func__);
 231                 devm_kfree(core->dev, pbclk);
 232         }
 233
 234         return clk;
 235 }
 236
 237 /* Reference oscillator operations */
 238 struct pic32_ref_osc {
 239         struct clk_hw hw;
 240         void __iomem *ctrl_reg;
 241         const u32 *parent_map;
 242         struct pic32_clk_common *core;
 243 };
 244
 245 #define clkhw_to_refosc(_hw)    container_of(_hw, struct pic32_ref_osc, hw)
 246
 247 static int roclk_is_enabled(struct clk_hw *hw)
 248 {
 249         struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
 250
 251         return readl(refo->ctrl_reg) & REFO_ON;
 252 }
 253
 254 static int roclk_enable(struct clk_hw *hw)
 255 {
 256         struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
 257
 258         writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg));
 259         return 0;
 260 }
 261
 262 static void roclk_disable(struct clk_hw *hw)
 263 {
 264         struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
 265
 266         writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg));
 267 }
 268
 269 static void roclk_init(struct clk_hw *hw)
 270 {
 271         /* initialize clock in disabled state */
 272         roclk_disable(hw);
 273 }
 274
 275 static u8 roclk_get_parent(struct clk_hw *hw)
 276 {
 277         struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
 278         u32 v, i;
 279
 280         v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
 281
 282         if (!refo->parent_map)
 283                 return v;
 284
 285         for (i = 0; i < clk_hw_get_num_parents(hw); i++)
 286                 if (refo->parent_map[i] == v)
 287                         return i;
 288
 289         return -EINVAL;
 290 }
 291
 292 static unsigned long roclk_calc_rate(unsigned long parent_rate,
 293                                      u32 rodiv, u32 rotrim)
 294 {
 295         u64 rate64;
 296
 297         /* fout = fin / [2 * {div + (trim / 512)}]
 298          *      = fin * 512 / [1024 * div + 2 * trim]
 299          *      = fin * 256 / (512 * div + trim)
 300          *      = (fin << 8) / ((div << 9) + trim)
 301          */
 302         if (rotrim) {
 303                 rodiv = (rodiv << 9) + rotrim;
 304                 rate64 = parent_rate;
 305                 rate64 <<= 8;
 306                 do_div(rate64, rodiv);
 307         } else if (rodiv) {
 308                 rate64 = parent_rate / (rodiv << 1);
 309         } else {
 310                 rate64 = parent_rate;
 311         }
 312         return rate64;
 313 }
 314
 315 static void roclk_calc_div_trim(unsigned long rate,
 316                                 unsigned long parent_rate,
 317                                 u32 *rodiv_p, u32 *rotrim_p)
 318 {
 319         u32 div, rotrim, rodiv;
 320         u64 frac;
 321
 322         /* Find integer approximation of floating-point arithmetic.
 323          *      fout = fin / [2 * {rodiv + (rotrim / 512)}] ... (1)
 324          * i.e. fout = fin / 2 * DIV
 325          *      whereas DIV = rodiv + (rotrim / 512)
 326          *
 327          * Since kernel does not perform floating-point arithmatic so
 328          * (rotrim/512) will be zero. And DIV & rodiv will result same.
 329          *
 330          * ie. fout = (fin * 256) / [(512 * rodiv) + rotrim]  ... from (1)
 331          * ie. rotrim = ((fin * 256) / fout) - (512 * DIV)
 332          */
 333         if (parent_rate <= rate) {
 334                 div = 0;
 335                 frac = 0;
 336                 rodiv = 0;
 337                 rotrim = 0;
 338         } else {
 339                 div = parent_rate / (rate << 1);
 340                 frac = parent_rate;
 341                 frac <<= 8;
 342                 do_div(frac, rate);
 343                 frac -= (u64)(div << 9);
 344
 345                 rodiv = (div > REFO_DIV_MASK) ? REFO_DIV_MASK : div;
 346                 rotrim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : frac;
 347         }
 348
 349         if (rodiv_p)
 350                 *rodiv_p = rodiv;
 351
 352         if (rotrim_p)
 353                 *rotrim_p = rotrim;
 354 }
 355
 356 static unsigned long roclk_recalc_rate(struct clk_hw *hw,
 357                                        unsigned long parent_rate)
 358 {
 359         struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
 360         u32 v, rodiv, rotrim;
 361
 362         /* get rodiv */
 363         v = readl(refo->ctrl_reg);
 364         rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK;
 365
 366         /* get trim */
 367         v = readl(refo->ctrl_reg + REFO_TRIM_REG);
 368         rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK;
 369
 370         return roclk_calc_rate(parent_rate, rodiv, rotrim);
 371 }
 372
 373 static long roclk_round_rate(struct clk_hw *hw, unsigned long rate,
 374                              unsigned long *parent_rate)
 375 {
 376         u32 rotrim, rodiv;
 377
 378         /* calculate dividers for new rate */
 379         roclk_calc_div_trim(rate, *parent_rate, &rodiv, &rotrim);
 380
 381         /* caclulate new rate (rounding) based on new rodiv & rotrim */
 382         return roclk_calc_rate(*parent_rate, rodiv, rotrim);
 383 }
 384
 385 static int roclk_determine_rate(struct clk_hw *hw,
 386                                 struct clk_rate_request *req)
 387 {
 388         struct clk_hw *parent_clk, *best_parent_clk = NULL;
 389         unsigned int i, delta, best_delta = -1;
 390         unsigned long parent_rate, best_parent_rate = 0;
 391         unsigned long best = 0, nearest_rate;
 392
 393         /* find a parent which can generate nearest clkrate >= rate */
 394         for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
 395                 /* get parent */
 396                 parent_clk = clk_hw_get_parent_by_index(hw, i);
 397                 if (!parent_clk)
 398                         continue;
 399
 400                 /* skip if parent runs slower than target rate */
 401                 parent_rate = clk_hw_get_rate(parent_clk);
 402                 if (req->rate > parent_rate)
 403                         continue;
 404
 405                 nearest_rate = roclk_round_rate(hw, req->rate, &parent_rate);
 406                 delta = abs(nearest_rate - req->rate);
 407                 if ((nearest_rate >= req->rate) && (delta < best_delta)) {
 408                         best_parent_clk = parent_clk;
 409                         best_parent_rate = parent_rate;
 410                         best = nearest_rate;
 411                         best_delta = delta;
 412
 413                         if (delta == 0)
 414                                 break;
 415                 }
 416         }
 417
 418         /* if no match found, retain old rate */
 419         if (!best_parent_clk) {
 420                 pr_err("%s:%s, no parent found for rate %lu.\n",
 421                        __func__, clk_hw_get_name(hw), req->rate);
 422                 return clk_hw_get_rate(hw);
 423         }
 424
 425         pr_debug("%s,rate %lu, best_parent(%s, %lu), best %lu, delta %d\n",
 426                  clk_hw_get_name(hw), req->rate,
 427                  clk_hw_get_name(best_parent_clk), best_parent_rate,
 428                  best, best_delta);
 429
 430         if (req->best_parent_rate)
 431                 req->best_parent_rate = best_parent_rate;
 432
 433         if (req->best_parent_hw)
 434                 req->best_parent_hw = best_parent_clk;
 435
 436         return best;
 437 }
 438
 439 static int roclk_set_parent(struct clk_hw *hw, u8 index)
 440 {
 441         struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
 442         unsigned long flags;
 443         u32 v;
 444         int err;
 445
 446         if (refo->parent_map)
 447                 index = refo->parent_map[index];
 448
 449         /* wait until ACTIVE bit is zero or timeout */
 450         err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE),
 451                                  1, LOCK_TIMEOUT_US);
 452         if (err) {
 453                 pr_err("%s: poll failed, clk active\n", clk_hw_get_name(hw));
 454                 return err;
 455         }
 456
 457         spin_lock_irqsave(&refo->core->reg_lock, flags);
 458
 459         pic32_syskey_unlock();
 460
 461         /* calculate & apply new */
 462         v = readl(refo->ctrl_reg);
 463         v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
 464         v |= index << REFO_SEL_SHIFT;
 465
 466         writel(v, refo->ctrl_reg);
 467
 468         spin_unlock_irqrestore(&refo->core->reg_lock, flags);
 469
 470         return 0;
 471 }
 472
 473 static int roclk_set_rate_and_parent(struct clk_hw *hw,
 474                                      unsigned long rate,
 475                                      unsigned long parent_rate,
 476                                      u8 index)
 477 {
 478         struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
 479         unsigned long flags;
 480         u32 trim, rodiv, v;
 481         int err;
 482
 483         /* calculate new rodiv & rotrim for new rate */
 484         roclk_calc_div_trim(rate, parent_rate, &rodiv, &trim);
 485
 486         pr_debug("parent_rate = %lu, rate = %lu, div = %d, trim = %d\n",
 487                  parent_rate, rate, rodiv, trim);
 488
 489         /* wait till source change is active */
 490         err = readl_poll_timeout(refo->ctrl_reg, v,
 491                                  !(v & (REFO_ACTIVE | REFO_DIVSW_EN)),
 492                                  1, LOCK_TIMEOUT_US);
 493         if (err) {
 494                 pr_err("%s: poll timedout, clock is still active\n", __func__);
 495                 return err;
 496         }
 497
 498         spin_lock_irqsave(&refo->core->reg_lock, flags);
 499         v = readl(refo->ctrl_reg);
 500
 501         pic32_syskey_unlock();
 502
 503         /* apply parent, if required */
 504         if (refo->parent_map)
 505                 index = refo->parent_map[index];
 506
 507         v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
 508         v |= index << REFO_SEL_SHIFT;
 509
 510         /* apply RODIV */
 511         v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT);
 512         v |= rodiv << REFO_DIV_SHIFT;
 513         writel(v, refo->ctrl_reg);
 514
 515         /* apply ROTRIM */
 516         v = readl(refo->ctrl_reg + REFO_TRIM_REG);
 517         v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT);
 518         v |= trim << REFO_TRIM_SHIFT;
 519         writel(v, refo->ctrl_reg + REFO_TRIM_REG);
 520
 521         /* enable & activate divider switching */
 522         writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg));
 523
 524         /* wait till divswen is in-progress */
 525         err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN),
 526                                         1, LOCK_TIMEOUT_US);
 527         /* leave the clk gated as it was */
 528         writel(REFO_ON, PIC32_CLR(refo->ctrl_reg));
 529
 530         spin_unlock_irqrestore(&refo->core->reg_lock, flags);
 531
 532         return err;
 533 }
 534
 535 static int roclk_set_rate(struct clk_hw *hw, unsigned long rate,
 536                           unsigned long parent_rate)
 537 {
 538         u8 index = roclk_get_parent(hw);
 539
 540         return roclk_set_rate_and_parent(hw, rate, parent_rate, index);
 541 }
 542
 543 const struct clk_ops pic32_roclk_ops = {
 544         .enable                 = roclk_enable,
 545         .disable                = roclk_disable,
 546         .is_enabled             = roclk_is_enabled,
 547         .get_parent             = roclk_get_parent,
 548         .set_parent             = roclk_set_parent,
 549         .determine_rate         = roclk_determine_rate,
 550         .recalc_rate            = roclk_recalc_rate,
 551         .set_rate_and_parent    = roclk_set_rate_and_parent,
 552         .set_rate               = roclk_set_rate,
 553         .init                   = roclk_init,
 554 };
 555
 556 struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data,
 557                                     struct pic32_clk_common *core)
 558 {
 559         struct pic32_ref_osc *refo;
 560         struct clk *clk;
 561
 562         refo = devm_kzalloc(core->dev, sizeof(*refo), GFP_KERNEL);
 563         if (!refo)
 564                 return ERR_PTR(-ENOMEM);
 565
 566         refo->core = core;
 567         refo->hw.init = &data->init_data;
 568         refo->ctrl_reg = data->ctrl_reg + core->iobase;
 569         refo->parent_map = data->parent_map;
 570
 571         clk = devm_clk_register(core->dev, &refo->hw);
 572         if (IS_ERR(clk))
 573                 dev_err(core->dev, "%s: clk_register() failed\n", __func__);
 574
 575         return clk;
 576 }
 577
 578 struct pic32_sys_pll {
 579         struct clk_hw hw;
 580         void __iomem *ctrl_reg;
 581         void __iomem *status_reg;
 582         u32 lock_mask;
 583         u32 idiv; /* PLL iclk divider, treated fixed */
 584         struct pic32_clk_common *core;
 585 };
 586
 587 #define clkhw_to_spll(_hw)      container_of(_hw, struct pic32_sys_pll, hw)
 588
 589 static inline u32 spll_odiv_to_divider(u32 odiv)
 590 {
 591         odiv = clamp_val(odiv, PLL_ODIV_MIN, PLL_ODIV_MAX);
 592
 593         return 1 << odiv;
 594 }
 595
 596 static unsigned long spll_calc_mult_div(struct pic32_sys_pll *pll,
 597                                         unsigned long rate,
 598                                         unsigned long parent_rate,
 599                                         u32 *mult_p, u32 *odiv_p)
 600 {
 601         u32 mul, div, best_mul = 1, best_div = 1;
 602         unsigned long new_rate, best_rate = rate;
 603         unsigned int best_delta = -1, delta, match_found = 0;
 604         u64 rate64;
 605
 606         parent_rate /= pll->idiv;
 607
 608         for (mul = 1; mul <= PLL_MULT_MAX; mul++) {
 609                 for (div = PLL_ODIV_MIN; div <= PLL_ODIV_MAX; div++) {
 610                         rate64 = parent_rate;
 611                         rate64 *= mul;
 612                         do_div(rate64, 1 << div);
 613                         new_rate = rate64;
 614                         delta = abs(rate - new_rate);
 615                         if ((new_rate >= rate) && (delta < best_delta)) {
 616                                 best_delta = delta;
 617                                 best_rate = new_rate;
 618                                 best_mul = mul;
 619                                 best_div = div;
 620                                 match_found = 1;
 621                         }
 622                 }
 623         }
 624
 625         if (!match_found) {
 626                 pr_warn("spll: no match found\n");
 627                 return 0;
 628         }
 629
 630         pr_debug("rate %lu, par_rate %lu/mult %u, div %u, best_rate %lu\n",
 631                  rate, parent_rate, best_mul, best_div, best_rate);
 632
 633         if (mult_p)
 634                 *mult_p = best_mul - 1;
 635
 636         if (odiv_p)
 637                 *odiv_p = best_div;
 638
 639         return best_rate;
 640 }
 641
 642 static unsigned long spll_clk_recalc_rate(struct clk_hw *hw,
 643                                           unsigned long parent_rate)
 644 {
 645         struct pic32_sys_pll *pll = clkhw_to_spll(hw);
 646         unsigned long pll_in_rate;
 647         u32 mult, odiv, div, v;
 648         u64 rate64;
 649
 650         v = readl(pll->ctrl_reg);
 651         odiv = ((v >> PLL_ODIV_SHIFT) & PLL_ODIV_MASK);
 652         mult = ((v >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
 653         div = spll_odiv_to_divider(odiv);
 654
 655         /* pll_in_rate = parent_rate / idiv
 656          * pll_out_rate = pll_in_rate * mult / div;
 657          */
 658         pll_in_rate = parent_rate / pll->idiv;
 659         rate64 = pll_in_rate;
 660         rate64 *= mult;
 661         do_div(rate64, div);
 662
 663         return rate64;
 664 }
 665
 666 static long spll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 667                                 unsigned long *parent_rate)
 668 {
 669         struct pic32_sys_pll *pll = clkhw_to_spll(hw);
 670
 671         return spll_calc_mult_div(pll, rate, *parent_rate, NULL, NULL);
 672 }
 673
 674 static int spll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 675                              unsigned long parent_rate)
 676 {
 677         struct pic32_sys_pll *pll = clkhw_to_spll(hw);
 678         unsigned long ret, flags;
 679         u32 mult, odiv, v;
 680         int err;
 681
 682         ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv);
 683         if (!ret)
 684                 return -EINVAL;
 685
 686         /*
 687          * We can't change SPLL counters when it is in-active use
 688          * by SYSCLK. So check before applying new counters/rate.
 689          */
 690
 691         /* Is spll_clk active parent of sys_clk ? */
 692         if (unlikely(clk_hw_get_parent(pic32_sclk_hw) == hw)) {
 693                 pr_err("%s: failed, clk in-use\n", __func__);
 694                 return -EBUSY;
 695         }
 696
 697         spin_lock_irqsave(&pll->core->reg_lock, flags);
 698
 699         /* apply new multiplier & divisor */
 700         v = readl(pll->ctrl_reg);
 701         v &= ~(PLL_MULT_MASK << PLL_MULT_SHIFT);
 702         v &= ~(PLL_ODIV_MASK << PLL_ODIV_SHIFT);
 703         v |= (mult << PLL_MULT_SHIFT) | (odiv << PLL_ODIV_SHIFT);
 704
 705         /* sys unlock before write */
 706         pic32_syskey_unlock();
 707
 708         writel(v, pll->ctrl_reg);
 709         cpu_relax();
 710
 711         /* insert few nops (5-stage) to ensure CPU does not hang */
 712         cpu_nop5();
 713         cpu_nop5();
 714
 715         /* Wait until PLL is locked (maximum 100 usecs). */
 716         err = readl_poll_timeout_atomic(pll->status_reg, v,
 717                                         v & pll->lock_mask, 1, 100);
 718         spin_unlock_irqrestore(&pll->core->reg_lock, flags);
 719
 720         return err;
 721 }
 722
 723 /* SPLL clock operation */
 724 const struct clk_ops pic32_spll_ops = {
 725         .recalc_rate    = spll_clk_recalc_rate,
 726         .round_rate     = spll_clk_round_rate,
 727         .set_rate       = spll_clk_set_rate,
 728 };
 729
 730 struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data,
 731                                     struct pic32_clk_common *core)
 732 {
 733         struct pic32_sys_pll *spll;
 734         struct clk *clk;
 735
 736         spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL);
 737         if (!spll)
 738                 return ERR_PTR(-ENOMEM);
 739
 740         spll->core = core;
 741         spll->hw.init = &data->init_data;
 742         spll->ctrl_reg = data->ctrl_reg + core->iobase;
 743         spll->status_reg = data->status_reg + core->iobase;
 744         spll->lock_mask = data->lock_mask;
 745
 746         /* cache PLL idiv; PLL driver uses it as constant.*/
 747         spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK;
 748         spll->idiv += 1;
 749
 750         clk = devm_clk_register(core->dev, &spll->hw);
 751         if (IS_ERR(clk))
 752                 dev_err(core->dev, "sys_pll: clk_register() failed\n");
 753
 754         return clk;
 755 }
 756
 757 /* System mux clock(aka SCLK) */
 758
 759 struct pic32_sys_clk {
 760         struct clk_hw hw;
 761         void __iomem *mux_reg;
 762         void __iomem *slew_reg;
 763         u32 slew_div;
 764         const u32 *parent_map;
 765         struct pic32_clk_common *core;
 766 };
 767
 768 #define clkhw_to_sys_clk(_hw)   container_of(_hw, struct pic32_sys_clk, hw)
 769
 770 static unsigned long sclk_get_rate(struct clk_hw *hw, unsigned long parent_rate)
 771 {
 772         struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
 773         u32 div;
 774
 775         div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV;
 776         div += 1; /* sys-div to divider */
 777
 778         return parent_rate / div;
 779 }
 780
 781 static long sclk_round_rate(struct clk_hw *hw, unsigned long rate,
 782                             unsigned long *parent_rate)
 783 {
 784         return calc_best_divided_rate(rate, *parent_rate, SLEW_SYSDIV, 1);
 785 }
 786
 787 static int sclk_set_rate(struct clk_hw *hw,
 788                          unsigned long rate, unsigned long parent_rate)
 789 {
 790         struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
 791         unsigned long flags;
 792         u32 v, div;
 793         int err;
 794
 795         div = parent_rate / rate;
 796
 797         spin_lock_irqsave(&sclk->core->reg_lock, flags);
 798
 799         /* apply new div */
 800         v = readl(sclk->slew_reg);
 801         v &= ~(SLEW_SYSDIV << SLEW_SYSDIV_SHIFT);
 802         v |= (div - 1) << SLEW_SYSDIV_SHIFT;
 803
 804         pic32_syskey_unlock();
 805
 806         writel(v, sclk->slew_reg);
 807
 808         /* wait until BUSY is cleared */
 809         err = readl_poll_timeout_atomic(sclk->slew_reg, v,
 810                                         !(v & SLEW_BUSY), 1, LOCK_TIMEOUT_US);
 811
 812         spin_unlock_irqrestore(&sclk->core->reg_lock, flags);
 813
 814         return err;
 815 }
 816
 817 static u8 sclk_get_parent(struct clk_hw *hw)
 818 {
 819         struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
 820         u32 i, v;
 821
 822         v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK;
 823
 824         if (!sclk->parent_map)
 825                 return v;
 826
 827         for (i = 0; i < clk_hw_get_num_parents(hw); i++)
 828                 if (sclk->parent_map[i] == v)
 829                         return i;
 830         return -EINVAL;
 831 }
 832
 833 static int sclk_set_parent(struct clk_hw *hw, u8 index)
 834 {
 835         struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
 836         unsigned long flags;
 837         u32 nosc, cosc, v;
 838         int err;
 839
 840         spin_lock_irqsave(&sclk->core->reg_lock, flags);
 841
 842         /* find new_osc */
 843         nosc = sclk->parent_map ? sclk->parent_map[index] : index;
 844
 845         /* set new parent */
 846         v = readl(sclk->mux_reg);
 847         v &= ~(OSC_NEW_MASK << OSC_NEW_SHIFT);
 848         v |= nosc << OSC_NEW_SHIFT;
 849
 850         pic32_syskey_unlock();
 851
 852         writel(v, sclk->mux_reg);
 853
 854         /* initate switch */
 855         writel(OSC_SWEN, PIC32_SET(sclk->mux_reg));
 856         cpu_relax();
 857
 858         /* add nop to flush pipeline (as cpu_clk is in-flux) */
 859         cpu_nop5();
 860
 861         /* wait for SWEN bit to clear */
 862         err = readl_poll_timeout_atomic(sclk->slew_reg, v,
 863                                         !(v & OSC_SWEN), 1, LOCK_TIMEOUT_US);
 864
 865         spin_unlock_irqrestore(&sclk->core->reg_lock, flags);
 866
 867         /*
 868          * SCLK clock-switching logic might reject a clock switching request
 869          * if pre-requisites (like new clk_src not present or unstable) are
 870          * not met.
 871          * So confirm before claiming success.
 872          */
 873         cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK;
 874         if (cosc != nosc) {
 875                 pr_err("%s: err, failed to set_parent() to %d, current %d\n",
 876                        clk_hw_get_name(hw), nosc, cosc);
 877                 err = -EBUSY;
 878         }
 879
 880         return err;
 881 }
 882
 883 static void sclk_init(struct clk_hw *hw)
 884 {
 885         struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
 886         unsigned long flags;
 887         u32 v;
 888
 889         /* Maintain reference to this clk, required in spll_clk_set_rate() */
 890         pic32_sclk_hw = hw;
 891
 892         /* apply slew divider on both up and down scaling */
 893         if (sclk->slew_div) {
 894                 spin_lock_irqsave(&sclk->core->reg_lock, flags);
 895                 v = readl(sclk->slew_reg);
 896                 v &= ~(SLEW_DIV << SLEW_DIV_SHIFT);
 897                 v |= sclk->slew_div << SLEW_DIV_SHIFT;
 898                 v |= SLEW_DOWNEN | SLEW_UPEN;
 899                 writel(v, sclk->slew_reg);
 900                 spin_unlock_irqrestore(&sclk->core->reg_lock, flags);
 901         }
 902 }
 903
 904 /* sclk with post-divider */
 905 const struct clk_ops pic32_sclk_ops = {
 906         .get_parent     = sclk_get_parent,
 907         .set_parent     = sclk_set_parent,
 908         .round_rate     = sclk_round_rate,
 909         .set_rate       = sclk_set_rate,
 910         .recalc_rate    = sclk_get_rate,
 911         .init           = sclk_init,
 912         .determine_rate = __clk_mux_determine_rate,
 913 };
 914
 915 /* sclk with no slew and no post-divider */
 916 const struct clk_ops pic32_sclk_no_div_ops = {
 917         .get_parent     = sclk_get_parent,
 918         .set_parent     = sclk_set_parent,
 919         .init           = sclk_init,
 920         .determine_rate = __clk_mux_determine_rate,
 921 };
 922
 923 struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data,
 924                                    struct pic32_clk_common *core)
 925 {
 926         struct pic32_sys_clk *sclk;
 927         struct clk *clk;
 928
 929         sclk = devm_kzalloc(core->dev, sizeof(*sclk), GFP_KERNEL);
 930         if (!sclk)
 931                 return ERR_PTR(-ENOMEM);
 932
 933         sclk->core = core;
 934         sclk->hw.init = &data->init_data;
 935         sclk->mux_reg = data->mux_reg + core->iobase;
 936         sclk->slew_reg = data->slew_reg + core->iobase;
 937         sclk->slew_div = data->slew_div;
 938         sclk->parent_map = data->parent_map;
 939
 940         clk = devm_clk_register(core->dev, &sclk->hw);
 941         if (IS_ERR(clk))
 942                 dev_err(core->dev, "%s: clk register failed\n", __func__);
 943
 944         return clk;
 945 }
 946
 947 /* secondary oscillator */
 948 struct pic32_sec_osc {
 949         struct clk_hw hw;
 950         void __iomem *enable_reg;
 951         void __iomem *status_reg;
 952         u32 enable_mask;
 953         u32 status_mask;
 954         unsigned long fixed_rate;
 955         struct pic32_clk_common *core;
 956 };
 957
 958 #define clkhw_to_sosc(_hw)      container_of(_hw, struct pic32_sec_osc, hw)
 959 static int sosc_clk_enable(struct clk_hw *hw)
 960 {
 961         struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);
 962         u32 v;
 963
 964         /* enable SOSC */
 965         pic32_syskey_unlock();
 966         writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg));
 967
 968         /* wait till warm-up period expires or ready-status is updated */
 969         return readl_poll_timeout_atomic(sosc->status_reg, v,
 970                                          v & sosc->status_mask, 1, 100);
 971 }
 972
 973 static void sosc_clk_disable(struct clk_hw *hw)
 974 {
 975         struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);
 976
 977         pic32_syskey_unlock();
 978         writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg));
 979 }
 980
 981 static int sosc_clk_is_enabled(struct clk_hw *hw)
 982 {
 983         struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);
 984         u32 enabled, ready;
 985
 986         /* check enabled and ready status */
 987         enabled = readl(sosc->enable_reg) & sosc->enable_mask;
 988         ready = readl(sosc->status_reg) & sosc->status_mask;
 989
 990         return enabled && ready;
 991 }
 992
 993 static unsigned long sosc_clk_calc_rate(struct clk_hw *hw,
 994                                         unsigned long parent_rate)
 995 {
 996         return clkhw_to_sosc(hw)->fixed_rate;
 997 }
 998
 999 const struct clk_ops pic32_sosc_ops = {
1000         .enable = sosc_clk_enable,
1001         .disable = sosc_clk_disable,
1002         .is_enabled = sosc_clk_is_enabled,
1003         .recalc_rate = sosc_clk_calc_rate,
1004 };
1005
1006 struct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data,
1007                                     struct pic32_clk_common *core)
1008 {
1009         struct pic32_sec_osc *sosc;
1010
1011         sosc = devm_kzalloc(core->dev, sizeof(*sosc), GFP_KERNEL);
1012         if (!sosc)
1013                 return ERR_PTR(-ENOMEM);
1014
1015         sosc->core = core;
1016         sosc->hw.init = &data->init_data;
1017         sosc->fixed_rate = data->fixed_rate;
1018         sosc->enable_mask = data->enable_mask;
1019         sosc->status_mask = data->status_mask;
1020         sosc->enable_reg = data->enable_reg + core->iobase;
1021         sosc->status_reg = data->status_reg + core->iobase;
1022
1023         return devm_clk_register(core->dev, &sosc->hw);
1024 }